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Merge branch 'bugfix/fix_rmt_driver_breaking_change_issue' into 'master'
Bugfix(RMT): Fix the breaking change issue of RMT driver. Closes IDFGH-2837, IDFGH-2579, and IDFGH-2915 See merge request espressif/esp-idf!8006
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@@ -21,6 +21,9 @@ extern "C" {
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#include "soc/rmt_struct.h"
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#include "soc/rmt_caps.h"
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#define RMT_LL_HW_BASE (&RMT)
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#define RMT_LL_MEM_BASE (&RMTMEM)
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static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
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{
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dev->conf_ch[0].conf0.clk_en = enable;
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@@ -276,9 +279,10 @@ static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel,
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dev->conf_ch[channel].conf0.carrier_out_lv = level;
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}
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//Writes items to the specified TX channel memory with the given offset and writen length.
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//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS)
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static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
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{
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length = (off + length) > SOC_RMT_CHANNEL_MEM_WORDS ? (SOC_RMT_CHANNEL_MEM_WORDS - off) : length;
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for (uint32_t i = 0; i < length; i++) {
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mem->chan[channel].data32[i + off].val = data[i].val;
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}
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@@ -21,6 +21,9 @@ extern "C" {
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#include "soc/rmt_struct.h"
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#include "soc/rmt_caps.h"
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#define RMT_LL_HW_BASE (&RMT)
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#define RMT_LL_MEM_BASE (&RMTMEM)
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static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
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{
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dev->apb_conf.clk_en = enable; // register clock gating
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@@ -367,9 +370,10 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan
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dev->conf_ch[channel].conf0.carrier_eff_en = !enable;
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}
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//Writes items to the specified TX channel memory with the given offset and writen length.
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//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS)
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static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
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{
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length = (off + length) > SOC_RMT_CHANNEL_MEM_WORDS ? (SOC_RMT_CHANNEL_MEM_WORDS - off) : length;
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for (uint32_t i = 0; i < length; i++) {
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mem->chan[channel].data32[i + off].val = data[i].val;
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}
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@@ -20,11 +20,6 @@ void rmt_hal_init(rmt_hal_context_t *hal)
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hal->mem = &RMTMEM;
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}
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void rmt_hal_reset(rmt_hal_context_t *hal)
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{
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}
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void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel)
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{
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rmt_ll_reset_tx_pointer(hal->regs, channel);
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@@ -103,4 +98,4 @@ void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32
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rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
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rmt_ll_write_memory(hal->mem, channel, src, length, offset);
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rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
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}
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}
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