From f709faea7c7be7d4abaa7f9204c8e3ba26959193 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Wed, 27 Apr 2022 14:56:55 +0530 Subject: [PATCH] ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V RTC_CNTL_COCPU_SHUT_RESET_EN register was being reset during ULP RISC-V initialization which does not let the ULP RISC-V coprocessor to reset after it goes to halt. For proper operation of the coprocessor, it must be reset after each cycle and hence this commit keeps RTC_CNTL_COCPU_SHUT_RESET_EN set. --- components/ulp/ulp_riscv/ulp_riscv.c | 14 +++++++------- components/ulp/ulp_riscv/ulp_riscv_utils.c | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/components/ulp/ulp_riscv/ulp_riscv.c b/components/ulp/ulp_riscv/ulp_riscv.c index 64e6999fe0..aa828c40a4 100644 --- a/components/ulp/ulp_riscv/ulp_riscv.c +++ b/components/ulp/ulp_riscv/ulp_riscv.c @@ -55,12 +55,10 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) #endif //CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_IDF_TARGET_ESP32S2 - /* Reset COCPU when power on. */ + /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - esp_rom_delay_us(20); - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - /* The coprocessor cpu trap signal doesnt have a stable reset value, + /* The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); @@ -77,12 +75,14 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source); #elif CONFIG_IDF_TARGET_ESP32S3 - /* Reset COCPU when power on. */ + /* The coprocessor cpu trap signal doesnt have a stable reset value, + force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); - SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); esp_rom_delay_us(20); CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); + + /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */ + SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); /* Disable ULP timer */ CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); diff --git a/components/ulp/ulp_riscv/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_riscv_utils.c index 75e48982c0..c14d08aeac 100644 --- a/components/ulp/ulp_riscv/ulp_riscv_utils.c +++ b/components/ulp/ulp_riscv/ulp_riscv_utils.c @@ -13,7 +13,7 @@ void ulp_riscv_rescue_from_monitor(void) { /* Rescue RISCV from monitor state. */ - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE); } void ulp_riscv_wakeup_main_processor(void)