esp_hw_support: create esp_cpu

Create a esp_cpu header that contains CPU-related functions and
utilities.

components/esp_hw_support/CMakeLists.txt

@@ -13,7 +13,7 @@ endif()
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS include
                        REQUIRES ${requires}
-                       PRIV_REQUIRES efuse esp_system
+                       PRIV_REQUIRES efuse
                        LDFRAGMENTS linker.lf)
 
 idf_build_get_property(target IDF_TARGET)

components/esp_hw_support/cpu_util.c

@@ -19,10 +19,11 @@
 #include "sdkconfig.h"
 
 #include "hal/cpu_hal.h"
-#include "esp_debug_helpers.h"
 #include "hal/cpu_types.h"
 #include "hal/mpu_hal.h"
 
+#include "esp_cpu.h"
+
 #include "hal/soc_hal.h"
 #include "soc/soc_caps.h"
 
@@ -47,7 +48,7 @@ void IRAM_ATTR esp_cpu_reset(int cpu_id)
     soc_hal_reset_core(cpu_id);
 }
 
-esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
+esp_err_t IRAM_ATTR esp_cpu_set_watchpoint(int no, void *adr, int size, int flags)
 {
     watchpoint_trigger_t trigger;
 
@@ -70,7 +71,7 @@ esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
     return ESP_OK;
 }
 
-void IRAM_ATTR esp_clear_watchpoint(int no)
+void IRAM_ATTR esp_cpu_clear_watchpoint(int no)
 {
     cpu_hal_clear_watchpoint(no);
 }
@@ -87,13 +88,6 @@ bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
 #endif
 }
 
-void IRAM_ATTR esp_set_breakpoint_if_jtag(void *fn)
-{
-    if (esp_cpu_in_ocd_debug_mode()) {
-        cpu_hal_set_breakpoint(0, fn);
-    }
-}
-
 #if __XTENSA__
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/include/esp_cpu.h

@@ -0,0 +1,109 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESP_CPU_H
+#define _ESP_CPU_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#include "hal/cpu_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP_WATCHPOINT_LOAD 0x40000000
+#define ESP_WATCHPOINT_STORE 0x80000000
+#define ESP_WATCHPOINT_ACCESS 0xC0000000
+
+typedef uint32_t esp_cpu_ccount_t;
+
+/** @brief Read current stack pointer address
+ *
+ */
+static inline void *esp_cpu_get_sp(void)
+{
+    return cpu_hal_get_sp();
+}
+
+/**
+ * @brief Stall CPU using RTC controller
+ * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
+ */
+void esp_cpu_stall(int cpu_id);
+
+/**
+ * @brief Un-stall CPU using RTC controller
+ * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
+ */
+void esp_cpu_unstall(int cpu_id);
+
+/**
+ * @brief Reset CPU using RTC controller
+ * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
+ */
+void esp_cpu_reset(int cpu_id);
+
+/**
+ * @brief Returns true if a JTAG debugger is attached to CPU
+ * OCD (on chip debug) port.
+ *
+ * @note If "Make exception and panic handlers JTAG/OCD aware"
+ * is disabled, this function always returns false.
+ */
+bool esp_cpu_in_ocd_debug_mode(void);
+
+static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
+{
+    return cpu_hal_get_cycle_count();
+}
+
+static inline void esp_cpu_set_ccount(esp_cpu_ccount_t val)
+{
+    cpu_hal_set_cycle_count(val);
+}
+
+/**
+ * @brief Set a watchpoint to break/panic when a certain memory range is accessed.
+ *
+ * @param no Watchpoint number. On the ESP32, this can be 0 or 1.
+ * @param adr Base address to watch
+ * @param size Size of the region, starting at the base address, to watch. Must
+ *             be one of 2^n, with n in [0..6].
+ * @param flags One of ESP_WATCHPOINT_* flags
+ *
+ * @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
+ *
+ * @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
+ *          masking away the lower n bits for a region with size 2^n. If adr does
+ *          not have zero for these lower n bits, you may not be watching the
+ *          region you intended.
+ */
+esp_err_t esp_cpu_set_watchpoint(int no, void *adr, int size, int flags);
+
+/**
+ * @brief Clear a watchpoint
+ *
+ * @param no Watchpoint to clear
+ *
+ */
+void esp_cpu_clear_watchpoint(int no);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _ESP_CPU_H

components/esp_hw_support/include/soc/cpu.h

@@ -19,6 +19,8 @@
 #include <stdbool.h>
 #include <stddef.h>
 
+#include "esp_cpu.h"
+
 #if __XTENSA__
 #include "xt_instr_macros.h"
 // [refactor-todo] not actually needed in this header now,
@@ -29,59 +31,18 @@
 #include "xtensa/config/specreg.h"
 #endif
 
-#include "hal/cpu_hal.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/** @brief Read current stack pointer address
- *
+/** @brief Read current stack pointer address.
+ * Superseded by esp_cpu_get_sp in esp_cpu.h.
  */
-static inline void *get_sp(void)
+static inline __attribute__((deprecated)) void *get_sp(void)
 {
-    return cpu_hal_get_sp();
+    return esp_cpu_get_sp();
 }
 
-/**
- * @brief Stall CPU using RTC controller
- * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
- */
-void esp_cpu_stall(int cpu_id);
-
-/**
- * @brief Un-stall CPU using RTC controller
- * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
- */
-void esp_cpu_unstall(int cpu_id);
-
-/**
- * @brief Reset CPU using RTC controller
- * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
- */
-void esp_cpu_reset(int cpu_id);
-
-
-/**
- * @brief Returns true if a JTAG debugger is attached to CPU
- * OCD (on chip debug) port.
- *
- * @note If "Make exception and panic handlers JTAG/OCD aware"
- * is disabled, this function always returns false.
- */
-bool esp_cpu_in_ocd_debug_mode(void);
-
-/**
- * @brief Convert the PC register value to its true address
- *
- * The address of the current instruction is not stored as an exact uint32_t
- * representation in PC register. This function will convert the value stored in
- * the PC register to a uint32_t address.
- *
- * @param pc_raw The PC as stored in register format.
- *
- * @return Address in uint32_t format
- */
 static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
 {
     if (pc & 0x80000000) {
@@ -92,18 +53,6 @@ static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
     return pc - 3;
 }
 
-typedef uint32_t esp_cpu_ccount_t;
-
-static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
-{
-    return cpu_hal_get_cycle_count();
-}
-
-static inline void esp_cpu_set_ccount(esp_cpu_ccount_t val)
-{
-    cpu_hal_set_cycle_count(val);
-}
-
 /**
  * @brief Configure CPU to disable access to invalid memory regions
  *