From 0f5d1c1c46c1710cbfeabbed1233153464f463cb Mon Sep 17 00:00:00 2001
From: morris <maoshengrong@espressif.com>
Date: Wed, 27 Jan 2021 12:07:05 +0800
Subject: [PATCH] rtc: supported disable rom log temporarily

---
 components/esp_rom/include/esp32/rom/rtc.h    | 18 +++++++++++++++++
 components/esp_rom/include/esp32c3/rom/rtc.h  | 20 +++++++++++++++++++
 components/esp_rom/include/esp32s2/rom/rtc.h  | 20 +++++++++++++++++++
 components/esp_rom/include/esp32s3/rom/rtc.h  | 19 ++++++++++++++++++
 components/esp_rom/include/esp_rom_sys.h      |  7 +------
 components/esp_system/sleep_modes.c           |  2 +-
 .../ulp_adc/main/ulp_adc_example_main.c       |  2 --
 7 files changed, 79 insertions(+), 9 deletions(-)

diff --git a/components/esp_rom/include/esp32/rom/rtc.h b/components/esp_rom/include/esp32/rom/rtc.h
index fa00b71bb9..79ad9b0acc 100644
--- a/components/esp_rom/include/esp32/rom/rtc.h
+++ b/components/esp_rom/include/esp32/rom/rtc.h
@@ -184,6 +184,24 @@ uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
   */
 void set_rtc_memory_crc(void);
 
+/**
+  * @brief Suppress ROM log by setting specific RTC control register.
+  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+static inline void rtc_suppress_rom_log(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
+
 /**
   * @brief Software Reset digital core.
   *
diff --git a/components/esp_rom/include/esp32c3/rom/rtc.h b/components/esp_rom/include/esp32c3/rom/rtc.h
index ef0c5daaba..fcbfddc1c0 100644
--- a/components/esp_rom/include/esp32c3/rom/rtc.h
+++ b/components/esp_rom/include/esp32c3/rom/rtc.h
@@ -71,6 +71,8 @@ extern "C" {
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
 
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
+
 
 typedef enum {
     AWAKE = 0,             //<CPU ON
@@ -164,6 +166,24 @@ WAKEUP_REASON rtc_get_wakeup_cause(void);
   */
 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
 
+/**
+  * @brief Suppress ROM log by setting specific RTC control register.
+  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+static inline void rtc_suppress_rom_log(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
+
 /**
   * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
   *
diff --git a/components/esp_rom/include/esp32s2/rom/rtc.h b/components/esp_rom/include/esp32s2/rom/rtc.h
index 535dc64a9a..509b6fd459 100644
--- a/components/esp_rom/include/esp32s2/rom/rtc.h
+++ b/components/esp_rom/include/esp32s2/rom/rtc.h
@@ -71,6 +71,8 @@ extern "C" {
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
 
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
+
 typedef enum {
     AWAKE = 0,             //<CPU ON
     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
@@ -172,6 +174,24 @@ uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
   */
 void set_rtc_memory_crc(void);
 
+/**
+  * @brief Suppress ROM log by setting specific RTC control register.
+  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+static inline void rtc_suppress_rom_log(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
+
 /**
   * @brief Fetch entry from RTC memory and RTC STORE reg
   *
diff --git a/components/esp_rom/include/esp32s3/rom/rtc.h b/components/esp_rom/include/esp32s3/rom/rtc.h
index a5a1ecb6a1..b8ff8519bf 100644
--- a/components/esp_rom/include/esp32s3/rom/rtc.h
+++ b/components/esp_rom/include/esp32s3/rom/rtc.h
@@ -65,6 +65,7 @@ extern "C" {
 #define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
 
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 
 typedef enum {
     AWAKE = 0,             //<CPU ON
@@ -159,6 +160,24 @@ WAKEUP_REASON rtc_get_wakeup_cause(void);
   */
 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
 
+/**
+  * @brief Suppress ROM log by setting specific RTC control register.
+  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+static inline void rtc_suppress_rom_log(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
+
 /**
   * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
   *
diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h
index 130c307014..a5b01aded1 100644
--- a/components/esp_rom/include/esp_rom_sys.h
+++ b/components/esp_rom/include/esp_rom_sys.h
@@ -47,13 +47,8 @@ void esp_rom_delay_us(uint32_t us);
 void esp_rom_install_channel_putc(int channel, void (*putc)(char c));
 
 /**
- *  @brief Disable logging from the ROM code.
+ * @brief Install UART1 as the default console channel, equivalent to `esp_rom_install_channel_putc(1, esp_rom_uart_putc)`
  */
-void esp_rom_disable_logging(void);
-
-/**
-  * @brief Install UART1 as the default console channel, equivalent to `esp_rom_install_channel_putc(1, esp_rom_uart_putc)`
-  */
 void esp_rom_install_uart_printf(void);
 
 #ifdef __cplusplus
diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c
index cbcd82b0ad..4a7476e9eb 100644
--- a/components/esp_system/sleep_modes.c
+++ b/components/esp_system/sleep_modes.c
@@ -1245,5 +1245,5 @@ static uint32_t get_power_down_flags(void)
 
 void esp_deep_sleep_disable_rom_logging(void)
 {
-    esp_rom_disable_logging();
+    rtc_suppress_rom_log();
 }
diff --git a/examples/system/ulp_adc/main/ulp_adc_example_main.c b/examples/system/ulp_adc/main/ulp_adc_example_main.c
index 9e38e9ff76..6eb7a9bb10 100644
--- a/examples/system/ulp_adc/main/ulp_adc_example_main.c
+++ b/examples/system/ulp_adc/main/ulp_adc_example_main.c
@@ -84,9 +84,7 @@ static void init_ulp_program(void)
      */
     rtc_gpio_isolate(GPIO_NUM_12);
     rtc_gpio_isolate(GPIO_NUM_15);
-#if CONFIG_IDF_TARGET_ESP32
     esp_deep_sleep_disable_rom_logging(); // suppress boot messages
-#endif
 }
 
 static void start_ulp_program(void)