espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-13 17:44:38 +02:00
Code Issues Packages Projects Releases Wiki Activity

test: formate test_spi_slave.c

Browse Source
This commit is contained in:
wanlei
2023-01-04 11:26:55 +08:00
parent 45c1dc424f
commit 120d54d700
2 changed files with 155 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
components/driver/include/esp_private/spi_slave_internal.h
View File

@@ -24,6 +24,7 @@ extern "C" {
/**
* @brief Reset the trans Queue of slave driver
* @note
* This API is used to reset SPI Slave transaction queue. After calling this function:
* - The SPI Slave transaction queue will be reset.
@@ -41,6 +42,7 @@ esp_err_t spi_slave_queue_reset(spi_host_device_t host);
/**
* @brief Reset the trans Queue from within ISR of slave driver
* @note
* This API is used to reset SPI Slave transaction queue from within ISR. After calling this function:
* - The SPI Slave transaction queue will be empty.
@@ -56,9 +58,9 @@ esp_err_t spi_slave_queue_reset_isr(spi_host_device_t host);
/**
* @brief Queue a SPI transaction in ISR
*
* @note
* Similar as ``spi_slave_queue_trans``, but can and can only called within an ISR, then get the transaction results
* through the transaction discriptor passed in ``spi_slave_interface_config_t::post_trans_cb``. if use this API, you
* through the transaction descriptor passed in ``spi_slave_interface_config_t::post_trans_cb``. if use this API, you
* should trigger a transaction by normal ``spi_slave_queue_trans`` once and only once to start isr
*
* If you use both ``spi_slave_queue_trans`` and ``spi_slave_queue_trans_isr`` simultaneously to transfer valid data,

69
components/driver/test_apps/spi/slave/main/test_spi_slave.c
View File

@@ -92,7 +92,8 @@ static void slave_init(void)
TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
}
static void custom_setup(void) {
static void custom_setup(void)
{
//Initialize buffers
memset(master_txbuf, 0, sizeof(master_txbuf));
memset(master_rxbuf, 0, sizeof(master_rxbuf));
@@ -111,7 +112,8 @@ static void custom_setup(void) {
int_connect( PIN_NUM_CLK, spi_periph_signal[TEST_SPI_HOST].spiclk_out, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in );
}
static void custom_teardown(void) {
static void custom_teardown(void)
{
TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK);
TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK);
@@ -394,7 +396,8 @@ TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Unaligned_Test", "[spi_ms][timeout=120]",
#define TEST_TRANS_LEN 120
#define TEST_BUFFER_SZ (TEST_IRAM_TRANS_NUM*TEST_TRANS_LEN)
static void test_slave_iram_master_normal(void){
static void test_slave_iram_master_normal(void)
{
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
@@ -439,16 +442,22 @@ static void test_slave_iram_master_normal(void){
}
//------------------------------------test slave func-----------------------------------------
static IRAM_ATTR void ESP_LOG_BUFFER_HEX_ISR(const char *tag, const uint8_t *buff, const uint32_t byte_len){
static IRAM_ATTR void ESP_LOG_BUFFER_HEX_ISR(const char *tag, const uint8_t *buff, const uint32_t byte_len)
{
esp_rom_printf(DRAM_STR("%s: "), tag);
for (uint16_t i = 0; i < byte_len; i++) {
if(0 == i%16) esp_rom_printf(DRAM_STR("\n"));
esp_rom_printf(DRAM_STR("%2x "), buff[i]);
} esp_rom_printf(DRAM_STR("\n"));
if (0 == i % 16) {
esp_rom_printf(DRAM_STR("\n"));
}
esp_rom_printf(DRAM_STR("%02x "), buff[i]);
}
esp_rom_printf(DRAM_STR("\n"));
}
static uint32_t isr_iram_cnt, iram_test_fail;
static IRAM_ATTR void test_slave_iram_post_trans_cbk(spi_slave_transaction_t *curr_trans){
static uint32_t isr_iram_cnt;
static uint32_t iram_test_fail;
static IRAM_ATTR void test_slave_iram_post_trans_cbk(spi_slave_transaction_t *curr_trans)
{
isr_iram_cnt ++;
// first trans is the trigger trans with random data by master
@@ -460,10 +469,15 @@ static IRAM_ATTR void test_slave_iram_post_trans_cbk(spi_slave_transaction_t *cu
iram_test_fail = true;
}
}
if(isr_iram_cnt <= TEST_IRAM_TRANS_NUM) esp_rom_printf(DRAM_STR("Send signal: [Slave ready]!\n"));
if (isr_iram_cnt <= TEST_IRAM_TRANS_NUM) {
// str "Send signal: [Slave ready]!\n" used for CI to run test automatically
// here use `esp_rom_printf` instead `unity_send_signal` because cache is disabled by test
esp_rom_printf(DRAM_STR("Send signal: [Slave ready]!\n"));
}
}
static IRAM_ATTR void test_slave_isr_iram(void){
static IRAM_ATTR void test_slave_isr_iram(void)
{
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
slvcfg.flags = SPI_SLAVE_NO_RETURN_RESULT;
@@ -500,7 +514,9 @@ static IRAM_ATTR void test_slave_isr_iram(void){
esp_rom_delay_us(10);
}
spi_flash_enable_interrupts_caches_and_other_cpu();
if(iram_test_fail) TEST_FAIL();
if (iram_test_fail) {
TEST_FAIL();
}
free(slave_iram_send);
free(slave_iram_recv);
@@ -512,12 +528,14 @@ TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_ISR_IRAM_disable_cache", "[spi_ms]",
static uint32_t isr_trans_cnt, isr_trans_test_fail;
static IRAM_ATTR void test_trans_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans){
static IRAM_ATTR void test_trans_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans)
{
isr_trans_cnt ++;
//first trans is the trigger trans with random data
if (isr_trans_cnt > 1) {
ESP_LOG_BUFFER_HEX_ISR(DRAM_STR("slave tx"), curr_trans->tx_buffer, curr_trans->trans_len / 8);
if (memcmp(curr_trans->rx_buffer, curr_trans->user, curr_trans->trans_len / 8)) {
ESP_LOG_BUFFER_HEX_ISR(DRAM_STR("slave rx"), curr_trans->rx_buffer, curr_trans->trans_len / 8);
ESP_LOG_BUFFER_HEX_ISR(DRAM_STR("slave exp"), curr_trans->user, curr_trans->trans_len / 8);
@@ -531,13 +549,16 @@ static IRAM_ATTR void test_trans_in_isr_post_trans_cbk(spi_slave_transaction_t *
if (isr_trans_cnt <= TEST_IRAM_TRANS_NUM) {
if (ESP_OK == spi_slave_queue_trans_isr(TEST_SPI_HOST, curr_trans)) {
// use `esp_rom_printf` instead `unity_send_signal` because cache is disabled by test
esp_rom_printf(DRAM_STR("Send signal: [Slave ready]!\n"));
} else {
esp_rom_printf(DRAM_STR("SPI Add trans in isr fail, Queue full\n"));
}
else esp_rom_printf(DRAM_STR("SPI Add trans in isr fail, Queue full\n"));
}
}
static IRAM_ATTR void spi_slave_trans_in_isr(void){
static IRAM_ATTR void spi_slave_trans_in_isr(void)
{
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
slvcfg.flags = SPI_SLAVE_NO_RETURN_RESULT;
@@ -565,7 +586,9 @@ static IRAM_ATTR void spi_slave_trans_in_isr(void){
esp_rom_delay_us(10);
}
spi_flash_enable_interrupts_caches_and_other_cpu();
if(isr_trans_test_fail) TEST_FAIL();
if (isr_trans_test_fail) {
TEST_FAIL();
}
free(slave_isr_send);
free(slave_isr_recv);
@@ -578,7 +601,8 @@ TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_Queue_Trans_in_ISR", "[spi_ms]", tes
uint32_t dummy_data[2] = {0x38383838, 0x5b5b5b5b};
spi_slave_transaction_t dummy_trans[2];
static uint32_t queue_reset_isr_trans_cnt, test_queue_reset_isr_fail;
static IRAM_ATTR void test_queue_reset_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans){
static IRAM_ATTR void test_queue_reset_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans)
{
queue_reset_isr_trans_cnt ++;
//first trans is the trigger trans with random data
@@ -611,13 +635,16 @@ static IRAM_ATTR void test_queue_reset_in_isr_post_trans_cbk(spi_slave_transacti
if (queue_reset_isr_trans_cnt <= TEST_IRAM_TRANS_NUM) {
if (ESP_OK == spi_slave_queue_trans_isr(TEST_SPI_HOST, curr_trans)) {
// use `esp_rom_printf` instead `unity_send_signal` because cache is disabled by test
esp_rom_printf(DRAM_STR("Send signal: [Slave ready]!\n"));
} else {
esp_rom_printf(DRAM_STR("SPI Add trans in isr fail, Queue full\n"));
}
else esp_rom_printf(DRAM_STR("SPI Add trans in isr fail, Queue full\n"));
}
}
static IRAM_ATTR void spi_queue_reset_in_isr(void){
static IRAM_ATTR void spi_queue_reset_in_isr(void)
{
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
slvcfg.flags = SPI_SLAVE_NO_RETURN_RESULT;
@@ -651,7 +678,9 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void){
esp_rom_delay_us(10);
}
// spi_flash_enable_interrupts_caches_and_other_cpu();
if(test_queue_reset_isr_fail) TEST_FAIL();
if (test_queue_reset_isr_fail) {
TEST_FAIL();
}
free(slave_isr_send);
free(slave_isr_recv);