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Merge branch 'feat/psram_support_d2wd_single_clk_u4wdh' into 'master'

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spiram: Add support for U4WDH, and fixed D0WD/D2WD cannot share CLK pins

Closes IDF-4485

See merge request espressif/esp-idf!17665
This commit is contained in:
Michael (XIAO Xufeng)
2023-08-03 10:37:46 +08:00
parent 23585c9af4 15f31f69b6
commit 1317d9a5b5
2 changed files with 22 additions and 7 deletions
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21
components/esp_psram/esp32/esp_psram_impl_quad.c
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@@ -849,14 +849,16 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
abort();
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO");
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) {
ESP_EARLY_LOGI(TAG, "This chip is %s",
(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)? "ESP32-PICO": "ESP32-U4WDH");
// We have better alternatives, though it's possible to use U4WDH together with PSRAM.
// U4WDH shares the same pin config with PICO for historical reasons.
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = PICO_PSRAM_CLK_IO;
psram_io.psram_cs_io = PICO_PSRAM_CS_IO;
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
@@ -866,7 +868,6 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = PICO_V3_02_PSRAM_CLK_IO;
psram_io.psram_cs_io = PICO_V3_02_PSRAM_CS_IO;
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)) {
@@ -880,7 +881,6 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
return ESP_FAIL;
}
s_clk_mode = PSRAM_CLK_MODE_NORM;
psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
psram_io.psram_cs_io = D0WDR2_V3_PSRAM_CS_IO;
} else {
@@ -913,6 +913,12 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
psram_io.psram_spiwp_sd3_io = bootloader_flash_get_wp_pin();
}
if (psram_io.flash_clk_io == psram_io.psram_clk_io) {
s_clk_mode = PSRAM_CLK_MODE_NORM;
} else {
s_clk_mode = PSRAM_CLK_MODE_DCLK;
}
assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
s_psram_mode = mode;
@@ -967,7 +973,10 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
}
if (psram_is_32mbit_ver0()) {
s_clk_mode = PSRAM_CLK_MODE_DCLK;
if (s_clk_mode != PSRAM_CLK_MODE_DCLK) {
ESP_EARLY_LOGE(TAG, "PSRAM rev0 can't share CLK with Flash");
abort();
}
if (mode == PSRAM_CACHE_F80M_S80M) {
#ifdef CONFIG_SPIRAM_OCCUPY_NO_HOST
ESP_EARLY_LOGE(TAG, "This version of PSRAM needs to claim an extra SPI peripheral at 80MHz. Please either: choose lower frequency by SPIRAM_SPEED_, or select one SPI peripheral it by SPIRAM_OCCUPY_*SPI_HOST in the menuconfig.");