diff --git a/components/esp_psram/device/esp_psram_impl_ap_hex.c b/components/esp_psram/device/esp_psram_impl_ap_hex.c
index cbf7990690..a1ca9ce698 100644
--- a/components/esp_psram/device/esp_psram_impl_ap_hex.c
+++ b/components/esp_psram/device/esp_psram_impl_ap_hex.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,8 @@
 #define AP_HEX_PSRAM_WR_CMD_BITLEN         16
 #define AP_HEX_PSRAM_ADDR_BITLEN           32
 #define AP_HEX_PSRAM_RD_DUMMY_BITLEN       (2*(10-1))
+#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN   (2*(5-1))
+#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN   (2*(5-1))
 #define AP_HEX_PSRAM_WR_DUMMY_BITLEN       (2*(5-1))
 #define AP_HEX_PSRAM_VENDOR_ID             0xD
 
@@ -118,7 +120,7 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co
     int cmd_len = 16;
     uint32_t addr = 0x0;
     int addr_bit_len = 32;
-    int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN;
+    int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN;
     hex_psram_mode_reg_t mode_reg = {0};
     int data_bit_len = 16;
 
@@ -176,7 +178,7 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg)
 {
     int cmd_len = 16;
     int addr_bit_len = 32;
-    int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN;
+    int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN;
     int data_bit_len = 16;
 
     //Read MR0~1 register
diff --git a/components/esp_psram/esp32s3/esp_psram_impl_octal.c b/components/esp_psram/esp32s3/esp_psram_impl_octal.c
index 218c039e06..8fb629f1b7 100644
--- a/components/esp_psram/esp32s3/esp_psram_impl_octal.c
+++ b/components/esp_psram/esp32s3/esp_psram_impl_octal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,6 +31,7 @@
 #define OCT_PSRAM_WR_CMD_BITLEN         16
 #define OCT_PSRAM_ADDR_BITLEN           32
 #define OCT_PSRAM_RD_DUMMY_BITLEN       (2*(10-1))
+#define OCT_PSRAM_RD_REG_DUMMY_BITLEN   (2*(5-1))
 #define OCT_PSRAM_WR_DUMMY_BITLEN       (2*(5-1))
 #define OCT_PSRAM_CS1_IO                SPI_CS1_GPIO_NUM
 #define OCT_PSRAM_VENDOR_ID             0xD
@@ -115,7 +116,7 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
     int cmd_len = 16;
     uint32_t addr = 0x0;    //0x0 is the MR0 register
     int addr_bit_len = 32;
-    int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
+    int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
     opi_psram_mode_reg_t mode_reg = {0};
     int data_bit_len = 16;
 
@@ -178,7 +179,7 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg)
     esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
     int cmd_len = 16;
     int addr_bit_len = 32;
-    int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
+    int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
     int data_bit_len = 16;
 
     //Read MR0~1 register