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Merge branch 'feature/memory_layout_config_for_esp8684' into 'master'
heap_init: Adjust the stack/DRAM region size for ESP8684 See merge request espressif/esp-idf!16725
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@@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@@ -37,11 +37,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
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{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
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{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
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};
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};
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#define SOC_MEMORY_TYPE_DEFAULT 0
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#else
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#define SOC_MEMORY_TYPE_DEFAULT 2
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#define SOC_MEMORY_TYPE_DEFAULT 2
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#endif
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const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
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const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
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@@ -52,12 +48,28 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
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* this list should always be sorted from low to high by start address.
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* this list should always be sorted from low to high by start address.
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*
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*
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*/
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*/
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#define RAM_BOTTOM_LEVEL_REUSE_SIZE 0x18000
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#define RAM_BOTTOM_LEVEL_RESERVE_SIZE 0x8000
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#define MIN_ADDR_OF_STARTUP_STACK_TOP 0x3FCD81D0 //TODO: IDF-4585
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/*|------------------------------------ SRAM LEVEL 3 -------------------------------------|*/
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/*|0x3FCC0000 0x3FCDFFFF|*/
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/*|------------------------------------------------|--------------------------|-------------|*/
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/*| Shared Buffer | Startup Stack | Interface |*/
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/*|------------------------------------------------|--------------------------|-------------|*/
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/*| <---RAM_BOTTOM_LEVEL_REUSE_SIZE---> | <---------RAM_BOTTOM_LEVEL_RESERVE_SIZE---------> |*/
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/*|-----------------------------------------------------------------------------------------|*/
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const soc_memory_region_t soc_memory_regions[] = {
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const soc_memory_region_t soc_memory_regions[] = {
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{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory
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{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 1, can be remapped to ROM, can be used as trace memory
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{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //Block 5, can be remapped to ROM, can be used as trace memory
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{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //Block 2, can be remapped to ROM, can be used as trace memory
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{ 0x3FCC0000, 0x20000, 1, 0x403A0000}, //Block 9, can be used as trace memory
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{ 0x3FCC0000, RAM_BOTTOM_LEVEL_REUSE_SIZE, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 3, can be remapped to ROM, can be used as trace memory
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{ 0x3FCC0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE, RAM_BOTTOM_LEVEL_RESERVE_SIZE, 1, 0x403A0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE} //Block 4, can be used as trace memory
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};
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};
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_Static_assert(0x3FCC0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE <= MIN_ADDR_OF_STARTUP_STACK_TOP, "Heap reuse area overlaps startup stack");
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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