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https://github.com/espressif/esp-idf.git
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soc: add modem regs and force enable i2c_ana_mst clock
This commit is contained in:
wuzhenghui
@@ -33,6 +33,7 @@
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#include "esp_private/regi2c_ctrl.h"
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#include "soc/regi2c_lp_bias.h"
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#include "soc/regi2c_bias.h"
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#include "modem/modem_lpcon_reg.h"
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#include "bootloader_console.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_soc.h"
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@@ -86,6 +87,7 @@ static void bootloader_super_wdt_auto_feed(void)
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static inline void bootloader_hardware_init(void)
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{
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// ESP32H2-TODO: IDF-5990
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SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO);
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}
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static inline void bootloader_ana_reset_config(void)
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -9,6 +9,8 @@
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/regi2c_defs.h"
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#include "soc/i2c_ana_mst_reg.h"
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#ifdef __cplusplus
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extern "C" {
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200
components/soc/esp32h2/include/modem/modem_lpcon_reg.h
Normal file
200
components/soc/esp32h2/include/modem/modem_lpcon_reg.h
Normal file
@@ -0,0 +1,200 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "modem/reg_base.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
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/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_EN (BIT(0))
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#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
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#define MODEM_LPCON_CLK_EN_V 0x00000001U
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#define MODEM_LPCON_CLK_EN_S 0
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#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
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/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
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/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
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#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
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/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
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#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
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#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_EN_S 1
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/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
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#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
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#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U
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#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
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/* MODEM_LPCON_CLK_FE_MEM_EN : R/W; bitpos: [5]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_FE_MEM_EN (BIT(5))
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#define MODEM_LPCON_CLK_FE_MEM_EN_M (MODEM_LPCON_CLK_FE_MEM_EN_V << MODEM_LPCON_CLK_FE_MEM_EN_S)
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#define MODEM_LPCON_CLK_FE_MEM_EN_V 0x00000001U
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#define MODEM_LPCON_CLK_FE_MEM_EN_S 5
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#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
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/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
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#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
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#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_FO_S 1
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/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
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#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
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#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U
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#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
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/* MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [5]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(5))
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#define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S)
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#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U
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#define MODEM_LPCON_CLK_FE_MEM_FO_S 5
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#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
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/* MODEM_LPCON_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 31; */
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/* description: .*/
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#define MODEM_LPCON_PWR_TICK_TARGET 0x0000003FU
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#define MODEM_LPCON_PWR_TICK_TARGET_M (MODEM_LPCON_PWR_TICK_TARGET_V << MODEM_LPCON_PWR_TICK_TARGET_S)
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#define MODEM_LPCON_PWR_TICK_TARGET_V 0x0000003FU
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#define MODEM_LPCON_PWR_TICK_TARGET_S 0
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#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
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/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_RST_COEX (BIT(1))
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#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
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#define MODEM_LPCON_RST_COEX_V 0x00000001U
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#define MODEM_LPCON_RST_COEX_S 1
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/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_RST_I2C_MST (BIT(2))
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#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
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#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U
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#define MODEM_LPCON_RST_I2C_MST_S 2
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#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
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/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */
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/* description: .*/
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#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2))
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#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S)
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#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U
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#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2
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/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3))
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#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S)
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#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x00000001U
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#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3
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/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */
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/* description: .*/
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#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4))
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#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S)
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#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x00000001U
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#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4
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/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5))
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#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S)
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#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U
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#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5
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/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8))
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S)
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x00000001U
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8
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/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9))
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S)
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x00000001U
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#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9
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/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10))
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S)
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10
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/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11))
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S)
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x00000001U
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#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11
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/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007U
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#define MODEM_LPCON_MODEM_PWR_MEM_WP_M (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S)
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#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x00000007U
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#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12
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/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 5; */
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/* description: .*/
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#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U
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#define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S)
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#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U
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#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15
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/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */
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/* description: .*/
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#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003U
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#define MODEM_LPCON_MODEM_PWR_MEM_RA_M (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S)
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#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x00000003U
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#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18
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/* MODEM_LPCON_MODEM_PWR_MEM_RM : R/W; bitpos: [23:20]; default: 2; */
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/* description: .*/
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#define MODEM_LPCON_MODEM_PWR_MEM_RM 0x0000000FU
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#define MODEM_LPCON_MODEM_PWR_MEM_RM_M (MODEM_LPCON_MODEM_PWR_MEM_RM_V << MODEM_LPCON_MODEM_PWR_MEM_RM_S)
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#define MODEM_LPCON_MODEM_PWR_MEM_RM_V 0x0000000FU
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#define MODEM_LPCON_MODEM_PWR_MEM_RM_S 20
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#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
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/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35689088; */
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/* description: .*/
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#define MODEM_LPCON_DATE 0x0FFFFFFFU
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#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
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#define MODEM_LPCON_DATE_V 0x0FFFFFFFU
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#define MODEM_LPCON_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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8
components/soc/esp32h2/include/modem/reg_base.h
Normal file
8
components/soc/esp32h2/include/modem/reg_base.h
Normal file
@@ -0,0 +1,8 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#define DR_REG_MODEM_LPCON_BASE 0x600AD000
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218
components/soc/esp32h2/include/soc/i2c_ana_mst_reg.h
Normal file
218
components/soc/esp32h2/include/soc/i2c_ana_mst_reg.h
Normal file
@@ -0,0 +1,218 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
|
||||
/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C0_CTRL 0x01FFFFFFU
|
||||
#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S)
|
||||
#define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU
|
||||
#define I2C_MST_I2C0_CTRL_S 0
|
||||
/* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C0_BUSY (BIT(25))
|
||||
#define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S)
|
||||
#define I2C_MST_I2C0_BUSY_V 0x00000001U
|
||||
#define I2C_MST_I2C0_BUSY_S 25
|
||||
|
||||
#define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
|
||||
/* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C1_CTRL 0x01FFFFFFU
|
||||
#define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S)
|
||||
#define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU
|
||||
#define I2C_MST_I2C1_CTRL_S 0
|
||||
/* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C1_BUSY (BIT(25))
|
||||
#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S)
|
||||
#define I2C_MST_I2C1_BUSY_V 0x00000001U
|
||||
#define I2C_MST_I2C1_BUSY_S 25
|
||||
|
||||
#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
|
||||
/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C0_CONF 0x00FFFFFFU
|
||||
#define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S)
|
||||
#define I2C_MST_I2C0_CONF_V 0x00FFFFFFU
|
||||
#define I2C_MST_I2C0_CONF_S 0
|
||||
/* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C0_STATUS 0x000000FFU
|
||||
#define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S)
|
||||
#define I2C_MST_I2C0_STATUS_V 0x000000FFU
|
||||
#define I2C_MST_I2C0_STATUS_S 24
|
||||
|
||||
#define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
|
||||
/* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C1_CONF 0x00FFFFFFU
|
||||
#define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S)
|
||||
#define I2C_MST_I2C1_CONF_V 0x00FFFFFFU
|
||||
#define I2C_MST_I2C1_CONF_S 0
|
||||
/* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C1_STATUS 0x000000FFU
|
||||
#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S)
|
||||
#define I2C_MST_I2C1_STATUS_V 0x000000FFU
|
||||
#define I2C_MST_I2C1_STATUS_S 24
|
||||
|
||||
#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
|
||||
/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_BURST_CTRL 0xFFFFFFFFU
|
||||
#define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S)
|
||||
#define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU
|
||||
#define I2C_MST_BURST_CTRL_S 0
|
||||
|
||||
#define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
|
||||
/* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C_MST_BURST_DONE (BIT(0))
|
||||
#define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S)
|
||||
#define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U
|
||||
#define I2C_MST_I2C_MST_BURST_DONE_S 0
|
||||
/* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
|
||||
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S)
|
||||
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U
|
||||
#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1
|
||||
/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
|
||||
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S)
|
||||
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U
|
||||
#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2
|
||||
/* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU
|
||||
#define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S)
|
||||
#define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU
|
||||
#define I2C_MST_BURST_TIMEOUT_CNT_S 3
|
||||
|
||||
#define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
|
||||
/* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ANA_CONF0 0x00FFFFFFU
|
||||
#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S)
|
||||
#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU
|
||||
#define I2C_MST_ANA_CONF0_S 0
|
||||
/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ANA_STATUS0 0x000000FFU
|
||||
#define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S)
|
||||
#define I2C_MST_ANA_STATUS0_V 0x000000FFU
|
||||
#define I2C_MST_ANA_STATUS0_S 24
|
||||
|
||||
#define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
|
||||
/* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ANA_CONF1 0x00FFFFFFU
|
||||
#define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S)
|
||||
#define I2C_MST_ANA_CONF1_V 0x00FFFFFFU
|
||||
#define I2C_MST_ANA_CONF1_S 0
|
||||
/* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ANA_STATUS1 0x000000FFU
|
||||
#define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S)
|
||||
#define I2C_MST_ANA_STATUS1_V 0x000000FFU
|
||||
#define I2C_MST_ANA_STATUS1_S 24
|
||||
|
||||
#define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
|
||||
/* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ANA_CONF2 0x00FFFFFFU
|
||||
#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S)
|
||||
#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU
|
||||
#define I2C_MST_ANA_CONF2_S 0
|
||||
/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ANA_STATUS2 0x000000FFU
|
||||
#define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S)
|
||||
#define I2C_MST_ANA_STATUS2_V 0x000000FFU
|
||||
#define I2C_MST_ANA_STATUS2_S 24
|
||||
|
||||
#define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
|
||||
/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU
|
||||
#define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S)
|
||||
#define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU
|
||||
#define I2C_MST_I2C0_SCL_PULSE_DUR_S 0
|
||||
/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU
|
||||
#define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S)
|
||||
#define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU
|
||||
#define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6
|
||||
|
||||
#define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
|
||||
/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU
|
||||
#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S)
|
||||
#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU
|
||||
#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0
|
||||
/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU
|
||||
#define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S)
|
||||
#define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU
|
||||
#define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6
|
||||
|
||||
#define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
|
||||
/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU
|
||||
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S)
|
||||
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU
|
||||
#define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0
|
||||
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU
|
||||
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)
|
||||
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU
|
||||
#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_ARBITER_DIS (BIT(11))
|
||||
#define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S)
|
||||
#define I2C_MST_ARBITER_DIS_V 0x00000001U
|
||||
#define I2C_MST_ARBITER_DIS_S 11
|
||||
|
||||
#define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
|
||||
/* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_NOUSE 0xFFFFFFFFU
|
||||
#define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S)
|
||||
#define I2C_MST_NOUSE_V 0xFFFFFFFFU
|
||||
#define I2C_MST_NOUSE_S 0
|
||||
|
||||
#define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
|
||||
/* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_DATE 0x0FFFFFFFU
|
||||
#define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S)
|
||||
#define I2C_MST_DATE_V 0x0FFFFFFFU
|
||||
#define I2C_MST_DATE_S 0
|
||||
/* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/
|
||||
/* description: .*/
|
||||
#define I2C_MST_CLK_EN (BIT(28))
|
||||
#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S)
|
||||
#define I2C_MST_CLK_EN_V 0x00000001U
|
||||
#define I2C_MST_CLK_EN_S 28
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -49,6 +49,8 @@
|
||||
#define DR_REG_LP_APM0_BASE 0x60099800
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
|
||||
#define DR_REG_I2C_ANA_MST_BASE 0x600AD800
|
||||
|
||||
#define DR_REG_PMU_BASE 0x600B0000
|
||||
#define DR_REG_LP_CLKRST_BASE 0x600B0400
|
||||
#define DR_REG_EFUSE_BASE 0x600B0800
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -9,7 +9,6 @@
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
/* Analog function control register */
|
||||
#define I2C_MST_ANA_CONF0_REG 0x6000E040
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
|
||||
|
||||
|
||||
Reference in New Issue
Block a user