From d87e007c6697a615aaa7e6a4d66d6e4841084b13 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 29 Nov 2023 20:46:54 +0800 Subject: [PATCH] feat(esp32c5): add esp32c5-beta3 soc header files (part1) --- .../soc/esp32c5/include/soc/apb_saradc_reg.h | 813 ++ .../esp32c5/include/soc/apb_saradc_struct.h | 696 ++ .../esp32c5/include/soc/assist_debug_reg.h | 582 ++ .../esp32c5/include/soc/assist_debug_struct.h | 548 ++ .../esp32c5/include/soc/bitscrambler_reg.h | 481 ++ .../esp32c5/include/soc/bitscrambler_struct.h | 436 ++ .../soc/esp32c5/include/soc/ecc_mult_reg.h | 167 + .../soc/esp32c5/include/soc/ecc_mult_struct.h | 164 + .../soc/esp32c5/include/soc/ecdsa_reg.h | 318 + .../soc/esp32c5/include/soc/ecdsa_struct.h | 323 + .../soc/esp32c5/include/soc/gpio_ext_struct.h | 340 + components/soc/esp32c5/include/soc/gpio_reg.h | 5727 ++++++++++++++ .../soc/esp32c5/include/soc/hp_apm_reg.h | 1950 +++++ .../soc/esp32c5/include/soc/hp_apm_struct.h | 1734 +++++ components/soc/esp32c5/include/soc/huk_reg.h | 222 + .../soc/esp32c5/include/soc/huk_struct.h | 241 + components/soc/esp32c5/include/soc/i2c_reg.h | 1521 ++++ .../soc/esp32c5/include/soc/i2c_struct.h | 1277 +++ components/soc/esp32c5/include/soc/i2s_reg.h | 1268 +++ .../soc/esp32c5/include/soc/i2s_struct.h | 1007 +++ .../esp32c5/include/soc/lp_i2c_ana_mst_reg.h | 135 + .../include/soc/lp_i2c_ana_mst_struct.h | 150 + .../soc/esp32c5/include/soc/lp_wdt_reg.h | 324 + .../soc/esp32c5/include/soc/lp_wdt_struct.h | 309 + .../soc/esp32c5/include/soc/mcpwm_reg.h | 4514 +++++++++++ .../soc/esp32c5/include/soc/mcpwm_struct.h | 2031 +++++ .../soc/esp32c5/include/soc/parl_io_reg.h | 480 ++ .../soc/esp32c5/include/soc/parl_io_struct.h | 509 ++ components/soc/esp32c5/include/soc/rsa_reg.h | 233 + .../soc/esp32c5/include/soc/rsa_struct.h | 273 + components/soc/esp32c5/include/soc/sha_reg.h | 148 + .../soc/esp32c5/include/soc/sha_struct.h | 188 + .../soc/esp32c5/include/soc/soc_etm_reg.h | 6867 +++++++++++++++++ .../soc/esp32c5/include/soc/soc_etm_struct.h | 5116 ++++++++++++ components/soc/esp32c5/include/soc/spi_reg.h | 2116 +++++ .../soc/esp32c5/include/soc/spi_struct.h | 1615 ++++ .../soc/esp32c5/include/soc/systimer_reg.h | 630 ++ .../soc/esp32c5/include/soc/systimer_struct.h | 683 ++ .../soc/esp32c5/include/soc/timer_group_reg.h | 538 ++ .../esp32c5/include/soc/timer_group_struct.h | 552 ++ .../soc/esp32c5/include/soc/trace_reg.h | 463 ++ .../soc/esp32c5/include/soc/trace_struct.h | 461 ++ components/soc/esp32c5/include/soc/uart_reg.h | 1579 ++++ .../soc/esp32c5/include/soc/uart_struct.h | 1271 +++ components/soc/esp32c5/include/soc/uhci_reg.h | 966 +++ .../soc/esp32c5/include/soc/uhci_struct.h | 844 ++ .../soc/esp32c5/ld/esp32c5.peripherals.ld | 78 + 47 files changed, 52888 insertions(+) create mode 100644 components/soc/esp32c5/include/soc/apb_saradc_reg.h create mode 100644 components/soc/esp32c5/include/soc/apb_saradc_struct.h create mode 100644 components/soc/esp32c5/include/soc/assist_debug_reg.h create mode 100644 components/soc/esp32c5/include/soc/assist_debug_struct.h create mode 100644 components/soc/esp32c5/include/soc/bitscrambler_reg.h create mode 100644 components/soc/esp32c5/include/soc/bitscrambler_struct.h create mode 100644 components/soc/esp32c5/include/soc/ecc_mult_reg.h create mode 100644 components/soc/esp32c5/include/soc/ecc_mult_struct.h create mode 100644 components/soc/esp32c5/include/soc/ecdsa_reg.h create mode 100644 components/soc/esp32c5/include/soc/ecdsa_struct.h create mode 100644 components/soc/esp32c5/include/soc/gpio_ext_struct.h create mode 100644 components/soc/esp32c5/include/soc/gpio_reg.h create mode 100644 components/soc/esp32c5/include/soc/hp_apm_reg.h create mode 100644 components/soc/esp32c5/include/soc/hp_apm_struct.h create mode 100644 components/soc/esp32c5/include/soc/huk_reg.h create mode 100644 components/soc/esp32c5/include/soc/huk_struct.h create mode 100644 components/soc/esp32c5/include/soc/i2c_reg.h create mode 100644 components/soc/esp32c5/include/soc/i2c_struct.h create mode 100644 components/soc/esp32c5/include/soc/i2s_reg.h create mode 100644 components/soc/esp32c5/include/soc/i2s_struct.h create mode 100644 components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h create mode 100644 components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h create mode 100644 components/soc/esp32c5/include/soc/lp_wdt_reg.h create mode 100644 components/soc/esp32c5/include/soc/lp_wdt_struct.h create mode 100644 components/soc/esp32c5/include/soc/mcpwm_reg.h create mode 100644 components/soc/esp32c5/include/soc/mcpwm_struct.h create mode 100644 components/soc/esp32c5/include/soc/parl_io_reg.h create mode 100644 components/soc/esp32c5/include/soc/parl_io_struct.h create mode 100644 components/soc/esp32c5/include/soc/rsa_reg.h create mode 100644 components/soc/esp32c5/include/soc/rsa_struct.h create mode 100644 components/soc/esp32c5/include/soc/sha_reg.h create mode 100644 components/soc/esp32c5/include/soc/sha_struct.h create mode 100644 components/soc/esp32c5/include/soc/soc_etm_reg.h create mode 100644 components/soc/esp32c5/include/soc/soc_etm_struct.h create mode 100644 components/soc/esp32c5/include/soc/spi_reg.h create mode 100644 components/soc/esp32c5/include/soc/spi_struct.h create mode 100644 components/soc/esp32c5/include/soc/systimer_reg.h create mode 100644 components/soc/esp32c5/include/soc/systimer_struct.h create mode 100644 components/soc/esp32c5/include/soc/timer_group_reg.h create mode 100644 components/soc/esp32c5/include/soc/timer_group_struct.h create mode 100644 components/soc/esp32c5/include/soc/trace_reg.h create mode 100644 components/soc/esp32c5/include/soc/trace_struct.h create mode 100644 components/soc/esp32c5/include/soc/uart_reg.h create mode 100644 components/soc/esp32c5/include/soc/uart_struct.h create mode 100644 components/soc/esp32c5/include/soc/uhci_reg.h create mode 100644 components/soc/esp32c5/include/soc/uhci_struct.h create mode 100644 components/soc/esp32c5/ld/esp32c5.peripherals.ld diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/include/soc/apb_saradc_reg.h new file mode 100644 index 0000000000..27bb876c35 --- /dev/null +++ b/components/soc/esp32c5/include/soc/apb_saradc_reg.h @@ -0,0 +1,813 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** APB_SARADC_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0) +/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ +#define APB_SARADC_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) +#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U +#define APB_SARADC_SARADC_START_FORCE_S 0 +/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ +#define APB_SARADC_SARADC_START (BIT(1)) +#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) +#define APB_SARADC_SARADC_START_V 0x00000001U +#define APB_SARADC_SARADC_START_S 1 +/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ +#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) +#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U +#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 +/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ +#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) +#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU +#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 +/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ +#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) +#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U +#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 +/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 +/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ +#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) +#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U +#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 +/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ +#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29)) +#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S) +#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U +#define APB_SARADC_SARADC2_PWDET_DRV_S 29 +/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 + +/** APB_SARADC_CTRL2_REG register + * digital saradc configure register + */ +#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4) +/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ +#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) +#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 +/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) +#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR1_INV_S 9 +/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ +#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) +#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U +#define APB_SARADC_SARADC_SAR2_INV_S 10 +/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ +#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) +#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU +#define APB_SARADC_SARADC_TIMER_TARGET_S 12 +/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ +#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) +#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U +#define APB_SARADC_SARADC_TIMER_EN_S 24 + +/** APB_SARADC_FILTER_CTRL1_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8) +/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26 +/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S) +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U +#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29 + +/** APB_SARADC_SAR_PATT_TAB1_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18) +/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 + +/** APB_SARADC_SAR_PATT_TAB2_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c) +/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ +#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) +#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 + +/** APB_SARADC_ONETIME_SAMPLE_REG register + * digital saradc configure register + */ +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20) +/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ +#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) +#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U +#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ +#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) +#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 +/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ +#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) +#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U +#define APB_SARADC_SARADC_ONETIME_START_S 29 +/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ +#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 +/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ +#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 + +/** APB_SARADC_ARB_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24) +/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 +/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 + +/** APB_SARADC_FILTER_CTRL0_REG register + * digital saradc configure register + */ +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28) +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18 +/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S) +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU +#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22 +/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ +#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S) +#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U +#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31 + +/** APB_SARADC_SAR1DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c) +/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ +#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S) +#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC1_DATA_S 0 + +/** APB_SARADC_SAR2DATA_STATUS_REG register + * digital saradc configure register + */ +#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30) +/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ +#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S) +#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC2_DATA_S 0 + +/** APB_SARADC_THRES0_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34) +/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18 + +/** APB_SARADC_THRES1_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38) +/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S) +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU +#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0 +/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5 +/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU +#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18 + +/** APB_SARADC_THRES_CTRL_REG register + * digital saradc configure register + */ +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c) +/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ +#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S) +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27 +/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ +#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S) +#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_EN_S 30 +/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ +#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S) +#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_EN_S 31 + +/** APB_SARADC_INT_ENA_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40) +/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31 + +/** APB_SARADC_INT_RAW_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44) +/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31 + +/** APB_SARADC_INT_ST_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48) +/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31 + +/** APB_SARADC_INT_CLR_REG register + * digital saradc int register + */ +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c) +/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25)) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S) +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25 +/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26 +/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S) +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30 +/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S) +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U +#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31 + +/** APB_SARADC_DMA_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50) +/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 +/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) +#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U +#define APB_SARADC_APB_ADC_TRANS_S 31 + +/** APB_SARADC_CLKM_CONF_REG register + * digital saradc configure register + */ +#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54) +/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S) +#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define APB_SARADC_CLKM_DIV_NUM_S 0 +/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ +#define APB_SARADC_CLKM_DIV_B 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S) +#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_B_S 8 +/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ +#define APB_SARADC_CLKM_DIV_A 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S) +#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU +#define APB_SARADC_CLKM_DIV_A_S 14 +/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; + * reg clk en + */ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) +#define APB_SARADC_CLK_EN_V 0x00000001U +#define APB_SARADC_CLK_EN_S 20 +/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ +#define APB_SARADC_CLK_SEL 0x00000003U +#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S) +#define APB_SARADC_CLK_SEL_V 0x00000003U +#define APB_SARADC_CLK_SEL_S 21 + +/** APB_SARADC_APB_TSENS_CTRL_REG register + * digital tsens configure register + */ +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58) +/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ +#define APB_SARADC_TSENS_OUT 0x000000FFU +#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S) +#define APB_SARADC_TSENS_OUT_V 0x000000FFU +#define APB_SARADC_TSENS_OUT_S 0 +/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ +#define APB_SARADC_TSENS_IN_INV (BIT(13)) +#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S) +#define APB_SARADC_TSENS_IN_INV_V 0x00000001U +#define APB_SARADC_TSENS_IN_INV_S 13 +/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ +#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S) +#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU +#define APB_SARADC_TSENS_CLK_DIV_S 14 +/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ +#define APB_SARADC_TSENS_PU (BIT(22)) +#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S) +#define APB_SARADC_TSENS_PU_V 0x00000001U +#define APB_SARADC_TSENS_PU_S 22 + +/** APB_SARADC_TSENS_CTRL2_REG register + * digital tsens configure register + */ +#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c) +/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ +#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) +#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) +#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U +#define APB_SARADC_TSENS_CLK_SEL_S 15 + +/** APB_SARADC_CALI_REG register + * digital saradc configure register + */ +#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60) +/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ +#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S) +#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU +#define APB_SARADC_APB_SARADC_CALI_CFG_S 0 + +/** APB_TSENS_WAKE_REG register + * digital tsens configure register + */ +#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64) +/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ +#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S) +#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_LOW_S 0 +/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ +#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S) +#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU +#define APB_SARADC_WAKEUP_TH_HIGH_S 8 +/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ +#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16)) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S) +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16 +/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ +#define APB_SARADC_WAKEUP_MODE (BIT(17)) +#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S) +#define APB_SARADC_WAKEUP_MODE_V 0x00000001U +#define APB_SARADC_WAKEUP_MODE_S 17 +/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ +#define APB_SARADC_WAKEUP_EN (BIT(18)) +#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S) +#define APB_SARADC_WAKEUP_EN_V 0x00000001U +#define APB_SARADC_WAKEUP_EN_S 18 + +/** APB_TSENS_SAMPLE_REG register + * digital tsens configure register + */ +#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68) +/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ +#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S) +#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU +#define APB_SARADC_TSENS_SAMPLE_RATE_S 0 +/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0; + * HW sample en + */ +#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16)) +#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S) +#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U +#define APB_SARADC_TSENS_SAMPLE_EN_S 16 + +/** APB_SARADC_CTRL_DATE_REG register + * version + */ +#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc) +/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736; + * version + */ +#define APB_SARADC_DATE 0xFFFFFFFFU +#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) +#define APB_SARADC_DATE_V 0xFFFFFFFFU +#define APB_SARADC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/include/soc/apb_saradc_struct.h new file mode 100644 index 0000000000..47fc369928 --- /dev/null +++ b/components/soc/esp32c5/include/soc/apb_saradc_struct.h @@ -0,0 +1,696 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Register */ +/** Type of saradc_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0; + * select software enable saradc sample + */ + uint32_t saradc_saradc_start_force:1; + /** saradc_saradc_start : R/W; bitpos: [1]; default: 0; + * software enable saradc sample + */ + uint32_t saradc_saradc_start:1; + uint32_t reserved_2:4; + /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1; + * SAR clock gated + */ + uint32_t saradc_saradc_sar_clk_gated:1; + /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + uint32_t saradc_saradc_sar_clk_div:8; + /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7; + * 0 ~ 15 means length 1 ~ 16 + */ + uint32_t saradc_saradc_sar_patt_len:3; + uint32_t reserved_18:5; + /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + uint32_t saradc_saradc_sar_patt_p_clear:1; + uint32_t reserved_24:3; + /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0; + * force option to xpd sar blocks + */ + uint32_t saradc_saradc_xpd_sar_force:2; + /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0; + * enable saradc2 power detect driven func. + */ + uint32_t saradc_saradc2_pwdet_drv:1; + /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1; + * wait arbit signal stable after sar_done + */ + uint32_t saradc_saradc_wait_arb_cycle:2; + }; + uint32_t val; +} apb_saradc_ctrl_reg_t; + +/** Type of saradc_ctrl2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0; + * enable max meas num + */ + uint32_t saradc_saradc_meas_num_limit:1; + /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255; + * max conversion number + */ + uint32_t saradc_saradc_max_meas_num:8; + /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar1_inv:1; + /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted, otherwise not + */ + uint32_t saradc_saradc_sar2_inv:1; + uint32_t reserved_11:1; + /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10; + * to set saradc timer target + */ + uint32_t saradc_saradc_timer_target:12; + /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0; + * to enable saradc timer trigger + */ + uint32_t saradc_saradc_timer_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} apb_saradc_ctrl2_reg_t; + +/** Type of saradc_filter_ctrl1 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0; + * Factor of saradc filter1 + */ + uint32_t saradc_apb_saradc_filter_factor1:3; + /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0; + * Factor of saradc filter0 + */ + uint32_t saradc_apb_saradc_filter_factor0:3; + }; + uint32_t val; +} apb_saradc_filter_ctrl1_reg_t; + +/** Type of saradc_sar_patt_tab1 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab1_reg_t; + +/** Type of saradc_sar_patt_tab2 register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + uint32_t saradc_saradc_sar_patt_tab2:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} apb_saradc_sar_patt_tab2_reg_t; + +/** Type of saradc_onetime_sample register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0; + * configure onetime atten + */ + uint32_t saradc_saradc_onetime_atten:2; + /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13; + * configure onetime channel + */ + uint32_t saradc_saradc_onetime_channel:4; + /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0; + * trigger adc onetime sample + */ + uint32_t saradc_saradc_onetime_start:1; + /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0; + * enable adc2 onetime sample + */ + uint32_t saradc_saradc2_onetime_sample:1; + /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0; + * enable adc1 onetime sample + */ + uint32_t saradc_saradc1_onetime_sample:1; + }; + uint32_t val; +} apb_saradc_onetime_sample_reg_t; + +/** Type of saradc_arb_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0; + * adc2 arbiter force to enableapb controller + */ + uint32_t saradc_adc_arb_apb_force:1; + /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0; + * adc2 arbiter force to enable rtc controller + */ + uint32_t saradc_adc_arb_rtc_force:1; + /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0; + * adc2 arbiter force to enable wifi controller + */ + uint32_t saradc_adc_arb_wifi_force:1; + /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0; + * adc2 arbiter force grant + */ + uint32_t saradc_adc_arb_grant_force:1; + /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0; + * Set adc2 arbiterapb priority + */ + uint32_t saradc_adc_arb_apb_priority:2; + /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1; + * Set adc2 arbiter rtc priority + */ + uint32_t saradc_adc_arb_rtc_priority:2; + /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2; + * Set adc2 arbiter wifi priority + */ + uint32_t saradc_adc_arb_wifi_priority:2; + /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0; + * adc2 arbiter uses fixed priority + */ + uint32_t saradc_adc_arb_fix_priority:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} apb_saradc_arb_ctrl_reg_t; + +/** Type of saradc_filter_ctrl0 register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13; + * configure filter1 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel1:4; + /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13; + * configure filter0 to adc channel + */ + uint32_t saradc_apb_saradc_filter_channel0:4; + uint32_t reserved_26:5; + /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0; + * enable apb_adc1_filter + */ + uint32_t saradc_apb_saradc_filter_reset:1; + }; + uint32_t val; +} apb_saradc_filter_ctrl0_reg_t; + +/** Type of saradc_sar1data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0; + * saradc1 data + */ + uint32_t saradc_apb_saradc1_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar1data_status_reg_t; + +/** Type of saradc_sar2data_status register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0; + * saradc2 data + */ + uint32_t saradc_apb_saradc2_data:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_sar2data_status_reg_t; + +/** Type of saradc_thres0_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres0 to adc channel + */ + uint32_t saradc_apb_saradc_thres0_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_high:13; + /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres0 monitor thres + */ + uint32_t saradc_apb_saradc_thres0_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres0_ctrl_reg_t; + +/** Type of saradc_thres1_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13; + * configure thres1 to adc channel + */ + uint32_t saradc_apb_saradc_thres1_channel:4; + uint32_t reserved_4:1; + /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_high:13; + /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0; + * saradc thres1 monitor thres + */ + uint32_t saradc_apb_saradc_thres1_low:13; + uint32_t reserved_31:1; + }; + uint32_t val; +} apb_saradc_thres1_ctrl_reg_t; + +/** Type of saradc_thres_ctrl register + * digital saradc configure register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0; + * enable thres to all channel + */ + uint32_t saradc_apb_saradc_thres_all_en:1; + uint32_t reserved_28:2; + /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0; + * enable thres1 + */ + uint32_t saradc_apb_saradc_thres1_en:1; + /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0; + * enable thres0 + */ + uint32_t saradc_apb_saradc_thres0_en:1; + }; + uint32_t val; +} apb_saradc_thres_ctrl_reg_t; + +/** Type of saradc_int_ena register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0; + * tsens low interrupt enable + */ + uint32_t saradc_apb_saradc_tsens_int_ena:1; + /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0; + * saradc thres1 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_low_int_ena:1; + /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0; + * saradc thres0 low interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_low_int_ena:1; + /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0; + * saradc thres1 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres1_high_int_ena:1; + /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0; + * saradc thres0 high interrupt enable + */ + uint32_t saradc_apb_saradc_thres0_high_int_ena:1; + /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0; + * saradc2 done interrupt enable + */ + uint32_t saradc_apb_saradc2_done_int_ena:1; + /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0; + * saradc1 done interrupt enable + */ + uint32_t saradc_apb_saradc1_done_int_ena:1; + }; + uint32_t val; +} apb_saradc_int_ena_reg_t; + +/** Type of saradc_int_raw register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * saradc tsens interrupt raw + */ + uint32_t saradc_apb_saradc_tsens_int_raw:1; + /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * saradc thres1 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_low_int_raw:1; + /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * saradc thres0 low interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_low_int_raw:1; + /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * saradc thres1 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres1_high_int_raw:1; + /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * saradc thres0 high interrupt raw + */ + uint32_t saradc_apb_saradc_thres0_high_int_raw:1; + /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * saradc2 done interrupt raw + */ + uint32_t saradc_apb_saradc2_done_int_raw:1; + /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * saradc1 done interrupt raw + */ + uint32_t saradc_apb_saradc1_done_int_raw:1; + }; + uint32_t val; +} apb_saradc_int_raw_reg_t; + +/** Type of saradc_int_st register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0; + * saradc tsens interrupt state + */ + uint32_t saradc_apb_saradc_tsens_int_st:1; + /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0; + * saradc thres1 low interrupt state + */ + uint32_t saradc_apb_saradc_thres1_low_int_st:1; + /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0; + * saradc thres0 low interrupt state + */ + uint32_t saradc_apb_saradc_thres0_low_int_st:1; + /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0; + * saradc thres1 high interrupt state + */ + uint32_t saradc_apb_saradc_thres1_high_int_st:1; + /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0; + * saradc thres0 high interrupt state + */ + uint32_t saradc_apb_saradc_thres0_high_int_st:1; + /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0; + * saradc2 done interrupt state + */ + uint32_t saradc_apb_saradc2_done_int_st:1; + /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0; + * saradc1 done interrupt state + */ + uint32_t saradc_apb_saradc1_done_int_st:1; + }; + uint32_t val; +} apb_saradc_int_st_reg_t; + +/** Type of saradc_int_clr register + * digital saradc int register + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0; + * saradc tsens interrupt clear + */ + uint32_t saradc_apb_saradc_tsens_int_clr:1; + /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0; + * saradc thres1 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_low_int_clr:1; + /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0; + * saradc thres0 low interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_low_int_clr:1; + /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0; + * saradc thres1 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres1_high_int_clr:1; + /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0; + * saradc thres0 high interrupt clear + */ + uint32_t saradc_apb_saradc_thres0_high_int_clr:1; + /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0; + * saradc2 done interrupt clear + */ + uint32_t saradc_apb_saradc2_done_int_clr:1; + /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0; + * saradc1 done interrupt clear + */ + uint32_t saradc_apb_saradc1_done_int_clr:1; + }; + uint32_t val; +} apb_saradc_int_clr_reg_t; + +/** Type of saradc_dma_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255; + * the dma_in_suc_eof gen when sample cnt = spi_eof_num + */ + uint32_t saradc_apb_adc_eof_num:16; + uint32_t reserved_16:14; + /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0; + * reset_apb_adc_state + */ + uint32_t saradc_apb_adc_reset_fsm:1; + /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0; + * enable apb_adc use spi_dma + */ + uint32_t saradc_apb_adc_trans:1; + }; + uint32_t val; +} apb_saradc_dma_conf_reg_t; + +/** Type of saradc_clkm_conf register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clk_en : R/W; bitpos: [20]; default: 0; + * reg clk en + */ + uint32_t saradc_clk_en:1; + /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0; + * Set this bit to enable clk_apll + */ + uint32_t saradc_clk_sel:2; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_clkm_conf_reg_t; + +/** Type of saradc_apb_tsens_ctrl register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128; + * temperature sensor data out + */ + uint32_t saradc_tsens_out:8; + uint32_t reserved_8:5; + /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0; + * invert temperature sensor data + */ + uint32_t saradc_tsens_in_inv:1; + /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6; + * temperature sensor clock divider + */ + uint32_t saradc_tsens_clk_div:8; + /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0; + * temperature sensor power up + */ + uint32_t saradc_tsens_pu:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} apb_saradc_apb_tsens_ctrl_reg_t; + +/** Type of saradc_tsens_ctrl2 register + * digital tsens configure register + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0; + * tsens clk select + */ + uint32_t saradc_tsens_clk_sel:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} apb_saradc_tsens_ctrl2_reg_t; + +/** Type of saradc_cali register + * digital saradc configure register + */ +typedef union { + struct { + /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768; + * saradc cali factor + */ + uint32_t saradc_apb_saradc_cali_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_saradc_cali_reg_t; + +/** Type of tsens_wake register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0; + * reg_wakeup_th_low + */ + uint32_t saradc_wakeup_th_low:8; + /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255; + * reg_wakeup_th_high + */ + uint32_t saradc_wakeup_th_high:8; + /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0; + * reg_wakeup_over_upper_th + */ + uint32_t saradc_wakeup_over_upper_th:1; + /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0; + * reg_wakeup_mode + */ + uint32_t saradc_wakeup_mode:1; + /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0; + * reg_wakeup_en + */ + uint32_t saradc_wakeup_en:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} apb_tsens_wake_reg_t; + +/** Type of tsens_sample register + * digital tsens configure register + */ +typedef union { + struct { + /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20; + * HW sample rate + */ + uint32_t saradc_tsens_sample_rate:16; + /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0; + * HW sample en + */ + uint32_t saradc_tsens_sample_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} apb_tsens_sample_reg_t; + +/** Type of saradc_ctrl_date register + * version + */ +typedef union { + struct { + /** saradc_date : R/W; bitpos: [31:0]; default: 35676736; + * version + */ + uint32_t saradc_date:32; + }; + uint32_t val; +} apb_saradc_ctrl_date_reg_t; + + +typedef struct { + volatile apb_saradc_ctrl_reg_t saradc_ctrl; + volatile apb_saradc_ctrl2_reg_t saradc_ctrl2; + volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1; + uint32_t reserved_00c[3]; + volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1; + volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2; + volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample; + volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl; + volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0; + volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status; + volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status; + volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl; + volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl; + volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl; + volatile apb_saradc_int_ena_reg_t saradc_int_ena; + volatile apb_saradc_int_raw_reg_t saradc_int_raw; + volatile apb_saradc_int_st_reg_t saradc_int_st; + volatile apb_saradc_int_clr_reg_t saradc_int_clr; + volatile apb_saradc_dma_conf_reg_t saradc_dma_conf; + volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl; + volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2; + volatile apb_saradc_cali_reg_t saradc_cali; + volatile apb_tsens_wake_reg_t tsens_wake; + volatile apb_tsens_sample_reg_t tsens_sample; + uint32_t reserved_06c[228]; + volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date; +} apb_dev_t; + +extern apb_dev_t APB_SARADC; + +#ifndef __cplusplus +_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/assist_debug_reg.h b/components/soc/esp32c5/include/soc/assist_debug_reg.h new file mode 100644 index 0000000000..cda7314f21 --- /dev/null +++ b/components/soc/esp32c5/include/soc/assist_debug_reg.h @@ -0,0 +1,582 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register + * core0 monitor enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 + +/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register + * core0 monitor interrupt status register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 + +/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register + * core0 monitor interrupt enable register + */ +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 + +/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register + * core0 monitor interrupt clr register + */ +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register + * core0 dram0 region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register + * core0 dram0 region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register + * core0 PIF region0 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register + * core0 PIF region1 addr configuration register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register + * core0 area pc status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) +/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register + * core0 area sp status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) +/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register + * stack min value + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) +/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register + * stack max value + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) +/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_PC_REG register + * stack monitor pc status register + */ +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) +/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register + * record enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) +/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register + * record status regsiter + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 +/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 + +/** ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78) +/** ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0; + * need desc + */ +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_M (ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V << ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S) +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S 0 + +/** ASSIST_DEBUG_CLOCK_GATE_REG register + * clock register + */ +#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c) +/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ +#define ASSIST_DEBUG_CLK_EN (BIT(0)) +#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) +#define ASSIST_DEBUG_CLK_EN_V 0x00000001U +#define ASSIST_DEBUG_CLK_EN_S 0 + +/** ASSIST_DEBUG_DATE_REG register + * version register + */ +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) +/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35725648; + * version register + */ +#define ASSIST_DEBUG_DATE 0x0FFFFFFFU +#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S) +#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU +#define ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/assist_debug_struct.h b/components/soc/esp32c5/include/soc/assist_debug_struct.h new file mode 100644 index 0000000000..a85202837e --- /dev/null +++ b/components/soc/esp32c5/include/soc/assist_debug_struct.h @@ -0,0 +1,548 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: monitor configuration registers */ +/** Type of core_0_montr_ena register + * core0 monitor enable configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor enable + */ + uint32_t core_0_area_dram0_0_rd_ena:1; + /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor enable + */ + uint32_t core_0_area_dram0_0_wr_ena:1; + /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor enable + */ + uint32_t core_0_area_dram0_1_rd_ena:1; + /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor enable + */ + uint32_t core_0_area_dram0_1_wr_ena:1; + /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor enable + */ + uint32_t core_0_area_pif_0_rd_ena:1; + /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor enable + */ + uint32_t core_0_area_pif_0_wr_ena:1; + /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor enable + */ + uint32_t core_0_area_pif_1_rd_ena:1; + /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor enable + */ + uint32_t core_0_area_pif_1_wr_ena:1; + /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor enable + */ + uint32_t core_0_sp_spill_min_ena:1; + /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor enable + */ + uint32_t core_0_sp_spill_max_ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_montr_ena_reg_t; + +/** Type of core_0_area_dram0_0_min register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region0 start addr + */ + uint32_t core_0_area_dram0_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_min_reg_t; + +/** Type of core_0_area_dram0_0_max register + * core0 dram0 region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region0 end addr + */ + uint32_t core_0_area_dram0_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_max_reg_t; + +/** Type of core_0_area_dram0_1_min register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 dram0 region1 start addr + */ + uint32_t core_0_area_dram0_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_min_reg_t; + +/** Type of core_0_area_dram0_1_max register + * core0 dram0 region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 dram0 region1 end addr + */ + uint32_t core_0_area_dram0_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_max_reg_t; + +/** Type of core_0_area_pif_0_min register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region0 start addr + */ + uint32_t core_0_area_pif_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_min_reg_t; + +/** Type of core_0_area_pif_0_max register + * core0 PIF region0 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region0 end addr + */ + uint32_t core_0_area_pif_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_max_reg_t; + +/** Type of core_0_area_pif_1_min register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Core0 PIF region1 start addr + */ + uint32_t core_0_area_pif_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_min_reg_t; + +/** Type of core_0_area_pif_1_max register + * core0 PIF region1 addr configuration register + */ +typedef union { + struct { + /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0; + * Core0 PIF region1 end addr + */ + uint32_t core_0_area_pif_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_max_reg_t; + +/** Type of core_0_area_pc register + * core0 area pc status register + */ +typedef union { + struct { + /** core_0_area_pc : RO; bitpos: [31:0]; default: 0; + * the stackpointer when first touch region monitor interrupt + */ + uint32_t core_0_area_pc:32; + }; + uint32_t val; +} assist_debug_core_0_area_pc_reg_t; + +/** Type of core_0_area_sp register + * core0 area sp status register + */ +typedef union { + struct { + /** core_0_area_sp : RO; bitpos: [31:0]; default: 0; + * the PC when first touch region monitor interrupt + */ + uint32_t core_0_area_sp:32; + }; + uint32_t val; +} assist_debug_core_0_area_sp_reg_t; + +/** Type of core_0_sp_min register + * stack min value + */ +typedef union { + struct { + /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; + * core0 sp region configuration regsiter + */ + uint32_t core_0_sp_min:32; + }; + uint32_t val; +} assist_debug_core_0_sp_min_reg_t; + +/** Type of core_0_sp_max register + * stack max value + */ +typedef union { + struct { + /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295; + * core0 sp pc status register + */ + uint32_t core_0_sp_max:32; + }; + uint32_t val; +} assist_debug_core_0_sp_max_reg_t; + +/** Type of core_0_sp_pc register + * stack monitor pc status register + */ +typedef union { + struct { + /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; + * This regsiter stores the PC when trigger stack monitor. + */ + uint32_t core_0_sp_pc:32; + }; + uint32_t val; +} assist_debug_core_0_sp_pc_reg_t; + + +/** Group: interrupt configuration register */ +/** Type of core_0_intr_raw register + * core0 monitor interrupt status register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt status + */ + uint32_t core_0_area_dram0_0_rd_raw:1; + /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt status + */ + uint32_t core_0_area_dram0_0_wr_raw:1; + /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt status + */ + uint32_t core_0_area_dram0_1_rd_raw:1; + /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt status + */ + uint32_t core_0_area_dram0_1_wr_raw:1; + /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt status + */ + uint32_t core_0_area_pif_0_rd_raw:1; + /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt status + */ + uint32_t core_0_area_pif_0_wr_raw:1; + /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt status + */ + uint32_t core_0_area_pif_1_rd_raw:1; + /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt status + */ + uint32_t core_0_area_pif_1_wr_raw:1; + /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt status + */ + uint32_t core_0_sp_spill_min_raw:1; + /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt status + */ + uint32_t core_0_sp_spill_max_raw:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_intr_raw_reg_t; + +/** Type of core_0_intr_ena register + * core0 monitor interrupt enable register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_rd_intr_ena:1; + /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_wr_intr_ena:1; + /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_rd_intr_ena:1; + /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_wr_intr_ena:1; + /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ + uint32_t core_0_area_pif_0_rd_intr_ena:1; + /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ + uint32_t core_0_area_pif_0_wr_intr_ena:1; + /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ + uint32_t core_0_area_pif_1_rd_intr_ena:1; + /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ + uint32_t core_0_area_pif_1_wr_intr_ena:1; + /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_min_intr_ena:1; + /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_max_intr_ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_intr_ena_reg_t; + +/** Type of core_0_intr_clr register + * core0 monitor interrupt clr register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_rd_clr:1; + /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_0_wr_clr:1; + /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_rd_clr:1; + /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt clr + */ + uint32_t core_0_area_dram0_1_wr_clr:1; + /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt clr + */ + uint32_t core_0_area_pif_0_rd_clr:1; + /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt clr + */ + uint32_t core_0_area_pif_0_wr_clr:1; + /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt clr + */ + uint32_t core_0_area_pif_1_rd_clr:1; + /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt clr + */ + uint32_t core_0_area_pif_1_wr_clr:1; + /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_min_clr:1; + /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt clr + */ + uint32_t core_0_sp_spill_max_clr:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} assist_debug_core_0_intr_clr_reg_t; + + +/** Group: pc reording configuration register */ +/** Type of core_0_rcd_en register + * record enable configuration register + */ +typedef union { + struct { + /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; + * Set 1 to enable record PC + */ + uint32_t core_0_rcd_recorden:1; + /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; + * Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + */ + uint32_t core_0_rcd_pdebugen:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_rcd_en_reg_t; + + +/** Group: pc reording status register */ +/** Type of core_0_rcd_pdebugpc register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0; + * recorded PC + */ + uint32_t core_0_rcd_pdebugpc:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugpc_reg_t; + +/** Type of core_0_rcd_pdebugsp register + * record status regsiter + */ +typedef union { + struct { + /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0; + * recorded sp + */ + uint32_t core_0_rcd_pdebugsp:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugsp_reg_t; + + +/** Group: cpu status registers */ +/** Type of core_0_lastpc_before_exception register + * cpu status register + */ +typedef union { + struct { + /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0; + * cpu's lastpc before exception + */ + uint32_t core_0_lastpc_before_exc:32; + }; + uint32_t val; +} assist_debug_core_0_lastpc_before_exception_reg_t; + +/** Type of core_0_debug_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_debug_mode : RO; bitpos: [0]; default: 0; + * cpu debug mode status, 1 means cpu enter debug mode. + */ + uint32_t core_0_debug_mode:1; + /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; + * cpu debug_module active status + */ + uint32_t core_0_debug_module_active:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_debug_mode_reg_t; + +/** Type of core_0_dmactive_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_dmactive_lpcore : RO; bitpos: [0]; default: 0; + * need desc + */ + uint32_t core_0_dmactive_lpcore:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_core_0_dmactive_mode_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * clock register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 force on the clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_clock_gate_reg_t; + +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725648; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} assist_debug_date_reg_t; + + +typedef struct { + volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena; + volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; + volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; + volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; + volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; + volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; + volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; + volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; + volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; + volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; + volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + uint32_t reserved_050[8]; + volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; + volatile assist_debug_core_0_dmactive_mode_reg_t core_0_dmactive_mode; + volatile assist_debug_clock_gate_reg_t clock_gate; + uint32_t reserved_080[223]; + volatile assist_debug_date_reg_t date; +} assist_debug_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/include/soc/bitscrambler_reg.h new file mode 100644 index 0000000000..44bfc3c874 --- /dev/null +++ b/components/soc/esp32c5/include/soc/bitscrambler_reg.h @@ -0,0 +1,481 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** BITSCRAMBLER_TX_INST_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0) +/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ +#define BITSCRAMBLER_TX_INST_IDX 0x00000007U +#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S) +#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U +#define BITSCRAMBLER_TX_INST_IDX_S 0 +/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ +#define BITSCRAMBLER_TX_INST_POS 0x0000000FU +#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S) +#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU +#define BITSCRAMBLER_TX_INST_POS_S 3 + +/** BITSCRAMBLER_TX_INST_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4) +/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4; + * write this bits to update instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG + */ +#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU +#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S) +#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU +#define BITSCRAMBLER_TX_INST_S 0 + +/** BITSCRAMBLER_RX_INST_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8) +/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ +#define BITSCRAMBLER_RX_INST_IDX 0x00000007U +#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S) +#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U +#define BITSCRAMBLER_RX_INST_IDX_S 0 +/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ +#define BITSCRAMBLER_RX_INST_POS 0x0000000FU +#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S) +#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU +#define BITSCRAMBLER_RX_INST_POS_S 3 + +/** BITSCRAMBLER_RX_INST_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc) +/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12; + * write this bits to update instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG + */ +#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU +#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S) +#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU +#define BITSCRAMBLER_RX_INST_S 0 + +/** BITSCRAMBLER_TX_LUT_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10) +/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_tx_lut_mode + */ +#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU +#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S) +#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU +#define BITSCRAMBLER_TX_LUT_IDX_S 0 +/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ +#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U +#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S) +#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U +#define BITSCRAMBLER_TX_LUT_MODE_S 11 + +/** BITSCRAMBLER_TX_LUT_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14) +/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20; + * write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + */ +#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU +#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S) +#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU +#define BITSCRAMBLER_TX_LUT_S 0 + +/** BITSCRAMBLER_RX_LUT_CFG0_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18) +/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_rx_lut_mode + */ +#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU +#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S) +#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU +#define BITSCRAMBLER_RX_LUT_IDX_S 0 +/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ +#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U +#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S) +#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U +#define BITSCRAMBLER_RX_LUT_MODE_S 11 + +/** BITSCRAMBLER_RX_LUT_CFG1_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c) +/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28; + * write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + */ +#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU +#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S) +#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU +#define BITSCRAMBLER_RX_LUT_S 0 + +/** BITSCRAMBLER_TX_TAILING_BITS_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20) +/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ +#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU +#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S) +#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU +#define BITSCRAMBLER_TX_TAILING_BITS_S 0 + +/** BITSCRAMBLER_RX_TAILING_BITS_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24) +/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ +#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU +#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S) +#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU +#define BITSCRAMBLER_RX_TAILING_BITS_S 0 + +/** BITSCRAMBLER_TX_CTRL_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28) +/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler tx + */ +#define BITSCRAMBLER_TX_ENA (BIT(0)) +#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S) +#define BITSCRAMBLER_TX_ENA_V 0x00000001U +#define BITSCRAMBLER_TX_ENA_S 0 +/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler tx core + */ +#define BITSCRAMBLER_TX_PAUSE (BIT(1)) +#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S) +#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U +#define BITSCRAMBLER_TX_PAUSE_S 1 +/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler tx core + */ +#define BITSCRAMBLER_TX_HALT (BIT(2)) +#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S) +#define BITSCRAMBLER_TX_HALT_V 0x00000001U +#define BITSCRAMBLER_TX_HALT_S 2 +/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler tx core EOF signal generating mode which is + * combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 + * counter by write peripheral buffer + */ +#define BITSCRAMBLER_TX_EOF_MODE (BIT(3)) +#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S) +#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_EOF_MODE_S 3 +/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler tx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ +#define BITSCRAMBLER_TX_COND_MODE (BIT(4)) +#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S) +#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_COND_MODE_S 4 +/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ +#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5)) +#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S) +#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_FETCH_MODE_S 5 +/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ +#define BITSCRAMBLER_TX_HALT_MODE (BIT(6)) +#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S) +#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U +#define BITSCRAMBLER_TX_HALT_MODE_S 6 +/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler tx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ +#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7)) +#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S) +#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U +#define BITSCRAMBLER_TX_RD_DUMMY_S 7 +/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler tx fifo + */ +#define BITSCRAMBLER_TX_FIFO_RST (BIT(8)) +#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S) +#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U +#define BITSCRAMBLER_TX_FIFO_RST_S 8 + +/** BITSCRAMBLER_RX_CTRL_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c) +/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler rx + */ +#define BITSCRAMBLER_RX_ENA (BIT(0)) +#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S) +#define BITSCRAMBLER_RX_ENA_V 0x00000001U +#define BITSCRAMBLER_RX_ENA_S 0 +/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler rx core + */ +#define BITSCRAMBLER_RX_PAUSE (BIT(1)) +#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S) +#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U +#define BITSCRAMBLER_RX_PAUSE_S 1 +/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler rx core + */ +#define BITSCRAMBLER_RX_HALT (BIT(2)) +#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S) +#define BITSCRAMBLER_RX_HALT_V 0x00000001U +#define BITSCRAMBLER_RX_HALT_S 2 +/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler rx core EOF signal generating mode which is + * combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral + * buffer, 0 counter by write dma fifo + */ +#define BITSCRAMBLER_RX_EOF_MODE (BIT(3)) +#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S) +#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_EOF_MODE_S 3 +/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler rx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ +#define BITSCRAMBLER_RX_COND_MODE (BIT(4)) +#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S) +#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_COND_MODE_S 4 +/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ +#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5)) +#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S) +#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_FETCH_MODE_S 5 +/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ +#define BITSCRAMBLER_RX_HALT_MODE (BIT(6)) +#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S) +#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U +#define BITSCRAMBLER_RX_HALT_MODE_S 6 +/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler rx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ +#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7)) +#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S) +#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U +#define BITSCRAMBLER_RX_RD_DUMMY_S 7 +/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler rx fifo + */ +#define BITSCRAMBLER_RX_FIFO_RST (BIT(8)) +#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S) +#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U +#define BITSCRAMBLER_RX_FIFO_RST_S 8 + +/** BITSCRAMBLER_TX_STATE_REG register + * Status registers + */ +#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30) +/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1; + * represents the bitscrambler tx core in halt mode + */ +#define BITSCRAMBLER_TX_IN_IDLE (BIT(0)) +#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S) +#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U +#define BITSCRAMBLER_TX_IN_IDLE_S 0 +/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0; + * represents the bitscrambler tx core in run mode + */ +#define BITSCRAMBLER_TX_IN_RUN (BIT(1)) +#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S) +#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U +#define BITSCRAMBLER_TX_IN_RUN_S 1 +/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0; + * represents the bitscrambler tx core in wait mode to wait write back done + */ +#define BITSCRAMBLER_TX_IN_WAIT (BIT(2)) +#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S) +#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U +#define BITSCRAMBLER_TX_IN_WAIT_S 2 +/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0; + * represents the bitscrambler tx core in pause mode + */ +#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3)) +#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S) +#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U +#define BITSCRAMBLER_TX_IN_PAUSE_S 3 +/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0; + * represents the bitscrambler tx fifo in empty state + */ +#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4)) +#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S) +#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U +#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4 +/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler tx core when get EOF + */ +#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU +#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S) +#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU +#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16 +/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler tx core + */ +#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30)) +#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S) +#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U +#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30 +/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_tx_eof_overload and + * reg_bitscrambler_tx_eof_get_cnt registers + */ +#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31)) +#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S) +#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U +#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31 + +/** BITSCRAMBLER_RX_STATE_REG register + * Status registers + */ +#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34) +/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1; + * represents the bitscrambler rx core in halt mode + */ +#define BITSCRAMBLER_RX_IN_IDLE (BIT(0)) +#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S) +#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U +#define BITSCRAMBLER_RX_IN_IDLE_S 0 +/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0; + * represents the bitscrambler rx core in run mode + */ +#define BITSCRAMBLER_RX_IN_RUN (BIT(1)) +#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S) +#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U +#define BITSCRAMBLER_RX_IN_RUN_S 1 +/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0; + * represents the bitscrambler rx core in wait mode to wait write back done + */ +#define BITSCRAMBLER_RX_IN_WAIT (BIT(2)) +#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S) +#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U +#define BITSCRAMBLER_RX_IN_WAIT_S 2 +/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0; + * represents the bitscrambler rx core in pause mode + */ +#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3)) +#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S) +#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U +#define BITSCRAMBLER_RX_IN_PAUSE_S 3 +/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0; + * represents the bitscrambler rx fifo in full state + */ +#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4)) +#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S) +#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U +#define BITSCRAMBLER_RX_FIFO_FULL_S 4 +/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler rx core when get EOF + */ +#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU +#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S) +#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU +#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16 +/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler rx core + */ +#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30)) +#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S) +#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U +#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30 +/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_rx_eof_overload and + * reg_bitscrambler_rx_eof_get_cnt registers + */ +#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31)) +#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S) +#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U +#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31 + +/** BITSCRAMBLER_SYS_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8) +/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0; + * write this bit to set the bitscrambler tx loop back to DMA rx + */ +#define BITSCRAMBLER_LOOP_MODE (BIT(0)) +#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S) +#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U +#define BITSCRAMBLER_LOOP_MODE_S 0 +/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0; + * Reserved + */ +#define BITSCRAMBLER_CLK_EN (BIT(31)) +#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S) +#define BITSCRAMBLER_CLK_EN_V 0x00000001U +#define BITSCRAMBLER_CLK_EN_S 31 + +/** BITSCRAMBLER_VERSION_REG register + * Control and configuration registers + */ +#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc) +/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024; + * Reserved + */ +#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU +#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S) +#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU +#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/include/soc/bitscrambler_struct.h new file mode 100644 index 0000000000..007c244d50 --- /dev/null +++ b/components/soc/esp32c5/include/soc/bitscrambler_struct.h @@ -0,0 +1,436 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of tx_inst_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ + uint32_t tx_inst_idx:3; + /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ + uint32_t tx_inst_pos:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} bitscrambler_tx_inst_cfg0_reg_t; + +/** Type of tx_inst_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_inst : R/W; bitpos: [31:0]; default: 4; + * write this bits to update instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_TX_INST_CFG0_REG + */ + uint32_t tx_inst:32; + }; + uint32_t val; +} bitscrambler_tx_inst_cfg1_reg_t; + +/** Type of rx_inst_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0; + * write this bits to specify the one of 8 instruction + */ + uint32_t rx_inst_idx:3; + /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0; + * write this bits to specify the bit position of 257 bit instruction which in units + * of 32 bits + */ + uint32_t rx_inst_pos:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} bitscrambler_rx_inst_cfg0_reg_t; + +/** Type of rx_inst_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_inst : R/W; bitpos: [31:0]; default: 12; + * write this bits to update instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by + * BITSCRAMBLER_RX_INST_CFG0_REG + */ + uint32_t rx_inst:32; + }; + uint32_t val; +} bitscrambler_rx_inst_cfg1_reg_t; + +/** Type of tx_lut_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_tx_lut_mode + */ + uint32_t tx_lut_idx:11; + /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ + uint32_t tx_lut_mode:2; + uint32_t reserved_13:19; + }; + uint32_t val; +} bitscrambler_tx_lut_cfg0_reg_t; + +/** Type of tx_lut_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_lut : R/W; bitpos: [31:0]; default: 20; + * write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + */ + uint32_t tx_lut:32; + }; + uint32_t val; +} bitscrambler_tx_lut_cfg1_reg_t; + +/** Type of rx_lut_cfg0 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0; + * write this bits to specify the bytes position of LUT RAM based on + * reg_bitscrambler_rx_lut_mode + */ + uint32_t rx_lut_idx:11; + /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0; + * write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 + * bytes + */ + uint32_t rx_lut_mode:2; + uint32_t reserved_13:19; + }; + uint32_t val; +} bitscrambler_rx_lut_cfg0_reg_t; + +/** Type of rx_lut_cfg1 register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_lut : R/W; bitpos: [31:0]; default: 28; + * write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read + * this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + */ + uint32_t rx_lut:32; + }; + uint32_t val; +} bitscrambler_rx_lut_cfg1_reg_t; + + +/** Group: Configuration registers */ +/** Type of tx_tailing_bits register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ + uint32_t tx_tailing_bits:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} bitscrambler_tx_tailing_bits_reg_t; + +/** Type of rx_tailing_bits register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0; + * write this bits to specify the extra data bit length after getting EOF + */ + uint32_t rx_tailing_bits:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} bitscrambler_rx_tailing_bits_reg_t; + +/** Type of tx_ctrl register + * Control and configuration registers + */ +typedef union { + struct { + /** tx_ena : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler tx + */ + uint32_t tx_ena:1; + /** tx_pause : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler tx core + */ + uint32_t tx_pause:1; + /** tx_halt : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler tx core + */ + uint32_t tx_halt:1; + /** tx_eof_mode : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler tx core EOF signal generating mode which is + * combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 + * counter by write peripheral buffer + */ + uint32_t tx_eof_mode:1; + /** tx_cond_mode : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler tx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ + uint32_t tx_cond_mode:1; + /** tx_fetch_mode : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ + uint32_t tx_fetch_mode:1; + /** tx_halt_mode : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ + uint32_t tx_halt_mode:1; + /** tx_rd_dummy : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler tx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ + uint32_t tx_rd_dummy:1; + /** tx_fifo_rst : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler tx fifo + */ + uint32_t tx_fifo_rst:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} bitscrambler_tx_ctrl_reg_t; + +/** Type of rx_ctrl register + * Control and configuration registers + */ +typedef union { + struct { + /** rx_ena : R/W; bitpos: [0]; default: 0; + * write this bit to enable the bitscrambler rx + */ + uint32_t rx_ena:1; + /** rx_pause : R/W; bitpos: [1]; default: 0; + * write this bit to pause the bitscrambler rx core + */ + uint32_t rx_pause:1; + /** rx_halt : R/W; bitpos: [2]; default: 1; + * write this bit to halt the bitscrambler rx core + */ + uint32_t rx_halt:1; + /** rx_eof_mode : R/W; bitpos: [3]; default: 0; + * write this bit to ser the bitscrambler rx core EOF signal generating mode which is + * combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral + * buffer, 0 counter by write dma fifo + */ + uint32_t rx_eof_mode:1; + /** rx_cond_mode : R/W; bitpos: [4]; default: 0; + * write this bit to specify the LOOP instruction condition mode of bitscrambler rx + * core, 0: use the little than operator to get the condition, 1: use not equal + * operator to get the condition + */ + uint32_t rx_cond_mode:1; + /** rx_fetch_mode : R/W; bitpos: [5]; default: 0; + * write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch + * by reset, 1: fetch by instrutions + */ + uint32_t rx_fetch_mode:1; + /** rx_halt_mode : R/W; bitpos: [6]; default: 0; + * write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: + * wait write data back done, , 1: ignore write data back + */ + uint32_t rx_halt_mode:1; + /** rx_rd_dummy : R/W; bitpos: [7]; default: 0; + * write this bit to set the bitscrambler rx core read data mode when EOF received.0: + * wait read data, 1: ignore read data + */ + uint32_t rx_rd_dummy:1; + /** rx_fifo_rst : WT; bitpos: [8]; default: 0; + * write this bit to reset the bitscrambler rx fifo + */ + uint32_t rx_fifo_rst:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} bitscrambler_rx_ctrl_reg_t; + +/** Type of sys register + * Control and configuration registers + */ +typedef union { + struct { + /** loop_mode : R/W; bitpos: [0]; default: 0; + * write this bit to set the bitscrambler tx loop back to DMA rx + */ + uint32_t loop_mode:1; + uint32_t reserved_1:30; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + }; + uint32_t val; +} bitscrambler_sys_reg_t; + + +/** Group: Status registers */ +/** Type of tx_state register + * Status registers + */ +typedef union { + struct { + /** tx_in_idle : RO; bitpos: [0]; default: 1; + * represents the bitscrambler tx core in halt mode + */ + uint32_t tx_in_idle:1; + /** tx_in_run : RO; bitpos: [1]; default: 0; + * represents the bitscrambler tx core in run mode + */ + uint32_t tx_in_run:1; + /** tx_in_wait : RO; bitpos: [2]; default: 0; + * represents the bitscrambler tx core in wait mode to wait write back done + */ + uint32_t tx_in_wait:1; + /** tx_in_pause : RO; bitpos: [3]; default: 0; + * represents the bitscrambler tx core in pause mode + */ + uint32_t tx_in_pause:1; + /** tx_fifo_empty : RO; bitpos: [4]; default: 0; + * represents the bitscrambler tx fifo in empty state + */ + uint32_t tx_fifo_empty:1; + uint32_t reserved_5:11; + /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler tx core when get EOF + */ + uint32_t tx_eof_get_cnt:14; + /** tx_eof_overload : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler tx core + */ + uint32_t tx_eof_overload:1; + /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_tx_eof_overload and + * reg_bitscrambler_tx_eof_get_cnt registers + */ + uint32_t tx_eof_trace_clr:1; + }; + uint32_t val; +} bitscrambler_tx_state_reg_t; + +/** Type of rx_state register + * Status registers + */ +typedef union { + struct { + /** rx_in_idle : RO; bitpos: [0]; default: 1; + * represents the bitscrambler rx core in halt mode + */ + uint32_t rx_in_idle:1; + /** rx_in_run : RO; bitpos: [1]; default: 0; + * represents the bitscrambler rx core in run mode + */ + uint32_t rx_in_run:1; + /** rx_in_wait : RO; bitpos: [2]; default: 0; + * represents the bitscrambler rx core in wait mode to wait write back done + */ + uint32_t rx_in_wait:1; + /** rx_in_pause : RO; bitpos: [3]; default: 0; + * represents the bitscrambler rx core in pause mode + */ + uint32_t rx_in_pause:1; + /** rx_fifo_full : RO; bitpos: [4]; default: 0; + * represents the bitscrambler rx fifo in full state + */ + uint32_t rx_fifo_full:1; + uint32_t reserved_5:11; + /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0; + * represents the bytes numbers of bitscrambler rx core when get EOF + */ + uint32_t rx_eof_get_cnt:14; + /** rx_eof_overload : RO; bitpos: [30]; default: 0; + * represents the some EOFs will be lost for bitscrambler rx core + */ + uint32_t rx_eof_overload:1; + /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0; + * write this bit to clear reg_bitscrambler_rx_eof_overload and + * reg_bitscrambler_rx_eof_get_cnt registers + */ + uint32_t rx_eof_trace_clr:1; + }; + uint32_t val; +} bitscrambler_rx_state_reg_t; + + +/** Group: Version register */ +/** Type of version register + * Control and configuration registers + */ +typedef union { + struct { + /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024; + * Reserved + */ + uint32_t bitscrambler_ver:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} bitscrambler_version_reg_t; + + +typedef struct { + volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0; + volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1; + volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0; + volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1; + volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0; + volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1; + volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0; + volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1; + volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits; + volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits; + volatile bitscrambler_tx_ctrl_reg_t tx_ctrl; + volatile bitscrambler_rx_ctrl_reg_t rx_ctrl; + volatile bitscrambler_tx_state_reg_t tx_state; + volatile bitscrambler_rx_state_reg_t rx_state; + uint32_t reserved_038[48]; + volatile bitscrambler_sys_reg_t sys; + volatile bitscrambler_version_reg_t version; +} bitscrambler_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/include/soc/ecc_mult_reg.h new file mode 100644 index 0000000000..c67c09ab47 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecc_mult_reg.h @@ -0,0 +1,167 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECC_MULT_INT_RAW_REG register + * ECC interrupt raw register, valid in level. + */ +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) +/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +/** ECC_MULT_INT_ST_REG register + * ECC interrupt status register. + */ +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) +/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +/** ECC_MULT_INT_ENA_REG register + * ECC interrupt enable register. + */ +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) +/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +/** ECC_MULT_INT_CLR_REG register + * ECC interrupt clear register. + */ +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) +/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +/** ECC_MULT_CONF_REG register + * ECC configure register + */ +#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) +/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) +#define ECC_MULT_START_V 0x00000001U +#define ECC_MULT_START_S 0 +/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) +#define ECC_MULT_RESET_V 0x00000001U +#define ECC_MULT_RESET_S 1 +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ +#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) +#define ECC_MULT_KEY_LENGTH_V 0x00000001U +#define ECC_MULT_KEY_LENGTH_S 2 +/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0; + * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). + * 1: p(mod base of curve) + */ +#define ECC_MULT_MOD_BASE (BIT(3)) +#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) +#define ECC_MULT_MOD_BASE_V 0x00000001U +#define ECC_MULT_MOD_BASE_S 3 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point + * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point + * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + */ +#define ECC_MULT_WORK_MODE 0x0000000FU +#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) +#define ECC_MULT_WORK_MODE_V 0x0000000FU +#define ECC_MULT_WORK_MODE_S 4 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define ECC_MULT_SECURITY_MODE (BIT(8)) +#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) +#define ECC_MULT_SECURITY_MODE_V 0x00000001U +#define ECC_MULT_SECURITY_MODE_S 8 +/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ +#define ECC_MULT_VERIFICATION_RESULT (BIT(29)) +#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) +#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U +#define ECC_MULT_VERIFICATION_RESULT_S 29 +/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECC_MULT_CLK_EN (BIT(30)) +#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) +#define ECC_MULT_CLK_EN_V 0x00000001U +#define ECC_MULT_CLK_EN_S 30 +/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0; + * ECC memory clock gate force on register + */ +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 + +/** ECC_MULT_DATE_REG register + * Version control register + */ +#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704; + * ECC mult version control register + */ +#define ECC_MULT_DATE 0x0FFFFFFFU +#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) +#define ECC_MULT_DATE_V 0x0FFFFFFFU +#define ECC_MULT_DATE_S 0 + +/** ECC_MULT_K_MEM register + * The memory that stores k. + */ +#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) +#define ECC_MULT_K_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PX_MEM register + * The memory that stores Px. + */ +#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) +#define ECC_MULT_PX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PY_MEM register + * The memory that stores Py. + */ +#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) +#define ECC_MULT_PY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/include/soc/ecc_mult_struct.h new file mode 100644 index 0000000000..a2a02f7f8a --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecc_mult_struct.h @@ -0,0 +1,164 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECC interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_raw_reg_t; + +/** Type of int_st register + * ECC interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_st_reg_t; + +/** Type of int_ena register + * ECC interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_ena_reg_t; + +/** Type of int_clr register + * ECC interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecc_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of conf register + * ECC configure register + */ +typedef union { + struct { + /** start : R/W/SC; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after + * the caculatrion is done. + */ + uint32_t start:1; + /** reset : WT; bitpos: [1]; default: 0; + * Write 1 to reset ECC Accelerator. + */ + uint32_t reset:1; + /** key_length : R/W; bitpos: [2]; default: 0; + * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + */ + uint32_t key_length:1; + /** mod_base : R/W; bitpos: [3]; default: 0; + * The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). + * 1: p(mod base of curve) + */ + uint32_t mod_base:1; + /** work_mode : R/W; bitpos: [7:4]; default: 0; + * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point + * verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point + * Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + * 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + */ + uint32_t work_mode:4; + /** security_mode : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t security_mode:1; + uint32_t reserved_9:20; + /** verification_result : RO/SS; bitpos: [29]; default: 0; + * The verification result bit of ECC Accelerator, only valid when calculation is done. + */ + uint32_t verification_result:1; + /** clk_en : R/W; bitpos: [30]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0; + * ECC memory clock gate force on register + */ + uint32_t mem_clock_gate_force_on:1; + }; + uint32_t val; +} ecc_mult_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * ECC mult version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecc_mult_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile ecc_mult_int_raw_reg_t int_raw; + volatile ecc_mult_int_st_reg_t int_st; + volatile ecc_mult_int_ena_reg_t int_ena; + volatile ecc_mult_int_clr_reg_t int_clr; + volatile ecc_mult_conf_reg_t conf; + uint32_t reserved_020[55]; + volatile ecc_mult_date_reg_t date; + volatile uint32_t k[8]; + volatile uint32_t px[8]; + volatile uint32_t py[8]; +} ecc_mult_dev_t; + +extern ecc_mult_dev_t ECC; + +#ifndef __cplusplus +_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecdsa_reg.h b/components/soc/esp32c5/include/soc/ecdsa_reg.h new file mode 100644 index 0000000000..6e09925e09 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecdsa_reg.h @@ -0,0 +1,318 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECDSA_CONF_REG register + * ECDSA configure register + */ +#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) +/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ +#define ECDSA_WORK_MODE 0x00000003U +#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) +#define ECDSA_WORK_MODE_V 0x00000003U +#define ECDSA_WORK_MODE_S 0 +/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ +#define ECDSA_ECC_CURVE (BIT(2)) +#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) +#define ECDSA_ECC_CURVE_V 0x00000001U +#define ECDSA_ECC_CURVE_S 2 +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ +#define ECDSA_SOFTWARE_SET_K (BIT(3)) +#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) +#define ECDSA_SOFTWARE_SET_K_V 0x00000001U +#define ECDSA_SOFTWARE_SET_K_S 3 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ +#define ECDSA_SOFTWARE_SET_Z (BIT(4)) +#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) +#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U +#define ECDSA_SOFTWARE_SET_Z_S 4 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ +#define ECDSA_DETERMINISTIC_K (BIT(5)) +#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) +#define ECDSA_DETERMINISTIC_K_V 0x00000001U +#define ECDSA_DETERMINISTIC_K_S 5 +/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0; + * The (loop number - 1) value in the deterministic derivation algorithm to derive k. + */ +#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU +#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S) +#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU +#define ECDSA_DETERMINISTIC_LOOP_S 6 + +/** ECDSA_CLK_REG register + * ECDSA clock gate register + */ +#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) +/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) +#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) +#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U +#define ECDSA_CLK_GATE_FORCE_ON_S 0 + +/** ECDSA_INT_RAW_REG register + * ECDSA interrupt raw register, valid in level. + */ +#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) +/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_RAW (BIT(0)) +#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S) +#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U +#define ECDSA_CALC_DONE_INT_RAW_S 0 +/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) +#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_RAW_S 1 + +/** ECDSA_INT_ST_REG register + * ECDSA interrupt status register. + */ +#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) +/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_ST (BIT(0)) +#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S) +#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U +#define ECDSA_CALC_DONE_INT_ST_S 0 +/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ST (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) +#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ST_S 1 + +/** ECDSA_INT_ENA_REG register + * ECDSA interrupt enable register. + */ +#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) +/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_ENA (BIT(0)) +#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S) +#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U +#define ECDSA_CALC_DONE_INT_ENA_S 0 +/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) +#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ENA_S 1 + +/** ECDSA_INT_CLR_REG register + * ECDSA interrupt clear register. + */ +#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) +/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_calc_done_int interrupt + */ +#define ECDSA_CALC_DONE_INT_CLR (BIT(0)) +#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S) +#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U +#define ECDSA_CALC_DONE_INT_CLR_S 0 +/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1)) +#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) +#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_CLR_S 1 + +/** ECDSA_START_REG register + * ECDSA start register + */ +#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) +/** ECDSA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ +#define ECDSA_START (BIT(0)) +#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) +#define ECDSA_START_V 0x00000001U +#define ECDSA_START_S 0 +/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_LOAD_DONE (BIT(1)) +#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) +#define ECDSA_LOAD_DONE_V 0x00000001U +#define ECDSA_LOAD_DONE_S 1 +/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_GET_DONE (BIT(2)) +#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) +#define ECDSA_GET_DONE_V 0x00000001U +#define ECDSA_GET_DONE_S 2 + +/** ECDSA_STATE_REG register + * ECDSA status register + */ +#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) +/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ +#define ECDSA_BUSY 0x00000003U +#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) +#define ECDSA_BUSY_V 0x00000003U +#define ECDSA_BUSY_S 0 + +/** ECDSA_RESULT_REG register + * ECDSA result register + */ +#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) +/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ +#define ECDSA_OPERATION_RESULT (BIT(0)) +#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) +#define ECDSA_OPERATION_RESULT_V 0x00000001U +#define ECDSA_OPERATION_RESULT_S 0 +/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0; + * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the + * curve order, then actually taken k = k mod n. + */ +#define ECDSA_K_VALUE_WARNING (BIT(1)) +#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S) +#define ECDSA_K_VALUE_WARNING_V 0x00000001U +#define ECDSA_K_VALUE_WARNING_S 1 + +/** ECDSA_DATE_REG register + * Version control register + */ +#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656; + * ECDSA version control register + */ +#define ECDSA_DATE 0x0FFFFFFFU +#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) +#define ECDSA_DATE_V 0x0FFFFFFFU +#define ECDSA_DATE_S 0 + +/** ECDSA_SHA_MODE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) +/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ +#define ECDSA_SHA_MODE 0x00000007U +#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) +#define ECDSA_SHA_MODE_V 0x00000007U +#define ECDSA_SHA_MODE_S 0 + +/** ECDSA_SHA_START_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) +/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_START (BIT(0)) +#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) +#define ECDSA_SHA_START_V 0x00000001U +#define ECDSA_SHA_START_S 0 + +/** ECDSA_SHA_CONTINUE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) +/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_CONTINUE (BIT(0)) +#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) +#define ECDSA_SHA_CONTINUE_V 0x00000001U +#define ECDSA_SHA_CONTINUE_S 0 + +/** ECDSA_SHA_BUSY_REG register + * ECDSA status register + */ +#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) +/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ +#define ECDSA_SHA_BUSY (BIT(0)) +#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) +#define ECDSA_SHA_BUSY_V 0x00000001U +#define ECDSA_SHA_BUSY_S 0 + +/** ECDSA_MESSAGE_MEM register + * The memory that stores message. + */ +#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 + +/** ECDSA_R_MEM register + * The memory that stores r. + */ +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00) +#define ECDSA_R_MEM_SIZE_BYTES 32 + +/** ECDSA_S_MEM register + * The memory that stores s. + */ +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20) +#define ECDSA_S_MEM_SIZE_BYTES 32 + +/** ECDSA_Z_MEM register + * The memory that stores software written z. + */ +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40) +#define ECDSA_Z_MEM_SIZE_BYTES 32 + +/** ECDSA_QAX_MEM register + * The memory that stores x coordinates of QA or software written k. + */ +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60) +#define ECDSA_QAX_MEM_SIZE_BYTES 32 + +/** ECDSA_QAY_MEM register + * The memory that stores y coordinates of QA. + */ +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80) +#define ECDSA_QAY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ecdsa_struct.h b/components/soc/esp32c5/include/soc/ecdsa_struct.h new file mode 100644 index 0000000000..1d39f1ad04 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ecdsa_struct.h @@ -0,0 +1,323 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Data Memory */ + +/** Group: Configuration registers */ +/** Type of conf register + * ECDSA configure register + */ +typedef union { + struct { + /** work_mode : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ + uint32_t work_mode:2; + /** ecc_curve : R/W; bitpos: [2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ + uint32_t ecc_curve:1; + /** software_set_k : R/W; bitpos: [3]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ + uint32_t software_set_k:1; + /** software_set_z : R/W; bitpos: [4]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ + uint32_t software_set_z:1; + /** deterministic_k : R/W; bitpos: [5]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ + uint32_t deterministic_k:1; + /** deterministic_loop : R/W; bitpos: [21:6]; default: 0; + * The (loop number - 1) value in the deterministic derivation algorithm to derive k. + */ + uint32_t deterministic_loop:16; + uint32_t reserved_22:10; + }; + uint32_t val; +} ecdsa_conf_reg_t; + +/** Type of start register + * ECDSA start register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ + uint32_t start:1; + /** load_done : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t load_done:1; + /** get_done : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t get_done:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_start_reg_t; + + +/** Group: Clock and reset registers */ +/** Type of clk register + * ECDSA clock gate register + */ +typedef union { + struct { + /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_gate_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECDSA interrupt raw register, valid in level. + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_raw:1; + /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_raw_reg_t; + +/** Type of int_st register + * ECDSA interrupt status register. + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_st:1; + /** sha_release_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_st_reg_t; + +/** Type of int_ena register + * ECDSA interrupt enable register. + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_ena:1; + /** sha_release_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_ena_reg_t; + +/** Type of int_clr register + * ECDSA interrupt clear register. + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_calc_done_int interrupt + */ + uint32_t calc_done_int_clr:1; + /** sha_release_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_int_clr_reg_t; + + +/** Group: Status registers */ +/** Type of state register + * ECDSA status register + */ +typedef union { + struct { + /** busy : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ + uint32_t busy:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * ECDSA result register + */ +typedef union { + struct { + /** operation_result : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ + uint32_t operation_result:1; + /** k_value_warning : RO/SS; bitpos: [1]; default: 0; + * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the + * curve order, then actually taken k = k mod n. + */ + uint32_t k_value_warning:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_result_reg_t; + + +/** Group: SHA register */ +/** Type of sha_mode register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_mode : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ + uint32_t sha_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_sha_mode_reg_t; + +/** Type of sha_start register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_start : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_start_reg_t; + +/** Type of sha_continue register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_continue : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_continue_reg_t; + +/** Type of sha_busy register + * ECDSA status register + */ +typedef union { + struct { + /** sha_busy : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ + uint32_t sha_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_busy_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716656; + * ECDSA version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecdsa_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile ecdsa_conf_reg_t conf; + volatile ecdsa_clk_reg_t clk; + volatile ecdsa_int_raw_reg_t int_raw; + volatile ecdsa_int_st_reg_t int_st; + volatile ecdsa_int_ena_reg_t int_ena; + volatile ecdsa_int_clr_reg_t int_clr; + volatile ecdsa_start_reg_t start; + volatile ecdsa_state_reg_t state; + volatile ecdsa_result_reg_t result; + uint32_t reserved_028[53]; + volatile ecdsa_date_reg_t date; + uint32_t reserved_100[64]; + volatile ecdsa_sha_mode_reg_t sha_mode; + uint32_t reserved_204[3]; + volatile ecdsa_sha_start_reg_t sha_start; + volatile ecdsa_sha_continue_reg_t sha_continue; + volatile ecdsa_sha_busy_reg_t sha_busy; + uint32_t reserved_21c[25]; + volatile uint32_t message[8]; + uint32_t reserved_2a0[472]; + volatile uint32_t r[8]; + volatile uint32_t s[8]; + volatile uint32_t z[8]; + volatile uint32_t qax[8]; + volatile uint32_t qay[8]; +} ecdsa_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/include/soc/gpio_ext_struct.h new file mode 100644 index 0000000000..f4a65cb89c --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_ext_struct.h @@ -0,0 +1,340 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SDM Configure Registers */ +/** Type of sigmadeltan register + * Duty Cycle Configure Register of SDMn + */ +typedef union { + struct { + /** sdn_in : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ + uint32_t sdn_in:8; + /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ + uint32_t sdn_prescale:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_ext_sigmadeltan_reg_t; + +/** Type of sigmadelta_misc register + * MISC Register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** function_clk_en : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ + uint32_t function_clk_en:1; + /** spi_swap : R/W; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t spi_swap:1; + }; + uint32_t val; +} gpio_ext_sigmadelta_misc_reg_t; + + +/** Group: Configure Registers */ +/** Type of pad_comp_config register + * PAD Compare configure Register + */ +typedef union { + struct { + /** xpd_comp : R/W; bitpos: [0]; default: 0; + * Pad compare enable bit. + */ + uint32_t xpd_comp:1; + /** mode_comp : R/W; bitpos: [1]; default: 0; + * 1 to enable external reference from PAD[0]. 0 to enable internal reference, + * meanwhile PAD[0] can be used as a regular GPIO. + */ + uint32_t mode_comp:1; + /** dref_comp : R/W; bitpos: [4:2]; default: 0; + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + */ + uint32_t dref_comp:3; + /** zero_det_mode : R/W; bitpos: [6:5]; default: 0; + * Zero Detect mode select. + */ + uint32_t zero_det_mode:2; + uint32_t reserved_7:25; + }; + uint32_t val; +} gpio_ext_pad_comp_config_reg_t; + +/** Type of pad_comp_filter register + * Zero Detect filter Register + */ +typedef union { + struct { + /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0; + * Zero Detect filter cycle length + */ + uint32_t zero_det_filter_cnt:32; + }; + uint32_t val; +} gpio_ext_pad_comp_filter_reg_t; + + +/** Group: Glitch filter Configure Registers */ +/** Type of glitch_filter_chn register + * Glitch Filter Configure Register of Channeln + */ +typedef union { + struct { + /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ + uint32_t filter_ch0_en:1; + /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ + uint32_t filter_ch0_input_io_num:6; + /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ + uint32_t filter_ch0_window_thres:6; + /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ + uint32_t filter_ch0_window_width:6; + uint32_t reserved_19:13; + }; + uint32_t val; +} gpio_ext_glitch_filter_chn_reg_t; + + +/** Group: Etm Configure Registers */ +/** Type of etm_event_chn_cfg register + * Etm Config register of Channeln + */ +typedef union { + struct { + /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ + uint32_t etm_ch0_event_sel:5; + uint32_t reserved_5:2; + /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ + uint32_t etm_ch0_event_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_ext_etm_event_chn_cfg_reg_t; + +/** Type of etm_task_pn_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio0_en:1; + /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio0_sel:3; + uint32_t reserved_4:4; + /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio1_en:1; + /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio1_sel:3; + uint32_t reserved_12:4; + /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio2_en:1; + /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio2_sel:3; + uint32_t reserved_20:4; + /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio3_en:1; + /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio3_sel:3; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_etm_task_pn_cfg_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * GPIOSD interrupt raw register + */ +typedef union { + struct { + /** comp0_neg_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt raw + */ + uint32_t comp0_neg_int_raw:1; + /** comp0_pos_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt raw + */ + uint32_t comp0_pos_int_raw:1; + /** comp0_all_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt raw + */ + uint32_t comp0_all_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_raw_reg_t; + +/** Type of int_st register + * GPIOSD interrupt masked register + */ +typedef union { + struct { + /** comp0_neg_int_st : RO; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt status + */ + uint32_t comp0_neg_int_st:1; + /** comp0_pos_int_st : RO; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt status + */ + uint32_t comp0_pos_int_st:1; + /** comp0_all_int_st : RO; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt status + */ + uint32_t comp0_all_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_st_reg_t; + +/** Type of int_ena register + * GPIOSD interrupt enable register + */ +typedef union { + struct { + /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1; + * analog comparator pos edge interrupt enable + */ + uint32_t comp0_neg_int_ena:1; + /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1; + * analog comparator neg edge interrupt enable + */ + uint32_t comp0_pos_int_ena:1; + /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1; + * analog comparator neg or pos edge interrupt enable + */ + uint32_t comp0_all_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_ena_reg_t; + +/** Type of int_clr register + * GPIOSD interrupt clear register + */ +typedef union { + struct { + /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt clear + */ + uint32_t comp0_neg_int_clr:1; + /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt clear + */ + uint32_t comp0_pos_int_clr:1; + /** comp0_all_int_clr : WT; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt clear + */ + uint32_t comp0_all_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gpio_ext_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of version register + * Version Control Register + */ +typedef union { + struct { + /** gpio_sd_date : R/W; bitpos: [27:0]; default: 36704513; + * Version control register. + */ + uint32_t gpio_sd_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_ext_version_reg_t; + + +typedef struct gpio_sd_dev_t { + volatile gpio_ext_sigmadeltan_reg_t channel[4]; + uint32_t reserved_010[5]; + volatile gpio_ext_sigmadelta_misc_reg_t misc; +} gpio_sd_dev_t; + +typedef struct gpio_ana_cmpr_dev_t { + volatile gpio_ext_pad_comp_config_reg_t pad_comp_config; + volatile gpio_ext_pad_comp_filter_reg_t pad_comp_filter; +} gpio_ana_cmpr_dev_t; + +typedef struct { + volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + +typedef struct gpio_etm_dev_t { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7]; +} gpio_etm_dev_t; + +typedef struct gpio_ext_dev_t { + volatile gpio_sd_dev_t sigma_delta; + volatile gpio_ana_cmpr_dev_t ana_cmpr; + volatile gpio_glitch_filter_dev_t glitch_filter; + uint32_t reserved_050[4]; + volatile gpio_etm_dev_t etm; + uint32_t reserved_0bc[9]; + volatile gpio_ext_int_raw_reg_t int_raw; + volatile gpio_ext_int_st_reg_t int_st; + volatile gpio_ext_int_ena_reg_t int_ena; + volatile gpio_ext_int_clr_reg_t int_clr; + uint32_t reserved_0f0[3]; + volatile gpio_ext_version_reg_t version; +} gpio_ext_dev_t; + +extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_reg.h b/components/soc/esp32c5/include/soc/gpio_reg.h new file mode 100644 index 0000000000..d0765dd040 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_reg.h @@ -0,0 +1,5727 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_BT_SELECT_REG register + * GPIO bit select register + */ +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ +#define GPIO_BT_SEL 0xFFFFFFFFU +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFFU +#define GPIO_BT_SEL_S 0 + +/** GPIO_OUT_REG register + * GPIO output register for GPIO0-30 + */ +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [30:0]; default: 0; + * GPIO output register for GPIO0-30 + */ +#define GPIO_OUT_DATA_ORIG 0x7FFFFFFFU +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0x7FFFFFFFU +#define GPIO_OUT_DATA_ORIG_S 0 + +/** GPIO_OUT_W1TS_REG register + * GPIO output set register for GPIO0-30 + */ +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/** GPIO_OUT_W1TS : WT; bitpos: [30:0]; default: 0; + * GPIO output set register for GPIO0-30 + */ +#define GPIO_OUT_W1TS 0x7FFFFFFFU +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0x7FFFFFFFU +#define GPIO_OUT_W1TS_S 0 + +/** GPIO_OUT_W1TC_REG register + * GPIO output clear register for GPIO0-30 + */ +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) +/** GPIO_OUT_W1TC : WT; bitpos: [30:0]; default: 0; + * GPIO output clear register for GPIO0-30 + */ +#define GPIO_OUT_W1TC 0x7FFFFFFFU +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0x7FFFFFFFU +#define GPIO_OUT_W1TC_S 0 + +/** GPIO_SDIO_SELECT_REG register + * GPIO sdio select register + */ +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) +/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ +#define GPIO_SDIO_SEL 0x000000FFU +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FFU +#define GPIO_SDIO_SEL_S 0 + +/** GPIO_ENABLE_REG register + * GPIO output enable register for GPIO0-30 + */ +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO output enable register for GPIO0-30 + */ +#define GPIO_ENABLE_DATA 0x7FFFFFFFU +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0x7FFFFFFFU +#define GPIO_ENABLE_DATA_S 0 + +/** GPIO_ENABLE_W1TS_REG register + * GPIO output enable set register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/** GPIO_ENABLE_W1TS : WT; bitpos: [30:0]; default: 0; + * GPIO output enable set register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TS 0x7FFFFFFFU +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0x7FFFFFFFU +#define GPIO_ENABLE_W1TS_S 0 + +/** GPIO_ENABLE_W1TC_REG register + * GPIO output enable clear register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/** GPIO_ENABLE_W1TC : WT; bitpos: [30:0]; default: 0; + * GPIO output enable clear register for GPIO0-30 + */ +#define GPIO_ENABLE_W1TC 0x7FFFFFFFU +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0x7FFFFFFFU +#define GPIO_ENABLE_W1TC_S 0 + +/** GPIO_STRAP_REG register + * pad strapping register + */ +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ +#define GPIO_STRAPPING 0x0000FFFFU +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFFU +#define GPIO_STRAPPING_S 0 + +/** GPIO_IN_REG register + * GPIO input register for GPIO0-30 + */ +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) +/** GPIO_IN_DATA_NEXT : RO; bitpos: [30:0]; default: 0; + * GPIO input register for GPIO0-30 + */ +#define GPIO_IN_DATA_NEXT 0x7FFFFFFFU +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0x7FFFFFFFU +#define GPIO_IN_DATA_NEXT_S 0 + +/** GPIO_STATUS_REG register + * GPIO interrupt status register for GPIO0-30 + */ +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO interrupt status register for GPIO0-30 + */ +#define GPIO_STATUS_INTERRUPT 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_S 0 + +/** GPIO_STATUS_W1TS_REG register + * GPIO interrupt status set register for GPIO0-30 + */ +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_STATUS_W1TS : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status set register for GPIO0-30 + */ +#define GPIO_STATUS_W1TS 0x7FFFFFFFU +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0x7FFFFFFFU +#define GPIO_STATUS_W1TS_S 0 + +/** GPIO_STATUS_W1TC_REG register + * GPIO interrupt status clear register for GPIO0-30 + */ +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) +/** GPIO_STATUS_W1TC : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-30 + */ +#define GPIO_STATUS_W1TC 0x7FFFFFFFU +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0x7FFFFFFFU +#define GPIO_STATUS_W1TC_S 0 + +/** GPIO_PCPU_INT_REG register + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) +/** GPIO_PROCPU_INT : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ +#define GPIO_PROCPU_INT 0x7FFFFFFFU +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0x7FFFFFFFU +#define GPIO_PROCPU_INT_S 0 + +/** GPIO_PCPU_NMI_INT_REG register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/** GPIO_PROCPU_NMI_INT : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ +#define GPIO_PROCPU_NMI_INT 0x7FFFFFFFU +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0x7FFFFFFFU +#define GPIO_PROCPU_NMI_INT_S 0 + +/** GPIO_CPUSDIO_INT_REG register + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/** GPIO_SDIO_INT : RO; bitpos: [30:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ +#define GPIO_SDIO_INT 0x7FFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0x7FFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC2_BYPASS_S 0 +/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN0_PAD_DRIVER_S 2 +/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN0_INT_TYPE 0x00000007U +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007U +#define GPIO_PIN0_INT_TYPE_S 7 +/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN0_CONFIG 0x00000003U +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003U +#define GPIO_PIN0_CONFIG_S 11 +/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN0_INT_ENA 0x0000001FU +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001FU +#define GPIO_PIN0_INT_ENA_S 13 + +/** GPIO_PIN1_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC2_BYPASS_S 0 +/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN1_PAD_DRIVER_S 2 +/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN1_INT_TYPE 0x00000007U +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007U +#define GPIO_PIN1_INT_TYPE_S 7 +/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN1_CONFIG 0x00000003U +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003U +#define GPIO_PIN1_CONFIG_S 11 +/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN1_INT_ENA 0x0000001FU +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001FU +#define GPIO_PIN1_INT_ENA_S 13 + +/** GPIO_PIN2_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) +/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC2_BYPASS_S 0 +/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN2_PAD_DRIVER_S 2 +/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN2_INT_TYPE 0x00000007U +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007U +#define GPIO_PIN2_INT_TYPE_S 7 +/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN2_CONFIG 0x00000003U +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003U +#define GPIO_PIN2_CONFIG_S 11 +/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN2_INT_ENA 0x0000001FU +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001FU +#define GPIO_PIN2_INT_ENA_S 13 + +/** GPIO_PIN3_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC2_BYPASS_S 0 +/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN3_PAD_DRIVER_S 2 +/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN3_INT_TYPE 0x00000007U +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007U +#define GPIO_PIN3_INT_TYPE_S 7 +/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN3_CONFIG 0x00000003U +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003U +#define GPIO_PIN3_CONFIG_S 11 +/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN3_INT_ENA 0x0000001FU +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001FU +#define GPIO_PIN3_INT_ENA_S 13 + +/** GPIO_PIN4_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC2_BYPASS_S 0 +/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN4_PAD_DRIVER_S 2 +/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN4_INT_TYPE 0x00000007U +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007U +#define GPIO_PIN4_INT_TYPE_S 7 +/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN4_CONFIG 0x00000003U +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003U +#define GPIO_PIN4_CONFIG_S 11 +/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN4_INT_ENA 0x0000001FU +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001FU +#define GPIO_PIN4_INT_ENA_S 13 + +/** GPIO_PIN5_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC2_BYPASS_S 0 +/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN5_PAD_DRIVER_S 2 +/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN5_INT_TYPE 0x00000007U +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007U +#define GPIO_PIN5_INT_TYPE_S 7 +/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN5_CONFIG 0x00000003U +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003U +#define GPIO_PIN5_CONFIG_S 11 +/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN5_INT_ENA 0x0000001FU +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001FU +#define GPIO_PIN5_INT_ENA_S 13 + +/** GPIO_PIN6_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) +/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC2_BYPASS_S 0 +/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN6_PAD_DRIVER_S 2 +/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN6_INT_TYPE 0x00000007U +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007U +#define GPIO_PIN6_INT_TYPE_S 7 +/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN6_CONFIG 0x00000003U +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003U +#define GPIO_PIN6_CONFIG_S 11 +/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN6_INT_ENA 0x0000001FU +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001FU +#define GPIO_PIN6_INT_ENA_S 13 + +/** GPIO_PIN7_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC2_BYPASS_S 0 +/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN7_PAD_DRIVER_S 2 +/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN7_INT_TYPE 0x00000007U +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007U +#define GPIO_PIN7_INT_TYPE_S 7 +/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN7_CONFIG 0x00000003U +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003U +#define GPIO_PIN7_CONFIG_S 11 +/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN7_INT_ENA 0x0000001FU +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001FU +#define GPIO_PIN7_INT_ENA_S 13 + +/** GPIO_PIN8_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC2_BYPASS_S 0 +/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN8_PAD_DRIVER_S 2 +/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN8_INT_TYPE 0x00000007U +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007U +#define GPIO_PIN8_INT_TYPE_S 7 +/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN8_CONFIG 0x00000003U +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003U +#define GPIO_PIN8_CONFIG_S 11 +/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN8_INT_ENA 0x0000001FU +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001FU +#define GPIO_PIN8_INT_ENA_S 13 + +/** GPIO_PIN9_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC2_BYPASS_S 0 +/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN9_PAD_DRIVER_S 2 +/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN9_INT_TYPE 0x00000007U +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007U +#define GPIO_PIN9_INT_TYPE_S 7 +/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN9_CONFIG 0x00000003U +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003U +#define GPIO_PIN9_CONFIG_S 11 +/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN9_INT_ENA 0x0000001FU +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001FU +#define GPIO_PIN9_INT_ENA_S 13 + +/** GPIO_PIN10_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) +/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC2_BYPASS_S 0 +/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN10_PAD_DRIVER_S 2 +/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN10_INT_TYPE 0x00000007U +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007U +#define GPIO_PIN10_INT_TYPE_S 7 +/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN10_CONFIG 0x00000003U +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003U +#define GPIO_PIN10_CONFIG_S 11 +/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN10_INT_ENA 0x0000001FU +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001FU +#define GPIO_PIN10_INT_ENA_S 13 + +/** GPIO_PIN11_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) +/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC2_BYPASS_S 0 +/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN11_PAD_DRIVER_S 2 +/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN11_INT_TYPE 0x00000007U +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007U +#define GPIO_PIN11_INT_TYPE_S 7 +/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN11_CONFIG 0x00000003U +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003U +#define GPIO_PIN11_CONFIG_S 11 +/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN11_INT_ENA 0x0000001FU +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001FU +#define GPIO_PIN11_INT_ENA_S 13 + +/** GPIO_PIN12_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) +/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC2_BYPASS_S 0 +/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN12_PAD_DRIVER_S 2 +/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN12_INT_TYPE 0x00000007U +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007U +#define GPIO_PIN12_INT_TYPE_S 7 +/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN12_CONFIG 0x00000003U +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003U +#define GPIO_PIN12_CONFIG_S 11 +/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN12_INT_ENA 0x0000001FU +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001FU +#define GPIO_PIN12_INT_ENA_S 13 + +/** GPIO_PIN13_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC2_BYPASS_S 0 +/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN13_PAD_DRIVER_S 2 +/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN13_INT_TYPE 0x00000007U +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007U +#define GPIO_PIN13_INT_TYPE_S 7 +/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN13_CONFIG 0x00000003U +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003U +#define GPIO_PIN13_CONFIG_S 11 +/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN13_INT_ENA 0x0000001FU +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001FU +#define GPIO_PIN13_INT_ENA_S 13 + +/** GPIO_PIN14_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC2_BYPASS_S 0 +/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN14_PAD_DRIVER_S 2 +/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN14_INT_TYPE 0x00000007U +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007U +#define GPIO_PIN14_INT_TYPE_S 7 +/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN14_CONFIG 0x00000003U +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003U +#define GPIO_PIN14_CONFIG_S 11 +/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN14_INT_ENA 0x0000001FU +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001FU +#define GPIO_PIN14_INT_ENA_S 13 + +/** GPIO_PIN15_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC2_BYPASS_S 0 +/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN15_PAD_DRIVER_S 2 +/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN15_INT_TYPE 0x00000007U +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007U +#define GPIO_PIN15_INT_TYPE_S 7 +/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN15_CONFIG 0x00000003U +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003U +#define GPIO_PIN15_CONFIG_S 11 +/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN15_INT_ENA 0x0000001FU +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001FU +#define GPIO_PIN15_INT_ENA_S 13 + +/** GPIO_PIN16_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) +/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC2_BYPASS_S 0 +/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN16_PAD_DRIVER_S 2 +/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN16_INT_TYPE 0x00000007U +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007U +#define GPIO_PIN16_INT_TYPE_S 7 +/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN16_CONFIG 0x00000003U +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003U +#define GPIO_PIN16_CONFIG_S 11 +/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN16_INT_ENA 0x0000001FU +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001FU +#define GPIO_PIN16_INT_ENA_S 13 + +/** GPIO_PIN17_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) +/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC2_BYPASS_S 0 +/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN17_PAD_DRIVER_S 2 +/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN17_INT_TYPE 0x00000007U +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007U +#define GPIO_PIN17_INT_TYPE_S 7 +/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN17_CONFIG 0x00000003U +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003U +#define GPIO_PIN17_CONFIG_S 11 +/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN17_INT_ENA 0x0000001FU +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001FU +#define GPIO_PIN17_INT_ENA_S 13 + +/** GPIO_PIN18_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) +/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC2_BYPASS_S 0 +/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN18_PAD_DRIVER_S 2 +/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN18_INT_TYPE 0x00000007U +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007U +#define GPIO_PIN18_INT_TYPE_S 7 +/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN18_CONFIG 0x00000003U +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003U +#define GPIO_PIN18_CONFIG_S 11 +/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN18_INT_ENA 0x0000001FU +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001FU +#define GPIO_PIN18_INT_ENA_S 13 + +/** GPIO_PIN19_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) +/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC2_BYPASS_S 0 +/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN19_PAD_DRIVER_S 2 +/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN19_INT_TYPE 0x00000007U +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007U +#define GPIO_PIN19_INT_TYPE_S 7 +/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN19_CONFIG 0x00000003U +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003U +#define GPIO_PIN19_CONFIG_S 11 +/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN19_INT_ENA 0x0000001FU +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001FU +#define GPIO_PIN19_INT_ENA_S 13 + +/** GPIO_PIN20_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC2_BYPASS_S 0 +/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN20_PAD_DRIVER_S 2 +/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN20_INT_TYPE 0x00000007U +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007U +#define GPIO_PIN20_INT_TYPE_S 7 +/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN20_CONFIG 0x00000003U +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003U +#define GPIO_PIN20_CONFIG_S 11 +/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN20_INT_ENA 0x0000001FU +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001FU +#define GPIO_PIN20_INT_ENA_S 13 + +/** GPIO_PIN21_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC2_BYPASS_S 0 +/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN21_PAD_DRIVER_S 2 +/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN21_INT_TYPE 0x00000007U +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007U +#define GPIO_PIN21_INT_TYPE_S 7 +/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN21_CONFIG 0x00000003U +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003U +#define GPIO_PIN21_CONFIG_S 11 +/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN21_INT_ENA 0x0000001FU +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001FU +#define GPIO_PIN21_INT_ENA_S 13 + +/** GPIO_PIN22_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) +/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC2_BYPASS_S 0 +/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN22_PAD_DRIVER_S 2 +/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN22_INT_TYPE 0x00000007U +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007U +#define GPIO_PIN22_INT_TYPE_S 7 +/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN22_CONFIG 0x00000003U +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003U +#define GPIO_PIN22_CONFIG_S 11 +/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN22_INT_ENA 0x0000001FU +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001FU +#define GPIO_PIN22_INT_ENA_S 13 + +/** GPIO_PIN23_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) +/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC2_BYPASS_S 0 +/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN23_PAD_DRIVER_S 2 +/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN23_INT_TYPE 0x00000007U +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007U +#define GPIO_PIN23_INT_TYPE_S 7 +/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN23_CONFIG 0x00000003U +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003U +#define GPIO_PIN23_CONFIG_S 11 +/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN23_INT_ENA 0x0000001FU +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001FU +#define GPIO_PIN23_INT_ENA_S 13 + +/** GPIO_PIN24_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) +/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC2_BYPASS_S 0 +/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN24_PAD_DRIVER_S 2 +/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN24_INT_TYPE 0x00000007U +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007U +#define GPIO_PIN24_INT_TYPE_S 7 +/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN24_CONFIG 0x00000003U +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003U +#define GPIO_PIN24_CONFIG_S 11 +/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN24_INT_ENA 0x0000001FU +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001FU +#define GPIO_PIN24_INT_ENA_S 13 + +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN25_CONFIG 0x00000003U +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003U +#define GPIO_PIN25_CONFIG_S 11 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN26_CONFIG 0x00000003U +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003U +#define GPIO_PIN26_CONFIG_S 11 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN27_CONFIG 0x00000003U +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003U +#define GPIO_PIN27_CONFIG_S 11 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN28_CONFIG 0x00000003U +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003U +#define GPIO_PIN28_CONFIG_S 11 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN29_CONFIG 0x00000003U +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003U +#define GPIO_PIN29_CONFIG_S 11 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 + +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * reserved + */ +#define GPIO_PIN30_CONFIG 0x00000003U +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003U +#define GPIO_PIN30_CONFIG_S 11 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 + +/** GPIO_STATUS_NEXT_REG register + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [30:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ +#define GPIO_STATUS_INTERRUPT_NEXT 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0x7FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** GPIO_FUNC0_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_S 0 +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001U +#define GPIO_SIG0_IN_SEL_S 7 + +/** GPIO_FUNC6_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_S 0 +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001U +#define GPIO_SIG6_IN_SEL_S 7 + +/** GPIO_FUNC7_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_S 0 +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001U +#define GPIO_SIG7_IN_SEL_S 7 + +/** GPIO_FUNC8_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_S 0 +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001U +#define GPIO_SIG8_IN_SEL_S 7 + +/** GPIO_FUNC9_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_S 0 +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001U +#define GPIO_SIG9_IN_SEL_S 7 + +/** GPIO_FUNC10_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_S 0 +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001U +#define GPIO_SIG10_IN_SEL_S 7 + +/** GPIO_FUNC11_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_S 0 +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001U +#define GPIO_SIG11_IN_SEL_S 7 + +/** GPIO_FUNC12_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_S 0 +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001U +#define GPIO_SIG12_IN_SEL_S 7 + +/** GPIO_FUNC13_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_S 0 +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001U +#define GPIO_SIG13_IN_SEL_S 7 + +/** GPIO_FUNC14_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_S 0 +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001U +#define GPIO_SIG14_IN_SEL_S 7 + +/** GPIO_FUNC15_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_S 0 +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001U +#define GPIO_SIG15_IN_SEL_S 7 + +/** GPIO_FUNC16_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_S 0 +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001U +#define GPIO_SIG16_IN_SEL_S 7 + +/** GPIO_FUNC17_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_S 0 +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001U +#define GPIO_SIG17_IN_SEL_S 7 + +/** GPIO_FUNC19_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) +/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC19_IN_SEL 0x0000003FU +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003FU +#define GPIO_FUNC19_IN_SEL_S 0 +/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001U +#define GPIO_SIG19_IN_SEL_S 7 + +/** GPIO_FUNC21_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) +/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC21_IN_SEL 0x0000003FU +#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) +#define GPIO_FUNC21_IN_SEL_V 0x0000003FU +#define GPIO_FUNC21_IN_SEL_S 0 +/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) +#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) +#define GPIO_SIG21_IN_SEL_V 0x00000001U +#define GPIO_SIG21_IN_SEL_S 7 + +/** GPIO_FUNC22_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) +/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC22_IN_SEL 0x0000003FU +#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) +#define GPIO_FUNC22_IN_SEL_V 0x0000003FU +#define GPIO_FUNC22_IN_SEL_S 0 +/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) +#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) +#define GPIO_SIG22_IN_SEL_V 0x00000001U +#define GPIO_SIG22_IN_SEL_S 7 + +/** GPIO_FUNC23_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) +/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC23_IN_SEL 0x0000003FU +#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) +#define GPIO_FUNC23_IN_SEL_V 0x0000003FU +#define GPIO_FUNC23_IN_SEL_S 0 +/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) +#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) +#define GPIO_SIG23_IN_SEL_V 0x00000001U +#define GPIO_SIG23_IN_SEL_S 7 + +/** GPIO_FUNC24_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) +/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC24_IN_SEL 0x0000003FU +#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) +#define GPIO_FUNC24_IN_SEL_V 0x0000003FU +#define GPIO_FUNC24_IN_SEL_S 0 +/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) +#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) +#define GPIO_SIG24_IN_SEL_V 0x00000001U +#define GPIO_SIG24_IN_SEL_S 7 + +/** GPIO_FUNC28_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_S 0 +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001U +#define GPIO_SIG28_IN_SEL_S 7 + +/** GPIO_FUNC29_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_S 0 +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001U +#define GPIO_SIG29_IN_SEL_S 7 + +/** GPIO_FUNC30_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_S 0 +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001U +#define GPIO_SIG30_IN_SEL_S 7 + +/** GPIO_FUNC31_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_S 0 +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001U +#define GPIO_SIG31_IN_SEL_S 7 + +/** GPIO_FUNC32_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_S 0 +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001U +#define GPIO_SIG32_IN_SEL_S 7 + +/** GPIO_FUNC33_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_S 0 +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001U +#define GPIO_SIG33_IN_SEL_S 7 + +/** GPIO_FUNC34_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_S 0 +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001U +#define GPIO_SIG34_IN_SEL_S 7 + +/** GPIO_FUNC35_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_S 0 +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001U +#define GPIO_SIG35_IN_SEL_S 7 + +/** GPIO_FUNC40_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) +/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC40_IN_SEL 0x0000003FU +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003FU +#define GPIO_FUNC40_IN_SEL_S 0 +/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001U +#define GPIO_SIG40_IN_SEL_S 7 + +/** GPIO_FUNC41_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_S 0 +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001U +#define GPIO_SIG41_IN_SEL_S 7 + +/** GPIO_FUNC42_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_S 0 +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001U +#define GPIO_SIG42_IN_SEL_S 7 + +/** GPIO_FUNC45_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC45_IN_SEL 0x0000003FU +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003FU +#define GPIO_FUNC45_IN_SEL_S 0 +/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001U +#define GPIO_SIG45_IN_SEL_S 7 + +/** GPIO_FUNC46_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_S 0 +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001U +#define GPIO_SIG46_IN_SEL_S 7 + +/** GPIO_FUNC47_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_S 0 +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001U +#define GPIO_SIG47_IN_SEL_S 7 + +/** GPIO_FUNC48_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC48_IN_SEL 0x0000003FU +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003FU +#define GPIO_FUNC48_IN_SEL_S 0 +/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001U +#define GPIO_SIG48_IN_SEL_S 7 + +/** GPIO_FUNC49_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC49_IN_SEL 0x0000003FU +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003FU +#define GPIO_FUNC49_IN_SEL_S 0 +/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001U +#define GPIO_SIG49_IN_SEL_S 7 + +/** GPIO_FUNC50_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) +/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC50_IN_SEL 0x0000003FU +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003FU +#define GPIO_FUNC50_IN_SEL_S 0 +/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001U +#define GPIO_SIG50_IN_SEL_S 7 + +/** GPIO_FUNC51_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC51_IN_SEL 0x0000003FU +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003FU +#define GPIO_FUNC51_IN_SEL_S 0 +/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001U +#define GPIO_SIG51_IN_SEL_S 7 + +/** GPIO_FUNC52_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC52_IN_SEL 0x0000003FU +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003FU +#define GPIO_FUNC52_IN_SEL_S 0 +/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001U +#define GPIO_SIG52_IN_SEL_S 7 + +/** GPIO_FUNC53_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC53_IN_SEL 0x0000003FU +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003FU +#define GPIO_FUNC53_IN_SEL_S 0 +/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001U +#define GPIO_SIG53_IN_SEL_S 7 + +/** GPIO_FUNC54_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) +/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC54_IN_SEL 0x0000003FU +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003FU +#define GPIO_FUNC54_IN_SEL_S 0 +/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001U +#define GPIO_SIG54_IN_SEL_S 7 + +/** GPIO_FUNC63_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC63_IN_SEL 0x0000003FU +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003FU +#define GPIO_FUNC63_IN_SEL_S 0 +/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001U +#define GPIO_SIG63_IN_SEL_S 7 + +/** GPIO_FUNC64_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_S 0 +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001U +#define GPIO_SIG64_IN_SEL_S 7 + +/** GPIO_FUNC65_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_S 0 +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001U +#define GPIO_SIG65_IN_SEL_S 7 + +/** GPIO_FUNC66_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_S 0 +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001U +#define GPIO_SIG66_IN_SEL_S 7 + +/** GPIO_FUNC67_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_S 0 +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001U +#define GPIO_SIG67_IN_SEL_S 7 + +/** GPIO_FUNC68_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_S 0 +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001U +#define GPIO_SIG68_IN_SEL_S 7 + +/** GPIO_FUNC69_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_S 0 +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001U +#define GPIO_SIG69_IN_SEL_S 7 + +/** GPIO_FUNC70_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) +/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC70_IN_SEL 0x0000003FU +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003FU +#define GPIO_FUNC70_IN_SEL_S 0 +/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001U +#define GPIO_SIG70_IN_SEL_S 7 + +/** GPIO_FUNC71_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC71_IN_SEL 0x0000003FU +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003FU +#define GPIO_FUNC71_IN_SEL_S 0 +/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001U +#define GPIO_SIG71_IN_SEL_S 7 + +/** GPIO_FUNC72_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_S 0 +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001U +#define GPIO_SIG72_IN_SEL_S 7 + +/** GPIO_FUNC73_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_S 0 +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001U +#define GPIO_SIG73_IN_SEL_S 7 + +/** GPIO_FUNC77_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC77_IN_SEL 0x0000003FU +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000003FU +#define GPIO_FUNC77_IN_SEL_S 0 +/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001U +#define GPIO_SIG77_IN_SEL_S 7 + +/** GPIO_FUNC81_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC81_IN_SEL 0x0000003FU +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003FU +#define GPIO_FUNC81_IN_SEL_S 0 +/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001U +#define GPIO_SIG81_IN_SEL_S 7 + +/** GPIO_FUNC82_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_S 0 +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001U +#define GPIO_SIG82_IN_SEL_S 7 + +/** GPIO_FUNC83_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC83_IN_SEL 0x0000003FU +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000003FU +#define GPIO_FUNC83_IN_SEL_S 0 +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001U +#define GPIO_SIG83_IN_SEL_S 7 + +/** GPIO_FUNC84_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) +/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC84_IN_SEL 0x0000003FU +#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) +#define GPIO_FUNC84_IN_SEL_V 0x0000003FU +#define GPIO_FUNC84_IN_SEL_S 0 +/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) +#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/** GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) +#define GPIO_SIG84_IN_SEL_V 0x00000001U +#define GPIO_SIG84_IN_SEL_S 7 + +/** GPIO_FUNC85_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) +/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC85_IN_SEL 0x0000003FU +#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) +#define GPIO_FUNC85_IN_SEL_V 0x0000003FU +#define GPIO_FUNC85_IN_SEL_S 0 +/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) +#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/** GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) +#define GPIO_SIG85_IN_SEL_V 0x00000001U +#define GPIO_SIG85_IN_SEL_S 7 + +/** GPIO_FUNC86_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) +/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC86_IN_SEL 0x0000003FU +#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) +#define GPIO_FUNC86_IN_SEL_V 0x0000003FU +#define GPIO_FUNC86_IN_SEL_S 0 +/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) +#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) +#define GPIO_SIG86_IN_SEL_V 0x00000001U +#define GPIO_SIG86_IN_SEL_S 7 + +/** GPIO_FUNC87_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) +/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC87_IN_SEL 0x0000003FU +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003FU +#define GPIO_FUNC87_IN_SEL_S 0 +/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001U +#define GPIO_SIG87_IN_SEL_S 7 + +/** GPIO_FUNC88_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) +/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC88_IN_SEL 0x0000003FU +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003FU +#define GPIO_FUNC88_IN_SEL_S 0 +/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001U +#define GPIO_SIG88_IN_SEL_S 7 + +/** GPIO_FUNC89_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) +/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC89_IN_SEL 0x0000003FU +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003FU +#define GPIO_FUNC89_IN_SEL_S 0 +/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001U +#define GPIO_SIG89_IN_SEL_S 7 + +/** GPIO_FUNC90_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) +/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC90_IN_SEL 0x0000003FU +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003FU +#define GPIO_FUNC90_IN_SEL_S 0 +/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001U +#define GPIO_SIG90_IN_SEL_S 7 + +/** GPIO_FUNC91_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) +/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC91_IN_SEL 0x0000003FU +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003FU +#define GPIO_FUNC91_IN_SEL_S 0 +/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001U +#define GPIO_SIG91_IN_SEL_S 7 + +/** GPIO_FUNC92_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) +/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC92_IN_SEL 0x0000003FU +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003FU +#define GPIO_FUNC92_IN_SEL_S 0 +/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001U +#define GPIO_SIG92_IN_SEL_S 7 + +/** GPIO_FUNC93_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) +/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC93_IN_SEL 0x0000003FU +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003FU +#define GPIO_FUNC93_IN_SEL_S 0 +/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001U +#define GPIO_SIG93_IN_SEL_S 7 + +/** GPIO_FUNC94_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) +/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC94_IN_SEL 0x0000003FU +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003FU +#define GPIO_FUNC94_IN_SEL_S 0 +/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001U +#define GPIO_SIG94_IN_SEL_S 7 + +/** GPIO_FUNC95_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) +/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC95_IN_SEL 0x0000003FU +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003FU +#define GPIO_FUNC95_IN_SEL_S 0 +/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001U +#define GPIO_SIG95_IN_SEL_S 7 + +/** GPIO_FUNC97_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_S 0 +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001U +#define GPIO_SIG97_IN_SEL_S 7 + +/** GPIO_FUNC98_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_S 0 +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001U +#define GPIO_SIG98_IN_SEL_S 7 + +/** GPIO_FUNC99_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_S 0 +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001U +#define GPIO_SIG99_IN_SEL_S 7 + +/** GPIO_FUNC100_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_S 0 +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001U +#define GPIO_SIG100_IN_SEL_S 7 + +/** GPIO_FUNC101_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) +/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC101_IN_SEL 0x0000003FU +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003FU +#define GPIO_FUNC101_IN_SEL_S 0 +/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001U +#define GPIO_SIG101_IN_SEL_S 7 + +/** GPIO_FUNC102_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC102_IN_SEL 0x0000003FU +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003FU +#define GPIO_FUNC102_IN_SEL_S 0 +/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001U +#define GPIO_SIG102_IN_SEL_S 7 + +/** GPIO_FUNC103_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC103_IN_SEL 0x0000003FU +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003FU +#define GPIO_FUNC103_IN_SEL_S 0 +/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001U +#define GPIO_SIG103_IN_SEL_S 7 + +/** GPIO_FUNC104_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC104_IN_SEL 0x0000003FU +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003FU +#define GPIO_FUNC104_IN_SEL_S 0 +/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001U +#define GPIO_SIG104_IN_SEL_S 7 + +/** GPIO_FUNC105_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC105_IN_SEL 0x0000003FU +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003FU +#define GPIO_FUNC105_IN_SEL_S 0 +/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001U +#define GPIO_SIG105_IN_SEL_S 7 + +/** GPIO_FUNC106_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC106_IN_SEL 0x0000003FU +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003FU +#define GPIO_FUNC106_IN_SEL_S 0 +/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001U +#define GPIO_SIG106_IN_SEL_S 7 + +/** GPIO_FUNC107_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC107_IN_SEL 0x0000003FU +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003FU +#define GPIO_FUNC107_IN_SEL_S 0 +/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001U +#define GPIO_SIG107_IN_SEL_S 7 + +/** GPIO_FUNC108_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC108_IN_SEL 0x0000003FU +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003FU +#define GPIO_FUNC108_IN_SEL_S 0 +/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001U +#define GPIO_SIG108_IN_SEL_S 7 + +/** GPIO_FUNC109_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC109_IN_SEL 0x0000003FU +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003FU +#define GPIO_FUNC109_IN_SEL_S 0 +/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001U +#define GPIO_SIG109_IN_SEL_S 7 + +/** GPIO_FUNC110_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC110_IN_SEL 0x0000003FU +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003FU +#define GPIO_FUNC110_IN_SEL_S 0 +/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001U +#define GPIO_SIG110_IN_SEL_S 7 + +/** GPIO_FUNC111_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC111_IN_SEL 0x0000003FU +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003FU +#define GPIO_FUNC111_IN_SEL_S 0 +/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001U +#define GPIO_SIG111_IN_SEL_S 7 + +/** GPIO_FUNC112_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC112_IN_SEL 0x0000003FU +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003FU +#define GPIO_FUNC112_IN_SEL_S 0 +/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001U +#define GPIO_SIG112_IN_SEL_S 7 + +/** GPIO_FUNC113_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC113_IN_SEL 0x0000003FU +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003FU +#define GPIO_FUNC113_IN_SEL_S 0 +/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001U +#define GPIO_SIG113_IN_SEL_S 7 + +/** GPIO_FUNC114_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) +/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC114_IN_SEL 0x0000003FU +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003FU +#define GPIO_FUNC114_IN_SEL_S 0 +/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001U +#define GPIO_SIG114_IN_SEL_S 7 + +/** GPIO_FUNC115_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC115_IN_SEL 0x0000003FU +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003FU +#define GPIO_FUNC115_IN_SEL_S 0 +/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001U +#define GPIO_SIG115_IN_SEL_S 7 + +/** GPIO_FUNC116_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC116_IN_SEL 0x0000003FU +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003FU +#define GPIO_FUNC116_IN_SEL_S 0 +/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001U +#define GPIO_SIG116_IN_SEL_S 7 + +/** GPIO_FUNC117_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC117_IN_SEL 0x0000003FU +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003FU +#define GPIO_FUNC117_IN_SEL_S 0 +/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001U +#define GPIO_SIG117_IN_SEL_S 7 + +/** GPIO_FUNC118_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_S 0 +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001U +#define GPIO_SIG118_IN_SEL_S 7 + +/** GPIO_FUNC119_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_S 0 +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001U +#define GPIO_SIG119_IN_SEL_S 7 + +/** GPIO_FUNC120_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_S 0 +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001U +#define GPIO_SIG120_IN_SEL_S 7 + +/** GPIO_FUNC121_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_S 0 +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001U +#define GPIO_SIG121_IN_SEL_S 7 + +/** GPIO_FUNC122_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) +/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC122_IN_SEL 0x0000003FU +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003FU +#define GPIO_FUNC122_IN_SEL_S 0 +/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001U +#define GPIO_SIG122_IN_SEL_S 7 + +/** GPIO_FUNC123_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC123_IN_SEL 0x0000003FU +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003FU +#define GPIO_FUNC123_IN_SEL_S 0 +/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001U +#define GPIO_SIG123_IN_SEL_S 7 + +/** GPIO_FUNC124_IN_SEL_CFG_REG register + * GPIO input function configuration register + */ +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ +#define GPIO_FUNC124_IN_SEL 0x0000003FU +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003FU +#define GPIO_FUNC124_IN_SEL_S 0 +/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001U +#define GPIO_SIG124_IN_SEL_S 7 + +/** GPIO_FUNC0_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC0_OUT_SEL 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC0_OUT_SEL_S 0 +/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OUT_INV_SEL_S 8 +/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_SEL_S 9 +/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC0_OEN_INV_SEL_S 10 + +/** GPIO_FUNC1_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC1_OUT_SEL 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC1_OUT_SEL_S 0 +/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OUT_INV_SEL_S 8 +/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_SEL_S 9 +/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC1_OEN_INV_SEL_S 10 + +/** GPIO_FUNC2_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) +/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC2_OUT_SEL 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC2_OUT_SEL_S 0 +/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OUT_INV_SEL_S 8 +/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_SEL_S 9 +/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC2_OEN_INV_SEL_S 10 + +/** GPIO_FUNC3_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC3_OUT_SEL 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC3_OUT_SEL_S 0 +/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OUT_INV_SEL_S 8 +/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_SEL_S 9 +/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC3_OEN_INV_SEL_S 10 + +/** GPIO_FUNC4_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC4_OUT_SEL 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC4_OUT_SEL_S 0 +/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OUT_INV_SEL_S 8 +/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_SEL_S 9 +/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC4_OEN_INV_SEL_S 10 + +/** GPIO_FUNC5_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC5_OUT_SEL 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC5_OUT_SEL_S 0 +/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OUT_INV_SEL_S 8 +/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_SEL_S 9 +/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC5_OEN_INV_SEL_S 10 + +/** GPIO_FUNC6_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) +/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC6_OUT_SEL 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC6_OUT_SEL_S 0 +/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OUT_INV_SEL_S 8 +/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_SEL_S 9 +/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC6_OEN_INV_SEL_S 10 + +/** GPIO_FUNC7_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC7_OUT_SEL 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC7_OUT_SEL_S 0 +/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OUT_INV_SEL_S 8 +/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_SEL_S 9 +/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC7_OEN_INV_SEL_S 10 + +/** GPIO_FUNC8_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC8_OUT_SEL 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC8_OUT_SEL_S 0 +/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OUT_INV_SEL_S 8 +/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_SEL_S 9 +/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC8_OEN_INV_SEL_S 10 + +/** GPIO_FUNC9_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC9_OUT_SEL 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC9_OUT_SEL_S 0 +/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OUT_INV_SEL_S 8 +/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_SEL_S 9 +/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC9_OEN_INV_SEL_S 10 + +/** GPIO_FUNC10_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) +/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC10_OUT_SEL 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC10_OUT_SEL_S 0 +/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OUT_INV_SEL_S 8 +/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_SEL_S 9 +/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC10_OEN_INV_SEL_S 10 + +/** GPIO_FUNC11_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC11_OUT_SEL 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC11_OUT_SEL_S 0 +/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OUT_INV_SEL_S 8 +/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_SEL_S 9 +/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC11_OEN_INV_SEL_S 10 + +/** GPIO_FUNC12_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC12_OUT_SEL 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC12_OUT_SEL_S 0 +/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OUT_INV_SEL_S 8 +/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_SEL_S 9 +/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC12_OEN_INV_SEL_S 10 + +/** GPIO_FUNC13_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC13_OUT_SEL 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC13_OUT_SEL_S 0 +/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OUT_INV_SEL_S 8 +/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_SEL_S 9 +/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC13_OEN_INV_SEL_S 10 + +/** GPIO_FUNC14_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) +/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC14_OUT_SEL 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC14_OUT_SEL_S 0 +/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OUT_INV_SEL_S 8 +/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_SEL_S 9 +/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC14_OEN_INV_SEL_S 10 + +/** GPIO_FUNC15_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC15_OUT_SEL 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC15_OUT_SEL_S 0 +/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OUT_INV_SEL_S 8 +/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_SEL_S 9 +/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC15_OEN_INV_SEL_S 10 + +/** GPIO_FUNC16_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC16_OUT_SEL 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC16_OUT_SEL_S 0 +/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OUT_INV_SEL_S 8 +/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_SEL_S 9 +/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC16_OEN_INV_SEL_S 10 + +/** GPIO_FUNC17_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC17_OUT_SEL 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC17_OUT_SEL_S 0 +/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OUT_INV_SEL_S 8 +/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_SEL_S 9 +/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC17_OEN_INV_SEL_S 10 + +/** GPIO_FUNC18_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) +/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC18_OUT_SEL 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC18_OUT_SEL_S 0 +/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OUT_INV_SEL_S 8 +/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_SEL_S 9 +/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC18_OEN_INV_SEL_S 10 + +/** GPIO_FUNC19_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) +/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC19_OUT_SEL 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC19_OUT_SEL_S 0 +/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OUT_INV_SEL_S 8 +/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_SEL_S 9 +/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC19_OEN_INV_SEL_S 10 + +/** GPIO_FUNC20_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) +/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC20_OUT_SEL 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC20_OUT_SEL_S 0 +/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OUT_INV_SEL_S 8 +/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_SEL_S 9 +/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC20_OEN_INV_SEL_S 10 + +/** GPIO_FUNC21_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) +/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC21_OUT_SEL 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC21_OUT_SEL_S 0 +/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OUT_INV_SEL_S 8 +/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_SEL_S 9 +/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC21_OEN_INV_SEL_S 10 + +/** GPIO_FUNC22_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) +/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC22_OUT_SEL 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC22_OUT_SEL_S 0 +/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OUT_INV_SEL_S 8 +/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_SEL_S 9 +/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC22_OEN_INV_SEL_S 10 + +/** GPIO_FUNC23_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) +/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC23_OUT_SEL 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC23_OUT_SEL_S 0 +/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OUT_INV_SEL_S 8 +/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_SEL_S 9 +/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC23_OEN_INV_SEL_S 10 + +/** GPIO_FUNC24_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) +/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC24_OUT_SEL 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC24_OUT_SEL_S 0 +/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OUT_INV_SEL_S 8 +/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_SEL_S 9 +/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC24_OEN_INV_SEL_S 10 + +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 8 +/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_SEL_S 9 +/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OEN_INV_SEL_S 10 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_SEL_S 9 +/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OEN_INV_SEL_S 10 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_SEL_S 9 +/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OEN_INV_SEL_S 10 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_SEL_S 9 +/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OEN_INV_SEL_S 10 + +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) +/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_SEL_S 9 +/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OEN_INV_SEL_S 10 + +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) +/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000000FFU +#define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 8 +/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OEN_SEL (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_SEL_S 9 +/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OEN_INV_SEL_S 10 + +/** GPIO_CLOCK_GATE_REG register + * GPIO clock gate register + */ +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) +/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001U +#define GPIO_CLK_EN_S 0 + +/** GPIO_DATE_REG register + * GPIO version register + */ +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 36704512; + * version register + */ +#define GPIO_DATE 0x0FFFFFFFU +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFFU +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_apm_reg.h b/components/soc/esp32c5/include/soc/hp_apm_reg.h new file mode 100644 index 0000000000..5779eea6fa --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_apm_reg.h @@ -0,0 +1,1950 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) +/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ +#define HP_APM_REGION_FILTER_EN 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) +#define HP_APM_REGION_FILTER_EN_V 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_S 0 + +/** HP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) +/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) +#define HP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_S 0 + +/** HP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) +/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) +#define HP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_S 0 + +/** HP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) +/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_X (BIT(0)) +#define HP_APM_REGION0_R0_PMS_X_M (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S) +#define HP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_X_S 0 +/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_W (BIT(1)) +#define HP_APM_REGION0_R0_PMS_W_M (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S) +#define HP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_W_S 1 +/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION0_R0_PMS_R (BIT(2)) +#define HP_APM_REGION0_R0_PMS_R_M (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S) +#define HP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R0_PMS_R_S 2 +/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_X (BIT(4)) +#define HP_APM_REGION0_R1_PMS_X_M (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S) +#define HP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_X_S 4 +/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_W (BIT(5)) +#define HP_APM_REGION0_R1_PMS_W_M (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S) +#define HP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_W_S 5 +/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION0_R1_PMS_R (BIT(6)) +#define HP_APM_REGION0_R1_PMS_R_M (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S) +#define HP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R1_PMS_R_S 6 +/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_X (BIT(8)) +#define HP_APM_REGION0_R2_PMS_X_M (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S) +#define HP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_X_S 8 +/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_W (BIT(9)) +#define HP_APM_REGION0_R2_PMS_W_M (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S) +#define HP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_W_S 9 +/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION0_R2_PMS_R (BIT(10)) +#define HP_APM_REGION0_R2_PMS_R_M (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S) +#define HP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION0_R2_PMS_R_S 10 +/** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION0_LOCK (BIT(11)) +#define HP_APM_REGION0_LOCK_M (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S) +#define HP_APM_REGION0_LOCK_V 0x00000001U +#define HP_APM_REGION0_LOCK_S 11 + +/** HP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) +/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) +#define HP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_S 0 + +/** HP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) +/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) +#define HP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_S 0 + +/** HP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) +/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_X (BIT(0)) +#define HP_APM_REGION1_R0_PMS_X_M (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S) +#define HP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_X_S 0 +/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_W (BIT(1)) +#define HP_APM_REGION1_R0_PMS_W_M (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S) +#define HP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_W_S 1 +/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION1_R0_PMS_R (BIT(2)) +#define HP_APM_REGION1_R0_PMS_R_M (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S) +#define HP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R0_PMS_R_S 2 +/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_X (BIT(4)) +#define HP_APM_REGION1_R1_PMS_X_M (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S) +#define HP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_X_S 4 +/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_W (BIT(5)) +#define HP_APM_REGION1_R1_PMS_W_M (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S) +#define HP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_W_S 5 +/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION1_R1_PMS_R (BIT(6)) +#define HP_APM_REGION1_R1_PMS_R_M (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S) +#define HP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R1_PMS_R_S 6 +/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_X (BIT(8)) +#define HP_APM_REGION1_R2_PMS_X_M (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S) +#define HP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_X_S 8 +/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_W (BIT(9)) +#define HP_APM_REGION1_R2_PMS_W_M (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S) +#define HP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_W_S 9 +/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION1_R2_PMS_R (BIT(10)) +#define HP_APM_REGION1_R2_PMS_R_M (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S) +#define HP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION1_R2_PMS_R_S 10 +/** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ +#define HP_APM_REGION1_LOCK (BIT(11)) +#define HP_APM_REGION1_LOCK_M (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S) +#define HP_APM_REGION1_LOCK_V 0x00000001U +#define HP_APM_REGION1_LOCK_S 11 + +/** HP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) +/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) +#define HP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_S 0 + +/** HP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) +/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) +#define HP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_S 0 + +/** HP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) +/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_X (BIT(0)) +#define HP_APM_REGION2_R0_PMS_X_M (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S) +#define HP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_X_S 0 +/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_W (BIT(1)) +#define HP_APM_REGION2_R0_PMS_W_M (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S) +#define HP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_W_S 1 +/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION2_R0_PMS_R (BIT(2)) +#define HP_APM_REGION2_R0_PMS_R_M (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S) +#define HP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R0_PMS_R_S 2 +/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_X (BIT(4)) +#define HP_APM_REGION2_R1_PMS_X_M (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S) +#define HP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_X_S 4 +/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_W (BIT(5)) +#define HP_APM_REGION2_R1_PMS_W_M (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S) +#define HP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_W_S 5 +/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION2_R1_PMS_R (BIT(6)) +#define HP_APM_REGION2_R1_PMS_R_M (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S) +#define HP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R1_PMS_R_S 6 +/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_X (BIT(8)) +#define HP_APM_REGION2_R2_PMS_X_M (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S) +#define HP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_X_S 8 +/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_W (BIT(9)) +#define HP_APM_REGION2_R2_PMS_W_M (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S) +#define HP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_W_S 9 +/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION2_R2_PMS_R (BIT(10)) +#define HP_APM_REGION2_R2_PMS_R_M (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S) +#define HP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION2_R2_PMS_R_S 10 +/** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ +#define HP_APM_REGION2_LOCK (BIT(11)) +#define HP_APM_REGION2_LOCK_M (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S) +#define HP_APM_REGION2_LOCK_V 0x00000001U +#define HP_APM_REGION2_LOCK_S 11 + +/** HP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) +/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) +#define HP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_S 0 + +/** HP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) +/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) +#define HP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_S 0 + +/** HP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) +/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_X (BIT(0)) +#define HP_APM_REGION3_R0_PMS_X_M (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S) +#define HP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_X_S 0 +/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_W (BIT(1)) +#define HP_APM_REGION3_R0_PMS_W_M (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S) +#define HP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_W_S 1 +/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION3_R0_PMS_R (BIT(2)) +#define HP_APM_REGION3_R0_PMS_R_M (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S) +#define HP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R0_PMS_R_S 2 +/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_X (BIT(4)) +#define HP_APM_REGION3_R1_PMS_X_M (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S) +#define HP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_X_S 4 +/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_W (BIT(5)) +#define HP_APM_REGION3_R1_PMS_W_M (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S) +#define HP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_W_S 5 +/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION3_R1_PMS_R (BIT(6)) +#define HP_APM_REGION3_R1_PMS_R_M (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S) +#define HP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R1_PMS_R_S 6 +/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_X (BIT(8)) +#define HP_APM_REGION3_R2_PMS_X_M (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S) +#define HP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_X_S 8 +/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_W (BIT(9)) +#define HP_APM_REGION3_R2_PMS_W_M (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S) +#define HP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_W_S 9 +/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION3_R2_PMS_R (BIT(10)) +#define HP_APM_REGION3_R2_PMS_R_M (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S) +#define HP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION3_R2_PMS_R_S 10 +/** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ +#define HP_APM_REGION3_LOCK (BIT(11)) +#define HP_APM_REGION3_LOCK_M (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S) +#define HP_APM_REGION3_LOCK_V 0x00000001U +#define HP_APM_REGION3_LOCK_S 11 + +/** HP_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) +/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ +#define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) +#define HP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_S 0 + +/** HP_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) +/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ +#define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) +#define HP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_S 0 + +/** HP_APM_REGION4_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) +/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_X (BIT(0)) +#define HP_APM_REGION4_R0_PMS_X_M (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S) +#define HP_APM_REGION4_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_X_S 0 +/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_W (BIT(1)) +#define HP_APM_REGION4_R0_PMS_W_M (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S) +#define HP_APM_REGION4_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_W_S 1 +/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION4_R0_PMS_R (BIT(2)) +#define HP_APM_REGION4_R0_PMS_R_M (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S) +#define HP_APM_REGION4_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R0_PMS_R_S 2 +/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_X (BIT(4)) +#define HP_APM_REGION4_R1_PMS_X_M (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S) +#define HP_APM_REGION4_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_X_S 4 +/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_W (BIT(5)) +#define HP_APM_REGION4_R1_PMS_W_M (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S) +#define HP_APM_REGION4_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_W_S 5 +/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION4_R1_PMS_R (BIT(6)) +#define HP_APM_REGION4_R1_PMS_R_M (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S) +#define HP_APM_REGION4_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R1_PMS_R_S 6 +/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_X (BIT(8)) +#define HP_APM_REGION4_R2_PMS_X_M (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S) +#define HP_APM_REGION4_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_X_S 8 +/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_W (BIT(9)) +#define HP_APM_REGION4_R2_PMS_W_M (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S) +#define HP_APM_REGION4_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_W_S 9 +/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION4_R2_PMS_R (BIT(10)) +#define HP_APM_REGION4_R2_PMS_R_M (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S) +#define HP_APM_REGION4_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION4_R2_PMS_R_S 10 +/** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region4 configuration + */ +#define HP_APM_REGION4_LOCK (BIT(11)) +#define HP_APM_REGION4_LOCK_M (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S) +#define HP_APM_REGION4_LOCK_V 0x00000001U +#define HP_APM_REGION4_LOCK_S 11 + +/** HP_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) +/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ +#define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) +#define HP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_S 0 + +/** HP_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) +/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ +#define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) +#define HP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_S 0 + +/** HP_APM_REGION5_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) +/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_X (BIT(0)) +#define HP_APM_REGION5_R0_PMS_X_M (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S) +#define HP_APM_REGION5_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_X_S 0 +/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_W (BIT(1)) +#define HP_APM_REGION5_R0_PMS_W_M (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S) +#define HP_APM_REGION5_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_W_S 1 +/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION5_R0_PMS_R (BIT(2)) +#define HP_APM_REGION5_R0_PMS_R_M (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S) +#define HP_APM_REGION5_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R0_PMS_R_S 2 +/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_X (BIT(4)) +#define HP_APM_REGION5_R1_PMS_X_M (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S) +#define HP_APM_REGION5_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_X_S 4 +/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_W (BIT(5)) +#define HP_APM_REGION5_R1_PMS_W_M (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S) +#define HP_APM_REGION5_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_W_S 5 +/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION5_R1_PMS_R (BIT(6)) +#define HP_APM_REGION5_R1_PMS_R_M (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S) +#define HP_APM_REGION5_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R1_PMS_R_S 6 +/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_X (BIT(8)) +#define HP_APM_REGION5_R2_PMS_X_M (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S) +#define HP_APM_REGION5_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_X_S 8 +/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_W (BIT(9)) +#define HP_APM_REGION5_R2_PMS_W_M (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S) +#define HP_APM_REGION5_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_W_S 9 +/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION5_R2_PMS_R (BIT(10)) +#define HP_APM_REGION5_R2_PMS_R_M (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S) +#define HP_APM_REGION5_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION5_R2_PMS_R_S 10 +/** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region5 configuration + */ +#define HP_APM_REGION5_LOCK (BIT(11)) +#define HP_APM_REGION5_LOCK_M (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S) +#define HP_APM_REGION5_LOCK_V 0x00000001U +#define HP_APM_REGION5_LOCK_S 11 + +/** HP_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) +/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ +#define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) +#define HP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_S 0 + +/** HP_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) +/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ +#define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) +#define HP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_S 0 + +/** HP_APM_REGION6_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) +/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_X (BIT(0)) +#define HP_APM_REGION6_R0_PMS_X_M (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S) +#define HP_APM_REGION6_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_X_S 0 +/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_W (BIT(1)) +#define HP_APM_REGION6_R0_PMS_W_M (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S) +#define HP_APM_REGION6_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_W_S 1 +/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION6_R0_PMS_R (BIT(2)) +#define HP_APM_REGION6_R0_PMS_R_M (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S) +#define HP_APM_REGION6_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R0_PMS_R_S 2 +/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_X (BIT(4)) +#define HP_APM_REGION6_R1_PMS_X_M (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S) +#define HP_APM_REGION6_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_X_S 4 +/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_W (BIT(5)) +#define HP_APM_REGION6_R1_PMS_W_M (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S) +#define HP_APM_REGION6_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_W_S 5 +/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION6_R1_PMS_R (BIT(6)) +#define HP_APM_REGION6_R1_PMS_R_M (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S) +#define HP_APM_REGION6_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R1_PMS_R_S 6 +/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_X (BIT(8)) +#define HP_APM_REGION6_R2_PMS_X_M (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S) +#define HP_APM_REGION6_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_X_S 8 +/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_W (BIT(9)) +#define HP_APM_REGION6_R2_PMS_W_M (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S) +#define HP_APM_REGION6_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_W_S 9 +/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION6_R2_PMS_R (BIT(10)) +#define HP_APM_REGION6_R2_PMS_R_M (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S) +#define HP_APM_REGION6_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION6_R2_PMS_R_S 10 +/** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region6 configuration + */ +#define HP_APM_REGION6_LOCK (BIT(11)) +#define HP_APM_REGION6_LOCK_M (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S) +#define HP_APM_REGION6_LOCK_V 0x00000001U +#define HP_APM_REGION6_LOCK_S 11 + +/** HP_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) +/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ +#define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) +#define HP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_S 0 + +/** HP_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) +/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ +#define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) +#define HP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_S 0 + +/** HP_APM_REGION7_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) +/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_X (BIT(0)) +#define HP_APM_REGION7_R0_PMS_X_M (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S) +#define HP_APM_REGION7_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_X_S 0 +/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_W (BIT(1)) +#define HP_APM_REGION7_R0_PMS_W_M (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S) +#define HP_APM_REGION7_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_W_S 1 +/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION7_R0_PMS_R (BIT(2)) +#define HP_APM_REGION7_R0_PMS_R_M (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S) +#define HP_APM_REGION7_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R0_PMS_R_S 2 +/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_X (BIT(4)) +#define HP_APM_REGION7_R1_PMS_X_M (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S) +#define HP_APM_REGION7_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_X_S 4 +/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_W (BIT(5)) +#define HP_APM_REGION7_R1_PMS_W_M (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S) +#define HP_APM_REGION7_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_W_S 5 +/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION7_R1_PMS_R (BIT(6)) +#define HP_APM_REGION7_R1_PMS_R_M (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S) +#define HP_APM_REGION7_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R1_PMS_R_S 6 +/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_X (BIT(8)) +#define HP_APM_REGION7_R2_PMS_X_M (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S) +#define HP_APM_REGION7_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_X_S 8 +/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_W (BIT(9)) +#define HP_APM_REGION7_R2_PMS_W_M (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S) +#define HP_APM_REGION7_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_W_S 9 +/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION7_R2_PMS_R (BIT(10)) +#define HP_APM_REGION7_R2_PMS_R_M (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S) +#define HP_APM_REGION7_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION7_R2_PMS_R_S 10 +/** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region7 configuration + */ +#define HP_APM_REGION7_LOCK (BIT(11)) +#define HP_APM_REGION7_LOCK_M (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S) +#define HP_APM_REGION7_LOCK_V 0x00000001U +#define HP_APM_REGION7_LOCK_S 11 + +/** HP_APM_REGION8_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) +/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ +#define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) +#define HP_APM_REGION8_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_S 0 + +/** HP_APM_REGION8_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) +/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ +#define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) +#define HP_APM_REGION8_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_S 0 + +/** HP_APM_REGION8_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) +/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_X (BIT(0)) +#define HP_APM_REGION8_R0_PMS_X_M (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S) +#define HP_APM_REGION8_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_X_S 0 +/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_W (BIT(1)) +#define HP_APM_REGION8_R0_PMS_W_M (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S) +#define HP_APM_REGION8_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_W_S 1 +/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION8_R0_PMS_R (BIT(2)) +#define HP_APM_REGION8_R0_PMS_R_M (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S) +#define HP_APM_REGION8_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R0_PMS_R_S 2 +/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_X (BIT(4)) +#define HP_APM_REGION8_R1_PMS_X_M (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S) +#define HP_APM_REGION8_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_X_S 4 +/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_W (BIT(5)) +#define HP_APM_REGION8_R1_PMS_W_M (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S) +#define HP_APM_REGION8_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_W_S 5 +/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION8_R1_PMS_R (BIT(6)) +#define HP_APM_REGION8_R1_PMS_R_M (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S) +#define HP_APM_REGION8_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R1_PMS_R_S 6 +/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_X (BIT(8)) +#define HP_APM_REGION8_R2_PMS_X_M (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S) +#define HP_APM_REGION8_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_X_S 8 +/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_W (BIT(9)) +#define HP_APM_REGION8_R2_PMS_W_M (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S) +#define HP_APM_REGION8_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_W_S 9 +/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION8_R2_PMS_R (BIT(10)) +#define HP_APM_REGION8_R2_PMS_R_M (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S) +#define HP_APM_REGION8_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION8_R2_PMS_R_S 10 +/** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region8 configuration + */ +#define HP_APM_REGION8_LOCK (BIT(11)) +#define HP_APM_REGION8_LOCK_M (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S) +#define HP_APM_REGION8_LOCK_V 0x00000001U +#define HP_APM_REGION8_LOCK_S 11 + +/** HP_APM_REGION9_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) +/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ +#define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) +#define HP_APM_REGION9_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_S 0 + +/** HP_APM_REGION9_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) +/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ +#define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) +#define HP_APM_REGION9_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_S 0 + +/** HP_APM_REGION9_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) +/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_X (BIT(0)) +#define HP_APM_REGION9_R0_PMS_X_M (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S) +#define HP_APM_REGION9_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_X_S 0 +/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_W (BIT(1)) +#define HP_APM_REGION9_R0_PMS_W_M (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S) +#define HP_APM_REGION9_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_W_S 1 +/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION9_R0_PMS_R (BIT(2)) +#define HP_APM_REGION9_R0_PMS_R_M (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S) +#define HP_APM_REGION9_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R0_PMS_R_S 2 +/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_X (BIT(4)) +#define HP_APM_REGION9_R1_PMS_X_M (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S) +#define HP_APM_REGION9_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_X_S 4 +/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_W (BIT(5)) +#define HP_APM_REGION9_R1_PMS_W_M (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S) +#define HP_APM_REGION9_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_W_S 5 +/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION9_R1_PMS_R (BIT(6)) +#define HP_APM_REGION9_R1_PMS_R_M (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S) +#define HP_APM_REGION9_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R1_PMS_R_S 6 +/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_X (BIT(8)) +#define HP_APM_REGION9_R2_PMS_X_M (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S) +#define HP_APM_REGION9_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_X_S 8 +/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_W (BIT(9)) +#define HP_APM_REGION9_R2_PMS_W_M (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S) +#define HP_APM_REGION9_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_W_S 9 +/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION9_R2_PMS_R (BIT(10)) +#define HP_APM_REGION9_R2_PMS_R_M (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S) +#define HP_APM_REGION9_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION9_R2_PMS_R_S 10 +/** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region9 configuration + */ +#define HP_APM_REGION9_LOCK (BIT(11)) +#define HP_APM_REGION9_LOCK_M (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S) +#define HP_APM_REGION9_LOCK_V 0x00000001U +#define HP_APM_REGION9_LOCK_S 11 + +/** HP_APM_REGION10_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) +/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ +#define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) +#define HP_APM_REGION10_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_S 0 + +/** HP_APM_REGION10_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) +/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ +#define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) +#define HP_APM_REGION10_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_S 0 + +/** HP_APM_REGION10_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) +/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_X (BIT(0)) +#define HP_APM_REGION10_R0_PMS_X_M (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S) +#define HP_APM_REGION10_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_X_S 0 +/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_W (BIT(1)) +#define HP_APM_REGION10_R0_PMS_W_M (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S) +#define HP_APM_REGION10_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_W_S 1 +/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION10_R0_PMS_R (BIT(2)) +#define HP_APM_REGION10_R0_PMS_R_M (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S) +#define HP_APM_REGION10_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R0_PMS_R_S 2 +/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_X (BIT(4)) +#define HP_APM_REGION10_R1_PMS_X_M (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S) +#define HP_APM_REGION10_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_X_S 4 +/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_W (BIT(5)) +#define HP_APM_REGION10_R1_PMS_W_M (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S) +#define HP_APM_REGION10_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_W_S 5 +/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION10_R1_PMS_R (BIT(6)) +#define HP_APM_REGION10_R1_PMS_R_M (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S) +#define HP_APM_REGION10_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R1_PMS_R_S 6 +/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_X (BIT(8)) +#define HP_APM_REGION10_R2_PMS_X_M (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S) +#define HP_APM_REGION10_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_X_S 8 +/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_W (BIT(9)) +#define HP_APM_REGION10_R2_PMS_W_M (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S) +#define HP_APM_REGION10_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_W_S 9 +/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION10_R2_PMS_R (BIT(10)) +#define HP_APM_REGION10_R2_PMS_R_M (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S) +#define HP_APM_REGION10_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION10_R2_PMS_R_S 10 +/** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region10 configuration + */ +#define HP_APM_REGION10_LOCK (BIT(11)) +#define HP_APM_REGION10_LOCK_M (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S) +#define HP_APM_REGION10_LOCK_V 0x00000001U +#define HP_APM_REGION10_LOCK_S 11 + +/** HP_APM_REGION11_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) +/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ +#define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) +#define HP_APM_REGION11_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_S 0 + +/** HP_APM_REGION11_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) +/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ +#define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) +#define HP_APM_REGION11_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_S 0 + +/** HP_APM_REGION11_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) +/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_X (BIT(0)) +#define HP_APM_REGION11_R0_PMS_X_M (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S) +#define HP_APM_REGION11_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_X_S 0 +/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_W (BIT(1)) +#define HP_APM_REGION11_R0_PMS_W_M (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S) +#define HP_APM_REGION11_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_W_S 1 +/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION11_R0_PMS_R (BIT(2)) +#define HP_APM_REGION11_R0_PMS_R_M (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S) +#define HP_APM_REGION11_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R0_PMS_R_S 2 +/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_X (BIT(4)) +#define HP_APM_REGION11_R1_PMS_X_M (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S) +#define HP_APM_REGION11_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_X_S 4 +/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_W (BIT(5)) +#define HP_APM_REGION11_R1_PMS_W_M (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S) +#define HP_APM_REGION11_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_W_S 5 +/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION11_R1_PMS_R (BIT(6)) +#define HP_APM_REGION11_R1_PMS_R_M (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S) +#define HP_APM_REGION11_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R1_PMS_R_S 6 +/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_X (BIT(8)) +#define HP_APM_REGION11_R2_PMS_X_M (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S) +#define HP_APM_REGION11_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_X_S 8 +/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_W (BIT(9)) +#define HP_APM_REGION11_R2_PMS_W_M (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S) +#define HP_APM_REGION11_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_W_S 9 +/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION11_R2_PMS_R (BIT(10)) +#define HP_APM_REGION11_R2_PMS_R_M (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S) +#define HP_APM_REGION11_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION11_R2_PMS_R_S 10 +/** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region11 configuration + */ +#define HP_APM_REGION11_LOCK (BIT(11)) +#define HP_APM_REGION11_LOCK_M (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S) +#define HP_APM_REGION11_LOCK_V 0x00000001U +#define HP_APM_REGION11_LOCK_S 11 + +/** HP_APM_REGION12_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) +/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ +#define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) +#define HP_APM_REGION12_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_S 0 + +/** HP_APM_REGION12_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) +/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ +#define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) +#define HP_APM_REGION12_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_S 0 + +/** HP_APM_REGION12_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) +/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_X (BIT(0)) +#define HP_APM_REGION12_R0_PMS_X_M (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S) +#define HP_APM_REGION12_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_X_S 0 +/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_W (BIT(1)) +#define HP_APM_REGION12_R0_PMS_W_M (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S) +#define HP_APM_REGION12_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_W_S 1 +/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION12_R0_PMS_R (BIT(2)) +#define HP_APM_REGION12_R0_PMS_R_M (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S) +#define HP_APM_REGION12_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R0_PMS_R_S 2 +/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_X (BIT(4)) +#define HP_APM_REGION12_R1_PMS_X_M (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S) +#define HP_APM_REGION12_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_X_S 4 +/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_W (BIT(5)) +#define HP_APM_REGION12_R1_PMS_W_M (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S) +#define HP_APM_REGION12_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_W_S 5 +/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION12_R1_PMS_R (BIT(6)) +#define HP_APM_REGION12_R1_PMS_R_M (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S) +#define HP_APM_REGION12_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R1_PMS_R_S 6 +/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_X (BIT(8)) +#define HP_APM_REGION12_R2_PMS_X_M (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S) +#define HP_APM_REGION12_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_X_S 8 +/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_W (BIT(9)) +#define HP_APM_REGION12_R2_PMS_W_M (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S) +#define HP_APM_REGION12_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_W_S 9 +/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION12_R2_PMS_R (BIT(10)) +#define HP_APM_REGION12_R2_PMS_R_M (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S) +#define HP_APM_REGION12_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION12_R2_PMS_R_S 10 +/** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region12 configuration + */ +#define HP_APM_REGION12_LOCK (BIT(11)) +#define HP_APM_REGION12_LOCK_M (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S) +#define HP_APM_REGION12_LOCK_V 0x00000001U +#define HP_APM_REGION12_LOCK_S 11 + +/** HP_APM_REGION13_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) +/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ +#define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) +#define HP_APM_REGION13_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_S 0 + +/** HP_APM_REGION13_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) +/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ +#define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) +#define HP_APM_REGION13_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_S 0 + +/** HP_APM_REGION13_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) +/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_X (BIT(0)) +#define HP_APM_REGION13_R0_PMS_X_M (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S) +#define HP_APM_REGION13_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_X_S 0 +/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_W (BIT(1)) +#define HP_APM_REGION13_R0_PMS_W_M (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S) +#define HP_APM_REGION13_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_W_S 1 +/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION13_R0_PMS_R (BIT(2)) +#define HP_APM_REGION13_R0_PMS_R_M (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S) +#define HP_APM_REGION13_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R0_PMS_R_S 2 +/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_X (BIT(4)) +#define HP_APM_REGION13_R1_PMS_X_M (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S) +#define HP_APM_REGION13_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_X_S 4 +/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_W (BIT(5)) +#define HP_APM_REGION13_R1_PMS_W_M (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S) +#define HP_APM_REGION13_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_W_S 5 +/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION13_R1_PMS_R (BIT(6)) +#define HP_APM_REGION13_R1_PMS_R_M (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S) +#define HP_APM_REGION13_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R1_PMS_R_S 6 +/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_X (BIT(8)) +#define HP_APM_REGION13_R2_PMS_X_M (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S) +#define HP_APM_REGION13_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_X_S 8 +/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_W (BIT(9)) +#define HP_APM_REGION13_R2_PMS_W_M (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S) +#define HP_APM_REGION13_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_W_S 9 +/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION13_R2_PMS_R (BIT(10)) +#define HP_APM_REGION13_R2_PMS_R_M (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S) +#define HP_APM_REGION13_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION13_R2_PMS_R_S 10 +/** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region13 configuration + */ +#define HP_APM_REGION13_LOCK (BIT(11)) +#define HP_APM_REGION13_LOCK_M (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S) +#define HP_APM_REGION13_LOCK_V 0x00000001U +#define HP_APM_REGION13_LOCK_S 11 + +/** HP_APM_REGION14_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) +/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ +#define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) +#define HP_APM_REGION14_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_S 0 + +/** HP_APM_REGION14_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) +/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ +#define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) +#define HP_APM_REGION14_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_S 0 + +/** HP_APM_REGION14_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) +/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_X (BIT(0)) +#define HP_APM_REGION14_R0_PMS_X_M (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S) +#define HP_APM_REGION14_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_X_S 0 +/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_W (BIT(1)) +#define HP_APM_REGION14_R0_PMS_W_M (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S) +#define HP_APM_REGION14_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_W_S 1 +/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION14_R0_PMS_R (BIT(2)) +#define HP_APM_REGION14_R0_PMS_R_M (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S) +#define HP_APM_REGION14_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R0_PMS_R_S 2 +/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_X (BIT(4)) +#define HP_APM_REGION14_R1_PMS_X_M (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S) +#define HP_APM_REGION14_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_X_S 4 +/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_W (BIT(5)) +#define HP_APM_REGION14_R1_PMS_W_M (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S) +#define HP_APM_REGION14_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_W_S 5 +/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION14_R1_PMS_R (BIT(6)) +#define HP_APM_REGION14_R1_PMS_R_M (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S) +#define HP_APM_REGION14_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R1_PMS_R_S 6 +/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_X (BIT(8)) +#define HP_APM_REGION14_R2_PMS_X_M (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S) +#define HP_APM_REGION14_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_X_S 8 +/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_W (BIT(9)) +#define HP_APM_REGION14_R2_PMS_W_M (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S) +#define HP_APM_REGION14_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_W_S 9 +/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION14_R2_PMS_R (BIT(10)) +#define HP_APM_REGION14_R2_PMS_R_M (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S) +#define HP_APM_REGION14_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION14_R2_PMS_R_S 10 +/** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region14 configuration + */ +#define HP_APM_REGION14_LOCK (BIT(11)) +#define HP_APM_REGION14_LOCK_M (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S) +#define HP_APM_REGION14_LOCK_V 0x00000001U +#define HP_APM_REGION14_LOCK_S 11 + +/** HP_APM_REGION15_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) +/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ +#define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) +#define HP_APM_REGION15_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_S 0 + +/** HP_APM_REGION15_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) +/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ +#define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) +#define HP_APM_REGION15_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_S 0 + +/** HP_APM_REGION15_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) +/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_X (BIT(0)) +#define HP_APM_REGION15_R0_PMS_X_M (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S) +#define HP_APM_REGION15_R0_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_X_S 0 +/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_W (BIT(1)) +#define HP_APM_REGION15_R0_PMS_W_M (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S) +#define HP_APM_REGION15_R0_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_W_S 1 +/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define HP_APM_REGION15_R0_PMS_R (BIT(2)) +#define HP_APM_REGION15_R0_PMS_R_M (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S) +#define HP_APM_REGION15_R0_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R0_PMS_R_S 2 +/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_X (BIT(4)) +#define HP_APM_REGION15_R1_PMS_X_M (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S) +#define HP_APM_REGION15_R1_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_X_S 4 +/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_W (BIT(5)) +#define HP_APM_REGION15_R1_PMS_W_M (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S) +#define HP_APM_REGION15_R1_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_W_S 5 +/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define HP_APM_REGION15_R1_PMS_R (BIT(6)) +#define HP_APM_REGION15_R1_PMS_R_M (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S) +#define HP_APM_REGION15_R1_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R1_PMS_R_S 6 +/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_X (BIT(8)) +#define HP_APM_REGION15_R2_PMS_X_M (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S) +#define HP_APM_REGION15_R2_PMS_X_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_X_S 8 +/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_W (BIT(9)) +#define HP_APM_REGION15_R2_PMS_W_M (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S) +#define HP_APM_REGION15_R2_PMS_W_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_W_S 9 +/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define HP_APM_REGION15_R2_PMS_R (BIT(10)) +#define HP_APM_REGION15_R2_PMS_R_M (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S) +#define HP_APM_REGION15_R2_PMS_R_V 0x00000001U +#define HP_APM_REGION15_R2_PMS_R_S 10 +/** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region15 configuration + */ +#define HP_APM_REGION15_LOCK (BIT(11)) +#define HP_APM_REGION15_LOCK_M (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S) +#define HP_APM_REGION15_LOCK_V 0x00000001U +#define HP_APM_REGION15_LOCK_S 11 + +/** HP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) +/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define HP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define HP_APM_M0_PMS_FUNC_EN_M (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S) +#define HP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M0_PMS_FUNC_EN_S 0 +/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define HP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define HP_APM_M1_PMS_FUNC_EN_M (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S) +#define HP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M1_PMS_FUNC_EN_S 1 +/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define HP_APM_M2_PMS_FUNC_EN (BIT(2)) +#define HP_APM_M2_PMS_FUNC_EN_M (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S) +#define HP_APM_M2_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M2_PMS_FUNC_EN_S 2 +/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define HP_APM_M3_PMS_FUNC_EN (BIT(3)) +#define HP_APM_M3_PMS_FUNC_EN_M (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S) +#define HP_APM_M3_PMS_FUNC_EN_V 0x00000001U +#define HP_APM_M3_PMS_FUNC_EN_S 3 + +/** HP_APM_M0_STATUS_REG register + * M0 status register + */ +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) +/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) +#define HP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_S 0 + +/** HP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) +/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M0_REGION_STATUS_CLR_M (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S) +#define HP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M0_REGION_STATUS_CLR_S 0 + +/** HP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) +/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) +#define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_S 0 +/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M0_EXCEPTION_MODE 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) +#define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_S 16 +/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M0_EXCEPTION_ID 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) +#define HP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_S 18 + +/** HP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) +/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) +#define HP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_S 0 + +/** HP_APM_M1_STATUS_REG register + * M1 status register + */ +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) +/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) +#define HP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_S 0 + +/** HP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) +/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M1_REGION_STATUS_CLR_M (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S) +#define HP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M1_REGION_STATUS_CLR_S 0 + +/** HP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) +/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) +#define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_S 0 +/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M1_EXCEPTION_MODE 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) +#define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_S 16 +/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M1_EXCEPTION_ID 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) +#define HP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_S 18 + +/** HP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) +/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) +#define HP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_S 0 + +/** HP_APM_M2_STATUS_REG register + * M2 status register + */ +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) +/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M2_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) +#define HP_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_S 0 + +/** HP_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) +/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M2_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M2_REGION_STATUS_CLR_M (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S) +#define HP_APM_M2_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M2_REGION_STATUS_CLR_S 0 + +/** HP_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) +/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) +#define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_S 0 +/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M2_EXCEPTION_MODE 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) +#define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_S 16 +/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M2_EXCEPTION_ID 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) +#define HP_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_S 18 + +/** HP_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) +/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) +#define HP_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_S 0 + +/** HP_APM_M3_STATUS_REG register + * M3 status register + */ +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) +/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define HP_APM_M3_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) +#define HP_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_S 0 + +/** HP_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) +/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define HP_APM_M3_REGION_STATUS_CLR (BIT(0)) +#define HP_APM_M3_REGION_STATUS_CLR_M (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S) +#define HP_APM_M3_REGION_STATUS_CLR_V 0x00000001U +#define HP_APM_M3_REGION_STATUS_CLR_S 0 + +/** HP_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) +/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Exception region + */ +#define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) +#define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_S 0 +/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define HP_APM_M3_EXCEPTION_MODE 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) +#define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_S 16 +/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define HP_APM_M3_EXCEPTION_ID 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) +#define HP_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_S 18 + +/** HP_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) +/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) +#define HP_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_S 0 + +/** HP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) +/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define HP_APM_M0_APM_INT_EN (BIT(0)) +#define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) +#define HP_APM_M0_APM_INT_EN_V 0x00000001U +#define HP_APM_M0_APM_INT_EN_S 0 +/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define HP_APM_M1_APM_INT_EN (BIT(1)) +#define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) +#define HP_APM_M1_APM_INT_EN_V 0x00000001U +#define HP_APM_M1_APM_INT_EN_S 1 +/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ +#define HP_APM_M2_APM_INT_EN (BIT(2)) +#define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) +#define HP_APM_M2_APM_INT_EN_V 0x00000001U +#define HP_APM_M2_APM_INT_EN_S 2 +/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ +#define HP_APM_M3_APM_INT_EN (BIT(3)) +#define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) +#define HP_APM_M3_APM_INT_EN_V 0x00000001U +#define HP_APM_M3_APM_INT_EN_S 3 + +/** HP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c) +/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define HP_APM_CLK_EN (BIT(0)) +#define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) +#define HP_APM_CLK_EN_V 0x00000001U +#define HP_APM_CLK_EN_S 0 + +/** HP_APM_DATE_REG register + * Version register + */ +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) +/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ +#define HP_APM_DATE 0x0FFFFFFFU +#define HP_APM_DATE_M (HP_APM_DATE_V << HP_APM_DATE_S) +#define HP_APM_DATE_V 0x0FFFFFFFU +#define HP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_apm_struct.h b/components/soc/esp32c5/include/soc/hp_apm_struct.h new file mode 100644 index 0000000000..b3aea706af --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_apm_struct.h @@ -0,0 +1,1734 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [15:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} hp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} hp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} hp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} hp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} hp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} hp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} hp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} hp_apm_region3_addr_end_reg_t; + +/** Type of region4_addr_start register + * Region address register + */ +typedef union { + struct { + /** region4_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region4 + */ + uint32_t region4_addr_start:32; + }; + uint32_t val; +} hp_apm_region4_addr_start_reg_t; + +/** Type of region4_addr_end register + * Region address register + */ +typedef union { + struct { + /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region4 + */ + uint32_t region4_addr_end:32; + }; + uint32_t val; +} hp_apm_region4_addr_end_reg_t; + +/** Type of region5_addr_start register + * Region address register + */ +typedef union { + struct { + /** region5_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region5 + */ + uint32_t region5_addr_start:32; + }; + uint32_t val; +} hp_apm_region5_addr_start_reg_t; + +/** Type of region5_addr_end register + * Region address register + */ +typedef union { + struct { + /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region5 + */ + uint32_t region5_addr_end:32; + }; + uint32_t val; +} hp_apm_region5_addr_end_reg_t; + +/** Type of region6_addr_start register + * Region address register + */ +typedef union { + struct { + /** region6_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region6 + */ + uint32_t region6_addr_start:32; + }; + uint32_t val; +} hp_apm_region6_addr_start_reg_t; + +/** Type of region6_addr_end register + * Region address register + */ +typedef union { + struct { + /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region6 + */ + uint32_t region6_addr_end:32; + }; + uint32_t val; +} hp_apm_region6_addr_end_reg_t; + +/** Type of region7_addr_start register + * Region address register + */ +typedef union { + struct { + /** region7_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region7 + */ + uint32_t region7_addr_start:32; + }; + uint32_t val; +} hp_apm_region7_addr_start_reg_t; + +/** Type of region7_addr_end register + * Region address register + */ +typedef union { + struct { + /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region7 + */ + uint32_t region7_addr_end:32; + }; + uint32_t val; +} hp_apm_region7_addr_end_reg_t; + +/** Type of region8_addr_start register + * Region address register + */ +typedef union { + struct { + /** region8_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region8 + */ + uint32_t region8_addr_start:32; + }; + uint32_t val; +} hp_apm_region8_addr_start_reg_t; + +/** Type of region8_addr_end register + * Region address register + */ +typedef union { + struct { + /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region8 + */ + uint32_t region8_addr_end:32; + }; + uint32_t val; +} hp_apm_region8_addr_end_reg_t; + +/** Type of region9_addr_start register + * Region address register + */ +typedef union { + struct { + /** region9_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region9 + */ + uint32_t region9_addr_start:32; + }; + uint32_t val; +} hp_apm_region9_addr_start_reg_t; + +/** Type of region9_addr_end register + * Region address register + */ +typedef union { + struct { + /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region9 + */ + uint32_t region9_addr_end:32; + }; + uint32_t val; +} hp_apm_region9_addr_end_reg_t; + +/** Type of region10_addr_start register + * Region address register + */ +typedef union { + struct { + /** region10_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region10 + */ + uint32_t region10_addr_start:32; + }; + uint32_t val; +} hp_apm_region10_addr_start_reg_t; + +/** Type of region10_addr_end register + * Region address register + */ +typedef union { + struct { + /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region10 + */ + uint32_t region10_addr_end:32; + }; + uint32_t val; +} hp_apm_region10_addr_end_reg_t; + +/** Type of region11_addr_start register + * Region address register + */ +typedef union { + struct { + /** region11_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region11 + */ + uint32_t region11_addr_start:32; + }; + uint32_t val; +} hp_apm_region11_addr_start_reg_t; + +/** Type of region11_addr_end register + * Region address register + */ +typedef union { + struct { + /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region11 + */ + uint32_t region11_addr_end:32; + }; + uint32_t val; +} hp_apm_region11_addr_end_reg_t; + +/** Type of region12_addr_start register + * Region address register + */ +typedef union { + struct { + /** region12_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region12 + */ + uint32_t region12_addr_start:32; + }; + uint32_t val; +} hp_apm_region12_addr_start_reg_t; + +/** Type of region12_addr_end register + * Region address register + */ +typedef union { + struct { + /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region12 + */ + uint32_t region12_addr_end:32; + }; + uint32_t val; +} hp_apm_region12_addr_end_reg_t; + +/** Type of region13_addr_start register + * Region address register + */ +typedef union { + struct { + /** region13_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region13 + */ + uint32_t region13_addr_start:32; + }; + uint32_t val; +} hp_apm_region13_addr_start_reg_t; + +/** Type of region13_addr_end register + * Region address register + */ +typedef union { + struct { + /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region13 + */ + uint32_t region13_addr_end:32; + }; + uint32_t val; +} hp_apm_region13_addr_end_reg_t; + +/** Type of region14_addr_start register + * Region address register + */ +typedef union { + struct { + /** region14_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region14 + */ + uint32_t region14_addr_start:32; + }; + uint32_t val; +} hp_apm_region14_addr_start_reg_t; + +/** Type of region14_addr_end register + * Region address register + */ +typedef union { + struct { + /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region14 + */ + uint32_t region14_addr_end:32; + }; + uint32_t val; +} hp_apm_region14_addr_end_reg_t; + +/** Type of region15_addr_start register + * Region address register + */ +typedef union { + struct { + /** region15_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region15 + */ + uint32_t region15_addr_start:32; + }; + uint32_t val; +} hp_apm_region15_addr_start_reg_t; + +/** Type of region15_addr_end register + * Region address register + */ +typedef union { + struct { + /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region15 + */ + uint32_t region15_addr_end:32; + }; + uint32_t val; +} hp_apm_region15_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + /** region0_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t region0_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + /** region1_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ + uint32_t region1_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + /** region2_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ + uint32_t region2_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + /** region3_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ + uint32_t region3_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region3_pms_attr_reg_t; + +/** Type of region4_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region4_r0_pms_x:1; + /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region4_r0_pms_w:1; + /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region4_r0_pms_r:1; + uint32_t reserved_3:1; + /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region4_r1_pms_x:1; + /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region4_r1_pms_w:1; + /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region4_r1_pms_r:1; + uint32_t reserved_7:1; + /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region4_r2_pms_x:1; + /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region4_r2_pms_w:1; + /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region4_r2_pms_r:1; + /** region4_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region4 configuration + */ + uint32_t region4_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region4_pms_attr_reg_t; + +/** Type of region5_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region5_r0_pms_x:1; + /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region5_r0_pms_w:1; + /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region5_r0_pms_r:1; + uint32_t reserved_3:1; + /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region5_r1_pms_x:1; + /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region5_r1_pms_w:1; + /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region5_r1_pms_r:1; + uint32_t reserved_7:1; + /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region5_r2_pms_x:1; + /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region5_r2_pms_w:1; + /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region5_r2_pms_r:1; + /** region5_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region5 configuration + */ + uint32_t region5_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region5_pms_attr_reg_t; + +/** Type of region6_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region6_r0_pms_x:1; + /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region6_r0_pms_w:1; + /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region6_r0_pms_r:1; + uint32_t reserved_3:1; + /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region6_r1_pms_x:1; + /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region6_r1_pms_w:1; + /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region6_r1_pms_r:1; + uint32_t reserved_7:1; + /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region6_r2_pms_x:1; + /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region6_r2_pms_w:1; + /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region6_r2_pms_r:1; + /** region6_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region6 configuration + */ + uint32_t region6_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region6_pms_attr_reg_t; + +/** Type of region7_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region7_r0_pms_x:1; + /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region7_r0_pms_w:1; + /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region7_r0_pms_r:1; + uint32_t reserved_3:1; + /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region7_r1_pms_x:1; + /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region7_r1_pms_w:1; + /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region7_r1_pms_r:1; + uint32_t reserved_7:1; + /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region7_r2_pms_x:1; + /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region7_r2_pms_w:1; + /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region7_r2_pms_r:1; + /** region7_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region7 configuration + */ + uint32_t region7_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region7_pms_attr_reg_t; + +/** Type of region8_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region8_r0_pms_x:1; + /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region8_r0_pms_w:1; + /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region8_r0_pms_r:1; + uint32_t reserved_3:1; + /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region8_r1_pms_x:1; + /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region8_r1_pms_w:1; + /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region8_r1_pms_r:1; + uint32_t reserved_7:1; + /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region8_r2_pms_x:1; + /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region8_r2_pms_w:1; + /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region8_r2_pms_r:1; + /** region8_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region8 configuration + */ + uint32_t region8_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region8_pms_attr_reg_t; + +/** Type of region9_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region9_r0_pms_x:1; + /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region9_r0_pms_w:1; + /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region9_r0_pms_r:1; + uint32_t reserved_3:1; + /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region9_r1_pms_x:1; + /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region9_r1_pms_w:1; + /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region9_r1_pms_r:1; + uint32_t reserved_7:1; + /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region9_r2_pms_x:1; + /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region9_r2_pms_w:1; + /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region9_r2_pms_r:1; + /** region9_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region9 configuration + */ + uint32_t region9_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region9_pms_attr_reg_t; + +/** Type of region10_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region10_r0_pms_x:1; + /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region10_r0_pms_w:1; + /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region10_r0_pms_r:1; + uint32_t reserved_3:1; + /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region10_r1_pms_x:1; + /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region10_r1_pms_w:1; + /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region10_r1_pms_r:1; + uint32_t reserved_7:1; + /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region10_r2_pms_x:1; + /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region10_r2_pms_w:1; + /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region10_r2_pms_r:1; + /** region10_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region10 configuration + */ + uint32_t region10_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region10_pms_attr_reg_t; + +/** Type of region11_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region11_r0_pms_x:1; + /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region11_r0_pms_w:1; + /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region11_r0_pms_r:1; + uint32_t reserved_3:1; + /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region11_r1_pms_x:1; + /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region11_r1_pms_w:1; + /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region11_r1_pms_r:1; + uint32_t reserved_7:1; + /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region11_r2_pms_x:1; + /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region11_r2_pms_w:1; + /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region11_r2_pms_r:1; + /** region11_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region11 configuration + */ + uint32_t region11_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region11_pms_attr_reg_t; + +/** Type of region12_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region12_r0_pms_x:1; + /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region12_r0_pms_w:1; + /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region12_r0_pms_r:1; + uint32_t reserved_3:1; + /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region12_r1_pms_x:1; + /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region12_r1_pms_w:1; + /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region12_r1_pms_r:1; + uint32_t reserved_7:1; + /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region12_r2_pms_x:1; + /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region12_r2_pms_w:1; + /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region12_r2_pms_r:1; + /** region12_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region12 configuration + */ + uint32_t region12_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region12_pms_attr_reg_t; + +/** Type of region13_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region13_r0_pms_x:1; + /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region13_r0_pms_w:1; + /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region13_r0_pms_r:1; + uint32_t reserved_3:1; + /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region13_r1_pms_x:1; + /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region13_r1_pms_w:1; + /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region13_r1_pms_r:1; + uint32_t reserved_7:1; + /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region13_r2_pms_x:1; + /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region13_r2_pms_w:1; + /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region13_r2_pms_r:1; + /** region13_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region13 configuration + */ + uint32_t region13_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region13_pms_attr_reg_t; + +/** Type of region14_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region14_r0_pms_x:1; + /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region14_r0_pms_w:1; + /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region14_r0_pms_r:1; + uint32_t reserved_3:1; + /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region14_r1_pms_x:1; + /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region14_r1_pms_w:1; + /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region14_r1_pms_r:1; + uint32_t reserved_7:1; + /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region14_r2_pms_x:1; + /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region14_r2_pms_w:1; + /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region14_r2_pms_r:1; + /** region14_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region14 configuration + */ + uint32_t region14_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region14_pms_attr_reg_t; + +/** Type of region15_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region15_r0_pms_x:1; + /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region15_r0_pms_w:1; + /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region15_r0_pms_r:1; + uint32_t reserved_3:1; + /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region15_r1_pms_x:1; + /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region15_r1_pms_w:1; + /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region15_r1_pms_r:1; + uint32_t reserved_7:1; + /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region15_r2_pms_x:1; + /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region15_r2_pms_w:1; + /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region15_r2_pms_r:1; + /** region15_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region15 configuration + */ + uint32_t region15_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_region15_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + /** m2_pms_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_pms_func_en:1; + /** m3_pms_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_pms_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} hp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} hp_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m2_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} hp_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m3_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Exception region + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} hp_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * APM M2 interrupt enable + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * APM M3 interrupt enable + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_apm_date_reg_t; + + +typedef struct { + volatile hp_apm_region_filter_en_reg_t region_filter_en; + volatile hp_apm_region0_addr_start_reg_t region0_addr_start; + volatile hp_apm_region0_addr_end_reg_t region0_addr_end; + volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile hp_apm_region1_addr_start_reg_t region1_addr_start; + volatile hp_apm_region1_addr_end_reg_t region1_addr_end; + volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile hp_apm_region2_addr_start_reg_t region2_addr_start; + volatile hp_apm_region2_addr_end_reg_t region2_addr_end; + volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile hp_apm_region3_addr_start_reg_t region3_addr_start; + volatile hp_apm_region3_addr_end_reg_t region3_addr_end; + volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr; + volatile hp_apm_region4_addr_start_reg_t region4_addr_start; + volatile hp_apm_region4_addr_end_reg_t region4_addr_end; + volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr; + volatile hp_apm_region5_addr_start_reg_t region5_addr_start; + volatile hp_apm_region5_addr_end_reg_t region5_addr_end; + volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr; + volatile hp_apm_region6_addr_start_reg_t region6_addr_start; + volatile hp_apm_region6_addr_end_reg_t region6_addr_end; + volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr; + volatile hp_apm_region7_addr_start_reg_t region7_addr_start; + volatile hp_apm_region7_addr_end_reg_t region7_addr_end; + volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr; + volatile hp_apm_region8_addr_start_reg_t region8_addr_start; + volatile hp_apm_region8_addr_end_reg_t region8_addr_end; + volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr; + volatile hp_apm_region9_addr_start_reg_t region9_addr_start; + volatile hp_apm_region9_addr_end_reg_t region9_addr_end; + volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr; + volatile hp_apm_region10_addr_start_reg_t region10_addr_start; + volatile hp_apm_region10_addr_end_reg_t region10_addr_end; + volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr; + volatile hp_apm_region11_addr_start_reg_t region11_addr_start; + volatile hp_apm_region11_addr_end_reg_t region11_addr_end; + volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr; + volatile hp_apm_region12_addr_start_reg_t region12_addr_start; + volatile hp_apm_region12_addr_end_reg_t region12_addr_end; + volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr; + volatile hp_apm_region13_addr_start_reg_t region13_addr_start; + volatile hp_apm_region13_addr_end_reg_t region13_addr_end; + volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr; + volatile hp_apm_region14_addr_start_reg_t region14_addr_start; + volatile hp_apm_region14_addr_end_reg_t region14_addr_end; + volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr; + volatile hp_apm_region15_addr_start_reg_t region15_addr_start; + volatile hp_apm_region15_addr_end_reg_t region15_addr_end; + volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr; + volatile hp_apm_func_ctrl_reg_t func_ctrl; + volatile hp_apm_m0_status_reg_t m0_status; + volatile hp_apm_m0_status_clr_reg_t m0_status_clr; + volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile hp_apm_m1_status_reg_t m1_status; + volatile hp_apm_m1_status_clr_reg_t m1_status_clr; + volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile hp_apm_m2_status_reg_t m2_status; + volatile hp_apm_m2_status_clr_reg_t m2_status_clr; + volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile hp_apm_m3_status_reg_t m3_status; + volatile hp_apm_m3_status_clr_reg_t m3_status_clr; + volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1; + volatile hp_apm_int_en_reg_t int_en; + volatile hp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_110[443]; + volatile hp_apm_date_reg_t date; +} hp_apm_dev_t; + +extern hp_apm_dev_t HP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/huk_reg.h b/components/soc/esp32c5/include/soc/huk_reg.h new file mode 100644 index 0000000000..3f394c71e4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/huk_reg.h @@ -0,0 +1,222 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HUK_CLK_REG register + * HUK Generator clock gate control register + */ +#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4) +/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define HUK_CLK_EN (BIT(0)) +#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S) +#define HUK_CLK_EN_V 0x00000001U +#define HUK_CLK_EN_S 0 +/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define HUK_MEM_CG_FORCE_ON (BIT(1)) +#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S) +#define HUK_MEM_CG_FORCE_ON_V 0x00000001U +#define HUK_MEM_CG_FORCE_ON_S 1 + +/** HUK_INT_RAW_REG register + * HUK Generator interrupt raw register, valid in level. + */ +#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8) +/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_RAW (BIT(0)) +#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S) +#define HUK_PREP_DONE_INT_RAW_V 0x00000001U +#define HUK_PREP_DONE_INT_RAW_S 0 +/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_RAW (BIT(1)) +#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S) +#define HUK_PROC_DONE_INT_RAW_V 0x00000001U +#define HUK_PROC_DONE_INT_RAW_S 1 +/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_RAW (BIT(2)) +#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S) +#define HUK_POST_DONE_INT_RAW_V 0x00000001U +#define HUK_POST_DONE_INT_RAW_S 2 + +/** HUK_INT_ST_REG register + * HUK Generator interrupt status register. + */ +#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc) +/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_ST (BIT(0)) +#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S) +#define HUK_PREP_DONE_INT_ST_V 0x00000001U +#define HUK_PREP_DONE_INT_ST_S 0 +/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_ST (BIT(1)) +#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S) +#define HUK_PROC_DONE_INT_ST_V 0x00000001U +#define HUK_PROC_DONE_INT_ST_S 1 +/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_ST (BIT(2)) +#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S) +#define HUK_POST_DONE_INT_ST_V 0x00000001U +#define HUK_POST_DONE_INT_ST_S 2 + +/** HUK_INT_ENA_REG register + * HUK Generator interrupt enable register. + */ +#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10) +/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_ENA (BIT(0)) +#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S) +#define HUK_PREP_DONE_INT_ENA_V 0x00000001U +#define HUK_PREP_DONE_INT_ENA_S 0 +/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_ENA (BIT(1)) +#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S) +#define HUK_PROC_DONE_INT_ENA_V 0x00000001U +#define HUK_PROC_DONE_INT_ENA_S 1 +/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_ENA (BIT(2)) +#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S) +#define HUK_POST_DONE_INT_ENA_V 0x00000001U +#define HUK_POST_DONE_INT_ENA_S 2 + +/** HUK_INT_CLR_REG register + * HUK Generator interrupt clear register. + */ +#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14) +/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the huk_prep_done_int interrupt + */ +#define HUK_PREP_DONE_INT_CLR (BIT(0)) +#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S) +#define HUK_PREP_DONE_INT_CLR_V 0x00000001U +#define HUK_PREP_DONE_INT_CLR_S 0 +/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the huk_proc_done_int interrupt + */ +#define HUK_PROC_DONE_INT_CLR (BIT(1)) +#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S) +#define HUK_PROC_DONE_INT_CLR_V 0x00000001U +#define HUK_PROC_DONE_INT_CLR_S 1 +/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the huk_post_done_int interrupt + */ +#define HUK_POST_DONE_INT_CLR (BIT(2)) +#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S) +#define HUK_POST_DONE_INT_CLR_V 0x00000001U +#define HUK_POST_DONE_INT_CLR_S 2 + +/** HUK_CONF_REG register + * HUK Generator configuration register + */ +#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20) +/** HUK_MODE : R/W; bitpos: [0]; default: 0; + * Set this field to choose the huk process. 1: process huk generate mode. 0: process + * huk recovery mode. + */ +#define HUK_MODE (BIT(0)) +#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S) +#define HUK_MODE_V 0x00000001U +#define HUK_MODE_S 0 + +/** HUK_START_REG register + * HUK Generator control register + */ +#define HUK_START_REG (DR_REG_HUK_BASE + 0x24) +/** HUK_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ +#define HUK_START (BIT(0)) +#define HUK_START_M (HUK_START_V << HUK_START_S) +#define HUK_START_V 0x00000001U +#define HUK_START_S 0 +/** HUK_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start HUK Generator at IDLE state. + */ +#define HUK_CONTINUE (BIT(1)) +#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S) +#define HUK_CONTINUE_V 0x00000001U +#define HUK_CONTINUE_S 1 + +/** HUK_STATE_REG register + * HUK Generator state register + */ +#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28) +/** HUK_STATE : RO; bitpos: [1:0]; default: 0; + * The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define HUK_STATE 0x00000003U +#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S) +#define HUK_STATE_V 0x00000003U +#define HUK_STATE_S 0 + +/** HUK_STATUS_REG register + * HUK Generator HUK status register + */ +#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34) +/** HUK_STATUS : RO; bitpos: [1:0]; default: 0; + * The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. + * 2: HUK is generated but invalid. 3: reserved. + */ +#define HUK_STATUS 0x00000003U +#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S) +#define HUK_STATUS_V 0x00000003U +#define HUK_STATUS_S 0 +/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0; + * The risk level of HUK. 0-6: the higher the risk level is, the more error bits there + * are in the PUF SRAM. 7: Error Level, HUK is invalid. + */ +#define HUK_RISK_LEVEL 0x00000007U +#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S) +#define HUK_RISK_LEVEL_V 0x00000007U +#define HUK_RISK_LEVEL_S 2 + +/** HUK_DATE_REG register + * Version control register + */ +#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc) +/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704; + * HUK Generator version control register. + */ +#define HUK_DATE 0x0FFFFFFFU +#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S) +#define HUK_DATE_V 0x0FFFFFFFU +#define HUK_DATE_S 0 + +/** HUK_INFO_MEM register + * The memory that stores HUK info. + */ +#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100) +#define HUK_INFO_MEM_SIZE_BYTES 384 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/include/soc/huk_struct.h new file mode 100644 index 0000000000..e9ba80fbc9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/huk_struct.h @@ -0,0 +1,241 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * HUK Generator clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * HUK Generator interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_raw_reg_t; + +/** Type of int_st register + * HUK Generator interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_st_reg_t; + +/** Type of int_ena register + * HUK Generator interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the huk_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_ena_reg_t; + +/** Type of int_clr register + * HUK Generator interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the huk_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the huk_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the huk_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} huk_int_clr_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * HUK Generator configuration register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [0]; default: 0; + * Set this field to choose the huk process. 1: process huk generate mode. 0: process + * huk recovery mode. + */ + uint32_t mode:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} huk_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * HUK Generator control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start HUK Generator at IDLE state. + */ + uint32_t continue:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * HUK Generator state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} huk_state_reg_t; + + +/** Group: Result registers */ +/** Type of status register + * HUK Generator HUK status register + */ +typedef union { + struct { + /** status : RO; bitpos: [1:0]; default: 0; + * The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. + * 2: HUK is generated but invalid. 3: reserved. + */ + uint32_t status:2; + /** risk_level : RO; bitpos: [4:2]; default: 0; + * The risk level of HUK. 0-6: the higher the risk level is, the more error bits there + * are in the PUF SRAM. 7: Error Level, HUK is invalid. + */ + uint32_t risk_level:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} huk_status_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * HUK Generator version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} huk_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile huk_clk_reg_t clk; + volatile huk_int_raw_reg_t int_raw; + volatile huk_int_st_reg_t int_st; + volatile huk_int_ena_reg_t int_ena; + volatile huk_int_clr_reg_t int_clr; + uint32_t reserved_018[2]; + volatile huk_conf_reg_t conf; + volatile huk_start_reg_t start; + volatile huk_state_reg_t state; + uint32_t reserved_02c[2]; + volatile huk_status_reg_t status; + uint32_t reserved_038[49]; + volatile huk_date_reg_t date; + volatile uint32_t info[96]; +} huk_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2c_reg.h b/components/soc/esp32c5/include/soc/i2c_reg.h new file mode 100644 index 0000000000..9cdfdcede6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2c_reg.h @@ -0,0 +1,1521 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL Clock. + */ +#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define I2C_SCL_LOW_PERIOD_S 0 + +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) +/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * Configures the SDA output mode + * 1: Direct output, + * + * 0: Open drain output. + */ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) +#define I2C_SDA_FORCE_OUT_V 0x00000001U +#define I2C_SDA_FORCE_OUT_S 0 +/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * Configures the SCL output mode + * 1: Direct output, + * + * 0: Open drain output. + */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) +#define I2C_SCL_FORCE_OUT_V 0x00000001U +#define I2C_SCL_FORCE_OUT_S 1 +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; + * Configures the module as an I2C Master or Slave. + * 0: Slave + * + * 1: Master + */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) +#define I2C_MS_MODE_V 0x00000001U +#define I2C_MS_MODE_S 4 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 +/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; + * Configures to enable slave to send data automatically + * 0: Disable + * + * 1: Enable + */ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check + * + * 1: Check + */ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; + * Configures to support the 7bit general call function. + * 0: Not support + * + * 1: Support + */ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) +#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/** I2C_SR_REG register + * Describe I2C work status. + */ +#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U +#define I2C_RESP_REC_S 0 +/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * Represents the transfer direction in slave mode,. + * 1: Master reads from slave, + * + * 0: Master writes to slave. + */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) +#define I2C_SLAVE_RW_V 0x00000001U +#define I2C_SLAVE_RW_S 1 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; + * Represents whether the address sent by the master is equal to the address of the + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * + * 1: Equal + */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) +#define I2C_SLAVE_ADDRESSED_V 0x00000001U +#define I2C_SLAVE_ADDRESSED_S 5 +/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; + * Represents the number of data bytes to be sent. + */ +#define I2C_RXFIFO_CNT 0x0000003FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000003FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + * + * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. + */ +#define I2C_STRETCH_CAUSE 0x00000003U +#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) +#define I2C_STRETCH_CAUSE_V 0x00000003U +#define I2C_STRETCH_CAUSE_S 14 +/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ +#define I2C_TXFIFO_CNT 0x0000003FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000003FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 + +/** I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU +#define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 + +/** I2C_SLAVE_ADDR_REG register + * Local slave address setting + */ +#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) +/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * Configure the slave address of I2C Slave. + */ +#define I2C_SLAVE_ADDR 0x00007FFFU +#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) +#define I2C_SLAVE_ADDR_V 0x00007FFFU +#define I2C_SLAVE_ADDR_S 0 +/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * + * 1: Enable + */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) +#define I2C_ADDR_10BIT_EN_V 0x00000001U +#define I2C_ADDR_10BIT_EN_S 31 + +/** I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ +#define I2C_RXFIFO_RADDR 0x0000001FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000001FU +#define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ +#define I2C_RXFIFO_WADDR 0x0000001FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000001FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ +#define I2C_TXFIFO_RADDR 0x0000001FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000001FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ +#define I2C_TXFIFO_WADDR 0x0000001FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000001FU +#define I2C_TXFIFO_WADDR_S 15 +/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C slave mode. + */ +#define I2C_SLAVE_RW_POINT 0x000000FFU +#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) +#define I2C_SLAVE_RW_POINT_V 0x000000FFU +#define I2C_SLAVE_RW_POINT_S 22 + +/** I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define I2C_RXFIFO_WM_THRHD 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; + * Configures to enable double addressing mode. When this mode is enabled, the byte + * received after the I2C address byte represents the offset address in the I2C Slave + * RAM. + * 0: Disable + * + * 1: Enable + */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) +#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 + +/** I2C_DATA_REG register + * Rx FIFO read data. + */ +#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) +/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU +#define I2C_FIFO_RDATA_S 0 + +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 +/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) +#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U +#define I2C_GENERAL_CALL_INT_RAW_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 + +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 +/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; + * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) +#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U +#define I2C_GENERAL_CALL_INT_CLR_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 + +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to enable the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to enable the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * Write 1 to enable I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 +/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; + * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) +#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ENA_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 + +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 +/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) +#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ST_S 17 +/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 + +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU +#define I2C_SDA_HOLD_TIME_S 0 + +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_S 0 + +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_S 0 + +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and SCL rising edge for a stop condition. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU +#define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 + +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU +#define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 + +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU +#define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 + +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU +#define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 + +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU +#define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 + +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU +#define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 + +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU +#define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 + +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU +#define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 + +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU +#define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 + +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 + +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U +#define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_sda_force_out is 1. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 + +/** I2C_SCL_STRETCH_CONF_REG register + * Set SCL stretch of I2C slave + */ +#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) +/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk + */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) +#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_S 0 +/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable slave SCL stretch function. + * 0: Disable + * + * 1: Enable + * The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and + * stretch event happens. The stretch cause can be seen in reg_stretch_cause. + */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * + * 1: Clear + */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * + * 1: Enable + */ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * + * 1: High level + */ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050; + * Version control register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU +#define I2C_DATE_S 0 + +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) +/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 + +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) +/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/include/soc/i2c_struct.h new file mode 100644 index 0000000000..9df9e0d41d --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2c_struct.h @@ -0,0 +1,1277 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL Clock. + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and SCL rising edge for a stop condition. + * Measurement unit: i2c_sclk + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 0; + * Configures the SDA output mode + * 1: Direct output, + * + * 0: Open drain output. + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 0; + * Configures the SCL output mode + * 1: Direct output, + * + * 0: Open drain output. + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ + uint32_t rx_full_ack_level:1; + /** ms_mode : R/W; bitpos: [4]; default: 0; + * Configures the module as an I2C Master or Slave. + * 0: Slave + * + * 1: Master + */ + uint32_t ms_mode:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ + uint32_t conf_upgate:1; + /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; + * Configures to enable slave to send data automatically + * 0: Disable + * + * 1: Enable + */ + uint32_t slv_tx_auto_start_en:1; + /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check + * + * 1: Check + */ + uint32_t addr_10bit_rw_check_en:1; + /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; + * Configures to support the 7bit general call function. + * 0: Not support + * + * 1: Support + */ + uint32_t addr_broadcasting_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of slave_addr register + * Local slave address setting + */ +typedef union { + struct { + /** slave_addr : R/W; bitpos: [14:0]; default: 0; + * Configure the slave address of I2C Slave. + */ + uint32_t slave_addr:15; + uint32_t reserved_15:16; + /** addr_10bit_en : R/W; bitpos: [31]; default: 0; + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * + * 1: Enable + */ + uint32_t addr_10bit_en:1; + }; + uint32_t val; +} i2c_slave_addr_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:5; + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:5; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; + * Configures to enable double addressing mode. When this mode is enabled, the byte + * received after the I2C address byte represents the offset address in the I2C Slave + * RAM. + * 0: Disable + * + * 1: Enable + */ + uint32_t fifo_addr_cfg_en:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_sda_force_out is 1. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ +typedef union { + struct { + /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk + */ + uint32_t stretch_protect_num:10; + /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; + * Configures to enable slave SCL stretch function. + * 0: Disable + * + * 1: Enable + * The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and + * stretch event happens. The stretch cause can be seen in reg_stretch_cause. + */ + uint32_t slave_scl_stretch_en:1; + /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * + * 1: Clear + */ + uint32_t slave_scl_stretch_clr:1; + /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * + * 1: Enable + */ + uint32_t slave_byte_ack_ctl_en:1; + /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * + * 1: High level + */ + uint32_t slave_byte_ack_lvl:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} i2c_scl_stretch_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ + uint32_t resp_rec:1; + /** slave_rw : RO; bitpos: [1]; default: 0; + * Represents the transfer direction in slave mode,. + * 1: Master reads from slave, + * + * 0: Master writes to slave. + */ + uint32_t slave_rw:1; + uint32_t reserved_2:1; + /** arb_lost : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ + uint32_t bus_busy:1; + /** slave_addressed : RO; bitpos: [5]; default: 0; + * Represents whether the address sent by the master is equal to the address of the + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * + * 1: Equal + */ + uint32_t slave_addressed:1; + uint32_t reserved_6:2; + /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; + * Represents the number of data bytes to be sent. + */ + uint32_t rxfifo_cnt:6; + /** stretch_cause : RO; bitpos: [15:14]; default: 3; + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + * + * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. + */ + uint32_t stretch_cause:2; + uint32_t reserved_16:2; + /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ + uint32_t txfifo_cnt:6; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ + uint32_t rxfifo_raddr:5; + /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ + uint32_t rxfifo_waddr:5; + /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ + uint32_t txfifo_raddr:5; + /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ + uint32_t txfifo_waddr:5; + uint32_t reserved_20:2; + /** slave_rw_point : RO; bitpos: [29:22]; default: 0; + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C slave mode. + */ + uint32_t slave_rw_point:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_raw:1; + /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_raw:1; + /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_raw:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_clr:1; + /** general_call_int_clr : WT; bitpos: [17]; default: 0; + * Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_clr:1; + /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + */ + uint32_t slave_addr_unmatch_int_clr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to enable the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to enable the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * Write 1 to enable I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; + * Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_ena:1; + /** general_call_int_ena : R/W; bitpos: [17]; default: 0; + * Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_ena:1; + /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_ena:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_st:1; + /** general_call_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_st:1; + /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + */ + uint32_t slave_addr_unmatch_int_st:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd0 register + * I2C command register 0 + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ + uint32_t command0:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command0_done:1; + }; + uint32_t val; +} i2c_comd0_reg_t; + +/** Type of comd1 register + * I2C command register 1 + */ +typedef union { + struct { + /** command1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command1:14; + uint32_t reserved_14:17; + /** command1_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command1_done:1; + }; + uint32_t val; +} i2c_comd1_reg_t; + +/** Type of comd2 register + * I2C command register 2 + */ +typedef union { + struct { + /** command2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command2:14; + uint32_t reserved_14:17; + /** command2_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command2_done:1; + }; + uint32_t val; +} i2c_comd2_reg_t; + +/** Type of comd3 register + * I2C command register 3 + */ +typedef union { + struct { + /** command3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command3:14; + uint32_t reserved_14:17; + /** command3_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command3_done:1; + }; + uint32_t val; +} i2c_comd3_reg_t; + +/** Type of comd4 register + * I2C command register 4 + */ +typedef union { + struct { + /** command4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command4:14; + uint32_t reserved_14:17; + /** command4_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command4_done:1; + }; + uint32_t val; +} i2c_comd4_reg_t; + +/** Type of comd5 register + * I2C command register 5 + */ +typedef union { + struct { + /** command5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command5:14; + uint32_t reserved_14:17; + /** command5_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command5_done:1; + }; + uint32_t val; +} i2c_comd5_reg_t; + +/** Type of comd6 register + * I2C command register 6 + */ +typedef union { + struct { + /** command6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command6:14; + uint32_t reserved_14:17; + /** command6_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command6_done:1; + }; + uint32_t val; +} i2c_comd6_reg_t; + +/** Type of comd7 register + * I2C command register 7 + */ +typedef union { + struct { + /** command7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command7:14; + uint32_t reserved_14:17; + /** command7_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command7_done:1; + }; + uint32_t val; +} i2c_comd7_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656050; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + volatile i2c_slave_addr_reg_t slave_addr; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + uint32_t reserved_054; + volatile i2c_comd0_reg_t comd0; + volatile i2c_comd1_reg_t comd1; + volatile i2c_comd2_reg_t comd2; + volatile i2c_comd3_reg_t comd3; + volatile i2c_comd4_reg_t comd4; + volatile i2c_comd5_reg_t comd5; + volatile i2c_comd6_reg_t comd6; + volatile i2c_comd7_reg_t comd7; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; + uint32_t reserved_088[28]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} i2c_dev_t; + +extern i2c_dev_t I2C0; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2s_reg.h b/components/soc/esp32c5/include/soc/i2s_reg.h new file mode 100644 index 0000000000..21d7c89692 --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2s_reg.h @@ -0,0 +1,1268 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2S_INT_RAW_REG register + * I2S interrupt raw register, valid in level. + */ +#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) +/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S) +#define I2S_RX_DONE_INT_RAW_V 0x00000001U +#define I2S_RX_DONE_INT_RAW_S 0 +/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S) +#define I2S_TX_DONE_INT_RAW_V 0x00000001U +#define I2S_TX_DONE_INT_RAW_S 1 +/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001U +#define I2S_RX_HUNG_INT_RAW_S 2 +/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001U +#define I2S_TX_HUNG_INT_RAW_S 3 + +/** I2S_INT_ST_REG register + * I2S interrupt status register. + */ +#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) +/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S) +#define I2S_RX_DONE_INT_ST_V 0x00000001U +#define I2S_RX_DONE_INT_ST_S 0 +/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S) +#define I2S_TX_DONE_INT_ST_V 0x00000001U +#define I2S_TX_DONE_INT_ST_S 1 +/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001U +#define I2S_RX_HUNG_INT_ST_S 2 +/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001U +#define I2S_TX_HUNG_INT_ST_S 3 + +/** I2S_INT_ENA_REG register + * I2S interrupt enable register. + */ +#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) +/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S) +#define I2S_RX_DONE_INT_ENA_V 0x00000001U +#define I2S_RX_DONE_INT_ENA_S 0 +/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S) +#define I2S_TX_DONE_INT_ENA_V 0x00000001U +#define I2S_TX_DONE_INT_ENA_S 1 +/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001U +#define I2S_RX_HUNG_INT_ENA_S 2 +/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001U +#define I2S_TX_HUNG_INT_ENA_S 3 + +/** I2S_INT_CLR_REG register + * I2S interrupt clear register. + */ +#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) +/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S) +#define I2S_RX_DONE_INT_CLR_V 0x00000001U +#define I2S_RX_DONE_INT_CLR_S 0 +/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S) +#define I2S_TX_DONE_INT_CLR_V 0x00000001U +#define I2S_TX_DONE_INT_CLR_S 1 +/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001U +#define I2S_RX_HUNG_INT_CLR_S 2 +/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001U +#define I2S_TX_HUNG_INT_CLR_S 3 + +/** I2S_RX_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20) +/** I2S_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001U +#define I2S_RX_RESET_S 0 +/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001U +#define I2S_RX_FIFO_RESET_S 1 +/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001U +#define I2S_RX_START_S 2 +/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001U +#define I2S_RX_SLAVE_MOD_S 3 +/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ +#define I2S_RX_STOP_MODE 0x00000003U +#define I2S_RX_STOP_MODE_M (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S) +#define I2S_RX_STOP_MODE_V 0x00000003U +#define I2S_RX_STOP_MODE_S 4 +/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ +#define I2S_RX_MONO (BIT(6)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001U +#define I2S_RX_MONO_S 6 +/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001U +#define I2S_RX_BIG_ENDIAN_S 7 +/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S) +#define I2S_RX_UPDATE_V 0x00000001U +#define I2S_RX_UPDATE_S 8 +/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S) +#define I2S_RX_MONO_FST_VLD_V 0x00000001U +#define I2S_RX_MONO_FST_VLD_S 9 +/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_RX_PCM_CONF 0x00000003U +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000003U +#define I2S_RX_PCM_CONF_S 10 +/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001U +#define I2S_RX_PCM_BYPASS_S 12 +/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ +#define I2S_RX_MSB_SHIFT (BIT(13)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001U +#define I2S_RX_MSB_SHIFT_S 13 +/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S) +#define I2S_RX_LEFT_ALIGN_V 0x00000001U +#define I2S_RX_LEFT_ALIGN_S 15 +/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S) +#define I2S_RX_24_FILL_EN_V 0x00000001U +#define I2S_RX_24_FILL_EN_S 16 +/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S) +#define I2S_RX_WS_IDLE_POL_V 0x00000001U +#define I2S_RX_WS_IDLE_POL_S 17 +/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S) +#define I2S_RX_BIT_ORDER_V 0x00000001U +#define I2S_RX_BIT_ORDER_S 18 +/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S) +#define I2S_RX_TDM_EN_V 0x00000001U +#define I2S_RX_TDM_EN_S 19 +/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S) +#define I2S_RX_PDM_EN_V 0x00000001U +#define I2S_RX_PDM_EN_S 20 +/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ +#define I2S_RX_BCK_DIV_NUM 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_RX_BCK_DIV_NUM_S 21 + +/** I2S_TX_CONF_REG register + * I2S TX configure register + */ +#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24) +/** I2S_TX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001U +#define I2S_TX_RESET_S 0 +/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001U +#define I2S_TX_FIFO_RESET_S 1 +/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001U +#define I2S_TX_START_S 2 +/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001U +#define I2S_TX_SLAVE_MOD_S 3 +/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ +#define I2S_TX_STOP_EN (BIT(4)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001U +#define I2S_TX_STOP_EN_S 4 +/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ +#define I2S_TX_CHAN_EQUAL (BIT(5)) +#define I2S_TX_CHAN_EQUAL_M (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S) +#define I2S_TX_CHAN_EQUAL_V 0x00000001U +#define I2S_TX_CHAN_EQUAL_S 5 +/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ +#define I2S_TX_MONO (BIT(6)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001U +#define I2S_TX_MONO_S 6 +/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001U +#define I2S_TX_BIG_ENDIAN_S 7 +/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S) +#define I2S_TX_UPDATE_V 0x00000001U +#define I2S_TX_UPDATE_S 8 +/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S) +#define I2S_TX_MONO_FST_VLD_V 0x00000001U +#define I2S_TX_MONO_FST_VLD_S 9 +/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define I2S_TX_PCM_CONF 0x00000003U +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000003U +#define I2S_TX_PCM_CONF_S 10 +/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001U +#define I2S_TX_PCM_BYPASS_S 12 +/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ +#define I2S_TX_MSB_SHIFT (BIT(13)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001U +#define I2S_TX_MSB_SHIFT_S 13 +/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ +#define I2S_TX_BCK_NO_DLY (BIT(14)) +#define I2S_TX_BCK_NO_DLY_M (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S) +#define I2S_TX_BCK_NO_DLY_V 0x00000001U +#define I2S_TX_BCK_NO_DLY_S 14 +/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S) +#define I2S_TX_LEFT_ALIGN_V 0x00000001U +#define I2S_TX_LEFT_ALIGN_S 15 +/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S) +#define I2S_TX_24_FILL_EN_V 0x00000001U +#define I2S_TX_24_FILL_EN_S 16 +/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S) +#define I2S_TX_WS_IDLE_POL_V 0x00000001U +#define I2S_TX_WS_IDLE_POL_S 17 +/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S) +#define I2S_TX_BIT_ORDER_V 0x00000001U +#define I2S_TX_BIT_ORDER_S 18 +/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S) +#define I2S_TX_TDM_EN_V 0x00000001U +#define I2S_TX_TDM_EN_S 19 +/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S) +#define I2S_TX_PDM_EN_V 0x00000001U +#define I2S_TX_PDM_EN_S 20 +/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ +#define I2S_TX_BCK_DIV_NUM 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003FU +#define I2S_TX_BCK_DIV_NUM_S 21 +/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ +#define I2S_TX_CHAN_MOD 0x00000007U +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007U +#define I2S_TX_CHAN_MOD_S 27 +/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ +#define I2S_SIG_LOOPBACK (BIT(30)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001U +#define I2S_SIG_LOOPBACK_S 30 + +/** I2S_RX_CONF1_REG register + * I2S RX configure register 1 + */ +#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28) +/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_RX_TDM_WS_WIDTH 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_M (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S) +#define I2S_RX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_RX_TDM_WS_WIDTH_S 0 +/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_RX_BITS_MOD 0x0000001FU +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000001FU +#define I2S_RX_BITS_MOD_S 14 +/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ +#define I2S_RX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_M (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_RX_HALF_SAMPLE_BITS_S 19 +/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ +#define I2S_RX_TDM_CHAN_BITS 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_M (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S) +#define I2S_RX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_RX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_CONF1_REG register + * I2S TX configure register 1 + */ +#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c) +/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ +#define I2S_TX_TDM_WS_WIDTH 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_M (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S) +#define I2S_TX_TDM_WS_WIDTH_V 0x000001FFU +#define I2S_TX_TDM_WS_WIDTH_S 0 +/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define I2S_TX_BITS_MOD 0x0000001FU +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000001FU +#define I2S_TX_BITS_MOD_S 14 +/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ +#define I2S_TX_HALF_SAMPLE_BITS 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_M (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x000000FFU +#define I2S_TX_HALF_SAMPLE_BITS_S 19 +/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ +#define I2S_TX_TDM_CHAN_BITS 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_M (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S) +#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU +#define I2S_TX_TDM_CHAN_BITS_S 27 + +/** I2S_TX_PCM2PDM_CONF_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40) +/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ +#define I2S_TX_PDM_SINC_OSR2 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_M (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S) +#define I2S_TX_PDM_SINC_OSR2_V 0x0000000FU +#define I2S_TX_PDM_SINC_OSR2_S 1 +/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ +#define I2S_TX_PDM_PRESCALE 0x000000FFU +#define I2S_TX_PDM_PRESCALE_M (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S) +#define I2S_TX_PDM_PRESCALE_V 0x000000FFU +#define I2S_TX_PDM_PRESCALE_S 5 +/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_M (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S) +#define I2S_TX_PDM_HP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_HP_IN_SHIFT_S 13 +/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_M (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S) +#define I2S_TX_PDM_LP_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_LP_IN_SHIFT_S 15 +/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_M (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S) +#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 +/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S) +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x00000003U +#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 +/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 +/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ +#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) +#define I2S_TX_PDM_SIGMADELTA_DITHER_M (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S) +#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x00000001U +#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 +/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ +#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) +#define I2S_TX_PDM_DAC_2OUT_EN_M (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S) +#define I2S_TX_PDM_DAC_2OUT_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_2OUT_EN_S 23 +/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ +#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) +#define I2S_TX_PDM_DAC_MODE_EN_M (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S) +#define I2S_TX_PDM_DAC_MODE_EN_V 0x00000001U +#define I2S_TX_PDM_DAC_MODE_EN_S 24 +/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ +#define I2S_PCM2PDM_CONV_EN (BIT(25)) +#define I2S_PCM2PDM_CONV_EN_M (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S) +#define I2S_PCM2PDM_CONV_EN_V 0x00000001U +#define I2S_PCM2PDM_CONV_EN_S 25 + +/** I2S_TX_PCM2PDM_CONF1_REG register + * I2S TX PCM2PDM configuration register + */ +#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44) +/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ +#define I2S_TX_PDM_FP 0x000003FFU +#define I2S_TX_PDM_FP_M (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S) +#define I2S_TX_PDM_FP_V 0x000003FFU +#define I2S_TX_PDM_FP_S 0 +/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ +#define I2S_TX_PDM_FS 0x000003FFU +#define I2S_TX_PDM_FS_M (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S) +#define I2S_TX_PDM_FS_V 0x000003FFU +#define I2S_TX_PDM_FS_S 10 +/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_5 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_M (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S) +#define I2S_TX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_5_S 20 +/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_TX_IIR_HP_MULT12_0 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_M (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S) +#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_TX_IIR_HP_MULT12_0_S 23 + +/** I2S_RX_PDM2PCM_CONF_REG register + * I2S RX configure register + */ +#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48) +/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ +#define I2S_RX_PDM2PCM_EN (BIT(19)) +#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S) +#define I2S_RX_PDM2PCM_EN_V 0x00000001U +#define I2S_RX_PDM2PCM_EN_S 19 +/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U +#define I2S_RX_PDM_SINC_DSR_16_EN_S 20 +/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ +#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S) +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU +#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21 +/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ +#define I2S_RX_PDM_HP_BYPASS (BIT(25)) +#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S) +#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U +#define I2S_RX_PDM_HP_BYPASS_S 25 +/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ +#define I2S_RX_IIR_HP_MULT12_5 0x00000007U +#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S) +#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U +#define I2S_RX_IIR_HP_MULT12_5_S 26 +/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ +#define I2S_RX_IIR_HP_MULT12_0 0x00000007U +#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S) +#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U +#define I2S_RX_IIR_HP_MULT12_0_S 29 + +/** I2S_RX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50) +/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x00000001U +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S) +#define I2S_RX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN8_EN_S 8 +/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S) +#define I2S_RX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN9_EN_S 9 +/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S) +#define I2S_RX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN10_EN_S 10 +/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S) +#define I2S_RX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN11_EN_S 11 +/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S) +#define I2S_RX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN12_EN_S 12 +/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S) +#define I2S_RX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN13_EN_S 13 +/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S) +#define I2S_RX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN14_EN_S 14 +/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S) +#define I2S_RX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_RX_TDM_CHAN15_EN_S 15 +/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_M (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 + +/** I2S_TX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54) +/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S) +#define I2S_TX_TDM_CHAN0_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN0_EN_S 0 +/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S) +#define I2S_TX_TDM_CHAN1_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN1_EN_S 1 +/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S) +#define I2S_TX_TDM_CHAN2_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN2_EN_S 2 +/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S) +#define I2S_TX_TDM_CHAN3_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN3_EN_S 3 +/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S) +#define I2S_TX_TDM_CHAN4_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN4_EN_S 4 +/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S) +#define I2S_TX_TDM_CHAN5_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN5_EN_S 5 +/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S) +#define I2S_TX_TDM_CHAN6_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN6_EN_S 6 +/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S) +#define I2S_TX_TDM_CHAN7_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN7_EN_S 7 +/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S) +#define I2S_TX_TDM_CHAN8_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN8_EN_S 8 +/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S) +#define I2S_TX_TDM_CHAN9_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN9_EN_S 9 +/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S) +#define I2S_TX_TDM_CHAN10_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN10_EN_S 10 +/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S) +#define I2S_TX_TDM_CHAN11_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN11_EN_S 11 +/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S) +#define I2S_TX_TDM_CHAN12_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN12_EN_S 12 +/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S) +#define I2S_TX_TDM_CHAN13_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN13_EN_S 13 +/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S) +#define I2S_TX_TDM_CHAN14_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN14_EN_S 14 +/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S) +#define I2S_TX_TDM_CHAN15_EN_V 0x00000001U +#define I2S_TX_TDM_CHAN15_EN_S 15 +/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_M (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x00000001U +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 + +/** I2S_RX_TIMING_REG register + * I2S RX timing control register + */ +#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58) +/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD_IN_DM 0x00000003U +#define I2S_RX_SD_IN_DM_M (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S) +#define I2S_RX_SD_IN_DM_V 0x00000003U +#define I2S_RX_SD_IN_DM_S 0 +/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD1_IN_DM 0x00000003U +#define I2S_RX_SD1_IN_DM_M (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S) +#define I2S_RX_SD1_IN_DM_V 0x00000003U +#define I2S_RX_SD1_IN_DM_S 4 +/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0; + * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD2_IN_DM 0x00000003U +#define I2S_RX_SD2_IN_DM_M (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S) +#define I2S_RX_SD2_IN_DM_V 0x00000003U +#define I2S_RX_SD2_IN_DM_S 8 +/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0; + * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_SD3_IN_DM 0x00000003U +#define I2S_RX_SD3_IN_DM_M (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S) +#define I2S_RX_SD3_IN_DM_V 0x00000003U +#define I2S_RX_SD3_IN_DM_S 12 +/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_OUT_DM 0x00000003U +#define I2S_RX_WS_OUT_DM_M (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S) +#define I2S_RX_WS_OUT_DM_V 0x00000003U +#define I2S_RX_WS_OUT_DM_S 16 +/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_OUT_DM 0x00000003U +#define I2S_RX_BCK_OUT_DM_M (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S) +#define I2S_RX_BCK_OUT_DM_V 0x00000003U +#define I2S_RX_BCK_OUT_DM_S 20 +/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_WS_IN_DM 0x00000003U +#define I2S_RX_WS_IN_DM_M (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S) +#define I2S_RX_WS_IN_DM_V 0x00000003U +#define I2S_RX_WS_IN_DM_S 24 +/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_RX_BCK_IN_DM 0x00000003U +#define I2S_RX_BCK_IN_DM_M (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S) +#define I2S_RX_BCK_IN_DM_V 0x00000003U +#define I2S_RX_BCK_IN_DM_S 28 + +/** I2S_TX_TIMING_REG register + * I2S TX timing control register + */ +#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c) +/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD_OUT_DM 0x00000003U +#define I2S_TX_SD_OUT_DM_M (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S) +#define I2S_TX_SD_OUT_DM_V 0x00000003U +#define I2S_TX_SD_OUT_DM_S 0 +/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_SD1_OUT_DM 0x00000003U +#define I2S_TX_SD1_OUT_DM_M (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S) +#define I2S_TX_SD1_OUT_DM_V 0x00000003U +#define I2S_TX_SD1_OUT_DM_S 4 +/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_OUT_DM 0x00000003U +#define I2S_TX_WS_OUT_DM_M (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S) +#define I2S_TX_WS_OUT_DM_V 0x00000003U +#define I2S_TX_WS_OUT_DM_S 16 +/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_OUT_DM 0x00000003U +#define I2S_TX_BCK_OUT_DM_M (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S) +#define I2S_TX_BCK_OUT_DM_V 0x00000003U +#define I2S_TX_BCK_OUT_DM_S 20 +/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_WS_IN_DM 0x00000003U +#define I2S_TX_WS_IN_DM_M (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S) +#define I2S_TX_WS_IN_DM_V 0x00000003U +#define I2S_TX_WS_IN_DM_S 24 +/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define I2S_TX_BCK_IN_DM 0x00000003U +#define I2S_TX_BCK_IN_DM_M (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S) +#define I2S_TX_BCK_IN_DM_V 0x00000003U +#define I2S_TX_BCK_IN_DM_S 28 + +/** I2S_LC_HUNG_CONF_REG register + * I2S HUNG configure register. + */ +#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60) +/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ +#define I2S_LC_FIFO_TIMEOUT 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FFU +#define I2S_LC_FIFO_TIMEOUT_S 0 +/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007U +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/** I2S_RXEOF_NUM_REG register + * I2S RX data number control register. + */ +#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64) +/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ +#define I2S_RX_EOF_NUM 0x00000FFFU +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0x00000FFFU +#define I2S_RX_EOF_NUM_S 0 + +/** I2S_CONF_SIGLE_DATA_REG register + * I2S signal data register + */ +#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68) +/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ +#define I2S_SINGLE_DATA 0xFFFFFFFFU +#define I2S_SINGLE_DATA_M (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S) +#define I2S_SINGLE_DATA_V 0xFFFFFFFFU +#define I2S_SINGLE_DATA_S 0 + +/** I2S_STATE_REG register + * I2S TX status register + */ +#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c) +/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001U +#define I2S_TX_IDLE_S 0 + +/** I2S_ETM_CONF_REG register + * I2S ETM configure register + */ +#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70) +/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_TX_SEND_WORD_NUM 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_M (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S) +#define I2S_ETM_TX_SEND_WORD_NUM_V 0x000003FFU +#define I2S_ETM_TX_SEND_WORD_NUM_S 0 +/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ +#define I2S_ETM_RX_RECEIVE_WORD_NUM 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_M (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S) +#define I2S_ETM_RX_RECEIVE_WORD_NUM_V 0x000003FFU +#define I2S_ETM_RX_RECEIVE_WORD_NUM_S 10 + +/** I2S_FIFO_CNT_REG register + * I2S sync counter register + */ +#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74) +/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0; + * tx fifo counter value. + */ +#define I2S_TX_FIFO_CNT 0x7FFFFFFFU +#define I2S_TX_FIFO_CNT_M (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S) +#define I2S_TX_FIFO_CNT_V 0x7FFFFFFFU +#define I2S_TX_FIFO_CNT_S 0 +/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx fifo counter. + */ +#define I2S_TX_FIFO_CNT_RST (BIT(31)) +#define I2S_TX_FIFO_CNT_RST_M (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S) +#define I2S_TX_FIFO_CNT_RST_V 0x00000001U +#define I2S_TX_FIFO_CNT_RST_S 31 + +/** I2S_BCK_CNT_REG register + * I2S sync counter register + */ +#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78) +/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0; + * tx bck counter value. + */ +#define I2S_TX_BCK_CNT 0x7FFFFFFFU +#define I2S_TX_BCK_CNT_M (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S) +#define I2S_TX_BCK_CNT_V 0x7FFFFFFFU +#define I2S_TX_BCK_CNT_S 0 +/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx bck counter. + */ +#define I2S_TX_BCK_CNT_RST (BIT(31)) +#define I2S_TX_BCK_CNT_RST_M (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S) +#define I2S_TX_BCK_CNT_RST_V 0x00000001U +#define I2S_TX_BCK_CNT_RST_S 31 + +/** I2S_CLK_GATE_REG register + * Clock gate register + */ +#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c) +/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ +#define I2S_CLK_EN (BIT(0)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001U +#define I2S_CLK_EN_S 0 + +/** I2S_DATE_REG register + * Version control register + */ +#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80) +/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024; + * I2S version control register + */ +#define I2S_DATE 0x0FFFFFFFU +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0x0FFFFFFFU +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/i2s_struct.h b/components/soc/esp32c5/include/soc/i2s_struct.h new file mode 100644 index 0000000000..3d5a63923a --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2s_struct.h @@ -0,0 +1,1007 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt registers */ +/** Type of int_raw register + * I2S interrupt raw register, valid in level. + */ +typedef union { + struct { + /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_raw:1; + /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_raw:1; + /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_raw_reg_t; + +/** Type of int_st register + * I2S interrupt status register. + */ +typedef union { + struct { + /** rx_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_st_reg_t; + +/** Type of int_ena register + * I2S interrupt enable register. + */ +typedef union { + struct { + /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_ena_reg_t; + +/** Type of int_clr register + * I2S interrupt clear register. + */ +typedef union { + struct { + /** rx_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_done_int interrupt + */ + uint32_t tx_done_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + uint32_t tx_hung_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} i2s_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of rx_conf register + * I2S RX configure register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ + uint32_t rx_reset:1; + /** rx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ + uint32_t rx_fifo_reset:1; + /** rx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ + uint32_t rx_start:1; + /** rx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ + uint32_t rx_slave_mod:1; + /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ + uint32_t rx_stop_mode:2; + /** rx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable receiver in mono mode + */ + uint32_t rx_mono:1; + /** rx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ + uint32_t rx_big_endian:1; + /** rx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t rx_update:1; + /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ + uint32_t rx_mono_fst_vld:1; + /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t rx_pcm_conf:2; + /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + uint32_t rx_pcm_bypass:1; + /** rx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ + uint32_t rx_msb_shift:1; + uint32_t reserved_14:1; + /** rx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ + uint32_t rx_left_align:1; + /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ + uint32_t rx_24_fill_en:1; + /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ + uint32_t rx_ws_idle_pol:1; + /** rx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ + uint32_t rx_bit_order:1; + /** rx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ + uint32_t rx_tdm_en:1; + /** rx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ + uint32_t rx_pdm_en:1; + /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + uint32_t rx_bck_div_num:6; + uint32_t reserved_27:5; + }; + uint32_t val; +} i2s_rx_conf_reg_t; + +/** Type of rx_conf1 register + * I2S RX configure register 1 + */ +typedef union { + struct { + /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t rx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t rx_bits_mod:5; + /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Rx half sample bits -1. + */ + uint32_t rx_half_sample_bits:8; + /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ + uint32_t rx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_rx_conf1_reg_t; + +/** Type of rx_pdm2pcm_conf register + * I2S RX configure register + */ +typedef union { + struct { + uint32_t reserved_0:19; + /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ + uint32_t rx_pdm2pcm_en:1; + /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ + uint32_t rx_pdm_sinc_dsr_16_en:1; + /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ + uint32_t rx_pdm2pcm_amplify_num:4; + /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ + uint32_t rx_pdm_hp_bypass:1; + /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t rx_iir_hp_mult12_5:3; + /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t rx_iir_hp_mult12_0:3; + }; + uint32_t val; +} i2s_rx_pdm2pcm_conf_reg_t; + +/** Type of rx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan0_en:1; + /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan1_en:1; + /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan2_en:1; + /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan3_en:1; + /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan4_en:1; + /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan5_en:1; + /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan6_en:1; + /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan7_en:1; + /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan8_en:1; + /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan9_en:1; + /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan10_en:1; + /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan11_en:1; + /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan12_en:1; + /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan13_en:1; + /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan14_en:1; + /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 + * in this channel. + */ + uint32_t rx_tdm_chan15_en:1; + /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t rx_tdm_tot_chan_num:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_rx_tdm_ctrl_reg_t; + +/** Type of rxeof_num register + * I2S RX data number control register. + */ +typedef union { + struct { + /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ + uint32_t rx_eof_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_rxeof_num_reg_t; + + +/** Group: TX Control and configuration registers */ +/** Type of tx_conf register + * I2S TX configure register + */ +typedef union { + struct { + /** tx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + uint32_t tx_reset:1; + /** tx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Tx AFIFO + */ + uint32_t tx_fifo_reset:1; + /** tx_start : R/W/SC; bitpos: [2]; default: 0; + * Set this bit to start transmitting data + */ + uint32_t tx_start:1; + /** tx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave transmitter mode + */ + uint32_t tx_slave_mod:1; + /** tx_stop_en : R/W; bitpos: [4]; default: 1; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + */ + uint32_t tx_stop_en:1; + /** tx_chan_equal : R/W; bitpos: [5]; default: 0; + * 1: The value of Left channel data is equal to the value of right channel data in + * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is + * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + */ + uint32_t tx_chan_equal:1; + /** tx_mono : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + uint32_t tx_mono:1; + /** tx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr + * value. + */ + uint32_t tx_big_endian:1; + /** tx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t tx_update:1; + /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S TX mono mode. 0: The second + * channel data value is valid in I2S TX mono mode. + */ + uint32_t tx_mono_fst_vld:1; + /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; + * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t tx_pcm_conf:2; + /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + uint32_t tx_pcm_bypass:1; + /** tx_msb_shift : R/W; bitpos: [13]; default: 1; + * Set this bit to enable transmitter in Phillips standard mode + */ + uint32_t tx_msb_shift:1; + /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1; + * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to + * generate pos/neg edge in master mode. + */ + uint32_t tx_bck_no_dly:1; + /** tx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + */ + uint32_t tx_left_align:1; + /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + */ + uint32_t tx_24_fill_en:1; + /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: + * WS should be 1 when sending left channel data, and WS is 0in right channel. + */ + uint32_t tx_ws_idle_pol:1; + /** tx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is + * sent first. + */ + uint32_t tx_bit_order:1; + /** tx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Tx mode . 0: Disable. + */ + uint32_t tx_tdm_en:1; + /** tx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Tx mode . 0: Disable. + */ + uint32_t tx_pdm_en:1; + /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + uint32_t tx_bck_div_num:6; + /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + uint32_t tx_chan_mod:3; + /** sig_loopback : R/W; bitpos: [30]; default: 0; + * Enable signal loop back mode with transmitter module and receiver module sharing + * the same WS and BCK signals. + */ + uint32_t sig_loopback:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2s_tx_conf_reg_t; + +/** Type of tx_conf1 register + * I2S TX configure register 1 + */ +typedef union { + struct { + /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; + * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * + * T_bck + */ + uint32_t tx_tdm_ws_width:9; + uint32_t reserved_9:5; + /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15; + * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: + * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t tx_bits_mod:5; + /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; + * I2S Tx half sample bits -1. + */ + uint32_t tx_half_sample_bits:8; + /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; + * The Tx bit number for each channel minus 1in TDM mode. + */ + uint32_t tx_tdm_chan_bits:5; + }; + uint32_t val; +} i2s_tx_conf1_reg_t; + +/** Type of tx_pcm2pdm_conf register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; + * I2S TX PDM OSR2 value + */ + uint32_t tx_pdm_sinc_osr2:4; + /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; + * I2S TX PDM prescale for sigmadelta + */ + uint32_t tx_pdm_prescale:8; + /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_hp_in_shift:2; + /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_lp_in_shift:2; + /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sinc_in_shift:2; + /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; + * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + */ + uint32_t tx_pdm_sigmadelta_in_shift:2; + /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; + * I2S TX PDM sigmadelta dither2 value + */ + uint32_t tx_pdm_sigmadelta_dither2:1; + /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; + * I2S TX PDM sigmadelta dither value + */ + uint32_t tx_pdm_sigmadelta_dither:1; + /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; + * I2S TX PDM dac mode enable + */ + uint32_t tx_pdm_dac_2out_en:1; + /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; + * I2S TX PDM dac 2channel enable + */ + uint32_t tx_pdm_dac_mode_en:1; + /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; + * I2S TX PDM Converter enable + */ + uint32_t pcm2pdm_conv_en:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf_reg_t; + +/** Type of tx_pcm2pdm_conf1 register + * I2S TX PCM2PDM configuration register + */ +typedef union { + struct { + /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; + * I2S TX PDM Fp + */ + uint32_t tx_pdm_fp:10; + /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; + * I2S TX PDM Fs + */ + uint32_t tx_pdm_fs:10; + /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + * I2S_TX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t tx_iir_hp_mult12_5:3; + /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; + * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + * I2S_TX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t tx_iir_hp_mult12_0:3; + uint32_t reserved_26:6; + }; + uint32_t val; +} i2s_tx_pcm2pdm_conf1_reg_t; + +/** Type of tx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan0_en:1; + /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan1_en:1; + /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan2_en:1; + /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan3_en:1; + /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan4_en:1; + /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan5_en:1; + /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan6_en:1; + /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan7_en:1; + /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan8_en:1; + /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan9_en:1; + /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan10_en:1; + /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan11_en:1; + /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan12_en:1; + /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan13_en:1; + /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan14_en:1; + /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; + * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output + * 0 in this channel. + */ + uint32_t tx_tdm_chan15_en:1; + /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t tx_tdm_tot_chan_num:4; + /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; + * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and + * only the data of the enabled channels is sent, then this bit should be set. Clear + * it when all the data stored in DMA TX buffer is for enabled channels. + */ + uint32_t tx_tdm_skip_msk_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} i2s_tx_tdm_ctrl_reg_t; + + +/** Group: RX clock and timing registers */ +/** Type of rx_timing register + * I2S RX timing control register + */ +typedef union { + struct { + /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd_in_dm:2; + uint32_t reserved_2:2; + /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd1_in_dm:2; + uint32_t reserved_6:2; + /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0; + * The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd2_in_dm:2; + uint32_t reserved_10:2; + /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0; + * The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd3_in_dm:2; + uint32_t reserved_14:2; + /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_out_dm:2; + uint32_t reserved_18:2; + /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_out_dm:2; + uint32_t reserved_22:2; + /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_in_dm:2; + uint32_t reserved_26:2; + /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_rx_timing_reg_t; + + +/** Group: TX clock and timing registers */ +/** Type of tx_timing register + * I2S TX timing control register + */ +typedef union { + struct { + /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd_out_dm:2; + uint32_t reserved_2:2; + /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; + * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_sd1_out_dm:2; + uint32_t reserved_6:10; + /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_out_dm:2; + uint32_t reserved_18:2; + /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_out_dm:2; + uint32_t reserved_22:2; + /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_ws_in_dm:2; + uint32_t reserved_26:2; + /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t tx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2s_tx_timing_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of lc_hung_conf register + * I2S HUNG configure register. + */ +typedef union { + struct { + /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ + uint32_t lc_fifo_timeout:8; + /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + uint32_t lc_fifo_timeout_shift:3; + /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + uint32_t lc_fifo_timeout_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2s_lc_hung_conf_reg_t; + +/** Type of conf_sigle_data register + * I2S signal data register + */ +typedef union { + struct { + /** single_data : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ + uint32_t single_data:32; + }; + uint32_t val; +} i2s_conf_sigle_data_reg_t; + + +/** Group: TX status registers */ +/** Type of state register + * I2S TX status register + */ +typedef union { + struct { + /** tx_idle : RO; bitpos: [0]; default: 1; + * 1: i2s_tx is idle state. 0: i2s_tx is working. + */ + uint32_t tx_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_state_reg_t; + + +/** Group: ETM registers */ +/** Type of etm_conf register + * I2S ETM configure register + */ +typedef union { + struct { + /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; + * I2S ETM send x words event. When sending word number of + * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_tx_send_word_num:10; + /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; + * I2S ETM receive x words event. When receiving word number of + * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + */ + uint32_t etm_rx_receive_word_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} i2s_etm_conf_reg_t; + + +/** Group: Sync counter registers */ +/** Type of fifo_cnt register + * I2S sync counter register + */ +typedef union { + struct { + /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0; + * tx fifo counter value. + */ + uint32_t tx_fifo_cnt:31; + /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx fifo counter. + */ + uint32_t tx_fifo_cnt_rst:1; + }; + uint32_t val; +} i2s_fifo_cnt_reg_t; + +/** Type of bck_cnt register + * I2S sync counter register + */ +typedef union { + struct { + /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0; + * tx bck counter value. + */ + uint32_t tx_bck_cnt:31; + /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset tx bck counter. + */ + uint32_t tx_bck_cnt_rst:1; + }; + uint32_t val; +} i2s_bck_cnt_reg_t; + + +/** Group: Clock registers */ +/** Type of clk_gate register + * Clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} i2s_clk_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36713024; + * I2S version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} i2s_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile i2s_int_raw_reg_t int_raw; + volatile i2s_int_st_reg_t int_st; + volatile i2s_int_ena_reg_t int_ena; + volatile i2s_int_clr_reg_t int_clr; + uint32_t reserved_01c; + volatile i2s_rx_conf_reg_t rx_conf; + volatile i2s_tx_conf_reg_t tx_conf; + volatile i2s_rx_conf1_reg_t rx_conf1; + volatile i2s_tx_conf1_reg_t tx_conf1; + uint32_t reserved_030[4]; + volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; + volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; + volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf; + uint32_t reserved_04c; + volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; + volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; + volatile i2s_rx_timing_reg_t rx_timing; + volatile i2s_tx_timing_reg_t tx_timing; + volatile i2s_lc_hung_conf_reg_t lc_hung_conf; + volatile i2s_rxeof_num_reg_t rxeof_num; + volatile i2s_conf_sigle_data_reg_t conf_sigle_data; + volatile i2s_state_reg_t state; + volatile i2s_etm_conf_reg_t etm_conf; + volatile i2s_fifo_cnt_reg_t fifo_cnt; + volatile i2s_bck_cnt_reg_t bck_cnt; + volatile i2s_clk_gate_reg_t clk_gate; + volatile i2s_date_reg_t date; +} i2s_dev_t; + +extern i2s_dev_t I2S0; + +#ifndef __cplusplus +_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h new file mode 100644 index 0000000000..5e67e185b3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h @@ -0,0 +1,135 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_ANA_MST_I2C0_CTRL_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) +/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) +#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CTRL_S 0 +/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) +#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U +#define LP_I2C_ANA_MST_I2C0_BUSY_S 25 + +/** LP_I2C_ANA_MST_I2C0_CONF_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) +/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) +#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_I2C0_CONF_S 0 +/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7; + * reserved + */ +#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) +#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_STATUS_S 24 + +/** LP_I2C_ANA_MST_I2C0_DATA_REG register + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) +/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S) +#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU +#define LP_I2C_ANA_MST_I2C0_RDATA_S 0 +/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1; + * need_des + */ +#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S) +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U +#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8 +/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1; + * need des + */ +#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11)) +#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S) +#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11 + +/** LP_I2C_ANA_MST_ANA_CONF1_REG register + * need_des + */ +#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) +/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) +#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU +#define LP_I2C_ANA_MST_ANA_CONF1_S 0 + +/** LP_I2C_ANA_MST_NOUSE_REG register + * need_des + */ +#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) +/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU +#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 + +/** LP_I2C_ANA_MST_DEVICE_EN_REG register + * need_des + */ +#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) +/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S) +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU +#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0 + +/** LP_I2C_ANA_MST_DATE_REG register + * need_des + */ +#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc) +/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU +#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S) +#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU +#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0 +/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28)) +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S) +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U +#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h new file mode 100644 index 0000000000..a87b4bdcd8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h @@ -0,0 +1,150 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of i2c0_ctrl register + * need_des + */ +typedef union { + struct { + /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0; + * need_des + */ + uint32_t i2c0_ctrl:25; + /** i2c0_busy : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t i2c0_busy:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_ctrl_reg_t; + +/** Type of i2c0_conf register + * need_des + */ +typedef union { + struct { + /** i2c0_conf : R/W; bitpos: [23:0]; default: 0; + * need_des + */ + uint32_t i2c0_conf:24; + /** i2c0_status : RO; bitpos: [31:24]; default: 7; + * reserved + */ + uint32_t i2c0_status:8; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_conf_reg_t; + +/** Type of i2c0_data register + * need_des + */ +typedef union { + struct { + /** i2c0_rdata : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t i2c0_rdata:8; + /** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1; + * need_des + */ + uint32_t i2c0_clk_sel:3; + /** i2c_mst_sel : R/W; bitpos: [11]; default: 1; + * need des + */ + uint32_t i2c_mst_sel:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ana_mst_i2c0_data_reg_t; + +/** Type of ana_conf1 register + * need_des + */ +typedef union { + struct { + /** ana_conf1 : R/W; bitpos: [23:0]; default: 0; + * need_des + */ + uint32_t ana_conf1:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_i2c_ana_mst_ana_conf1_reg_t; + +/** Type of nouse register + * need_des + */ +typedef union { + struct { + /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t i2c_mst_nouse:32; + }; + uint32_t val; +} lp_i2c_ana_mst_nouse_reg_t; + +/** Type of device_en register + * need_des + */ +typedef union { + struct { + /** i2c_device_en : R/W; bitpos: [11:0]; default: 0; + * need_des + */ + uint32_t i2c_device_en:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ana_mst_device_en_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873; + * need_des + */ + uint32_t i2c_mat_date:28; + /** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t i2c_mat_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_i2c_ana_mst_date_reg_t; + + +typedef struct { + volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; + volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; + volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data; + volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1; + volatile lp_i2c_ana_mst_nouse_reg_t nouse; + volatile lp_i2c_ana_mst_device_en_reg_t device_en; + uint32_t reserved_018[249]; + volatile lp_i2c_ana_mst_date_reg_t date; +} lp_i2c_ana_mst_dev_t; + +extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/include/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..4f7a3353f3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_wdt_reg.h @@ -0,0 +1,324 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/include/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..6195024ccb --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_wdt_struct.h @@ -0,0 +1,309 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of config0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of config1 register + * need_des + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of config2 register + * need_des + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of config3 register + * need_des + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of config4 register + * need_des + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of swd_config register + * need_des + */ +typedef union { + struct { + /** swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t swd_reset_flag:1; + uint32_t reserved_1:17; + /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t swd_auto_feed_en:1; + /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t swd_rst_flag_clr:1; + /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t swd_signal_width:10; + /** swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t swd_disable:1; + /** swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of swd_wprotect register + * need_des + */ +typedef union { + struct { + /** swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_raw:1; + /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ + uint32_t lp_wdt_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct { + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; + uint32_t reserved_034[242]; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mcpwm_reg.h b/components/soc/esp32c5/include/soc/mcpwm_reg.h new file mode 100644 index 0000000000..2c5d5957a7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mcpwm_reg.h @@ -0,0 +1,4514 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU +#define MCPWM_CLK_PRESCALE_S 0 + +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer0, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer0 period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control register. + */ +#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer0.\\0: If PWM timer0 starts, then + * stops at TEZ\\1: If timer0 starts, then stops at TEP\\2: PWM timer0 starts and runs + * on\\3: Timer0 starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U +#define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer0.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 + +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER0_SYNCI_EN_S 0 +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer0 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer0 reload on sync event. + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer0's direction when timer0 mode is up-down mode.\\0: + * Increase\\1: Decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer0 counter value. + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer0 counter direction.\\0: Increment\\1: Decrement + */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_DIRECTION_S 16 + +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer1, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer1 period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control register. + */ +#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer1.\\0: If PWM timer1 starts, then + * stops at TEZ\\1: If timer1 starts, then stops at TEP\\2: PWM timer1 starts and runs + * on\\3: Timer1 starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U +#define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer1.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 + +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer1 reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER1_SYNCI_EN_S 0 +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer1 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer1 reload on sync event. + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer1's direction when timer1 mode is up-down mode.\\0: + * Increase\\1: Decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer1 counter value. + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer1 counter direction.\\0: Increment\\1: Decrement + */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_DIRECTION_S 16 + +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer2, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer2 period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control register. + */ +#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer2.\\0: If PWM timer2 starts, then + * stops at TEZ\\1: If timer2 starts, then stops at TEP\\2: PWM timer2 starts and runs + * on\\3: Timer2 starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U +#define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer2.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 + +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer2 reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER2_SYNCI_EN_S 0 +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer2 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer2 reload on sync event. + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer2's direction when timer2 mode is up-down mode.\\0: + * Increase\\1: Decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer2 counter value. + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer2 counter direction.\\0: Increment\\1: Decrement + */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_DIRECTION_S 16 + +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection register for PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 + +/** MCPWM_OPERATOR_TIMERSEL_REG register + * PWM operator's timer select register + */ +#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 + +/** MCPWM_GEN0_STMP_CFG_REG register + * Generator0 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c) +/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 0 time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_M (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S) +#define MCPWM_GEN0_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_A_UPMETHOD_S 0 +/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 0 time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_M (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S) +#define MCPWM_GEN0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_B_UPMETHOD_S 4 +/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_M (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S) +#define MCPWM_GEN0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_A_SHDW_FULL_S 8 +/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_M (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S) +#define MCPWM_GEN0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN0_B_SHDW_FULL_S 9 + +/** MCPWM_GEN0_TSTMP_A_REG register + * Generator0 time stamp A's shadow register + */ +#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40) +/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 0 time stamp A's shadow register. + */ +#define MCPWM_GEN0_A 0x0000FFFFU +#define MCPWM_GEN0_A_M (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S) +#define MCPWM_GEN0_A_V 0x0000FFFFU +#define MCPWM_GEN0_A_S 0 + +/** MCPWM_GEN0_TSTMP_B_REG register + * Generator0 time stamp B's shadow register + */ +#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44) +/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 0 time stamp B's shadow register. + */ +#define MCPWM_GEN0_B 0x0000FFFFU +#define MCPWM_GEN0_B_M (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S) +#define MCPWM_GEN0_B_V 0x0000FFFFU +#define MCPWM_GEN0_B_S 0 + +/** MCPWM_GEN0_CFG0_REG register + * Generator0 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 0's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 0 event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 0 event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 + +/** MCPWM_GEN0_FORCE_REG register + * Generator0 output signal force mode register. + */ +#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator0.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM0 A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM0 B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM0 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM0 A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM0 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM0 B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN0_A_REG register + * PWM0 output signal A actions configuration register + */ +#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM0 A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U +#define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM0 A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM0 A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM0 A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM0 A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM0 A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM0 A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM0 A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM0 A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM0 A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM0 A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM0 A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 + +/** MCPWM_GEN0_B_REG register + * PWM0 output signal B actions configuration register + */ +#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM0 B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U +#define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM0 B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM0 B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM0 B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM0 B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM0 B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM0 B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM0 B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM0 B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM0 B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM0 B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM0 B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 + +/** MCPWM_DT0_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58) +/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_M (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S) +#define MCPWM_DT0_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_FED_UPMETHOD_S 0 +/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_M (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S) +#define MCPWM_DT0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT0_RED_UPMETHOD_S 4 +/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT0_DEB_MODE (BIT(8)) +#define MCPWM_DT0_DEB_MODE_M (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S) +#define MCPWM_DT0_DEB_MODE_V 0x00000001U +#define MCPWM_DT0_DEB_MODE_S 8 +/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DT0_A_OUTSWAP (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_M (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S) +#define MCPWM_DT0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_A_OUTSWAP_S 9 +/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DT0_B_OUTSWAP (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_M (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S) +#define MCPWM_DT0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT0_B_OUTSWAP_S 10 +/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DT0_RED_INSEL (BIT(11)) +#define MCPWM_DT0_RED_INSEL_M (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S) +#define MCPWM_DT0_RED_INSEL_V 0x00000001U +#define MCPWM_DT0_RED_INSEL_S 11 +/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DT0_FED_INSEL (BIT(12)) +#define MCPWM_DT0_FED_INSEL_M (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S) +#define MCPWM_DT0_FED_INSEL_V 0x00000001U +#define MCPWM_DT0_FED_INSEL_S 12 +/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_M (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S) +#define MCPWM_DT0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_RED_OUTINVERT_S 13 +/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_M (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S) +#define MCPWM_DT0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT0_FED_OUTINVERT_S 14 +/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_M (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S) +#define MCPWM_DT0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_A_OUTBYPASS_S 15 +/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_M (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S) +#define MCPWM_DT0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT0_B_OUTBYPASS_S 16 +/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 0 clock selection.\\0: PWM_clk\\1: PT_clk + */ +#define MCPWM_DT0_CLK_SEL (BIT(17)) +#define MCPWM_DT0_CLK_SEL_M (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S) +#define MCPWM_DT0_CLK_SEL_V 0x00000001U +#define MCPWM_DT0_CLK_SEL_S 17 + +/** MCPWM_DT0_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c) +/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DT0_FED 0x0000FFFFU +#define MCPWM_DT0_FED_M (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S) +#define MCPWM_DT0_FED_V 0x0000FFFFU +#define MCPWM_DT0_FED_S 0 + +/** MCPWM_DT0_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60) +/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DT0_RED 0x0000FFFFU +#define MCPWM_DT0_RED_M (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S) +#define MCPWM_DT0_RED_V 0x0000FFFFU +#define MCPWM_DT0_RED_S 0 + +/** MCPWM_CARRIER0_CFG_REG register + * Carrier0 configuration register + */ +#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64) +/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier0.\\0: Bypassed\\1: Enabled + */ +#define MCPWM_CARRIER0_EN (BIT(0)) +#define MCPWM_CARRIER0_EN_M (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S) +#define MCPWM_CARRIER0_EN_V 0x00000001U +#define MCPWM_CARRIER0_EN_S 0 +/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier0 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CARRIER0_PRESCALE 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_M (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S) +#define MCPWM_CARRIER0_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER0_PRESCALE_S 1 +/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CARRIER0_DUTY 0x00000007U +#define MCPWM_CARRIER0_DUTY_M (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S) +#define MCPWM_CARRIER0_DUTY_V 0x00000007U +#define MCPWM_CARRIER0_DUTY_S 5 +/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CARRIER0_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_M (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S) +#define MCPWM_CARRIER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER0_OSHTWTH_S 8 +/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM0 A and PWM0 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_M (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S) +#define MCPWM_CARRIER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_OUT_INVERT_S 12 +/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM0 A and PWM0 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_M (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S) +#define MCPWM_CARRIER0_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER0_IN_INVERT_S 13 + +/** MCPWM_FH0_CFG0_REG register + * PWM0 A and PWM0 B trip events actions configuration register + */ +#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68) +/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_SW_CBC (BIT(0)) +#define MCPWM_FH0_SW_CBC_M (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S) +#define MCPWM_FH0_SW_CBC_V 0x00000001U +#define MCPWM_FH0_SW_CBC_S 0 +/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F2_CBC (BIT(1)) +#define MCPWM_FH0_F2_CBC_M (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S) +#define MCPWM_FH0_F2_CBC_V 0x00000001U +#define MCPWM_FH0_F2_CBC_S 1 +/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F1_CBC (BIT(2)) +#define MCPWM_FH0_F1_CBC_M (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S) +#define MCPWM_FH0_F1_CBC_V 0x00000001U +#define MCPWM_FH0_F1_CBC_S 2 +/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F0_CBC (BIT(3)) +#define MCPWM_FH0_F0_CBC_M (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S) +#define MCPWM_FH0_F0_CBC_V 0x00000001U +#define MCPWM_FH0_F0_CBC_S 3 +/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_SW_OST (BIT(4)) +#define MCPWM_FH0_SW_OST_M (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S) +#define MCPWM_FH0_SW_OST_V 0x00000001U +#define MCPWM_FH0_SW_OST_S 4 +/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F2_OST (BIT(5)) +#define MCPWM_FH0_F2_OST_M (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S) +#define MCPWM_FH0_F2_OST_V 0x00000001U +#define MCPWM_FH0_F2_OST_S 5 +/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F1_OST (BIT(6)) +#define MCPWM_FH0_F1_OST_M (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S) +#define MCPWM_FH0_F1_OST_V 0x00000001U +#define MCPWM_FH0_F1_OST_S 6 +/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH0_F0_OST (BIT(7)) +#define MCPWM_FH0_F0_OST_M (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S) +#define MCPWM_FH0_F0_OST_V 0x00000001U +#define MCPWM_FH0_F0_OST_S 7 +/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_CBC_D 0x00000003U +#define MCPWM_FH0_A_CBC_D_M (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S) +#define MCPWM_FH0_A_CBC_D_V 0x00000003U +#define MCPWM_FH0_A_CBC_D_S 8 +/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_CBC_U 0x00000003U +#define MCPWM_FH0_A_CBC_U_M (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S) +#define MCPWM_FH0_A_CBC_U_V 0x00000003U +#define MCPWM_FH0_A_CBC_U_S 10 +/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM0 A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_OST_D 0x00000003U +#define MCPWM_FH0_A_OST_D_M (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S) +#define MCPWM_FH0_A_OST_D_V 0x00000003U +#define MCPWM_FH0_A_OST_D_S 12 +/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM0 A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_A_OST_U 0x00000003U +#define MCPWM_FH0_A_OST_U_M (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S) +#define MCPWM_FH0_A_OST_U_V 0x00000003U +#define MCPWM_FH0_A_OST_U_S 14 +/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_CBC_D 0x00000003U +#define MCPWM_FH0_B_CBC_D_M (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S) +#define MCPWM_FH0_B_CBC_D_V 0x00000003U +#define MCPWM_FH0_B_CBC_D_S 16 +/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_CBC_U 0x00000003U +#define MCPWM_FH0_B_CBC_U_M (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S) +#define MCPWM_FH0_B_CBC_U_V 0x00000003U +#define MCPWM_FH0_B_CBC_U_S 18 +/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM0 B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_OST_D 0x00000003U +#define MCPWM_FH0_B_OST_D_M (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S) +#define MCPWM_FH0_B_OST_D_V 0x00000003U +#define MCPWM_FH0_B_OST_D_S 20 +/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM0 B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH0_B_OST_U 0x00000003U +#define MCPWM_FH0_B_OST_U_M (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S) +#define MCPWM_FH0_B_OST_U_V 0x00000003U +#define MCPWM_FH0_B_OST_U_S 22 + +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c) +/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_FH0_CLR_OST (BIT(0)) +#define MCPWM_FH0_CLR_OST_M (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S) +#define MCPWM_FH0_CLR_OST_V 0x00000001U +#define MCPWM_FH0_CLR_OST_S 0 +/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ +#define MCPWM_FH0_CBCPULSE 0x00000003U +#define MCPWM_FH0_CBCPULSE_M (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S) +#define MCPWM_FH0_CBCPULSE_V 0x00000003U +#define MCPWM_FH0_CBCPULSE_S 1 +/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_FH0_FORCE_CBC (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_M (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S) +#define MCPWM_FH0_FORCE_CBC_V 0x00000001U +#define MCPWM_FH0_FORCE_CBC_S 3 +/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_FH0_FORCE_OST (BIT(4)) +#define MCPWM_FH0_FORCE_OST_M (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S) +#define MCPWM_FH0_FORCE_OST_V 0x00000001U +#define MCPWM_FH0_FORCE_OST_S 4 + +/** MCPWM_FH0_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70) +/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ +#define MCPWM_FH0_CBC_ON (BIT(0)) +#define MCPWM_FH0_CBC_ON_M (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S) +#define MCPWM_FH0_CBC_ON_V 0x00000001U +#define MCPWM_FH0_CBC_ON_S 0 +/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ +#define MCPWM_FH0_OST_ON (BIT(1)) +#define MCPWM_FH0_OST_ON_M (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S) +#define MCPWM_FH0_OST_ON_V 0x00000001U +#define MCPWM_FH0_OST_ON_S 1 + +/** MCPWM_GEN1_STMP_CFG_REG register + * Generator1 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74) +/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 1 time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_M (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S) +#define MCPWM_GEN1_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_A_UPMETHOD_S 0 +/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 1 time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_M (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S) +#define MCPWM_GEN1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_B_UPMETHOD_S 4 +/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_M (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S) +#define MCPWM_GEN1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_A_SHDW_FULL_S 8 +/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_M (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S) +#define MCPWM_GEN1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN1_B_SHDW_FULL_S 9 + +/** MCPWM_GEN1_TSTMP_A_REG register + * Generator1 time stamp A's shadow register + */ +#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78) +/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 1 time stamp A's shadow register. + */ +#define MCPWM_GEN1_A 0x0000FFFFU +#define MCPWM_GEN1_A_M (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S) +#define MCPWM_GEN1_A_V 0x0000FFFFU +#define MCPWM_GEN1_A_S 0 + +/** MCPWM_GEN1_TSTMP_B_REG register + * Generator1 time stamp B's shadow register + */ +#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c) +/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 1 time stamp B's shadow register. + */ +#define MCPWM_GEN1_B 0x0000FFFFU +#define MCPWM_GEN1_B_M (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S) +#define MCPWM_GEN1_B_V 0x0000FFFFU +#define MCPWM_GEN1_B_S 0 + +/** MCPWM_GEN1_CFG0_REG register + * Generator1 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 1's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 1 event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 1 event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 + +/** MCPWM_GEN1_FORCE_REG register + * Generator1 output signal force mode register. + */ +#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator1.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM1 A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM1 B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM1 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM1 A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM1 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM1 B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN1_A_REG register + * PWM1 output signal A actions configuration register + */ +#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM1 A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U +#define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM1 A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM1 A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM1 A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM1 A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM1 A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM1 A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM1 A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM1 A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM1 A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM1 A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM1 A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 + +/** MCPWM_GEN1_B_REG register + * PWM1 output signal B actions configuration register + */ +#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM1 B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U +#define MCPWM_GEN1_B_UTEZ_S 0 +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM1 B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM1 B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM1 B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM1 B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM1 B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM1 B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM1 B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM1 B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM1 B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM1 B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM1 B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 + +/** MCPWM_DT1_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90) +/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_M (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S) +#define MCPWM_DT1_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_FED_UPMETHOD_S 0 +/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_M (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S) +#define MCPWM_DT1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT1_RED_UPMETHOD_S 4 +/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT1_DEB_MODE (BIT(8)) +#define MCPWM_DT1_DEB_MODE_M (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S) +#define MCPWM_DT1_DEB_MODE_V 0x00000001U +#define MCPWM_DT1_DEB_MODE_S 8 +/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DT1_A_OUTSWAP (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_M (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S) +#define MCPWM_DT1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_A_OUTSWAP_S 9 +/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DT1_B_OUTSWAP (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_M (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S) +#define MCPWM_DT1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT1_B_OUTSWAP_S 10 +/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DT1_RED_INSEL (BIT(11)) +#define MCPWM_DT1_RED_INSEL_M (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S) +#define MCPWM_DT1_RED_INSEL_V 0x00000001U +#define MCPWM_DT1_RED_INSEL_S 11 +/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DT1_FED_INSEL (BIT(12)) +#define MCPWM_DT1_FED_INSEL_M (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S) +#define MCPWM_DT1_FED_INSEL_V 0x00000001U +#define MCPWM_DT1_FED_INSEL_S 12 +/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_M (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S) +#define MCPWM_DT1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_RED_OUTINVERT_S 13 +/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_M (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S) +#define MCPWM_DT1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT1_FED_OUTINVERT_S 14 +/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_M (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S) +#define MCPWM_DT1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_A_OUTBYPASS_S 15 +/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_M (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S) +#define MCPWM_DT1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT1_B_OUTBYPASS_S 16 +/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 1 clock selection.\\0: PWM_clk\\1: PT_clk + */ +#define MCPWM_DT1_CLK_SEL (BIT(17)) +#define MCPWM_DT1_CLK_SEL_M (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S) +#define MCPWM_DT1_CLK_SEL_V 0x00000001U +#define MCPWM_DT1_CLK_SEL_S 17 + +/** MCPWM_DT1_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94) +/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DT1_FED 0x0000FFFFU +#define MCPWM_DT1_FED_M (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S) +#define MCPWM_DT1_FED_V 0x0000FFFFU +#define MCPWM_DT1_FED_S 0 + +/** MCPWM_DT1_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98) +/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DT1_RED 0x0000FFFFU +#define MCPWM_DT1_RED_M (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S) +#define MCPWM_DT1_RED_V 0x0000FFFFU +#define MCPWM_DT1_RED_S 0 + +/** MCPWM_CARRIER1_CFG_REG register + * Carrier1 configuration register + */ +#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c) +/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier1.\\0: Bypassed\\1: Enabled + */ +#define MCPWM_CARRIER1_EN (BIT(0)) +#define MCPWM_CARRIER1_EN_M (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S) +#define MCPWM_CARRIER1_EN_V 0x00000001U +#define MCPWM_CARRIER1_EN_S 0 +/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier1 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1) + */ +#define MCPWM_CARRIER1_PRESCALE 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_M (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S) +#define MCPWM_CARRIER1_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER1_PRESCALE_S 1 +/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER1_DUTY / 8 + */ +#define MCPWM_CARRIER1_DUTY 0x00000007U +#define MCPWM_CARRIER1_DUTY_M (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S) +#define MCPWM_CARRIER1_DUTY_V 0x00000007U +#define MCPWM_CARRIER1_DUTY_S 5 +/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CARRIER1_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_M (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S) +#define MCPWM_CARRIER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER1_OSHTWTH_S 8 +/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM1 A and PWM1 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_M (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S) +#define MCPWM_CARRIER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_OUT_INVERT_S 12 +/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM1 A and PWM1 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_M (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S) +#define MCPWM_CARRIER1_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER1_IN_INVERT_S 13 + +/** MCPWM_FH1_CFG0_REG register + * PWM1 A and PWM1 B trip events actions configuration register + */ +#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0) +/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_SW_CBC (BIT(0)) +#define MCPWM_FH1_SW_CBC_M (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S) +#define MCPWM_FH1_SW_CBC_V 0x00000001U +#define MCPWM_FH1_SW_CBC_S 0 +/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F2_CBC (BIT(1)) +#define MCPWM_FH1_F2_CBC_M (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S) +#define MCPWM_FH1_F2_CBC_V 0x00000001U +#define MCPWM_FH1_F2_CBC_S 1 +/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F1_CBC (BIT(2)) +#define MCPWM_FH1_F1_CBC_M (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S) +#define MCPWM_FH1_F1_CBC_V 0x00000001U +#define MCPWM_FH1_F1_CBC_S 2 +/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F0_CBC (BIT(3)) +#define MCPWM_FH1_F0_CBC_M (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S) +#define MCPWM_FH1_F0_CBC_V 0x00000001U +#define MCPWM_FH1_F0_CBC_S 3 +/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_SW_OST (BIT(4)) +#define MCPWM_FH1_SW_OST_M (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S) +#define MCPWM_FH1_SW_OST_V 0x00000001U +#define MCPWM_FH1_SW_OST_S 4 +/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F2_OST (BIT(5)) +#define MCPWM_FH1_F2_OST_M (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S) +#define MCPWM_FH1_F2_OST_V 0x00000001U +#define MCPWM_FH1_F2_OST_S 5 +/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F1_OST (BIT(6)) +#define MCPWM_FH1_F1_OST_M (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S) +#define MCPWM_FH1_F1_OST_V 0x00000001U +#define MCPWM_FH1_F1_OST_S 6 +/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH1_F0_OST (BIT(7)) +#define MCPWM_FH1_F0_OST_M (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S) +#define MCPWM_FH1_F0_OST_V 0x00000001U +#define MCPWM_FH1_F0_OST_S 7 +/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_CBC_D 0x00000003U +#define MCPWM_FH1_A_CBC_D_M (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S) +#define MCPWM_FH1_A_CBC_D_V 0x00000003U +#define MCPWM_FH1_A_CBC_D_S 8 +/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_CBC_U 0x00000003U +#define MCPWM_FH1_A_CBC_U_M (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S) +#define MCPWM_FH1_A_CBC_U_V 0x00000003U +#define MCPWM_FH1_A_CBC_U_S 10 +/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM1 A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_OST_D 0x00000003U +#define MCPWM_FH1_A_OST_D_M (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S) +#define MCPWM_FH1_A_OST_D_V 0x00000003U +#define MCPWM_FH1_A_OST_D_S 12 +/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM1 A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_A_OST_U 0x00000003U +#define MCPWM_FH1_A_OST_U_M (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S) +#define MCPWM_FH1_A_OST_U_V 0x00000003U +#define MCPWM_FH1_A_OST_U_S 14 +/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_CBC_D 0x00000003U +#define MCPWM_FH1_B_CBC_D_M (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S) +#define MCPWM_FH1_B_CBC_D_V 0x00000003U +#define MCPWM_FH1_B_CBC_D_S 16 +/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_CBC_U 0x00000003U +#define MCPWM_FH1_B_CBC_U_M (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S) +#define MCPWM_FH1_B_CBC_U_V 0x00000003U +#define MCPWM_FH1_B_CBC_U_S 18 +/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM1 B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_OST_D 0x00000003U +#define MCPWM_FH1_B_OST_D_M (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S) +#define MCPWM_FH1_B_OST_D_V 0x00000003U +#define MCPWM_FH1_B_OST_D_S 20 +/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM1 B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH1_B_OST_U 0x00000003U +#define MCPWM_FH1_B_OST_U_M (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S) +#define MCPWM_FH1_B_OST_U_V 0x00000003U +#define MCPWM_FH1_B_OST_U_S 22 + +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4) +/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_FH1_CLR_OST (BIT(0)) +#define MCPWM_FH1_CLR_OST_M (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S) +#define MCPWM_FH1_CLR_OST_V 0x00000001U +#define MCPWM_FH1_CLR_OST_S 0 +/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ +#define MCPWM_FH1_CBCPULSE 0x00000003U +#define MCPWM_FH1_CBCPULSE_M (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S) +#define MCPWM_FH1_CBCPULSE_V 0x00000003U +#define MCPWM_FH1_CBCPULSE_S 1 +/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_FH1_FORCE_CBC (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_M (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S) +#define MCPWM_FH1_FORCE_CBC_V 0x00000001U +#define MCPWM_FH1_FORCE_CBC_S 3 +/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_FH1_FORCE_OST (BIT(4)) +#define MCPWM_FH1_FORCE_OST_M (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S) +#define MCPWM_FH1_FORCE_OST_V 0x00000001U +#define MCPWM_FH1_FORCE_OST_S 4 + +/** MCPWM_FH1_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8) +/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ +#define MCPWM_FH1_CBC_ON (BIT(0)) +#define MCPWM_FH1_CBC_ON_M (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S) +#define MCPWM_FH1_CBC_ON_V 0x00000001U +#define MCPWM_FH1_CBC_ON_S 0 +/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ +#define MCPWM_FH1_OST_ON (BIT(1)) +#define MCPWM_FH1_OST_ON_M (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S) +#define MCPWM_FH1_OST_ON_V 0x00000001U +#define MCPWM_FH1_OST_ON_S 1 + +/** MCPWM_GEN2_STMP_CFG_REG register + * Generator2 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac) +/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 2 time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_A_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_M (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S) +#define MCPWM_GEN2_A_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_A_UPMETHOD_S 0 +/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 2 time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_B_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_M (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S) +#define MCPWM_GEN2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_B_UPMETHOD_S 4 +/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_M (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S) +#define MCPWM_GEN2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_A_SHDW_FULL_S 8 +/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_M (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S) +#define MCPWM_GEN2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_GEN2_B_SHDW_FULL_S 9 + +/** MCPWM_GEN2_TSTMP_A_REG register + * Generator2 time stamp A's shadow register + */ +#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0) +/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 2 time stamp A's shadow register. + */ +#define MCPWM_GEN2_A 0x0000FFFFU +#define MCPWM_GEN2_A_M (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S) +#define MCPWM_GEN2_A_V 0x0000FFFFU +#define MCPWM_GEN2_A_S 0 + +/** MCPWM_GEN2_TSTMP_B_REG register + * Generator2 time stamp B's shadow register + */ +#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4) +/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 2 time stamp B's shadow register. + */ +#define MCPWM_GEN2_B 0x0000FFFFU +#define MCPWM_GEN2_B_M (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S) +#define MCPWM_GEN2_B_V 0x0000FFFFU +#define MCPWM_GEN2_B_S 0 + +/** MCPWM_GEN2_CFG0_REG register + * Generator2 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 2's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 2 event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 2 event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 + +/** MCPWM_GEN2_FORCE_REG register + * Generator2 output signal force mode register. + */ +#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator2.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM2 A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM2 B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM2 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM2 A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM2 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM2 B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN2_A_REG register + * PWM2 output signal A actions configuration register + */ +#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM2 A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U +#define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM2 A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM2 A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM2 A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM2 A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM2 A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM2 A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM2 A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM2 A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM2 A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM2 A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM2 A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 + +/** MCPWM_GEN2_B_REG register + * PWM2 output signal B actions configuration register + */ +#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM2 B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U +#define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM2 B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM2 B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM2 B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM2 B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM2 B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM2 B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM2 B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM2 B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM2 B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM2 B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM2 B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 + +/** MCPWM_DT2_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8) +/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_M (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S) +#define MCPWM_DT2_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_FED_UPMETHOD_S 0 +/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ +#define MCPWM_DT2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_M (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S) +#define MCPWM_DT2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DT2_RED_UPMETHOD_S 4 +/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DT2_DEB_MODE (BIT(8)) +#define MCPWM_DT2_DEB_MODE_M (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S) +#define MCPWM_DT2_DEB_MODE_V 0x00000001U +#define MCPWM_DT2_DEB_MODE_S 8 +/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DT2_A_OUTSWAP (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_M (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S) +#define MCPWM_DT2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_A_OUTSWAP_S 9 +/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DT2_B_OUTSWAP (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_M (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S) +#define MCPWM_DT2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DT2_B_OUTSWAP_S 10 +/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DT2_RED_INSEL (BIT(11)) +#define MCPWM_DT2_RED_INSEL_M (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S) +#define MCPWM_DT2_RED_INSEL_V 0x00000001U +#define MCPWM_DT2_RED_INSEL_S 11 +/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DT2_FED_INSEL (BIT(12)) +#define MCPWM_DT2_FED_INSEL_M (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S) +#define MCPWM_DT2_FED_INSEL_V 0x00000001U +#define MCPWM_DT2_FED_INSEL_S 12 +/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_M (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S) +#define MCPWM_DT2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_RED_OUTINVERT_S 13 +/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_M (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S) +#define MCPWM_DT2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DT2_FED_OUTINVERT_S 14 +/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_M (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S) +#define MCPWM_DT2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_A_OUTBYPASS_S 15 +/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_M (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S) +#define MCPWM_DT2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DT2_B_OUTBYPASS_S 16 +/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 2 clock selection.\\0: PWM_clk\\1: PT_clk + */ +#define MCPWM_DT2_CLK_SEL (BIT(17)) +#define MCPWM_DT2_CLK_SEL_M (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S) +#define MCPWM_DT2_CLK_SEL_V 0x00000001U +#define MCPWM_DT2_CLK_SEL_S 17 + +/** MCPWM_DT2_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc) +/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DT2_FED 0x0000FFFFU +#define MCPWM_DT2_FED_M (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S) +#define MCPWM_DT2_FED_V 0x0000FFFFU +#define MCPWM_DT2_FED_S 0 + +/** MCPWM_DT2_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0) +/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DT2_RED 0x0000FFFFU +#define MCPWM_DT2_RED_M (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S) +#define MCPWM_DT2_RED_V 0x0000FFFFU +#define MCPWM_DT2_RED_S 0 + +/** MCPWM_CARRIER2_CFG_REG register + * Carrier2 configuration register + */ +#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4) +/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier2.\\0: Bypassed\\1: Enabled + */ +#define MCPWM_CARRIER2_EN (BIT(0)) +#define MCPWM_CARRIER2_EN_M (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S) +#define MCPWM_CARRIER2_EN_V 0x00000001U +#define MCPWM_CARRIER2_EN_S 0 +/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier2 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1) + */ +#define MCPWM_CARRIER2_PRESCALE 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_M (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S) +#define MCPWM_CARRIER2_PRESCALE_V 0x0000000FU +#define MCPWM_CARRIER2_PRESCALE_S 1 +/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER2_DUTY / 8 + */ +#define MCPWM_CARRIER2_DUTY 0x00000007U +#define MCPWM_CARRIER2_DUTY_M (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S) +#define MCPWM_CARRIER2_DUTY_V 0x00000007U +#define MCPWM_CARRIER2_DUTY_S 5 +/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CARRIER2_OSHTWTH 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_M (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S) +#define MCPWM_CARRIER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CARRIER2_OSHTWTH_S 8 +/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM2 A and PWM2 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_M (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S) +#define MCPWM_CARRIER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_OUT_INVERT_S 12 +/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM2 A and PWM2 B for this + * submodule.\\0: Normal\\1: Invert + */ +#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_M (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S) +#define MCPWM_CARRIER2_IN_INVERT_V 0x00000001U +#define MCPWM_CARRIER2_IN_INVERT_S 13 + +/** MCPWM_FH2_CFG0_REG register + * PWM2 A and PWM2 B trip events actions configuration register + */ +#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8) +/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_SW_CBC (BIT(0)) +#define MCPWM_FH2_SW_CBC_M (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S) +#define MCPWM_FH2_SW_CBC_V 0x00000001U +#define MCPWM_FH2_SW_CBC_S 0 +/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F2_CBC (BIT(1)) +#define MCPWM_FH2_F2_CBC_M (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S) +#define MCPWM_FH2_F2_CBC_V 0x00000001U +#define MCPWM_FH2_F2_CBC_S 1 +/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F1_CBC (BIT(2)) +#define MCPWM_FH2_F1_CBC_M (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S) +#define MCPWM_FH2_F1_CBC_V 0x00000001U +#define MCPWM_FH2_F1_CBC_S 2 +/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F0_CBC (BIT(3)) +#define MCPWM_FH2_F0_CBC_M (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S) +#define MCPWM_FH2_F0_CBC_V 0x00000001U +#define MCPWM_FH2_F0_CBC_S 3 +/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_SW_OST (BIT(4)) +#define MCPWM_FH2_SW_OST_M (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S) +#define MCPWM_FH2_SW_OST_V 0x00000001U +#define MCPWM_FH2_SW_OST_S 4 +/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F2_OST (BIT(5)) +#define MCPWM_FH2_F2_OST_M (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S) +#define MCPWM_FH2_F2_OST_V 0x00000001U +#define MCPWM_FH2_F2_OST_S 5 +/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F1_OST (BIT(6)) +#define MCPWM_FH2_F1_OST_M (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S) +#define MCPWM_FH2_F1_OST_V 0x00000001U +#define MCPWM_FH2_F1_OST_S 6 +/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ +#define MCPWM_FH2_F0_OST (BIT(7)) +#define MCPWM_FH2_F0_OST_M (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S) +#define MCPWM_FH2_F0_OST_V 0x00000001U +#define MCPWM_FH2_F0_OST_S 7 +/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_CBC_D 0x00000003U +#define MCPWM_FH2_A_CBC_D_M (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S) +#define MCPWM_FH2_A_CBC_D_V 0x00000003U +#define MCPWM_FH2_A_CBC_D_S 8 +/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_CBC_U 0x00000003U +#define MCPWM_FH2_A_CBC_U_M (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S) +#define MCPWM_FH2_A_CBC_U_V 0x00000003U +#define MCPWM_FH2_A_CBC_U_S 10 +/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM2 A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_OST_D 0x00000003U +#define MCPWM_FH2_A_OST_D_M (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S) +#define MCPWM_FH2_A_OST_D_V 0x00000003U +#define MCPWM_FH2_A_OST_D_S 12 +/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM2 A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_A_OST_U 0x00000003U +#define MCPWM_FH2_A_OST_U_M (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S) +#define MCPWM_FH2_A_OST_U_V 0x00000003U +#define MCPWM_FH2_A_OST_U_S 14 +/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_CBC_D 0x00000003U +#define MCPWM_FH2_B_CBC_D_M (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S) +#define MCPWM_FH2_B_CBC_D_V 0x00000003U +#define MCPWM_FH2_B_CBC_D_S 16 +/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_CBC_U 0x00000003U +#define MCPWM_FH2_B_CBC_U_M (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S) +#define MCPWM_FH2_B_CBC_U_V 0x00000003U +#define MCPWM_FH2_B_CBC_U_S 18 +/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM2 B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_OST_D 0x00000003U +#define MCPWM_FH2_B_OST_D_M (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S) +#define MCPWM_FH2_B_OST_D_V 0x00000003U +#define MCPWM_FH2_B_OST_D_S 20 +/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM2 B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ +#define MCPWM_FH2_B_OST_U 0x00000003U +#define MCPWM_FH2_B_OST_U_M (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S) +#define MCPWM_FH2_B_OST_U_V 0x00000003U +#define MCPWM_FH2_B_OST_U_S 22 + +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc) +/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_FH2_CLR_OST (BIT(0)) +#define MCPWM_FH2_CLR_OST_M (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S) +#define MCPWM_FH2_CLR_OST_V 0x00000001U +#define MCPWM_FH2_CLR_OST_S 0 +/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ +#define MCPWM_FH2_CBCPULSE 0x00000003U +#define MCPWM_FH2_CBCPULSE_M (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S) +#define MCPWM_FH2_CBCPULSE_V 0x00000003U +#define MCPWM_FH2_CBCPULSE_S 1 +/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_FH2_FORCE_CBC (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_M (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S) +#define MCPWM_FH2_FORCE_CBC_V 0x00000001U +#define MCPWM_FH2_FORCE_CBC_S 3 +/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_FH2_FORCE_OST (BIT(4)) +#define MCPWM_FH2_FORCE_OST_M (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S) +#define MCPWM_FH2_FORCE_OST_V 0x00000001U +#define MCPWM_FH2_FORCE_OST_S 4 + +/** MCPWM_FH2_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0) +/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ +#define MCPWM_FH2_CBC_ON (BIT(0)) +#define MCPWM_FH2_CBC_ON_M (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S) +#define MCPWM_FH2_CBC_ON_V 0x00000001U +#define MCPWM_FH2_CBC_ON_S 0 +/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ +#define MCPWM_FH2_OST_ON (BIT(1)) +#define MCPWM_FH2_OST_ON_M (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S) +#define MCPWM_FH2_OST_ON_V 0x00000001U +#define MCPWM_FH2_OST_ON_S 1 + +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status register + */ +#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U +#define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 + +/** MCPWM_CAP_TIMER_CFG_REG register + * Capture timer configuration register + */ +#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U +#define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input.\\0: None\\1: Timer0 + * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: + * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: + * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with + * value in phase register + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 + +/** MCPWM_CAP_TIMER_PHASE_REG register + * Capture timer sync phase register + */ +#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec) +/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ +#define MCPWM_CAP_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration register + */ +#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U +#define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 0 after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAP0. Prescale value = + * PWM_CAP0_PRESCALE + 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 + +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration register + */ +#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U +#define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 1 after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAP1. Prescale value = + * PWM_CAP1_PRESCALE + 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 + +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration register + */ +#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable + */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U +#define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 2 after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAP2. Prescale value = + * PWM_CAP2_PRESCALE + 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 + +/** MCPWM_CAP_CH0_REG register + * CAP0 capture value register + */ +#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_S 0 + +/** MCPWM_CAP_CH1_REG register + * CAP1 capture value register + */ +#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_S 0 + +/** MCPWM_CAP_CH2_REG register + * CAP2 capture value register + */ +#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_S 0 + +/** MCPWM_CAP_STATUS_REG register + * Last capture trigger edge information register + */ +#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U +#define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 + +/** MCPWM_UPDATE_CFG_REG register + * Generator Update configuration register + */ +#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module.\\0: Disable\\1: Enable + */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U +#define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 + +/** MCPWM_INT_ENA_REG register + * Interrupt enable register + */ +#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) +#define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ENA_S 24 +/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) +#define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ENA_S 25 +/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) +#define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 + +/** MCPWM_INT_RAW_REG register + * Interrupt raw status register + */ +#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) +#define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_OST_INT_RAW_S 24 +/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) +#define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_OST_INT_RAW_S 25 +/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) +#define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 + +/** MCPWM_INT_ST_REG register + * Interrupt masked status register + */ +#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) +#define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ST_S 21 +/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) +#define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ST_S 22 +/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) +#define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ST_S 23 +/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) +#define MCPWM_TZ0_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ST_S 24 +/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) +#define MCPWM_TZ1_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ST_S 25 +/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) +#define MCPWM_TZ2_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 + +/** MCPWM_INT_CLR_REG register + * Interrupt clear register + */ +#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) +#define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_OST_INT_CLR_S 24 +/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) +#define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_OST_INT_CLR_S 25 +/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) +#define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 + +/** MCPWM_EVT_EN_REG register + * Event enable register + */ +#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120) +/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) +#define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) +#define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_STOP_EN_S 0 +/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) +#define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) +#define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_STOP_EN_S 1 +/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) +#define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) +#define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_STOP_EN_S 2 +/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) +#define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) +#define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEZ_EN_S 3 +/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) +#define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) +#define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEZ_EN_S 4 +/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) +#define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) +#define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEZ_EN_S 5 +/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) +#define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) +#define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEP_EN_S 6 +/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) +#define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) +#define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEP_EN_S 7 +/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) +#define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) +#define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEP_EN_S 8 +/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEA_EN (BIT(9)) +#define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) +#define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEA_EN_S 9 +/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEA_EN (BIT(10)) +#define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) +#define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEA_EN_S 10 +/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEA_EN (BIT(11)) +#define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) +#define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEA_EN_S 11 +/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEB_EN (BIT(12)) +#define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) +#define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEB_EN_S 12 +/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEB_EN (BIT(13)) +#define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) +#define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEB_EN_S 13 +/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event + * generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEB_EN (BIT(14)) +#define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) +#define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEB_EN_S 14 +/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_F0_EN (BIT(15)) +#define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) +#define MCPWM_EVT_F0_EN_V 0x00000001U +#define MCPWM_EVT_F0_EN_S 15 +/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_F1_EN (BIT(16)) +#define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) +#define MCPWM_EVT_F1_EN_V 0x00000001U +#define MCPWM_EVT_F1_EN_S 16 +/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_F2_EN (BIT(17)) +#define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) +#define MCPWM_EVT_F2_EN_V 0x00000001U +#define MCPWM_EVT_F2_EN_S 17 +/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_F0_CLR_EN (BIT(18)) +#define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) +#define MCPWM_EVT_F0_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F0_CLR_EN_S 18 +/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_F1_CLR_EN (BIT(19)) +#define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) +#define MCPWM_EVT_F1_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F1_CLR_EN_S 19 +/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_F2_CLR_EN (BIT(20)) +#define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) +#define MCPWM_EVT_F2_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F2_CLR_EN_S 20 +/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) +#define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) +#define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_CBC_EN_S 21 +/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) +#define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) +#define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_CBC_EN_S 22 +/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: + * Disable\\1: Enable + */ +#define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) +#define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) +#define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_CBC_EN_S 23 +/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TZ0_OST_EN (BIT(24)) +#define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) +#define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_OST_EN_S 24 +/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TZ1_OST_EN (BIT(25)) +#define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) +#define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_OST_EN_S 25 +/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: + * Enable + */ +#define MCPWM_EVT_TZ2_OST_EN (BIT(26)) +#define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) +#define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_OST_EN_S 26 +/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_CAP0_EN (BIT(27)) +#define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) +#define MCPWM_EVT_CAP0_EN_V 0x00000001U +#define MCPWM_EVT_CAP0_EN_S 27 +/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_CAP1_EN (BIT(28)) +#define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) +#define MCPWM_EVT_CAP1_EN_V 0x00000001U +#define MCPWM_EVT_CAP1_EN_S 28 +/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_CAP2_EN (BIT(29)) +#define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) +#define MCPWM_EVT_CAP2_EN_V 0x00000001U +#define MCPWM_EVT_CAP2_EN_S 29 + +/** MCPWM_TASK_EN_REG register + * Task enable register + */ +#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124) +/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) +#define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) +#define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_A_UP_EN_S 0 +/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) +#define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) +#define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_A_UP_EN_S 1 +/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) +#define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) +#define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_A_UP_EN_S 2 +/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) +#define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) +#define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_B_UP_EN_S 3 +/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) +#define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) +#define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_B_UP_EN_S 4 +/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) +#define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) +#define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_B_UP_EN_S 5 +/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_GEN_STOP_EN (BIT(6)) +#define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) +#define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U +#define MCPWM_TASK_GEN_STOP_EN_S 6 +/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) +#define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) +#define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_SYNC_EN_S 7 +/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) +#define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) +#define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_SYNC_EN_S 8 +/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) +#define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) +#define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_SYNC_EN_S 9 +/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 +/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 +/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 +/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: + * Enable + */ +#define MCPWM_TASK_TZ0_OST_EN (BIT(13)) +#define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) +#define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ0_OST_EN_S 13 +/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: + * Enable + */ +#define MCPWM_TASK_TZ1_OST_EN (BIT(14)) +#define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) +#define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ1_OST_EN_S 14 +/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: + * Enable + */ +#define MCPWM_TASK_TZ2_OST_EN (BIT(15)) +#define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) +#define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ2_OST_EN_S 15 +/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_CLR0_OST_EN (BIT(16)) +#define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) +#define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR0_OST_EN_S 16 +/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_CLR1_OST_EN (BIT(17)) +#define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) +#define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR1_OST_EN_S 17 +/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive.\\0: + * Disable\\1: Enable + */ +#define MCPWM_TASK_CLR2_OST_EN (BIT(18)) +#define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) +#define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR2_OST_EN_S 18 +/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CAP0_EN (BIT(19)) +#define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) +#define MCPWM_TASK_CAP0_EN_V 0x00000001U +#define MCPWM_TASK_CAP0_EN_S 19 +/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CAP1_EN (BIT(20)) +#define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) +#define MCPWM_TASK_CAP1_EN_V 0x00000001U +#define MCPWM_TASK_CAP1_EN_S 20 +/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + */ +#define MCPWM_TASK_CAP2_EN (BIT(21)) +#define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) +#define MCPWM_TASK_CAP2_EN_V 0x00000001U +#define MCPWM_TASK_CAP2_EN_S 21 + +/** MCPWM_EVT_EN2_REG register + * Event enable register2 + */ +#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128) +/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEE1_EN (BIT(0)) +#define MCPWM_EVT_OP0_TEE1_EN_M (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S) +#define MCPWM_EVT_OP0_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEE1_EN_S 0 +/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEE1_EN (BIT(1)) +#define MCPWM_EVT_OP1_TEE1_EN_M (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S) +#define MCPWM_EVT_OP1_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEE1_EN_S 1 +/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEE1_EN (BIT(2)) +#define MCPWM_EVT_OP2_TEE1_EN_M (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S) +#define MCPWM_EVT_OP2_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEE1_EN_S 2 +/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP0_TEE2_EN (BIT(3)) +#define MCPWM_EVT_OP0_TEE2_EN_M (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S) +#define MCPWM_EVT_OP0_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEE2_EN_S 3 +/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP1_TEE2_EN (BIT(4)) +#define MCPWM_EVT_OP1_TEE2_EN_M (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S) +#define MCPWM_EVT_OP1_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEE2_EN_S 4 +/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ +#define MCPWM_EVT_OP2_TEE2_EN (BIT(5)) +#define MCPWM_EVT_OP2_TEE2_EN_M (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S) +#define MCPWM_EVT_OP2_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEE2_EN_S 5 + +/** MCPWM_OP0_TSTMP_E1_REG register + * Generator0 timer stamp E1 value register + */ +#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c) +/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator0 timer stamp E1 value register + */ +#define MCPWM_OP0_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E1_M (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S) +#define MCPWM_OP0_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E1_S 0 + +/** MCPWM_OP0_TSTMP_E2_REG register + * Generator0 timer stamp E2 value register + */ +#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130) +/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator0 timer stamp E2 value register + */ +#define MCPWM_OP0_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E2_M (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S) +#define MCPWM_OP0_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E2_S 0 + +/** MCPWM_OP1_TSTMP_E1_REG register + * Generator1 timer stamp E1 value register + */ +#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134) +/** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator1 timer stamp E1 value register + */ +#define MCPWM_OP1_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E1_M (MCPWM_OP1_TSTMP_E1_V << MCPWM_OP1_TSTMP_E1_S) +#define MCPWM_OP1_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E1_S 0 + +/** MCPWM_OP1_TSTMP_E2_REG register + * Generator1 timer stamp E2 value register + */ +#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138) +/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator1 timer stamp E2 value register + */ +#define MCPWM_OP1_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E2_M (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S) +#define MCPWM_OP1_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E2_S 0 + +/** MCPWM_OP2_TSTMP_E1_REG register + * Generator2 timer stamp E1 value register + */ +#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c) +/** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator2 timer stamp E1 value register + */ +#define MCPWM_OP2_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E1_M (MCPWM_OP2_TSTMP_E1_V << MCPWM_OP2_TSTMP_E1_S) +#define MCPWM_OP2_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E1_S 0 + +/** MCPWM_OP2_TSTMP_E2_REG register + * Generator2 timer stamp E2 value register + */ +#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140) +/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator2 timer stamp E2 value register + */ +#define MCPWM_OP2_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E2_M (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S) +#define MCPWM_OP2_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E2_S 0 + +/** MCPWM_CLK_REG register + * Global configuration register + */ +#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U +#define MCPWM_CLK_EN_S 0 + +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU +#define MCPWM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mcpwm_struct.h b/components/soc/esp32c5/include/soc/mcpwm_struct.h new file mode 100644 index 0000000000..4eb4e6bc03 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mcpwm_struct.h @@ -0,0 +1,2031 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration register */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ + uint32_t clk_prescale:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + +/** Type of timern_cfg0 register + * PWM timern period and update method configuration register. + */ +typedef union { + struct { + /** timern_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timern, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMERn_PRESCALE + 1) + */ + uint32_t timern_prescale:8; + /** timern_period : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timern + */ + uint32_t timern_period:16; + /** timern_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timern period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ + uint32_t timern_period_upmethod:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} mcpwm_timern_cfg0_reg_t; + +/** Type of timern_cfg1 register + * PWM timern working mode and start/stop control register. + */ +typedef union { + struct { + /** timern_start : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timern.\\0: If PWM timern starts, then + * stops at TEZ\\1: If timern starts, then stops at TEP\\2: PWM timern starts and runs + * on\\3: Timern starts and stops at the next TEZ\\4: Timer0 starts and stops at the + * next TEP.\\TEP here and below means the event that happens when the timer equals to + * period + */ + uint32_t timern_start:3; + /** timern_mod : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timern.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ + uint32_t timern_mod:2; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_timern_cfg1_reg_t; + +/** Type of timern_sync register + * PWM timern sync function configuration register. + */ +typedef union { + struct { + /** timern_synci_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timern reloading with phase on sync input event + * is enabled.\\0: Disable\\1: Enable + */ + uint32_t timern_synci_en:1; + /** timern_sync_sw : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ + uint32_t timern_sync_sw:1; + /** timern_synco_sel : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timern sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ + uint32_t timern_synco_sel:2; + /** timern_phase : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timern reload on sync event. + */ + uint32_t timern_phase:16; + /** timern_phase_direction : R/W; bitpos: [20]; default: 0; + * Configures the PWM timern's direction when timern mode is up-down mode.\\0: + * Increase\\1: Decrease + */ + uint32_t timern_phase_direction:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} mcpwm_timern_sync_reg_t; + +/** Type of timern_status register + * PWM timern status register. + */ +typedef union { + struct { + /** timern_value : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timern counter value. + */ + uint32_t timern_value:16; + /** timern_direction : RO; bitpos: [16]; default: 0; + * Represents current PWM timern counter direction.\\0: Increment\\1: Decrement + */ + uint32_t timern_direction:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} mcpwm_timern_status_reg_t; + +/** Type of timer_synci_cfg register + * Synchronization input selection register for PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer0_syncisel:3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer1_syncisel:3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer2_syncisel:3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci0_invert:1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci1_invert:1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci2_invert:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * PWM operator's timer select register + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator0_timersel:2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator1_timersel:2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator2_timersel:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: cfgrep */ +/** Type of genn_stmp_cfg register + * Generatorn time stamp registers A and B transfer status and update method register + */ +typedef union { + struct { + /** genn_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator n time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t genn_a_upmethod:4; + /** genn_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator n time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t genn_b_upmethod:4; + /** genn_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ + uint32_t genn_a_shdw_full:1; + /** genn_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ + uint32_t genn_b_shdw_full:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_genn_stmp_cfg_reg_t; + +/** Type of genn_tstmp_a register + * Generatorn time stamp A's shadow register + */ +typedef union { + struct { + /** genn_a : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator n time stamp A's shadow register. + */ + uint32_t genn_a:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_tstmp_a_reg_t; + +/** Type of genn_tstmp_b register + * Generatorn time stamp B's shadow register + */ +typedef union { + struct { + /** genn_b : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator n time stamp B's shadow register. + */ + uint32_t genn_b:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_tstmp_b_reg_t; + +/** Type of genn_cfg0 register + * Generatorn fault event T0 and T1 configuration register + */ +typedef union { + struct { + /** genn_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator n's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t genn_cfg_upmethod:4; + /** genn_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator n event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ + uint32_t genn_t0_sel:3; + /** genn_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator n event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ + uint32_t genn_t1_sel:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_genn_cfg0_reg_t; + +/** Type of genn_force register + * Generatorn output signal force mode register. + */ +typedef union { + struct { + /** genn_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generatorn.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ + uint32_t genn_cntuforce_upmethod:6; + /** genn_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWMn A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ + uint32_t genn_a_cntuforce_mode:2; + /** genn_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWMn B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ + uint32_t genn_b_cntuforce_mode:2; + /** genn_a_nciforce : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWMn + * A, a toggle will trigger a force event. + */ + uint32_t genn_a_nciforce:1; + /** genn_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWMn A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ + uint32_t genn_a_nciforce_mode:2; + /** genn_b_nciforce : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWMn + * B, a toggle will trigger a force event. + */ + uint32_t genn_b_nciforce:1; + /** genn_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWMn B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ + uint32_t genn_b_nciforce_mode:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_force_reg_t; + +/** Type of genn_a register + * PWMn output signal A actions configuration register + */ +typedef union { + struct { + /** genn_a_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWMn A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_utez:2; + /** genn_a_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWMn A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_utep:2; + /** genn_a_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWMn A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_utea:2; + /** genn_a_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWMn A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_uteb:2; + /** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWMn A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_ut0:2; + /** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWMn A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_ut1:2; + /** genn_a_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWMn A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dtez:2; + /** genn_a_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWMn A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dtep:2; + /** genn_a_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWMn A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dtea:2; + /** genn_a_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWMn A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dteb:2; + /** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWMn A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dt0:2; + /** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWMn A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_a_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_genn_a_reg_t; + +/** Type of genn_b register + * PWMn output signal B actions configuration register + */ +typedef union { + struct { + /** genn_b_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWMn B triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_utez:2; + /** genn_b_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWMn B triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_utep:2; + /** genn_b_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWMn B triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_utea:2; + /** genn_b_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWMn B triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_uteb:2; + /** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWMn B triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_ut0:2; + /** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWMn B triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_ut1:2; + /** genn_b_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWMn B triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dtez:2; + /** genn_b_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWMn B triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dtep:2; + /** genn_b_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWMn B triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dtea:2; + /** genn_b_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWMn B triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dteb:2; + /** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWMn B triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dt0:2; + /** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWMn B triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t genn_b_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_genn_b_reg_t; + +/** Type of dtn_cfg register + * Dead time configuration register + */ +typedef union { + struct { + /** dtn_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t dtn_fed_upmethod:4; + /** dtn_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t dtn_red_upmethod:4; + /** dtn_deb_mode : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t dtn_deb_mode:1; + /** dtn_a_outswap : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ + uint32_t dtn_a_outswap:1; + /** dtn_b_outswap : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ + uint32_t dtn_b_outswap:1; + /** dtn_red_insel : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ + uint32_t dtn_red_insel:1; + /** dtn_fed_insel : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ + uint32_t dtn_fed_insel:1; + /** dtn_red_outinvert : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ + uint32_t dtn_red_outinvert:1; + /** dtn_fed_outinvert : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ + uint32_t dtn_fed_outinvert:1; + /** dtn_a_outbypass : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ + uint32_t dtn_a_outbypass:1; + /** dtn_b_outbypass : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ + uint32_t dtn_b_outbypass:1; + /** dtn_clk_sel : R/W; bitpos: [17]; default: 0; + * Configures dead time generator n clock selection.\\0: PWM_clk\\1: PT_clk + */ + uint32_t dtn_clk_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} mcpwm_dtn_cfg_reg_t; + +/** Type of dtn_fed_cfg register + * Falling edge delay (FED) shadow register + */ +typedef union { + struct { + /** dtn_fed : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ + uint32_t dtn_fed:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dtn_fed_cfg_reg_t; + +/** Type of dtn_red_cfg register + * Rising edge delay (RED) shadow register + */ +typedef union { + struct { + /** dtn_red : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ + uint32_t dtn_red:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dtn_red_cfg_reg_t; + +/** Type of carriern_cfg register + * Carriern configuration register + */ +typedef union { + struct { + /** carriern_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carriern.\\0: Bypassed\\1: Enabled + */ + uint32_t carriern_en:1; + /** carriern_prescale : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carriern clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1) + */ + uint32_t carriern_prescale:4; + /** carriern_duty : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8 + */ + uint32_t carriern_duty:3; + /** carriern_oshtwth : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ + uint32_t carriern_oshtwth:4; + /** carriern_out_invert : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWMn A and PWMn B for this + * submodule.\\0: Normal\\1: Invert + */ + uint32_t carriern_out_invert:1; + /** carriern_in_invert : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWMn A and PWMn B for this + * submodule.\\0: Normal\\1: Invert + */ + uint32_t carriern_in_invert:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} mcpwm_carriern_cfg_reg_t; + +/** Type of fhn_cfg0 register + * PWMn A and PWMn B trip events actions configuration register + */ +typedef union { + struct { + /** fhn_sw_cbc : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_sw_cbc:1; + /** fhn_f2_cbc : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f2_cbc:1; + /** fhn_f1_cbc : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f1_cbc:1; + /** fhn_f0_cbc : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f0_cbc:1; + /** fhn_sw_ost : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_sw_ost:1; + /** fhn_f2_ost : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f2_ost:1; + /** fhn_f1_ost : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f1_ost:1; + /** fhn_f0_ost : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t fhn_f0_ost:1; + /** fhn_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_cbc_d:2; + /** fhn_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_cbc_u:2; + /** fhn_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWMn A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_ost_d:2; + /** fhn_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWMn A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_a_ost_u:2; + /** fhn_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_cbc_d:2; + /** fhn_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_cbc_u:2; + /** fhn_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWMn B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_ost_d:2; + /** fhn_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWMn B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t fhn_b_ost_u:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_fhn_cfg0_reg_t; + +/** Type of fhn_cfg1 register + * Software triggers for fault handler actions configuration register + */ +typedef union { + struct { + /** fhn_clr_ost : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ + uint32_t fhn_clr_ost:1; + /** fhn_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ + uint32_t fhn_cbcpulse:2; + /** fhn_force_cbc : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ + uint32_t fhn_force_cbc:1; + /** fhn_force_ost : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ + uint32_t fhn_force_ost:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_fhn_cfg1_reg_t; + +/** Type of fhn_status register + * Fault events status register + */ +typedef union { + struct { + /** fhn_cbc_on : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ + uint32_t fhn_cbc_on:1; + /** fhn_ost_on : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ + uint32_t fhn_ost_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mcpwm_fhn_status_reg_t; + + +/** Group: fault det */ +/** Type of fault_detect register + * Fault detection configuration and status register + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + */ + uint32_t f0_en:1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + */ + uint32_t f1_en:1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + */ + uint32_t f2_en:1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f0_pole:1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f1_pole:1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f2_pole:1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + */ + uint32_t event_f0:1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + */ + uint32_t event_f1:1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + */ + uint32_t event_f2:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: sync */ +/** Type of cap_timer_cfg register + * Capture timer configuration register + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + */ + uint32_t cap_timer_en:1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + */ + uint32_t cap_synci_en:1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input.\\0: None\\1: Timer0 + * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: + * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + */ + uint32_t cap_synci_sel:3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: + * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with + * value in phase register + */ + uint32_t cap_sync_sw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + + +/** Group: phase */ +/** Type of cap_timer_phase register + * Capture timer sync phase register + */ +typedef union { + struct { + /** cap_phase : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ + uint32_t cap_phase:32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + + +/** Group: cap_cfg */ +/** Type of cap_chn_cfg register + * Capture channel n configuration register + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable + */ + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel n after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on possitive edge of CAPn. Prescale value = + * PWM_CAPn_PRESCALE + 1 + */ + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel n + */ + uint32_t capn_sw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + + +/** Group: cap_ch */ +/** Type of cap_chn register + * CAPn capture value register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAPn + */ + uint32_t capn_value:32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + + +/** Group: edge */ +/** Type of cap_status register + * Last capture trigger edge information register + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + */ + uint32_t cap0_edge:1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + */ + uint32_t cap1_edge:1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + */ + uint32_t cap2_edge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: update */ +/** Type of update_cfg register + * Generator Update configuration register + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module.\\0: Disable\\1: Enable + */ + uint32_t global_up_en:1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ + uint32_t global_force_up:1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op0_up_en:1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ + uint32_t op0_force_up:1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op1_up_en:1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ + uint32_t op1_force_up:1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op2_up_en:1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ + uint32_t op2_force_up:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: Interrupt register */ +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena:1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena:1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena:1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena:1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena:1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena:1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena:1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena:1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena:1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_ena:1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_ena:1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_ena:1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_ena:1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_ena:1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_ena:1; + /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ + uint32_t cmpr0_tea_int_ena:1; + /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ + uint32_t cmpr1_tea_int_ena:1; + /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ + uint32_t cmpr2_tea_int_ena:1; + /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ + uint32_t cmpr0_teb_int_ena:1; + /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ + uint32_t cmpr1_teb_int_ena:1; + /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ + uint32_t cmpr2_teb_int_ena:1; + /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ + uint32_t tz0_cbc_int_ena:1; + /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ + uint32_t tz1_cbc_int_ena:1; + /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ + uint32_t tz2_cbc_int_ena:1; + /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_ena:1; + /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_ena:1; + /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_ena:1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_ena:1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_ena:1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ + uint32_t timer0_stop_int_raw:1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ + uint32_t timer1_stop_int_raw:1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ + uint32_t timer2_stop_int_raw:1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ + uint32_t timer0_tez_int_raw:1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ + uint32_t timer1_tez_int_raw:1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ + uint32_t timer2_tez_int_raw:1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ + uint32_t timer0_tep_int_raw:1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ + uint32_t timer1_tep_int_raw:1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ + uint32_t timer2_tep_int_raw:1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ + uint32_t fault0_int_raw:1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ + uint32_t fault1_int_raw:1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ + uint32_t fault2_int_raw:1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ + uint32_t fault0_clr_int_raw:1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ + uint32_t fault1_clr_int_raw:1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ + uint32_t fault2_clr_int_raw:1; + /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_raw:1; + /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_raw:1; + /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_raw:1; + /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_raw:1; + /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_raw:1; + /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_raw:1; + /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_raw:1; + /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_raw:1; + /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_raw:1; + /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ + uint32_t tz0_ost_int_raw:1; + /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ + uint32_t tz1_ost_int_raw:1; + /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ + uint32_t tz2_ost_int_raw:1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ + uint32_t cap0_int_raw:1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ + uint32_t cap1_int_raw:1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ + uint32_t cap2_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ + uint32_t timer0_stop_int_st:1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ + uint32_t timer1_stop_int_st:1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ + uint32_t timer2_stop_int_st:1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st:1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st:1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st:1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ + uint32_t timer0_tep_int_st:1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ + uint32_t timer1_tep_int_st:1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ + uint32_t timer2_tep_int_st:1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ + uint32_t fault0_int_st:1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ + uint32_t fault1_int_st:1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ + uint32_t fault2_int_st:1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ + uint32_t fault0_clr_int_st:1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ + uint32_t fault1_clr_int_st:1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ + uint32_t fault2_clr_int_st:1; + /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_st:1; + /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_st:1; + /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_st:1; + /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_st:1; + /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_st:1; + /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_st:1; + /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_st:1; + /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_st:1; + /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_st:1; + /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_st:1; + /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_st:1; + /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_st:1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ + uint32_t cap0_int_st:1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ + uint32_t cap1_int_st:1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ + uint32_t cap2_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr:1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr:1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr:1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr:1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr:1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr:1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr:1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr:1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr:1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_clr:1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_clr:1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_clr:1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_clr:1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_clr:1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_clr:1; + /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_clr:1; + /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_clr:1; + /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_clr:1; + /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_clr:1; + /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_clr:1; + /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_clr:1; + /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t tz0_cbc_int_clr:1; + /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t tz1_cbc_int_clr:1; + /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t tz2_cbc_int_clr:1; + /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_clr:1; + /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_clr:1; + /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_clr:1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_clr:1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_clr:1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: etm */ +/** Type of evt_en register + * Event enable register + */ +typedef union { + struct { + /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer0_stop_en:1; + /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer1_stop_en:1; + /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer2_stop_en:1; + /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer0_tez_en:1; + /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer1_tez_en:1; + /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer2_tez_en:1; + /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer0_tep_en:1; + /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer1_tep_en:1; + /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer2_tep_en:1; + /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tea_en:1; + /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tea_en:1; + /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tea_en:1; + /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_teb_en:1; + /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_teb_en:1; + /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_teb_en:1; + /** evt_f0_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f0_en:1; + /** evt_f1_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f1_en:1; + /** evt_f2_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f2_en:1; + /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f0_clr_en:1; + /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f1_clr_en:1; + /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f2_clr_en:1; + /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz0_cbc_en:1; + /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz1_cbc_en:1; + /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz2_cbc_en:1; + /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz0_ost_en:1; + /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz1_ost_en:1; + /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz2_ost_en:1; + /** evt_cap0_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap0_en:1; + /** evt_cap1_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap1_en:1; + /** evt_cap2_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap2_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_evt_en_reg_t; + +/** Type of task_en register + * Task enable register + */ +typedef union { + struct { + /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr0_a_up_en:1; + /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr1_a_up_en:1; + /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr2_a_up_en:1; + /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr0_b_up_en:1; + /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr1_b_up_en:1; + /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr2_b_up_en:1; + /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_gen_stop_en:1; + /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_sync_en:1; + /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_sync_en:1; + /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_sync_en:1; + /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer0_period_up_en:1; + /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer1_period_up_en:1; + /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer2_period_up_en:1; + /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz0_ost_en:1; + /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz1_ost_en:1; + /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz2_ost_en:1; + /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr0_ost_en:1; + /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr1_ost_en:1; + /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr2_ost_en:1; + /** task_cap0_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap0_en:1; + /** task_cap1_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap1_en:1; + /** task_cap2_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap2_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} mcpwm_task_en_reg_t; + +/** Type of evt_en2 register + * Event enable register2 + */ +typedef union { + struct { + /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tee1_en:1; + /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tee1_en:1; + /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tee1_en:1; + /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tee2_en:1; + /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tee2_en:1; + /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tee2_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_evt_en2_reg_t; + + +/** Group: tstmp */ +/** Type of opn_tstmp_e1 register + * Generatorn timer stamp E1 value register + */ +typedef union { + struct { + /** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E1 value register + */ + uint32_t opn_tstmp_e1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_opn_tstmp_e1_reg_t; + +/** Type of opn_tstmp_e2 register + * Generatorn timer stamp E2 value register + */ +typedef union { + struct { + /** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E2 value register + */ + uint32_t opn_tstmp_e2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_opn_tstmp_e2_reg_t; + +/** Type of clk register + * Global configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mcpwm_version_reg_t; + + +typedef struct { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timern_cfg0_reg_t timer0_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer0_cfg1; + volatile mcpwm_timern_sync_reg_t timer0_sync; + volatile mcpwm_timern_status_reg_t timer0_status; + volatile mcpwm_timern_cfg0_reg_t timer1_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer1_cfg1; + volatile mcpwm_timern_sync_reg_t timer1_sync; + volatile mcpwm_timern_status_reg_t timer1_status; + volatile mcpwm_timern_cfg0_reg_t timer2_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer2_cfg1; + volatile mcpwm_timern_sync_reg_t timer2_sync; + volatile mcpwm_timern_status_reg_t timer2_status; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen0_cfg0; + volatile mcpwm_genn_force_reg_t gen0_force; + volatile mcpwm_genn_a_reg_t gen0_a; + volatile mcpwm_genn_b_reg_t gen0_b; + volatile mcpwm_dtn_cfg_reg_t dt0_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier0_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1; + volatile mcpwm_fhn_status_reg_t fh0_status; + volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen1_cfg0; + volatile mcpwm_genn_force_reg_t gen1_force; + volatile mcpwm_genn_a_reg_t gen1_a; + volatile mcpwm_genn_b_reg_t gen1_b; + volatile mcpwm_dtn_cfg_reg_t dt1_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier1_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1; + volatile mcpwm_fhn_status_reg_t fh1_status; + volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen2_cfg0; + volatile mcpwm_genn_force_reg_t gen2_force; + volatile mcpwm_genn_a_reg_t gen2_a; + volatile mcpwm_genn_b_reg_t gen2_b; + volatile mcpwm_dtn_cfg_reg_t dt2_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier2_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1; + volatile mcpwm_fhn_status_reg_t fh2_status; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_evt_en_reg_t evt_en; + volatile mcpwm_task_en_reg_t task_en; + volatile mcpwm_evt_en2_reg_t evt_en2; + volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2; + volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2; + volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/parl_io_reg.h b/components/soc/esp32c5/include/soc/parl_io_reg.h new file mode 100644 index 0000000000..74a528017d --- /dev/null +++ b/components/soc/esp32c5/include/soc/parl_io_reg.h @@ -0,0 +1,480 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PARL_IO_RX_MODE_CFG_REG register + * Parallel RX Sampling mode configuration register. + */ +#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0) +/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ +#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S) +#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU +#define PARL_IO_RX_EXT_EN_SEL_S 21 +/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable data sampling by software. + */ +#define PARL_IO_RX_SW_EN (BIT(25)) +#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S) +#define PARL_IO_RX_SW_EN_V 0x00000001U +#define PARL_IO_RX_SW_EN_S 25 +/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0; + * Set this bit to invert the external enable signal. + */ +#define PARL_IO_RX_EXT_EN_INV (BIT(26)) +#define PARL_IO_RX_EXT_EN_INV_M (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S) +#define PARL_IO_RX_EXT_EN_INV_V 0x00000001U +#define PARL_IO_RX_EXT_EN_INV_S 26 +/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 4'd0: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 4'd1: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 4'd4: positive pulse start(data bit included) && length end + * 4'd5: positive pulse start(data bit excluded) && length end + */ +#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S) +#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x00000007U +#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 27 +/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 2'b00: external level enable mode + * 2'b01: external pulse enable mode + * 2'b10: internal software enable mode + */ +#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S) +#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U +#define PARL_IO_RX_SMP_MODE_SEL_S 30 + +/** PARL_IO_RX_DATA_CFG_REG register + * Parallel RX data configuration register. + */ +#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4) +/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ +#define PARL_IO_RX_BITLEN 0x0007FFFFU +#define PARL_IO_RX_BITLEN_M (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S) +#define PARL_IO_RX_BITLEN_V 0x0007FFFFU +#define PARL_IO_RX_BITLEN_S 9 +/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + */ +#define PARL_IO_RX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_RX_DATA_ORDER_INV_M (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S) +#define PARL_IO_RX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_RX_DATA_ORDER_INV_S 28 +/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ +#define PARL_IO_RX_BUS_WID_SEL 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S) +#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_RX_BUS_WID_SEL_S 29 + +/** PARL_IO_RX_GENRL_CFG_REG register + * Parallel RX general configuration register. + */ +#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8) +/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0; + * Set this bit to enable the clock gating of output rx clock. + */ +#define PARL_IO_RX_GATING_EN (BIT(12)) +#define PARL_IO_RX_GATING_EN_M (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S) +#define PARL_IO_RX_GATING_EN_V 0x00000001U +#define PARL_IO_RX_GATING_EN_S 12 +/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ +#define PARL_IO_RX_TIMEOUT_THRES 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_M (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S) +#define PARL_IO_RX_TIMEOUT_THRES_V 0x0000FFFFU +#define PARL_IO_RX_TIMEOUT_THRES_S 13 +/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to enable timeout function to generate error eof. + */ +#define PARL_IO_RX_TIMEOUT_EN (BIT(29)) +#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S) +#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U +#define PARL_IO_RX_TIMEOUT_EN_S 29 +/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by external enable signal. + */ +#define PARL_IO_RX_EOF_GEN_SEL (BIT(30)) +#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S) +#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_RX_EOF_GEN_SEL_S 30 + +/** PARL_IO_RX_START_CFG_REG register + * Parallel RX Start configuration register. + */ +#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc) +/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start rx data sampling. + */ +#define PARL_IO_RX_START (BIT(31)) +#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S) +#define PARL_IO_RX_START_V 0x00000001U +#define PARL_IO_RX_START_S 31 + +/** PARL_IO_TX_DATA_CFG_REG register + * Parallel TX data configuration register. + */ +#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10) +/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ +#define PARL_IO_TX_BITLEN 0x0007FFFFU +#define PARL_IO_TX_BITLEN_M (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S) +#define PARL_IO_TX_BITLEN_V 0x0007FFFFU +#define PARL_IO_TX_BITLEN_S 9 +/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + */ +#define PARL_IO_TX_DATA_ORDER_INV (BIT(28)) +#define PARL_IO_TX_DATA_ORDER_INV_M (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S) +#define PARL_IO_TX_DATA_ORDER_INV_V 0x00000001U +#define PARL_IO_TX_DATA_ORDER_INV_S 28 +/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ +#define PARL_IO_TX_BUS_WID_SEL 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S) +#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U +#define PARL_IO_TX_BUS_WID_SEL_S 29 + +/** PARL_IO_TX_START_CFG_REG register + * Parallel TX Start configuration register. + */ +#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14) +/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start tx data transmit. + */ +#define PARL_IO_TX_START (BIT(31)) +#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S) +#define PARL_IO_TX_START_V 0x00000001U +#define PARL_IO_TX_START_S 31 + +/** PARL_IO_TX_GENRL_CFG_REG register + * Parallel TX general configuration register. + */ +#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18) +/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0; + * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by DMA eof. + */ +#define PARL_IO_TX_EOF_GEN_SEL (BIT(13)) +#define PARL_IO_TX_EOF_GEN_SEL_M (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S) +#define PARL_IO_TX_EOF_GEN_SEL_V 0x00000001U +#define PARL_IO_TX_EOF_GEN_SEL_S 13 +/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ +#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S) +#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU +#define PARL_IO_TX_IDLE_VALUE_S 14 +/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0; + * Set this bit to enable the clock gating of output tx clock. + */ +#define PARL_IO_TX_GATING_EN (BIT(30)) +#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S) +#define PARL_IO_TX_GATING_EN_V 0x00000001U +#define PARL_IO_TX_GATING_EN_S 30 +/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable the output of tx data valid signal. + */ +#define PARL_IO_TX_VALID_OUTPUT_EN (BIT(31)) +#define PARL_IO_TX_VALID_OUTPUT_EN_M (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S) +#define PARL_IO_TX_VALID_OUTPUT_EN_V 0x00000001U +#define PARL_IO_TX_VALID_OUTPUT_EN_S 31 + +/** PARL_IO_FIFO_CFG_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c) +/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; + * Set this bit to reset async fifo in tx module. + */ +#define PARL_IO_TX_FIFO_SRST (BIT(30)) +#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S) +#define PARL_IO_TX_FIFO_SRST_V 0x00000001U +#define PARL_IO_TX_FIFO_SRST_S 30 +/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0; + * Set this bit to reset async fifo in rx module. + */ +#define PARL_IO_RX_FIFO_SRST (BIT(31)) +#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S) +#define PARL_IO_RX_FIFO_SRST_V 0x00000001U +#define PARL_IO_RX_FIFO_SRST_S 31 + +/** PARL_IO_REG_UPDATE_REG register + * Parallel IO FIFO configuration register. + */ +#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20) +/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0; + * Set this bit to update rx register configuration. + */ +#define PARL_IO_RX_REG_UPDATE (BIT(31)) +#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S) +#define PARL_IO_RX_REG_UPDATE_V 0x00000001U +#define PARL_IO_RX_REG_UPDATE_S 31 + +/** PARL_IO_ST_REG register + * Parallel IO module status register0. + */ +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24) +/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ +#define PARL_IO_TX_READY (BIT(31)) +#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S) +#define PARL_IO_TX_READY_V 0x00000001U +#define PARL_IO_TX_READY_S 31 + +/** PARL_IO_INT_ENA_REG register + * Parallel IO interrupt enable singal configuration register. + */ +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) +/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ENA (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S 1 +/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ENA (BIT(2)) +#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S) +#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ENA_S 2 + +/** PARL_IO_INT_RAW_REG register + * Parallel IO interrupt raw singal status register. + */ +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) +/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_RAW (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S) +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S 1 +/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_RAW (BIT(2)) +#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S) +#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U +#define PARL_IO_TX_EOF_INT_RAW_S 2 + +/** PARL_IO_INT_ST_REG register + * Parallel IO interrupt singal status register. + */ +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) +/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_ST (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_M (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S) +#define PARL_IO_RX_FIFO_WOVF_INT_ST_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_ST_S 1 +/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_ST (BIT(2)) +#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S) +#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U +#define PARL_IO_TX_EOF_INT_ST_S 2 + +/** PARL_IO_INT_CLR_REG register + * Parallel IO interrupt clear singal configuration register. + */ +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) +/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear TX_FIFO_REMPTY_INT. + */ +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0)) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S) +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U +#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0 +/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear RX_FIFO_WOVF_INT. + */ +#define PARL_IO_RX_FIFO_WOVF_INT_CLR (BIT(1)) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S) +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V 0x00000001U +#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S 1 +/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear TX_EOF_INT. + */ +#define PARL_IO_TX_EOF_INT_CLR (BIT(2)) +#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S) +#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U +#define PARL_IO_TX_EOF_INT_CLR_S 2 + +/** PARL_IO_RX_ST0_REG register + * Parallel IO RX status register0 + */ +#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38) +/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ +#define PARL_IO_RX_CNT 0x0000001FU +#define PARL_IO_RX_CNT_M (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S) +#define PARL_IO_RX_CNT_V 0x0000001FU +#define PARL_IO_RX_CNT_S 8 +/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ +#define PARL_IO_RX_FIFO_WR_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_M (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S) +#define PARL_IO_RX_FIFO_WR_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_WR_BIT_CNT_S 13 + +/** PARL_IO_RX_ST1_REG register + * Parallel IO RX status register1 + */ +#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c) +/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ +#define PARL_IO_RX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_M (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_RX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_RX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_TX_ST0_REG register + * Parallel IO TX status register0 + */ +#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40) +/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ +#define PARL_IO_TX_CNT 0x0000007FU +#define PARL_IO_TX_CNT_M (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S) +#define PARL_IO_TX_CNT_V 0x0000007FU +#define PARL_IO_TX_CNT_S 6 +/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ +#define PARL_IO_TX_FIFO_RD_BIT_CNT 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_M (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S) +#define PARL_IO_TX_FIFO_RD_BIT_CNT_V 0x0007FFFFU +#define PARL_IO_TX_FIFO_RD_BIT_CNT_S 13 + +/** PARL_IO_RX_CLK_CFG_REG register + * Parallel IO RX clk configuration register + */ +#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44) +/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Rx core clock. + */ +#define PARL_IO_RX_CLK_I_INV (BIT(30)) +#define PARL_IO_RX_CLK_I_INV_M (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S) +#define PARL_IO_RX_CLK_I_INV_V 0x00000001U +#define PARL_IO_RX_CLK_I_INV_S 30 +/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Rx core clock. + */ +#define PARL_IO_RX_CLK_O_INV (BIT(31)) +#define PARL_IO_RX_CLK_O_INV_M (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S) +#define PARL_IO_RX_CLK_O_INV_V 0x00000001U +#define PARL_IO_RX_CLK_O_INV_S 31 + +/** PARL_IO_TX_CLK_CFG_REG register + * Parallel IO TX clk configuration register + */ +#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48) +/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Tx core clock. + */ +#define PARL_IO_TX_CLK_I_INV (BIT(30)) +#define PARL_IO_TX_CLK_I_INV_M (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S) +#define PARL_IO_TX_CLK_I_INV_V 0x00000001U +#define PARL_IO_TX_CLK_I_INV_S 30 +/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Tx core clock. + */ +#define PARL_IO_TX_CLK_O_INV (BIT(31)) +#define PARL_IO_TX_CLK_O_INV_M (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S) +#define PARL_IO_TX_CLK_O_INV_V 0x00000001U +#define PARL_IO_TX_CLK_O_INV_S 31 + +/** PARL_IO_CLK_REG register + * Parallel IO clk configuration register + */ +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) +/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ +#define PARL_IO_CLK_EN (BIT(31)) +#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S) +#define PARL_IO_CLK_EN_V 0x00000001U +#define PARL_IO_CLK_EN_S 31 + +/** PARL_IO_VERSION_REG register + * Version register. + */ +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) +/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920; + * Version of this register file + */ +#define PARL_IO_DATE 0x0FFFFFFFU +#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S) +#define PARL_IO_DATE_V 0x0FFFFFFFU +#define PARL_IO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/include/soc/parl_io_struct.h new file mode 100644 index 0000000000..eb0e1c5a31 --- /dev/null +++ b/components/soc/esp32c5/include/soc/parl_io_struct.h @@ -0,0 +1,509 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PARL_IO RX Mode Configuration */ +/** Type of rx_mode_cfg register + * Parallel RX Sampling mode configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7; + * Configures rx external enable signal selection from IO PAD. + */ + uint32_t rx_ext_en_sel:4; + /** rx_sw_en : R/W; bitpos: [25]; default: 0; + * Set this bit to enable data sampling by software. + */ + uint32_t rx_sw_en:1; + /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0; + * Set this bit to invert the external enable signal. + */ + uint32_t rx_ext_en_inv:1; + /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0; + * Configures the rxd pulse sampling submode. + * 4'd0: positive pulse start(data bit included) && positive pulse end(data bit + * included) + * 4'd1: positive pulse start(data bit included) && positive pulse end (data bit + * excluded) + * 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit + * included) + * 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit + * excluded) + * 4'd4: positive pulse start(data bit included) && length end + * 4'd5: positive pulse start(data bit excluded) && length end + */ + uint32_t rx_pulse_submode_sel:3; + /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0; + * Configures the rxd sampling mode. + * 2'b00: external level enable mode + * 2'b01: external pulse enable mode + * 2'b10: internal software enable mode + */ + uint32_t rx_smp_mode_sel:2; + }; + uint32_t val; +} parl_io_rx_mode_cfg_reg_t; + + +/** Group: PARL_IO RX Data Configuration */ +/** Type of rx_data_cfg register + * Parallel RX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** rx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of received data. + */ + uint32_t rx_bitlen:19; + /** rx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + */ + uint32_t rx_data_order_inv:1; + /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the rxd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ + uint32_t rx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_rx_data_cfg_reg_t; + + +/** Group: PARL_IO RX General Configuration */ +/** Type of rx_genrl_cfg register + * Parallel RX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rx_gating_en : R/W; bitpos: [12]; default: 0; + * Set this bit to enable the clock gating of output rx clock. + */ + uint32_t rx_gating_en:1; + /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095; + * Configures threshold of timeout counter. + */ + uint32_t rx_timeout_thres:16; + /** rx_timeout_en : R/W; bitpos: [29]; default: 1; + * Set this bit to enable timeout function to generate error eof. + */ + uint32_t rx_timeout_en:1; + /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0; + * Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by external enable signal. + */ + uint32_t rx_eof_gen_sel:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} parl_io_rx_genrl_cfg_reg_t; + + +/** Group: PARL_IO RX Start Configuration */ +/** Type of rx_start_cfg register + * Parallel RX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start rx data sampling. + */ + uint32_t rx_start:1; + }; + uint32_t val; +} parl_io_rx_start_cfg_reg_t; + + +/** Group: PARL_IO TX Data Configuration */ +/** Type of tx_data_cfg register + * Parallel TX data configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** tx_bitlen : R/W; bitpos: [27:9]; default: 0; + * Configures expected byte number of sent data. + */ + uint32_t tx_bitlen:19; + /** tx_data_order_inv : R/W; bitpos: [28]; default: 0; + * Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + */ + uint32_t tx_data_order_inv:1; + /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3; + * Configures the txd bus width. + * 3'd0: bus width is 1. + * 3'd1: bus width is 2. + * 3'd2: bus width is 4. + * 3'd3: bus width is 8. + */ + uint32_t tx_bus_wid_sel:3; + }; + uint32_t val; +} parl_io_tx_data_cfg_reg_t; + + +/** Group: PARL_IO TX Start Configuration */ +/** Type of tx_start_cfg register + * Parallel TX Start configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start tx data transmit. + */ + uint32_t tx_start:1; + }; + uint32_t val; +} parl_io_tx_start_cfg_reg_t; + + +/** Group: PARL_IO TX General Configuration */ +/** Type of tx_genrl_cfg register + * Parallel TX general configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0; + * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. + * 1'b1: eof generated by DMA eof. + */ + uint32_t tx_eof_gen_sel:1; + /** tx_idle_value : R/W; bitpos: [29:14]; default: 0; + * Configures bus value of transmitter in IDLE state. + */ + uint32_t tx_idle_value:16; + /** tx_gating_en : R/W; bitpos: [30]; default: 0; + * Set this bit to enable the clock gating of output tx clock. + */ + uint32_t tx_gating_en:1; + /** tx_valid_output_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable the output of tx data valid signal. + */ + uint32_t tx_valid_output_en:1; + }; + uint32_t val; +} parl_io_tx_genrl_cfg_reg_t; + + +/** Group: PARL_IO FIFO Configuration */ +/** Type of fifo_cfg register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_fifo_srst : R/W; bitpos: [30]; default: 0; + * Set this bit to reset async fifo in tx module. + */ + uint32_t tx_fifo_srst:1; + /** rx_fifo_srst : R/W; bitpos: [31]; default: 0; + * Set this bit to reset async fifo in rx module. + */ + uint32_t rx_fifo_srst:1; + }; + uint32_t val; +} parl_io_fifo_cfg_reg_t; + + +/** Group: PARL_IO Register Update Configuration */ +/** Type of reg_update register + * Parallel IO FIFO configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rx_reg_update : WT; bitpos: [31]; default: 0; + * Set this bit to update rx register configuration. + */ + uint32_t rx_reg_update:1; + }; + uint32_t val; +} parl_io_reg_update_reg_t; + + +/** Group: PARL_IO Status */ +/** Type of st register + * Parallel IO module status register0. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_ready : RO; bitpos: [31]; default: 0; + * Represents the status that tx is ready to transmit. + */ + uint32_t tx_ready:1; + }; + uint32_t val; +} parl_io_st_reg_t; + + +/** Group: PARL_IO Interrupt Configuration and Status */ +/** Type of int_ena register + * Parallel IO interrupt enable singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_ena:1; + /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_ena:1; + /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable TX_EOF_INT. + */ + uint32_t tx_eof_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_ena_reg_t; + +/** Type of int_raw register + * Parallel IO interrupt raw singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_raw:1; + /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_raw:1; + /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_raw_reg_t; + +/** Type of int_st register + * Parallel IO interrupt singal status register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_st:1; + /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status of RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_st:1; + /** tx_eof_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status of TX_EOF_INT. + */ + uint32_t tx_eof_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_st_reg_t; + +/** Type of int_clr register + * Parallel IO interrupt clear singal configuration register. + */ +typedef union { + struct { + /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear TX_FIFO_REMPTY_INT. + */ + uint32_t tx_fifo_rempty_int_clr:1; + /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear RX_FIFO_WOVF_INT. + */ + uint32_t rx_fifo_wovf_int_clr:1; + /** tx_eof_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear TX_EOF_INT. + */ + uint32_t tx_eof_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} parl_io_int_clr_reg_t; + + +/** Group: PARL_IO Rx Status0 */ +/** Type of rx_st0 register + * Parallel IO RX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** rx_cnt : RO; bitpos: [12:8]; default: 0; + * Indicates the cycle number of reading Rx FIFO. + */ + uint32_t rx_cnt:5; + /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current written bit number into Rx FIFO. + */ + uint32_t rx_fifo_wr_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st0_reg_t; + + +/** Group: PARL_IO Rx Status1 */ +/** Type of rx_st1 register + * Parallel IO RX status register1 + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Rx FIFO. + */ + uint32_t rx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_rx_st1_reg_t; + + +/** Group: PARL_IO Tx Status0 */ +/** Type of tx_st0 register + * Parallel IO TX status register0 + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** tx_cnt : RO; bitpos: [12:6]; default: 0; + * Indicates the cycle number of reading Tx FIFO. + */ + uint32_t tx_cnt:7; + /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0; + * Indicates the current read bit number from Tx FIFO. + */ + uint32_t tx_fifo_rd_bit_cnt:19; + }; + uint32_t val; +} parl_io_tx_st0_reg_t; + + +/** Group: PARL_IO Rx Clock Configuration */ +/** Type of rx_clk_cfg register + * Parallel IO RX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Rx core clock. + */ + uint32_t rx_clk_i_inv:1; + /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Rx core clock. + */ + uint32_t rx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_rx_clk_cfg_reg_t; + + +/** Group: PARL_IO Tx Clock Configuration */ +/** Type of tx_clk_cfg register + * Parallel IO TX clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0; + * Set this bit to invert the input Tx core clock. + */ + uint32_t tx_clk_i_inv:1; + /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0; + * Set this bit to invert the output Tx core clock. + */ + uint32_t tx_clk_o_inv:1; + }; + uint32_t val; +} parl_io_tx_clk_cfg_reg_t; + + +/** Group: PARL_IO Clock Configuration */ +/** Type of clk register + * Parallel IO clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Force clock on for this register file + */ + uint32_t clk_en:1; + }; + uint32_t val; +} parl_io_clk_reg_t; + + +/** Group: PARL_IO Version Register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725920; + * Version of this register file + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} parl_io_version_reg_t; + + +typedef struct { + volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg; + volatile parl_io_rx_data_cfg_reg_t rx_data_cfg; + volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg; + volatile parl_io_rx_start_cfg_reg_t rx_start_cfg; + volatile parl_io_tx_data_cfg_reg_t tx_data_cfg; + volatile parl_io_tx_start_cfg_reg_t tx_start_cfg; + volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg; + volatile parl_io_fifo_cfg_reg_t fifo_cfg; + volatile parl_io_reg_update_reg_t reg_update; + volatile parl_io_st_reg_t st; + volatile parl_io_int_ena_reg_t int_ena; + volatile parl_io_int_raw_reg_t int_raw; + volatile parl_io_int_st_reg_t int_st; + volatile parl_io_int_clr_reg_t int_clr; + volatile parl_io_rx_st0_reg_t rx_st0; + volatile parl_io_rx_st1_reg_t rx_st1; + volatile parl_io_tx_st0_reg_t tx_st0; + volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg; + volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg; + uint32_t reserved_04c[53]; + volatile parl_io_clk_reg_t clk; + uint32_t reserved_124[182]; + volatile parl_io_version_reg_t version; +} parl_io_dev_t; + +extern parl_io_dev_t PARL_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rsa_reg.h b/components/soc/esp32c5/include/soc/rsa_reg.h new file mode 100644 index 0000000000..542612dbb4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/rsa_reg.h @@ -0,0 +1,233 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RSA_M_MEM register + * Represents M + */ +#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0) +#define RSA_M_MEM_SIZE_BYTES 16 + +/** RSA_Z_MEM register + * Represents Z + */ +#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200) +#define RSA_Z_MEM_SIZE_BYTES 16 + +/** RSA_Y_MEM register + * Represents Y + */ +#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400) +#define RSA_Y_MEM_SIZE_BYTES 16 + +/** RSA_X_MEM register + * Represents X + */ +#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600) +#define RSA_X_MEM_SIZE_BYTES 16 + +/** RSA_M_PRIME_REG register + * Represents M’ + */ +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) +/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Represents M’ + */ +#define RSA_M_PRIME 0xFFFFFFFFU +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFFU +#define RSA_M_PRIME_S 0 + +/** RSA_MODE_REG register + * Configures RSA length + */ +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) +/** RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ +#define RSA_MODE 0x0000007FU +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007FU +#define RSA_MODE_S 0 + +/** RSA_QUERY_CLEAN_REG register + * RSA clean register + */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) +/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ +#define RSA_QUERY_CLEAN (BIT(0)) +#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) +#define RSA_QUERY_CLEAN_V 0x00000001U +#define RSA_QUERY_CLEAN_S 0 + +/** RSA_SET_START_MODEXP_REG register + * Starts modular exponentiation + */ +#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) +/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODEXP (BIT(0)) +#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) +#define RSA_SET_START_MODEXP_V 0x00000001U +#define RSA_SET_START_MODEXP_S 0 + +/** RSA_SET_START_MODMULT_REG register + * Starts modular multiplication + */ +#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) +/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MODMULT (BIT(0)) +#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) +#define RSA_SET_START_MODMULT_V 0x00000001U +#define RSA_SET_START_MODMULT_S 0 + +/** RSA_SET_START_MULT_REG register + * Starts multiplication + */ +#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) +/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ +#define RSA_SET_START_MULT (BIT(0)) +#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) +#define RSA_SET_START_MULT_V 0x00000001U +#define RSA_SET_START_MULT_S 0 + +/** RSA_QUERY_IDLE_REG register + * Represents the RSA status + */ +#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) +/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ +#define RSA_QUERY_IDLE (BIT(0)) +#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) +#define RSA_QUERY_IDLE_V 0x00000001U +#define RSA_QUERY_IDLE_S 0 + +/** RSA_INT_CLR_REG register + * Clears RSA interrupt + */ +#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c) +/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001U +#define RSA_CLEAR_INTERRUPT_S 0 + +/** RSA_CONSTANT_TIME_REG register + * Configures the constant_time option + */ +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001U +#define RSA_CONSTANT_TIME_S 0 + +/** RSA_SEARCH_ENABLE_REG register + * Configures the search option + */ +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) +/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001U +#define RSA_SEARCH_ENABLE_S 0 + +/** RSA_SEARCH_POS_REG register + * Configures the search position + */ +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) +/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ +#define RSA_SEARCH_POS 0x00000FFFU +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFFU +#define RSA_SEARCH_POS_S 0 + +/** RSA_INT_ENA_REG register + * Enables the RSA interrupt + */ +#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c) +/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ +#define RSA_INT_ENA (BIT(0)) +#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S) +#define RSA_INT_ENA_V 0x00000001U +#define RSA_INT_ENA_S 0 + +/** RSA_DATE_REG register + * Version control register + */ +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) +/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ +#define RSA_DATE 0x3FFFFFFFU +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFFU +#define RSA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rsa_struct.h b/components/soc/esp32c5/include/soc/rsa_struct.h new file mode 100644 index 0000000000..34e831bc7f --- /dev/null +++ b/components/soc/esp32c5/include/soc/rsa_struct.h @@ -0,0 +1,273 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory */ + +/** Group: Control / Configuration Registers */ +/** Type of m_prime register + * Represents M’ + */ +typedef union { + struct { + /** m_prime : R/W; bitpos: [31:0]; default: 0; + * Represents M’ + */ + uint32_t m_prime:32; + }; + uint32_t val; +} rsa_m_prime_reg_t; + +/** Type of mode register + * Configures RSA length + */ +typedef union { + struct { + /** mode : R/W; bitpos: [6:0]; default: 0; + * Configures the RSA length. + */ + uint32_t mode:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} rsa_mode_reg_t; + +/** Type of set_start_modexp register + * Starts modular exponentiation + */ +typedef union { + struct { + /** set_start_modexp : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular exponentiation. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modexp:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modexp_reg_t; + +/** Type of set_start_modmult register + * Starts modular multiplication + */ +typedef union { + struct { + /** set_start_modmult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the modular multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_modmult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_modmult_reg_t; + +/** Type of set_start_mult register + * Starts multiplication + */ +typedef union { + struct { + /** set_start_mult : WT; bitpos: [0]; default: 0; + * Configure whether or not to start the multiplication. + * + * 0: No effect + * + * 1: Start + * + */ + uint32_t set_start_mult:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_set_start_mult_reg_t; + +/** Type of query_idle register + * Represents the RSA status + */ +typedef union { + struct { + /** query_idle : RO; bitpos: [0]; default: 0; + * Represents the RSA status. + * + * 0: Busy + * + * 1: Idle + * + */ + uint32_t query_idle:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_idle_reg_t; + +/** Type of constant_time register + * Configures the constant_time option + */ +typedef union { + struct { + /** constant_time : R/W; bitpos: [0]; default: 1; + * Configures the constant_time option. + * + * 0: Acceleration + * + * 1: No acceleration (default) + * + */ + uint32_t constant_time:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_constant_time_reg_t; + +/** Type of search_enable register + * Configures the search option + */ +typedef union { + struct { + /** search_enable : R/W; bitpos: [0]; default: 0; + * Configure the search option. + * + * 0: No acceleration (default) + * + * 1: Acceleration + * + * This option should be used together with RSA_SEARCH_POS. + */ + uint32_t search_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_search_enable_reg_t; + +/** Type of search_pos register + * Configures the search position + */ +typedef union { + struct { + /** search_pos : R/W; bitpos: [11:0]; default: 0; + * Configures the starting address to start search. This field should be used together + * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + */ + uint32_t search_pos:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} rsa_search_pos_reg_t; + + +/** Group: Status Register */ +/** Type of query_clean register + * RSA clean register + */ +typedef union { + struct { + /** query_clean : RO; bitpos: [0]; default: 0; + * Represents whether or not the RSA memory completes initialization. + * + * 0: Not complete + * + * 1: Completed + * + */ + uint32_t query_clean:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_query_clean_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_clr register + * Clears RSA interrupt + */ +typedef union { + struct { + /** clear_interrupt : WT; bitpos: [0]; default: 0; + * Write 1 to clear the RSA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_clr_reg_t; + +/** Type of int_ena register + * Enables the RSA interrupt + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the RSA interrupt. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rsa_int_ena_reg_t; + + +/** Group: Version Control Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} rsa_date_reg_t; + + +typedef struct { + volatile uint32_t m[4]; + uint32_t reserved_010[124]; + volatile uint32_t z[4]; + uint32_t reserved_210[124]; + volatile uint32_t y[4]; + uint32_t reserved_410[124]; + volatile uint32_t x[4]; + uint32_t reserved_610[124]; + volatile rsa_m_prime_reg_t m_prime; + volatile rsa_mode_reg_t mode; + volatile rsa_query_clean_reg_t query_clean; + volatile rsa_set_start_modexp_reg_t set_start_modexp; + volatile rsa_set_start_modmult_reg_t set_start_modmult; + volatile rsa_set_start_mult_reg_t set_start_mult; + volatile rsa_query_idle_reg_t query_idle; + volatile rsa_int_clr_reg_t int_clr; + volatile rsa_constant_time_reg_t constant_time; + volatile rsa_search_enable_reg_t search_enable; + volatile rsa_search_pos_reg_t search_pos; + volatile rsa_int_ena_reg_t int_ena; + volatile rsa_date_reg_t date; +} rsa_dev_t; + +extern rsa_dev_t RSA; + +#ifndef __cplusplus +_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sha_reg.h b/components/soc/esp32c5/include/soc/sha_reg.h new file mode 100644 index 0000000000..11181a16e1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/sha_reg.h @@ -0,0 +1,148 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Initial configuration register. + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * DMA configuration register 0. + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Typical SHA configuration register 0. + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_START 0x7FFFFFFFU +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x7FFFFFFFU +#define SHA_START_S 1 + +/** SHA_CONTINUE_REG register + * Typical SHA configuration register 1. + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ +#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x7FFFFFFFU +#define SHA_CONTINUE_S 1 + +/** SHA_BUSY_REG register + * Busy register. + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * DMA configuration register 1. + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * DMA configuration register 2. + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * Interrupt clear register. + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * Interrupt enable register. + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Date register. + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or finial hash. + */ +#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 64 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/include/soc/sha_struct.h new file mode 100644 index 0000000000..b5e24d24a8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/sha_struct.h @@ -0,0 +1,188 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of mode register + * Initial configuration register. + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Sha mode. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of dma_block_num register + * DMA configuration register 0. + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [5:0]; default: 0; + * Dma-sha block number. + */ + uint32_t dma_block_num:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Typical SHA configuration register 0. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** start : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t start:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Typical SHA configuration register 1. + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** continue : RO; bitpos: [31:1]; default: 0; + * Reserved. + */ + uint32_t continue:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * DMA configuration register 1. + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Start dma-sha. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * DMA configuration register 2. + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Continue dma-sha. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + + +/** Group: Status Register */ +/** Type of busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Sha busy state. 1'b0: idle. 1'b1: busy. + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Register */ +/** Type of clear_irq register + * Interrupt clear register. + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Clear sha interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * Interrupt enable register. + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538972713; + * Sha date information/ sha version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +typedef struct { + volatile sha_mode_reg_t mode; + uint32_t reserved_004[2]; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t continue; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + uint32_t reserved_030[4]; + volatile uint32_t h[16]; + volatile uint32_t m[16]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/soc_etm_reg.h b/components/soc/esp32c5/include/soc/soc_etm_reg.h new file mode 100644 index 0000000000..d5ca5417e7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_etm_reg.h @@ -0,0 +1,6867 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SOC_ETM_CH_ENA_AD0_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) +/** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED0 (BIT(0)) +#define SOC_ETM_CH_ENABLED0_M (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S) +#define SOC_ETM_CH_ENABLED0_V 0x00000001U +#define SOC_ETM_CH_ENABLED0_S 0 +/** SOC_ETM_CH_ENABLED1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED1 (BIT(1)) +#define SOC_ETM_CH_ENABLED1_M (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S) +#define SOC_ETM_CH_ENABLED1_V 0x00000001U +#define SOC_ETM_CH_ENABLED1_S 1 +/** SOC_ETM_CH_ENABLED2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED2 (BIT(2)) +#define SOC_ETM_CH_ENABLED2_M (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S) +#define SOC_ETM_CH_ENABLED2_V 0x00000001U +#define SOC_ETM_CH_ENABLED2_S 2 +/** SOC_ETM_CH_ENABLED3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED3 (BIT(3)) +#define SOC_ETM_CH_ENABLED3_M (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S) +#define SOC_ETM_CH_ENABLED3_V 0x00000001U +#define SOC_ETM_CH_ENABLED3_S 3 +/** SOC_ETM_CH_ENABLED4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED4 (BIT(4)) +#define SOC_ETM_CH_ENABLED4_M (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S) +#define SOC_ETM_CH_ENABLED4_V 0x00000001U +#define SOC_ETM_CH_ENABLED4_S 4 +/** SOC_ETM_CH_ENABLED5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED5 (BIT(5)) +#define SOC_ETM_CH_ENABLED5_M (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S) +#define SOC_ETM_CH_ENABLED5_V 0x00000001U +#define SOC_ETM_CH_ENABLED5_S 5 +/** SOC_ETM_CH_ENABLED6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED6 (BIT(6)) +#define SOC_ETM_CH_ENABLED6_M (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S) +#define SOC_ETM_CH_ENABLED6_V 0x00000001U +#define SOC_ETM_CH_ENABLED6_S 6 +/** SOC_ETM_CH_ENABLED7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED7 (BIT(7)) +#define SOC_ETM_CH_ENABLED7_M (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S) +#define SOC_ETM_CH_ENABLED7_V 0x00000001U +#define SOC_ETM_CH_ENABLED7_S 7 +/** SOC_ETM_CH_ENABLED8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED8 (BIT(8)) +#define SOC_ETM_CH_ENABLED8_M (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S) +#define SOC_ETM_CH_ENABLED8_V 0x00000001U +#define SOC_ETM_CH_ENABLED8_S 8 +/** SOC_ETM_CH_ENABLED9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED9 (BIT(9)) +#define SOC_ETM_CH_ENABLED9_M (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S) +#define SOC_ETM_CH_ENABLED9_V 0x00000001U +#define SOC_ETM_CH_ENABLED9_S 9 +/** SOC_ETM_CH_ENABLED10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED10 (BIT(10)) +#define SOC_ETM_CH_ENABLED10_M (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S) +#define SOC_ETM_CH_ENABLED10_V 0x00000001U +#define SOC_ETM_CH_ENABLED10_S 10 +/** SOC_ETM_CH_ENABLED11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED11 (BIT(11)) +#define SOC_ETM_CH_ENABLED11_M (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S) +#define SOC_ETM_CH_ENABLED11_V 0x00000001U +#define SOC_ETM_CH_ENABLED11_S 11 +/** SOC_ETM_CH_ENABLED12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED12 (BIT(12)) +#define SOC_ETM_CH_ENABLED12_M (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S) +#define SOC_ETM_CH_ENABLED12_V 0x00000001U +#define SOC_ETM_CH_ENABLED12_S 12 +/** SOC_ETM_CH_ENABLED13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED13 (BIT(13)) +#define SOC_ETM_CH_ENABLED13_M (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S) +#define SOC_ETM_CH_ENABLED13_V 0x00000001U +#define SOC_ETM_CH_ENABLED13_S 13 +/** SOC_ETM_CH_ENABLED14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED14 (BIT(14)) +#define SOC_ETM_CH_ENABLED14_M (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S) +#define SOC_ETM_CH_ENABLED14_V 0x00000001U +#define SOC_ETM_CH_ENABLED14_S 14 +/** SOC_ETM_CH_ENABLED15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED15 (BIT(15)) +#define SOC_ETM_CH_ENABLED15_M (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S) +#define SOC_ETM_CH_ENABLED15_V 0x00000001U +#define SOC_ETM_CH_ENABLED15_S 15 +/** SOC_ETM_CH_ENABLED16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED16 (BIT(16)) +#define SOC_ETM_CH_ENABLED16_M (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S) +#define SOC_ETM_CH_ENABLED16_V 0x00000001U +#define SOC_ETM_CH_ENABLED16_S 16 +/** SOC_ETM_CH_ENABLED17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED17 (BIT(17)) +#define SOC_ETM_CH_ENABLED17_M (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S) +#define SOC_ETM_CH_ENABLED17_V 0x00000001U +#define SOC_ETM_CH_ENABLED17_S 17 +/** SOC_ETM_CH_ENABLED18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED18 (BIT(18)) +#define SOC_ETM_CH_ENABLED18_M (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S) +#define SOC_ETM_CH_ENABLED18_V 0x00000001U +#define SOC_ETM_CH_ENABLED18_S 18 +/** SOC_ETM_CH_ENABLED19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED19 (BIT(19)) +#define SOC_ETM_CH_ENABLED19_M (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S) +#define SOC_ETM_CH_ENABLED19_V 0x00000001U +#define SOC_ETM_CH_ENABLED19_S 19 +/** SOC_ETM_CH_ENABLED20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED20 (BIT(20)) +#define SOC_ETM_CH_ENABLED20_M (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S) +#define SOC_ETM_CH_ENABLED20_V 0x00000001U +#define SOC_ETM_CH_ENABLED20_S 20 +/** SOC_ETM_CH_ENABLED21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED21 (BIT(21)) +#define SOC_ETM_CH_ENABLED21_M (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S) +#define SOC_ETM_CH_ENABLED21_V 0x00000001U +#define SOC_ETM_CH_ENABLED21_S 21 +/** SOC_ETM_CH_ENABLED22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED22 (BIT(22)) +#define SOC_ETM_CH_ENABLED22_M (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S) +#define SOC_ETM_CH_ENABLED22_V 0x00000001U +#define SOC_ETM_CH_ENABLED22_S 22 +/** SOC_ETM_CH_ENABLED23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED23 (BIT(23)) +#define SOC_ETM_CH_ENABLED23_M (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S) +#define SOC_ETM_CH_ENABLED23_V 0x00000001U +#define SOC_ETM_CH_ENABLED23_S 23 +/** SOC_ETM_CH_ENABLED24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED24 (BIT(24)) +#define SOC_ETM_CH_ENABLED24_M (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S) +#define SOC_ETM_CH_ENABLED24_V 0x00000001U +#define SOC_ETM_CH_ENABLED24_S 24 +/** SOC_ETM_CH_ENABLED25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED25 (BIT(25)) +#define SOC_ETM_CH_ENABLED25_M (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S) +#define SOC_ETM_CH_ENABLED25_V 0x00000001U +#define SOC_ETM_CH_ENABLED25_S 25 +/** SOC_ETM_CH_ENABLED26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED26 (BIT(26)) +#define SOC_ETM_CH_ENABLED26_M (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S) +#define SOC_ETM_CH_ENABLED26_V 0x00000001U +#define SOC_ETM_CH_ENABLED26_S 26 +/** SOC_ETM_CH_ENABLED27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED27 (BIT(27)) +#define SOC_ETM_CH_ENABLED27_M (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S) +#define SOC_ETM_CH_ENABLED27_V 0x00000001U +#define SOC_ETM_CH_ENABLED27_S 27 +/** SOC_ETM_CH_ENABLED28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED28 (BIT(28)) +#define SOC_ETM_CH_ENABLED28_M (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S) +#define SOC_ETM_CH_ENABLED28_V 0x00000001U +#define SOC_ETM_CH_ENABLED28_S 28 +/** SOC_ETM_CH_ENABLED29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED29 (BIT(29)) +#define SOC_ETM_CH_ENABLED29_M (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S) +#define SOC_ETM_CH_ENABLED29_V 0x00000001U +#define SOC_ETM_CH_ENABLED29_S 29 +/** SOC_ETM_CH_ENABLED30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED30 (BIT(30)) +#define SOC_ETM_CH_ENABLED30_M (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S) +#define SOC_ETM_CH_ENABLED30_V 0x00000001U +#define SOC_ETM_CH_ENABLED30_S 30 +/** SOC_ETM_CH_ENABLED31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED31 (BIT(31)) +#define SOC_ETM_CH_ENABLED31_M (SOC_ETM_CH_ENABLED31_V << SOC_ETM_CH_ENABLED31_S) +#define SOC_ETM_CH_ENABLED31_V 0x00000001U +#define SOC_ETM_CH_ENABLED31_S 31 + +/** SOC_ETM_CH_ENA_AD0_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) +/** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE0 (BIT(0)) +#define SOC_ETM_CH_ENABLE0_M (SOC_ETM_CH_ENABLE0_V << SOC_ETM_CH_ENABLE0_S) +#define SOC_ETM_CH_ENABLE0_V 0x00000001U +#define SOC_ETM_CH_ENABLE0_S 0 +/** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE1 (BIT(1)) +#define SOC_ETM_CH_ENABLE1_M (SOC_ETM_CH_ENABLE1_V << SOC_ETM_CH_ENABLE1_S) +#define SOC_ETM_CH_ENABLE1_V 0x00000001U +#define SOC_ETM_CH_ENABLE1_S 1 +/** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE2 (BIT(2)) +#define SOC_ETM_CH_ENABLE2_M (SOC_ETM_CH_ENABLE2_V << SOC_ETM_CH_ENABLE2_S) +#define SOC_ETM_CH_ENABLE2_V 0x00000001U +#define SOC_ETM_CH_ENABLE2_S 2 +/** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE3 (BIT(3)) +#define SOC_ETM_CH_ENABLE3_M (SOC_ETM_CH_ENABLE3_V << SOC_ETM_CH_ENABLE3_S) +#define SOC_ETM_CH_ENABLE3_V 0x00000001U +#define SOC_ETM_CH_ENABLE3_S 3 +/** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE4 (BIT(4)) +#define SOC_ETM_CH_ENABLE4_M (SOC_ETM_CH_ENABLE4_V << SOC_ETM_CH_ENABLE4_S) +#define SOC_ETM_CH_ENABLE4_V 0x00000001U +#define SOC_ETM_CH_ENABLE4_S 4 +/** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE5 (BIT(5)) +#define SOC_ETM_CH_ENABLE5_M (SOC_ETM_CH_ENABLE5_V << SOC_ETM_CH_ENABLE5_S) +#define SOC_ETM_CH_ENABLE5_V 0x00000001U +#define SOC_ETM_CH_ENABLE5_S 5 +/** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE6 (BIT(6)) +#define SOC_ETM_CH_ENABLE6_M (SOC_ETM_CH_ENABLE6_V << SOC_ETM_CH_ENABLE6_S) +#define SOC_ETM_CH_ENABLE6_V 0x00000001U +#define SOC_ETM_CH_ENABLE6_S 6 +/** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE7 (BIT(7)) +#define SOC_ETM_CH_ENABLE7_M (SOC_ETM_CH_ENABLE7_V << SOC_ETM_CH_ENABLE7_S) +#define SOC_ETM_CH_ENABLE7_V 0x00000001U +#define SOC_ETM_CH_ENABLE7_S 7 +/** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE8 (BIT(8)) +#define SOC_ETM_CH_ENABLE8_M (SOC_ETM_CH_ENABLE8_V << SOC_ETM_CH_ENABLE8_S) +#define SOC_ETM_CH_ENABLE8_V 0x00000001U +#define SOC_ETM_CH_ENABLE8_S 8 +/** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE9 (BIT(9)) +#define SOC_ETM_CH_ENABLE9_M (SOC_ETM_CH_ENABLE9_V << SOC_ETM_CH_ENABLE9_S) +#define SOC_ETM_CH_ENABLE9_V 0x00000001U +#define SOC_ETM_CH_ENABLE9_S 9 +/** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE10 (BIT(10)) +#define SOC_ETM_CH_ENABLE10_M (SOC_ETM_CH_ENABLE10_V << SOC_ETM_CH_ENABLE10_S) +#define SOC_ETM_CH_ENABLE10_V 0x00000001U +#define SOC_ETM_CH_ENABLE10_S 10 +/** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE11 (BIT(11)) +#define SOC_ETM_CH_ENABLE11_M (SOC_ETM_CH_ENABLE11_V << SOC_ETM_CH_ENABLE11_S) +#define SOC_ETM_CH_ENABLE11_V 0x00000001U +#define SOC_ETM_CH_ENABLE11_S 11 +/** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE12 (BIT(12)) +#define SOC_ETM_CH_ENABLE12_M (SOC_ETM_CH_ENABLE12_V << SOC_ETM_CH_ENABLE12_S) +#define SOC_ETM_CH_ENABLE12_V 0x00000001U +#define SOC_ETM_CH_ENABLE12_S 12 +/** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE13 (BIT(13)) +#define SOC_ETM_CH_ENABLE13_M (SOC_ETM_CH_ENABLE13_V << SOC_ETM_CH_ENABLE13_S) +#define SOC_ETM_CH_ENABLE13_V 0x00000001U +#define SOC_ETM_CH_ENABLE13_S 13 +/** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE14 (BIT(14)) +#define SOC_ETM_CH_ENABLE14_M (SOC_ETM_CH_ENABLE14_V << SOC_ETM_CH_ENABLE14_S) +#define SOC_ETM_CH_ENABLE14_V 0x00000001U +#define SOC_ETM_CH_ENABLE14_S 14 +/** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE15 (BIT(15)) +#define SOC_ETM_CH_ENABLE15_M (SOC_ETM_CH_ENABLE15_V << SOC_ETM_CH_ENABLE15_S) +#define SOC_ETM_CH_ENABLE15_V 0x00000001U +#define SOC_ETM_CH_ENABLE15_S 15 +/** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE16 (BIT(16)) +#define SOC_ETM_CH_ENABLE16_M (SOC_ETM_CH_ENABLE16_V << SOC_ETM_CH_ENABLE16_S) +#define SOC_ETM_CH_ENABLE16_V 0x00000001U +#define SOC_ETM_CH_ENABLE16_S 16 +/** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE17 (BIT(17)) +#define SOC_ETM_CH_ENABLE17_M (SOC_ETM_CH_ENABLE17_V << SOC_ETM_CH_ENABLE17_S) +#define SOC_ETM_CH_ENABLE17_V 0x00000001U +#define SOC_ETM_CH_ENABLE17_S 17 +/** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE18 (BIT(18)) +#define SOC_ETM_CH_ENABLE18_M (SOC_ETM_CH_ENABLE18_V << SOC_ETM_CH_ENABLE18_S) +#define SOC_ETM_CH_ENABLE18_V 0x00000001U +#define SOC_ETM_CH_ENABLE18_S 18 +/** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE19 (BIT(19)) +#define SOC_ETM_CH_ENABLE19_M (SOC_ETM_CH_ENABLE19_V << SOC_ETM_CH_ENABLE19_S) +#define SOC_ETM_CH_ENABLE19_V 0x00000001U +#define SOC_ETM_CH_ENABLE19_S 19 +/** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE20 (BIT(20)) +#define SOC_ETM_CH_ENABLE20_M (SOC_ETM_CH_ENABLE20_V << SOC_ETM_CH_ENABLE20_S) +#define SOC_ETM_CH_ENABLE20_V 0x00000001U +#define SOC_ETM_CH_ENABLE20_S 20 +/** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE21 (BIT(21)) +#define SOC_ETM_CH_ENABLE21_M (SOC_ETM_CH_ENABLE21_V << SOC_ETM_CH_ENABLE21_S) +#define SOC_ETM_CH_ENABLE21_V 0x00000001U +#define SOC_ETM_CH_ENABLE21_S 21 +/** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE22 (BIT(22)) +#define SOC_ETM_CH_ENABLE22_M (SOC_ETM_CH_ENABLE22_V << SOC_ETM_CH_ENABLE22_S) +#define SOC_ETM_CH_ENABLE22_V 0x00000001U +#define SOC_ETM_CH_ENABLE22_S 22 +/** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE23 (BIT(23)) +#define SOC_ETM_CH_ENABLE23_M (SOC_ETM_CH_ENABLE23_V << SOC_ETM_CH_ENABLE23_S) +#define SOC_ETM_CH_ENABLE23_V 0x00000001U +#define SOC_ETM_CH_ENABLE23_S 23 +/** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE24 (BIT(24)) +#define SOC_ETM_CH_ENABLE24_M (SOC_ETM_CH_ENABLE24_V << SOC_ETM_CH_ENABLE24_S) +#define SOC_ETM_CH_ENABLE24_V 0x00000001U +#define SOC_ETM_CH_ENABLE24_S 24 +/** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE25 (BIT(25)) +#define SOC_ETM_CH_ENABLE25_M (SOC_ETM_CH_ENABLE25_V << SOC_ETM_CH_ENABLE25_S) +#define SOC_ETM_CH_ENABLE25_V 0x00000001U +#define SOC_ETM_CH_ENABLE25_S 25 +/** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE26 (BIT(26)) +#define SOC_ETM_CH_ENABLE26_M (SOC_ETM_CH_ENABLE26_V << SOC_ETM_CH_ENABLE26_S) +#define SOC_ETM_CH_ENABLE26_V 0x00000001U +#define SOC_ETM_CH_ENABLE26_S 26 +/** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE27 (BIT(27)) +#define SOC_ETM_CH_ENABLE27_M (SOC_ETM_CH_ENABLE27_V << SOC_ETM_CH_ENABLE27_S) +#define SOC_ETM_CH_ENABLE27_V 0x00000001U +#define SOC_ETM_CH_ENABLE27_S 27 +/** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE28 (BIT(28)) +#define SOC_ETM_CH_ENABLE28_M (SOC_ETM_CH_ENABLE28_V << SOC_ETM_CH_ENABLE28_S) +#define SOC_ETM_CH_ENABLE28_V 0x00000001U +#define SOC_ETM_CH_ENABLE28_S 28 +/** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE29 (BIT(29)) +#define SOC_ETM_CH_ENABLE29_M (SOC_ETM_CH_ENABLE29_V << SOC_ETM_CH_ENABLE29_S) +#define SOC_ETM_CH_ENABLE29_V 0x00000001U +#define SOC_ETM_CH_ENABLE29_S 29 +/** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE30 (BIT(30)) +#define SOC_ETM_CH_ENABLE30_M (SOC_ETM_CH_ENABLE30_V << SOC_ETM_CH_ENABLE30_S) +#define SOC_ETM_CH_ENABLE30_V 0x00000001U +#define SOC_ETM_CH_ENABLE30_S 30 +/** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE31 (BIT(31)) +#define SOC_ETM_CH_ENABLE31_M (SOC_ETM_CH_ENABLE31_V << SOC_ETM_CH_ENABLE31_S) +#define SOC_ETM_CH_ENABLE31_V 0x00000001U +#define SOC_ETM_CH_ENABLE31_S 31 + +/** SOC_ETM_CH_ENA_AD0_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) +/** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE0 (BIT(0)) +#define SOC_ETM_CH_DISABLE0_M (SOC_ETM_CH_DISABLE0_V << SOC_ETM_CH_DISABLE0_S) +#define SOC_ETM_CH_DISABLE0_V 0x00000001U +#define SOC_ETM_CH_DISABLE0_S 0 +/** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE1 (BIT(1)) +#define SOC_ETM_CH_DISABLE1_M (SOC_ETM_CH_DISABLE1_V << SOC_ETM_CH_DISABLE1_S) +#define SOC_ETM_CH_DISABLE1_V 0x00000001U +#define SOC_ETM_CH_DISABLE1_S 1 +/** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE2 (BIT(2)) +#define SOC_ETM_CH_DISABLE2_M (SOC_ETM_CH_DISABLE2_V << SOC_ETM_CH_DISABLE2_S) +#define SOC_ETM_CH_DISABLE2_V 0x00000001U +#define SOC_ETM_CH_DISABLE2_S 2 +/** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE3 (BIT(3)) +#define SOC_ETM_CH_DISABLE3_M (SOC_ETM_CH_DISABLE3_V << SOC_ETM_CH_DISABLE3_S) +#define SOC_ETM_CH_DISABLE3_V 0x00000001U +#define SOC_ETM_CH_DISABLE3_S 3 +/** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE4 (BIT(4)) +#define SOC_ETM_CH_DISABLE4_M (SOC_ETM_CH_DISABLE4_V << SOC_ETM_CH_DISABLE4_S) +#define SOC_ETM_CH_DISABLE4_V 0x00000001U +#define SOC_ETM_CH_DISABLE4_S 4 +/** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE5 (BIT(5)) +#define SOC_ETM_CH_DISABLE5_M (SOC_ETM_CH_DISABLE5_V << SOC_ETM_CH_DISABLE5_S) +#define SOC_ETM_CH_DISABLE5_V 0x00000001U +#define SOC_ETM_CH_DISABLE5_S 5 +/** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE6 (BIT(6)) +#define SOC_ETM_CH_DISABLE6_M (SOC_ETM_CH_DISABLE6_V << SOC_ETM_CH_DISABLE6_S) +#define SOC_ETM_CH_DISABLE6_V 0x00000001U +#define SOC_ETM_CH_DISABLE6_S 6 +/** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE7 (BIT(7)) +#define SOC_ETM_CH_DISABLE7_M (SOC_ETM_CH_DISABLE7_V << SOC_ETM_CH_DISABLE7_S) +#define SOC_ETM_CH_DISABLE7_V 0x00000001U +#define SOC_ETM_CH_DISABLE7_S 7 +/** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE8 (BIT(8)) +#define SOC_ETM_CH_DISABLE8_M (SOC_ETM_CH_DISABLE8_V << SOC_ETM_CH_DISABLE8_S) +#define SOC_ETM_CH_DISABLE8_V 0x00000001U +#define SOC_ETM_CH_DISABLE8_S 8 +/** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE9 (BIT(9)) +#define SOC_ETM_CH_DISABLE9_M (SOC_ETM_CH_DISABLE9_V << SOC_ETM_CH_DISABLE9_S) +#define SOC_ETM_CH_DISABLE9_V 0x00000001U +#define SOC_ETM_CH_DISABLE9_S 9 +/** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE10 (BIT(10)) +#define SOC_ETM_CH_DISABLE10_M (SOC_ETM_CH_DISABLE10_V << SOC_ETM_CH_DISABLE10_S) +#define SOC_ETM_CH_DISABLE10_V 0x00000001U +#define SOC_ETM_CH_DISABLE10_S 10 +/** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE11 (BIT(11)) +#define SOC_ETM_CH_DISABLE11_M (SOC_ETM_CH_DISABLE11_V << SOC_ETM_CH_DISABLE11_S) +#define SOC_ETM_CH_DISABLE11_V 0x00000001U +#define SOC_ETM_CH_DISABLE11_S 11 +/** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE12 (BIT(12)) +#define SOC_ETM_CH_DISABLE12_M (SOC_ETM_CH_DISABLE12_V << SOC_ETM_CH_DISABLE12_S) +#define SOC_ETM_CH_DISABLE12_V 0x00000001U +#define SOC_ETM_CH_DISABLE12_S 12 +/** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE13 (BIT(13)) +#define SOC_ETM_CH_DISABLE13_M (SOC_ETM_CH_DISABLE13_V << SOC_ETM_CH_DISABLE13_S) +#define SOC_ETM_CH_DISABLE13_V 0x00000001U +#define SOC_ETM_CH_DISABLE13_S 13 +/** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE14 (BIT(14)) +#define SOC_ETM_CH_DISABLE14_M (SOC_ETM_CH_DISABLE14_V << SOC_ETM_CH_DISABLE14_S) +#define SOC_ETM_CH_DISABLE14_V 0x00000001U +#define SOC_ETM_CH_DISABLE14_S 14 +/** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE15 (BIT(15)) +#define SOC_ETM_CH_DISABLE15_M (SOC_ETM_CH_DISABLE15_V << SOC_ETM_CH_DISABLE15_S) +#define SOC_ETM_CH_DISABLE15_V 0x00000001U +#define SOC_ETM_CH_DISABLE15_S 15 +/** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE16 (BIT(16)) +#define SOC_ETM_CH_DISABLE16_M (SOC_ETM_CH_DISABLE16_V << SOC_ETM_CH_DISABLE16_S) +#define SOC_ETM_CH_DISABLE16_V 0x00000001U +#define SOC_ETM_CH_DISABLE16_S 16 +/** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE17 (BIT(17)) +#define SOC_ETM_CH_DISABLE17_M (SOC_ETM_CH_DISABLE17_V << SOC_ETM_CH_DISABLE17_S) +#define SOC_ETM_CH_DISABLE17_V 0x00000001U +#define SOC_ETM_CH_DISABLE17_S 17 +/** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE18 (BIT(18)) +#define SOC_ETM_CH_DISABLE18_M (SOC_ETM_CH_DISABLE18_V << SOC_ETM_CH_DISABLE18_S) +#define SOC_ETM_CH_DISABLE18_V 0x00000001U +#define SOC_ETM_CH_DISABLE18_S 18 +/** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE19 (BIT(19)) +#define SOC_ETM_CH_DISABLE19_M (SOC_ETM_CH_DISABLE19_V << SOC_ETM_CH_DISABLE19_S) +#define SOC_ETM_CH_DISABLE19_V 0x00000001U +#define SOC_ETM_CH_DISABLE19_S 19 +/** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE20 (BIT(20)) +#define SOC_ETM_CH_DISABLE20_M (SOC_ETM_CH_DISABLE20_V << SOC_ETM_CH_DISABLE20_S) +#define SOC_ETM_CH_DISABLE20_V 0x00000001U +#define SOC_ETM_CH_DISABLE20_S 20 +/** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE21 (BIT(21)) +#define SOC_ETM_CH_DISABLE21_M (SOC_ETM_CH_DISABLE21_V << SOC_ETM_CH_DISABLE21_S) +#define SOC_ETM_CH_DISABLE21_V 0x00000001U +#define SOC_ETM_CH_DISABLE21_S 21 +/** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE22 (BIT(22)) +#define SOC_ETM_CH_DISABLE22_M (SOC_ETM_CH_DISABLE22_V << SOC_ETM_CH_DISABLE22_S) +#define SOC_ETM_CH_DISABLE22_V 0x00000001U +#define SOC_ETM_CH_DISABLE22_S 22 +/** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE23 (BIT(23)) +#define SOC_ETM_CH_DISABLE23_M (SOC_ETM_CH_DISABLE23_V << SOC_ETM_CH_DISABLE23_S) +#define SOC_ETM_CH_DISABLE23_V 0x00000001U +#define SOC_ETM_CH_DISABLE23_S 23 +/** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE24 (BIT(24)) +#define SOC_ETM_CH_DISABLE24_M (SOC_ETM_CH_DISABLE24_V << SOC_ETM_CH_DISABLE24_S) +#define SOC_ETM_CH_DISABLE24_V 0x00000001U +#define SOC_ETM_CH_DISABLE24_S 24 +/** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE25 (BIT(25)) +#define SOC_ETM_CH_DISABLE25_M (SOC_ETM_CH_DISABLE25_V << SOC_ETM_CH_DISABLE25_S) +#define SOC_ETM_CH_DISABLE25_V 0x00000001U +#define SOC_ETM_CH_DISABLE25_S 25 +/** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE26 (BIT(26)) +#define SOC_ETM_CH_DISABLE26_M (SOC_ETM_CH_DISABLE26_V << SOC_ETM_CH_DISABLE26_S) +#define SOC_ETM_CH_DISABLE26_V 0x00000001U +#define SOC_ETM_CH_DISABLE26_S 26 +/** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE27 (BIT(27)) +#define SOC_ETM_CH_DISABLE27_M (SOC_ETM_CH_DISABLE27_V << SOC_ETM_CH_DISABLE27_S) +#define SOC_ETM_CH_DISABLE27_V 0x00000001U +#define SOC_ETM_CH_DISABLE27_S 27 +/** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE28 (BIT(28)) +#define SOC_ETM_CH_DISABLE28_M (SOC_ETM_CH_DISABLE28_V << SOC_ETM_CH_DISABLE28_S) +#define SOC_ETM_CH_DISABLE28_V 0x00000001U +#define SOC_ETM_CH_DISABLE28_S 28 +/** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE29 (BIT(29)) +#define SOC_ETM_CH_DISABLE29_M (SOC_ETM_CH_DISABLE29_V << SOC_ETM_CH_DISABLE29_S) +#define SOC_ETM_CH_DISABLE29_V 0x00000001U +#define SOC_ETM_CH_DISABLE29_S 29 +/** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE30 (BIT(30)) +#define SOC_ETM_CH_DISABLE30_M (SOC_ETM_CH_DISABLE30_V << SOC_ETM_CH_DISABLE30_S) +#define SOC_ETM_CH_DISABLE30_V 0x00000001U +#define SOC_ETM_CH_DISABLE30_S 30 +/** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE31 (BIT(31)) +#define SOC_ETM_CH_DISABLE31_M (SOC_ETM_CH_DISABLE31_V << SOC_ETM_CH_DISABLE31_S) +#define SOC_ETM_CH_DISABLE31_V 0x00000001U +#define SOC_ETM_CH_DISABLE31_S 31 + +/** SOC_ETM_CH_ENA_AD1_REG register + * Channel enable status register + */ +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) +/** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED32 (BIT(0)) +#define SOC_ETM_CH_ENABLED32_M (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S) +#define SOC_ETM_CH_ENABLED32_V 0x00000001U +#define SOC_ETM_CH_ENABLED32_S 0 +/** SOC_ETM_CH_ENABLED33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED33 (BIT(1)) +#define SOC_ETM_CH_ENABLED33_M (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S) +#define SOC_ETM_CH_ENABLED33_V 0x00000001U +#define SOC_ETM_CH_ENABLED33_S 1 +/** SOC_ETM_CH_ENABLED34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED34 (BIT(2)) +#define SOC_ETM_CH_ENABLED34_M (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S) +#define SOC_ETM_CH_ENABLED34_V 0x00000001U +#define SOC_ETM_CH_ENABLED34_S 2 +/** SOC_ETM_CH_ENABLED35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED35 (BIT(3)) +#define SOC_ETM_CH_ENABLED35_M (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S) +#define SOC_ETM_CH_ENABLED35_V 0x00000001U +#define SOC_ETM_CH_ENABLED35_S 3 +/** SOC_ETM_CH_ENABLED36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED36 (BIT(4)) +#define SOC_ETM_CH_ENABLED36_M (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S) +#define SOC_ETM_CH_ENABLED36_V 0x00000001U +#define SOC_ETM_CH_ENABLED36_S 4 +/** SOC_ETM_CH_ENABLED37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED37 (BIT(5)) +#define SOC_ETM_CH_ENABLED37_M (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S) +#define SOC_ETM_CH_ENABLED37_V 0x00000001U +#define SOC_ETM_CH_ENABLED37_S 5 +/** SOC_ETM_CH_ENABLED38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED38 (BIT(6)) +#define SOC_ETM_CH_ENABLED38_M (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S) +#define SOC_ETM_CH_ENABLED38_V 0x00000001U +#define SOC_ETM_CH_ENABLED38_S 6 +/** SOC_ETM_CH_ENABLED39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED39 (BIT(7)) +#define SOC_ETM_CH_ENABLED39_M (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S) +#define SOC_ETM_CH_ENABLED39_V 0x00000001U +#define SOC_ETM_CH_ENABLED39_S 7 +/** SOC_ETM_CH_ENABLED40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED40 (BIT(8)) +#define SOC_ETM_CH_ENABLED40_M (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S) +#define SOC_ETM_CH_ENABLED40_V 0x00000001U +#define SOC_ETM_CH_ENABLED40_S 8 +/** SOC_ETM_CH_ENABLED41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED41 (BIT(9)) +#define SOC_ETM_CH_ENABLED41_M (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S) +#define SOC_ETM_CH_ENABLED41_V 0x00000001U +#define SOC_ETM_CH_ENABLED41_S 9 +/** SOC_ETM_CH_ENABLED42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED42 (BIT(10)) +#define SOC_ETM_CH_ENABLED42_M (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S) +#define SOC_ETM_CH_ENABLED42_V 0x00000001U +#define SOC_ETM_CH_ENABLED42_S 10 +/** SOC_ETM_CH_ENABLED43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED43 (BIT(11)) +#define SOC_ETM_CH_ENABLED43_M (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S) +#define SOC_ETM_CH_ENABLED43_V 0x00000001U +#define SOC_ETM_CH_ENABLED43_S 11 +/** SOC_ETM_CH_ENABLED44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED44 (BIT(12)) +#define SOC_ETM_CH_ENABLED44_M (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S) +#define SOC_ETM_CH_ENABLED44_V 0x00000001U +#define SOC_ETM_CH_ENABLED44_S 12 +/** SOC_ETM_CH_ENABLED45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED45 (BIT(13)) +#define SOC_ETM_CH_ENABLED45_M (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S) +#define SOC_ETM_CH_ENABLED45_V 0x00000001U +#define SOC_ETM_CH_ENABLED45_S 13 +/** SOC_ETM_CH_ENABLED46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED46 (BIT(14)) +#define SOC_ETM_CH_ENABLED46_M (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S) +#define SOC_ETM_CH_ENABLED46_V 0x00000001U +#define SOC_ETM_CH_ENABLED46_S 14 +/** SOC_ETM_CH_ENABLED47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED47 (BIT(15)) +#define SOC_ETM_CH_ENABLED47_M (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S) +#define SOC_ETM_CH_ENABLED47_V 0x00000001U +#define SOC_ETM_CH_ENABLED47_S 15 +/** SOC_ETM_CH_ENABLED48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED48 (BIT(16)) +#define SOC_ETM_CH_ENABLED48_M (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S) +#define SOC_ETM_CH_ENABLED48_V 0x00000001U +#define SOC_ETM_CH_ENABLED48_S 16 +/** SOC_ETM_CH_ENABLED49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ +#define SOC_ETM_CH_ENABLED49 (BIT(17)) +#define SOC_ETM_CH_ENABLED49_M (SOC_ETM_CH_ENABLED49_V << SOC_ETM_CH_ENABLED49_S) +#define SOC_ETM_CH_ENABLED49_V 0x00000001U +#define SOC_ETM_CH_ENABLED49_S 17 + +/** SOC_ETM_CH_ENA_AD1_SET_REG register + * Channel enable set register + */ +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) +/** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE32 (BIT(0)) +#define SOC_ETM_CH_ENABLE32_M (SOC_ETM_CH_ENABLE32_V << SOC_ETM_CH_ENABLE32_S) +#define SOC_ETM_CH_ENABLE32_V 0x00000001U +#define SOC_ETM_CH_ENABLE32_S 0 +/** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE33 (BIT(1)) +#define SOC_ETM_CH_ENABLE33_M (SOC_ETM_CH_ENABLE33_V << SOC_ETM_CH_ENABLE33_S) +#define SOC_ETM_CH_ENABLE33_V 0x00000001U +#define SOC_ETM_CH_ENABLE33_S 1 +/** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE34 (BIT(2)) +#define SOC_ETM_CH_ENABLE34_M (SOC_ETM_CH_ENABLE34_V << SOC_ETM_CH_ENABLE34_S) +#define SOC_ETM_CH_ENABLE34_V 0x00000001U +#define SOC_ETM_CH_ENABLE34_S 2 +/** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE35 (BIT(3)) +#define SOC_ETM_CH_ENABLE35_M (SOC_ETM_CH_ENABLE35_V << SOC_ETM_CH_ENABLE35_S) +#define SOC_ETM_CH_ENABLE35_V 0x00000001U +#define SOC_ETM_CH_ENABLE35_S 3 +/** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE36 (BIT(4)) +#define SOC_ETM_CH_ENABLE36_M (SOC_ETM_CH_ENABLE36_V << SOC_ETM_CH_ENABLE36_S) +#define SOC_ETM_CH_ENABLE36_V 0x00000001U +#define SOC_ETM_CH_ENABLE36_S 4 +/** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE37 (BIT(5)) +#define SOC_ETM_CH_ENABLE37_M (SOC_ETM_CH_ENABLE37_V << SOC_ETM_CH_ENABLE37_S) +#define SOC_ETM_CH_ENABLE37_V 0x00000001U +#define SOC_ETM_CH_ENABLE37_S 5 +/** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE38 (BIT(6)) +#define SOC_ETM_CH_ENABLE38_M (SOC_ETM_CH_ENABLE38_V << SOC_ETM_CH_ENABLE38_S) +#define SOC_ETM_CH_ENABLE38_V 0x00000001U +#define SOC_ETM_CH_ENABLE38_S 6 +/** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE39 (BIT(7)) +#define SOC_ETM_CH_ENABLE39_M (SOC_ETM_CH_ENABLE39_V << SOC_ETM_CH_ENABLE39_S) +#define SOC_ETM_CH_ENABLE39_V 0x00000001U +#define SOC_ETM_CH_ENABLE39_S 7 +/** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE40 (BIT(8)) +#define SOC_ETM_CH_ENABLE40_M (SOC_ETM_CH_ENABLE40_V << SOC_ETM_CH_ENABLE40_S) +#define SOC_ETM_CH_ENABLE40_V 0x00000001U +#define SOC_ETM_CH_ENABLE40_S 8 +/** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE41 (BIT(9)) +#define SOC_ETM_CH_ENABLE41_M (SOC_ETM_CH_ENABLE41_V << SOC_ETM_CH_ENABLE41_S) +#define SOC_ETM_CH_ENABLE41_V 0x00000001U +#define SOC_ETM_CH_ENABLE41_S 9 +/** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE42 (BIT(10)) +#define SOC_ETM_CH_ENABLE42_M (SOC_ETM_CH_ENABLE42_V << SOC_ETM_CH_ENABLE42_S) +#define SOC_ETM_CH_ENABLE42_V 0x00000001U +#define SOC_ETM_CH_ENABLE42_S 10 +/** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE43 (BIT(11)) +#define SOC_ETM_CH_ENABLE43_M (SOC_ETM_CH_ENABLE43_V << SOC_ETM_CH_ENABLE43_S) +#define SOC_ETM_CH_ENABLE43_V 0x00000001U +#define SOC_ETM_CH_ENABLE43_S 11 +/** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE44 (BIT(12)) +#define SOC_ETM_CH_ENABLE44_M (SOC_ETM_CH_ENABLE44_V << SOC_ETM_CH_ENABLE44_S) +#define SOC_ETM_CH_ENABLE44_V 0x00000001U +#define SOC_ETM_CH_ENABLE44_S 12 +/** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE45 (BIT(13)) +#define SOC_ETM_CH_ENABLE45_M (SOC_ETM_CH_ENABLE45_V << SOC_ETM_CH_ENABLE45_S) +#define SOC_ETM_CH_ENABLE45_V 0x00000001U +#define SOC_ETM_CH_ENABLE45_S 13 +/** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE46 (BIT(14)) +#define SOC_ETM_CH_ENABLE46_M (SOC_ETM_CH_ENABLE46_V << SOC_ETM_CH_ENABLE46_S) +#define SOC_ETM_CH_ENABLE46_V 0x00000001U +#define SOC_ETM_CH_ENABLE46_S 14 +/** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE47 (BIT(15)) +#define SOC_ETM_CH_ENABLE47_M (SOC_ETM_CH_ENABLE47_V << SOC_ETM_CH_ENABLE47_S) +#define SOC_ETM_CH_ENABLE47_V 0x00000001U +#define SOC_ETM_CH_ENABLE47_S 15 +/** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE48 (BIT(16)) +#define SOC_ETM_CH_ENABLE48_M (SOC_ETM_CH_ENABLE48_V << SOC_ETM_CH_ENABLE48_S) +#define SOC_ETM_CH_ENABLE48_V 0x00000001U +#define SOC_ETM_CH_ENABLE48_S 16 +/** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ +#define SOC_ETM_CH_ENABLE49 (BIT(17)) +#define SOC_ETM_CH_ENABLE49_M (SOC_ETM_CH_ENABLE49_V << SOC_ETM_CH_ENABLE49_S) +#define SOC_ETM_CH_ENABLE49_V 0x00000001U +#define SOC_ETM_CH_ENABLE49_S 17 + +/** SOC_ETM_CH_ENA_AD1_CLR_REG register + * Channel enable clear register + */ +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) +/** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE32 (BIT(0)) +#define SOC_ETM_CH_DISABLE32_M (SOC_ETM_CH_DISABLE32_V << SOC_ETM_CH_DISABLE32_S) +#define SOC_ETM_CH_DISABLE32_V 0x00000001U +#define SOC_ETM_CH_DISABLE32_S 0 +/** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE33 (BIT(1)) +#define SOC_ETM_CH_DISABLE33_M (SOC_ETM_CH_DISABLE33_V << SOC_ETM_CH_DISABLE33_S) +#define SOC_ETM_CH_DISABLE33_V 0x00000001U +#define SOC_ETM_CH_DISABLE33_S 1 +/** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE34 (BIT(2)) +#define SOC_ETM_CH_DISABLE34_M (SOC_ETM_CH_DISABLE34_V << SOC_ETM_CH_DISABLE34_S) +#define SOC_ETM_CH_DISABLE34_V 0x00000001U +#define SOC_ETM_CH_DISABLE34_S 2 +/** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE35 (BIT(3)) +#define SOC_ETM_CH_DISABLE35_M (SOC_ETM_CH_DISABLE35_V << SOC_ETM_CH_DISABLE35_S) +#define SOC_ETM_CH_DISABLE35_V 0x00000001U +#define SOC_ETM_CH_DISABLE35_S 3 +/** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE36 (BIT(4)) +#define SOC_ETM_CH_DISABLE36_M (SOC_ETM_CH_DISABLE36_V << SOC_ETM_CH_DISABLE36_S) +#define SOC_ETM_CH_DISABLE36_V 0x00000001U +#define SOC_ETM_CH_DISABLE36_S 4 +/** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE37 (BIT(5)) +#define SOC_ETM_CH_DISABLE37_M (SOC_ETM_CH_DISABLE37_V << SOC_ETM_CH_DISABLE37_S) +#define SOC_ETM_CH_DISABLE37_V 0x00000001U +#define SOC_ETM_CH_DISABLE37_S 5 +/** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE38 (BIT(6)) +#define SOC_ETM_CH_DISABLE38_M (SOC_ETM_CH_DISABLE38_V << SOC_ETM_CH_DISABLE38_S) +#define SOC_ETM_CH_DISABLE38_V 0x00000001U +#define SOC_ETM_CH_DISABLE38_S 6 +/** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE39 (BIT(7)) +#define SOC_ETM_CH_DISABLE39_M (SOC_ETM_CH_DISABLE39_V << SOC_ETM_CH_DISABLE39_S) +#define SOC_ETM_CH_DISABLE39_V 0x00000001U +#define SOC_ETM_CH_DISABLE39_S 7 +/** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE40 (BIT(8)) +#define SOC_ETM_CH_DISABLE40_M (SOC_ETM_CH_DISABLE40_V << SOC_ETM_CH_DISABLE40_S) +#define SOC_ETM_CH_DISABLE40_V 0x00000001U +#define SOC_ETM_CH_DISABLE40_S 8 +/** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE41 (BIT(9)) +#define SOC_ETM_CH_DISABLE41_M (SOC_ETM_CH_DISABLE41_V << SOC_ETM_CH_DISABLE41_S) +#define SOC_ETM_CH_DISABLE41_V 0x00000001U +#define SOC_ETM_CH_DISABLE41_S 9 +/** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE42 (BIT(10)) +#define SOC_ETM_CH_DISABLE42_M (SOC_ETM_CH_DISABLE42_V << SOC_ETM_CH_DISABLE42_S) +#define SOC_ETM_CH_DISABLE42_V 0x00000001U +#define SOC_ETM_CH_DISABLE42_S 10 +/** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE43 (BIT(11)) +#define SOC_ETM_CH_DISABLE43_M (SOC_ETM_CH_DISABLE43_V << SOC_ETM_CH_DISABLE43_S) +#define SOC_ETM_CH_DISABLE43_V 0x00000001U +#define SOC_ETM_CH_DISABLE43_S 11 +/** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE44 (BIT(12)) +#define SOC_ETM_CH_DISABLE44_M (SOC_ETM_CH_DISABLE44_V << SOC_ETM_CH_DISABLE44_S) +#define SOC_ETM_CH_DISABLE44_V 0x00000001U +#define SOC_ETM_CH_DISABLE44_S 12 +/** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE45 (BIT(13)) +#define SOC_ETM_CH_DISABLE45_M (SOC_ETM_CH_DISABLE45_V << SOC_ETM_CH_DISABLE45_S) +#define SOC_ETM_CH_DISABLE45_V 0x00000001U +#define SOC_ETM_CH_DISABLE45_S 13 +/** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE46 (BIT(14)) +#define SOC_ETM_CH_DISABLE46_M (SOC_ETM_CH_DISABLE46_V << SOC_ETM_CH_DISABLE46_S) +#define SOC_ETM_CH_DISABLE46_V 0x00000001U +#define SOC_ETM_CH_DISABLE46_S 14 +/** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE47 (BIT(15)) +#define SOC_ETM_CH_DISABLE47_M (SOC_ETM_CH_DISABLE47_V << SOC_ETM_CH_DISABLE47_S) +#define SOC_ETM_CH_DISABLE47_V 0x00000001U +#define SOC_ETM_CH_DISABLE47_S 15 +/** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE48 (BIT(16)) +#define SOC_ETM_CH_DISABLE48_M (SOC_ETM_CH_DISABLE48_V << SOC_ETM_CH_DISABLE48_S) +#define SOC_ETM_CH_DISABLE48_V 0x00000001U +#define SOC_ETM_CH_DISABLE48_S 16 +/** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_CH_DISABLE49 (BIT(17)) +#define SOC_ETM_CH_DISABLE49_M (SOC_ETM_CH_DISABLE49_V << SOC_ETM_CH_DISABLE49_S) +#define SOC_ETM_CH_DISABLE49_V 0x00000001U +#define SOC_ETM_CH_DISABLE49_S 17 + +/** SOC_ETM_CH0_EVT_ID_REG register + * Channel0 event id register + */ +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) +/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_evt_id + */ +#define SOC_ETM_CH0_EVT_ID 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) +#define SOC_ETM_CH0_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH0_EVT_ID_S 0 + +/** SOC_ETM_CH0_TASK_ID_REG register + * Channel0 task id register + */ +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) +/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_task_id + */ +#define SOC_ETM_CH0_TASK_ID 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) +#define SOC_ETM_CH0_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH0_TASK_ID_S 0 + +/** SOC_ETM_CH1_EVT_ID_REG register + * Channel1 event id register + */ +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) +/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_evt_id + */ +#define SOC_ETM_CH1_EVT_ID 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) +#define SOC_ETM_CH1_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH1_EVT_ID_S 0 + +/** SOC_ETM_CH1_TASK_ID_REG register + * Channel1 task id register + */ +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) +/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_task_id + */ +#define SOC_ETM_CH1_TASK_ID 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) +#define SOC_ETM_CH1_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH1_TASK_ID_S 0 + +/** SOC_ETM_CH2_EVT_ID_REG register + * Channel2 event id register + */ +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) +/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_evt_id + */ +#define SOC_ETM_CH2_EVT_ID 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) +#define SOC_ETM_CH2_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH2_EVT_ID_S 0 + +/** SOC_ETM_CH2_TASK_ID_REG register + * Channel2 task id register + */ +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) +/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_task_id + */ +#define SOC_ETM_CH2_TASK_ID 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) +#define SOC_ETM_CH2_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH2_TASK_ID_S 0 + +/** SOC_ETM_CH3_EVT_ID_REG register + * Channel3 event id register + */ +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) +/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_evt_id + */ +#define SOC_ETM_CH3_EVT_ID 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) +#define SOC_ETM_CH3_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH3_EVT_ID_S 0 + +/** SOC_ETM_CH3_TASK_ID_REG register + * Channel3 task id register + */ +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) +/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_task_id + */ +#define SOC_ETM_CH3_TASK_ID 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) +#define SOC_ETM_CH3_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH3_TASK_ID_S 0 + +/** SOC_ETM_CH4_EVT_ID_REG register + * Channel4 event id register + */ +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) +/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_evt_id + */ +#define SOC_ETM_CH4_EVT_ID 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) +#define SOC_ETM_CH4_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH4_EVT_ID_S 0 + +/** SOC_ETM_CH4_TASK_ID_REG register + * Channel4 task id register + */ +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) +/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_task_id + */ +#define SOC_ETM_CH4_TASK_ID 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) +#define SOC_ETM_CH4_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH4_TASK_ID_S 0 + +/** SOC_ETM_CH5_EVT_ID_REG register + * Channel5 event id register + */ +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) +/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_evt_id + */ +#define SOC_ETM_CH5_EVT_ID 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) +#define SOC_ETM_CH5_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH5_EVT_ID_S 0 + +/** SOC_ETM_CH5_TASK_ID_REG register + * Channel5 task id register + */ +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) +/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_task_id + */ +#define SOC_ETM_CH5_TASK_ID 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) +#define SOC_ETM_CH5_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH5_TASK_ID_S 0 + +/** SOC_ETM_CH6_EVT_ID_REG register + * Channel6 event id register + */ +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) +/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_evt_id + */ +#define SOC_ETM_CH6_EVT_ID 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) +#define SOC_ETM_CH6_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH6_EVT_ID_S 0 + +/** SOC_ETM_CH6_TASK_ID_REG register + * Channel6 task id register + */ +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) +/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_task_id + */ +#define SOC_ETM_CH6_TASK_ID 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) +#define SOC_ETM_CH6_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH6_TASK_ID_S 0 + +/** SOC_ETM_CH7_EVT_ID_REG register + * Channel7 event id register + */ +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) +/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_evt_id + */ +#define SOC_ETM_CH7_EVT_ID 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) +#define SOC_ETM_CH7_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH7_EVT_ID_S 0 + +/** SOC_ETM_CH7_TASK_ID_REG register + * Channel7 task id register + */ +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) +/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_task_id + */ +#define SOC_ETM_CH7_TASK_ID 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) +#define SOC_ETM_CH7_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH7_TASK_ID_S 0 + +/** SOC_ETM_CH8_EVT_ID_REG register + * Channel8 event id register + */ +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) +/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_evt_id + */ +#define SOC_ETM_CH8_EVT_ID 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) +#define SOC_ETM_CH8_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH8_EVT_ID_S 0 + +/** SOC_ETM_CH8_TASK_ID_REG register + * Channel8 task id register + */ +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) +/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_task_id + */ +#define SOC_ETM_CH8_TASK_ID 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) +#define SOC_ETM_CH8_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH8_TASK_ID_S 0 + +/** SOC_ETM_CH9_EVT_ID_REG register + * Channel9 event id register + */ +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) +/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_evt_id + */ +#define SOC_ETM_CH9_EVT_ID 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) +#define SOC_ETM_CH9_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH9_EVT_ID_S 0 + +/** SOC_ETM_CH9_TASK_ID_REG register + * Channel9 task id register + */ +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) +/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_task_id + */ +#define SOC_ETM_CH9_TASK_ID 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) +#define SOC_ETM_CH9_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH9_TASK_ID_S 0 + +/** SOC_ETM_CH10_EVT_ID_REG register + * Channel10 event id register + */ +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) +/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_evt_id + */ +#define SOC_ETM_CH10_EVT_ID 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) +#define SOC_ETM_CH10_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH10_EVT_ID_S 0 + +/** SOC_ETM_CH10_TASK_ID_REG register + * Channel10 task id register + */ +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) +/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_task_id + */ +#define SOC_ETM_CH10_TASK_ID 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) +#define SOC_ETM_CH10_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH10_TASK_ID_S 0 + +/** SOC_ETM_CH11_EVT_ID_REG register + * Channel11 event id register + */ +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) +/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_evt_id + */ +#define SOC_ETM_CH11_EVT_ID 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) +#define SOC_ETM_CH11_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH11_EVT_ID_S 0 + +/** SOC_ETM_CH11_TASK_ID_REG register + * Channel11 task id register + */ +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) +/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_task_id + */ +#define SOC_ETM_CH11_TASK_ID 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) +#define SOC_ETM_CH11_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH11_TASK_ID_S 0 + +/** SOC_ETM_CH12_EVT_ID_REG register + * Channel12 event id register + */ +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) +/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_evt_id + */ +#define SOC_ETM_CH12_EVT_ID 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) +#define SOC_ETM_CH12_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH12_EVT_ID_S 0 + +/** SOC_ETM_CH12_TASK_ID_REG register + * Channel12 task id register + */ +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) +/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_task_id + */ +#define SOC_ETM_CH12_TASK_ID 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) +#define SOC_ETM_CH12_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH12_TASK_ID_S 0 + +/** SOC_ETM_CH13_EVT_ID_REG register + * Channel13 event id register + */ +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) +/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_evt_id + */ +#define SOC_ETM_CH13_EVT_ID 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) +#define SOC_ETM_CH13_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH13_EVT_ID_S 0 + +/** SOC_ETM_CH13_TASK_ID_REG register + * Channel13 task id register + */ +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) +/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_task_id + */ +#define SOC_ETM_CH13_TASK_ID 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) +#define SOC_ETM_CH13_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH13_TASK_ID_S 0 + +/** SOC_ETM_CH14_EVT_ID_REG register + * Channel14 event id register + */ +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) +/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_evt_id + */ +#define SOC_ETM_CH14_EVT_ID 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) +#define SOC_ETM_CH14_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH14_EVT_ID_S 0 + +/** SOC_ETM_CH14_TASK_ID_REG register + * Channel14 task id register + */ +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) +/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_task_id + */ +#define SOC_ETM_CH14_TASK_ID 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) +#define SOC_ETM_CH14_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH14_TASK_ID_S 0 + +/** SOC_ETM_CH15_EVT_ID_REG register + * Channel15 event id register + */ +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) +/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_evt_id + */ +#define SOC_ETM_CH15_EVT_ID 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) +#define SOC_ETM_CH15_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH15_EVT_ID_S 0 + +/** SOC_ETM_CH15_TASK_ID_REG register + * Channel15 task id register + */ +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) +/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_task_id + */ +#define SOC_ETM_CH15_TASK_ID 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) +#define SOC_ETM_CH15_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH15_TASK_ID_S 0 + +/** SOC_ETM_CH16_EVT_ID_REG register + * Channel16 event id register + */ +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) +/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_evt_id + */ +#define SOC_ETM_CH16_EVT_ID 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) +#define SOC_ETM_CH16_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH16_EVT_ID_S 0 + +/** SOC_ETM_CH16_TASK_ID_REG register + * Channel16 task id register + */ +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) +/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_task_id + */ +#define SOC_ETM_CH16_TASK_ID 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) +#define SOC_ETM_CH16_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH16_TASK_ID_S 0 + +/** SOC_ETM_CH17_EVT_ID_REG register + * Channel17 event id register + */ +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) +/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_evt_id + */ +#define SOC_ETM_CH17_EVT_ID 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) +#define SOC_ETM_CH17_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH17_EVT_ID_S 0 + +/** SOC_ETM_CH17_TASK_ID_REG register + * Channel17 task id register + */ +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) +/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_task_id + */ +#define SOC_ETM_CH17_TASK_ID 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) +#define SOC_ETM_CH17_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH17_TASK_ID_S 0 + +/** SOC_ETM_CH18_EVT_ID_REG register + * Channel18 event id register + */ +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) +/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_evt_id + */ +#define SOC_ETM_CH18_EVT_ID 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) +#define SOC_ETM_CH18_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH18_EVT_ID_S 0 + +/** SOC_ETM_CH18_TASK_ID_REG register + * Channel18 task id register + */ +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) +/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_task_id + */ +#define SOC_ETM_CH18_TASK_ID 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) +#define SOC_ETM_CH18_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH18_TASK_ID_S 0 + +/** SOC_ETM_CH19_EVT_ID_REG register + * Channel19 event id register + */ +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) +/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_evt_id + */ +#define SOC_ETM_CH19_EVT_ID 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) +#define SOC_ETM_CH19_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH19_EVT_ID_S 0 + +/** SOC_ETM_CH19_TASK_ID_REG register + * Channel19 task id register + */ +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) +/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_task_id + */ +#define SOC_ETM_CH19_TASK_ID 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) +#define SOC_ETM_CH19_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH19_TASK_ID_S 0 + +/** SOC_ETM_CH20_EVT_ID_REG register + * Channel20 event id register + */ +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) +/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_evt_id + */ +#define SOC_ETM_CH20_EVT_ID 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) +#define SOC_ETM_CH20_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH20_EVT_ID_S 0 + +/** SOC_ETM_CH20_TASK_ID_REG register + * Channel20 task id register + */ +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) +/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_task_id + */ +#define SOC_ETM_CH20_TASK_ID 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) +#define SOC_ETM_CH20_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH20_TASK_ID_S 0 + +/** SOC_ETM_CH21_EVT_ID_REG register + * Channel21 event id register + */ +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) +/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_evt_id + */ +#define SOC_ETM_CH21_EVT_ID 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) +#define SOC_ETM_CH21_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH21_EVT_ID_S 0 + +/** SOC_ETM_CH21_TASK_ID_REG register + * Channel21 task id register + */ +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) +/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_task_id + */ +#define SOC_ETM_CH21_TASK_ID 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) +#define SOC_ETM_CH21_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH21_TASK_ID_S 0 + +/** SOC_ETM_CH22_EVT_ID_REG register + * Channel22 event id register + */ +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) +/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_evt_id + */ +#define SOC_ETM_CH22_EVT_ID 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) +#define SOC_ETM_CH22_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH22_EVT_ID_S 0 + +/** SOC_ETM_CH22_TASK_ID_REG register + * Channel22 task id register + */ +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) +/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_task_id + */ +#define SOC_ETM_CH22_TASK_ID 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) +#define SOC_ETM_CH22_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH22_TASK_ID_S 0 + +/** SOC_ETM_CH23_EVT_ID_REG register + * Channel23 event id register + */ +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) +/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_evt_id + */ +#define SOC_ETM_CH23_EVT_ID 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) +#define SOC_ETM_CH23_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH23_EVT_ID_S 0 + +/** SOC_ETM_CH23_TASK_ID_REG register + * Channel23 task id register + */ +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) +/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_task_id + */ +#define SOC_ETM_CH23_TASK_ID 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) +#define SOC_ETM_CH23_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH23_TASK_ID_S 0 + +/** SOC_ETM_CH24_EVT_ID_REG register + * Channel24 event id register + */ +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) +/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_evt_id + */ +#define SOC_ETM_CH24_EVT_ID 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) +#define SOC_ETM_CH24_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH24_EVT_ID_S 0 + +/** SOC_ETM_CH24_TASK_ID_REG register + * Channel24 task id register + */ +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) +/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_task_id + */ +#define SOC_ETM_CH24_TASK_ID 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) +#define SOC_ETM_CH24_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH24_TASK_ID_S 0 + +/** SOC_ETM_CH25_EVT_ID_REG register + * Channel25 event id register + */ +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) +/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_evt_id + */ +#define SOC_ETM_CH25_EVT_ID 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) +#define SOC_ETM_CH25_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH25_EVT_ID_S 0 + +/** SOC_ETM_CH25_TASK_ID_REG register + * Channel25 task id register + */ +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) +/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_task_id + */ +#define SOC_ETM_CH25_TASK_ID 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) +#define SOC_ETM_CH25_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH25_TASK_ID_S 0 + +/** SOC_ETM_CH26_EVT_ID_REG register + * Channel26 event id register + */ +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) +/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_evt_id + */ +#define SOC_ETM_CH26_EVT_ID 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) +#define SOC_ETM_CH26_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH26_EVT_ID_S 0 + +/** SOC_ETM_CH26_TASK_ID_REG register + * Channel26 task id register + */ +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) +/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_task_id + */ +#define SOC_ETM_CH26_TASK_ID 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) +#define SOC_ETM_CH26_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH26_TASK_ID_S 0 + +/** SOC_ETM_CH27_EVT_ID_REG register + * Channel27 event id register + */ +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) +/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_evt_id + */ +#define SOC_ETM_CH27_EVT_ID 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) +#define SOC_ETM_CH27_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH27_EVT_ID_S 0 + +/** SOC_ETM_CH27_TASK_ID_REG register + * Channel27 task id register + */ +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) +/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_task_id + */ +#define SOC_ETM_CH27_TASK_ID 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) +#define SOC_ETM_CH27_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH27_TASK_ID_S 0 + +/** SOC_ETM_CH28_EVT_ID_REG register + * Channel28 event id register + */ +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) +/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_evt_id + */ +#define SOC_ETM_CH28_EVT_ID 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) +#define SOC_ETM_CH28_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH28_EVT_ID_S 0 + +/** SOC_ETM_CH28_TASK_ID_REG register + * Channel28 task id register + */ +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) +/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_task_id + */ +#define SOC_ETM_CH28_TASK_ID 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) +#define SOC_ETM_CH28_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH28_TASK_ID_S 0 + +/** SOC_ETM_CH29_EVT_ID_REG register + * Channel29 event id register + */ +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) +/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_evt_id + */ +#define SOC_ETM_CH29_EVT_ID 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) +#define SOC_ETM_CH29_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH29_EVT_ID_S 0 + +/** SOC_ETM_CH29_TASK_ID_REG register + * Channel29 task id register + */ +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) +/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_task_id + */ +#define SOC_ETM_CH29_TASK_ID 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) +#define SOC_ETM_CH29_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH29_TASK_ID_S 0 + +/** SOC_ETM_CH30_EVT_ID_REG register + * Channel30 event id register + */ +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) +/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_evt_id + */ +#define SOC_ETM_CH30_EVT_ID 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) +#define SOC_ETM_CH30_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH30_EVT_ID_S 0 + +/** SOC_ETM_CH30_TASK_ID_REG register + * Channel30 task id register + */ +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) +/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_task_id + */ +#define SOC_ETM_CH30_TASK_ID 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) +#define SOC_ETM_CH30_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH30_TASK_ID_S 0 + +/** SOC_ETM_CH31_EVT_ID_REG register + * Channel31 event id register + */ +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) +/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_evt_id + */ +#define SOC_ETM_CH31_EVT_ID 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) +#define SOC_ETM_CH31_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH31_EVT_ID_S 0 + +/** SOC_ETM_CH31_TASK_ID_REG register + * Channel31 task id register + */ +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) +/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_task_id + */ +#define SOC_ETM_CH31_TASK_ID 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) +#define SOC_ETM_CH31_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH31_TASK_ID_S 0 + +/** SOC_ETM_CH32_EVT_ID_REG register + * Channel32 event id register + */ +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) +/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_evt_id + */ +#define SOC_ETM_CH32_EVT_ID 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) +#define SOC_ETM_CH32_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH32_EVT_ID_S 0 + +/** SOC_ETM_CH32_TASK_ID_REG register + * Channel32 task id register + */ +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) +/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_task_id + */ +#define SOC_ETM_CH32_TASK_ID 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) +#define SOC_ETM_CH32_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH32_TASK_ID_S 0 + +/** SOC_ETM_CH33_EVT_ID_REG register + * Channel33 event id register + */ +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) +/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_evt_id + */ +#define SOC_ETM_CH33_EVT_ID 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) +#define SOC_ETM_CH33_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH33_EVT_ID_S 0 + +/** SOC_ETM_CH33_TASK_ID_REG register + * Channel33 task id register + */ +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) +/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_task_id + */ +#define SOC_ETM_CH33_TASK_ID 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) +#define SOC_ETM_CH33_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH33_TASK_ID_S 0 + +/** SOC_ETM_CH34_EVT_ID_REG register + * Channel34 event id register + */ +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) +/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_evt_id + */ +#define SOC_ETM_CH34_EVT_ID 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) +#define SOC_ETM_CH34_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH34_EVT_ID_S 0 + +/** SOC_ETM_CH34_TASK_ID_REG register + * Channel34 task id register + */ +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) +/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_task_id + */ +#define SOC_ETM_CH34_TASK_ID 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) +#define SOC_ETM_CH34_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH34_TASK_ID_S 0 + +/** SOC_ETM_CH35_EVT_ID_REG register + * Channel35 event id register + */ +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) +/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_evt_id + */ +#define SOC_ETM_CH35_EVT_ID 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) +#define SOC_ETM_CH35_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH35_EVT_ID_S 0 + +/** SOC_ETM_CH35_TASK_ID_REG register + * Channel35 task id register + */ +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) +/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_task_id + */ +#define SOC_ETM_CH35_TASK_ID 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) +#define SOC_ETM_CH35_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH35_TASK_ID_S 0 + +/** SOC_ETM_CH36_EVT_ID_REG register + * Channel36 event id register + */ +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) +/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_evt_id + */ +#define SOC_ETM_CH36_EVT_ID 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) +#define SOC_ETM_CH36_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH36_EVT_ID_S 0 + +/** SOC_ETM_CH36_TASK_ID_REG register + * Channel36 task id register + */ +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) +/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_task_id + */ +#define SOC_ETM_CH36_TASK_ID 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) +#define SOC_ETM_CH36_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH36_TASK_ID_S 0 + +/** SOC_ETM_CH37_EVT_ID_REG register + * Channel37 event id register + */ +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) +/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_evt_id + */ +#define SOC_ETM_CH37_EVT_ID 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) +#define SOC_ETM_CH37_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH37_EVT_ID_S 0 + +/** SOC_ETM_CH37_TASK_ID_REG register + * Channel37 task id register + */ +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) +/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_task_id + */ +#define SOC_ETM_CH37_TASK_ID 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) +#define SOC_ETM_CH37_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH37_TASK_ID_S 0 + +/** SOC_ETM_CH38_EVT_ID_REG register + * Channel38 event id register + */ +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) +/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_evt_id + */ +#define SOC_ETM_CH38_EVT_ID 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) +#define SOC_ETM_CH38_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH38_EVT_ID_S 0 + +/** SOC_ETM_CH38_TASK_ID_REG register + * Channel38 task id register + */ +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) +/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_task_id + */ +#define SOC_ETM_CH38_TASK_ID 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) +#define SOC_ETM_CH38_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH38_TASK_ID_S 0 + +/** SOC_ETM_CH39_EVT_ID_REG register + * Channel39 event id register + */ +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) +/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_evt_id + */ +#define SOC_ETM_CH39_EVT_ID 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) +#define SOC_ETM_CH39_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH39_EVT_ID_S 0 + +/** SOC_ETM_CH39_TASK_ID_REG register + * Channel39 task id register + */ +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) +/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_task_id + */ +#define SOC_ETM_CH39_TASK_ID 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) +#define SOC_ETM_CH39_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH39_TASK_ID_S 0 + +/** SOC_ETM_CH40_EVT_ID_REG register + * Channel40 event id register + */ +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) +/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_evt_id + */ +#define SOC_ETM_CH40_EVT_ID 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) +#define SOC_ETM_CH40_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH40_EVT_ID_S 0 + +/** SOC_ETM_CH40_TASK_ID_REG register + * Channel40 task id register + */ +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) +/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_task_id + */ +#define SOC_ETM_CH40_TASK_ID 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) +#define SOC_ETM_CH40_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH40_TASK_ID_S 0 + +/** SOC_ETM_CH41_EVT_ID_REG register + * Channel41 event id register + */ +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) +/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_evt_id + */ +#define SOC_ETM_CH41_EVT_ID 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) +#define SOC_ETM_CH41_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH41_EVT_ID_S 0 + +/** SOC_ETM_CH41_TASK_ID_REG register + * Channel41 task id register + */ +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) +/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_task_id + */ +#define SOC_ETM_CH41_TASK_ID 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) +#define SOC_ETM_CH41_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH41_TASK_ID_S 0 + +/** SOC_ETM_CH42_EVT_ID_REG register + * Channel42 event id register + */ +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) +/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_evt_id + */ +#define SOC_ETM_CH42_EVT_ID 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) +#define SOC_ETM_CH42_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH42_EVT_ID_S 0 + +/** SOC_ETM_CH42_TASK_ID_REG register + * Channel42 task id register + */ +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) +/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_task_id + */ +#define SOC_ETM_CH42_TASK_ID 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) +#define SOC_ETM_CH42_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH42_TASK_ID_S 0 + +/** SOC_ETM_CH43_EVT_ID_REG register + * Channel43 event id register + */ +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) +/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_evt_id + */ +#define SOC_ETM_CH43_EVT_ID 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) +#define SOC_ETM_CH43_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH43_EVT_ID_S 0 + +/** SOC_ETM_CH43_TASK_ID_REG register + * Channel43 task id register + */ +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) +/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_task_id + */ +#define SOC_ETM_CH43_TASK_ID 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) +#define SOC_ETM_CH43_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH43_TASK_ID_S 0 + +/** SOC_ETM_CH44_EVT_ID_REG register + * Channel44 event id register + */ +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) +/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_evt_id + */ +#define SOC_ETM_CH44_EVT_ID 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) +#define SOC_ETM_CH44_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH44_EVT_ID_S 0 + +/** SOC_ETM_CH44_TASK_ID_REG register + * Channel44 task id register + */ +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) +/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_task_id + */ +#define SOC_ETM_CH44_TASK_ID 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) +#define SOC_ETM_CH44_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH44_TASK_ID_S 0 + +/** SOC_ETM_CH45_EVT_ID_REG register + * Channel45 event id register + */ +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) +/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_evt_id + */ +#define SOC_ETM_CH45_EVT_ID 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) +#define SOC_ETM_CH45_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH45_EVT_ID_S 0 + +/** SOC_ETM_CH45_TASK_ID_REG register + * Channel45 task id register + */ +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) +/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_task_id + */ +#define SOC_ETM_CH45_TASK_ID 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) +#define SOC_ETM_CH45_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH45_TASK_ID_S 0 + +/** SOC_ETM_CH46_EVT_ID_REG register + * Channel46 event id register + */ +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) +/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_evt_id + */ +#define SOC_ETM_CH46_EVT_ID 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) +#define SOC_ETM_CH46_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH46_EVT_ID_S 0 + +/** SOC_ETM_CH46_TASK_ID_REG register + * Channel46 task id register + */ +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) +/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_task_id + */ +#define SOC_ETM_CH46_TASK_ID 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) +#define SOC_ETM_CH46_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH46_TASK_ID_S 0 + +/** SOC_ETM_CH47_EVT_ID_REG register + * Channel47 event id register + */ +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) +/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_evt_id + */ +#define SOC_ETM_CH47_EVT_ID 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) +#define SOC_ETM_CH47_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH47_EVT_ID_S 0 + +/** SOC_ETM_CH47_TASK_ID_REG register + * Channel47 task id register + */ +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) +/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_task_id + */ +#define SOC_ETM_CH47_TASK_ID 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) +#define SOC_ETM_CH47_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH47_TASK_ID_S 0 + +/** SOC_ETM_CH48_EVT_ID_REG register + * Channel48 event id register + */ +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) +/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_evt_id + */ +#define SOC_ETM_CH48_EVT_ID 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) +#define SOC_ETM_CH48_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH48_EVT_ID_S 0 + +/** SOC_ETM_CH48_TASK_ID_REG register + * Channel48 task id register + */ +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) +/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_task_id + */ +#define SOC_ETM_CH48_TASK_ID 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) +#define SOC_ETM_CH48_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH48_TASK_ID_S 0 + +/** SOC_ETM_CH49_EVT_ID_REG register + * Channel49 event id register + */ +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) +/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_evt_id + */ +#define SOC_ETM_CH49_EVT_ID 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) +#define SOC_ETM_CH49_EVT_ID_V 0x000000FFU +#define SOC_ETM_CH49_EVT_ID_S 0 + +/** SOC_ETM_CH49_TASK_ID_REG register + * Channel49 task id register + */ +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) +/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_task_id + */ +#define SOC_ETM_CH49_TASK_ID 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) +#define SOC_ETM_CH49_TASK_ID_V 0x000000FFU +#define SOC_ETM_CH49_TASK_ID_S 0 + +/** SOC_ETM_EVT_ST0_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_S 25 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST (BIT(26)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S 26 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST (BIT(27)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S 31 + +/** SOC_ETM_EVT_ST0_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) +/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S 0 +/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S 1 +/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S 2 +/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S 3 +/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S 4 +/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S 5 +/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S 6 +/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S 7 +/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S 8 +/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S 9 +/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S 10 +/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S 11 +/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S 12 +/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S 13 +/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S 14 +/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S 15 +/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S 16 +/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S 17 +/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S 18 +/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S 19 +/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S 20 +/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S 21 +/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S 22 +/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_M (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S 23 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR (BIT(24)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_S 24 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR (BIT(25)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_S 25 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S 26 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S 27 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S 28 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S 29 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S 30 +/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST1_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST (BIT(0)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S 0 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST (BIT(1)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S 1 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST (BIT(2)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S 2 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST (BIT(3)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S 5 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST (BIT(6)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S 6 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST (BIT(7)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S 7 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST (BIT(8)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S 8 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST (BIT(9)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S 9 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST (BIT(10)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S 10 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST (BIT(11)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S 11 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S 12 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S 13 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST (BIT(14)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S 14 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST (BIT(15)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S 15 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST (BIT(16)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S 16 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST (BIT(17)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S 17 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST (BIT(18)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S 18 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST (BIT(19)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S 19 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST (BIT(20)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S 20 +/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S 21 +/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S 22 +/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S 23 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S 24 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST (BIT(25)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S 25 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST (BIT(26)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S 26 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S 27 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S 28 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S 29 +/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S 30 +/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST (BIT(31)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S 31 + +/** SOC_ETM_EVT_ST1_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S 0 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S 1 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S 2 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S 3 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S 4 +/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_M (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S 5 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S 6 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S 7 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S 8 +/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_M (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S 9 +/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S 10 +/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S 11 +/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S 12 +/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_M (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S) +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S 13 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(14)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S 14 +/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(15)) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S 15 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(16)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S 16 +/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(17)) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_M (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S 17 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR (BIT(18)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S 18 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR (BIT(19)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S 19 +/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR (BIT(20)) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_M (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S) +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V 0x00000001U +#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S 24 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S 25 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR (BIT(26)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S 26 +/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR (BIT(27)) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S 27 +/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR (BIT(28)) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S 28 +/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR (BIT(29)) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S 29 +/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR (BIT(30)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S 30 +/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR (BIT(31)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST2_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) +/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST (BIT(0)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S 0 +/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST (BIT(1)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S 1 +/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST (BIT(2)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S 2 +/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST (BIT(3)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S 3 +/** SOC_ETM_MCPWM0_EVT_F0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F0_ST (BIT(4)) +#define SOC_ETM_MCPWM0_EVT_F0_ST_M (SOC_ETM_MCPWM0_EVT_F0_ST_V << SOC_ETM_MCPWM0_EVT_F0_ST_S) +#define SOC_ETM_MCPWM0_EVT_F0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_ST_S 4 +/** SOC_ETM_MCPWM0_EVT_F1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F1_ST (BIT(5)) +#define SOC_ETM_MCPWM0_EVT_F1_ST_M (SOC_ETM_MCPWM0_EVT_F1_ST_V << SOC_ETM_MCPWM0_EVT_F1_ST_S) +#define SOC_ETM_MCPWM0_EVT_F1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_ST_S 5 +/** SOC_ETM_MCPWM0_EVT_F2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F2_ST (BIT(6)) +#define SOC_ETM_MCPWM0_EVT_F2_ST_M (SOC_ETM_MCPWM0_EVT_F2_ST_V << SOC_ETM_MCPWM0_EVT_F2_ST_S) +#define SOC_ETM_MCPWM0_EVT_F2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_ST_S 6 +/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST (BIT(7)) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S 7 +/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST (BIT(8)) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S 8 +/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST (BIT(9)) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_M (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S 9 +/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST (BIT(10)) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S 10 +/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST (BIT(11)) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S 11 +/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST (BIT(12)) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_M (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S 12 +/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST (BIT(13)) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S 13 +/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST (BIT(14)) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S 14 +/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST (BIT(15)) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_M (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S 15 +/** SOC_ETM_MCPWM0_EVT_CAP0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP0_ST (BIT(16)) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_M (SOC_ETM_MCPWM0_EVT_CAP0_ST_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_S 16 +/** SOC_ETM_MCPWM0_EVT_CAP1_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP1_ST (BIT(17)) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_M (SOC_ETM_MCPWM0_EVT_CAP1_ST_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_S 17 +/** SOC_ETM_MCPWM0_EVT_CAP2_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_CAP2_ST (BIT(18)) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_M (SOC_ETM_MCPWM0_EVT_CAP2_ST_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_S) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_S 18 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST (BIT(19)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S 19 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST (BIT(20)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S 20 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S 21 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S 22 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S 23 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_M (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S 24 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST (BIT(25)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S 25 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST (BIT(26)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S 26 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST (BIT(27)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S 27 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST (BIT(28)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S 28 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST (BIT(29)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S 29 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST (BIT(30)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S 30 +/** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST (BIT(31)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_M (SOC_ETM_ADC_EVT_STOPPED0_ST_V << SOC_ETM_ADC_EVT_STOPPED0_ST_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_S 31 + +/** SOC_ETM_EVT_ST2_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) +/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR (BIT(0)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S 0 +/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR (BIT(1)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S 1 +/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR (BIT(2)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S 2 +/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR (BIT(3)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S 3 +/** SOC_ETM_MCPWM0_EVT_F0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S 4 +/** SOC_ETM_MCPWM0_EVT_F1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S 5 +/** SOC_ETM_MCPWM0_EVT_F2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S 6 +/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S 7 +/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S 8 +/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_M (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S 9 +/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S 10 +/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S 11 +/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S 12 +/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S 13 +/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S 14 +/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S 15 +/** SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S 16 +/** SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S 17 +/** SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S 18 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S 19 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_M (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S) +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S 24 +/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR (BIT(25)) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_M (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S 25 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR (BIT(26)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S 26 +/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR (BIT(27)) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S 27 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR (BIT(28)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S 28 +/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR (BIT(29)) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_M (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S) +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S 29 +/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR (BIT(30)) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_M (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S 30 +/** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR (BIT(31)) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_M (SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V << SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST3_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) +/** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST (BIT(0)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_M (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_S 0 +/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_M (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_S 1 +/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_M (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_S 2 +/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST (BIT(3)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_M (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_S 3 +/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST (BIT(4)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_M (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_S 4 +/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_M (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_S 5 +/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_M (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_S 6 +/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST (BIT(7)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_M (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_S 7 +/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST (BIT(8)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_M (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_S 8 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GDMA_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST (BIT(9)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_S 9 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST (BIT(10)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_S 10 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GDMA_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST (BIT(11)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_S 11 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST (BIT(12)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_S 12 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST (BIT(13)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_S 13 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST (BIT(14)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_S 14 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST (BIT(15)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_S 15 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST (BIT(16)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_S 16 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(17)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_S 17 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST (BIT(18)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_S 18 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST (BIT(19)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_S 19 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST (BIT(20)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_S 20 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GDMA_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST (BIT(21)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_S 21 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GDMA_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST (BIT(22)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_S 22 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GDMA_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST (BIT(23)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_S 23 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST (BIT(24)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_S 24 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GDMA_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST (BIT(25)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_S 25 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GDMA_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST (BIT(26)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_S 26 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST (BIT(27)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_S 27 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST (BIT(28)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_S 28 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(29)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_S 29 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST (BIT(30)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_S 30 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST (BIT(31)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_S 31 + +/** SOC_ETM_EVT_ST3_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) +/** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR (BIT(0)) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S) +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S 0 +/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S 1 +/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S 2 +/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR (BIT(3)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S 3 +/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR (BIT(4)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S 4 +/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S 5 +/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S 6 +/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR (BIT(7)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S 7 +/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR (BIT(8)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S 8 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR (BIT(9)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_S 9 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR (BIT(10)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_S 10 +/** SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR (BIT(11)) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_S 11 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_S 12 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_S 13 +/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_S 14 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(15)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 15 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(16)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 16 +/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(17)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 17 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(18)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 18 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(19)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 19 +/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(20)) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 20 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR (BIT(21)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_S 21 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR (BIT(22)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_S 22 +/** SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR (BIT(23)) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_S 23 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR (BIT(24)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_S 24 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR (BIT(25)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_S 25 +/** SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR (BIT(26)) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_S 26 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(27)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 27 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(28)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 28 +/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(29)) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 29 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 30 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 31 + +/** SOC_ETM_EVT_ST4_REG register + * Events trigger status register + */ +#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8) +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(0)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_S 0 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST (BIT(1)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_S 1 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST (BIT(2)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_S 2 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST (BIT(3)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_S 3 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST (BIT(4)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S 4 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST (BIT(5)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_S 5 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST (BIT(6)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_S 6 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST (BIT(7)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S 7 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST (BIT(8)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S 8 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST (BIT(9)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S 9 +/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_HALT_ST (BIT(10)) +#define SOC_ETM_ULP_EVT_HALT_ST_M (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S) +#define SOC_ETM_ULP_EVT_HALT_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_S 10 +/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST (BIT(11)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_M (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_S 11 +/** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_TICK_ST (BIT(12)) +#define SOC_ETM_RTC_EVT_TICK_ST_M (SOC_ETM_RTC_EVT_TICK_ST_V << SOC_ETM_RTC_EVT_TICK_ST_S) +#define SOC_ETM_RTC_EVT_TICK_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_S 12 +/** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_OVF_ST (BIT(13)) +#define SOC_ETM_RTC_EVT_OVF_ST_M (SOC_ETM_RTC_EVT_OVF_ST_V << SOC_ETM_RTC_EVT_OVF_ST_S) +#define SOC_ETM_RTC_EVT_OVF_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_S 13 +/** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_EVT_CMP_ST (BIT(14)) +#define SOC_ETM_RTC_EVT_CMP_ST_M (SOC_ETM_RTC_EVT_CMP_ST_V << SOC_ETM_RTC_EVT_CMP_ST_S) +#define SOC_ETM_RTC_EVT_CMP_ST_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_S 14 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST (BIT(15)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S 15 + +/** SOC_ETM_EVT_ST4_CLR_REG register + * Events trigger status clear register + */ +#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) +/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 0 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 1 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(2)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 2 +/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(3)) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 3 +/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR (BIT(4)) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_M (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S) +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S 4 +/** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR (BIT(5)) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S 5 +/** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR (BIT(6)) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S 6 +/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(7)) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S 7 +/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR (BIT(8)) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S 8 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR (BIT(9)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S 9 +/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_HALT_ST_CLR (BIT(10)) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S 10 +/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR (BIT(11)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S 11 +/** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_TICK_ST_CLR (BIT(12)) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_M (SOC_ETM_RTC_EVT_TICK_ST_CLR_V << SOC_ETM_RTC_EVT_TICK_ST_CLR_S) +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_TICK_ST_CLR_S 12 +/** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_OVF_ST_CLR (BIT(13)) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_M (SOC_ETM_RTC_EVT_OVF_ST_CLR_V << SOC_ETM_RTC_EVT_OVF_ST_CLR_S) +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_OVF_ST_CLR_S 13 +/** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_EVT_CMP_ST_CLR (BIT(14)) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_M (SOC_ETM_RTC_EVT_CMP_ST_CLR_V << SOC_ETM_RTC_EVT_CMP_ST_CLR_S) +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_EVT_CMP_ST_CLR_S 14 +/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR (BIT(15)) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_M (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S) +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S 15 + +/** SOC_ETM_TASK_ST0_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1d0) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S 31 + +/** SOC_ETM_TASK_ST0_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) +/** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR (BIT(0)) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S 0 +/** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR (BIT(1)) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S 1 +/** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR (BIT(2)) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S 2 +/** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR (BIT(3)) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S 3 +/** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR (BIT(4)) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S 4 +/** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR (BIT(5)) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S 5 +/** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR (BIT(6)) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S 6 +/** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR (BIT(7)) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S 7 +/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR (BIT(8)) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S 8 +/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR (BIT(9)) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S 9 +/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR (BIT(10)) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S 10 +/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR (BIT(11)) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S 11 +/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR (BIT(12)) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S 12 +/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR (BIT(13)) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S 13 +/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR (BIT(14)) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S 14 +/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR (BIT(15)) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S 15 +/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR (BIT(16)) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S 16 +/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR (BIT(17)) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S 17 +/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR (BIT(18)) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S 18 +/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR (BIT(19)) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S 19 +/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR (BIT(20)) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S 20 +/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR (BIT(21)) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S 21 +/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR (BIT(22)) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S 22 +/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR (BIT(23)) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_M (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S) +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST1_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1d8) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S 1 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S 2 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S 3 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S 4 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S 5 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S 6 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S 11 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S 12 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S 13 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S 14 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S 17 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST (BIT(18)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S 18 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST (BIT(19)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S 19 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST (BIT(20)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S 20 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST (BIT(21)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S 21 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST (BIT(22)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S 22 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST (BIT(23)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S 23 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S 24 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S 25 +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S 26 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S 27 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S 28 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S 29 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST (BIT(30)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S 30 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST (BIT(31)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S 31 + +/** SOC_ETM_TASK_ST1_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S 15 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR (BIT(16)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S 16 +/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR (BIT(17)) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S 17 +/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR (BIT(18)) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S 18 +/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR (BIT(19)) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S 19 +/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR (BIT(20)) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S 20 +/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR (BIT(21)) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S 21 +/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR (BIT(22)) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S 22 +/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR (BIT(23)) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S 23 +/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR (BIT(24)) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S 24 +/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR (BIT(25)) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S 25 +/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR (BIT(26)) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S 26 +/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR (BIT(27)) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S 27 +/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR (BIT(28)) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S 28 +/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR (BIT(29)) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_M (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S 29 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR (BIT(30)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S 30 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR (BIT(31)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST2_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1e0) +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST (BIT(0)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S 0 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST (BIT(1)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S 1 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST (BIT(2)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S 2 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST (BIT(3)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S 15 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST (BIT(16)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S 16 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST (BIT(17)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S 17 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST (BIT(18)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S 18 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST (BIT(19)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S 19 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST (BIT(20)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S 20 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST (BIT(21)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S 21 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST (BIT(22)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S 22 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST (BIT(23)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S 23 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST (BIT(24)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S 24 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST (BIT(25)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S 25 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST (BIT(26)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S 26 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST (BIT(27)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S 27 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST (BIT(28)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S 28 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST (BIT(29)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S 29 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST (BIT(30)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S 30 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST (BIT(31)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S 31 + +/** SOC_ETM_TASK_ST2_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR (BIT(0)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S 0 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR (BIT(1)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S 1 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR (BIT(2)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S 2 +/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR (BIT(3)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S 3 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR (BIT(4)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S 4 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR (BIT(5)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S 5 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR (BIT(6)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S 6 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR (BIT(7)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S 7 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR (BIT(8)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S 8 +/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR (BIT(9)) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S 9 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR (BIT(10)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S 10 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR (BIT(11)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S 11 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR (BIT(12)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S 12 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR (BIT(13)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S 13 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR (BIT(14)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S 14 +/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR (BIT(15)) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_M (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S) +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V 0x00000001U +#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S 15 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR (BIT(16)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S 16 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR (BIT(17)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S 17 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(18)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S 18 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(19)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 19 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(20)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S 20 +/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR (BIT(21)) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S 21 +/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR (BIT(22)) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S 22 +/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(23)) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S 23 +/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(24)) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 24 +/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(25)) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S 25 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR (BIT(26)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S 26 +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR (BIT(27)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S 27 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(28)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S 28 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(29)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 29 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(30)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S 30 +/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR (BIT(31)) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST3_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1e8) +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST (BIT(0)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S 0 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST (BIT(1)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S 1 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST (BIT(2)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S 2 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST (BIT(3)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S 3 +/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST (BIT(4)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S 4 +/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST (BIT(5)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S 5 +/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST (BIT(6)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S 6 +/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST (BIT(7)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S 7 +/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST (BIT(8)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S 8 +/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST (BIT(9)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_M (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S 9 +/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST (BIT(10)) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_M (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S 10 +/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST (BIT(11)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S 11 +/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST (BIT(12)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S 12 +/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST (BIT(13)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_M (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S 13 +/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST (BIT(14)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S 14 +/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST (BIT(15)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S 15 +/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST (BIT(16)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_M (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S 16 +/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST (BIT(17)) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S 17 +/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST (BIT(18)) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S 18 +/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST (BIT(19)) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_M (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S 19 +/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST (BIT(20)) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S 20 +/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST (BIT(21)) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S 21 +/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST (BIT(22)) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_M (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S 22 +/** SOC_ETM_MCPWM0_TASK_CAP0_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP0_ST (BIT(23)) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_M (SOC_ETM_MCPWM0_TASK_CAP0_ST_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_S 23 +/** SOC_ETM_MCPWM0_TASK_CAP1_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP1_ST (BIT(24)) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_M (SOC_ETM_MCPWM0_TASK_CAP1_ST_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_S 24 +/** SOC_ETM_MCPWM0_TASK_CAP2_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_MCPWM0_TASK_CAP2_ST (BIT(25)) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_M (SOC_ETM_MCPWM0_TASK_CAP2_ST_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_S) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_S 25 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST (BIT(26)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 26 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(27)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 27 +/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_START0_ST (BIT(28)) +#define SOC_ETM_ADC_TASK_START0_ST_M (SOC_ETM_ADC_TASK_START0_ST_V << SOC_ETM_ADC_TASK_START0_ST_S) +#define SOC_ETM_ADC_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_S 28 +/** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ADC_TASK_STOP0_ST (BIT(29)) +#define SOC_ETM_ADC_TASK_STOP0_ST_M (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_S 29 +/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START0_ST (BIT(30)) +#define SOC_ETM_REGDMA_TASK_START0_ST_M (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_S 30 +/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START1_ST (BIT(31)) +#define SOC_ETM_REGDMA_TASK_START1_ST_M (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_S 31 + +/** SOC_ETM_TASK_ST3_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) +/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR (BIT(0)) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S 0 +/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(1)) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S 1 +/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(2)) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 2 +/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(3)) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_M (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S) +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U +#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S 3 +/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR (BIT(4)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S 4 +/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR (BIT(5)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S 5 +/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR (BIT(6)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S 6 +/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR (BIT(7)) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S 7 +/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR (BIT(8)) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S 8 +/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR (BIT(9)) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S 9 +/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR (BIT(10)) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S 10 +/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR (BIT(11)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S 11 +/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR (BIT(12)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S 12 +/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR (BIT(13)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S 13 +/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR (BIT(14)) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S 14 +/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR (BIT(15)) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S 15 +/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR (BIT(16)) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S 16 +/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR (BIT(17)) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S 17 +/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR (BIT(18)) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S 18 +/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR (BIT(19)) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S 19 +/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR (BIT(20)) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S 20 +/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR (BIT(21)) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S 21 +/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR (BIT(22)) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S 22 +/** SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR (BIT(23)) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S 23 +/** SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR (BIT(24)) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S 24 +/** SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR (BIT(25)) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_M (SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S) +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V 0x00000001U +#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S 25 +/** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR (BIT(26)) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 26 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(27)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 27 +/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_START0_ST_CLR (BIT(28)) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_M (SOC_ETM_ADC_TASK_START0_ST_CLR_V << SOC_ETM_ADC_TASK_START0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_START0_ST_CLR_S 28 +/** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR (BIT(29)) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S) +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S 29 +/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR (BIT(30)) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S 30 +/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR (BIT(31)) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S 31 + +/** SOC_ETM_TASK_ST4_REG register + * Tasks trigger status register + */ +#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1f0) +/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START2_ST (BIT(0)) +#define SOC_ETM_REGDMA_TASK_START2_ST_M (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_S 0 +/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START3_ST (BIT(1)) +#define SOC_ETM_REGDMA_TASK_START3_ST_M (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_S 1 +/** SOC_ETM_GDMA_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST (BIT(2)) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_M (SOC_ETM_GDMA_TASK_IN_START_CH0_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH0_ST_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_S 2 +/** SOC_ETM_GDMA_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST (BIT(3)) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_M (SOC_ETM_GDMA_TASK_IN_START_CH1_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH1_ST_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_S 3 +/** SOC_ETM_GDMA_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST (BIT(4)) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_M (SOC_ETM_GDMA_TASK_IN_START_CH2_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_S 4 +/** SOC_ETM_GDMA_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GDMA_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST (BIT(5)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_M (SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_S 5 +/** SOC_ETM_GDMA_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GDMA_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST (BIT(6)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_M (SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_S 6 +/** SOC_ETM_GDMA_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST (BIT(7)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_M (SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_S 7 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST (BIT(8)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S 8 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST (BIT(9)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S 9 +/** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST (BIT(10)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_M (SOC_ETM_I2S0_TASK_START_RX_ST_V << SOC_ETM_I2S0_TASK_START_RX_ST_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_S 10 +/** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST (BIT(11)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_M (SOC_ETM_I2S0_TASK_START_TX_ST_V << SOC_ETM_I2S0_TASK_START_TX_ST_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_S 11 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST (BIT(12)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_S 12 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST (BIT(13)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_S 13 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST (BIT(14)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S 14 +/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST (BIT(15)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_M (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_S 15 +/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_START_ST (BIT(16)) +#define SOC_ETM_RTC_TASK_START_ST_M (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S) +#define SOC_ETM_RTC_TASK_START_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_S 16 +/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_STOP_ST (BIT(17)) +#define SOC_ETM_RTC_TASK_STOP_ST_M (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S) +#define SOC_ETM_RTC_TASK_STOP_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_S 17 +/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_CLR_ST (BIT(18)) +#define SOC_ETM_RTC_TASK_CLR_ST_M (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S) +#define SOC_ETM_RTC_TASK_CLR_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_S 18 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST (BIT(19)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S 19 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST (BIT(20)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S 20 + +/** SOC_ETM_TASK_ST4_CLR_REG register + * Tasks trigger status clear register + */ +#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4) +/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR (BIT(0)) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S 0 +/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S 1 +/** SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR (BIT(2)) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_M (SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_S 2 +/** SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR (BIT(3)) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_S 3 +/** SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR (BIT(4)) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_S 4 +/** SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR (BIT(5)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_M (SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_S 5 +/** SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR (BIT(6)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_S 6 +/** SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR (BIT(7)) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_S 7 +/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR (BIT(8)) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S 8 +/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR (BIT(9)) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_M (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S) +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V 0x00000001U +#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S 9 +/** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR (BIT(10)) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S 10 +/** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR (BIT(11)) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S 11 +/** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR (BIT(12)) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S 12 +/** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR (BIT(13)) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S 13 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR (BIT(14)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S 14 +/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR (BIT(15)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S 15 +/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_START_ST_CLR (BIT(16)) +#define SOC_ETM_RTC_TASK_START_ST_CLR_M (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S) +#define SOC_ETM_RTC_TASK_START_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_CLR_S 16 +/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_STOP_ST_CLR (BIT(17)) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S 17 +/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_CLR_ST_CLR (BIT(18)) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S 18 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR (BIT(19)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S 19 +/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR (BIT(20)) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_M (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S) +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V 0x00000001U +#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S 20 + +/** SOC_ETM_CLK_EN_REG register + * ETM clock enable register + */ +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1f8) +/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define SOC_ETM_CLK_EN (BIT(0)) +#define SOC_ETM_CLK_EN_M (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S) +#define SOC_ETM_CLK_EN_V 0x00000001U +#define SOC_ETM_CLK_EN_S 0 + +/** SOC_ETM_DATE_REG register + * ETM date register + */ +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1fc) +/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36716929; + * Configures the version. + */ +#define SOC_ETM_DATE 0x0FFFFFFFU +#define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) +#define SOC_ETM_DATE_V 0x0FFFFFFFU +#define SOC_ETM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/soc_etm_struct.h b/components/soc/esp32c5/include/soc/soc_etm_struct.h new file mode 100644 index 0000000000..3d46175e49 --- /dev/null +++ b/components/soc/esp32c5/include/soc/soc_etm_struct.h @@ -0,0 +1,5116 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status register */ +/** Type of ch_ena_ad0 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_enabled0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled0:1; + /** ch_enabled1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled1:1; + /** ch_enabled2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled2:1; + /** ch_enabled3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled3:1; + /** ch_enabled4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled4:1; + /** ch_enabled5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled5:1; + /** ch_enabled6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled6:1; + /** ch_enabled7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled7:1; + /** ch_enabled8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled8:1; + /** ch_enabled9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled9:1; + /** ch_enabled10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled10:1; + /** ch_enabled11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled11:1; + /** ch_enabled12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled12:1; + /** ch_enabled13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled13:1; + /** ch_enabled14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled14:1; + /** ch_enabled15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled15:1; + /** ch_enabled16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled16:1; + /** ch_enabled17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled17:1; + /** ch_enabled18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled18:1; + /** ch_enabled19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled19:1; + /** ch_enabled20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled20:1; + /** ch_enabled21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled21:1; + /** ch_enabled22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled22:1; + /** ch_enabled23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled23:1; + /** ch_enabled24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled24:1; + /** ch_enabled25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled25:1; + /** ch_enabled26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled26:1; + /** ch_enabled27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled27:1; + /** ch_enabled28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled28:1; + /** ch_enabled29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled29:1; + /** ch_enabled30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled30:1; + /** ch_enabled31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_reg_t; + +/** Type of ch_ena_ad1 register + * Channel enable status register + */ +typedef union { + struct { + /** ch_enabled32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled32:1; + /** ch_enabled33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled33:1; + /** ch_enabled34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled34:1; + /** ch_enabled35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled35:1; + /** ch_enabled36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled36:1; + /** ch_enabled37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled37:1; + /** ch_enabled38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled38:1; + /** ch_enabled39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled39:1; + /** ch_enabled40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled40:1; + /** ch_enabled41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled41:1; + /** ch_enabled42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled42:1; + /** ch_enabled43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled43:1; + /** ch_enabled44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled44:1; + /** ch_enabled45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled45:1; + /** ch_enabled46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled46:1; + /** ch_enabled47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled47:1; + /** ch_enabled48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled48:1; + /** ch_enabled49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status.\\0: Disable\\1: Enable + */ + uint32_t ch_enabled49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_reg_t; + +/** Type of evt_st0 register + * Events trigger status register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_rise_edge_st:1; + /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_rise_edge_st:1; + /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_rise_edge_st:1; + /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_rise_edge_st:1; + /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_rise_edge_st:1; + /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_rise_edge_st:1; + /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_rise_edge_st:1; + /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_rise_edge_st:1; + /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_fall_edge_st:1; + /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_fall_edge_st:1; + /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_fall_edge_st:1; + /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_fall_edge_st:1; + /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_fall_edge_st:1; + /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_fall_edge_st:1; + /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_fall_edge_st:1; + /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_fall_edge_st:1; + /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch0_any_edge_st:1; + /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch1_any_edge_st:1; + /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch2_any_edge_st:1; + /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch3_any_edge_st:1; + /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch4_any_edge_st:1; + /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch5_any_edge_st:1; + /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch6_any_edge_st:1; + /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_ch7_any_edge_st:1; + /** gpio_evt_zero_det_pos_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GPIO_evt_zero_det_pos trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_pos_st:1; + /** gpio_evt_zero_det_neg_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GPIO_evt_zero_det_neg trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_evt_zero_det_neg_st:1; + /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch0_st:1; + /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch1_st:1; + /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch2_st:1; + /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch3_st:1; + /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch4_st:1; + /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_evt_duty_chng_end_ch5_st:1; + }; + uint32_t val; +} soc_etm_evt_st0_reg_t; + +/** Type of evt_st1 register + * Events trigger status register + */ +typedef union { + struct { + /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1; + /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1; + /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1; + /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1; + /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1; + /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1; + /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer0_st:1; + /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer1_st:1; + /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer2_st:1; + /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_time_ovf_timer3_st:1; + /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer0_cmp_st:1; + /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer1_cmp_st:1; + /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer2_cmp_st:1; + /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_evt_timer3_cmp_st:1; + /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer0_st:1; + /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_evt_cnt_cmp_timer1_st:1; + /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer0_st:1; + /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_evt_cnt_cmp_timer1_st:1; + /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp0_st:1; + /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp1_st:1; + /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t systimer_evt_cnt_cmp2_st:1; + /** mcpwm0_evt_timer0_stop_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_stop_st:1; + /** mcpwm0_evt_timer1_stop_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_stop_st:1; + /** mcpwm0_evt_timer2_stop_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_stop_st:1; + /** mcpwm0_evt_timer0_tez_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_tez_st:1; + /** mcpwm0_evt_timer1_tez_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_tez_st:1; + /** mcpwm0_evt_timer2_tez_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_tez_st:1; + /** mcpwm0_evt_timer0_tep_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer0_tep_st:1; + /** mcpwm0_evt_timer1_tep_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer1_tep_st:1; + /** mcpwm0_evt_timer2_tep_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_timer2_tep_st:1; + /** mcpwm0_evt_op0_tea_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tea_st:1; + /** mcpwm0_evt_op1_tea_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tea_st:1; + }; + uint32_t val; +} soc_etm_evt_st1_reg_t; + +/** Type of evt_st2 register + * Events trigger status register + */ +typedef union { + struct { + /** mcpwm0_evt_op2_tea_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tea_st:1; + /** mcpwm0_evt_op0_teb_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_teb_st:1; + /** mcpwm0_evt_op1_teb_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_teb_st:1; + /** mcpwm0_evt_op2_teb_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_teb_st:1; + /** mcpwm0_evt_f0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f0_st:1; + /** mcpwm0_evt_f1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f1_st:1; + /** mcpwm0_evt_f2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f2_st:1; + /** mcpwm0_evt_f0_clr_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f0_clr_st:1; + /** mcpwm0_evt_f1_clr_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f1_clr_st:1; + /** mcpwm0_evt_f2_clr_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_f2_clr_st:1; + /** mcpwm0_evt_tz0_cbc_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz0_cbc_st:1; + /** mcpwm0_evt_tz1_cbc_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz1_cbc_st:1; + /** mcpwm0_evt_tz2_cbc_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz2_cbc_st:1; + /** mcpwm0_evt_tz0_ost_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz0_ost_st:1; + /** mcpwm0_evt_tz1_ost_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz1_ost_st:1; + /** mcpwm0_evt_tz2_ost_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_tz2_ost_st:1; + /** mcpwm0_evt_cap0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap0_st:1; + /** mcpwm0_evt_cap1_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap1_st:1; + /** mcpwm0_evt_cap2_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_cap2_st:1; + /** mcpwm0_evt_op0_tee1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tee1_st:1; + /** mcpwm0_evt_op1_tee1_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tee1_st:1; + /** mcpwm0_evt_op2_tee1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tee1_st:1; + /** mcpwm0_evt_op0_tee2_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op0_tee2_st:1; + /** mcpwm0_evt_op1_tee2_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op1_tee2_st:1; + /** mcpwm0_evt_op2_tee2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_evt_op2_tee2_st:1; + /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_conv_cmplt0_st:1; + /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh0_st:1; + /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_above_thresh1_st:1; + /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh0_st:1; + /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_eq_below_thresh1_st:1; + /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_result_done0_st:1; + /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_stopped0_st:1; + }; + uint32_t val; +} soc_etm_evt_st2_reg_t; + +/** Type of evt_st3 register + * Events trigger status register + */ +typedef union { + struct { + /** adc_evt_started0_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_evt_started0_st:1; + /** regdma_evt_done0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done0_st:1; + /** regdma_evt_done1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done1_st:1; + /** regdma_evt_done2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done2_st:1; + /** regdma_evt_done3_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_done3_st:1; + /** regdma_evt_err0_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err0_st:1; + /** regdma_evt_err1_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err1_st:1; + /** regdma_evt_err2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err2_st:1; + /** regdma_evt_err3_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_evt_err3_st:1; + /** gdma_evt_in_done_ch0_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GDMA_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_done_ch0_st:1; + /** gdma_evt_in_done_ch1_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_done_ch1_st:1; + /** gdma_evt_in_done_ch2_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GDMA_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_done_ch2_st:1; + /** gdma_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_suc_eof_ch0_st:1; + /** gdma_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_suc_eof_ch1_st:1; + /** gdma_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GDMA_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_suc_eof_ch2_st:1; + /** gdma_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_in_fifo_empty_ch0_st:1; + /** gdma_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_in_fifo_empty_ch1_st:1; + /** gdma_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_in_fifo_empty_ch2_st:1; + /** gdma_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_fifo_full_ch0_st:1; + /** gdma_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_fifo_full_ch1_st:1; + /** gdma_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GDMA_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_in_fifo_full_ch2_st:1; + /** gdma_evt_out_done_ch0_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GDMA_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_done_ch0_st:1; + /** gdma_evt_out_done_ch1_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GDMA_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_done_ch1_st:1; + /** gdma_evt_out_done_ch2_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GDMA_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_done_ch2_st:1; + /** gdma_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_eof_ch0_st:1; + /** gdma_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents GDMA_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_eof_ch1_st:1; + /** gdma_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GDMA_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_evt_out_eof_ch2_st:1; + /** gdma_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_total_eof_ch0_st:1; + /** gdma_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents GDMA_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_total_eof_ch1_st:1; + /** gdma_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents GDMA_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_total_eof_ch2_st:1; + /** gdma_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_empty_ch0_st:1; + /** gdma_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_empty_ch1_st:1; + }; + uint32_t val; +} soc_etm_evt_st3_reg_t; + +/** Type of evt_st4 register + * Events trigger status register + */ +typedef union { + struct { + /** gdma_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_empty_ch2_st:1; + /** gdma_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_full_ch0_st:1; + /** gdma_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_full_ch1_st:1; + /** gdma_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t gdma_evt_out_fifo_full_ch2_st:1; + /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_evt_over_limit_st:1; + /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_rx_done_st:1; + /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_tx_done_st:1; + /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_received_st:1; + /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_evt_x_words_sent_st:1; + /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_err_intr_st:1; + /** ulp_evt_halt_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_halt_st:1; + /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_evt_start_intr_st:1; + /** rtc_evt_tick_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_tick_st:1; + /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_ovf_st:1; + /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_evt_cmp_st:1; + /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_evt_sleep_weekup_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} soc_etm_evt_st4_reg_t; + +/** Type of task_st0 register + * Tasks trigger status register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_set_st:1; + /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_set_st:1; + /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_set_st:1; + /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_set_st:1; + /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_set_st:1; + /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_set_st:1; + /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_set_st:1; + /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_set_st:1; + /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_clear_st:1; + /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_clear_st:1; + /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_clear_st:1; + /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_clear_st:1; + /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_clear_st:1; + /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_clear_st:1; + /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_clear_st:1; + /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_clear_st:1; + /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch0_toggle_st:1; + /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch1_toggle_st:1; + /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch2_toggle_st:1; + /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch3_toggle_st:1; + /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch4_toggle_st:1; + /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch5_toggle_st:1; + /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch6_toggle_st:1; + /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gpio_task_ch7_toggle_st:1; + /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer0_res_update_st:1; + /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer1_res_update_st:1; + /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer2_res_update_st:1; + /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_timer3_res_update_st:1; + /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch0_st:1; + /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch1_st:1; + /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch2_st:1; + /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch3_st:1; + }; + uint32_t val; +} soc_etm_task_st0_reg_t; + +/** Type of task_st1 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch4_st:1; + /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_duty_scale_update_ch5_st:1; + /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_cap_st:1; + /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_cap_st:1; + /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_cap_st:1; + /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_cap_st:1; + /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch0_st:1; + /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch1_st:1; + /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch2_st:1; + /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch3_st:1; + /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch4_st:1; + /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_sig_out_dis_ch5_st:1; + /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st:1; + /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st:1; + /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st:1; + /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st:1; + /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st:1; + /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st:1; + /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_rst_st:1; + /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_rst_st:1; + /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_rst_st:1; + /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_rst_st:1; + /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_resume_st:1; + /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_resume_st:1; + /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_resume_st:1; + /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_resume_st:1; + /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer0_pause_st:1; + /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer1_pause_st:1; + /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer2_pause_st:1; + /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_timer3_pause_st:1; + /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch0_st:1; + /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch1_st:1; + }; + uint32_t val; +} soc_etm_task_st1_reg_t; + +/** Type of task_st2 register + * Tasks trigger status register + */ +typedef union { + struct { + /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch2_st:1; + /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch3_st:1; + /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch4_st:1; + /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_restart_ch5_st:1; + /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch0_st:1; + /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch1_st:1; + /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch2_st:1; + /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch3_st:1; + /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch4_st:1; + /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ledc_task_gamma_pause_ch5_st:1; + /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch0_st:1; + /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch1_st:1; + /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch2_st:1; + /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch3_st:1; + /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch4_st:1; + /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t ledc_task_gamma_resume_ch5_st:1; + /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer0_st:1; + /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer0_st:1; + /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer0_st:1; + /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer0_st:1; + /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer0_st:1; + /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_start_timer1_st:1; + /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_alarm_start_timer1_st:1; + /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_stop_timer1_st:1; + /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg0_task_cnt_reload_timer1_st:1; + /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg0_task_cnt_cap_timer1_st:1; + /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer0_st:1; + /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer0_st:1; + /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer0_st:1; + /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer0_st:1; + /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer0_st:1; + /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_start_timer1_st:1; + }; + uint32_t val; +} soc_etm_task_st2_reg_t; + +/** Type of task_st3 register + * Tasks trigger status register + */ +typedef union { + struct { + /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_alarm_start_timer1_st:1; + /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_stop_timer1_st:1; + /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t tg1_task_cnt_reload_timer1_st:1; + /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tg1_task_cnt_cap_timer1_st:1; + /** mcpwm0_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr0_a_up_st:1; + /** mcpwm0_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr1_a_up_st:1; + /** mcpwm0_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr2_a_up_st:1; + /** mcpwm0_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr0_b_up_st:1; + /** mcpwm0_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr1_b_up_st:1; + /** mcpwm0_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cmpr2_b_up_st:1; + /** mcpwm0_task_gen_stop_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_gen_stop_st:1; + /** mcpwm0_task_timer0_syn_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer0_syn_st:1; + /** mcpwm0_task_timer1_syn_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer1_syn_st:1; + /** mcpwm0_task_timer2_syn_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_timer2_syn_st:1; + /** mcpwm0_task_timer0_period_up_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer0_period_up_st:1; + /** mcpwm0_task_timer1_period_up_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer1_period_up_st:1; + /** mcpwm0_task_timer2_period_up_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: + * Triggered + */ + uint32_t mcpwm0_task_timer2_period_up_st:1; + /** mcpwm0_task_tz0_ost_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz0_ost_st:1; + /** mcpwm0_task_tz1_ost_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz1_ost_st:1; + /** mcpwm0_task_tz2_ost_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_tz2_ost_st:1; + /** mcpwm0_task_clr0_ost_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr0_ost_st:1; + /** mcpwm0_task_clr1_ost_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr1_ost_st:1; + /** mcpwm0_task_clr2_ost_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_clr2_ost_st:1; + /** mcpwm0_task_cap0_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap0_st:1; + /** mcpwm0_task_cap1_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap1_st:1; + /** mcpwm0_task_cap2_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t mcpwm0_task_cap2_st:1; + /** adc_task_sample0_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample0_st:1; + /** adc_task_sample1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_sample1_st:1; + /** adc_task_start0_st : R/WTC/SS; bitpos: [28]; default: 0; + * Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_start0_st:1; + /** adc_task_stop0_st : R/WTC/SS; bitpos: [29]; default: 0; + * Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t adc_task_stop0_st:1; + /** regdma_task_start0_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start0_st:1; + /** regdma_task_start1_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start1_st:1; + }; + uint32_t val; +} soc_etm_task_st3_reg_t; + +/** Type of task_st4 register + * Tasks trigger status register + */ +typedef union { + struct { + /** regdma_task_start2_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start2_st:1; + /** regdma_task_start3_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t regdma_task_start3_st:1; + /** gdma_task_in_start_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents GDMA_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_in_start_ch0_st:1; + /** gdma_task_in_start_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents GDMA_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_in_start_ch1_st:1; + /** gdma_task_in_start_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_in_start_ch2_st:1; + /** gdma_task_out_start_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents GDMA_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_out_start_ch0_st:1; + /** gdma_task_out_start_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents GDMA_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_out_start_ch1_st:1; + /** gdma_task_out_start_ch2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t gdma_task_out_start_ch2_st:1; + /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_start_sample_st:1; + /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t tmpsnsr_task_stop_sample_st:1; + /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_rx_st:1; + /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_start_tx_st:1; + /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_rx_st:1; + /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t i2s0_task_stop_tx_st:1; + /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_wakeup_cpu_st:1; + /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t ulp_task_int_cpu_st:1; + /** rtc_task_start_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_start_st:1; + /** rtc_task_stop_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_stop_st:1; + /** rtc_task_clr_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_clr_st:1; + /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t rtc_task_triggerflw_st:1; + /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + */ + uint32_t pmu_task_sleep_req_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} soc_etm_task_st4_reg_t; + + +/** Group: Configuration Register */ +/** Type of ch_ena_ad0_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_enable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable0:1; + /** ch_enable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable1:1; + /** ch_enable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable2:1; + /** ch_enable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable3:1; + /** ch_enable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable4:1; + /** ch_enable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable5:1; + /** ch_enable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable6:1; + /** ch_enable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable7:1; + /** ch_enable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable8:1; + /** ch_enable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable9:1; + /** ch_enable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable10:1; + /** ch_enable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable11:1; + /** ch_enable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable12:1; + /** ch_enable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable13:1; + /** ch_enable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable14:1; + /** ch_enable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable15:1; + /** ch_enable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable16:1; + /** ch_enable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable17:1; + /** ch_enable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable18:1; + /** ch_enable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable19:1; + /** ch_enable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable20:1; + /** ch_enable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable21:1; + /** ch_enable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable22:1; + /** ch_enable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable23:1; + /** ch_enable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable24:1; + /** ch_enable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable25:1; + /** ch_enable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable26:1; + /** ch_enable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable27:1; + /** ch_enable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable28:1; + /** ch_enable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable29:1; + /** ch_enable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable30:1; + /** ch_enable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_set_reg_t; + +/** Type of ch_ena_ad0_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_disable0 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable0:1; + /** ch_disable1 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable1:1; + /** ch_disable2 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable2:1; + /** ch_disable3 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable3:1; + /** ch_disable4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable4:1; + /** ch_disable5 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable5:1; + /** ch_disable6 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable6:1; + /** ch_disable7 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable7:1; + /** ch_disable8 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable8:1; + /** ch_disable9 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable9:1; + /** ch_disable10 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable10:1; + /** ch_disable11 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable11:1; + /** ch_disable12 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable12:1; + /** ch_disable13 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable13:1; + /** ch_disable14 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable14:1; + /** ch_disable15 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable15:1; + /** ch_disable16 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable16:1; + /** ch_disable17 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable17:1; + /** ch_disable18 : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable18:1; + /** ch_disable19 : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable19:1; + /** ch_disable20 : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable20:1; + /** ch_disable21 : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable21:1; + /** ch_disable22 : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable22:1; + /** ch_disable23 : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable23:1; + /** ch_disable24 : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable24:1; + /** ch_disable25 : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable25:1; + /** ch_disable26 : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable26:1; + /** ch_disable27 : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable27:1; + /** ch_disable28 : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable28:1; + /** ch_disable29 : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable29:1; + /** ch_disable30 : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable30:1; + /** ch_disable31 : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable31:1; + }; + uint32_t val; +} soc_etm_ch_ena_ad0_clr_reg_t; + +/** Type of ch_ena_ad1_set register + * Channel enable set register + */ +typedef union { + struct { + /** ch_enable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable32:1; + /** ch_enable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable33:1; + /** ch_enable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable34:1; + /** ch_enable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable35:1; + /** ch_enable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable36:1; + /** ch_enable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable37:1; + /** ch_enable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable38:1; + /** ch_enable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable39:1; + /** ch_enable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable40:1; + /** ch_enable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable41:1; + /** ch_enable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable42:1; + /** ch_enable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable43:1; + /** ch_enable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable44:1; + /** ch_enable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable45:1; + /** ch_enable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable46:1; + /** ch_enable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable47:1; + /** ch_enable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable48:1; + /** ch_enable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + */ + uint32_t ch_enable49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_set_reg_t; + +/** Type of ch_ena_ad1_clr register + * Channel enable clear register + */ +typedef union { + struct { + /** ch_disable32 : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable32:1; + /** ch_disable33 : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable33:1; + /** ch_disable34 : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable34:1; + /** ch_disable35 : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable35:1; + /** ch_disable36 : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable36:1; + /** ch_disable37 : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable37:1; + /** ch_disable38 : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable38:1; + /** ch_disable39 : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable39:1; + /** ch_disable40 : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable40:1; + /** ch_disable41 : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable41:1; + /** ch_disable42 : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable42:1; + /** ch_disable43 : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable43:1; + /** ch_disable44 : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable44:1; + /** ch_disable45 : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable45:1; + /** ch_disable46 : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable46:1; + /** ch_disable47 : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable47:1; + /** ch_disable48 : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable48:1; + /** ch_disable49 : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ch_disable49:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} soc_etm_ch_ena_ad1_clr_reg_t; + +/** Type of ch0_evt_id register + * Channel0 event id register + */ +typedef union { + struct { + /** ch0_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_evt_id + */ + uint32_t ch0_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch0_evt_id_reg_t; + +/** Type of ch0_task_id register + * Channel0 task id register + */ +typedef union { + struct { + /** ch0_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch0_task_id + */ + uint32_t ch0_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch0_task_id_reg_t; + +/** Type of ch1_evt_id register + * Channel1 event id register + */ +typedef union { + struct { + /** ch1_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_evt_id + */ + uint32_t ch1_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch1_evt_id_reg_t; + +/** Type of ch1_task_id register + * Channel1 task id register + */ +typedef union { + struct { + /** ch1_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch1_task_id + */ + uint32_t ch1_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch1_task_id_reg_t; + +/** Type of ch2_evt_id register + * Channel2 event id register + */ +typedef union { + struct { + /** ch2_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_evt_id + */ + uint32_t ch2_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch2_evt_id_reg_t; + +/** Type of ch2_task_id register + * Channel2 task id register + */ +typedef union { + struct { + /** ch2_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch2_task_id + */ + uint32_t ch2_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch2_task_id_reg_t; + +/** Type of ch3_evt_id register + * Channel3 event id register + */ +typedef union { + struct { + /** ch3_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_evt_id + */ + uint32_t ch3_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch3_evt_id_reg_t; + +/** Type of ch3_task_id register + * Channel3 task id register + */ +typedef union { + struct { + /** ch3_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch3_task_id + */ + uint32_t ch3_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch3_task_id_reg_t; + +/** Type of ch4_evt_id register + * Channel4 event id register + */ +typedef union { + struct { + /** ch4_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_evt_id + */ + uint32_t ch4_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch4_evt_id_reg_t; + +/** Type of ch4_task_id register + * Channel4 task id register + */ +typedef union { + struct { + /** ch4_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch4_task_id + */ + uint32_t ch4_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch4_task_id_reg_t; + +/** Type of ch5_evt_id register + * Channel5 event id register + */ +typedef union { + struct { + /** ch5_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_evt_id + */ + uint32_t ch5_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch5_evt_id_reg_t; + +/** Type of ch5_task_id register + * Channel5 task id register + */ +typedef union { + struct { + /** ch5_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch5_task_id + */ + uint32_t ch5_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch5_task_id_reg_t; + +/** Type of ch6_evt_id register + * Channel6 event id register + */ +typedef union { + struct { + /** ch6_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_evt_id + */ + uint32_t ch6_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch6_evt_id_reg_t; + +/** Type of ch6_task_id register + * Channel6 task id register + */ +typedef union { + struct { + /** ch6_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch6_task_id + */ + uint32_t ch6_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch6_task_id_reg_t; + +/** Type of ch7_evt_id register + * Channel7 event id register + */ +typedef union { + struct { + /** ch7_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_evt_id + */ + uint32_t ch7_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch7_evt_id_reg_t; + +/** Type of ch7_task_id register + * Channel7 task id register + */ +typedef union { + struct { + /** ch7_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch7_task_id + */ + uint32_t ch7_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch7_task_id_reg_t; + +/** Type of ch8_evt_id register + * Channel8 event id register + */ +typedef union { + struct { + /** ch8_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_evt_id + */ + uint32_t ch8_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch8_evt_id_reg_t; + +/** Type of ch8_task_id register + * Channel8 task id register + */ +typedef union { + struct { + /** ch8_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch8_task_id + */ + uint32_t ch8_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch8_task_id_reg_t; + +/** Type of ch9_evt_id register + * Channel9 event id register + */ +typedef union { + struct { + /** ch9_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_evt_id + */ + uint32_t ch9_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch9_evt_id_reg_t; + +/** Type of ch9_task_id register + * Channel9 task id register + */ +typedef union { + struct { + /** ch9_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch9_task_id + */ + uint32_t ch9_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch9_task_id_reg_t; + +/** Type of ch10_evt_id register + * Channel10 event id register + */ +typedef union { + struct { + /** ch10_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_evt_id + */ + uint32_t ch10_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch10_evt_id_reg_t; + +/** Type of ch10_task_id register + * Channel10 task id register + */ +typedef union { + struct { + /** ch10_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch10_task_id + */ + uint32_t ch10_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch10_task_id_reg_t; + +/** Type of ch11_evt_id register + * Channel11 event id register + */ +typedef union { + struct { + /** ch11_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_evt_id + */ + uint32_t ch11_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch11_evt_id_reg_t; + +/** Type of ch11_task_id register + * Channel11 task id register + */ +typedef union { + struct { + /** ch11_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch11_task_id + */ + uint32_t ch11_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch11_task_id_reg_t; + +/** Type of ch12_evt_id register + * Channel12 event id register + */ +typedef union { + struct { + /** ch12_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_evt_id + */ + uint32_t ch12_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch12_evt_id_reg_t; + +/** Type of ch12_task_id register + * Channel12 task id register + */ +typedef union { + struct { + /** ch12_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch12_task_id + */ + uint32_t ch12_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch12_task_id_reg_t; + +/** Type of ch13_evt_id register + * Channel13 event id register + */ +typedef union { + struct { + /** ch13_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_evt_id + */ + uint32_t ch13_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch13_evt_id_reg_t; + +/** Type of ch13_task_id register + * Channel13 task id register + */ +typedef union { + struct { + /** ch13_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch13_task_id + */ + uint32_t ch13_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch13_task_id_reg_t; + +/** Type of ch14_evt_id register + * Channel14 event id register + */ +typedef union { + struct { + /** ch14_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_evt_id + */ + uint32_t ch14_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch14_evt_id_reg_t; + +/** Type of ch14_task_id register + * Channel14 task id register + */ +typedef union { + struct { + /** ch14_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch14_task_id + */ + uint32_t ch14_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch14_task_id_reg_t; + +/** Type of ch15_evt_id register + * Channel15 event id register + */ +typedef union { + struct { + /** ch15_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_evt_id + */ + uint32_t ch15_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch15_evt_id_reg_t; + +/** Type of ch15_task_id register + * Channel15 task id register + */ +typedef union { + struct { + /** ch15_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch15_task_id + */ + uint32_t ch15_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch15_task_id_reg_t; + +/** Type of ch16_evt_id register + * Channel16 event id register + */ +typedef union { + struct { + /** ch16_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_evt_id + */ + uint32_t ch16_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch16_evt_id_reg_t; + +/** Type of ch16_task_id register + * Channel16 task id register + */ +typedef union { + struct { + /** ch16_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch16_task_id + */ + uint32_t ch16_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch16_task_id_reg_t; + +/** Type of ch17_evt_id register + * Channel17 event id register + */ +typedef union { + struct { + /** ch17_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_evt_id + */ + uint32_t ch17_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch17_evt_id_reg_t; + +/** Type of ch17_task_id register + * Channel17 task id register + */ +typedef union { + struct { + /** ch17_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch17_task_id + */ + uint32_t ch17_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch17_task_id_reg_t; + +/** Type of ch18_evt_id register + * Channel18 event id register + */ +typedef union { + struct { + /** ch18_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_evt_id + */ + uint32_t ch18_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch18_evt_id_reg_t; + +/** Type of ch18_task_id register + * Channel18 task id register + */ +typedef union { + struct { + /** ch18_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch18_task_id + */ + uint32_t ch18_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch18_task_id_reg_t; + +/** Type of ch19_evt_id register + * Channel19 event id register + */ +typedef union { + struct { + /** ch19_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_evt_id + */ + uint32_t ch19_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch19_evt_id_reg_t; + +/** Type of ch19_task_id register + * Channel19 task id register + */ +typedef union { + struct { + /** ch19_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch19_task_id + */ + uint32_t ch19_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch19_task_id_reg_t; + +/** Type of ch20_evt_id register + * Channel20 event id register + */ +typedef union { + struct { + /** ch20_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_evt_id + */ + uint32_t ch20_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch20_evt_id_reg_t; + +/** Type of ch20_task_id register + * Channel20 task id register + */ +typedef union { + struct { + /** ch20_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch20_task_id + */ + uint32_t ch20_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch20_task_id_reg_t; + +/** Type of ch21_evt_id register + * Channel21 event id register + */ +typedef union { + struct { + /** ch21_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_evt_id + */ + uint32_t ch21_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch21_evt_id_reg_t; + +/** Type of ch21_task_id register + * Channel21 task id register + */ +typedef union { + struct { + /** ch21_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch21_task_id + */ + uint32_t ch21_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch21_task_id_reg_t; + +/** Type of ch22_evt_id register + * Channel22 event id register + */ +typedef union { + struct { + /** ch22_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_evt_id + */ + uint32_t ch22_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch22_evt_id_reg_t; + +/** Type of ch22_task_id register + * Channel22 task id register + */ +typedef union { + struct { + /** ch22_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch22_task_id + */ + uint32_t ch22_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch22_task_id_reg_t; + +/** Type of ch23_evt_id register + * Channel23 event id register + */ +typedef union { + struct { + /** ch23_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_evt_id + */ + uint32_t ch23_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch23_evt_id_reg_t; + +/** Type of ch23_task_id register + * Channel23 task id register + */ +typedef union { + struct { + /** ch23_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch23_task_id + */ + uint32_t ch23_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch23_task_id_reg_t; + +/** Type of ch24_evt_id register + * Channel24 event id register + */ +typedef union { + struct { + /** ch24_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_evt_id + */ + uint32_t ch24_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch24_evt_id_reg_t; + +/** Type of ch24_task_id register + * Channel24 task id register + */ +typedef union { + struct { + /** ch24_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch24_task_id + */ + uint32_t ch24_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch24_task_id_reg_t; + +/** Type of ch25_evt_id register + * Channel25 event id register + */ +typedef union { + struct { + /** ch25_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_evt_id + */ + uint32_t ch25_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch25_evt_id_reg_t; + +/** Type of ch25_task_id register + * Channel25 task id register + */ +typedef union { + struct { + /** ch25_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch25_task_id + */ + uint32_t ch25_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch25_task_id_reg_t; + +/** Type of ch26_evt_id register + * Channel26 event id register + */ +typedef union { + struct { + /** ch26_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_evt_id + */ + uint32_t ch26_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch26_evt_id_reg_t; + +/** Type of ch26_task_id register + * Channel26 task id register + */ +typedef union { + struct { + /** ch26_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch26_task_id + */ + uint32_t ch26_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch26_task_id_reg_t; + +/** Type of ch27_evt_id register + * Channel27 event id register + */ +typedef union { + struct { + /** ch27_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_evt_id + */ + uint32_t ch27_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch27_evt_id_reg_t; + +/** Type of ch27_task_id register + * Channel27 task id register + */ +typedef union { + struct { + /** ch27_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch27_task_id + */ + uint32_t ch27_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch27_task_id_reg_t; + +/** Type of ch28_evt_id register + * Channel28 event id register + */ +typedef union { + struct { + /** ch28_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_evt_id + */ + uint32_t ch28_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch28_evt_id_reg_t; + +/** Type of ch28_task_id register + * Channel28 task id register + */ +typedef union { + struct { + /** ch28_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch28_task_id + */ + uint32_t ch28_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch28_task_id_reg_t; + +/** Type of ch29_evt_id register + * Channel29 event id register + */ +typedef union { + struct { + /** ch29_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_evt_id + */ + uint32_t ch29_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch29_evt_id_reg_t; + +/** Type of ch29_task_id register + * Channel29 task id register + */ +typedef union { + struct { + /** ch29_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch29_task_id + */ + uint32_t ch29_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch29_task_id_reg_t; + +/** Type of ch30_evt_id register + * Channel30 event id register + */ +typedef union { + struct { + /** ch30_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_evt_id + */ + uint32_t ch30_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch30_evt_id_reg_t; + +/** Type of ch30_task_id register + * Channel30 task id register + */ +typedef union { + struct { + /** ch30_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch30_task_id + */ + uint32_t ch30_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch30_task_id_reg_t; + +/** Type of ch31_evt_id register + * Channel31 event id register + */ +typedef union { + struct { + /** ch31_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_evt_id + */ + uint32_t ch31_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch31_evt_id_reg_t; + +/** Type of ch31_task_id register + * Channel31 task id register + */ +typedef union { + struct { + /** ch31_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch31_task_id + */ + uint32_t ch31_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch31_task_id_reg_t; + +/** Type of ch32_evt_id register + * Channel32 event id register + */ +typedef union { + struct { + /** ch32_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_evt_id + */ + uint32_t ch32_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch32_evt_id_reg_t; + +/** Type of ch32_task_id register + * Channel32 task id register + */ +typedef union { + struct { + /** ch32_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch32_task_id + */ + uint32_t ch32_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch32_task_id_reg_t; + +/** Type of ch33_evt_id register + * Channel33 event id register + */ +typedef union { + struct { + /** ch33_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_evt_id + */ + uint32_t ch33_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch33_evt_id_reg_t; + +/** Type of ch33_task_id register + * Channel33 task id register + */ +typedef union { + struct { + /** ch33_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch33_task_id + */ + uint32_t ch33_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch33_task_id_reg_t; + +/** Type of ch34_evt_id register + * Channel34 event id register + */ +typedef union { + struct { + /** ch34_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_evt_id + */ + uint32_t ch34_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch34_evt_id_reg_t; + +/** Type of ch34_task_id register + * Channel34 task id register + */ +typedef union { + struct { + /** ch34_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch34_task_id + */ + uint32_t ch34_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch34_task_id_reg_t; + +/** Type of ch35_evt_id register + * Channel35 event id register + */ +typedef union { + struct { + /** ch35_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_evt_id + */ + uint32_t ch35_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch35_evt_id_reg_t; + +/** Type of ch35_task_id register + * Channel35 task id register + */ +typedef union { + struct { + /** ch35_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch35_task_id + */ + uint32_t ch35_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch35_task_id_reg_t; + +/** Type of ch36_evt_id register + * Channel36 event id register + */ +typedef union { + struct { + /** ch36_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_evt_id + */ + uint32_t ch36_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch36_evt_id_reg_t; + +/** Type of ch36_task_id register + * Channel36 task id register + */ +typedef union { + struct { + /** ch36_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch36_task_id + */ + uint32_t ch36_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch36_task_id_reg_t; + +/** Type of ch37_evt_id register + * Channel37 event id register + */ +typedef union { + struct { + /** ch37_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_evt_id + */ + uint32_t ch37_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch37_evt_id_reg_t; + +/** Type of ch37_task_id register + * Channel37 task id register + */ +typedef union { + struct { + /** ch37_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch37_task_id + */ + uint32_t ch37_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch37_task_id_reg_t; + +/** Type of ch38_evt_id register + * Channel38 event id register + */ +typedef union { + struct { + /** ch38_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_evt_id + */ + uint32_t ch38_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch38_evt_id_reg_t; + +/** Type of ch38_task_id register + * Channel38 task id register + */ +typedef union { + struct { + /** ch38_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch38_task_id + */ + uint32_t ch38_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch38_task_id_reg_t; + +/** Type of ch39_evt_id register + * Channel39 event id register + */ +typedef union { + struct { + /** ch39_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_evt_id + */ + uint32_t ch39_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch39_evt_id_reg_t; + +/** Type of ch39_task_id register + * Channel39 task id register + */ +typedef union { + struct { + /** ch39_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch39_task_id + */ + uint32_t ch39_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch39_task_id_reg_t; + +/** Type of ch40_evt_id register + * Channel40 event id register + */ +typedef union { + struct { + /** ch40_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_evt_id + */ + uint32_t ch40_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch40_evt_id_reg_t; + +/** Type of ch40_task_id register + * Channel40 task id register + */ +typedef union { + struct { + /** ch40_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch40_task_id + */ + uint32_t ch40_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch40_task_id_reg_t; + +/** Type of ch41_evt_id register + * Channel41 event id register + */ +typedef union { + struct { + /** ch41_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_evt_id + */ + uint32_t ch41_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch41_evt_id_reg_t; + +/** Type of ch41_task_id register + * Channel41 task id register + */ +typedef union { + struct { + /** ch41_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch41_task_id + */ + uint32_t ch41_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch41_task_id_reg_t; + +/** Type of ch42_evt_id register + * Channel42 event id register + */ +typedef union { + struct { + /** ch42_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_evt_id + */ + uint32_t ch42_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch42_evt_id_reg_t; + +/** Type of ch42_task_id register + * Channel42 task id register + */ +typedef union { + struct { + /** ch42_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch42_task_id + */ + uint32_t ch42_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch42_task_id_reg_t; + +/** Type of ch43_evt_id register + * Channel43 event id register + */ +typedef union { + struct { + /** ch43_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_evt_id + */ + uint32_t ch43_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch43_evt_id_reg_t; + +/** Type of ch43_task_id register + * Channel43 task id register + */ +typedef union { + struct { + /** ch43_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch43_task_id + */ + uint32_t ch43_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch43_task_id_reg_t; + +/** Type of ch44_evt_id register + * Channel44 event id register + */ +typedef union { + struct { + /** ch44_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_evt_id + */ + uint32_t ch44_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch44_evt_id_reg_t; + +/** Type of ch44_task_id register + * Channel44 task id register + */ +typedef union { + struct { + /** ch44_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch44_task_id + */ + uint32_t ch44_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch44_task_id_reg_t; + +/** Type of ch45_evt_id register + * Channel45 event id register + */ +typedef union { + struct { + /** ch45_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_evt_id + */ + uint32_t ch45_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch45_evt_id_reg_t; + +/** Type of ch45_task_id register + * Channel45 task id register + */ +typedef union { + struct { + /** ch45_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch45_task_id + */ + uint32_t ch45_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch45_task_id_reg_t; + +/** Type of ch46_evt_id register + * Channel46 event id register + */ +typedef union { + struct { + /** ch46_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_evt_id + */ + uint32_t ch46_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch46_evt_id_reg_t; + +/** Type of ch46_task_id register + * Channel46 task id register + */ +typedef union { + struct { + /** ch46_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch46_task_id + */ + uint32_t ch46_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch46_task_id_reg_t; + +/** Type of ch47_evt_id register + * Channel47 event id register + */ +typedef union { + struct { + /** ch47_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_evt_id + */ + uint32_t ch47_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch47_evt_id_reg_t; + +/** Type of ch47_task_id register + * Channel47 task id register + */ +typedef union { + struct { + /** ch47_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch47_task_id + */ + uint32_t ch47_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch47_task_id_reg_t; + +/** Type of ch48_evt_id register + * Channel48 event id register + */ +typedef union { + struct { + /** ch48_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_evt_id + */ + uint32_t ch48_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch48_evt_id_reg_t; + +/** Type of ch48_task_id register + * Channel48 task id register + */ +typedef union { + struct { + /** ch48_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch48_task_id + */ + uint32_t ch48_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch48_task_id_reg_t; + +/** Type of ch49_evt_id register + * Channel49 event id register + */ +typedef union { + struct { + /** ch49_evt_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_evt_id + */ + uint32_t ch49_evt_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch49_evt_id_reg_t; + +/** Type of ch49_task_id register + * Channel49 task id register + */ +typedef union { + struct { + /** ch49_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch49_task_id + */ + uint32_t ch49_task_id:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} soc_etm_ch49_task_id_reg_t; + +/** Type of evt_st0_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_rise_edge_st_clr:1; + /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_rise_edge_st_clr:1; + /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_rise_edge_st_clr:1; + /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_rise_edge_st_clr:1; + /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_rise_edge_st_clr:1; + /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_rise_edge_st_clr:1; + /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_rise_edge_st_clr:1; + /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_rise_edge_st_clr:1; + /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_fall_edge_st_clr:1; + /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_fall_edge_st_clr:1; + /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_fall_edge_st_clr:1; + /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_fall_edge_st_clr:1; + /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_fall_edge_st_clr:1; + /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_fall_edge_st_clr:1; + /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_fall_edge_st_clr:1; + /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_fall_edge_st_clr:1; + /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch0_any_edge_st_clr:1; + /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch1_any_edge_st_clr:1; + /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch2_any_edge_st_clr:1; + /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch3_any_edge_st_clr:1; + /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch4_any_edge_st_clr:1; + /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch5_any_edge_st_clr:1; + /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch6_any_edge_st_clr:1; + /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_ch7_any_edge_st_clr:1; + /** gpio_evt_zero_det_pos_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_pos_st_clr:1; + /** gpio_evt_zero_det_neg_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_evt_zero_det_neg_st_clr:1; + /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1; + /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1; + /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1; + /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1; + /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1; + /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st0_clr_reg_t; + +/** Type of evt_st1_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1; + /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1; + /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer0_st_clr:1; + /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer1_st_clr:1; + /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer2_st_clr:1; + /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_evt_time_ovf_timer3_st_clr:1; + /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer0_cmp_st_clr:1; + /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer1_cmp_st_clr:1; + /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer2_cmp_st_clr:1; + /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ledc_evt_timer3_cmp_st_clr:1; + /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1; + /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1; + /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1; + /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1; + /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp0_st_clr:1; + /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp1_st_clr:1; + /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t systimer_evt_cnt_cmp2_st_clr:1; + /** mcpwm0_evt_timer0_stop_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_stop_st_clr:1; + /** mcpwm0_evt_timer1_stop_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_stop_st_clr:1; + /** mcpwm0_evt_timer2_stop_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_stop_st_clr:1; + /** mcpwm0_evt_timer0_tez_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_tez_st_clr:1; + /** mcpwm0_evt_timer1_tez_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_tez_st_clr:1; + /** mcpwm0_evt_timer2_tez_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_tez_st_clr:1; + /** mcpwm0_evt_timer0_tep_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer0_tep_st_clr:1; + /** mcpwm0_evt_timer1_tep_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer1_tep_st_clr:1; + /** mcpwm0_evt_timer2_tep_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_evt_timer2_tep_st_clr:1; + /** mcpwm0_evt_op0_tea_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tea_st_clr:1; + /** mcpwm0_evt_op1_tea_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tea_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st1_clr_reg_t; + +/** Type of evt_st2_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** mcpwm0_evt_op2_tea_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tea_st_clr:1; + /** mcpwm0_evt_op0_teb_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_teb_st_clr:1; + /** mcpwm0_evt_op1_teb_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_teb_st_clr:1; + /** mcpwm0_evt_op2_teb_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_teb_st_clr:1; + /** mcpwm0_evt_f0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f0_st_clr:1; + /** mcpwm0_evt_f1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f1_st_clr:1; + /** mcpwm0_evt_f2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_f2_st_clr:1; + /** mcpwm0_evt_f0_clr_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f0_clr_st_clr:1; + /** mcpwm0_evt_f1_clr_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f1_clr_st_clr:1; + /** mcpwm0_evt_f2_clr_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_f2_clr_st_clr:1; + /** mcpwm0_evt_tz0_cbc_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz0_cbc_st_clr:1; + /** mcpwm0_evt_tz1_cbc_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz1_cbc_st_clr:1; + /** mcpwm0_evt_tz2_cbc_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz2_cbc_st_clr:1; + /** mcpwm0_evt_tz0_ost_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz0_ost_st_clr:1; + /** mcpwm0_evt_tz1_ost_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz1_ost_st_clr:1; + /** mcpwm0_evt_tz2_ost_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_tz2_ost_st_clr:1; + /** mcpwm0_evt_cap0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap0_st_clr:1; + /** mcpwm0_evt_cap1_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap1_st_clr:1; + /** mcpwm0_evt_cap2_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_evt_cap2_st_clr:1; + /** mcpwm0_evt_op0_tee1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tee1_st_clr:1; + /** mcpwm0_evt_op1_tee1_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tee1_st_clr:1; + /** mcpwm0_evt_op2_tee1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tee1_st_clr:1; + /** mcpwm0_evt_op0_tee2_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op0_tee2_st_clr:1; + /** mcpwm0_evt_op1_tee2_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op1_tee2_st_clr:1; + /** mcpwm0_evt_op2_tee2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_evt_op2_tee2_st_clr:1; + /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t adc_evt_conv_cmplt0_st_clr:1; + /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh0_st_clr:1; + /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_above_thresh1_st_clr:1; + /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh0_st_clr:1; + /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_eq_below_thresh1_st_clr:1; + /** adc_evt_result_done0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t adc_evt_result_done0_st_clr:1; + /** adc_evt_stopped0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_stopped0_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st2_clr_reg_t; + +/** Type of evt_st3_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** adc_evt_started0_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_evt_started0_st_clr:1; + /** regdma_evt_done0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done0_st_clr:1; + /** regdma_evt_done1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done1_st_clr:1; + /** regdma_evt_done2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done2_st_clr:1; + /** regdma_evt_done3_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_done3_st_clr:1; + /** regdma_evt_err0_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err0_st_clr:1; + /** regdma_evt_err1_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err1_st_clr:1; + /** regdma_evt_err2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err2_st_clr:1; + /** regdma_evt_err3_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t regdma_evt_err3_st_clr:1; + /** gdma_evt_in_done_ch0_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_done_ch0_st_clr:1; + /** gdma_evt_in_done_ch1_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_done_ch1_st_clr:1; + /** gdma_evt_in_done_ch2_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GDMA_evt_in_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_done_ch2_st_clr:1; + /** gdma_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_suc_eof_ch0_st_clr:1; + /** gdma_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_suc_eof_ch1_st_clr:1; + /** gdma_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GDMA_evt_in_suc_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_suc_eof_ch2_st_clr:1; + /** gdma_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_empty_ch0_st_clr:1; + /** gdma_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_empty_ch1_st_clr:1; + /** gdma_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_empty_ch2_st_clr:1; + /** gdma_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_full_ch0_st_clr:1; + /** gdma_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_full_ch1_st_clr:1; + /** gdma_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GDMA_evt_in_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_in_fifo_full_ch2_st_clr:1; + /** gdma_evt_out_done_ch0_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_done_ch0_st_clr:1; + /** gdma_evt_out_done_ch1_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_done_ch1_st_clr:1; + /** gdma_evt_out_done_ch2_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_done_ch2_st_clr:1; + /** gdma_evt_out_eof_ch0_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_eof_ch0_st_clr:1; + /** gdma_evt_out_eof_ch1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_eof_ch1_st_clr:1; + /** gdma_evt_out_eof_ch2_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_eof_ch2_st_clr:1; + /** gdma_evt_out_total_eof_ch0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_total_eof_ch0_st_clr:1; + /** gdma_evt_out_total_eof_ch1_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_total_eof_ch1_st_clr:1; + /** gdma_evt_out_total_eof_ch2_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_total_eof_ch2_st_clr:1; + /** gdma_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_empty_ch0_st_clr:1; + /** gdma_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_empty_ch1_st_clr:1; + }; + uint32_t val; +} soc_etm_evt_st3_clr_reg_t; + +/** Type of evt_st4_clr register + * Events trigger status clear register + */ +typedef union { + struct { + /** gdma_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_empty_ch2_st_clr:1; + /** gdma_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_full_ch0_st_clr:1; + /** gdma_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_full_ch1_st_clr:1; + /** gdma_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_evt_out_fifo_full_ch2_st_clr:1; + /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_evt_over_limit_st_clr:1; + /** i2s0_evt_rx_done_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_rx_done_st_clr:1; + /** i2s0_evt_tx_done_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t i2s0_evt_tx_done_st_clr:1; + /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_received_st_clr:1; + /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t i2s0_evt_x_words_sent_st_clr:1; + /** ulp_evt_err_intr_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_err_intr_st_clr:1; + /** ulp_evt_halt_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_evt_halt_st_clr:1; + /** ulp_evt_start_intr_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_evt_start_intr_st_clr:1; + /** rtc_evt_tick_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_tick_st_clr:1; + /** rtc_evt_ovf_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_ovf_st_clr:1; + /** rtc_evt_cmp_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_evt_cmp_st_clr:1; + /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t pmu_evt_sleep_weekup_st_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} soc_etm_evt_st4_clr_reg_t; + +/** Type of task_st0_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_set_st_clr:1; + /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_set_st_clr:1; + /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_set_st_clr:1; + /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_set_st_clr:1; + /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_set_st_clr:1; + /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_set_st_clr:1; + /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_set_st_clr:1; + /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_set_st_clr:1; + /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch0_clear_st_clr:1; + /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch1_clear_st_clr:1; + /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch2_clear_st_clr:1; + /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch3_clear_st_clr:1; + /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch4_clear_st_clr:1; + /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch5_clear_st_clr:1; + /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch6_clear_st_clr:1; + /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t gpio_task_ch7_clear_st_clr:1; + /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch0_toggle_st_clr:1; + /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch1_toggle_st_clr:1; + /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch2_toggle_st_clr:1; + /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch3_toggle_st_clr:1; + /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch4_toggle_st_clr:1; + /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch5_toggle_st_clr:1; + /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch6_toggle_st_clr:1; + /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gpio_task_ch7_toggle_st_clr:1; + /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_res_update_st_clr:1; + /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_res_update_st_clr:1; + /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_res_update_st_clr:1; + /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_res_update_st_clr:1; + /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch0_st_clr:1; + /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch1_st_clr:1; + /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch2_st_clr:1; + /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch3_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st0_clr_reg_t; + +/** Type of task_st1_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch4_st_clr:1; + /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger + * status.\\0: Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_duty_scale_update_ch5_st_clr:1; + /** ledc_task_timer0_cap_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_cap_st_clr:1; + /** ledc_task_timer1_cap_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_cap_st_clr:1; + /** ledc_task_timer2_cap_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_cap_st_clr:1; + /** ledc_task_timer3_cap_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_cap_st_clr:1; + /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch0_st_clr:1; + /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch1_st_clr:1; + /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch2_st_clr:1; + /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch3_st_clr:1; + /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch4_st_clr:1; + /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_sig_out_dis_ch5_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1; + /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1; + /** ledc_task_timer0_rst_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_rst_st_clr:1; + /** ledc_task_timer1_rst_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_rst_st_clr:1; + /** ledc_task_timer2_rst_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_rst_st_clr:1; + /** ledc_task_timer3_rst_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_rst_st_clr:1; + /** ledc_task_timer0_resume_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_resume_st_clr:1; + /** ledc_task_timer1_resume_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_resume_st_clr:1; + /** ledc_task_timer2_resume_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_resume_st_clr:1; + /** ledc_task_timer3_resume_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_resume_st_clr:1; + /** ledc_task_timer0_pause_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer0_pause_st_clr:1; + /** ledc_task_timer1_pause_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer1_pause_st_clr:1; + /** ledc_task_timer2_pause_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer2_pause_st_clr:1; + /** ledc_task_timer3_pause_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_timer3_pause_st_clr:1; + /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch0_st_clr:1; + /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st1_clr_reg_t; + +/** Type of task_st2_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch2_st_clr:1; + /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch3_st_clr:1; + /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch4_st_clr:1; + /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_restart_ch5_st_clr:1; + /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch0_st_clr:1; + /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch1_st_clr:1; + /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch2_st_clr:1; + /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch3_st_clr:1; + /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch4_st_clr:1; + /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_pause_ch5_st_clr:1; + /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch0_st_clr:1; + /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch1_st_clr:1; + /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch2_st_clr:1; + /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch3_st_clr:1; + /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch4_st_clr:1; + /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t ledc_task_gamma_resume_ch5_st_clr:1; + /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer0_st_clr:1; + /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer0_st_clr:1; + /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer0_st_clr:1; + /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer0_st_clr:1; + /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer0_st_clr:1; + /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_start_timer1_st_clr:1; + /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_alarm_start_timer1_st_clr:1; + /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_stop_timer1_st_clr:1; + /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_reload_timer1_st_clr:1; + /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg0_task_cnt_cap_timer1_st_clr:1; + /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer0_st_clr:1; + /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer0_st_clr:1; + /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer0_st_clr:1; + /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer0_st_clr:1; + /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer0_st_clr:1; + /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_start_timer1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st2_clr_reg_t; + +/** Type of task_st3_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_alarm_start_timer1_st_clr:1; + /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_stop_timer1_st_clr:1; + /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_reload_timer1_st_clr:1; + /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tg1_task_cnt_cap_timer1_st_clr:1; + /** mcpwm0_task_cmpr0_a_up_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr0_a_up_st_clr:1; + /** mcpwm0_task_cmpr1_a_up_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr1_a_up_st_clr:1; + /** mcpwm0_task_cmpr2_a_up_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr2_a_up_st_clr:1; + /** mcpwm0_task_cmpr0_b_up_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr0_b_up_st_clr:1; + /** mcpwm0_task_cmpr1_b_up_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr1_b_up_st_clr:1; + /** mcpwm0_task_cmpr2_b_up_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_cmpr2_b_up_st_clr:1; + /** mcpwm0_task_gen_stop_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_gen_stop_st_clr:1; + /** mcpwm0_task_timer0_syn_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer0_syn_st_clr:1; + /** mcpwm0_task_timer1_syn_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer1_syn_st_clr:1; + /** mcpwm0_task_timer2_syn_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer2_syn_st_clr:1; + /** mcpwm0_task_timer0_period_up_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer0_period_up_st_clr:1; + /** mcpwm0_task_timer1_period_up_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer1_period_up_st_clr:1; + /** mcpwm0_task_timer2_period_up_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_timer2_period_up_st_clr:1; + /** mcpwm0_task_tz0_ost_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz0_ost_st_clr:1; + /** mcpwm0_task_tz1_ost_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz1_ost_st_clr:1; + /** mcpwm0_task_tz2_ost_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t mcpwm0_task_tz2_ost_st_clr:1; + /** mcpwm0_task_clr0_ost_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr0_ost_st_clr:1; + /** mcpwm0_task_clr1_ost_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr1_ost_st_clr:1; + /** mcpwm0_task_clr2_ost_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t mcpwm0_task_clr2_ost_st_clr:1; + /** mcpwm0_task_cap0_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap0_st_clr:1; + /** mcpwm0_task_cap1_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap1_st_clr:1; + /** mcpwm0_task_cap2_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t mcpwm0_task_cap2_st_clr:1; + /** adc_task_sample0_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample0_st_clr:1; + /** adc_task_sample1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_sample1_st_clr:1; + /** adc_task_start0_st_clr : WT; bitpos: [28]; default: 0; + * Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_start0_st_clr:1; + /** adc_task_stop0_st_clr : WT; bitpos: [29]; default: 0; + * Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t adc_task_stop0_st_clr:1; + /** regdma_task_start0_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start0_st_clr:1; + /** regdma_task_start1_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start1_st_clr:1; + }; + uint32_t val; +} soc_etm_task_st3_clr_reg_t; + +/** Type of task_st4_clr register + * Tasks trigger status clear register + */ +typedef union { + struct { + /** regdma_task_start2_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start2_st_clr:1; + /** regdma_task_start3_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t regdma_task_start3_st_clr:1; + /** gdma_task_in_start_ch0_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_in_start_ch0_st_clr:1; + /** gdma_task_in_start_ch1_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_in_start_ch1_st_clr:1; + /** gdma_task_in_start_ch2_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_task_in_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_in_start_ch2_st_clr:1; + /** gdma_task_out_start_ch0_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch0 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_out_start_ch0_st_clr:1; + /** gdma_task_out_start_ch1_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch1 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_out_start_ch1_st_clr:1; + /** gdma_task_out_start_ch2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_task_out_start_ch2 trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t gdma_task_out_start_ch2_st_clr:1; + /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_start_sample_st_clr:1; + /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: + * Invalid, No effect\\1: Clear + */ + uint32_t tmpsnsr_task_stop_sample_st_clr:1; + /** i2s0_task_start_rx_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_rx_st_clr:1; + /** i2s0_task_start_tx_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_start_tx_st_clr:1; + /** i2s0_task_stop_rx_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_rx_st_clr:1; + /** i2s0_task_stop_tx_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t i2s0_task_stop_tx_st_clr:1; + /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t ulp_task_wakeup_cpu_st_clr:1; + /** ulp_task_int_cpu_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t ulp_task_int_cpu_st_clr:1; + /** rtc_task_start_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_start_st_clr:1; + /** rtc_task_stop_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_stop_st_clr:1; + /** rtc_task_clr_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No + * effect\\1: Clear + */ + uint32_t rtc_task_clr_st_clr:1; + /** rtc_task_triggerflw_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t rtc_task_triggerflw_st_clr:1; + /** pmu_task_sleep_req_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, + * No effect\\1: Clear + */ + uint32_t pmu_task_sleep_req_st_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} soc_etm_task_st4_clr_reg_t; + +/** Type of clk_en register + * ETM clock enable register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} soc_etm_clk_en_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * ETM date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716929; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} soc_etm_date_reg_t; + + +typedef struct { + volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; + volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; + volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; + volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; + volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; + volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; + volatile soc_etm_ch0_evt_id_reg_t ch0_evt_id; + volatile soc_etm_ch0_task_id_reg_t ch0_task_id; + volatile soc_etm_ch1_evt_id_reg_t ch1_evt_id; + volatile soc_etm_ch1_task_id_reg_t ch1_task_id; + volatile soc_etm_ch2_evt_id_reg_t ch2_evt_id; + volatile soc_etm_ch2_task_id_reg_t ch2_task_id; + volatile soc_etm_ch3_evt_id_reg_t ch3_evt_id; + volatile soc_etm_ch3_task_id_reg_t ch3_task_id; + volatile soc_etm_ch4_evt_id_reg_t ch4_evt_id; + volatile soc_etm_ch4_task_id_reg_t ch4_task_id; + volatile soc_etm_ch5_evt_id_reg_t ch5_evt_id; + volatile soc_etm_ch5_task_id_reg_t ch5_task_id; + volatile soc_etm_ch6_evt_id_reg_t ch6_evt_id; + volatile soc_etm_ch6_task_id_reg_t ch6_task_id; + volatile soc_etm_ch7_evt_id_reg_t ch7_evt_id; + volatile soc_etm_ch7_task_id_reg_t ch7_task_id; + volatile soc_etm_ch8_evt_id_reg_t ch8_evt_id; + volatile soc_etm_ch8_task_id_reg_t ch8_task_id; + volatile soc_etm_ch9_evt_id_reg_t ch9_evt_id; + volatile soc_etm_ch9_task_id_reg_t ch9_task_id; + volatile soc_etm_ch10_evt_id_reg_t ch10_evt_id; + volatile soc_etm_ch10_task_id_reg_t ch10_task_id; + volatile soc_etm_ch11_evt_id_reg_t ch11_evt_id; + volatile soc_etm_ch11_task_id_reg_t ch11_task_id; + volatile soc_etm_ch12_evt_id_reg_t ch12_evt_id; + volatile soc_etm_ch12_task_id_reg_t ch12_task_id; + volatile soc_etm_ch13_evt_id_reg_t ch13_evt_id; + volatile soc_etm_ch13_task_id_reg_t ch13_task_id; + volatile soc_etm_ch14_evt_id_reg_t ch14_evt_id; + volatile soc_etm_ch14_task_id_reg_t ch14_task_id; + volatile soc_etm_ch15_evt_id_reg_t ch15_evt_id; + volatile soc_etm_ch15_task_id_reg_t ch15_task_id; + volatile soc_etm_ch16_evt_id_reg_t ch16_evt_id; + volatile soc_etm_ch16_task_id_reg_t ch16_task_id; + volatile soc_etm_ch17_evt_id_reg_t ch17_evt_id; + volatile soc_etm_ch17_task_id_reg_t ch17_task_id; + volatile soc_etm_ch18_evt_id_reg_t ch18_evt_id; + volatile soc_etm_ch18_task_id_reg_t ch18_task_id; + volatile soc_etm_ch19_evt_id_reg_t ch19_evt_id; + volatile soc_etm_ch19_task_id_reg_t ch19_task_id; + volatile soc_etm_ch20_evt_id_reg_t ch20_evt_id; + volatile soc_etm_ch20_task_id_reg_t ch20_task_id; + volatile soc_etm_ch21_evt_id_reg_t ch21_evt_id; + volatile soc_etm_ch21_task_id_reg_t ch21_task_id; + volatile soc_etm_ch22_evt_id_reg_t ch22_evt_id; + volatile soc_etm_ch22_task_id_reg_t ch22_task_id; + volatile soc_etm_ch23_evt_id_reg_t ch23_evt_id; + volatile soc_etm_ch23_task_id_reg_t ch23_task_id; + volatile soc_etm_ch24_evt_id_reg_t ch24_evt_id; + volatile soc_etm_ch24_task_id_reg_t ch24_task_id; + volatile soc_etm_ch25_evt_id_reg_t ch25_evt_id; + volatile soc_etm_ch25_task_id_reg_t ch25_task_id; + volatile soc_etm_ch26_evt_id_reg_t ch26_evt_id; + volatile soc_etm_ch26_task_id_reg_t ch26_task_id; + volatile soc_etm_ch27_evt_id_reg_t ch27_evt_id; + volatile soc_etm_ch27_task_id_reg_t ch27_task_id; + volatile soc_etm_ch28_evt_id_reg_t ch28_evt_id; + volatile soc_etm_ch28_task_id_reg_t ch28_task_id; + volatile soc_etm_ch29_evt_id_reg_t ch29_evt_id; + volatile soc_etm_ch29_task_id_reg_t ch29_task_id; + volatile soc_etm_ch30_evt_id_reg_t ch30_evt_id; + volatile soc_etm_ch30_task_id_reg_t ch30_task_id; + volatile soc_etm_ch31_evt_id_reg_t ch31_evt_id; + volatile soc_etm_ch31_task_id_reg_t ch31_task_id; + volatile soc_etm_ch32_evt_id_reg_t ch32_evt_id; + volatile soc_etm_ch32_task_id_reg_t ch32_task_id; + volatile soc_etm_ch33_evt_id_reg_t ch33_evt_id; + volatile soc_etm_ch33_task_id_reg_t ch33_task_id; + volatile soc_etm_ch34_evt_id_reg_t ch34_evt_id; + volatile soc_etm_ch34_task_id_reg_t ch34_task_id; + volatile soc_etm_ch35_evt_id_reg_t ch35_evt_id; + volatile soc_etm_ch35_task_id_reg_t ch35_task_id; + volatile soc_etm_ch36_evt_id_reg_t ch36_evt_id; + volatile soc_etm_ch36_task_id_reg_t ch36_task_id; + volatile soc_etm_ch37_evt_id_reg_t ch37_evt_id; + volatile soc_etm_ch37_task_id_reg_t ch37_task_id; + volatile soc_etm_ch38_evt_id_reg_t ch38_evt_id; + volatile soc_etm_ch38_task_id_reg_t ch38_task_id; + volatile soc_etm_ch39_evt_id_reg_t ch39_evt_id; + volatile soc_etm_ch39_task_id_reg_t ch39_task_id; + volatile soc_etm_ch40_evt_id_reg_t ch40_evt_id; + volatile soc_etm_ch40_task_id_reg_t ch40_task_id; + volatile soc_etm_ch41_evt_id_reg_t ch41_evt_id; + volatile soc_etm_ch41_task_id_reg_t ch41_task_id; + volatile soc_etm_ch42_evt_id_reg_t ch42_evt_id; + volatile soc_etm_ch42_task_id_reg_t ch42_task_id; + volatile soc_etm_ch43_evt_id_reg_t ch43_evt_id; + volatile soc_etm_ch43_task_id_reg_t ch43_task_id; + volatile soc_etm_ch44_evt_id_reg_t ch44_evt_id; + volatile soc_etm_ch44_task_id_reg_t ch44_task_id; + volatile soc_etm_ch45_evt_id_reg_t ch45_evt_id; + volatile soc_etm_ch45_task_id_reg_t ch45_task_id; + volatile soc_etm_ch46_evt_id_reg_t ch46_evt_id; + volatile soc_etm_ch46_task_id_reg_t ch46_task_id; + volatile soc_etm_ch47_evt_id_reg_t ch47_evt_id; + volatile soc_etm_ch47_task_id_reg_t ch47_task_id; + volatile soc_etm_ch48_evt_id_reg_t ch48_evt_id; + volatile soc_etm_ch48_task_id_reg_t ch48_task_id; + volatile soc_etm_ch49_evt_id_reg_t ch49_evt_id; + volatile soc_etm_ch49_task_id_reg_t ch49_task_id; + volatile soc_etm_evt_st0_reg_t evt_st0; + volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; + volatile soc_etm_evt_st1_reg_t evt_st1; + volatile soc_etm_evt_st1_clr_reg_t evt_st1_clr; + volatile soc_etm_evt_st2_reg_t evt_st2; + volatile soc_etm_evt_st2_clr_reg_t evt_st2_clr; + volatile soc_etm_evt_st3_reg_t evt_st3; + volatile soc_etm_evt_st3_clr_reg_t evt_st3_clr; + volatile soc_etm_evt_st4_reg_t evt_st4; + volatile soc_etm_evt_st4_clr_reg_t evt_st4_clr; + volatile soc_etm_task_st0_reg_t task_st0; + volatile soc_etm_task_st0_clr_reg_t task_st0_clr; + volatile soc_etm_task_st1_reg_t task_st1; + volatile soc_etm_task_st1_clr_reg_t task_st1_clr; + volatile soc_etm_task_st2_reg_t task_st2; + volatile soc_etm_task_st2_clr_reg_t task_st2_clr; + volatile soc_etm_task_st3_reg_t task_st3; + volatile soc_etm_task_st3_clr_reg_t task_st3_clr; + volatile soc_etm_task_st4_reg_t task_st4; + volatile soc_etm_task_st4_clr_reg_t task_st4_clr; + volatile soc_etm_clk_en_reg_t clk_en; + volatile soc_etm_date_reg_t date; +} soc_etm_dev_t; + +extern soc_etm_dev_t SOC_ETM; + +#ifndef __cplusplus +_Static_assert(sizeof(soc_etm_dev_t) == 0x200, "Invalid size of soc_etm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_reg.h b/components/soc/esp32c5/include/soc/spi_reg.h new file mode 100644 index 0000000000..034ea1aa4d --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_reg.h @@ -0,0 +1,2116 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_CMD_REG register + * Command control register + */ +#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0) +/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ +#define SPI_CONF_BITLEN 0x0003FFFFU +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFFU +#define SPI_CONF_BITLEN_S 0 +/** SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001U +#define SPI_UPDATE_S 23 +/** SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001U +#define SPI_USR_S 24 + +/** SPI_ADDR_REG register + * Address value register + */ +#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4) +/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI_USR_ADDR_VALUE_S 0 + +/** SPI_CTRL_REG register + * SPI control register + */ +#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8) +/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001U +#define SPI_DUMMY_OUT_S 3 +/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001U +#define SPI_FADDR_DUAL_S 5 +/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001U +#define SPI_FADDR_QUAD_S 6 +/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001U +#define SPI_FADDR_OCT_S 7 +/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001U +#define SPI_FCMD_DUAL_S 8 +/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001U +#define SPI_FCMD_QUAD_S 9 +/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001U +#define SPI_FCMD_OCT_S 10 +/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001U +#define SPI_FREAD_DUAL_S 14 +/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001U +#define SPI_FREAD_QUAD_S 15 +/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001U +#define SPI_FREAD_OCT_S 16 +/** SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001U +#define SPI_Q_POL_S 18 +/** SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001U +#define SPI_D_POL_S 19 +/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001U +#define SPI_HOLD_POL_S 20 +/** SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001U +#define SPI_WP_POL_S 21 +/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ +#define SPI_RD_BIT_ORDER 0x00000003U +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000003U +#define SPI_RD_BIT_ORDER_S 23 +/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ +#define SPI_WR_BIT_ORDER 0x00000003U +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000003U +#define SPI_WR_BIT_ORDER_S 25 + +/** SPI_CLOCK_REG register + * SPI clock control register + */ +#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc) +/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_L 0x0000003FU +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003FU +#define SPI_CLKCNT_L_S 0 +/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ +#define SPI_CLKCNT_H 0x0000003FU +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003FU +#define SPI_CLKCNT_H_S 6 +/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ +#define SPI_CLKCNT_N 0x0000003FU +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003FU +#define SPI_CLKCNT_N_S 12 +/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ +#define SPI_CLKDIV_PRE 0x0000000FU +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000FU +#define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_CLK_EQU_SYSCLK_S 31 + +/** SPI_USER_REG register + * SPI USER control register + */ +#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10) +/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001U +#define SPI_DOUTDIN_S 0 +/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001U +#define SPI_QPI_MODE_S 3 +/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001U +#define SPI_OPI_MODE_S 4 +/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001U +#define SPI_TSCK_I_EDGE_S 5 +/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001U +#define SPI_CS_HOLD_S 6 +/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001U +#define SPI_CS_SETUP_S 7 +/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001U +#define SPI_RSCK_I_EDGE_S 8 +/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001U +#define SPI_CK_OUT_EDGE_S 9 +/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001U +#define SPI_FWRITE_DUAL_S 12 +/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001U +#define SPI_FWRITE_QUAD_S 13 +/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001U +#define SPI_FWRITE_OCT_S 14 +/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001U +#define SPI_USR_CONF_NXT_S 15 +/** SPI_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001U +#define SPI_SIO_S 17 +/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001U +#define SPI_USR_MISO_HIGHPART_S 24 +/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001U +#define SPI_USR_MOSI_HIGHPART_S 25 +/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_USR_DUMMY_IDLE_S 26 +/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001U +#define SPI_USR_MOSI_S 27 +/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001U +#define SPI_USR_MISO_S 28 +/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001U +#define SPI_USR_DUMMY_S 29 +/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001U +#define SPI_USR_ADDR_S 30 +/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001U +#define SPI_USR_COMMAND_S 31 + +/** SPI_USER1_REG register + * SPI USER control register 1 + */ +#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14) +/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define SPI_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001U +#define SPI_MST_WFULL_ERR_END_EN_S 16 +/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ +#define SPI_CS_SETUP_TIME 0x0000001FU +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001FU +#define SPI_CS_SETUP_TIME_S 17 +/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ +#define SPI_CS_HOLD_TIME 0x0000001FU +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001FU +#define SPI_CS_HOLD_TIME_S 22 +/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_ADDR_BITLEN 0x0000001FU +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001FU +#define SPI_USR_ADDR_BITLEN_S 27 + +/** SPI_USER2_REG register + * SPI USER control register 2 + */ +#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18) +/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ +#define SPI_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_USR_COMMAND_VALUE_S 0 +/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define SPI_MST_REMPTY_ERR_END_EN_S 27 +/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define SPI_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_USR_COMMAND_BITLEN_S 28 + +/** SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c) +/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ +#define SPI_MS_DATA_BITLEN 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFFU +#define SPI_MS_DATA_BITLEN_S 0 + +/** SPI_MISC_REG register + * SPI misc register + */ +#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20) +/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001U +#define SPI_CS0_DIS_S 0 +/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001U +#define SPI_CS1_DIS_S 1 +/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001U +#define SPI_CS2_DIS_S 2 +/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001U +#define SPI_CS3_DIS_S 3 +/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001U +#define SPI_CS4_DIS_S 4 +/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001U +#define SPI_CS5_DIS_S 5 +/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001U +#define SPI_CK_DIS_S 6 +/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ +#define SPI_MASTER_CS_POL 0x0000003FU +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003FU +#define SPI_MASTER_CS_POL_S 7 +/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S) +#define SPI_CLK_DATA_DTR_EN_V 0x00000001U +#define SPI_CLK_DATA_DTR_EN_S 16 +/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S) +#define SPI_DATA_DTR_EN_V 0x00000001U +#define SPI_DATA_DTR_EN_S 17 +/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S) +#define SPI_ADDR_DTR_EN_V 0x00000001U +#define SPI_ADDR_DTR_EN_S 18 +/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S) +#define SPI_CMD_DTR_EN_V 0x00000001U +#define SPI_CMD_DTR_EN_S 19 +/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001U +#define SPI_SLAVE_CS_POL_S 23 +/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001U +#define SPI_DQS_IDLE_EDGE_S 24 +/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001U +#define SPI_CK_IDLE_EDGE_S 29 +/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_CS_KEEP_ACTIVE_S 30 +/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001U +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/** SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24) +/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN0_MODE 0x00000003U +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003U +#define SPI_DIN0_MODE_S 0 +/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN1_MODE 0x00000003U +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003U +#define SPI_DIN1_MODE_S 2 +/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN2_MODE 0x00000003U +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003U +#define SPI_DIN2_MODE_S 4 +/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN3_MODE 0x00000003U +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003U +#define SPI_DIN3_MODE_S 6 +/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN4_MODE 0x00000003U +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000003U +#define SPI_DIN4_MODE_S 8 +/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN5_MODE 0x00000003U +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000003U +#define SPI_DIN5_MODE_S 10 +/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN6_MODE 0x00000003U +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000003U +#define SPI_DIN6_MODE_S 12 +/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define SPI_DIN7_MODE 0x00000003U +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000003U +#define SPI_DIN7_MODE_S 14 +/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001U +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/** SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28) +/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN0_NUM 0x00000003U +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003U +#define SPI_DIN0_NUM_S 0 +/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN1_NUM 0x00000003U +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003U +#define SPI_DIN1_NUM_S 2 +/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN2_NUM 0x00000003U +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003U +#define SPI_DIN2_NUM_S 4 +/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN3_NUM 0x00000003U +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003U +#define SPI_DIN3_NUM_S 6 +/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN4_NUM 0x00000003U +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003U +#define SPI_DIN4_NUM_S 8 +/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN5_NUM 0x00000003U +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003U +#define SPI_DIN5_NUM_S 10 +/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN6_NUM 0x00000003U +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003U +#define SPI_DIN6_NUM_S 12 +/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define SPI_DIN7_NUM 0x00000003U +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003U +#define SPI_DIN7_NUM_S 14 + +/** SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c) +/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001U +#define SPI_DOUT0_MODE_S 0 +/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001U +#define SPI_DOUT1_MODE_S 1 +/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001U +#define SPI_DOUT2_MODE_S 2 +/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001U +#define SPI_DOUT3_MODE_S 3 +/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000001U +#define SPI_DOUT4_MODE_S 4 +/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000001U +#define SPI_DOUT5_MODE_S 5 +/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000001U +#define SPI_DOUT6_MODE_S 6 +/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000001U +#define SPI_DOUT7_MODE_S 7 +/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000001U +#define SPI_D_DQS_MODE_S 8 + +/** SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30) +/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_S 0 +/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_S 1 +/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001U +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001U +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001U +#define SPI_RX_EOF_EN_S 21 +/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001U +#define SPI_DMA_RX_ENA_S 27 +/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001U +#define SPI_DMA_TX_ENA_S 28 +/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001U +#define SPI_RX_AFIFO_RST_S 29 +/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001U +#define SPI_BUF_AFIFO_RST_S 30 +/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001U +#define SPI_DMA_AFIFO_RST_S 31 + +/** SPI_DMA_INT_ENA_REG register + * SPI interrupt enable register + */ +#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD7_INT_ENA_S 4 +/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD8_INT_ENA_S 5 +/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD9_INT_ENA_S 6 +/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001U +#define SPI_SLV_CMDA_INT_ENA_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_TRANS_DONE_INT_ENA_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001U +#define SPI_APP2_INT_ENA_S 19 +/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001U +#define SPI_APP1_INT_ENA_S 20 + +/** SPI_DMA_INT_CLR_REG register + * SPI interrupt clear register + */ +#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38) +/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD7_INT_CLR_S 4 +/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD8_INT_CLR_S 5 +/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD9_INT_CLR_S 6 +/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001U +#define SPI_SLV_CMDA_INT_CLR_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_TRANS_DONE_INT_CLR_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001U +#define SPI_APP2_INT_CLR_S 19 +/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001U +#define SPI_APP1_INT_CLR_S 20 + +/** SPI_DMA_INT_RAW_REG register + * SPI interrupt raw register + */ +#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c) +/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD7_INT_RAW_S 4 +/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD8_INT_RAW_S 5 +/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD9_INT_RAW_S 6 +/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001U +#define SPI_SLV_CMDA_INT_RAW_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_TRANS_DONE_INT_RAW_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001U +#define SPI_APP2_INT_RAW_S 19 +/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001U +#define SPI_APP1_INT_RAW_S 20 + +/** SPI_DMA_INT_ST_REG register + * SPI interrupt status register + */ +#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40) +/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001U +#define SPI_SLV_CMD7_INT_ST_S 4 +/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001U +#define SPI_SLV_CMD8_INT_ST_S 5 +/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001U +#define SPI_SLV_CMD9_INT_ST_S 6 +/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001U +#define SPI_SLV_CMDA_INT_ST_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_TRANS_DONE_INT_ST_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001U +#define SPI_APP2_INT_ST_S 19 +/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001U +#define SPI_APP1_INT_ST_S 20 + +/** SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44) +/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 +/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S) +#define SPI_SLV_EX_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S) +#define SPI_SLV_EN_QPI_INT_SET_V 0x00000001U +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S) +#define SPI_SLV_CMD7_INT_SET_V 0x00000001U +#define SPI_SLV_CMD7_INT_SET_S 4 +/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S) +#define SPI_SLV_CMD8_INT_SET_V 0x00000001U +#define SPI_SLV_CMD8_INT_SET_S 5 +/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S) +#define SPI_SLV_CMD9_INT_SET_V 0x00000001U +#define SPI_SLV_CMD9_INT_SET_S 6 +/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S) +#define SPI_SLV_CMDA_INT_SET_V 0x00000001U +#define SPI_SLV_CMDA_INT_SET_S 7 +/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S) +#define SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_TRANS_DONE_INT_SET_S 12 +/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x00000001U +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x00000001U +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S) +#define SPI_APP2_INT_SET_V 0x00000001U +#define SPI_APP2_INT_SET_S 19 +/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S) +#define SPI_APP1_INT_SET_V 0x00000001U +#define SPI_APP1_INT_SET_S 20 + +/** SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98) +/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF0 0xFFFFFFFFU +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFFU +#define SPI_BUF0_S 0 + +/** SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c) +/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF1 0xFFFFFFFFU +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFFU +#define SPI_BUF1_S 0 + +/** SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0) +/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF2 0xFFFFFFFFU +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFFU +#define SPI_BUF2_S 0 + +/** SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4) +/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF3 0xFFFFFFFFU +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFFU +#define SPI_BUF3_S 0 + +/** SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8) +/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF4 0xFFFFFFFFU +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFFU +#define SPI_BUF4_S 0 + +/** SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac) +/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF5 0xFFFFFFFFU +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFFU +#define SPI_BUF5_S 0 + +/** SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0) +/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF6 0xFFFFFFFFU +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFFU +#define SPI_BUF6_S 0 + +/** SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4) +/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF7 0xFFFFFFFFU +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFFU +#define SPI_BUF7_S 0 + +/** SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8) +/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF8 0xFFFFFFFFU +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFFU +#define SPI_BUF8_S 0 + +/** SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc) +/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF9 0xFFFFFFFFU +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFFU +#define SPI_BUF9_S 0 + +/** SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0) +/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF10 0xFFFFFFFFU +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFFU +#define SPI_BUF10_S 0 + +/** SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4) +/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF11 0xFFFFFFFFU +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFFU +#define SPI_BUF11_S 0 + +/** SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8) +/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF12 0xFFFFFFFFU +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFFU +#define SPI_BUF12_S 0 + +/** SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc) +/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF13 0xFFFFFFFFU +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFFU +#define SPI_BUF13_S 0 + +/** SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0) +/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF14 0xFFFFFFFFU +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFFU +#define SPI_BUF14_S 0 + +/** SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4) +/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI_BUF15 0xFFFFFFFFU +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFFU +#define SPI_BUF15_S 0 + +/** SPI_SLAVE_REG register + * SPI slave control register + */ +#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0) +/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ +#define SPI_CLK_MODE 0x00000003U +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003U +#define SPI_CLK_MODE_S 0 +/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001U +#define SPI_CLK_MODE_13_S 2 +/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001U +#define SPI_RSCK_DATA_OUT_S 3 +/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ +#define SPI_SLV_LAST_BYTE_STRB 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_M (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S) +#define SPI_SLV_LAST_BYTE_STRB_V 0x000000FFU +#define SPI_SLV_LAST_BYTE_STRB_S 12 +/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001U +#define SPI_SLAVE_MODE_S 26 +/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001U +#define SPI_SOFT_RESET_S 27 +/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001U +#define SPI_USR_CONF_S 28 +/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ +#define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) +#define SPI_MST_FD_WAIT_DMA_TX_DATA_V 0x00000001U +#define SPI_MST_FD_WAIT_DMA_TX_DATA_S 29 + +/** SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4) +/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ +#define SPI_SLV_DATA_BITLEN 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFFU +#define SPI_SLV_DATA_BITLEN_S 0 +/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ +#define SPI_SLV_LAST_COMMAND 0x000000FFU +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FFU +#define SPI_SLV_LAST_COMMAND_S 18 +/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ +#define SPI_SLV_LAST_ADDR 0x0000003FU +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003FU +#define SPI_SLV_LAST_ADDR_S 26 + +/** SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 +/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001U +#define SPI_MST_CLK_ACTIVE_S 1 +/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001U +#define SPI_MST_CLK_SEL_S 2 + +/** SPI_DATE_REG register + * Version control + */ +#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0) +/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931; + * SPI register version. + */ +#define SPI_DATE 0x0FFFFFFFU +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFFU +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_struct.h b/components/soc/esp32c5/include/soc/spi_struct.h new file mode 100644 index 0000000000..96c79c5376 --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_struct.h @@ -0,0 +1,1615 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; + * Represents the effective bit of the last received data byte in SPI slave FD and HD + * mode. + */ + uint32_t slv_last_byte_strb:8; + uint32_t reserved_20:2; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; + * In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before + * starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI + * transfer. + */ + uint32_t mst_fd_wait_dma_tx_data:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + + +/** Group: CPU-controlled data buffer */ +/** Type of w0 register + * SPI CPU-controlled buffer0 + */ +typedef union { + struct { + /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi_w0_reg_t; + +/** Type of w1 register + * SPI CPU-controlled buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi_w1_reg_t; + +/** Type of w2 register + * SPI CPU-controlled buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi_w2_reg_t; + +/** Type of w3 register + * SPI CPU-controlled buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi_w3_reg_t; + +/** Type of w4 register + * SPI CPU-controlled buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi_w4_reg_t; + +/** Type of w5 register + * SPI CPU-controlled buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi_w5_reg_t; + +/** Type of w6 register + * SPI CPU-controlled buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi_w6_reg_t; + +/** Type of w7 register + * SPI CPU-controlled buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi_w7_reg_t; + +/** Type of w8 register + * SPI CPU-controlled buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi_w8_reg_t; + +/** Type of w9 register + * SPI CPU-controlled buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi_w9_reg_t; + +/** Type of w10 register + * SPI CPU-controlled buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi_w10_reg_t; + +/** Type of w11 register + * SPI CPU-controlled buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi_w11_reg_t; + +/** Type of w12 register + * SPI CPU-controlled buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi_w12_reg_t; + +/** Type of w13 register + * SPI CPU-controlled buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi_w13_reg_t; + +/** Type of w14 register + * SPI CPU-controlled buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi_w14_reg_t; + +/** Type of w15 register + * SPI CPU-controlled buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi_w15_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716931; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile spi_w0_reg_t w0; + volatile spi_w1_reg_t w1; + volatile spi_w2_reg_t w2; + volatile spi_w3_reg_t w3; + volatile spi_w4_reg_t w4; + volatile spi_w5_reg_t w5; + volatile spi_w6_reg_t w6; + volatile spi_w7_reg_t w7; + volatile spi_w8_reg_t w8; + volatile spi_w9_reg_t w9; + volatile spi_w10_reg_t w10; + volatile spi_w11_reg_t w11; + volatile spi_w12_reg_t w12; + volatile spi_w13_reg_t w13; + volatile spi_w14_reg_t w14; + volatile spi_w15_reg_t w15; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/systimer_reg.h b/components/soc/esp32c5/include/soc/systimer_reg.h new file mode 100644 index 0000000000..07b67111f5 --- /dev/null +++ b/components/soc/esp32c5/include/soc/systimer_reg.h @@ -0,0 +1,630 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ +#define SYSTIMER_ETM_EN (BIT(1)) +#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) +#define SYSTIMER_ETM_EN_V 0x00000001U +#define SYSTIMER_ETM_EN_S 1 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001U +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFFU +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFFU +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/systimer_struct.h b/components/soc/esp32c5/include/soc/systimer_struct.h new file mode 100644 index 0000000000..1bd6331870 --- /dev/null +++ b/components/soc/esp32c5/include/soc/systimer_struct.h @@ -0,0 +1,683 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** etm_en : R/W; bitpos: [1]; default: 0; + * enable systimer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_2:20; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en:1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en:1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en:1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en:1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en:1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en:1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en:1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en:1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en:1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en:1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit0_op register + * system timer unit0 value update register + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit0_value_valid:1; + /** timer_unit0_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit0_update:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} systimer_unit0_op_reg_t; + +/** Type of unit0_load_hi register + * system timer unit0 value high load register + */ +typedef union { + struct { + /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ + uint32_t timer_unit0_load_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit0_load_hi_reg_t; + +/** Type of unit0_load_lo register + * system timer unit0 value low load register + */ +typedef union { + struct { + /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ + uint32_t timer_unit0_load_lo:32; + }; + uint32_t val; +} systimer_unit0_load_lo_reg_t; + +/** Type of unit0_value_hi register + * system timer unit0 value high register + */ +typedef union { + struct { + /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ + uint32_t timer_unit0_value_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit0_value_hi_reg_t; + +/** Type of unit0_value_lo register + * system timer unit0 value low register + */ +typedef union { + struct { + /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ + uint32_t timer_unit0_value_lo:32; + }; + uint32_t val; +} systimer_unit0_value_lo_reg_t; + +/** Type of unit0_load register + * system timer unit0 conf sync register + */ +typedef union { + struct { + /** timer_unit0_load : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ + uint32_t timer_unit0_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_unit0_load_reg_t; + + +/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */ +/** Type of unit1_op register + * system timer unit1 value update register + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ + uint32_t timer_unit1_value_valid:1; + /** timer_unit1_update : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ + uint32_t timer_unit1_update:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} systimer_unit1_op_reg_t; + +/** Type of unit1_load_hi register + * system timer unit1 value high load register + */ +typedef union { + struct { + /** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ + uint32_t timer_unit1_load_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit1_load_hi_reg_t; + +/** Type of unit1_load_lo register + * system timer unit1 value low load register + */ +typedef union { + struct { + /** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ + uint32_t timer_unit1_load_lo:32; + }; + uint32_t val; +} systimer_unit1_load_lo_reg_t; + +/** Type of unit1_value_hi register + * system timer unit1 value high register + */ +typedef union { + struct { + /** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ + uint32_t timer_unit1_value_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_unit1_value_hi_reg_t; + +/** Type of unit1_value_lo register + * system timer unit1 value low register + */ +typedef union { + struct { + /** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ + uint32_t timer_unit1_value_lo:32; + }; + uint32_t val; +} systimer_unit1_value_lo_reg_t; + +/** Type of unit1_load register + * system timer unit1 conf sync register + */ +typedef union { + struct { + /** timer_unit1_load : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ + uint32_t timer_unit1_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_unit1_load_reg_t; + + +/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target0_hi register + * system timer comp0 value high register + */ +typedef union { + struct { + /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ + uint32_t timer_target0_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target0_hi_reg_t; + +/** Type of target0_lo register + * system timer comp0 value low register + */ +typedef union { + struct { + /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ + uint32_t timer_target0_lo:32; + }; + uint32_t val; +} systimer_target0_lo_reg_t; + +/** Type of target0_conf register + * system timer comp0 target mode register + */ +typedef union { + struct { + /** target0_period : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ + uint32_t target0_period:26; + uint32_t reserved_26:4; + /** target0_period_mode : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ + uint32_t target0_period_mode:1; + /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target0_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target0_conf_reg_t; + +/** Type of comp0_load register + * system timer comp0 conf sync register + */ +typedef union { + struct { + /** timer_comp0_load : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ + uint32_t timer_comp0_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp0_load_reg_t; + + +/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target1_hi register + * system timer comp1 value high register + */ +typedef union { + struct { + /** timer_target1_hi : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ + uint32_t timer_target1_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target1_hi_reg_t; + +/** Type of target1_lo register + * system timer comp1 value low register + */ +typedef union { + struct { + /** timer_target1_lo : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ + uint32_t timer_target1_lo:32; + }; + uint32_t val; +} systimer_target1_lo_reg_t; + +/** Type of target1_conf register + * system timer comp1 target mode register + */ +typedef union { + struct { + /** target1_period : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ + uint32_t target1_period:26; + uint32_t reserved_26:4; + /** target1_period_mode : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ + uint32_t target1_period_mode:1; + /** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target1_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target1_conf_reg_t; + +/** Type of comp1_load register + * system timer comp1 conf sync register + */ +typedef union { + struct { + /** timer_comp1_load : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ + uint32_t timer_comp1_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp1_load_reg_t; + + +/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */ +/** Type of target2_hi register + * system timer comp2 value high register + */ +typedef union { + struct { + /** timer_target2_hi : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ + uint32_t timer_target2_hi:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_target2_hi_reg_t; + +/** Type of target2_lo register + * system timer comp2 value low register + */ +typedef union { + struct { + /** timer_target2_lo : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ + uint32_t timer_target2_lo:32; + }; + uint32_t val; +} systimer_target2_lo_reg_t; + +/** Type of target2_conf register + * system timer comp2 target mode register + */ +typedef union { + struct { + /** target2_period : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ + uint32_t target2_period:26; + uint32_t reserved_26:4; + /** target2_period_mode : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ + uint32_t target2_period_mode:1; + /** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target2_timer_unit_sel:1; + }; + uint32_t val; +} systimer_target2_conf_reg_t; + +/** Type of comp2_load register + * system timer comp2 conf sync register + */ +typedef union { + struct { + /** timer_comp2_load : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ + uint32_t timer_comp2_load:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} systimer_comp2_load_reg_t; + + +/** Group: SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena:1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena:1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw:1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw:1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr:1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr:1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st:1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st:1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */ +/** Type of real_target0_lo register + * system timer comp0 actual target value low register + */ +typedef union { + struct { + /** target0_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target0_lo_ro:32; + }; + uint32_t val; +} systimer_real_target0_lo_reg_t; + +/** Type of real_target0_hi register + * system timer comp0 actual target value high register + */ +typedef union { + struct { + /** target0_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target0_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target0_hi_reg_t; + + +/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */ +/** Type of real_target1_lo register + * system timer comp1 actual target value low register + */ +typedef union { + struct { + /** target1_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target1_lo_ro:32; + }; + uint32_t val; +} systimer_real_target1_lo_reg_t; + +/** Type of real_target1_hi register + * system timer comp1 actual target value high register + */ +typedef union { + struct { + /** target1_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target1_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target1_hi_reg_t; + + +/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */ +/** Type of real_target2_lo register + * system timer comp2 actual target value low register + */ +typedef union { + struct { + /** target2_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target2_lo_ro:32; + }; + uint32_t val; +} systimer_real_target2_lo_reg_t; + +/** Type of real_target2_hi register + * system timer comp2 actual target value high register + */ +typedef union { + struct { + /** target2_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target2_hi_ro:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} systimer_real_target2_hi_reg_t; + + +/** Group: VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655795; + * systimer register version + */ + uint32_t date:32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit0_op_reg_t unit0_op; + volatile systimer_unit1_op_reg_t unit1_op; + volatile systimer_unit0_load_hi_reg_t unit0_load_hi; + volatile systimer_unit0_load_lo_reg_t unit0_load_lo; + volatile systimer_unit1_load_hi_reg_t unit1_load_hi; + volatile systimer_unit1_load_lo_reg_t unit1_load_lo; + volatile systimer_target0_hi_reg_t target0_hi; + volatile systimer_target0_lo_reg_t target0_lo; + volatile systimer_target1_hi_reg_t target1_hi; + volatile systimer_target1_lo_reg_t target1_lo; + volatile systimer_target2_hi_reg_t target2_hi; + volatile systimer_target2_lo_reg_t target2_lo; + volatile systimer_target0_conf_reg_t target0_conf; + volatile systimer_target1_conf_reg_t target1_conf; + volatile systimer_target2_conf_reg_t target2_conf; + volatile systimer_unit0_value_hi_reg_t unit0_value_hi; + volatile systimer_unit0_value_lo_reg_t unit0_value_lo; + volatile systimer_unit1_value_hi_reg_t unit1_value_hi; + volatile systimer_unit1_value_lo_reg_t unit1_value_lo; + volatile systimer_comp0_load_reg_t comp0_load; + volatile systimer_comp1_load_reg_t comp1_load; + volatile systimer_comp2_load_reg_t comp2_load; + volatile systimer_unit0_load_reg_t unit0_load; + volatile systimer_unit1_load_reg_t unit1_load; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target0_lo_reg_t real_target0_lo; + volatile systimer_real_target0_hi_reg_t real_target0_hi; + volatile systimer_real_target1_lo_reg_t real_target1_lo; + volatile systimer_real_target1_hi_reg_t real_target1_hi; + volatile systimer_real_target2_lo_reg_t real_target2_lo; + volatile systimer_real_target2_hi_reg_t real_target2_hi; + uint32_t reserved_08c[28]; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/timer_group_reg.h b/components/soc/esp32c5/include/soc/timer_group_reg.h new file mode 100644 index 0000000000..4d3f13661b --- /dev/null +++ b/components/soc/esp32c5/include/soc/timer_group_reg.h @@ -0,0 +1,538 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ +#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0) +/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001U +#define TIMG_T0_ALARM_EN_S 10 +/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; + * When set, Timer 0 's clock divider counter will be reset. + */ +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) +#define TIMG_T0_DIVCNT_RST_V 0x00000001U +#define TIMG_T0_DIVCNT_RST_S 12 +/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ +#define TIMG_T0_DIVIDER 0x0000FFFFU +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFFU +#define TIMG_T0_DIVIDER_S 13 +/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001U +#define TIMG_T0_AUTORELOAD_S 29 +/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. When + * cleared, the timer 0 time-base counter will decrement. + */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001U +#define TIMG_T0_INCREASE_S 30 +/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001U +#define TIMG_T0_EN_S 31 + +/** TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ +#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4) +/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_LO 0xFFFFFFFFU +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFFU +#define TIMG_T0_LO_S 0 + +/** TIMG_T0HI_REG register + * Timer 0 current value, high 22 bits + */ +#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8) +/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter + * of timer 0 can be read here. + */ +#define TIMG_T0_HI 0x003FFFFFU +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0x003FFFFFU +#define TIMG_T0_HI_S 0 + +/** TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ +#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc) +/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001U +#define TIMG_T0_UPDATE_S 31 + +/** TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ +#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10) +/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU +#define TIMG_T0_ALARM_LO_S 0 + +/** TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ +#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14) +/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, high 22 bits. + */ +#define TIMG_T0_ALARM_HI 0x003FFFFFU +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0x003FFFFFU +#define TIMG_T0_ALARM_HI_S 0 + +/** TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ +#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18) +/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * Counter. + */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_LO_S 0 + +/** TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 22 bits + */ +#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c) +/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer 0 time-base + * counter. + */ +#define TIMG_T0_LOAD_HI 0x003FFFFFU +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0x003FFFFFU +#define TIMG_T0_LOAD_HI_S 0 + +/** TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ +#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20) +/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer 0 time-base counter reload. + */ +#define TIMG_T0_LOAD 0xFFFFFFFFU +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFFU +#define TIMG_T0_LOAD_S 0 + +/** TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ +#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48) +/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_APPCPU_RESET_EN_S 12 +/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U +#define TIMG_WDT_CONF_UPDATE_EN_S 22 +/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG3 0x00000003U +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003U +#define TIMG_WDT_STG3_S 23 +/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG2 0x00000003U +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003U +#define TIMG_WDT_STG2_S 25 +/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG1 0x00000003U +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003U +#define TIMG_WDT_STG1_S 27 +/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ +#define TIMG_WDT_STG0 0x00000003U +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003U +#define TIMG_WDT_STG0_S 29 +/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001U +#define TIMG_WDT_EN_S 31 + +/** TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ +#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c) +/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) +#define TIMG_WDT_DIVCNT_RST_V 0x00000001U +#define TIMG_WDT_DIVCNT_RST_S 0 +/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) +#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/** TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ +#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50) +/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG0_HOLD_S 0 + +/** TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ +#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54) +/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG1_HOLD_S 0 + +/** TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ +#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58) +/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG2_HOLD_S 0 + +/** TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ +#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c) +/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define TIMG_WDT_STG3_HOLD_S 0 + +/** TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ +#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60) +/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ +#define TIMG_WDT_FEED 0xFFFFFFFFU +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFFU +#define TIMG_WDT_FEED_S 0 + +/** TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ +#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64) +/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ +#define TIMG_WDT_WKEY 0xFFFFFFFFU +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFFU +#define TIMG_WDT_WKEY_S 0 + +/** TIMG_RTCCALICFG_REG register + * RTC calibration configure register + */ +#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68) +/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U +#define TIMG_RTC_CALI_START_CYCLING_S 12 +/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001U +#define TIMG_RTC_CALI_RDY_S 15 +/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_MAX 0x00007FFFU +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFFU +#define TIMG_RTC_CALI_MAX_S 16 +/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001U +#define TIMG_RTC_CALI_START_S 31 + +/** TIMG_RTCCALICFG1_REG register + * RTC calibration configure1 register + */ +#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c) +/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 +/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU +#define TIMG_RTC_CALI_VALUE_S 7 + +/** TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ +#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70) +/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001U +#define TIMG_T0_INT_ENA_S 0 +/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001U +#define TIMG_WDT_INT_ENA_S 2 + +/** TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ +#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74) +/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001U +#define TIMG_T0_INT_RAW_S 0 +/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001U +#define TIMG_WDT_INT_RAW_S 2 + +/** TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ +#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78) +/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001U +#define TIMG_T0_INT_ST_S 0 +/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001U +#define TIMG_WDT_INT_ST_S 2 + +/** TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ +#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c) +/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001U +#define TIMG_T0_INT_CLR_S 0 +/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001U +#define TIMG_WDT_INT_CLR_S 2 + +/** TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ +#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80) +/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U +#define TIMG_RTC_CALI_TIMEOUT_S 0 +/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/** TIMG_NTIMERS_DATE_REG register + * Timer version control register + */ +#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8) +/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ +#define TIMG_NTIMGS_DATE 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) +#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU +#define TIMG_NTIMGS_DATE_S 0 + +/** TIMG_REGCLK_REG register + * Timer group clock gate register + */ +#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc) +/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ +#define TIMG_ETM_EN (BIT(28)) +#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S) +#define TIMG_ETM_EN_V 0x00000001U +#define TIMG_ETM_EN_S 28 +/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001U +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/timer_group_struct.h b/components/soc/esp32c5/include/soc/timer_group_struct.h new file mode 100644 index 0000000000..b29bece720 --- /dev/null +++ b/components/soc/esp32c5/include/soc/timer_group_struct.h @@ -0,0 +1,552 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: T0 Control and configuration registers */ +/** Type of txconfig register + * Timer x configuration register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * alarm occurs. + */ + uint32_t tx_alarm_en:1; + uint32_t reserved_11:1; + /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; + * When set, Timer x 's clock divider counter will be reset. + */ + uint32_t tx_divcnt_rst:1; + /** tx_divider : R/W; bitpos: [28:13]; default: 1; + * Timer x clock (Tx_clk) prescaler value. + */ + uint32_t tx_divider:16; + /** tx_autoreload : R/W; bitpos: [29]; default: 1; + * When set, timer x auto-reload at alarm is enabled. + */ + uint32_t tx_autoreload:1; + /** tx_increase : R/W; bitpos: [30]; default: 1; + * When set, the timer x time-base counter will increment every clock tick. When + * cleared, the timer x time-base counter will decrement. + */ + uint32_t tx_increase:1; + /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0; + * When set, the timer x time-base counter is enabled. + */ + uint32_t tx_en:1; + }; + uint32_t val; +} timg_txconfig_reg_t; + +/** Type of txlo register + * Timer x current value, low 32 bits + */ +typedef union { + struct { + /** tx_lo : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_lo:32; + }; + uint32_t val; +} timg_txlo_reg_t; + +/** Type of txhi register + * Timer x current value, high 22 bits + */ +typedef union { + struct { + /** tx_hi : RO; bitpos: [21:0]; default: 0; + * After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter + * of timer x can be read here. + */ + uint32_t tx_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txhi_reg_t; + +/** Type of txupdate register + * Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** tx_update : R/W/SC; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched. + */ + uint32_t tx_update:1; + }; + uint32_t val; +} timg_txupdate_reg_t; + +/** Type of txalarmlo register + * Timer x alarm value, low 32 bits + */ +typedef union { + struct { + /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; + * Timer x alarm trigger time-base counter value, low 32 bits. + */ + uint32_t tx_alarm_lo:32; + }; + uint32_t val; +} timg_txalarmlo_reg_t; + +/** Type of txalarmhi register + * Timer x alarm value, high bits + */ +typedef union { + struct { + /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; + * Timer x alarm trigger time-base counter value, high 22 bits. + */ + uint32_t tx_alarm_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txalarmhi_reg_t; + +/** Type of txloadlo register + * Timer x reload value, low 32 bits + */ +typedef union { + struct { + /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32 bits of the value that a reload will load onto timer x time-base + * Counter. + */ + uint32_t tx_load_lo:32; + }; + uint32_t val; +} timg_txloadlo_reg_t; + +/** Type of txloadhi register + * Timer x reload value, high 22 bits + */ +typedef union { + struct { + /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; + * High 22 bits of the value that a reload will load onto timer x time-base + * counter. + */ + uint32_t tx_load_hi:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} timg_txloadhi_reg_t; + +/** Type of txload register + * Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG + */ +typedef union { + struct { + /** tx_load : WT; bitpos: [31:0]; default: 0; + * + * Write any value to trigger a timer x time-base counter reload. + */ + uint32_t tx_load:32; + }; + uint32_t val; +} timg_txload_reg_t; + + +/** Group: WDT Control and configuration registers */ +/** Type of wdtconfig0 register + * Watchdog timer configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + uint32_t wdt_cpu_reset_length:3; + uint32_t reserved_21:1; + /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; + * update the WDT configuration registers + */ + uint32_t wdt_conf_update_en:1; + /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg3:2; + /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg2:2; + /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg1:2; + /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + */ + uint32_t wdt_stg0:2; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} timg_wdtconfig0_reg_t; + +/** Type of wdtconfig1 register + * Watchdog timer prescaler register + */ +typedef union { + struct { + /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; + * When set, WDT 's clock divider counter will be reset. + */ + uint32_t wdt_divcnt_rst:1; + uint32_t reserved_1:15; + /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * TIMG_WDT_CLK_PRESCALE. + */ + uint32_t wdt_clk_prescale:16; + }; + uint32_t val; +} timg_wdtconfig1_reg_t; + +/** Type of wdtconfig2 register + * Watchdog timer stage 0 timeout value + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} timg_wdtconfig2_reg_t; + +/** Type of wdtconfig3 register + * Watchdog timer stage 1 timeout value + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} timg_wdtconfig3_reg_t; + +/** Type of wdtconfig4 register + * Watchdog timer stage 2 timeout value + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} timg_wdtconfig4_reg_t; + +/** Type of wdtconfig5 register + * Watchdog timer stage 3 timeout value + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} timg_wdtconfig5_reg_t; + +/** Type of wdtfeed register + * Write to feed the watchdog timer + */ +typedef union { + struct { + /** wdt_feed : WT; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + uint32_t wdt_feed:32; + }; + uint32_t val; +} timg_wdtfeed_reg_t; + +/** Type of wdtwprotect register + * Watchdog write protect register + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * protection is enabled. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} timg_wdtwprotect_reg_t; + + +/** Group: RTC CALI Control and configuration registers */ +/** Type of rtccalicfg register + * RTC calibration configure register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; + * 0: one-shot frequency calculation,1: periodic frequency calculation, + */ + uint32_t rtc_cali_start_cycling:1; + /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0; + * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + */ + uint32_t rtc_cali_clk_sel:2; + /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; + * indicate one-shot frequency calculation is done. + */ + uint32_t rtc_cali_rdy:1; + /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; + * Configure the time to calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_max:15; + /** rtc_cali_start : R/W; bitpos: [31]; default: 0; + * Set this bit to start one-shot frequency calculation. + */ + uint32_t rtc_cali_start:1; + }; + uint32_t val; +} timg_rtccalicfg_reg_t; + +/** Type of rtccalicfg1 register + * RTC calibration configure1 register + */ +typedef union { + struct { + /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; + * indicate periodic frequency calculation is done. + */ + uint32_t rtc_cali_cycling_data_vld:1; + uint32_t reserved_1:6; + /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; + * When one-shot or periodic frequency calculation is done, read this value to + * calculate RTC slow clock's frequency. + */ + uint32_t rtc_cali_value:25; + }; + uint32_t val; +} timg_rtccalicfg1_reg_t; + +/** Type of rtccalicfg2 register + * Timer group calibration register + */ +typedef union { + struct { + /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + uint32_t rtc_cali_timeout:1; + uint32_t reserved_1:2; + /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + uint32_t rtc_cali_timeout_rst_cnt:4; + /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's value + * exceeds this threshold, a timeout is triggered. + */ + uint32_t rtc_cali_timeout_thres:25; + }; + uint32_t val; +} timg_rtccalicfg2_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena_timers register + * Interrupt enable bits + */ +typedef union { + struct { + /** t0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_ena:1; + uint32_t reserved_1:1; + /** wdt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_ena_timers_reg_t; + +/** Type of int_raw_timers register + * Raw interrupt status + */ +typedef union { + struct { + /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_raw:1; + uint32_t reserved_1:1; + /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_raw_timers_reg_t; + +/** Type of int_st_timers register + * Masked interrupt status + */ +typedef union { + struct { + /** t0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_st:1; + uint32_t reserved_1:1; + /** wdt_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_st_timers_reg_t; + +/** Type of int_clr_timers register + * Interrupt clear bits + */ +typedef union { + struct { + /** t0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T$x_INT interrupt. + */ + uint32_t t0_int_clr:1; + uint32_t reserved_1:1; + /** wdt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + uint32_t wdt_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} timg_int_clr_timers_reg_t; + + +/** Group: Version register */ +/** Type of ntimers_date register + * Timer version control register + */ +typedef union { + struct { + /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770; + * Timer version control register + */ + uint32_t ntimgs_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} timg_ntimers_date_reg_t; + + +/** Group: Clock configuration registers */ +/** Type of regclk register + * Timer group clock gate register + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** etm_en : R/W; bitpos: [28]; default: 1; + * enable timer's etm task and event + */ + uint32_t etm_en:1; + uint32_t reserved_29:2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by software. 0: + * Registers can not be read or written to by software. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} timg_regclk_reg_t; + + +typedef struct { + volatile timg_txconfig_reg_t t0config; + volatile timg_txlo_reg_t t0lo; + volatile timg_txhi_reg_t t0hi; + volatile timg_txupdate_reg_t t0update; + volatile timg_txalarmlo_reg_t t0alarmlo; + volatile timg_txalarmhi_reg_t t0alarmhi; + volatile timg_txloadlo_reg_t t0loadlo; + volatile timg_txloadhi_reg_t t0loadhi; + volatile timg_txload_reg_t t0load; + uint32_t reserved_024[9]; + volatile timg_wdtconfig0_reg_t wdtconfig0; + volatile timg_wdtconfig1_reg_t wdtconfig1; + volatile timg_wdtconfig2_reg_t wdtconfig2; + volatile timg_wdtconfig3_reg_t wdtconfig3; + volatile timg_wdtconfig4_reg_t wdtconfig4; + volatile timg_wdtconfig5_reg_t wdtconfig5; + volatile timg_wdtfeed_reg_t wdtfeed; + volatile timg_wdtwprotect_reg_t wdtwprotect; + volatile timg_rtccalicfg_reg_t rtccalicfg; + volatile timg_rtccalicfg1_reg_t rtccalicfg1; + volatile timg_int_ena_timers_reg_t int_ena_timers; + volatile timg_int_raw_timers_reg_t int_raw_timers; + volatile timg_int_st_timers_reg_t int_st_timers; + volatile timg_int_clr_timers_reg_t int_clr_timers; + volatile timg_rtccalicfg2_reg_t rtccalicfg2; + uint32_t reserved_084[29]; + volatile timg_ntimers_date_reg_t ntimers_date; + volatile timg_regclk_reg_t regclk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifndef __cplusplus +_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/trace_reg.h b/components/soc/esp32c5/include/soc/trace_reg.h new file mode 100644 index 0000000000..c0f45143e9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/trace_reg.h @@ -0,0 +1,463 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * mem start addr + */ +#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ +#define TRACE_MEM_START_ADDR 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S) +#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * mem end addr + */ +#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * mem current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * mem addr update + */ +#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * fifo status register + */ +#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. \\1: empty \\0: not empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due + * to hart halted or havereset \\3: lost state + */ +#define TRACE_WORK_STATUS 0x00000003U +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000003U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * interrupt enable register + */ +#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * interrupt status register + */ +#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * interrupt clear register + */ +#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * trigger register + */ +#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace.\\1: start trace \\0: invalid\\ + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_CONFIG_REG register + * trace configuration register + */ +#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24) +/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + */ +#define TRACE_DM_TRIGGER_ENA (BIT(0)) +#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S) +#define TRACE_DM_TRIGGER_ENA_V 0x00000001U +#define TRACE_DM_TRIGGER_ENA_S 0 +/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * disabled\\ + */ +#define TRACE_RESET_ENA (BIT(1)) +#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S) +#define TRACE_RESET_ENA_V 0x00000001U +#define TRACE_RESET_ENA_S 1 +/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + */ +#define TRACE_HALT_ENA (BIT(2)) +#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) +#define TRACE_HALT_ENA_V 0x00000001U +#define TRACE_HALT_ENA_S 2 +/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo.\\1: + * enabled.\\0: disabled\\ + */ +#define TRACE_STALL_ENA (BIT(3)) +#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S) +#define TRACE_STALL_ENA_V 0x00000001U +#define TRACE_STALL_ENA_S 3 +/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta + * address mode\\ + */ +#define TRACE_FULL_ADDRESS (BIT(4)) +#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S) +#define TRACE_FULL_ADDRESS_V 0x00000001U +#define TRACE_FULL_ADDRESS_S 4 +/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ +#define TRACE_IMPLICIT_EXCEPT (BIT(5)) +#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S) +#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U +#define TRACE_IMPLICIT_EXCEPT_S 5 + +/** TRACE_FILTER_CONTROL_REG register + * filter control register + */ +#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28) +/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + */ +#define TRACE_FILTER_EN (BIT(0)) +#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S) +#define TRACE_FILTER_EN_V 0x00000001U +#define TRACE_FILTER_EN_S 0 +/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ +#define TRACE_MATCH_COMP (BIT(1)) +#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S) +#define TRACE_MATCH_COMP_V 0x00000001U +#define TRACE_MATCH_COMP_S 1 +/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ +#define TRACE_MATCH_PRIVILEGE (BIT(2)) +#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S) +#define TRACE_MATCH_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_PRIVILEGE_S 2 +/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ +#define TRACE_MATCH_ECAUSE (BIT(3)) +#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S) +#define TRACE_MATCH_ECAUSE_V 0x00000001U +#define TRACE_MATCH_ECAUSE_S 3 +/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ +#define TRACE_MATCH_INTERRUPT (BIT(4)) +#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S) +#define TRACE_MATCH_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_INTERRUPT_S 4 + +/** TRACE_FILTER_MATCH_CONTROL_REG register + * filter match control register + */ +#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c) +/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: + * machine mode. \\0: user mode + */ +#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0)) +#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S) +#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0 +/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match + * itype of 2. \\0: match itype or 1. + */ +#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1)) +#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S) +#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_VALUE_INTERRUPT_S 1 +/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ +#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S) +#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_S 2 + +/** TRACE_FILTER_COMPARATOR_CONTROL_REG register + * filter comparator match control register + */ +#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30) +/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: + * tval. + */ +#define TRACE_P_INPUT (BIT(0)) +#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S) +#define TRACE_P_INPUT_V 0x00000001U +#define TRACE_P_INPUT_S 0 +/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, + * \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: + * always match + */ +#define TRACE_P_FUNCTION 0x00000007U +#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S) +#define TRACE_P_FUNCTION_V 0x00000007U +#define TRACE_P_FUNCTION_S 2 +/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ +#define TRACE_P_NOTIFY (BIT(5)) +#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S) +#define TRACE_P_NOTIFY_V 0x00000001U +#define TRACE_P_NOTIFY_S 5 +/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, \\0: iaddr, + * \\1: tval. + */ +#define TRACE_S_INPUT (BIT(8)) +#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S) +#define TRACE_S_INPUT_V 0x00000001U +#define TRACE_S_INPUT_S 8 +/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less + * than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, + * \\other: always match + */ +#define TRACE_S_FUNCTION 0x00000007U +#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S) +#define TRACE_S_FUNCTION_V 0x00000007U +#define TRACE_S_FUNCTION_S 10 +/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ +#define TRACE_S_NOTIFY (BIT(13)) +#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S) +#define TRACE_S_NOTIFY_V 0x00000001U +#define TRACE_S_NOTIFY_S 13 +/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, \\1: primary and secondary comparator both + * matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: + * set when primary matches and continue to match until after secondary comparator + * matches + */ +#define TRACE_MATCH_MODE 0x00000003U +#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S) +#define TRACE_MATCH_MODE_V 0x00000003U +#define TRACE_MATCH_MODE_S 16 + +/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register + * primary comparator match value + */ +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34) +/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ +#define TRACE_P_MATCH 0xFFFFFFFFU +#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S) +#define TRACE_P_MATCH_V 0xFFFFFFFFU +#define TRACE_P_MATCH_S 0 + +/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register + * secondary comparator match value + */ +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38) +/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ +#define TRACE_S_MATCH 0xFFFFFFFFU +#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S) +#define TRACE_S_MATCH_V 0xFFFFFFFFU +#define TRACE_S_MATCH_S 0 + +/** TRACE_RESYNC_PROLONGED_REG register + * resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + */ +#define TRACE_RESYNC_MODE 0x00000003U +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000003U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_AHB_CONFIG_REG register + * AHB config register + */ +#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) +/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ +#define TRACE_HBURST 0x00000007U +#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S) +#define TRACE_HBURST_V 0x00000007U +#define TRACE_HBURST_S 0 +/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ +#define TRACE_MAX_INCR 0x00000007U +#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S) +#define TRACE_MAX_INCR_V 0x00000007U +#define TRACE_MAX_INCR_S 3 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/trace_struct.h b/components/soc/esp32c5/include/soc/trace_struct.h new file mode 100644 index 0000000000..08667b8cbc --- /dev/null +++ b/components/soc/esp32c5/include/soc/trace_struct.h @@ -0,0 +1,461 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Trace memory configuration registers */ +/** Type of mem_start_addr register + * mem start addr + */ +typedef union { + struct { + /** mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address of trace memory + */ + uint32_t mem_start_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * mem end addr + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address of trace memory + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * mem current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * current_mem_addr,indicate that next writing addr + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * mem addr update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * when set, the will + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * fifo status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * Represent whether the fifo is empty. \\1: empty \\0: not empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [2:1]; default: 0; + * Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due + * to hart halted or havereset \\3: lost state + */ + uint32_t work_status:2; + uint32_t reserved_3:29; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Trace interrupt configuration registers */ +/** Type of intr_ena register + * interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Set 1 enable fifo_overflow interrupt + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Set 1 enable mem_full interrupt + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * interrupt status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * fifo_overflow interrupt status + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * mem_full interrupt status + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Set 1 clear fifo overflow interrupt + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Set 1 clear mem full interrupt + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * trigger register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * Configure whether or not start trace.\\1: start trace \\0: invalid\\ + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of config register + * trace configuration register + */ +typedef union { + struct { + /** dm_trigger_ena : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + */ + uint32_t dm_trigger_ena:1; + /** reset_ena : R/W; bitpos: [1]; default: 0; + * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * reset, the encoder will output a packet to report the address of the last + * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * disabled\\ + */ + uint32_t reset_ena:1; + /** halt_ena : R/W; bitpos: [2]; default: 0; + * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * halted, the encoder will output a packet to report the address of the last + * instruction, and upon halted deassertion, the encoder start again.When disabled, + * encoder will not report the last address before halted and first address after + * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + */ + uint32_t halt_ena:1; + /** stall_ena : R/W; bitpos: [3]; default: 0; + * Configure whether or not enable stall cpu. When enabled, when the fifo almost full, + * the cpu will be stalled until the packets is able to write to fifo.\\1: + * enabled.\\0: disabled\\ + */ + uint32_t stall_ena:1; + /** full_address : R/W; bitpos: [4]; default: 0; + * Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta + * address mode\\ + */ + uint32_t full_address:1; + /** implicit_except : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ + uint32_t implicit_except:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_config_reg_t; + +/** Type of filter_control register + * filter control register + */ +typedef union { + struct { + /** filter_en : R/W; bitpos: [0]; default: 0; + * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + */ + uint32_t filter_en:1; + /** match_comp : R/W; bitpos: [1]; default: 0; + * when set, the comparator must be high in order for the filter to match + */ + uint32_t match_comp:1; + /** match_privilege : R/W; bitpos: [2]; default: 0; + * when set, match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ + uint32_t match_privilege:1; + /** match_ecause : R/W; bitpos: [3]; default: 0; + * when set, start matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ + uint32_t match_ecause:1; + /** match_interrupt : R/W; bitpos: [4]; default: 0; + * when set, start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ + uint32_t match_interrupt:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} trace_filter_control_reg_t; + +/** Type of filter_match_control register + * filter match control register + */ +typedef union { + struct { + /** match_choice_privilege : R/W; bitpos: [0]; default: 0; + * Select match which privilege level when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: + * machine mode. \\0: user mode + */ + uint32_t match_choice_privilege:1; + /** match_value_interrupt : R/W; bitpos: [1]; default: 0; + * Select which match which itype when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match + * itype of 2. \\0: match itype or 1. + */ + uint32_t match_value_interrupt:1; + /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0; + * specified which ecause matched. + */ + uint32_t match_choice_ecause:6; + uint32_t reserved_8:24; + }; + uint32_t val; +} trace_filter_match_control_reg_t; + +/** Type of filter_comparator_control register + * filter comparator match control register + */ +typedef union { + struct { + /** p_input : R/W; bitpos: [0]; default: 0; + * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: + * tval. + */ + uint32_t p_input:1; + uint32_t reserved_1:1; + /** p_function : R/W; bitpos: [4:2]; default: 0; + * Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, + * \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: + * always match + */ + uint32_t p_function:3; + /** p_notify : R/W; bitpos: [5]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the primary + * match + */ + uint32_t p_notify:1; + uint32_t reserved_6:2; + /** s_input : R/W; bitpos: [8]; default: 0; + * Determines which input to compare against the secondary comparator, \\0: iaddr, + * \\1: tval. + */ + uint32_t s_input:1; + uint32_t reserved_9:1; + /** s_function : R/W; bitpos: [12:10]; default: 0; + * Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less + * than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, + * \\other: always match + */ + uint32_t s_function:3; + /** s_notify : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ + uint32_t s_notify:1; + uint32_t reserved_14:2; + /** match_mode : R/W; bitpos: [17:16]; default: 0; + * 0: only primary matches, \\1: primary and secondary comparator both + * matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: + * set when primary matches and continue to match until after secondary comparator + * matches + */ + uint32_t match_mode:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} trace_filter_comparator_control_reg_t; + +/** Type of filter_p_comparator_match register + * primary comparator match value + */ +typedef union { + struct { + /** p_match : R/W; bitpos: [31:0]; default: 0; + * primary comparator match value + */ + uint32_t p_match:32; + }; + uint32_t val; +} trace_filter_p_comparator_match_reg_t; + +/** Type of filter_s_comparator_match register + * secondary comparator match value + */ +typedef union { + struct { + /** s_match : R/W; bitpos: [31:0]; default: 0; + * secondary comparator match value + */ + uint32_t s_match:32; + }; + uint32_t val; +} trace_filter_s_comparator_match_reg_t; + +/** Type of resync_prolonged register + * resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * count number, when count to this value, send a sync package + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [25:24]; default: 0; + * resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + */ + uint32_t resync_mode:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + +/** Type of ahb_config register + * AHB config register + */ +typedef union { + struct { + /** hburst : R/W; bitpos: [2:0]; default: 0; + * set hburst + */ + uint32_t hburst:3; + /** max_incr : R/W; bitpos: [5:3]; default: 0; + * set max continuous access for incr mode + */ + uint32_t max_incr:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_ahb_config_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gate when access all registers in this module. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35721984; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_config_reg_t config; + volatile trace_filter_control_reg_t filter_control; + volatile trace_filter_match_control_reg_t filter_match_control; + volatile trace_filter_comparator_control_reg_t filter_comparator_control; + volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match; + volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_ahb_config_reg_t ahb_config; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_048[237]; + volatile trace_date_reg_t date; +} trace_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uart_reg.h b/components/soc/esp32c5/include/soc/uart_reg.h new file mode 100644 index 0000000000..1be6cb107f --- /dev/null +++ b/components/soc/esp32c5/include/soc/uart_reg.h @@ -0,0 +1,1579 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UART_FIFO_REG register + * FIFO data register + */ +#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0) +/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define UART_RXFIFO_RD_BYTE 0x000000FFU +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define UART_RXFIFO_RD_BYTE_S 0 + +/** UART_INT_RAW_REG register + * Raw interrupt status + */ +#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4) +/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define UART_RXFIFO_FULL_INT_RAW_S 0 +/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_PARITY_ERR_INT_RAW_S 2 +/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_FRM_ERR_INT_RAW_S 3 +/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001U +#define UART_DSR_CHG_INT_RAW_S 5 +/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001U +#define UART_CTS_CHG_INT_RAW_S 6 +/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001U +#define UART_BRK_DET_INT_RAW_S 7 +/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001U +#define UART_SW_XON_INT_RAW_S 9 +/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001U +#define UART_SW_XOFF_INT_RAW_S 10 +/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define UART_GLITCH_DET_INT_RAW_S 11 +/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001U +#define UART_TX_DONE_INT_RAW_S 14 +/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001U +#define UART_RS485_CLASH_INT_RAW_S 17 +/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001U +#define UART_WAKEUP_INT_RAW_S 19 + +/** UART_INT_ST_REG register + * Masked interrupt status + */ +#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8) +/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ST_S 0 +/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_PARITY_ERR_INT_ST_S 2 +/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001U +#define UART_FRM_ERR_INT_ST_S 3 +/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ST_S 4 +/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001U +#define UART_DSR_CHG_INT_ST_S 5 +/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001U +#define UART_CTS_CHG_INT_ST_S 6 +/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001U +#define UART_BRK_DET_INT_ST_S 7 +/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001U +#define UART_SW_XON_INT_ST_S 9 +/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001U +#define UART_SW_XOFF_INT_ST_S 10 +/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001U +#define UART_GLITCH_DET_INT_ST_S 11 +/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ST_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001U +#define UART_TX_DONE_INT_ST_S 14 +/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001U +#define UART_RS485_CLASH_INT_ST_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001U +#define UART_WAKEUP_INT_ST_S 19 + +/** UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc) +/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define UART_RXFIFO_FULL_INT_ENA_S 0 +/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_PARITY_ERR_INT_ENA_S 2 +/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_FRM_ERR_INT_ENA_S 3 +/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001U +#define UART_DSR_CHG_INT_ENA_S 5 +/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001U +#define UART_CTS_CHG_INT_ENA_S 6 +/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001U +#define UART_BRK_DET_INT_ENA_S 7 +/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001U +#define UART_SW_XON_INT_ENA_S 9 +/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001U +#define UART_SW_XOFF_INT_ENA_S 10 +/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define UART_GLITCH_DET_INT_ENA_S 11 +/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001U +#define UART_TX_DONE_INT_ENA_S 14 +/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001U +#define UART_RS485_CLASH_INT_ENA_S 17 +/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001U +#define UART_WAKEUP_INT_ENA_S 19 + +/** UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10) +/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define UART_RXFIFO_FULL_INT_CLR_S 0 +/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_PARITY_ERR_INT_CLR_S 2 +/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_FRM_ERR_INT_CLR_S 3 +/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001U +#define UART_DSR_CHG_INT_CLR_S 5 +/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001U +#define UART_CTS_CHG_INT_CLR_S 6 +/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001U +#define UART_BRK_DET_INT_CLR_S 7 +/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001U +#define UART_SW_XON_INT_CLR_S 9 +/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001U +#define UART_SW_XOFF_INT_CLR_S 10 +/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define UART_GLITCH_DET_INT_CLR_S 11 +/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001U +#define UART_TX_DONE_INT_CLR_S 14 +/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001U +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001U +#define UART_RS485_CLASH_INT_CLR_S 17 +/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001U +#define UART_WAKEUP_INT_CLR_S 19 + +/** UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14) +/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define UART_CLKDIV 0x00000FFFU +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x00000FFFU +#define UART_CLKDIV_S 0 +/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define UART_CLKDIV_FRAG 0x0000000FU +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000FU +#define UART_CLKDIV_FRAG_S 20 + +/** UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18) +/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define UART_GLITCH_FILT 0x000000FFU +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FFU +#define UART_GLITCH_FILT_S 0 +/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) +#define UART_GLITCH_FILT_EN_V 0x00000001U +#define UART_GLITCH_FILT_EN_S 8 + +/** UART_STATUS_REG register + * UART status register + */ +#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c) +/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define UART_RXFIFO_CNT 0x000000FFU +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000000FFU +#define UART_RXFIFO_CNT_S 0 +/** UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001U +#define UART_DSRN_S 13 +/** UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001U +#define UART_CTSN_S 14 +/** UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001U +#define UART_RXD_S 15 +/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define UART_TXFIFO_CNT 0x000000FFU +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000000FFU +#define UART_TXFIFO_CNT_S 16 +/** UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001U +#define UART_DTRN_S 29 +/** UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001U +#define UART_RTSN_S 30 +/** UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001U +#define UART_TXD_S 31 + +/** UART_CONF0_SYNC_REG register + * a + */ +#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20) +/** UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001U +#define UART_PARITY_S 0 +/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001U +#define UART_PARITY_EN_S 1 +/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define UART_BIT_NUM 0x00000003U +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003U +#define UART_BIT_NUM_S 2 +/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define UART_STOP_BIT_NUM 0x00000003U +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003U +#define UART_STOP_BIT_NUM_S 4 +/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define UART_TXD_BRK (BIT(6)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001U +#define UART_TXD_BRK_S 6 +/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ +#define UART_IRDA_DPLX (BIT(7)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001U +#define UART_IRDA_DPLX_S 7 +/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ +#define UART_IRDA_TX_EN (BIT(8)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001U +#define UART_IRDA_TX_EN_S 8 +/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ +#define UART_IRDA_WCTL (BIT(9)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001U +#define UART_IRDA_WCTL_S 9 +/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ +#define UART_IRDA_TX_INV (BIT(10)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001U +#define UART_IRDA_TX_INV_S 10 +/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ +#define UART_IRDA_RX_INV (BIT(11)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001U +#define UART_IRDA_RX_INV_S 11 +/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define UART_LOOPBACK (BIT(12)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001U +#define UART_LOOPBACK_S 12 +/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define UART_TX_FLOW_EN (BIT(13)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001U +#define UART_TX_FLOW_EN_S 13 +/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ +#define UART_IRDA_EN (BIT(14)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001U +#define UART_IRDA_EN_S 14 +/** UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define UART_RXD_INV (BIT(15)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001U +#define UART_RXD_INV_S 15 +/** UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define UART_TXD_INV (BIT(16)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001U +#define UART_TXD_INV_S 16 +/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define UART_DIS_RX_DAT_OVF (BIT(17)) +#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) +#define UART_DIS_RX_DAT_OVF_V 0x00000001U +#define UART_DIS_RX_DAT_OVF_S 17 +/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define UART_ERR_WR_MASK (BIT(18)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001U +#define UART_ERR_WR_MASK_S 18 +/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ +#define UART_AUTOBAUD_EN (BIT(19)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001U +#define UART_AUTOBAUD_EN_S 19 +/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define UART_MEM_CLK_EN (BIT(20)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001U +#define UART_MEM_CLK_EN_S 20 +/** UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define UART_SW_RTS (BIT(21)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001U +#define UART_SW_RTS_S 21 +/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define UART_RXFIFO_RST (BIT(22)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001U +#define UART_RXFIFO_RST_S 22 +/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define UART_TXFIFO_RST (BIT(23)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001U +#define UART_TXFIFO_RST_S 23 + +/** UART_CONF1_REG register + * Configuration register 1 + */ +#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24) +/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define UART_RXFIFO_FULL_THRHD 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000000FFU +#define UART_RXFIFO_FULL_THRHD_S 0 +/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define UART_TXFIFO_EMPTY_THRHD 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000000FFU +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/** UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define UART_CTS_INV (BIT(16)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001U +#define UART_CTS_INV_S 16 +/** UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define UART_DSR_INV (BIT(17)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001U +#define UART_DSR_INV_S 17 +/** UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define UART_RTS_INV (BIT(18)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001U +#define UART_RTS_INV_S 18 +/** UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define UART_DTR_INV (BIT(19)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001U +#define UART_DTR_INV_S 19 +/** UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define UART_SW_DTR (BIT(20)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001U +#define UART_SW_DTR_S 20 +/** UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define UART_CLK_EN (BIT(21)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001U +#define UART_CLK_EN_S 21 + +/** UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c) +/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define UART_RX_FLOW_THRHD 0x000000FFU +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000000FFU +#define UART_RX_FLOW_THRHD_S 0 +/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define UART_RX_FLOW_EN (BIT(8)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001U +#define UART_RX_FLOW_EN_S 8 + +/** UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30) +/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define UART_WK_CHAR1 0x000000FFU +#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) +#define UART_WK_CHAR1_V 0x000000FFU +#define UART_WK_CHAR1_S 0 +/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define UART_WK_CHAR2 0x000000FFU +#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) +#define UART_WK_CHAR2_V 0x000000FFU +#define UART_WK_CHAR2_S 8 +/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define UART_WK_CHAR3 0x000000FFU +#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) +#define UART_WK_CHAR3_V 0x000000FFU +#define UART_WK_CHAR3_S 16 +/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define UART_WK_CHAR4 0x000000FFU +#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) +#define UART_WK_CHAR4_V 0x000000FFU +#define UART_WK_CHAR4_S 24 + +/** UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34) +/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define UART_WK_CHAR0 0x000000FFU +#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) +#define UART_WK_CHAR0_V 0x000000FFU +#define UART_WK_CHAR0_S 0 + +/** UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38) +/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define UART_ACTIVE_THRESHOLD 0x000003FFU +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define UART_ACTIVE_THRESHOLD_S 0 +/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define UART_RX_WAKE_UP_THRHD 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) +#define UART_RX_WAKE_UP_THRHD_V 0x000000FFU +#define UART_RX_WAKE_UP_THRHD_S 10 +/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define UART_WK_CHAR_NUM 0x00000007U +#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) +#define UART_WK_CHAR_NUM_V 0x00000007U +#define UART_WK_CHAR_NUM_S 18 +/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define UART_WK_CHAR_MASK 0x0000001FU +#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) +#define UART_WK_CHAR_MASK_V 0x0000001FU +#define UART_WK_CHAR_MASK_S 21 +/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define UART_WK_MODE_SEL 0x00000003U +#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) +#define UART_WK_MODE_SEL_V 0x00000003U +#define UART_WK_MODE_SEL_S 26 + +/** UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c) +/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define UART_XON_CHAR 0x000000FFU +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FFU +#define UART_XON_CHAR_S 0 +/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define UART_XOFF_CHAR 0x000000FFU +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FFU +#define UART_XOFF_CHAR_S 8 +/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define UART_XON_XOFF_STILL_SEND (BIT(16)) +#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) +#define UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define UART_XON_XOFF_STILL_SEND_S 16 +/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define UART_SW_FLOW_CON_EN (BIT(17)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001U +#define UART_SW_FLOW_CON_EN_S 17 +/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define UART_XONOFF_DEL (BIT(18)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001U +#define UART_XONOFF_DEL_S 18 +/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define UART_FORCE_XON (BIT(19)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001U +#define UART_FORCE_XON_S 19 +/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define UART_FORCE_XOFF (BIT(20)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001U +#define UART_FORCE_XOFF_S 20 +/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define UART_SEND_XON (BIT(21)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001U +#define UART_SEND_XON_S 21 +/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define UART_SEND_XOFF (BIT(22)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001U +#define UART_SEND_XOFF_S 22 + +/** UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40) +/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define UART_XON_THRESHOLD 0x000000FFU +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000000FFU +#define UART_XON_THRESHOLD_S 0 +/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define UART_XOFF_THRESHOLD 0x000000FFU +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000000FFU +#define UART_XOFF_THRESHOLD_S 8 + +/** UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44) +/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define UART_TX_BRK_NUM 0x000000FFU +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FFU +#define UART_TX_BRK_NUM_S 0 + +/** UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48) +/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define UART_RX_IDLE_THRHD 0x000003FFU +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FFU +#define UART_RX_IDLE_THRHD_S 0 +/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define UART_TX_IDLE_NUM 0x000003FFU +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FFU +#define UART_TX_IDLE_NUM_S 10 + +/** UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c) +/** UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001U +#define UART_RS485_EN_S 0 +/** UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001U +#define UART_DL0_EN_S 1 +/** UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001U +#define UART_DL1_EN_S 2 +/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001U +#define UART_RS485TX_RX_EN_S 3 +/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001U +#define UART_RS485RXBY_TX_EN_S 4 +/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001U +#define UART_RS485_RX_DLY_NUM_S 5 +/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ +#define UART_RS485_TX_DLY_NUM 0x0000000FU +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000FU +#define UART_RS485_TX_DLY_NUM_S 6 + +/** UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50) +/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define UART_PRE_IDLE_NUM 0x0000FFFFU +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define UART_PRE_IDLE_NUM_S 0 + +/** UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54) +/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define UART_POST_IDLE_NUM 0x0000FFFFU +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFFU +#define UART_POST_IDLE_NUM_S 0 + +/** UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58) +/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define UART_RX_GAP_TOUT 0x0000FFFFU +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFFU +#define UART_RX_GAP_TOUT_S 0 + +/** UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c) +/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define UART_AT_CMD_CHAR 0x000000FFU +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FFU +#define UART_AT_CMD_CHAR_S 0 +/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define UART_CHAR_NUM 0x000000FFU +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FFU +#define UART_CHAR_NUM_S 8 + +/** UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60) +/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define UART_MEM_FORCE_PD (BIT(25)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001U +#define UART_MEM_FORCE_PD_S 25 +/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define UART_MEM_FORCE_PU (BIT(26)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001U +#define UART_MEM_FORCE_PU_S 26 + +/** UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64) +/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define UART_RX_TOUT_EN (BIT(0)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001U +#define UART_RX_TOUT_EN_S 0 +/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define UART_RX_TOUT_FLOW_DIS_S 1 +/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define UART_RX_TOUT_THRHD 0x000003FFU +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FFU +#define UART_RX_TOUT_THRHD_S 2 + +/** UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68) +/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define UART_TX_SRAM_WADDR 0x000000FFU +#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) +#define UART_TX_SRAM_WADDR_V 0x000000FFU +#define UART_TX_SRAM_WADDR_S 0 +/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define UART_TX_SRAM_RADDR 0x000000FFU +#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) +#define UART_TX_SRAM_RADDR_V 0x000000FFU +#define UART_TX_SRAM_RADDR_S 9 + +/** UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c) +/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ +#define UART_RX_SRAM_RADDR 0x000000FFU +#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) +#define UART_RX_SRAM_RADDR_V 0x000000FFU +#define UART_RX_SRAM_RADDR_S 0 +/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ +#define UART_RX_SRAM_WADDR 0x000000FFU +#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) +#define UART_RX_SRAM_WADDR_V 0x000000FFU +#define UART_RX_SRAM_WADDR_S 9 + +/** UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70) +/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define UART_ST_URX_OUT 0x0000000FU +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000FU +#define UART_ST_URX_OUT_S 0 +/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define UART_ST_UTX_OUT 0x0000000FU +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000FU +#define UART_ST_UTX_OUT_S 4 + +/** UART_POSPULSE_REG register + * Autobaud high pulse register + */ +#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74) +/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ +#define UART_POSEDGE_MIN_CNT 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x00000FFFU +#define UART_POSEDGE_MIN_CNT_S 0 + +/** UART_NEGPULSE_REG register + * Autobaud low pulse register + */ +#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78) +/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x00000FFFU +#define UART_NEGEDGE_MIN_CNT_S 0 + +/** UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ +#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c) +/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x00000FFFU +#define UART_LOWPULSE_MIN_CNT_S 0 + +/** UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ +#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80) +/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x00000FFFU +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/** UART_RXD_CNT_REG register + * Autobaud edge change count register + */ +#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84) +/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ +#define UART_RXD_EDGE_CNT 0x000003FFU +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FFU +#define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + +/** UART_DATE_REG register + * UART Version register + */ +#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c) +/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848; + * This is the version register. + */ +#define UART_DATE 0xFFFFFFFFU +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFFU +#define UART_DATE_S 0 + +/** UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90) +/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_FULL (BIT(0)) +#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) +#define UART_TX_AFIFO_FULL_V 0x00000001U +#define UART_TX_AFIFO_FULL_S 0 +/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define UART_TX_AFIFO_EMPTY (BIT(1)) +#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) +#define UART_TX_AFIFO_EMPTY_V 0x00000001U +#define UART_TX_AFIFO_EMPTY_S 1 +/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_FULL (BIT(2)) +#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) +#define UART_RX_AFIFO_FULL_V 0x00000001U +#define UART_RX_AFIFO_FULL_S 2 +/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define UART_RX_AFIFO_EMPTY (BIT(3)) +#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) +#define UART_RX_AFIFO_EMPTY_V 0x00000001U +#define UART_RX_AFIFO_EMPTY_S 3 + +/** UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98) +/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define UART_REG_UPDATE (BIT(0)) +#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) +#define UART_REG_UPDATE_V 0x00000001U +#define UART_REG_UPDATE_S 0 + +/** UART_ID_REG register + * UART ID register + */ +#define UART_ID_REG (DR_REG_UART_BASE + 0x9c) +/** UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define UART_ID 0xFFFFFFFFU +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFFU +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uart_struct.h b/components/soc/esp32c5/include/soc/uart_struct.h new file mode 100644 index 0000000000..696e8918a3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/uart_struct.h @@ -0,0 +1,1271 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_parity_err_int_raw:1; + /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * from the echo of transmitter in rs485 mode. + */ + uint32_t rs485_frm_err_int_raw:1; + /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between transmitter + * and receiver in rs485 mode. + */ + uint32_t rs485_clash_int_raw:1; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; + * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is + * set to 1. + */ + uint32_t rs485_parity_err_int_st:1; + /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; + * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set + * to 1. + */ + uint32_t rs485_frm_err_int_st:1; + /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; + * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + */ + uint32_t rs485_clash_int_st:1; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_parity_err_int_ena:1; + /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; + * This is the enable bit for rs485_parity_err_int_st register. + */ + uint32_t rs485_frm_err_int_ena:1; + /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; + * This is the enable bit for rs485_clash_int_st register. + */ + uint32_t rs485_clash_int_ena:1; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the rs485_parity_err_int_raw interrupt. + */ + uint32_t rs485_parity_err_int_clr:1; + /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear the rs485_frm_err_int_raw interrupt. + */ + uint32_t rs485_frm_err_int_clr:1; + /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear the rs485_clash_int_raw interrupt. + */ + uint32_t rs485_clash_int_clr:1; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * a + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + /** irda_dplx : R/W; bitpos: [7]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + uint32_t irda_dplx:1; + /** irda_tx_en : R/W; bitpos: [8]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + uint32_t irda_tx_en:1; + /** irda_wctl : R/W; bitpos: [9]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA + * transmitter's 11th bit to 0. + */ + uint32_t irda_wctl:1; + /** irda_tx_inv : R/W; bitpos: [10]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + uint32_t irda_tx_inv:1; + /** irda_rx_inv : R/W; bitpos: [11]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + uint32_t irda_rx_inv:1; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + /** irda_en : R/W; bitpos: [14]; default: 0; + * Set this bit to enable IrDA protocol. + */ + uint32_t irda_en:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + /** autobaud_en : R/W; bitpos: [19]; default: 0; + * This is the enable bit for detecting baudrate. + */ + uint32_t autobaud_en:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:8; + /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:8; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:8; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:8; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_threshold : R/W; bitpos: [7:0]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:8; + /** xoff_threshold : R/W; bitpos: [15:8]; default: 224; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + /** rs485_en : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the rs485 mode. + */ + uint32_t rs485_en:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter is + * transmitting data in rs485 mode. + */ + uint32_t rs485tx_rx_en:1; + /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; + * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + */ + uint32_t rs485rxby_tx_en:1; + /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + uint32_t rs485_rx_dly_num:1; + /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + uint32_t rs485_tx_dly_num:4; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:8; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + /** txfifo_cnt : RO; bitpos: [23:16]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:8; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:8; + uint32_t reserved_8:1; + /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:8; + uint32_t reserved_8:1; + /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} uart_at_cmd_char_sync_reg_t; + + +/** Group: Autobaud Register */ +/** Type of pospulse register + * Autobaud high pulse register + */ +typedef union { + struct { + /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two positive edges. It + * is used in boudrate-detect process. + */ + uint32_t posedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_pospulse_reg_t; + +/** Type of negpulse register + * Autobaud low pulse register + */ +typedef union { + struct { + /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the minimal input clock count between two negative edges. It + * is used in boudrate-detect process. + */ + uint32_t negedge_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_negpulse_reg_t; + +/** Type of lowpulse register + * Autobaud minimum low pulse duration register + */ +typedef union { + struct { + /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the minimum duration time of the low level pulse. + * It is used in baud rate-detect process. + */ + uint32_t lowpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_lowpulse_reg_t; + +/** Type of highpulse register + * Autobaud minimum high pulse duration register + */ +typedef union { + struct { + /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; + * This register stores the value of the maxinum duration time for the high level + * pulse. It is used in baud rate-detect process. + */ + uint32_t highpulse_min_cnt:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} uart_highpulse_reg_t; + +/** Type of rxd_cnt register + * Autobaud edge change count register + */ +typedef union { + struct { + /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud rate-detect + * process. + */ + uint32_t rxd_edge_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} uart_rxd_cnt_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35680848; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} uart_id_reg_t; + + +typedef struct { + volatile uart_fifo_reg_t fifo; + volatile uart_int_raw_reg_t int_raw; + volatile uart_int_st_reg_t int_st; + volatile uart_int_ena_reg_t int_ena; + volatile uart_int_clr_reg_t int_clr; + volatile uart_clkdiv_sync_reg_t clkdiv_sync; + volatile uart_rx_filt_reg_t rx_filt; + volatile uart_status_reg_t status; + volatile uart_conf0_sync_reg_t conf0_sync; + volatile uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile uart_sleep_conf0_reg_t sleep_conf0; + volatile uart_sleep_conf1_reg_t sleep_conf1; + volatile uart_sleep_conf2_reg_t sleep_conf2; + volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile uart_swfc_conf1_reg_t swfc_conf1; + volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile uart_idle_conf_sync_reg_t idle_conf_sync; + volatile uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile uart_mem_conf_reg_t mem_conf; + volatile uart_tout_conf_sync_reg_t tout_conf_sync; + volatile uart_mem_tx_status_reg_t mem_tx_status; + volatile uart_mem_rx_status_reg_t mem_rx_status; + volatile uart_fsm_status_reg_t fsm_status; + volatile uart_pospulse_reg_t pospulse; + volatile uart_negpulse_reg_t negpulse; + volatile uart_lowpulse_reg_t lowpulse; + volatile uart_highpulse_reg_t highpulse; + volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_clk_conf_reg_t clk_conf; + volatile uart_date_reg_t date; + volatile uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile uart_reg_update_reg_t reg_update; + volatile uart_id_reg_t id; +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; + +#ifndef __cplusplus +_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uhci_reg.h b/components/soc/esp32c5/include/soc/uhci_reg.h new file mode 100644 index 0000000000..af11531832 --- /dev/null +++ b/components/soc/esp32c5/include/soc/uhci_reg.h @@ -0,0 +1,966 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** UHCI_CONF0_REG register + * UHCI Configuration Register0 + */ +#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0) +/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (UHCI_TX_RST_V << UHCI_TX_RST_S) +#define UHCI_TX_RST_V 0x00000001U +#define UHCI_TX_RST_S 0 +/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (UHCI_RX_RST_V << UHCI_RX_RST_S) +#define UHCI_RX_RST_V 0x00000001U +#define UHCI_RX_RST_S 1 +/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7; + * Select which uart to connect with GDMA. + */ +#define UHCI_UART_SEL 0x00000007U +#define UHCI_UART_SEL_M (UHCI_UART_SEL_V << UHCI_UART_SEL_S) +#define UHCI_UART_SEL_V 0x00000007U +#define UHCI_UART_SEL_S 2 +/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S) +#define UHCI_SEPER_EN_V 0x00000001U +#define UHCI_SEPER_EN_S 5 +/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S) +#define UHCI_HEAD_EN_V 0x00000001U +#define UHCI_HEAD_EN_S 6 +/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S) +#define UHCI_CRC_REC_EN_V 0x00000001U +#define UHCI_CRC_REC_EN_S 7 +/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S) +#define UHCI_UART_IDLE_EOF_EN_V 0x00000001U +#define UHCI_UART_IDLE_EOF_EN_S 8 +/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S) +#define UHCI_LEN_EOF_EN_V 0x00000001U +#define UHCI_LEN_EOF_EN_S 9 +/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S) +#define UHCI_ENCODE_CRC_EN_V 0x00000001U +#define UHCI_ENCODE_CRC_EN_S 10 +/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (UHCI_CLK_EN_V << UHCI_CLK_EN_S) +#define UHCI_CLK_EN_V 0x00000001U +#define UHCI_CLK_EN_S 11 +/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x00000001U +#define UHCI_UART_RX_BRK_EOF_EN_S 12 + +/** UHCI_INT_RAW_REG register + * UHCI Interrupt Raw Register + */ +#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4) +/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S) +#define UHCI_RX_START_INT_RAW_V 0x00000001U +#define UHCI_RX_START_INT_RAW_S 0 +/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S) +#define UHCI_TX_START_INT_RAW_V 0x00000001U +#define UHCI_TX_START_INT_RAW_S 1 +/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S) +#define UHCI_RX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_RX_HUNG_INT_RAW_S 2 +/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S) +#define UHCI_TX_HUNG_INT_RAW_V 0x00000001U +#define UHCI_TX_HUNG_INT_RAW_S 3 +/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ +#define UHCI_SEND_S_REG_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_RAW_M (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S) +#define UHCI_SEND_S_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_RAW_S 4 +/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ +#define UHCI_SEND_A_REG_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_RAW_M (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S) +#define UHCI_SEND_A_REG_Q_INT_RAW_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_RAW_S 5 +/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ +#define UHCI_OUT_EOF_INT_RAW (BIT(6)) +#define UHCI_OUT_EOF_INT_RAW_M (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S) +#define UHCI_OUT_EOF_INT_RAW_V 0x00000001U +#define UHCI_OUT_EOF_INT_RAW_S 6 +/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) +#define UHCI_APP_CTRL0_INT_RAW_M (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S) +#define UHCI_APP_CTRL0_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL0_INT_RAW_S 7 +/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ +#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) +#define UHCI_APP_CTRL1_INT_RAW_M (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S) +#define UHCI_APP_CTRL1_INT_RAW_V 0x00000001U +#define UHCI_APP_CTRL1_INT_RAW_S 8 + +/** UHCI_INT_ST_REG register + * UHCI Interrupt Status Register + */ +#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8) +/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S) +#define UHCI_RX_START_INT_ST_V 0x00000001U +#define UHCI_RX_START_INT_ST_S 0 +/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S) +#define UHCI_TX_START_INT_ST_V 0x00000001U +#define UHCI_TX_START_INT_ST_S 1 +/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S) +#define UHCI_RX_HUNG_INT_ST_V 0x00000001U +#define UHCI_RX_HUNG_INT_ST_S 2 +/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S) +#define UHCI_TX_HUNG_INT_ST_V 0x00000001U +#define UHCI_TX_HUNG_INT_ST_S 3 +/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ST_M (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S) +#define UHCI_SEND_S_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ST_S 4 +/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ST_M (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S) +#define UHCI_SEND_A_REG_Q_INT_ST_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ST_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 +/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ST (BIT(7)) +#define UHCI_APP_CTRL0_INT_ST_M (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S) +#define UHCI_APP_CTRL0_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ST_S 7 +/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ST (BIT(8)) +#define UHCI_APP_CTRL1_INT_ST_M (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S) +#define UHCI_APP_CTRL1_INT_ST_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ST_S 8 + +/** UHCI_INT_ENA_REG register + * UHCI Interrupt Enable Register + */ +#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc) +/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S) +#define UHCI_RX_START_INT_ENA_V 0x00000001U +#define UHCI_RX_START_INT_ENA_S 0 +/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S) +#define UHCI_TX_START_INT_ENA_V 0x00000001U +#define UHCI_TX_START_INT_ENA_S 1 +/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S) +#define UHCI_RX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_RX_HUNG_INT_ENA_S 2 +/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S) +#define UHCI_TX_HUNG_INT_ENA_V 0x00000001U +#define UHCI_TX_HUNG_INT_ENA_S 3 +/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_ENA_M (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S) +#define UHCI_SEND_S_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_ENA_S 4 +/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_ENA_M (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S) +#define UHCI_SEND_A_REG_Q_INT_ENA_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_ENA_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S) +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 +/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) +#define UHCI_APP_CTRL0_INT_ENA_M (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S) +#define UHCI_APP_CTRL0_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL0_INT_ENA_S 7 +/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) +#define UHCI_APP_CTRL1_INT_ENA_M (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S) +#define UHCI_APP_CTRL1_INT_ENA_V 0x00000001U +#define UHCI_APP_CTRL1_INT_ENA_S 8 + +/** UHCI_INT_CLR_REG register + * UHCI Interrupt Clear Register + */ +#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10) +/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S) +#define UHCI_RX_START_INT_CLR_V 0x00000001U +#define UHCI_RX_START_INT_CLR_S 0 +/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S) +#define UHCI_TX_START_INT_CLR_V 0x00000001U +#define UHCI_TX_START_INT_CLR_S 1 +/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S) +#define UHCI_RX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_RX_HUNG_INT_CLR_S 2 +/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S) +#define UHCI_TX_HUNG_INT_CLR_V 0x00000001U +#define UHCI_TX_HUNG_INT_CLR_S 3 +/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ +#define UHCI_SEND_S_REG_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_REG_Q_INT_CLR_M (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S) +#define UHCI_SEND_S_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_S_REG_Q_INT_CLR_S 4 +/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ +#define UHCI_SEND_A_REG_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_REG_Q_INT_CLR_M (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S) +#define UHCI_SEND_A_REG_Q_INT_CLR_V 0x00000001U +#define UHCI_SEND_A_REG_Q_INT_CLR_S 5 +/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ +#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S) +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x00000001U +#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 +/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ +#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) +#define UHCI_APP_CTRL0_INT_CLR_M (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S) +#define UHCI_APP_CTRL0_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL0_INT_CLR_S 7 +/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ +#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) +#define UHCI_APP_CTRL1_INT_CLR_M (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S) +#define UHCI_APP_CTRL1_INT_CLR_V 0x00000001U +#define UHCI_APP_CTRL1_INT_CLR_S 8 + +/** UHCI_CONF1_REG register + * UHCI Configuration Register1 + */ +#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14) +/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S) +#define UHCI_CHECK_SUM_EN_V 0x00000001U +#define UHCI_CHECK_SUM_EN_S 0 +/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S) +#define UHCI_CHECK_SEQ_EN_V 0x00000001U +#define UHCI_CHECK_SEQ_EN_S 1 +/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S) +#define UHCI_CRC_DISABLE_V 0x00000001U +#define UHCI_CRC_DISABLE_S 2 +/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S) +#define UHCI_SAVE_HEAD_V 0x00000001U +#define UHCI_SAVE_HEAD_S 3 +/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S) +#define UHCI_TX_CHECK_SUM_RE_V 0x00000001U +#define UHCI_TX_CHECK_SUM_RE_S 4 +/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S) +#define UHCI_TX_ACK_NUM_RE_V 0x00000001U +#define UHCI_TX_ACK_NUM_RE_S 5 +/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S) +#define UHCI_WAIT_SW_START_V 0x00000001U +#define UHCI_WAIT_SW_START_S 7 +/** UHCI_SW_START : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (UHCI_SW_START_V << UHCI_SW_START_S) +#define UHCI_SW_START_V 0x00000001U +#define UHCI_SW_START_S 8 + +/** UHCI_STATE0_REG register + * UHCI Receive Status Register + */ +#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18) +/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ +#define UHCI_RX_ERR_CAUSE 0x00000007U +#define UHCI_RX_ERR_CAUSE_M (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S) +#define UHCI_RX_ERR_CAUSE_V 0x00000007U +#define UHCI_RX_ERR_CAUSE_S 0 +/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ +#define UHCI_DECODE_STATE 0x00000007U +#define UHCI_DECODE_STATE_M (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S) +#define UHCI_DECODE_STATE_V 0x00000007U +#define UHCI_DECODE_STATE_S 3 + +/** UHCI_STATE1_REG register + * UHCI Transmit Status Register + */ +#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c) +/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ +#define UHCI_ENCODE_STATE 0x00000007U +#define UHCI_ENCODE_STATE_M (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S) +#define UHCI_ENCODE_STATE_V 0x00000007U +#define UHCI_ENCODE_STATE_S 0 + +/** UHCI_ESCAPE_CONF_REG register + * UHCI Escapes Configuration Register0 + */ +#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20) +/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S) +#define UHCI_TX_C0_ESC_EN_V 0x00000001U +#define UHCI_TX_C0_ESC_EN_S 0 +/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S) +#define UHCI_TX_DB_ESC_EN_V 0x00000001U +#define UHCI_TX_DB_ESC_EN_S 1 +/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S) +#define UHCI_TX_11_ESC_EN_V 0x00000001U +#define UHCI_TX_11_ESC_EN_S 2 +/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S) +#define UHCI_TX_13_ESC_EN_V 0x00000001U +#define UHCI_TX_13_ESC_EN_S 3 +/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S) +#define UHCI_RX_C0_ESC_EN_V 0x00000001U +#define UHCI_RX_C0_ESC_EN_S 4 +/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S) +#define UHCI_RX_DB_ESC_EN_V 0x00000001U +#define UHCI_RX_DB_ESC_EN_S 5 +/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S) +#define UHCI_RX_11_ESC_EN_V 0x00000001U +#define UHCI_RX_11_ESC_EN_S 6 +/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S) +#define UHCI_RX_13_ESC_EN_V 0x00000001U +#define UHCI_RX_13_ESC_EN_S 7 + +/** UHCI_HUNG_CONF_REG register + * UHCI Hung Configuration Register0 + */ +#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24) +/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_M (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S) +#define UHCI_TXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_TXFIFO_TIMEOUT_S 0 +/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_M (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S) +#define UHCI_RXFIFO_TIMEOUT_V 0x000000FFU +#define UHCI_RXFIFO_TIMEOUT_S 12 +/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x00000007U +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x00000001U +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 + +/** UHCI_ACK_NUM_REG register + * UHCI Ack Value Configuration Register0 + */ +#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28) +/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ +#define UHCI_ACK_NUM 0x00000007U +#define UHCI_ACK_NUM_M (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S) +#define UHCI_ACK_NUM_V 0x00000007U +#define UHCI_ACK_NUM_S 0 +/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ +#define UHCI_ACK_NUM_LOAD (BIT(3)) +#define UHCI_ACK_NUM_LOAD_M (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S) +#define UHCI_ACK_NUM_LOAD_V 0x00000001U +#define UHCI_ACK_NUM_LOAD_S 3 + +/** UHCI_RX_HEAD_REG register + * UHCI Head Register + */ +#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c) +/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ +#define UHCI_RX_HEAD 0xFFFFFFFFU +#define UHCI_RX_HEAD_M (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S) +#define UHCI_RX_HEAD_V 0xFFFFFFFFU +#define UHCI_RX_HEAD_S 0 + +/** UHCI_QUICK_SENT_REG register + * UCHI Quick send Register + */ +#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30) +/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ +#define UHCI_SINGLE_SEND_NUM 0x00000007U +#define UHCI_SINGLE_SEND_NUM_M (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S) +#define UHCI_SINGLE_SEND_NUM_V 0x00000007U +#define UHCI_SINGLE_SEND_NUM_S 0 +/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S) +#define UHCI_SINGLE_SEND_EN_V 0x00000001U +#define UHCI_SINGLE_SEND_EN_S 3 +/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_M (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S) +#define UHCI_ALWAYS_SEND_NUM_V 0x00000007U +#define UHCI_ALWAYS_SEND_NUM_S 4 +/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S) +#define UHCI_ALWAYS_SEND_EN_V 0x00000001U +#define UHCI_ALWAYS_SEND_EN_S 7 + +/** UHCI_REG_Q0_WORD0_REG register + * UHCI Q0_WORD0 Quick Send Register + */ +#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34) +/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_M (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD0_S 0 + +/** UHCI_REG_Q0_WORD1_REG register + * UHCI Q0_WORD1 Quick Send Register + */ +#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38) +/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_M (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q0_WORD1_S 0 + +/** UHCI_REG_Q1_WORD0_REG register + * UHCI Q1_WORD0 Quick Send Register + */ +#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c) +/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_M (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD0_S 0 + +/** UHCI_REG_Q1_WORD1_REG register + * UHCI Q1_WORD1 Quick Send Register + */ +#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40) +/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_M (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q1_WORD1_S 0 + +/** UHCI_REG_Q2_WORD0_REG register + * UHCI Q2_WORD0 Quick Send Register + */ +#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44) +/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_M (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD0_S 0 + +/** UHCI_REG_Q2_WORD1_REG register + * UHCI Q2_WORD1 Quick Send Register + */ +#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48) +/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_M (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q2_WORD1_S 0 + +/** UHCI_REG_Q3_WORD0_REG register + * UHCI Q3_WORD0 Quick Send Register + */ +#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c) +/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_M (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD0_S 0 + +/** UHCI_REG_Q3_WORD1_REG register + * UHCI Q3_WORD1 Quick Send Register + */ +#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50) +/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_M (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q3_WORD1_S 0 + +/** UHCI_REG_Q4_WORD0_REG register + * UHCI Q4_WORD0 Quick Send Register + */ +#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54) +/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_M (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD0_S 0 + +/** UHCI_REG_Q4_WORD1_REG register + * UHCI Q4_WORD1 Quick Send Register + */ +#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58) +/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_M (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q4_WORD1_S 0 + +/** UHCI_REG_Q5_WORD0_REG register + * UHCI Q5_WORD0 Quick Send Register + */ +#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c) +/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_M (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD0_S 0 + +/** UHCI_REG_Q5_WORD1_REG register + * UHCI Q5_WORD1 Quick Send Register + */ +#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60) +/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_M (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q5_WORD1_S 0 + +/** UHCI_REG_Q6_WORD0_REG register + * UHCI Q6_WORD0 Quick Send Register + */ +#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64) +/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_M (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD0_S 0 + +/** UHCI_REG_Q6_WORD1_REG register + * UHCI Q6_WORD1 Quick Send Register + */ +#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68) +/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_M (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFFU +#define UHCI_SEND_Q6_WORD1_S 0 + +/** UHCI_ESC_CONF0_REG register + * UHCI Escapes Sequence Configuration Register0 + */ +#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c) +/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ +#define UHCI_SEPER_CHAR 0x000000FFU +#define UHCI_SEPER_CHAR_M (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S) +#define UHCI_SEPER_CHAR_V 0x000000FFU +#define UHCI_SEPER_CHAR_S 0 +/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_M (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S) +#define UHCI_SEPER_ESC_CHAR0_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR0_S 8 +/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_M (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S) +#define UHCI_SEPER_ESC_CHAR1_V 0x000000FFU +#define UHCI_SEPER_ESC_CHAR1_S 16 + +/** UHCI_ESC_CONF1_REG register + * UHCI Escapes Sequence Configuration Register1 + */ +#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70) +/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ +#define UHCI_ESC_SEQ0 0x000000FFU +#define UHCI_ESC_SEQ0_M (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S) +#define UHCI_ESC_SEQ0_V 0x000000FFU +#define UHCI_ESC_SEQ0_S 0 +/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_M (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S) +#define UHCI_ESC_SEQ0_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_M (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S) +#define UHCI_ESC_SEQ0_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ0_CHAR1_S 16 + +/** UHCI_ESC_CONF2_REG register + * UHCI Escapes Sequence Configuration Register2 + */ +#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74) +/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ +#define UHCI_ESC_SEQ1 0x000000FFU +#define UHCI_ESC_SEQ1_M (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S) +#define UHCI_ESC_SEQ1_V 0x000000FFU +#define UHCI_ESC_SEQ1_S 0 +/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_M (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S) +#define UHCI_ESC_SEQ1_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_M (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S) +#define UHCI_ESC_SEQ1_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ1_CHAR1_S 16 + +/** UHCI_ESC_CONF3_REG register + * UHCI Escapes Sequence Configuration Register3 + */ +#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78) +/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ +#define UHCI_ESC_SEQ2 0x000000FFU +#define UHCI_ESC_SEQ2_M (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S) +#define UHCI_ESC_SEQ2_V 0x000000FFU +#define UHCI_ESC_SEQ2_S 0 +/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_M (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S) +#define UHCI_ESC_SEQ2_CHAR0_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_M (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S) +#define UHCI_ESC_SEQ2_CHAR1_V 0x000000FFU +#define UHCI_ESC_SEQ2_CHAR1_S 16 + +/** UHCI_PKT_THRES_REG register + * UCHI Packet Length Configuration Register + */ +#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c) +/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ +#define UHCI_PKT_THRS 0x00001FFFU +#define UHCI_PKT_THRS_M (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S) +#define UHCI_PKT_THRS_V 0x00001FFFU +#define UHCI_PKT_THRS_S 0 + +/** UHCI_DATE_REG register + * UHCI Version Register + */ +#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80) +/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ +#define UHCI_DATE 0xFFFFFFFFU +#define UHCI_DATE_M (UHCI_DATE_V << UHCI_DATE_S) +#define UHCI_DATE_V 0xFFFFFFFFU +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/uhci_struct.h b/components/soc/esp32c5/include/soc/uhci_struct.h new file mode 100644 index 0000000000..d6b02a72bc --- /dev/null +++ b/components/soc/esp32c5/include/soc/uhci_struct.h @@ -0,0 +1,844 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of conf0 register + * UHCI Configuration Register0 + */ +typedef union { + struct { + /** tx_rst : R/W; bitpos: [0]; default: 0; + * Write 1 then write 0 to this bit to reset decode state machine. + */ + uint32_t tx_rst:1; + /** rx_rst : R/W; bitpos: [1]; default: 0; + * Write 1 then write 0 to this bit to reset encode state machine. + */ + uint32_t rx_rst:1; + /** uart_sel : R/W; bitpos: [4:2]; default: 7; + * Select which uart to connect with GDMA. + */ + uint32_t uart_sel:3; + /** seper_en : R/W; bitpos: [5]; default: 1; + * Set this bit to separate the data frame using a special char. + */ + uint32_t seper_en:1; + /** head_en : R/W; bitpos: [6]; default: 1; + * Set this bit to encode the data packet with a formatting header. + */ + uint32_t head_en:1; + /** crc_rec_en : R/W; bitpos: [7]; default: 1; + * Set this bit to enable UHCI to receive the 16 bit CRC. + */ + uint32_t crc_rec_en:1; + /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; + * If this bit is set to 1 UHCI will end the payload receiving process when UART has + * been in idle state. + */ + uint32_t uart_idle_eof_en:1; + /** len_eof_en : R/W; bitpos: [9]; default: 1; + * If this bit is set to 1 UHCI decoder receiving payload data is end when the + * receiving byte count has reached the specified value. The value is payload length + * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is + * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder + * receiving payload data is end when 0xc0 is received. + */ + uint32_t len_eof_en:1; + /** encode_crc_en : R/W; bitpos: [10]; default: 1; + * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to + * end of the payload. + */ + uint32_t encode_crc_en:1; + /** clk_en : R/W; bitpos: [11]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; + * If this bit is set to 1 UHCI will end payload receive process when NULL frame is + * received by UART. + */ + uint32_t uart_rx_brk_eof_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_conf0_reg_t; + +/** Type of conf1 register + * UHCI Configuration Register1 + */ +typedef union { + struct { + /** check_sum_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable head checksum check when receiving. + */ + uint32_t check_sum_en:1; + /** check_seq_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable sequence number check when receiving. + */ + uint32_t check_seq_en:1; + /** crc_disable : R/W; bitpos: [2]; default: 0; + * Set this bit to support CRC calculation, and data integrity check bit should 1. + */ + uint32_t crc_disable:1; + /** save_head : R/W; bitpos: [3]; default: 0; + * Set this bit to save data packet head when UHCI receive data. + */ + uint32_t save_head:1; + /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; + * Set this bit to encode data packet with checksum. + */ + uint32_t tx_check_sum_re:1; + /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; + * Set this bit to encode data packet with ACK when reliable data packet is ready. + */ + uint32_t tx_ack_num_re:1; + uint32_t reserved_6:1; + /** wait_sw_start : R/W; bitpos: [7]; default: 0; + * Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + */ + uint32_t wait_sw_start:1; + /** sw_start : WT; bitpos: [8]; default: 0; + * Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + */ + uint32_t sw_start:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_conf1_reg_t; + +/** Type of escape_conf register + * UHCI Escapes Configuration Register0 + */ +typedef union { + struct { + /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; + * Set this bit to enable resolve char 0xC0 when DMA receiving data. + */ + uint32_t tx_c0_esc_en:1; + /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; + * Set this bit to enable resolve char 0xDB when DMA receiving data. + */ + uint32_t tx_db_esc_en:1; + /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; + * Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + */ + uint32_t tx_11_esc_en:1; + /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; + * Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + */ + uint32_t tx_13_esc_en:1; + /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; + * Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + */ + uint32_t rx_c0_esc_en:1; + /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; + * Set this bit to enable replacing 0xDB with special char when DMA receiving data. + */ + uint32_t rx_db_esc_en:1; + /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; + * Set this bit to enable replacing 0x11 with special char when DMA receiving data. + */ + uint32_t rx_11_esc_en:1; + /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable replacing 0x13 with special char when DMA receiving data. + */ + uint32_t rx_13_esc_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_escape_conf_reg_t; + +/** Type of hung_conf register + * UHCI Hung Configuration Register0 + */ +typedef union { + struct { + /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving + * data. + */ + uint32_t txfifo_timeout:8; + /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * Configures the maximum counter value. + */ + uint32_t txfifo_timeout_shift:3; + /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * Set this bit to enable TX FIFO timeout when receiving. + */ + uint32_t txfifo_timeout_ena:1; + /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; + * Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading + * RAM data. + */ + uint32_t rxfifo_timeout:8; + /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; + * Configures the maximum counter value. + */ + uint32_t rxfifo_timeout_shift:3; + /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; + * Set this bit to enable TX FIFO timeout when DMA sending data. + */ + uint32_t rxfifo_timeout_ena:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_hung_conf_reg_t; + +/** Type of ack_num register + * UHCI Ack Value Configuration Register0 + */ +typedef union { + struct { + /** ack_num : R/W; bitpos: [2:0]; default: 0; + * Indicates the ACK number during software flow control. + */ + uint32_t ack_num:3; + /** ack_num_load : WT; bitpos: [3]; default: 0; + * Set this bit to load the ACK value of UHCI_ACK_NUM. + */ + uint32_t ack_num_load:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} uhci_ack_num_reg_t; + +/** Type of quick_sent register + * UCHI Quick send Register + */ +typedef union { + struct { + /** single_send_num : R/W; bitpos: [2:0]; default: 0; + * Configures single_send mode. + */ + uint32_t single_send_num:3; + /** single_send_en : WT; bitpos: [3]; default: 0; + * Set this bit to enable sending short packet with single_send mode. + */ + uint32_t single_send_en:1; + /** always_send_num : R/W; bitpos: [6:4]; default: 0; + * Configures always_send mode. + */ + uint32_t always_send_num:3; + /** always_send_en : R/W; bitpos: [7]; default: 0; + * Set this bit to enable sending short packet with always_send mode. + */ + uint32_t always_send_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} uhci_quick_sent_reg_t; + +/** Type of reg_q0_word0 register + * UHCI Q0_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q0_word0:32; + }; + uint32_t val; +} uhci_reg_q0_word0_reg_t; + +/** Type of reg_q0_word1 register + * UHCI Q0_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q0_word1:32; + }; + uint32_t val; +} uhci_reg_q0_word1_reg_t; + +/** Type of reg_q1_word0 register + * UHCI Q1_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q1_word0:32; + }; + uint32_t val; +} uhci_reg_q1_word0_reg_t; + +/** Type of reg_q1_word1 register + * UHCI Q1_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q1_word1:32; + }; + uint32_t val; +} uhci_reg_q1_word1_reg_t; + +/** Type of reg_q2_word0 register + * UHCI Q2_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q2_word0:32; + }; + uint32_t val; +} uhci_reg_q2_word0_reg_t; + +/** Type of reg_q2_word1 register + * UHCI Q2_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q2_word1:32; + }; + uint32_t val; +} uhci_reg_q2_word1_reg_t; + +/** Type of reg_q3_word0 register + * UHCI Q3_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q3_word0:32; + }; + uint32_t val; +} uhci_reg_q3_word0_reg_t; + +/** Type of reg_q3_word1 register + * UHCI Q3_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q3_word1:32; + }; + uint32_t val; +} uhci_reg_q3_word1_reg_t; + +/** Type of reg_q4_word0 register + * UHCI Q4_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q4_word0:32; + }; + uint32_t val; +} uhci_reg_q4_word0_reg_t; + +/** Type of reg_q4_word1 register + * UHCI Q4_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q4_word1:32; + }; + uint32_t val; +} uhci_reg_q4_word1_reg_t; + +/** Type of reg_q5_word0 register + * UHCI Q5_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q5_word0:32; + }; + uint32_t val; +} uhci_reg_q5_word0_reg_t; + +/** Type of reg_q5_word1 register + * UHCI Q5_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q5_word1:32; + }; + uint32_t val; +} uhci_reg_q5_word1_reg_t; + +/** Type of reg_q6_word0 register + * UHCI Q6_WORD0 Quick Send Register + */ +typedef union { + struct { + /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q6_word0:32; + }; + uint32_t val; +} uhci_reg_q6_word0_reg_t; + +/** Type of reg_q6_word1 register + * UHCI Q6_WORD1 Quick Send Register + */ +typedef union { + struct { + /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0; + * Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or + * UHCI_SINGLE_SEND_NUM. + */ + uint32_t send_q6_word1:32; + }; + uint32_t val; +} uhci_reg_q6_word1_reg_t; + +/** Type of esc_conf0 register + * UHCI Escapes Sequence Configuration Register0 + */ +typedef union { + struct { + /** seper_char : R/W; bitpos: [7:0]; default: 192; + * Configures the delimiter for encoding, default value is 0xC0. + */ + uint32_t seper_char:8; + /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t seper_esc_char0:8; + /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; + * Configures the second char of SLIP escape character, default value is 0xDC. + */ + uint32_t seper_esc_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf0_reg_t; + +/** Type of esc_conf1 register + * UHCI Escapes Sequence Configuration Register1 + */ +typedef union { + struct { + /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; + * Configures the char needing encoding, which is 0xDB as flow control char by default. + */ + uint32_t esc_seq0:8; + /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq0_char0:8; + /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; + * Configures the second char of SLIP escape character, default value is 0xDD. + */ + uint32_t esc_seq0_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf1_reg_t; + +/** Type of esc_conf2 register + * UHCI Escapes Sequence Configuration Register2 + */ +typedef union { + struct { + /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; + * Configures the char needing encoding, which is 0x11 as flow control char by default. + */ + uint32_t esc_seq1:8; + /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq1_char0:8; + /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; + * Configures the second char of SLIP escape character, default value is 0xDE. + */ + uint32_t esc_seq1_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf2_reg_t; + +/** Type of esc_conf3 register + * UHCI Escapes Sequence Configuration Register3 + */ +typedef union { + struct { + /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; + * Configures the char needing encoding, which is 0x13 as flow control char by default. + */ + uint32_t esc_seq2:8; + /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; + * Configures the first char of SLIP escape character, default value is 0xDB. + */ + uint32_t esc_seq2_char0:8; + /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; + * Configures the second char of SLIP escape character, default value is 0xDF. + */ + uint32_t esc_seq2_char1:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} uhci_esc_conf3_reg_t; + +/** Type of pkt_thres register + * UCHI Packet Length Configuration Register + */ +typedef union { + struct { + /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; + * Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + */ + uint32_t pkt_thrs:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} uhci_pkt_thres_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * UHCI Interrupt Raw Register + */ +typedef union { + struct { + /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when + * delimiter is sent successfully. + */ + uint32_t rx_start_int_raw:1; + /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when + * DMA detects delimiter. + */ + uint32_t tx_start_int_raw:1; + /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA receiving data exceeds the configuration value. + */ + uint32_t rx_hung_int_raw:1; + /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when + * the required time of DMA reading RAM data exceeds the configuration value. + */ + uint32_t tx_hung_int_raw:1; + /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with single_send mode. + */ + uint32_t send_s_reg_q_int_raw:1; + /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered + * when UHCI sends short packet successfully with always_send mode. + */ + uint32_t send_a_reg_q_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when + * there are errors in EOF. + */ + uint32_t out_eof_int_raw:1; + /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when + * UHCI_APP_CTRL0_IN_SET is set to 1. + */ + uint32_t app_ctrl0_int_raw:1; + /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; + * Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when + * UHCI_APP_CTRL1_IN_SET is set to 1. + */ + uint32_t app_ctrl1_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_raw_reg_t; + +/** Type of int_st register + * UHCI Interrupt Status Register + */ +typedef union { + struct { + /** rx_start_int_st : RO; bitpos: [0]; default: 0; + * Indicates the interrupt status of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_st:1; + /** tx_start_int_st : RO; bitpos: [1]; default: 0; + * Indicates the interrupt status of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_st:1; + /** rx_hung_int_st : RO; bitpos: [2]; default: 0; + * Indicates the interrupt status of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_st:1; + /** tx_hung_int_st : RO; bitpos: [3]; default: 0; + * Indicates the interrupt status of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_st:1; + /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; + * Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_st:1; + /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; + * Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_st:1; + /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; + * Indicates the interrupt status of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_st:1; + /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_st:1; + /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; + * Indicates the interrupt status of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_st_reg_t; + +/** Type of int_ena register + * UHCI Interrupt Enable Register + */ +typedef union { + struct { + /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_ena:1; + /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_ena:1; + /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; + * Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_ena:1; + /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_ena:1; + /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; + * Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_ena:1; + /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_ena:1; + /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_ena:1; + /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; + * Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_ena_reg_t; + +/** Type of int_clr register + * UHCI Interrupt Clear Register + */ +typedef union { + struct { + /** rx_start_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + */ + uint32_t rx_start_int_clr:1; + /** tx_start_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + */ + uint32_t tx_start_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + */ + uint32_t rx_hung_int_clr:1; + /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + */ + uint32_t tx_hung_int_clr:1; + /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + */ + uint32_t send_s_reg_q_int_clr:1; + /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + */ + uint32_t send_a_reg_q_int_clr:1; + /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + */ + uint32_t outlink_eof_err_int_clr:1; + /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + */ + uint32_t app_ctrl0_int_clr:1; + /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + */ + uint32_t app_ctrl1_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} uhci_int_clr_reg_t; + + +/** Group: UHCI Status Register */ +/** Type of state0 register + * UHCI Receive Status Register + */ +typedef union { + struct { + /** rx_err_cause : RO; bitpos: [2:0]; default: 0; + * Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet + * checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC + * bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is + * not found, but received packet is completed. 3'b110: CRC check error. + */ + uint32_t rx_err_cause:3; + /** decode_state : RO; bitpos: [5:3]; default: 0; + * Indicates UHCI decoder status. + */ + uint32_t decode_state:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} uhci_state0_reg_t; + +/** Type of state1 register + * UHCI Transmit Status Register + */ +typedef union { + struct { + /** encode_state : RO; bitpos: [2:0]; default: 0; + * Indicates UHCI encoder status. + */ + uint32_t encode_state:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} uhci_state1_reg_t; + +/** Type of rx_head register + * UHCI Head Register + */ +typedef union { + struct { + /** rx_head : RO; bitpos: [31:0]; default: 0; + * Stores the head of received packet. + */ + uint32_t rx_head:32; + }; + uint32_t val; +} uhci_rx_head_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UHCI Version Register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35655936; + * Configures version. + */ + uint32_t date:32; + }; + uint32_t val; +} uhci_date_reg_t; + + +typedef struct { + volatile uhci_conf0_reg_t conf0; + volatile uhci_int_raw_reg_t int_raw; + volatile uhci_int_st_reg_t int_st; + volatile uhci_int_ena_reg_t int_ena; + volatile uhci_int_clr_reg_t int_clr; + volatile uhci_conf1_reg_t conf1; + volatile uhci_state0_reg_t state0; + volatile uhci_state1_reg_t state1; + volatile uhci_escape_conf_reg_t escape_conf; + volatile uhci_hung_conf_reg_t hung_conf; + volatile uhci_ack_num_reg_t ack_num; + volatile uhci_rx_head_reg_t rx_head; + volatile uhci_quick_sent_reg_t quick_sent; + volatile uhci_reg_q0_word0_reg_t reg_q0_word0; + volatile uhci_reg_q0_word1_reg_t reg_q0_word1; + volatile uhci_reg_q1_word0_reg_t reg_q1_word0; + volatile uhci_reg_q1_word1_reg_t reg_q1_word1; + volatile uhci_reg_q2_word0_reg_t reg_q2_word0; + volatile uhci_reg_q2_word1_reg_t reg_q2_word1; + volatile uhci_reg_q3_word0_reg_t reg_q3_word0; + volatile uhci_reg_q3_word1_reg_t reg_q3_word1; + volatile uhci_reg_q4_word0_reg_t reg_q4_word0; + volatile uhci_reg_q4_word1_reg_t reg_q4_word1; + volatile uhci_reg_q5_word0_reg_t reg_q5_word0; + volatile uhci_reg_q5_word1_reg_t reg_q5_word1; + volatile uhci_reg_q6_word0_reg_t reg_q6_word0; + volatile uhci_reg_q6_word1_reg_t reg_q6_word1; + volatile uhci_esc_conf0_reg_t esc_conf0; + volatile uhci_esc_conf1_reg_t esc_conf1; + volatile uhci_esc_conf2_reg_t esc_conf2; + volatile uhci_esc_conf3_reg_t esc_conf3; + volatile uhci_pkt_thres_reg_t pkt_thres; + volatile uhci_date_reg_t date; +} uhci_dev_t; + +extern uhci_dev_t UHCI0; + +#ifndef __cplusplus +_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld new file mode 100644 index 0000000000..eea6217a66 --- /dev/null +++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C0 = 0x60004000 ); +PROVIDE ( UHCI0 = 0x60005000 ); +PROVIDE ( RMT = 0x60006000 ); +PROVIDE ( RMTMEM = 0x60006400 ); +PROVIDE ( LEDC = 0x60007000 ); +PROVIDE ( TIMERG0 = 0x60008000 ); +PROVIDE ( TIMERG1 = 0x60009000 ); +PROVIDE ( SYSTIMER = 0x6000A000 ); +PROVIDE ( TWAI0 = 0x6000B000 ); +PROVIDE ( I2S0 = 0x6000C000 ); +PROVIDE ( TWAI1 = 0x6000D000 ); +PROVIDE ( APB_SARADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); + +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( ATOMIC_LOCKER = 0x60011000 ); +PROVIDE ( PCNT = 0x60012000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( MCPWM0 = 0x60014000 ); +PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( HINF = 0x60016000 ); +PROVIDE ( SLC = 0x60017000 ); +PROVIDE ( HOST = 0x60018000 ); +PROVIDE ( PVT_MONITOR = 0x60019000 ); + +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); + +PROVIDE ( AES = 0x60088000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( RSA = 0x6008A000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( DS = 0x6008C000 ); +PROVIDE ( HMAC = 0x6008D000 ); + +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091f00 ); +PROVIDE ( SDM = 0x60091f00 ); +PROVIDE ( GLITCH_FILTER = 0x60091f30 ); +PROVIDE ( GPIO_ETM = 0x60091f60 ); + +PROVIDE ( MEM_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); + +PROVIDE ( IEEE802154 = 0x600A3000 ); +PROVIDE ( MODEM_SYSCON = 0x600A9800 ); +PROVIDE ( MODEM_LPCON = 0x600AF000 ); + +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( EFUSE = 0x600B0800 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_UART = 0x600B1400 ); +PROVIDE ( LP_I2C = 0x600B1800 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( LP_IO = 0x600B2000 ); +PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 ); +PROVIDE ( LPPERI = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( OTP_DEBUG = 0x600B3C00 );