change(i2s): update i2s soc and hal for p4 hw_ver3

components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c

@@ -907,10 +907,10 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]")
     TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
     TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
 
-// ESP32-P4 has no PLL except XTAL
+#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP_REV_MIN_FULL >= 300
-#if !CONFIG_IDF_TARGET_ESP32P4
+    std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_PLL_160M;
+#endif
     i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
-#endif  // CONFIG_IDF_TARGET_ESP32P4
 #if SOC_I2S_SUPPORTS_XTAL
     std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_XTAL;
     i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);

components/hal/esp32p4/include/hal/i2s_ll.h

@@ -23,6 +23,7 @@
 #include "soc/soc_etm_source.h"
 #include "hal/i2s_types.h"
 #include "hal/hal_utils.h"
+#include "hal/config.h"
 
 
 #ifdef __cplusplus
@@ -441,6 +442,11 @@ static inline uint32_t i2s_ll_get_clk_src(i2s_clock_src_t src)
             return 1;
         case I2S_CLK_SRC_EXTERNAL:
             return 2;
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+        // Only support PLL_160M on P4 ver3 and later
+        case I2S_CLK_SRC_PLL_160M:
+            return 3;
+#endif
         default:
             HAL_ASSERT(false && "unsupported clock source");
             return -1;
@@ -1195,7 +1201,8 @@ static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t pa
  */
 static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable)
 {
-    hw->tx_pcm2pdm_conf.tx_pdm_hp_bypass = !enable;
+    // Must enable on P4
+    HAL_ASSERT(enable);
 }
 
 /**

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -353,13 +353,14 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL, I2S_CLK_SRC_EXTERNAL}
+#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_APLL, I2S_CLK_SRC_EXTERNAL}
 
 /**
  * @brief I2S clock source enum
  */
 typedef enum {
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,             /*!< Select XTAL as the default source clock  */
+    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,       /*!< Select PLL_F160M as the source clock (only supported on P4 hw_ver3) */
     I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                /*!< Select XTAL as the source clock */
     I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL,                /*!< Select APLL as the source clock */
     I2S_CLK_SRC_EXTERNAL = -1,                          /*!< Select external clock as source clock */

components/soc/esp32p4/register/hw_ver1/soc/i2s_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -282,10 +282,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+        uint32_t reserved_0:1;
-         *  I2S TX PDM bypass hp filter or not. The option has been removed.
-         */
-        uint32_t tx_pdm_hp_bypass:1;
         /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
          *  I2S TX PDM OSR2 value
          */

components/soc/esp32p4/register/hw_ver3/soc/i2s_struct.h

@@ -282,10 +282,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+        uint32_t reserved_0:1;
-         *  I2S TX PDM bypass hp filter or not. The option has been removed.
-         */
-        uint32_t tx_pdm_hp_bypass:1;
         /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
          *  I2S TX PDM OSR2 value
          */