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rmt: simplify rmt source clock configure with clk_tree API

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Also decrease the payload size for testing the multi-channel behaviour.
This commit is contained in:
morris
2023-02-08 17:02:21 +08:00
parent 648b1a41c6
commit 1626766abf
9 changed files with 59 additions and 89 deletions
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21
components/driver/deprecated/rmt_legacy.c
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@@ -21,7 +21,7 @@
#include "soc/soc_memory_layout.h"
#include "soc/rmt_periph.h"
#include "soc/rmt_struct.h"
#include "esp_private/esp_clk.h"
#include "clk_tree.h"
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#include "hal/gpio_hal.h"
@@ -58,16 +58,6 @@ static const char *TAG = "rmt(legacy)";
#define RMT_DECODE_RX_CHANNEL(encode_chan) ((encode_chan - RMT_RX_CHANNEL_ENCODING_START))
#define RMT_ENCODE_RX_CHANNEL(decode_chan) ((decode_chan + RMT_RX_CHANNEL_ENCODING_START))
#if SOC_RMT_SUPPORT_APB
#define RMT_DEFAULT_CLOCK_FREQ esp_clk_apb_freq()
#elif SOC_RMT_SUPPORT_PLL_F80M
#define RMT_DEFAULT_CLOCK_FREQ (80*1000*1000)
#elif SOC_RMT_SUPPORT_XTAL
#define RMT_DEFAULT_CLOCK_FREQ esp_clk_xtal_freq()
#else
#error "RMT unknow default clock"
#endif
typedef struct {
rmt_hal_context_t hal;
_lock_t rmt_driver_isr_lock;
@@ -575,19 +565,20 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
rmt_ll_enable_mem_access_nonfifo(dev, true);
if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
// [clk_tree] TODO: refactor the following code by clk_tree API
#if SOC_RMT_SUPPORT_XTAL
// clock src: XTAL_CLK
rmt_source_clk_hz = esp_clk_xtal_freq();
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_XTAL, 1, 0, 0);
#elif SOC_RMT_SUPPORT_REF_TICK
// clock src: REF_CLK
rmt_source_clk_hz = REF_CLK_FREQ;
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_REF, 1, 0, 0);
#else
#error "No clock source is aware of DFS"
#endif
} else {
// fallback to use default clock source
rmt_source_clk_hz = RMT_DEFAULT_CLOCK_FREQ;
clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz);
rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_DEFAULT, 1, 0, 0);
}
RMT_EXIT_CRITICAL();