From 18420f8d3dbd1c9db521dddefee725106f0bc288 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Wed, 13 Aug 2025 14:03:20 +0800 Subject: [PATCH] feat(h4mp): part1 update compatible soc headers --- .../soc/esp32h4/register/soc/cache_reg.h | 28 +- .../soc/esp32h4/register/soc/cache_struct.h | 25 +- .../soc/esp32h4/register/soc/hp_mem_apm_reg.h | 1402 ++++++++ .../esp32h4/register/soc/hp_mem_apm_struct.h | 578 ++++ .../soc/esp32h4/register/soc/hp_system_reg.h | 53 +- .../esp32h4/register/soc/hp_system_struct.h | 349 +- .../soc/esp32h4/register/soc/lp_aon_reg.h | 79 +- .../soc/esp32h4/register/soc/lp_aon_struct.h | 86 +- .../soc/esp32h4/register/soc/lp_tee_reg.h | 77 +- .../soc/esp32h4/register/soc/lp_tee_struct.h | 616 ++-- .../soc/esp32h4/register/soc/lpperi_reg.h | 16 +- .../soc/esp32h4/register/soc/lpperi_struct.h | 21 +- components/soc/esp32h4/register/soc/pmu_reg.h | 27 +- .../soc/esp32h4/register/soc/pmu_struct_mp.h | 3001 +++++++++++++++++ .../soc/esp32h4/register/soc/spi_mem_c_reg.h | 186 +- .../esp32h4/register/soc/spi_mem_c_struct.h | 34 +- .../soc/esp32h4/register/soc/touch_aon_reg.h | 137 +- .../esp32h4/register/soc/touch_aon_struct.h | 8 +- .../soc/esp32h4/register/soc/touch_reg.h | 28 + .../soc/esp32h4/register/soc/touch_struct.h | 24 +- 20 files changed, 6135 insertions(+), 640 deletions(-) create mode 100644 components/soc/esp32h4/register/soc/hp_mem_apm_reg.h create mode 100644 components/soc/esp32h4/register/soc/hp_mem_apm_struct.h create mode 100644 components/soc/esp32h4/register/soc/pmu_struct_mp.h diff --git a/components/soc/esp32h4/register/soc/cache_reg.h b/components/soc/esp32h4/register/soc/cache_reg.h index 900f2820a5..df662576b0 100644 --- a/components/soc/esp32h4/register/soc/cache_reg.h +++ b/components/soc/esp32h4/register/soc/cache_reg.h @@ -254,7 +254,7 @@ extern "C" { #define CACHE_L1_DCACHE_FREEZE_EN_S 16 /** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; * The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. + * will stuck. 1: a miss-access will not stuck. */ #define CACHE_L1_DCACHE_FREEZE_MODE (BIT(17)) #define CACHE_L1_DCACHE_FREEZE_MODE_M (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S) @@ -810,6 +810,14 @@ extern "C" { #define CACHE_L1_ICACHE0_PRELOAD_RGID_M (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S) #define CACHE_L1_ICACHE0_PRELOAD_RGID_V 0x0000000FU #define CACHE_L1_ICACHE0_PRELOAD_RGID_S 3 +/** CACHE_L1_ICACHE0_PRELOAD_MODE : R/W; bitpos: [7]; default: 0; + * Configures the mode of l1 icache0 preload, 0: load data from next level memory, 1: + * not load data from next level memory. + */ +#define CACHE_L1_ICACHE0_PRELOAD_MODE (BIT(7)) +#define CACHE_L1_ICACHE0_PRELOAD_MODE_M (CACHE_L1_ICACHE0_PRELOAD_MODE_V << CACHE_L1_ICACHE0_PRELOAD_MODE_S) +#define CACHE_L1_ICACHE0_PRELOAD_MODE_V 0x00000001U +#define CACHE_L1_ICACHE0_PRELOAD_MODE_S 7 /** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register * L1 instruction Cache 0 preload address configure register @@ -872,6 +880,14 @@ extern "C" { #define CACHE_L1_ICACHE1_PRELOAD_RGID_M (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S) #define CACHE_L1_ICACHE1_PRELOAD_RGID_V 0x0000000FU #define CACHE_L1_ICACHE1_PRELOAD_RGID_S 3 +/** CACHE_L1_ICACHE1_PRELOAD_MODE : R/W; bitpos: [7]; default: 0; + * Configures the mode of l1 icache1 preload, 0: load data from next level memory, 1: + * not load data from next level memory. + */ +#define CACHE_L1_ICACHE1_PRELOAD_MODE (BIT(7)) +#define CACHE_L1_ICACHE1_PRELOAD_MODE_M (CACHE_L1_ICACHE1_PRELOAD_MODE_V << CACHE_L1_ICACHE1_PRELOAD_MODE_S) +#define CACHE_L1_ICACHE1_PRELOAD_MODE_V 0x00000001U +#define CACHE_L1_ICACHE1_PRELOAD_MODE_S 7 /** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register * L1 instruction Cache 1 preload address configure register @@ -934,6 +950,14 @@ extern "C" { #define CACHE_L1_DCACHE_PRELOAD_RGID_M (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S) #define CACHE_L1_DCACHE_PRELOAD_RGID_V 0x0000000FU #define CACHE_L1_DCACHE_PRELOAD_RGID_S 3 +/** CACHE_L1_DCACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0; + * Configures the mode of l1 dcache preload, 0: load data from next level memory, 1: + * not load data from next level memory. + */ +#define CACHE_L1_DCACHE_PRELOAD_MODE (BIT(7)) +#define CACHE_L1_DCACHE_PRELOAD_MODE_M (CACHE_L1_DCACHE_PRELOAD_MODE_V << CACHE_L1_DCACHE_PRELOAD_MODE_S) +#define CACHE_L1_DCACHE_PRELOAD_MODE_V 0x00000001U +#define CACHE_L1_DCACHE_PRELOAD_MODE_S 7 /** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register * L1 data Cache preload address configure register @@ -2575,7 +2599,7 @@ extern "C" { * Version control register */ #define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) -/** CACHE_DATE : R/W; bitpos: [27:0]; default: 37765696; +/** CACHE_DATE : R/W; bitpos: [27:0]; default: 38810384; * version control register. Note that this default value stored is the latest date * when the hardware logic was updated. */ diff --git a/components/soc/esp32h4/register/soc/cache_struct.h b/components/soc/esp32h4/register/soc/cache_struct.h index 3b567707ed..050ed1c890 100644 --- a/components/soc/esp32h4/register/soc/cache_struct.h +++ b/components/soc/esp32h4/register/soc/cache_struct.h @@ -251,7 +251,7 @@ typedef union { uint32_t l1_dcache_freeze_en:1; /** l1_dcache_freeze_mode : R/W; bitpos: [17]; default: 0; * The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. + * will stuck. 1: a miss-access will not stuck. */ uint32_t l1_dcache_freeze_mode:1; /** l1_dcache_freeze_done : RO; bitpos: [18]; default: 0; @@ -768,7 +768,12 @@ typedef union { * The bit is used to set the gid of l1 icache0 preload. */ uint32_t l1_icache0_preload_rgid:4; - uint32_t reserved_7:25; + /** l1_icache0_preload_mode : R/W; bitpos: [7]; default: 0; + * Configures the mode of l1 icache0 preload, 0: load data from next level memory, 1: + * not load data from next level memory. + */ + uint32_t l1_icache0_preload_mode:1; + uint32_t reserved_8:24; }; uint32_t val; } cache_l1_icache0_preload_ctrl_reg_t; @@ -826,7 +831,12 @@ typedef union { * The bit is used to set the gid of l1 icache1 preload. */ uint32_t l1_icache1_preload_rgid:4; - uint32_t reserved_7:25; + /** l1_icache1_preload_mode : R/W; bitpos: [7]; default: 0; + * Configures the mode of l1 icache1 preload, 0: load data from next level memory, 1: + * not load data from next level memory. + */ + uint32_t l1_icache1_preload_mode:1; + uint32_t reserved_8:24; }; uint32_t val; } cache_l1_icache1_preload_ctrl_reg_t; @@ -884,7 +894,12 @@ typedef union { * The bit is used to set the gid of l1 dcache preload. */ uint32_t l1_dcache_preload_rgid:4; - uint32_t reserved_7:25; + /** l1_dcache_preload_mode : R/W; bitpos: [7]; default: 0; + * Configures the mode of l1 dcache preload, 0: load data from next level memory, 1: + * not load data from next level memory. + */ + uint32_t l1_dcache_preload_mode:1; + uint32_t reserved_8:24; }; uint32_t val; } cache_l1_dcache_preload_ctrl_reg_t; @@ -2415,7 +2430,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37765696; + /** date : R/W; bitpos: [27:0]; default: 38810384; * version control register. Note that this default value stored is the latest date * when the hardware logic was updated. */ diff --git a/components/soc/esp32h4/register/soc/hp_mem_apm_reg.h b/components/soc/esp32h4/register/soc/hp_mem_apm_reg.h new file mode 100644 index 0000000000..75fda335c1 --- /dev/null +++ b/components/soc/esp32h4/register/soc/hp_mem_apm_reg.h @@ -0,0 +1,1402 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_MEM_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define HP_MEM_APM_REGION_FILTER_EN_REG (DR_REG_HP_MEM_APM_BASE + 0x0) +/** HP_MEM_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ +#define HP_MEM_APM_REGION_FILTER_EN 0x000000FFU +#define HP_MEM_APM_REGION_FILTER_EN_M (HP_MEM_APM_REGION_FILTER_EN_V << HP_MEM_APM_REGION_FILTER_EN_S) +#define HP_MEM_APM_REGION_FILTER_EN_V 0x000000FFU +#define HP_MEM_APM_REGION_FILTER_EN_S 0 + +/** HP_MEM_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION0_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x4) +/** HP_MEM_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 0. + */ +#define HP_MEM_APM_REGION0_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION0_ADDR_START_L_M (HP_MEM_APM_REGION0_ADDR_START_L_V << HP_MEM_APM_REGION0_ADDR_START_L_S) +#define HP_MEM_APM_REGION0_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION0_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 0. + */ +#define HP_MEM_APM_REGION0_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION0_ADDR_START_M (HP_MEM_APM_REGION0_ADDR_START_V << HP_MEM_APM_REGION0_ADDR_START_S) +#define HP_MEM_APM_REGION0_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION0_ADDR_START_S 12 +/** HP_MEM_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 0. + */ +#define HP_MEM_APM_REGION0_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION0_ADDR_START_H_M (HP_MEM_APM_REGION0_ADDR_START_H_V << HP_MEM_APM_REGION0_ADDR_START_H_S) +#define HP_MEM_APM_REGION0_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION0_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION0_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x8) +/** HP_MEM_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 0. + */ +#define HP_MEM_APM_REGION0_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION0_ADDR_END_L_M (HP_MEM_APM_REGION0_ADDR_END_L_V << HP_MEM_APM_REGION0_ADDR_END_L_S) +#define HP_MEM_APM_REGION0_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION0_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 0. + */ +#define HP_MEM_APM_REGION0_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION0_ADDR_END_M (HP_MEM_APM_REGION0_ADDR_END_V << HP_MEM_APM_REGION0_ADDR_END_S) +#define HP_MEM_APM_REGION0_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION0_ADDR_END_S 12 +/** HP_MEM_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 0. + */ +#define HP_MEM_APM_REGION0_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION0_ADDR_END_H_M (HP_MEM_APM_REGION0_ADDR_END_H_V << HP_MEM_APM_REGION0_ADDR_END_H_S) +#define HP_MEM_APM_REGION0_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION0_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION0_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0xc) +/** HP_MEM_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define HP_MEM_APM_REGION0_R0_X (BIT(0)) +#define HP_MEM_APM_REGION0_R0_X_M (HP_MEM_APM_REGION0_R0_X_V << HP_MEM_APM_REGION0_R0_X_S) +#define HP_MEM_APM_REGION0_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION0_R0_X_S 0 +/** HP_MEM_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define HP_MEM_APM_REGION0_R0_W (BIT(1)) +#define HP_MEM_APM_REGION0_R0_W_M (HP_MEM_APM_REGION0_R0_W_V << HP_MEM_APM_REGION0_R0_W_S) +#define HP_MEM_APM_REGION0_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION0_R0_W_S 1 +/** HP_MEM_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define HP_MEM_APM_REGION0_R0_R (BIT(2)) +#define HP_MEM_APM_REGION0_R0_R_M (HP_MEM_APM_REGION0_R0_R_V << HP_MEM_APM_REGION0_R0_R_S) +#define HP_MEM_APM_REGION0_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION0_R0_R_S 2 +/** HP_MEM_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define HP_MEM_APM_REGION0_R1_X (BIT(4)) +#define HP_MEM_APM_REGION0_R1_X_M (HP_MEM_APM_REGION0_R1_X_V << HP_MEM_APM_REGION0_R1_X_S) +#define HP_MEM_APM_REGION0_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION0_R1_X_S 4 +/** HP_MEM_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define HP_MEM_APM_REGION0_R1_W (BIT(5)) +#define HP_MEM_APM_REGION0_R1_W_M (HP_MEM_APM_REGION0_R1_W_V << HP_MEM_APM_REGION0_R1_W_S) +#define HP_MEM_APM_REGION0_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION0_R1_W_S 5 +/** HP_MEM_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define HP_MEM_APM_REGION0_R1_R (BIT(6)) +#define HP_MEM_APM_REGION0_R1_R_M (HP_MEM_APM_REGION0_R1_R_V << HP_MEM_APM_REGION0_R1_R_S) +#define HP_MEM_APM_REGION0_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION0_R1_R_S 6 +/** HP_MEM_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define HP_MEM_APM_REGION0_R2_X (BIT(8)) +#define HP_MEM_APM_REGION0_R2_X_M (HP_MEM_APM_REGION0_R2_X_V << HP_MEM_APM_REGION0_R2_X_S) +#define HP_MEM_APM_REGION0_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION0_R2_X_S 8 +/** HP_MEM_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define HP_MEM_APM_REGION0_R2_W (BIT(9)) +#define HP_MEM_APM_REGION0_R2_W_M (HP_MEM_APM_REGION0_R2_W_V << HP_MEM_APM_REGION0_R2_W_S) +#define HP_MEM_APM_REGION0_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION0_R2_W_S 9 +/** HP_MEM_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define HP_MEM_APM_REGION0_R2_R (BIT(10)) +#define HP_MEM_APM_REGION0_R2_R_M (HP_MEM_APM_REGION0_R2_R_V << HP_MEM_APM_REGION0_R2_R_S) +#define HP_MEM_APM_REGION0_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION0_R2_R_S 10 +/** HP_MEM_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION0_LOCK (BIT(11)) +#define HP_MEM_APM_REGION0_LOCK_M (HP_MEM_APM_REGION0_LOCK_V << HP_MEM_APM_REGION0_LOCK_S) +#define HP_MEM_APM_REGION0_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION0_LOCK_S 11 + +/** HP_MEM_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION1_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x10) +/** HP_MEM_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 1. + */ +#define HP_MEM_APM_REGION1_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION1_ADDR_START_L_M (HP_MEM_APM_REGION1_ADDR_START_L_V << HP_MEM_APM_REGION1_ADDR_START_L_S) +#define HP_MEM_APM_REGION1_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION1_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 1. + */ +#define HP_MEM_APM_REGION1_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION1_ADDR_START_M (HP_MEM_APM_REGION1_ADDR_START_V << HP_MEM_APM_REGION1_ADDR_START_S) +#define HP_MEM_APM_REGION1_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION1_ADDR_START_S 12 +/** HP_MEM_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 1. + */ +#define HP_MEM_APM_REGION1_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION1_ADDR_START_H_M (HP_MEM_APM_REGION1_ADDR_START_H_V << HP_MEM_APM_REGION1_ADDR_START_H_S) +#define HP_MEM_APM_REGION1_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION1_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION1_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x14) +/** HP_MEM_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 1. + */ +#define HP_MEM_APM_REGION1_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION1_ADDR_END_L_M (HP_MEM_APM_REGION1_ADDR_END_L_V << HP_MEM_APM_REGION1_ADDR_END_L_S) +#define HP_MEM_APM_REGION1_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION1_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 1. + */ +#define HP_MEM_APM_REGION1_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION1_ADDR_END_M (HP_MEM_APM_REGION1_ADDR_END_V << HP_MEM_APM_REGION1_ADDR_END_S) +#define HP_MEM_APM_REGION1_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION1_ADDR_END_S 12 +/** HP_MEM_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 1. + */ +#define HP_MEM_APM_REGION1_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION1_ADDR_END_H_M (HP_MEM_APM_REGION1_ADDR_END_H_V << HP_MEM_APM_REGION1_ADDR_END_H_S) +#define HP_MEM_APM_REGION1_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION1_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION1_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x18) +/** HP_MEM_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define HP_MEM_APM_REGION1_R0_X (BIT(0)) +#define HP_MEM_APM_REGION1_R0_X_M (HP_MEM_APM_REGION1_R0_X_V << HP_MEM_APM_REGION1_R0_X_S) +#define HP_MEM_APM_REGION1_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION1_R0_X_S 0 +/** HP_MEM_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define HP_MEM_APM_REGION1_R0_W (BIT(1)) +#define HP_MEM_APM_REGION1_R0_W_M (HP_MEM_APM_REGION1_R0_W_V << HP_MEM_APM_REGION1_R0_W_S) +#define HP_MEM_APM_REGION1_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION1_R0_W_S 1 +/** HP_MEM_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define HP_MEM_APM_REGION1_R0_R (BIT(2)) +#define HP_MEM_APM_REGION1_R0_R_M (HP_MEM_APM_REGION1_R0_R_V << HP_MEM_APM_REGION1_R0_R_S) +#define HP_MEM_APM_REGION1_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION1_R0_R_S 2 +/** HP_MEM_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define HP_MEM_APM_REGION1_R1_X (BIT(4)) +#define HP_MEM_APM_REGION1_R1_X_M (HP_MEM_APM_REGION1_R1_X_V << HP_MEM_APM_REGION1_R1_X_S) +#define HP_MEM_APM_REGION1_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION1_R1_X_S 4 +/** HP_MEM_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define HP_MEM_APM_REGION1_R1_W (BIT(5)) +#define HP_MEM_APM_REGION1_R1_W_M (HP_MEM_APM_REGION1_R1_W_V << HP_MEM_APM_REGION1_R1_W_S) +#define HP_MEM_APM_REGION1_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION1_R1_W_S 5 +/** HP_MEM_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define HP_MEM_APM_REGION1_R1_R (BIT(6)) +#define HP_MEM_APM_REGION1_R1_R_M (HP_MEM_APM_REGION1_R1_R_V << HP_MEM_APM_REGION1_R1_R_S) +#define HP_MEM_APM_REGION1_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION1_R1_R_S 6 +/** HP_MEM_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define HP_MEM_APM_REGION1_R2_X (BIT(8)) +#define HP_MEM_APM_REGION1_R2_X_M (HP_MEM_APM_REGION1_R2_X_V << HP_MEM_APM_REGION1_R2_X_S) +#define HP_MEM_APM_REGION1_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION1_R2_X_S 8 +/** HP_MEM_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define HP_MEM_APM_REGION1_R2_W (BIT(9)) +#define HP_MEM_APM_REGION1_R2_W_M (HP_MEM_APM_REGION1_R2_W_V << HP_MEM_APM_REGION1_R2_W_S) +#define HP_MEM_APM_REGION1_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION1_R2_W_S 9 +/** HP_MEM_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define HP_MEM_APM_REGION1_R2_R (BIT(10)) +#define HP_MEM_APM_REGION1_R2_R_M (HP_MEM_APM_REGION1_R2_R_V << HP_MEM_APM_REGION1_R2_R_S) +#define HP_MEM_APM_REGION1_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION1_R2_R_S 10 +/** HP_MEM_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION1_LOCK (BIT(11)) +#define HP_MEM_APM_REGION1_LOCK_M (HP_MEM_APM_REGION1_LOCK_V << HP_MEM_APM_REGION1_LOCK_S) +#define HP_MEM_APM_REGION1_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION1_LOCK_S 11 + +/** HP_MEM_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION2_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x1c) +/** HP_MEM_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 2. + */ +#define HP_MEM_APM_REGION2_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION2_ADDR_START_L_M (HP_MEM_APM_REGION2_ADDR_START_L_V << HP_MEM_APM_REGION2_ADDR_START_L_S) +#define HP_MEM_APM_REGION2_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION2_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 2. + */ +#define HP_MEM_APM_REGION2_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION2_ADDR_START_M (HP_MEM_APM_REGION2_ADDR_START_V << HP_MEM_APM_REGION2_ADDR_START_S) +#define HP_MEM_APM_REGION2_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION2_ADDR_START_S 12 +/** HP_MEM_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 2. + */ +#define HP_MEM_APM_REGION2_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION2_ADDR_START_H_M (HP_MEM_APM_REGION2_ADDR_START_H_V << HP_MEM_APM_REGION2_ADDR_START_H_S) +#define HP_MEM_APM_REGION2_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION2_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION2_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x20) +/** HP_MEM_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 2. + */ +#define HP_MEM_APM_REGION2_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION2_ADDR_END_L_M (HP_MEM_APM_REGION2_ADDR_END_L_V << HP_MEM_APM_REGION2_ADDR_END_L_S) +#define HP_MEM_APM_REGION2_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION2_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 2. + */ +#define HP_MEM_APM_REGION2_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION2_ADDR_END_M (HP_MEM_APM_REGION2_ADDR_END_V << HP_MEM_APM_REGION2_ADDR_END_S) +#define HP_MEM_APM_REGION2_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION2_ADDR_END_S 12 +/** HP_MEM_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 2. + */ +#define HP_MEM_APM_REGION2_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION2_ADDR_END_H_M (HP_MEM_APM_REGION2_ADDR_END_H_V << HP_MEM_APM_REGION2_ADDR_END_H_S) +#define HP_MEM_APM_REGION2_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION2_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION2_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x24) +/** HP_MEM_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define HP_MEM_APM_REGION2_R0_X (BIT(0)) +#define HP_MEM_APM_REGION2_R0_X_M (HP_MEM_APM_REGION2_R0_X_V << HP_MEM_APM_REGION2_R0_X_S) +#define HP_MEM_APM_REGION2_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION2_R0_X_S 0 +/** HP_MEM_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define HP_MEM_APM_REGION2_R0_W (BIT(1)) +#define HP_MEM_APM_REGION2_R0_W_M (HP_MEM_APM_REGION2_R0_W_V << HP_MEM_APM_REGION2_R0_W_S) +#define HP_MEM_APM_REGION2_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION2_R0_W_S 1 +/** HP_MEM_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define HP_MEM_APM_REGION2_R0_R (BIT(2)) +#define HP_MEM_APM_REGION2_R0_R_M (HP_MEM_APM_REGION2_R0_R_V << HP_MEM_APM_REGION2_R0_R_S) +#define HP_MEM_APM_REGION2_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION2_R0_R_S 2 +/** HP_MEM_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define HP_MEM_APM_REGION2_R1_X (BIT(4)) +#define HP_MEM_APM_REGION2_R1_X_M (HP_MEM_APM_REGION2_R1_X_V << HP_MEM_APM_REGION2_R1_X_S) +#define HP_MEM_APM_REGION2_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION2_R1_X_S 4 +/** HP_MEM_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define HP_MEM_APM_REGION2_R1_W (BIT(5)) +#define HP_MEM_APM_REGION2_R1_W_M (HP_MEM_APM_REGION2_R1_W_V << HP_MEM_APM_REGION2_R1_W_S) +#define HP_MEM_APM_REGION2_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION2_R1_W_S 5 +/** HP_MEM_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define HP_MEM_APM_REGION2_R1_R (BIT(6)) +#define HP_MEM_APM_REGION2_R1_R_M (HP_MEM_APM_REGION2_R1_R_V << HP_MEM_APM_REGION2_R1_R_S) +#define HP_MEM_APM_REGION2_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION2_R1_R_S 6 +/** HP_MEM_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define HP_MEM_APM_REGION2_R2_X (BIT(8)) +#define HP_MEM_APM_REGION2_R2_X_M (HP_MEM_APM_REGION2_R2_X_V << HP_MEM_APM_REGION2_R2_X_S) +#define HP_MEM_APM_REGION2_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION2_R2_X_S 8 +/** HP_MEM_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define HP_MEM_APM_REGION2_R2_W (BIT(9)) +#define HP_MEM_APM_REGION2_R2_W_M (HP_MEM_APM_REGION2_R2_W_V << HP_MEM_APM_REGION2_R2_W_S) +#define HP_MEM_APM_REGION2_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION2_R2_W_S 9 +/** HP_MEM_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define HP_MEM_APM_REGION2_R2_R (BIT(10)) +#define HP_MEM_APM_REGION2_R2_R_M (HP_MEM_APM_REGION2_R2_R_V << HP_MEM_APM_REGION2_R2_R_S) +#define HP_MEM_APM_REGION2_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION2_R2_R_S 10 +/** HP_MEM_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION2_LOCK (BIT(11)) +#define HP_MEM_APM_REGION2_LOCK_M (HP_MEM_APM_REGION2_LOCK_V << HP_MEM_APM_REGION2_LOCK_S) +#define HP_MEM_APM_REGION2_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION2_LOCK_S 11 + +/** HP_MEM_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION3_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x28) +/** HP_MEM_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 3. + */ +#define HP_MEM_APM_REGION3_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION3_ADDR_START_L_M (HP_MEM_APM_REGION3_ADDR_START_L_V << HP_MEM_APM_REGION3_ADDR_START_L_S) +#define HP_MEM_APM_REGION3_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION3_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 3. + */ +#define HP_MEM_APM_REGION3_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION3_ADDR_START_M (HP_MEM_APM_REGION3_ADDR_START_V << HP_MEM_APM_REGION3_ADDR_START_S) +#define HP_MEM_APM_REGION3_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION3_ADDR_START_S 12 +/** HP_MEM_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 3. + */ +#define HP_MEM_APM_REGION3_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION3_ADDR_START_H_M (HP_MEM_APM_REGION3_ADDR_START_H_V << HP_MEM_APM_REGION3_ADDR_START_H_S) +#define HP_MEM_APM_REGION3_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION3_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION3_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x2c) +/** HP_MEM_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 3. + */ +#define HP_MEM_APM_REGION3_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION3_ADDR_END_L_M (HP_MEM_APM_REGION3_ADDR_END_L_V << HP_MEM_APM_REGION3_ADDR_END_L_S) +#define HP_MEM_APM_REGION3_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION3_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 3. + */ +#define HP_MEM_APM_REGION3_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION3_ADDR_END_M (HP_MEM_APM_REGION3_ADDR_END_V << HP_MEM_APM_REGION3_ADDR_END_S) +#define HP_MEM_APM_REGION3_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION3_ADDR_END_S 12 +/** HP_MEM_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 3. + */ +#define HP_MEM_APM_REGION3_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION3_ADDR_END_H_M (HP_MEM_APM_REGION3_ADDR_END_H_V << HP_MEM_APM_REGION3_ADDR_END_H_S) +#define HP_MEM_APM_REGION3_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION3_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION3_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x30) +/** HP_MEM_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define HP_MEM_APM_REGION3_R0_X (BIT(0)) +#define HP_MEM_APM_REGION3_R0_X_M (HP_MEM_APM_REGION3_R0_X_V << HP_MEM_APM_REGION3_R0_X_S) +#define HP_MEM_APM_REGION3_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION3_R0_X_S 0 +/** HP_MEM_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define HP_MEM_APM_REGION3_R0_W (BIT(1)) +#define HP_MEM_APM_REGION3_R0_W_M (HP_MEM_APM_REGION3_R0_W_V << HP_MEM_APM_REGION3_R0_W_S) +#define HP_MEM_APM_REGION3_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION3_R0_W_S 1 +/** HP_MEM_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define HP_MEM_APM_REGION3_R0_R (BIT(2)) +#define HP_MEM_APM_REGION3_R0_R_M (HP_MEM_APM_REGION3_R0_R_V << HP_MEM_APM_REGION3_R0_R_S) +#define HP_MEM_APM_REGION3_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION3_R0_R_S 2 +/** HP_MEM_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define HP_MEM_APM_REGION3_R1_X (BIT(4)) +#define HP_MEM_APM_REGION3_R1_X_M (HP_MEM_APM_REGION3_R1_X_V << HP_MEM_APM_REGION3_R1_X_S) +#define HP_MEM_APM_REGION3_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION3_R1_X_S 4 +/** HP_MEM_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define HP_MEM_APM_REGION3_R1_W (BIT(5)) +#define HP_MEM_APM_REGION3_R1_W_M (HP_MEM_APM_REGION3_R1_W_V << HP_MEM_APM_REGION3_R1_W_S) +#define HP_MEM_APM_REGION3_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION3_R1_W_S 5 +/** HP_MEM_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define HP_MEM_APM_REGION3_R1_R (BIT(6)) +#define HP_MEM_APM_REGION3_R1_R_M (HP_MEM_APM_REGION3_R1_R_V << HP_MEM_APM_REGION3_R1_R_S) +#define HP_MEM_APM_REGION3_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION3_R1_R_S 6 +/** HP_MEM_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define HP_MEM_APM_REGION3_R2_X (BIT(8)) +#define HP_MEM_APM_REGION3_R2_X_M (HP_MEM_APM_REGION3_R2_X_V << HP_MEM_APM_REGION3_R2_X_S) +#define HP_MEM_APM_REGION3_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION3_R2_X_S 8 +/** HP_MEM_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define HP_MEM_APM_REGION3_R2_W (BIT(9)) +#define HP_MEM_APM_REGION3_R2_W_M (HP_MEM_APM_REGION3_R2_W_V << HP_MEM_APM_REGION3_R2_W_S) +#define HP_MEM_APM_REGION3_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION3_R2_W_S 9 +/** HP_MEM_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define HP_MEM_APM_REGION3_R2_R (BIT(10)) +#define HP_MEM_APM_REGION3_R2_R_M (HP_MEM_APM_REGION3_R2_R_V << HP_MEM_APM_REGION3_R2_R_S) +#define HP_MEM_APM_REGION3_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION3_R2_R_S 10 +/** HP_MEM_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION3_LOCK (BIT(11)) +#define HP_MEM_APM_REGION3_LOCK_M (HP_MEM_APM_REGION3_LOCK_V << HP_MEM_APM_REGION3_LOCK_S) +#define HP_MEM_APM_REGION3_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION3_LOCK_S 11 + +/** HP_MEM_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION4_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x34) +/** HP_MEM_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 4. + */ +#define HP_MEM_APM_REGION4_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION4_ADDR_START_L_M (HP_MEM_APM_REGION4_ADDR_START_L_V << HP_MEM_APM_REGION4_ADDR_START_L_S) +#define HP_MEM_APM_REGION4_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION4_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 4. + */ +#define HP_MEM_APM_REGION4_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION4_ADDR_START_M (HP_MEM_APM_REGION4_ADDR_START_V << HP_MEM_APM_REGION4_ADDR_START_S) +#define HP_MEM_APM_REGION4_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION4_ADDR_START_S 12 +/** HP_MEM_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 4. + */ +#define HP_MEM_APM_REGION4_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION4_ADDR_START_H_M (HP_MEM_APM_REGION4_ADDR_START_H_V << HP_MEM_APM_REGION4_ADDR_START_H_S) +#define HP_MEM_APM_REGION4_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION4_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION4_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x38) +/** HP_MEM_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 4. + */ +#define HP_MEM_APM_REGION4_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION4_ADDR_END_L_M (HP_MEM_APM_REGION4_ADDR_END_L_V << HP_MEM_APM_REGION4_ADDR_END_L_S) +#define HP_MEM_APM_REGION4_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION4_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 4. + */ +#define HP_MEM_APM_REGION4_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION4_ADDR_END_M (HP_MEM_APM_REGION4_ADDR_END_V << HP_MEM_APM_REGION4_ADDR_END_S) +#define HP_MEM_APM_REGION4_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION4_ADDR_END_S 12 +/** HP_MEM_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 4. + */ +#define HP_MEM_APM_REGION4_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION4_ADDR_END_H_M (HP_MEM_APM_REGION4_ADDR_END_H_V << HP_MEM_APM_REGION4_ADDR_END_H_S) +#define HP_MEM_APM_REGION4_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION4_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION4_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x3c) +/** HP_MEM_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define HP_MEM_APM_REGION4_R0_X (BIT(0)) +#define HP_MEM_APM_REGION4_R0_X_M (HP_MEM_APM_REGION4_R0_X_V << HP_MEM_APM_REGION4_R0_X_S) +#define HP_MEM_APM_REGION4_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION4_R0_X_S 0 +/** HP_MEM_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define HP_MEM_APM_REGION4_R0_W (BIT(1)) +#define HP_MEM_APM_REGION4_R0_W_M (HP_MEM_APM_REGION4_R0_W_V << HP_MEM_APM_REGION4_R0_W_S) +#define HP_MEM_APM_REGION4_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION4_R0_W_S 1 +/** HP_MEM_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define HP_MEM_APM_REGION4_R0_R (BIT(2)) +#define HP_MEM_APM_REGION4_R0_R_M (HP_MEM_APM_REGION4_R0_R_V << HP_MEM_APM_REGION4_R0_R_S) +#define HP_MEM_APM_REGION4_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION4_R0_R_S 2 +/** HP_MEM_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define HP_MEM_APM_REGION4_R1_X (BIT(4)) +#define HP_MEM_APM_REGION4_R1_X_M (HP_MEM_APM_REGION4_R1_X_V << HP_MEM_APM_REGION4_R1_X_S) +#define HP_MEM_APM_REGION4_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION4_R1_X_S 4 +/** HP_MEM_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define HP_MEM_APM_REGION4_R1_W (BIT(5)) +#define HP_MEM_APM_REGION4_R1_W_M (HP_MEM_APM_REGION4_R1_W_V << HP_MEM_APM_REGION4_R1_W_S) +#define HP_MEM_APM_REGION4_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION4_R1_W_S 5 +/** HP_MEM_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define HP_MEM_APM_REGION4_R1_R (BIT(6)) +#define HP_MEM_APM_REGION4_R1_R_M (HP_MEM_APM_REGION4_R1_R_V << HP_MEM_APM_REGION4_R1_R_S) +#define HP_MEM_APM_REGION4_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION4_R1_R_S 6 +/** HP_MEM_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define HP_MEM_APM_REGION4_R2_X (BIT(8)) +#define HP_MEM_APM_REGION4_R2_X_M (HP_MEM_APM_REGION4_R2_X_V << HP_MEM_APM_REGION4_R2_X_S) +#define HP_MEM_APM_REGION4_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION4_R2_X_S 8 +/** HP_MEM_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define HP_MEM_APM_REGION4_R2_W (BIT(9)) +#define HP_MEM_APM_REGION4_R2_W_M (HP_MEM_APM_REGION4_R2_W_V << HP_MEM_APM_REGION4_R2_W_S) +#define HP_MEM_APM_REGION4_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION4_R2_W_S 9 +/** HP_MEM_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define HP_MEM_APM_REGION4_R2_R (BIT(10)) +#define HP_MEM_APM_REGION4_R2_R_M (HP_MEM_APM_REGION4_R2_R_V << HP_MEM_APM_REGION4_R2_R_S) +#define HP_MEM_APM_REGION4_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION4_R2_R_S 10 +/** HP_MEM_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION4_LOCK (BIT(11)) +#define HP_MEM_APM_REGION4_LOCK_M (HP_MEM_APM_REGION4_LOCK_V << HP_MEM_APM_REGION4_LOCK_S) +#define HP_MEM_APM_REGION4_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION4_LOCK_S 11 + +/** HP_MEM_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION5_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x40) +/** HP_MEM_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 5. + */ +#define HP_MEM_APM_REGION5_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION5_ADDR_START_L_M (HP_MEM_APM_REGION5_ADDR_START_L_V << HP_MEM_APM_REGION5_ADDR_START_L_S) +#define HP_MEM_APM_REGION5_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION5_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 5. + */ +#define HP_MEM_APM_REGION5_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION5_ADDR_START_M (HP_MEM_APM_REGION5_ADDR_START_V << HP_MEM_APM_REGION5_ADDR_START_S) +#define HP_MEM_APM_REGION5_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION5_ADDR_START_S 12 +/** HP_MEM_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 5. + */ +#define HP_MEM_APM_REGION5_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION5_ADDR_START_H_M (HP_MEM_APM_REGION5_ADDR_START_H_V << HP_MEM_APM_REGION5_ADDR_START_H_S) +#define HP_MEM_APM_REGION5_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION5_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION5_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x44) +/** HP_MEM_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 5. + */ +#define HP_MEM_APM_REGION5_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION5_ADDR_END_L_M (HP_MEM_APM_REGION5_ADDR_END_L_V << HP_MEM_APM_REGION5_ADDR_END_L_S) +#define HP_MEM_APM_REGION5_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION5_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 5. + */ +#define HP_MEM_APM_REGION5_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION5_ADDR_END_M (HP_MEM_APM_REGION5_ADDR_END_V << HP_MEM_APM_REGION5_ADDR_END_S) +#define HP_MEM_APM_REGION5_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION5_ADDR_END_S 12 +/** HP_MEM_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 5. + */ +#define HP_MEM_APM_REGION5_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION5_ADDR_END_H_M (HP_MEM_APM_REGION5_ADDR_END_H_V << HP_MEM_APM_REGION5_ADDR_END_H_S) +#define HP_MEM_APM_REGION5_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION5_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION5_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x48) +/** HP_MEM_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define HP_MEM_APM_REGION5_R0_X (BIT(0)) +#define HP_MEM_APM_REGION5_R0_X_M (HP_MEM_APM_REGION5_R0_X_V << HP_MEM_APM_REGION5_R0_X_S) +#define HP_MEM_APM_REGION5_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION5_R0_X_S 0 +/** HP_MEM_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define HP_MEM_APM_REGION5_R0_W (BIT(1)) +#define HP_MEM_APM_REGION5_R0_W_M (HP_MEM_APM_REGION5_R0_W_V << HP_MEM_APM_REGION5_R0_W_S) +#define HP_MEM_APM_REGION5_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION5_R0_W_S 1 +/** HP_MEM_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define HP_MEM_APM_REGION5_R0_R (BIT(2)) +#define HP_MEM_APM_REGION5_R0_R_M (HP_MEM_APM_REGION5_R0_R_V << HP_MEM_APM_REGION5_R0_R_S) +#define HP_MEM_APM_REGION5_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION5_R0_R_S 2 +/** HP_MEM_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define HP_MEM_APM_REGION5_R1_X (BIT(4)) +#define HP_MEM_APM_REGION5_R1_X_M (HP_MEM_APM_REGION5_R1_X_V << HP_MEM_APM_REGION5_R1_X_S) +#define HP_MEM_APM_REGION5_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION5_R1_X_S 4 +/** HP_MEM_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define HP_MEM_APM_REGION5_R1_W (BIT(5)) +#define HP_MEM_APM_REGION5_R1_W_M (HP_MEM_APM_REGION5_R1_W_V << HP_MEM_APM_REGION5_R1_W_S) +#define HP_MEM_APM_REGION5_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION5_R1_W_S 5 +/** HP_MEM_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define HP_MEM_APM_REGION5_R1_R (BIT(6)) +#define HP_MEM_APM_REGION5_R1_R_M (HP_MEM_APM_REGION5_R1_R_V << HP_MEM_APM_REGION5_R1_R_S) +#define HP_MEM_APM_REGION5_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION5_R1_R_S 6 +/** HP_MEM_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define HP_MEM_APM_REGION5_R2_X (BIT(8)) +#define HP_MEM_APM_REGION5_R2_X_M (HP_MEM_APM_REGION5_R2_X_V << HP_MEM_APM_REGION5_R2_X_S) +#define HP_MEM_APM_REGION5_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION5_R2_X_S 8 +/** HP_MEM_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define HP_MEM_APM_REGION5_R2_W (BIT(9)) +#define HP_MEM_APM_REGION5_R2_W_M (HP_MEM_APM_REGION5_R2_W_V << HP_MEM_APM_REGION5_R2_W_S) +#define HP_MEM_APM_REGION5_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION5_R2_W_S 9 +/** HP_MEM_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define HP_MEM_APM_REGION5_R2_R (BIT(10)) +#define HP_MEM_APM_REGION5_R2_R_M (HP_MEM_APM_REGION5_R2_R_V << HP_MEM_APM_REGION5_R2_R_S) +#define HP_MEM_APM_REGION5_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION5_R2_R_S 10 +/** HP_MEM_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION5_LOCK (BIT(11)) +#define HP_MEM_APM_REGION5_LOCK_M (HP_MEM_APM_REGION5_LOCK_V << HP_MEM_APM_REGION5_LOCK_S) +#define HP_MEM_APM_REGION5_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION5_LOCK_S 11 + +/** HP_MEM_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION6_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x4c) +/** HP_MEM_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 6. + */ +#define HP_MEM_APM_REGION6_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION6_ADDR_START_L_M (HP_MEM_APM_REGION6_ADDR_START_L_V << HP_MEM_APM_REGION6_ADDR_START_L_S) +#define HP_MEM_APM_REGION6_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION6_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 6. + */ +#define HP_MEM_APM_REGION6_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION6_ADDR_START_M (HP_MEM_APM_REGION6_ADDR_START_V << HP_MEM_APM_REGION6_ADDR_START_S) +#define HP_MEM_APM_REGION6_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION6_ADDR_START_S 12 +/** HP_MEM_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 6. + */ +#define HP_MEM_APM_REGION6_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION6_ADDR_START_H_M (HP_MEM_APM_REGION6_ADDR_START_H_V << HP_MEM_APM_REGION6_ADDR_START_H_S) +#define HP_MEM_APM_REGION6_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION6_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION6_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x50) +/** HP_MEM_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 6. + */ +#define HP_MEM_APM_REGION6_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION6_ADDR_END_L_M (HP_MEM_APM_REGION6_ADDR_END_L_V << HP_MEM_APM_REGION6_ADDR_END_L_S) +#define HP_MEM_APM_REGION6_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION6_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 6. + */ +#define HP_MEM_APM_REGION6_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION6_ADDR_END_M (HP_MEM_APM_REGION6_ADDR_END_V << HP_MEM_APM_REGION6_ADDR_END_S) +#define HP_MEM_APM_REGION6_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION6_ADDR_END_S 12 +/** HP_MEM_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 6. + */ +#define HP_MEM_APM_REGION6_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION6_ADDR_END_H_M (HP_MEM_APM_REGION6_ADDR_END_H_V << HP_MEM_APM_REGION6_ADDR_END_H_S) +#define HP_MEM_APM_REGION6_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION6_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION6_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x54) +/** HP_MEM_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define HP_MEM_APM_REGION6_R0_X (BIT(0)) +#define HP_MEM_APM_REGION6_R0_X_M (HP_MEM_APM_REGION6_R0_X_V << HP_MEM_APM_REGION6_R0_X_S) +#define HP_MEM_APM_REGION6_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION6_R0_X_S 0 +/** HP_MEM_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define HP_MEM_APM_REGION6_R0_W (BIT(1)) +#define HP_MEM_APM_REGION6_R0_W_M (HP_MEM_APM_REGION6_R0_W_V << HP_MEM_APM_REGION6_R0_W_S) +#define HP_MEM_APM_REGION6_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION6_R0_W_S 1 +/** HP_MEM_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define HP_MEM_APM_REGION6_R0_R (BIT(2)) +#define HP_MEM_APM_REGION6_R0_R_M (HP_MEM_APM_REGION6_R0_R_V << HP_MEM_APM_REGION6_R0_R_S) +#define HP_MEM_APM_REGION6_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION6_R0_R_S 2 +/** HP_MEM_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define HP_MEM_APM_REGION6_R1_X (BIT(4)) +#define HP_MEM_APM_REGION6_R1_X_M (HP_MEM_APM_REGION6_R1_X_V << HP_MEM_APM_REGION6_R1_X_S) +#define HP_MEM_APM_REGION6_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION6_R1_X_S 4 +/** HP_MEM_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define HP_MEM_APM_REGION6_R1_W (BIT(5)) +#define HP_MEM_APM_REGION6_R1_W_M (HP_MEM_APM_REGION6_R1_W_V << HP_MEM_APM_REGION6_R1_W_S) +#define HP_MEM_APM_REGION6_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION6_R1_W_S 5 +/** HP_MEM_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define HP_MEM_APM_REGION6_R1_R (BIT(6)) +#define HP_MEM_APM_REGION6_R1_R_M (HP_MEM_APM_REGION6_R1_R_V << HP_MEM_APM_REGION6_R1_R_S) +#define HP_MEM_APM_REGION6_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION6_R1_R_S 6 +/** HP_MEM_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define HP_MEM_APM_REGION6_R2_X (BIT(8)) +#define HP_MEM_APM_REGION6_R2_X_M (HP_MEM_APM_REGION6_R2_X_V << HP_MEM_APM_REGION6_R2_X_S) +#define HP_MEM_APM_REGION6_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION6_R2_X_S 8 +/** HP_MEM_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define HP_MEM_APM_REGION6_R2_W (BIT(9)) +#define HP_MEM_APM_REGION6_R2_W_M (HP_MEM_APM_REGION6_R2_W_V << HP_MEM_APM_REGION6_R2_W_S) +#define HP_MEM_APM_REGION6_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION6_R2_W_S 9 +/** HP_MEM_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define HP_MEM_APM_REGION6_R2_R (BIT(10)) +#define HP_MEM_APM_REGION6_R2_R_M (HP_MEM_APM_REGION6_R2_R_V << HP_MEM_APM_REGION6_R2_R_S) +#define HP_MEM_APM_REGION6_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION6_R2_R_S 10 +/** HP_MEM_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION6_LOCK (BIT(11)) +#define HP_MEM_APM_REGION6_LOCK_M (HP_MEM_APM_REGION6_LOCK_V << HP_MEM_APM_REGION6_LOCK_S) +#define HP_MEM_APM_REGION6_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION6_LOCK_S 11 + +/** HP_MEM_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define HP_MEM_APM_REGION7_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x58) +/** HP_MEM_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 7. + */ +#define HP_MEM_APM_REGION7_ADDR_START_L 0x00000FFFU +#define HP_MEM_APM_REGION7_ADDR_START_L_M (HP_MEM_APM_REGION7_ADDR_START_L_V << HP_MEM_APM_REGION7_ADDR_START_L_S) +#define HP_MEM_APM_REGION7_ADDR_START_L_V 0x00000FFFU +#define HP_MEM_APM_REGION7_ADDR_START_L_S 0 +/** HP_MEM_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 7. + */ +#define HP_MEM_APM_REGION7_ADDR_START 0x0000007FU +#define HP_MEM_APM_REGION7_ADDR_START_M (HP_MEM_APM_REGION7_ADDR_START_V << HP_MEM_APM_REGION7_ADDR_START_S) +#define HP_MEM_APM_REGION7_ADDR_START_V 0x0000007FU +#define HP_MEM_APM_REGION7_ADDR_START_S 12 +/** HP_MEM_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 7. + */ +#define HP_MEM_APM_REGION7_ADDR_START_H 0x00001FFFU +#define HP_MEM_APM_REGION7_ADDR_START_H_M (HP_MEM_APM_REGION7_ADDR_START_H_V << HP_MEM_APM_REGION7_ADDR_START_H_S) +#define HP_MEM_APM_REGION7_ADDR_START_H_V 0x00001FFFU +#define HP_MEM_APM_REGION7_ADDR_START_H_S 19 + +/** HP_MEM_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define HP_MEM_APM_REGION7_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x5c) +/** HP_MEM_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 7. + */ +#define HP_MEM_APM_REGION7_ADDR_END_L 0x00000FFFU +#define HP_MEM_APM_REGION7_ADDR_END_L_M (HP_MEM_APM_REGION7_ADDR_END_L_V << HP_MEM_APM_REGION7_ADDR_END_L_S) +#define HP_MEM_APM_REGION7_ADDR_END_L_V 0x00000FFFU +#define HP_MEM_APM_REGION7_ADDR_END_L_S 0 +/** HP_MEM_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 7. + */ +#define HP_MEM_APM_REGION7_ADDR_END 0x0000007FU +#define HP_MEM_APM_REGION7_ADDR_END_M (HP_MEM_APM_REGION7_ADDR_END_V << HP_MEM_APM_REGION7_ADDR_END_S) +#define HP_MEM_APM_REGION7_ADDR_END_V 0x0000007FU +#define HP_MEM_APM_REGION7_ADDR_END_S 12 +/** HP_MEM_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 7. + */ +#define HP_MEM_APM_REGION7_ADDR_END_H 0x00001FFFU +#define HP_MEM_APM_REGION7_ADDR_END_H_M (HP_MEM_APM_REGION7_ADDR_END_H_V << HP_MEM_APM_REGION7_ADDR_END_H_S) +#define HP_MEM_APM_REGION7_ADDR_END_H_V 0x00001FFFU +#define HP_MEM_APM_REGION7_ADDR_END_H_S 19 + +/** HP_MEM_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define HP_MEM_APM_REGION7_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x60) +/** HP_MEM_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define HP_MEM_APM_REGION7_R0_X (BIT(0)) +#define HP_MEM_APM_REGION7_R0_X_M (HP_MEM_APM_REGION7_R0_X_V << HP_MEM_APM_REGION7_R0_X_S) +#define HP_MEM_APM_REGION7_R0_X_V 0x00000001U +#define HP_MEM_APM_REGION7_R0_X_S 0 +/** HP_MEM_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define HP_MEM_APM_REGION7_R0_W (BIT(1)) +#define HP_MEM_APM_REGION7_R0_W_M (HP_MEM_APM_REGION7_R0_W_V << HP_MEM_APM_REGION7_R0_W_S) +#define HP_MEM_APM_REGION7_R0_W_V 0x00000001U +#define HP_MEM_APM_REGION7_R0_W_S 1 +/** HP_MEM_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define HP_MEM_APM_REGION7_R0_R (BIT(2)) +#define HP_MEM_APM_REGION7_R0_R_M (HP_MEM_APM_REGION7_R0_R_V << HP_MEM_APM_REGION7_R0_R_S) +#define HP_MEM_APM_REGION7_R0_R_V 0x00000001U +#define HP_MEM_APM_REGION7_R0_R_S 2 +/** HP_MEM_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define HP_MEM_APM_REGION7_R1_X (BIT(4)) +#define HP_MEM_APM_REGION7_R1_X_M (HP_MEM_APM_REGION7_R1_X_V << HP_MEM_APM_REGION7_R1_X_S) +#define HP_MEM_APM_REGION7_R1_X_V 0x00000001U +#define HP_MEM_APM_REGION7_R1_X_S 4 +/** HP_MEM_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define HP_MEM_APM_REGION7_R1_W (BIT(5)) +#define HP_MEM_APM_REGION7_R1_W_M (HP_MEM_APM_REGION7_R1_W_V << HP_MEM_APM_REGION7_R1_W_S) +#define HP_MEM_APM_REGION7_R1_W_V 0x00000001U +#define HP_MEM_APM_REGION7_R1_W_S 5 +/** HP_MEM_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define HP_MEM_APM_REGION7_R1_R (BIT(6)) +#define HP_MEM_APM_REGION7_R1_R_M (HP_MEM_APM_REGION7_R1_R_V << HP_MEM_APM_REGION7_R1_R_S) +#define HP_MEM_APM_REGION7_R1_R_V 0x00000001U +#define HP_MEM_APM_REGION7_R1_R_S 6 +/** HP_MEM_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define HP_MEM_APM_REGION7_R2_X (BIT(8)) +#define HP_MEM_APM_REGION7_R2_X_M (HP_MEM_APM_REGION7_R2_X_V << HP_MEM_APM_REGION7_R2_X_S) +#define HP_MEM_APM_REGION7_R2_X_V 0x00000001U +#define HP_MEM_APM_REGION7_R2_X_S 8 +/** HP_MEM_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define HP_MEM_APM_REGION7_R2_W (BIT(9)) +#define HP_MEM_APM_REGION7_R2_W_M (HP_MEM_APM_REGION7_R2_W_V << HP_MEM_APM_REGION7_R2_W_S) +#define HP_MEM_APM_REGION7_R2_W_V 0x00000001U +#define HP_MEM_APM_REGION7_R2_W_S 9 +/** HP_MEM_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define HP_MEM_APM_REGION7_R2_R (BIT(10)) +#define HP_MEM_APM_REGION7_R2_R_M (HP_MEM_APM_REGION7_R2_R_V << HP_MEM_APM_REGION7_R2_R_S) +#define HP_MEM_APM_REGION7_R2_R_V 0x00000001U +#define HP_MEM_APM_REGION7_R2_R_S 10 +/** HP_MEM_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_MEM_APM_REGION7_LOCK (BIT(11)) +#define HP_MEM_APM_REGION7_LOCK_M (HP_MEM_APM_REGION7_LOCK_V << HP_MEM_APM_REGION7_LOCK_S) +#define HP_MEM_APM_REGION7_LOCK_V 0x00000001U +#define HP_MEM_APM_REGION7_LOCK_S 11 + +/** HP_MEM_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define HP_MEM_APM_FUNC_CTRL_REG (DR_REG_HP_MEM_APM_BASE + 0xc4) +/** HP_MEM_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define HP_MEM_APM_M0_FUNC_EN (BIT(0)) +#define HP_MEM_APM_M0_FUNC_EN_M (HP_MEM_APM_M0_FUNC_EN_V << HP_MEM_APM_M0_FUNC_EN_S) +#define HP_MEM_APM_M0_FUNC_EN_V 0x00000001U +#define HP_MEM_APM_M0_FUNC_EN_S 0 +/** HP_MEM_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define HP_MEM_APM_M1_FUNC_EN (BIT(1)) +#define HP_MEM_APM_M1_FUNC_EN_M (HP_MEM_APM_M1_FUNC_EN_V << HP_MEM_APM_M1_FUNC_EN_S) +#define HP_MEM_APM_M1_FUNC_EN_V 0x00000001U +#define HP_MEM_APM_M1_FUNC_EN_S 1 +/** HP_MEM_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define HP_MEM_APM_M2_FUNC_EN (BIT(2)) +#define HP_MEM_APM_M2_FUNC_EN_M (HP_MEM_APM_M2_FUNC_EN_V << HP_MEM_APM_M2_FUNC_EN_S) +#define HP_MEM_APM_M2_FUNC_EN_V 0x00000001U +#define HP_MEM_APM_M2_FUNC_EN_S 2 +/** HP_MEM_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define HP_MEM_APM_M3_FUNC_EN (BIT(3)) +#define HP_MEM_APM_M3_FUNC_EN_M (HP_MEM_APM_M3_FUNC_EN_V << HP_MEM_APM_M3_FUNC_EN_S) +#define HP_MEM_APM_M3_FUNC_EN_V 0x00000001U +#define HP_MEM_APM_M3_FUNC_EN_S 3 + +/** HP_MEM_APM_M0_STATUS_REG register + * M0 status register + */ +#define HP_MEM_APM_M0_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xc8) +/** HP_MEM_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define HP_MEM_APM_M0_EXCEPTION_STATUS 0x00000003U +#define HP_MEM_APM_M0_EXCEPTION_STATUS_M (HP_MEM_APM_M0_EXCEPTION_STATUS_V << HP_MEM_APM_M0_EXCEPTION_STATUS_S) +#define HP_MEM_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define HP_MEM_APM_M0_EXCEPTION_STATUS_S 0 + +/** HP_MEM_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define HP_MEM_APM_M0_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xcc) +/** HP_MEM_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_M (HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_S) +#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** HP_MEM_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define HP_MEM_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0xd0) +/** HP_MEM_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_MEM_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define HP_MEM_APM_M0_EXCEPTION_REGION_M (HP_MEM_APM_M0_EXCEPTION_REGION_V << HP_MEM_APM_M0_EXCEPTION_REGION_S) +#define HP_MEM_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_MEM_APM_M0_EXCEPTION_REGION_S 0 +/** HP_MEM_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_MEM_APM_M0_EXCEPTION_MODE 0x00000003U +#define HP_MEM_APM_M0_EXCEPTION_MODE_M (HP_MEM_APM_M0_EXCEPTION_MODE_V << HP_MEM_APM_M0_EXCEPTION_MODE_S) +#define HP_MEM_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define HP_MEM_APM_M0_EXCEPTION_MODE_S 16 +/** HP_MEM_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_MEM_APM_M0_EXCEPTION_ID 0x0000001FU +#define HP_MEM_APM_M0_EXCEPTION_ID_M (HP_MEM_APM_M0_EXCEPTION_ID_V << HP_MEM_APM_M0_EXCEPTION_ID_S) +#define HP_MEM_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define HP_MEM_APM_M0_EXCEPTION_ID_S 18 + +/** HP_MEM_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define HP_MEM_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0xd4) +/** HP_MEM_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_MEM_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_MEM_APM_M0_EXCEPTION_ADDR_M (HP_MEM_APM_M0_EXCEPTION_ADDR_V << HP_MEM_APM_M0_EXCEPTION_ADDR_S) +#define HP_MEM_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_MEM_APM_M0_EXCEPTION_ADDR_S 0 + +/** HP_MEM_APM_M1_STATUS_REG register + * M1 status register + */ +#define HP_MEM_APM_M1_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xd8) +/** HP_MEM_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define HP_MEM_APM_M1_EXCEPTION_STATUS 0x00000003U +#define HP_MEM_APM_M1_EXCEPTION_STATUS_M (HP_MEM_APM_M1_EXCEPTION_STATUS_V << HP_MEM_APM_M1_EXCEPTION_STATUS_S) +#define HP_MEM_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define HP_MEM_APM_M1_EXCEPTION_STATUS_S 0 + +/** HP_MEM_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define HP_MEM_APM_M1_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xdc) +/** HP_MEM_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_M (HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_S) +#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_S 0 + +/** HP_MEM_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define HP_MEM_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0xe0) +/** HP_MEM_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_MEM_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define HP_MEM_APM_M1_EXCEPTION_REGION_M (HP_MEM_APM_M1_EXCEPTION_REGION_V << HP_MEM_APM_M1_EXCEPTION_REGION_S) +#define HP_MEM_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_MEM_APM_M1_EXCEPTION_REGION_S 0 +/** HP_MEM_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_MEM_APM_M1_EXCEPTION_MODE 0x00000003U +#define HP_MEM_APM_M1_EXCEPTION_MODE_M (HP_MEM_APM_M1_EXCEPTION_MODE_V << HP_MEM_APM_M1_EXCEPTION_MODE_S) +#define HP_MEM_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define HP_MEM_APM_M1_EXCEPTION_MODE_S 16 +/** HP_MEM_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_MEM_APM_M1_EXCEPTION_ID 0x0000001FU +#define HP_MEM_APM_M1_EXCEPTION_ID_M (HP_MEM_APM_M1_EXCEPTION_ID_V << HP_MEM_APM_M1_EXCEPTION_ID_S) +#define HP_MEM_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define HP_MEM_APM_M1_EXCEPTION_ID_S 18 + +/** HP_MEM_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define HP_MEM_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0xe4) +/** HP_MEM_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_MEM_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_MEM_APM_M1_EXCEPTION_ADDR_M (HP_MEM_APM_M1_EXCEPTION_ADDR_V << HP_MEM_APM_M1_EXCEPTION_ADDR_S) +#define HP_MEM_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_MEM_APM_M1_EXCEPTION_ADDR_S 0 + +/** HP_MEM_APM_M2_STATUS_REG register + * M2 status register + */ +#define HP_MEM_APM_M2_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xe8) +/** HP_MEM_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define HP_MEM_APM_M2_EXCEPTION_STATUS 0x00000003U +#define HP_MEM_APM_M2_EXCEPTION_STATUS_M (HP_MEM_APM_M2_EXCEPTION_STATUS_V << HP_MEM_APM_M2_EXCEPTION_STATUS_S) +#define HP_MEM_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define HP_MEM_APM_M2_EXCEPTION_STATUS_S 0 + +/** HP_MEM_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define HP_MEM_APM_M2_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xec) +/** HP_MEM_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_M (HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_S) +#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_S 0 + +/** HP_MEM_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define HP_MEM_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0xf0) +/** HP_MEM_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_MEM_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define HP_MEM_APM_M2_EXCEPTION_REGION_M (HP_MEM_APM_M2_EXCEPTION_REGION_V << HP_MEM_APM_M2_EXCEPTION_REGION_S) +#define HP_MEM_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_MEM_APM_M2_EXCEPTION_REGION_S 0 +/** HP_MEM_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_MEM_APM_M2_EXCEPTION_MODE 0x00000003U +#define HP_MEM_APM_M2_EXCEPTION_MODE_M (HP_MEM_APM_M2_EXCEPTION_MODE_V << HP_MEM_APM_M2_EXCEPTION_MODE_S) +#define HP_MEM_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define HP_MEM_APM_M2_EXCEPTION_MODE_S 16 +/** HP_MEM_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_MEM_APM_M2_EXCEPTION_ID 0x0000001FU +#define HP_MEM_APM_M2_EXCEPTION_ID_M (HP_MEM_APM_M2_EXCEPTION_ID_V << HP_MEM_APM_M2_EXCEPTION_ID_S) +#define HP_MEM_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define HP_MEM_APM_M2_EXCEPTION_ID_S 18 + +/** HP_MEM_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define HP_MEM_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0xf4) +/** HP_MEM_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_MEM_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_MEM_APM_M2_EXCEPTION_ADDR_M (HP_MEM_APM_M2_EXCEPTION_ADDR_V << HP_MEM_APM_M2_EXCEPTION_ADDR_S) +#define HP_MEM_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_MEM_APM_M2_EXCEPTION_ADDR_S 0 + +/** HP_MEM_APM_M3_STATUS_REG register + * M3 status register + */ +#define HP_MEM_APM_M3_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xf8) +/** HP_MEM_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define HP_MEM_APM_M3_EXCEPTION_STATUS 0x00000003U +#define HP_MEM_APM_M3_EXCEPTION_STATUS_M (HP_MEM_APM_M3_EXCEPTION_STATUS_V << HP_MEM_APM_M3_EXCEPTION_STATUS_S) +#define HP_MEM_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define HP_MEM_APM_M3_EXCEPTION_STATUS_S 0 + +/** HP_MEM_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define HP_MEM_APM_M3_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xfc) +/** HP_MEM_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_M (HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_S) +#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_S 0 + +/** HP_MEM_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define HP_MEM_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0x100) +/** HP_MEM_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_MEM_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define HP_MEM_APM_M3_EXCEPTION_REGION_M (HP_MEM_APM_M3_EXCEPTION_REGION_V << HP_MEM_APM_M3_EXCEPTION_REGION_S) +#define HP_MEM_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_MEM_APM_M3_EXCEPTION_REGION_S 0 +/** HP_MEM_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_MEM_APM_M3_EXCEPTION_MODE 0x00000003U +#define HP_MEM_APM_M3_EXCEPTION_MODE_M (HP_MEM_APM_M3_EXCEPTION_MODE_V << HP_MEM_APM_M3_EXCEPTION_MODE_S) +#define HP_MEM_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define HP_MEM_APM_M3_EXCEPTION_MODE_S 16 +/** HP_MEM_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_MEM_APM_M3_EXCEPTION_ID 0x0000001FU +#define HP_MEM_APM_M3_EXCEPTION_ID_M (HP_MEM_APM_M3_EXCEPTION_ID_V << HP_MEM_APM_M3_EXCEPTION_ID_S) +#define HP_MEM_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define HP_MEM_APM_M3_EXCEPTION_ID_S 18 + +/** HP_MEM_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define HP_MEM_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0x104) +/** HP_MEM_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_MEM_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_MEM_APM_M3_EXCEPTION_ADDR_M (HP_MEM_APM_M3_EXCEPTION_ADDR_V << HP_MEM_APM_M3_EXCEPTION_ADDR_S) +#define HP_MEM_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_MEM_APM_M3_EXCEPTION_ADDR_S 0 + +/** HP_MEM_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_MEM_APM_INT_EN_REG (DR_REG_HP_MEM_APM_BASE + 0x118) +/** HP_MEM_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ +#define HP_MEM_APM_M0_APM_INT_EN (BIT(0)) +#define HP_MEM_APM_M0_APM_INT_EN_M (HP_MEM_APM_M0_APM_INT_EN_V << HP_MEM_APM_M0_APM_INT_EN_S) +#define HP_MEM_APM_M0_APM_INT_EN_V 0x00000001U +#define HP_MEM_APM_M0_APM_INT_EN_S 0 +/** HP_MEM_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ +#define HP_MEM_APM_M1_APM_INT_EN (BIT(1)) +#define HP_MEM_APM_M1_APM_INT_EN_M (HP_MEM_APM_M1_APM_INT_EN_V << HP_MEM_APM_M1_APM_INT_EN_S) +#define HP_MEM_APM_M1_APM_INT_EN_V 0x00000001U +#define HP_MEM_APM_M1_APM_INT_EN_S 1 +/** HP_MEM_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * Configures to enable APM M2 interrupt. + * 0: disable + * 1: enable + */ +#define HP_MEM_APM_M2_APM_INT_EN (BIT(2)) +#define HP_MEM_APM_M2_APM_INT_EN_M (HP_MEM_APM_M2_APM_INT_EN_V << HP_MEM_APM_M2_APM_INT_EN_S) +#define HP_MEM_APM_M2_APM_INT_EN_V 0x00000001U +#define HP_MEM_APM_M2_APM_INT_EN_S 2 +/** HP_MEM_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * Configures to enable APM M3 interrupt. + * 0: disable + * 1: enable + */ +#define HP_MEM_APM_M3_APM_INT_EN (BIT(3)) +#define HP_MEM_APM_M3_APM_INT_EN_M (HP_MEM_APM_M3_APM_INT_EN_V << HP_MEM_APM_M3_APM_INT_EN_S) +#define HP_MEM_APM_M3_APM_INT_EN_V 0x00000001U +#define HP_MEM_APM_M3_APM_INT_EN_S 3 + +/** HP_MEM_APM_CLOCK_GATE_REG register + * Clock gating register + */ +#define HP_MEM_APM_CLOCK_GATE_REG (DR_REG_HP_MEM_APM_BASE + 0x7f8) +/** HP_MEM_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define HP_MEM_APM_CLK_EN (BIT(0)) +#define HP_MEM_APM_CLK_EN_M (HP_MEM_APM_CLK_EN_V << HP_MEM_APM_CLK_EN_S) +#define HP_MEM_APM_CLK_EN_V 0x00000001U +#define HP_MEM_APM_CLK_EN_S 0 + +/** HP_MEM_APM_DATE_REG register + * Version control register + */ +#define HP_MEM_APM_DATE_REG (DR_REG_HP_MEM_APM_BASE + 0x7fc) +/** HP_MEM_APM_DATE : R/W; bitpos: [27:0]; default: 37769360; + * Version control register. + */ +#define HP_MEM_APM_DATE 0x0FFFFFFFU +#define HP_MEM_APM_DATE_M (HP_MEM_APM_DATE_V << HP_MEM_APM_DATE_S) +#define HP_MEM_APM_DATE_V 0x0FFFFFFFU +#define HP_MEM_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/hp_mem_apm_struct.h b/components/soc/esp32h4/register/soc/hp_mem_apm_struct.h new file mode 100644 index 0000000000..16fda07b72 --- /dev/null +++ b/components/soc/esp32h4/register/soc/hp_mem_apm_struct.h @@ -0,0 +1,578 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ + uint32_t region_filter_en:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} hp_mem_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region n. + */ + uint32_t regionn_addr_start_l:12; + /** regionn_addr_start : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region n. + */ + uint32_t regionn_addr_start:7; + /** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region n. + */ + uint32_t regionn_addr_start_h:13; + }; + uint32_t val; +} hp_mem_apm_regionn_addr_start_reg_t; + +/** Type of regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region n. + */ + uint32_t regionn_addr_end_l:12; + /** regionn_addr_end : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region n. + */ + uint32_t regionn_addr_end:7; + /** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region n. + */ + uint32_t regionn_addr_end_h:13; + }; + uint32_t val; +} hp_mem_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_x:1; + /** regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_w:1; + /** regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_r:1; + uint32_t reserved_3:1; + /** regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_x:1; + /** regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_w:1; + /** regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_r:1; + uint32_t reserved_7:1; + /** regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_x:1; + /** regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_w:1; + /** regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_r:1; + /** regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_mem_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_func_en:1; + /** m1_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_func_en:1; + /** m2_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_func_en:1; + /** m3_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_mem_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_mem_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_mem_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_mem_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} hp_mem_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_mem_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m1_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_mem_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_mem_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} hp_mem_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_mem_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m2_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_mem_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_mem_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} hp_mem_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_mem_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m3_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_mem_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_mem_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} hp_mem_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * Configures to enable APM M2 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * Configures to enable APM M3 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_mem_apm_int_en_reg_t; + + +/** Group: Clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_mem_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37769360; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_mem_apm_date_reg_t; + + +typedef struct { + volatile hp_mem_apm_region_filter_en_reg_t region_filter_en; + volatile hp_mem_apm_regionn_addr_start_reg_t region0_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region0_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region0_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region1_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region1_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region1_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region2_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region2_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region2_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region3_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region3_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region3_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region4_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region4_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region4_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region5_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region5_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region5_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region6_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region6_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region6_attr; + volatile hp_mem_apm_regionn_addr_start_reg_t region7_addr_start; + volatile hp_mem_apm_regionn_addr_end_reg_t region7_addr_end; + volatile hp_mem_apm_regionn_attr_reg_t region7_attr; + uint32_t reserved_064[24]; + volatile hp_mem_apm_func_ctrl_reg_t func_ctrl; + volatile hp_mem_apm_m0_status_reg_t m0_status; + volatile hp_mem_apm_m0_status_clr_reg_t m0_status_clr; + volatile hp_mem_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile hp_mem_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile hp_mem_apm_m1_status_reg_t m1_status; + volatile hp_mem_apm_m1_status_clr_reg_t m1_status_clr; + volatile hp_mem_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile hp_mem_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile hp_mem_apm_m2_status_reg_t m2_status; + volatile hp_mem_apm_m2_status_clr_reg_t m2_status_clr; + volatile hp_mem_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile hp_mem_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile hp_mem_apm_m3_status_reg_t m3_status; + volatile hp_mem_apm_m3_status_clr_reg_t m3_status_clr; + volatile hp_mem_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile hp_mem_apm_m3_exception_info1_reg_t m3_exception_info1; + uint32_t reserved_108[4]; + volatile hp_mem_apm_int_en_reg_t int_en; + uint32_t reserved_11c[439]; + volatile hp_mem_apm_clock_gate_reg_t clock_gate; + volatile hp_mem_apm_date_reg_t date; +} hp_mem_apm_dev_t; + +extern hp_mem_apm_dev_t HP_MEM_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_mem_apm_dev_t) == 0x800, "Invalid size of hp_mem_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/hp_system_reg.h b/components/soc/esp32h4/register/soc/hp_system_reg.h index 2c4bd1bd95..29df932af7 100644 --- a/components/soc/esp32h4/register/soc/hp_system_reg.h +++ b/components/soc/esp32h4/register/soc/hp_system_reg.h @@ -478,6 +478,57 @@ extern "C" { #define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU #define HP_SYSTEM_MODEM_PERI_PMS_EXCEPTION_ADDR_S 8 +/** HP_SYSTEM_PERI_PMS_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_SYSTEM_PERI_PMS_INT_EN_REG (DR_REG_HP_SYSTEM_BASE + 0xa8) +/** HP_SYSTEM_HP_PERI_PMS_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable hp peri pms interrupt. + * 0: disable + * 1: enable + */ +#define HP_SYSTEM_HP_PERI_PMS_INT_EN (BIT(0)) +#define HP_SYSTEM_HP_PERI_PMS_INT_EN_M (HP_SYSTEM_HP_PERI_PMS_INT_EN_V << HP_SYSTEM_HP_PERI_PMS_INT_EN_S) +#define HP_SYSTEM_HP_PERI_PMS_INT_EN_V 0x00000001U +#define HP_SYSTEM_HP_PERI_PMS_INT_EN_S 0 +/** HP_SYSTEM_CPU_PERI_PMS_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable cpu peri pms interrupt. + * 0: disable + * 1: enable + */ +#define HP_SYSTEM_CPU_PERI_PMS_INT_EN (BIT(1)) +#define HP_SYSTEM_CPU_PERI_PMS_INT_EN_M (HP_SYSTEM_CPU_PERI_PMS_INT_EN_V << HP_SYSTEM_CPU_PERI_PMS_INT_EN_S) +#define HP_SYSTEM_CPU_PERI_PMS_INT_EN_V 0x00000001U +#define HP_SYSTEM_CPU_PERI_PMS_INT_EN_S 1 +/** HP_SYSTEM_MODEM_PERI_PMS_INT_EN : R/W; bitpos: [2]; default: 0; + * Configures to enable modem peri pms interrupt. + * 0: disable + * 1: enable + */ +#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN (BIT(2)) +#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN_M (HP_SYSTEM_MODEM_PERI_PMS_INT_EN_V << HP_SYSTEM_MODEM_PERI_PMS_INT_EN_S) +#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN_V 0x00000001U +#define HP_SYSTEM_MODEM_PERI_PMS_INT_EN_S 2 + +/** HP_SYSTEM_CPU_WAKEUP_EVENT_REG register + * NA + */ +#define HP_SYSTEM_CPU_WAKEUP_EVENT_REG (DR_REG_HP_SYSTEM_BASE + 0xc0) +/** HP_SYSTEM_CPU0_WAKEUP_EVENT : R/W; bitpos: [0]; default: 0; + * Configures the cpu0 to exit WFI mode + */ +#define HP_SYSTEM_CPU0_WAKEUP_EVENT (BIT(0)) +#define HP_SYSTEM_CPU0_WAKEUP_EVENT_M (HP_SYSTEM_CPU0_WAKEUP_EVENT_V << HP_SYSTEM_CPU0_WAKEUP_EVENT_S) +#define HP_SYSTEM_CPU0_WAKEUP_EVENT_V 0x00000001U +#define HP_SYSTEM_CPU0_WAKEUP_EVENT_S 0 +/** HP_SYSTEM_CPU1_WAKEUP_EVENT : R/W; bitpos: [1]; default: 0; + * Configures the cpu1 to exit WFI mode + */ +#define HP_SYSTEM_CPU1_WAKEUP_EVENT (BIT(1)) +#define HP_SYSTEM_CPU1_WAKEUP_EVENT_M (HP_SYSTEM_CPU1_WAKEUP_EVENT_V << HP_SYSTEM_CPU1_WAKEUP_EVENT_S) +#define HP_SYSTEM_CPU1_WAKEUP_EVENT_V 0x00000001U +#define HP_SYSTEM_CPU1_WAKEUP_EVENT_S 1 + /** HP_SYSTEM_ID_REG register * ID register */ @@ -506,7 +557,7 @@ extern "C" { * Date control and version control register */ #define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) -/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823056; +/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 38813728; * Version control register. */ #define HP_SYSTEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/hp_system_struct.h b/components/soc/esp32h4/register/soc/hp_system_struct.h index 362c830cf7..c6280f6677 100644 --- a/components/soc/esp32h4/register/soc/hp_system_struct.h +++ b/components/soc/esp32h4/register/soc/hp_system_struct.h @@ -11,213 +11,231 @@ extern "C" { #endif /** Group: Configuration Register */ -/** Type of system_external_device_encrypt_decrypt_control register +/** Type of external_device_encrypt_decrypt_control register * External device encryption/decryption configuration register */ typedef union { struct { - /** system_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. * 0: Disable * 1: Enable */ - uint32_t system_enable_spi_manual_encrypt:1; - /** system_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; * reserved */ - uint32_t system_enable_download_db_encrypt:1; - /** system_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. * 0: Disable * 1: Enable */ - uint32_t system_enable_download_g0cb_decrypt:1; - /** system_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot * mode. * 0: Disable * 1: Enable */ - uint32_t system_enable_download_manual_encrypt:1; + uint32_t enable_download_manual_encrypt:1; uint32_t reserved_4:28; }; uint32_t val; } hp_system_external_device_encrypt_decrypt_control_reg_t; -/** Type of system_sdio_ctrl register +/** Type of sdio_ctrl register * SDIO Control configuration register */ typedef union { struct { - /** system_dis_sdio_prob : R/W; bitpos: [0]; default: 1; + /** dis_sdio_prob : R/W; bitpos: [0]; default: 1; * Set this bit as 1 to disable SDIO_PROB function. disable by default. */ - uint32_t system_dis_sdio_prob:1; - /** system_sdio_win_access_en : R/W; bitpos: [1]; default: 1; + uint32_t dis_sdio_prob:1; + /** sdio_win_access_en : R/W; bitpos: [1]; default: 1; * Enable sdio slave to access other peripherals on the chip */ - uint32_t system_sdio_win_access_en:1; + uint32_t sdio_win_access_en:1; uint32_t reserved_2:30; }; uint32_t val; } hp_system_sdio_ctrl_reg_t; -/** Type of system_rom_table_lock register +/** Type of rom_table_lock register * ROM-Table lock register */ typedef union { struct { - /** system_rom_table_lock : R/W; bitpos: [0]; default: 0; + /** rom_table_lock : R/W; bitpos: [0]; default: 0; * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. * 0: Unlock * 1: Lock */ - uint32_t system_rom_table_lock:1; + uint32_t rom_table_lock:1; uint32_t reserved_1:31; }; uint32_t val; } hp_system_rom_table_lock_reg_t; -/** Type of system_rom_table register +/** Type of rom_table register * ROM-Table register */ typedef union { struct { - /** system_rom_table : R/W; bitpos: [31:0]; default: 0; + /** rom_table : R/W; bitpos: [31:0]; default: 0; * Software ROM-Table register, whose content can be modified only when * HP_SYSTEM_ROM_TABLE_LOCK is 0. */ - uint32_t system_rom_table:32; + uint32_t rom_table:32; }; uint32_t val; } hp_system_rom_table_reg_t; -/** Type of system_core_debug_runstall_conf register +/** Type of core_debug_runstall_conf register * Core Debug RunStall configurion register */ typedef union { struct { - /** system_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0; + /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable debug RunStall functionality between HP CPU and * LP CPU. * 0: Disable * 1: Enable */ - uint32_t system_core_debug_runstall_enable:1; - /** system_core0_runstalled : RO; bitpos: [1]; default: 0; + uint32_t core_debug_runstall_enable:1; + /** core0_runstalled : RO; bitpos: [1]; default: 0; * Software can read this field to get the runstall status of hp-core0. 1: stalled, 0: * not stalled. */ - uint32_t system_core0_runstalled:1; - /** system_core1_runstalled : RO; bitpos: [2]; default: 0; + uint32_t core0_runstalled:1; + /** core1_runstalled : RO; bitpos: [2]; default: 0; * Software can read this field to get the runstall status of hp-core1. 1: stalled, 0: * not stalled. */ - uint32_t system_core1_runstalled:1; + uint32_t core1_runstalled:1; uint32_t reserved_3:29; }; uint32_t val; } hp_system_core_debug_runstall_conf_reg_t; -/** Type of system_sprom_ctrl register +/** Type of sprom_ctrl register * reserved */ typedef union { struct { - /** system_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 80; + /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 80; * reserved */ - uint32_t system_sprom_mem_aux_ctrl:32; + uint32_t sprom_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sprom_ctrl_reg_t; -/** Type of system_spram_ctrl register +/** Type of spram_ctrl register * reserved */ typedef union { struct { - /** system_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320; + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320; * reserved */ - uint32_t system_spram_mem_aux_ctrl:32; + uint32_t spram_mem_aux_ctrl:32; }; uint32_t val; } hp_system_spram_ctrl_reg_t; -/** Type of system_sprf_ctrl register +/** Type of sprf_ctrl register * reserved */ typedef union { struct { - /** system_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320; + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 10320; * reserved */ - uint32_t system_sprf_mem_aux_ctrl:32; + uint32_t sprf_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sprf_ctrl_reg_t; -/** Type of system_bitscrambler_peri_sel register +/** Type of bitscrambler_peri_sel register * reserved */ typedef union { struct { - /** system_bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0; + /** bitscrambler_rx_sel : R/W; bitpos: [3:0]; default: 0; * select peri that will be connected to bitscrambler,dir : receive data from bs */ - uint32_t system_bitscrambler_rx_sel:4; - /** system_bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0; + uint32_t bitscrambler_rx_sel:4; + /** bitscrambler_tx_sel : R/W; bitpos: [7:4]; default: 0; * select peri that will be connected to bitscrambler,dir : transfer data to peri */ - uint32_t system_bitscrambler_tx_sel:4; + uint32_t bitscrambler_tx_sel:4; uint32_t reserved_8:24; }; uint32_t val; } hp_system_bitscrambler_peri_sel_reg_t; -/** Type of system_appcpu_boot_addr register +/** Type of appcpu_boot_addr register * reserved */ typedef union { struct { - /** system_appcpu_boot_addr : R/W; bitpos: [31:0]; default: 0; + /** appcpu_boot_addr : R/W; bitpos: [31:0]; default: 0; * reserved */ - uint32_t system_appcpu_boot_addr:32; + uint32_t appcpu_boot_addr:32; }; uint32_t val; } hp_system_appcpu_boot_addr_reg_t; -/** Type of system_axi_mst_pri register +/** Type of axi_mst_pri register * AXI mst priority configuration register */ typedef union { struct { - /** system_dma_priority : R/W; bitpos: [0]; default: 0; + /** dma_priority : R/W; bitpos: [0]; default: 0; * AHB-DMA arbitration priority for command channels between masters connected to * ext_mem_DW_axi */ - uint32_t system_dma_priority:1; - /** system_cache_priority : R/W; bitpos: [1]; default: 0; + uint32_t dma_priority:1; + /** cache_priority : R/W; bitpos: [1]; default: 0; * CACHE arbitration priority for command channels between masters connected to * ext_mem_DW_axi */ - uint32_t system_cache_priority:1; + uint32_t cache_priority:1; uint32_t reserved_2:30; }; uint32_t val; } hp_system_axi_mst_pri_reg_t; -/** Type of system_rst_en register +/** Type of cpu_wakeup_event register + * NA + */ +typedef union { + struct { + /** cpu0_wakeup_event : R/W; bitpos: [0]; default: 0; + * Configures the cpu0 to exit WFI mode + */ + uint32_t cpu0_wakeup_event:1; + /** cpu1_wakeup_event : R/W; bitpos: [1]; default: 0; + * Configures the cpu1 to exit WFI mode + */ + uint32_t cpu1_wakeup_event:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_cpu_wakeup_event_reg_t; + +/** Type of rst_en register * PCR clock gating configure register */ typedef union { struct { - /** system_hpsysreg_rst_en : R/W; bitpos: [0]; default: 0; + /** hpsysreg_rst_en : R/W; bitpos: [0]; default: 0; * Set 0 to reset hp_system_reg module */ - uint32_t system_hpsysreg_rst_en:1; + uint32_t hpsysreg_rst_en:1; uint32_t reserved_1:31; }; uint32_t val; @@ -225,111 +243,111 @@ typedef union { /** Group: Timeout Register */ -/** Type of system_cpu_peri_timeout_conf register +/** Type of cpu_peri_timeout_conf register * CPU_PERI_TIMEOUT configuration register */ typedef union { struct { - /** system_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing CPU peripheral * register in the number of clock cycles of the clock domain. */ - uint32_t system_cpu_peri_timeout_thres:16; - /** system_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + uint32_t cpu_peri_timeout_thres:16; + /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; * Write 1 to clear timeout interrupt. */ - uint32_t system_cpu_peri_timeout_int_clear:1; - /** system_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + uint32_t cpu_peri_timeout_int_clear:1; + /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral * registers. * 0: Disable * 1: Enable */ - uint32_t system_cpu_peri_timeout_protect_en:1; + uint32_t cpu_peri_timeout_protect_en:1; uint32_t reserved_18:14; }; uint32_t val; } hp_system_cpu_peri_timeout_conf_reg_t; -/** Type of system_cpu_peri_timeout_addr register +/** Type of cpu_peri_timeout_addr register * CPU_PERI_TIMEOUT_ADDR register */ typedef union { struct { - /** system_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ - uint32_t system_cpu_peri_timeout_addr:32; + uint32_t cpu_peri_timeout_addr:32; }; uint32_t val; } hp_system_cpu_peri_timeout_addr_reg_t; -/** Type of system_cpu_peri_timeout_uid register +/** Type of cpu_peri_timeout_uid register * CPU_PERI_TIMEOUT_UID register */ typedef union { struct { - /** system_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. */ - uint32_t system_cpu_peri_timeout_uid:7; + uint32_t cpu_peri_timeout_uid:7; uint32_t reserved_7:25; }; uint32_t val; } hp_system_cpu_peri_timeout_uid_reg_t; -/** Type of system_hp_peri_timeout_conf register +/** Type of hp_peri_timeout_conf register * HP_PERI_TIMEOUT configuration register */ typedef union { struct { - /** system_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing HP peripheral * register, corresponding to the number of clock cycles of the clock domain. */ - uint32_t system_hp_peri_timeout_thres:16; - /** system_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + uint32_t hp_peri_timeout_thres:16; + /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; * Configures whether or not to clear timeout interrupt. * 0: No effect * 1: Clear timeout interrupt */ - uint32_t system_hp_peri_timeout_int_clear:1; - /** system_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + uint32_t hp_peri_timeout_int_clear:1; + /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral * registers. * 0: Disable * 1: Enable */ - uint32_t system_hp_peri_timeout_protect_en:1; + uint32_t hp_peri_timeout_protect_en:1; uint32_t reserved_18:14; }; uint32_t val; } hp_system_hp_peri_timeout_conf_reg_t; -/** Type of system_hp_peri_timeout_addr register +/** Type of hp_peri_timeout_addr register * HP_PERI_TIMEOUT_ADDR register */ typedef union { struct { - /** system_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ - uint32_t system_hp_peri_timeout_addr:32; + uint32_t hp_peri_timeout_addr:32; }; uint32_t val; } hp_system_hp_peri_timeout_addr_reg_t; -/** Type of system_hp_peri_timeout_uid register +/** Type of hp_peri_timeout_uid register * HP_PERI_TIMEOUT_UID register */ typedef union { struct { - /** system_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. */ - uint32_t system_hp_peri_timeout_uid:7; + uint32_t hp_peri_timeout_uid:7; uint32_t reserved_7:25; }; uint32_t val; @@ -337,150 +355,178 @@ typedef union { /** Group: PMS Register */ -/** Type of system_cpu_peri_pms_conf register +/** Type of cpu_peri_pms_conf register * CPU Peripherals PMS configuration register */ typedef union { struct { - /** system_cpu_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; + /** cpu_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; * Configures whether or not to clear cpu peri_pms_record_reg. * 0: No clear * 1: Clear peri_pms_record_reg */ - uint32_t system_cpu_peri_pms_exception_clr:1; + uint32_t cpu_peri_pms_exception_clr:1; uint32_t reserved_1:31; }; uint32_t val; } hp_system_cpu_peri_pms_conf_reg_t; -/** Type of system_cpu_peri_pms_exception_info register +/** Type of cpu_peri_pms_exception_info register * CPU Peripherals PMS exception info record register */ typedef union { struct { - /** system_cpu_peri_pms_exception_det : RO; bitpos: [0]; default: 0; + /** cpu_peri_pms_exception_det : RO; bitpos: [0]; default: 0; * Represents whether the cpu peripheral pms has been triggered. * 0: No triggered * 1: Has been triggered */ - uint32_t system_cpu_peri_pms_exception_det:1; - /** system_cpu_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; + uint32_t cpu_peri_pms_exception_det:1; + /** cpu_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; * Represents the master id when cpu peripheral pms has been triggered. */ - uint32_t system_cpu_peri_pms_exception_id:5; - /** system_cpu_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; + uint32_t cpu_peri_pms_exception_id:5; + /** cpu_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; * Represents the security mode when cpu peripheral pms has been triggered. */ - uint32_t system_cpu_peri_pms_exception_mode:2; - /** system_cpu_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; + uint32_t cpu_peri_pms_exception_mode:2; + /** cpu_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; * Represents the access address (bit23~bit0) when cpu peripheral pms has been * triggered. */ - uint32_t system_cpu_peri_pms_exception_addr:24; + uint32_t cpu_peri_pms_exception_addr:24; }; uint32_t val; } hp_system_cpu_peri_pms_exception_info_reg_t; -/** Type of system_hp_peri_pms_conf register +/** Type of hp_peri_pms_conf register * HP Peripherals PMS configuration register */ typedef union { struct { - /** system_hp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; + /** hp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; * Configures whether or not to clear hp peri_pms_record_reg. * 0: No clear * 1: Clear peri_pms_record_reg */ - uint32_t system_hp_peri_pms_exception_clr:1; + uint32_t hp_peri_pms_exception_clr:1; uint32_t reserved_1:31; }; uint32_t val; } hp_system_hp_peri_pms_conf_reg_t; -/** Type of system_hp_peri_pms_exception_info register +/** Type of hp_peri_pms_exception_info register * HP Peripherals PMS exception info record register */ typedef union { struct { - /** system_hp_peri_pms_exception_det : RO; bitpos: [0]; default: 0; + /** hp_peri_pms_exception_det : RO; bitpos: [0]; default: 0; * Represents whether the hp peripheral pms has been triggered. * 0: No triggered * 1: Has been triggered */ - uint32_t system_hp_peri_pms_exception_det:1; - /** system_hp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; + uint32_t hp_peri_pms_exception_det:1; + /** hp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; * Represents the master id when hp peripheral pms has been triggered. */ - uint32_t system_hp_peri_pms_exception_id:5; - /** system_hp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; + uint32_t hp_peri_pms_exception_id:5; + /** hp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; * Represents the security mode when hp peripheral pms has been triggered. */ - uint32_t system_hp_peri_pms_exception_mode:2; - /** system_hp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; + uint32_t hp_peri_pms_exception_mode:2; + /** hp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; * Represents the access address (bit23~bit0) when hp peripheral pms has been * triggered. */ - uint32_t system_hp_peri_pms_exception_addr:24; + uint32_t hp_peri_pms_exception_addr:24; }; uint32_t val; } hp_system_hp_peri_pms_exception_info_reg_t; -/** Type of system_modem_peri_pms_conf register +/** Type of modem_peri_pms_conf register * MODEM Peripherals PMS configuration register */ typedef union { struct { - /** system_modem_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; + /** modem_peri_pms_exception_clr : WT; bitpos: [0]; default: 0; * Configures whether or not to clear modem peri_pms_record_reg. * 0: No clear * 1: Clear peri_pms_record_reg */ - uint32_t system_modem_peri_pms_exception_clr:1; + uint32_t modem_peri_pms_exception_clr:1; uint32_t reserved_1:31; }; uint32_t val; } hp_system_modem_peri_pms_conf_reg_t; -/** Type of system_modem_peri_pms_exception_info register +/** Type of modem_peri_pms_exception_info register * MODEM Peripherals PMS exception info record register */ typedef union { struct { - /** system_modem_peri_pms_exception_det : RO; bitpos: [0]; default: 0; + /** modem_peri_pms_exception_det : RO; bitpos: [0]; default: 0; * Represents whether the modem peripheral pms has been triggered. * 0: No triggered * 1: Has been triggered */ - uint32_t system_modem_peri_pms_exception_det:1; - /** system_modem_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; + uint32_t modem_peri_pms_exception_det:1; + /** modem_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0; * Represents the master id when modem peripheral pms has been triggered. */ - uint32_t system_modem_peri_pms_exception_id:5; - /** system_modem_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; + uint32_t modem_peri_pms_exception_id:5; + /** modem_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0; * Represents the security mode when modem peripheral pms has been triggered. */ - uint32_t system_modem_peri_pms_exception_mode:2; - /** system_modem_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; + uint32_t modem_peri_pms_exception_mode:2; + /** modem_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0; * Represents the access address (bit23~bit0) when modem peripheral pms has been * triggered. */ - uint32_t system_modem_peri_pms_exception_addr:24; + uint32_t modem_peri_pms_exception_addr:24; }; uint32_t val; } hp_system_modem_peri_pms_exception_info_reg_t; +/** Type of peri_pms_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** hp_peri_pms_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable hp peri pms interrupt. + * 0: disable + * 1: enable + */ + uint32_t hp_peri_pms_int_en:1; + /** cpu_peri_pms_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable cpu peri pms interrupt. + * 0: disable + * 1: enable + */ + uint32_t cpu_peri_pms_int_en:1; + /** modem_peri_pms_int_en : R/W; bitpos: [2]; default: 0; + * Configures to enable modem peri pms interrupt. + * 0: disable + * 1: enable + */ + uint32_t modem_peri_pms_int_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} hp_system_peri_pms_int_en_reg_t; + /** Group: ID Register */ -/** Type of system_id register +/** Type of id register * ID register */ typedef union { struct { uint32_t reserved_0:12; - /** system_rom_id : RO; bitpos: [27:12]; default: 0; + /** rom_id : RO; bitpos: [27:12]; default: 0; * Represents the ROM ID of chip */ - uint32_t system_rom_id:16; + uint32_t rom_id:16; uint32_t reserved_28:4; }; uint32_t val; @@ -488,15 +534,15 @@ typedef union { /** Group: Version Register */ -/** Type of system_date register +/** Type of date register * Date control and version control register */ typedef union { struct { - /** system_date : R/W; bitpos: [27:0]; default: 37823056; + /** date : R/W; bitpos: [27:0]; default: 38813728; * Version control register. */ - uint32_t system_date:28; + uint32_t date:28; uint32_t reserved_28:4; }; uint32_t val; @@ -504,47 +550,50 @@ typedef union { typedef struct { - volatile hp_system_external_device_encrypt_decrypt_control_reg_t system_external_device_encrypt_decrypt_control; + volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; uint32_t reserved_004[2]; - volatile hp_system_cpu_peri_timeout_conf_reg_t system_cpu_peri_timeout_conf; - volatile hp_system_cpu_peri_timeout_addr_reg_t system_cpu_peri_timeout_addr; - volatile hp_system_cpu_peri_timeout_uid_reg_t system_cpu_peri_timeout_uid; - volatile hp_system_hp_peri_timeout_conf_reg_t system_hp_peri_timeout_conf; - volatile hp_system_hp_peri_timeout_addr_reg_t system_hp_peri_timeout_addr; - volatile hp_system_hp_peri_timeout_uid_reg_t system_hp_peri_timeout_uid; + volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; + volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; + volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; + volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; + volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; + volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; uint32_t reserved_024[3]; - volatile hp_system_sdio_ctrl_reg_t system_sdio_ctrl; + volatile hp_system_sdio_ctrl_reg_t sdio_ctrl; uint32_t reserved_034; - volatile hp_system_rom_table_lock_reg_t system_rom_table_lock; - volatile hp_system_rom_table_reg_t system_rom_table; - volatile hp_system_core_debug_runstall_conf_reg_t system_core_debug_runstall_conf; + volatile hp_system_rom_table_lock_reg_t rom_table_lock; + volatile hp_system_rom_table_reg_t rom_table; + volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf; uint32_t reserved_044[11]; - volatile hp_system_sprom_ctrl_reg_t system_sprom_ctrl; - volatile hp_system_spram_ctrl_reg_t system_spram_ctrl; - volatile hp_system_sprf_ctrl_reg_t system_sprf_ctrl; + volatile hp_system_sprom_ctrl_reg_t sprom_ctrl; + volatile hp_system_spram_ctrl_reg_t spram_ctrl; + volatile hp_system_sprf_ctrl_reg_t sprf_ctrl; uint32_t reserved_07c; - volatile hp_system_bitscrambler_peri_sel_reg_t system_bitscrambler_peri_sel; - volatile hp_system_appcpu_boot_addr_reg_t system_appcpu_boot_addr; - volatile hp_system_axi_mst_pri_reg_t system_axi_mst_pri; + volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel; + volatile hp_system_appcpu_boot_addr_reg_t appcpu_boot_addr; + volatile hp_system_axi_mst_pri_reg_t axi_mst_pri; uint32_t reserved_08c; - volatile hp_system_cpu_peri_pms_conf_reg_t system_cpu_peri_pms_conf; - volatile hp_system_cpu_peri_pms_exception_info_reg_t system_cpu_peri_pms_exception_info; - volatile hp_system_hp_peri_pms_conf_reg_t system_hp_peri_pms_conf; - volatile hp_system_hp_peri_pms_exception_info_reg_t system_hp_peri_pms_exception_info; - volatile hp_system_modem_peri_pms_conf_reg_t system_modem_peri_pms_conf; - volatile hp_system_modem_peri_pms_exception_info_reg_t system_modem_peri_pms_exception_info; - uint32_t reserved_0a8[205]; - volatile hp_system_id_reg_t system_id; + volatile hp_system_cpu_peri_pms_conf_reg_t cpu_peri_pms_conf; + volatile hp_system_cpu_peri_pms_exception_info_reg_t cpu_peri_pms_exception_info; + volatile hp_system_hp_peri_pms_conf_reg_t hp_peri_pms_conf; + volatile hp_system_hp_peri_pms_exception_info_reg_t hp_peri_pms_exception_info; + volatile hp_system_modem_peri_pms_conf_reg_t modem_peri_pms_conf; + volatile hp_system_modem_peri_pms_exception_info_reg_t modem_peri_pms_exception_info; + volatile hp_system_peri_pms_int_en_reg_t peri_pms_int_en; + uint32_t reserved_0ac[5]; + volatile hp_system_cpu_wakeup_event_reg_t cpu_wakeup_event; + uint32_t reserved_0c4[198]; + volatile hp_system_id_reg_t id; uint32_t reserved_3e0[4]; - volatile hp_system_rst_en_reg_t system_rst_en; + volatile hp_system_rst_en_reg_t rst_en; uint32_t reserved_3f4[2]; - volatile hp_system_date_reg_t system_date; -} hp_dev_t; + volatile hp_system_date_reg_t date; +} hp_system_dev_t; -extern hp_dev_t HP_SYSTEM; +extern hp_system_dev_t HP_SYSTEM; #ifndef __cplusplus -_Static_assert(sizeof(hp_dev_t) == 0x400, "Invalid size of hp_dev_t structure"); +_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h4/register/soc/lp_aon_reg.h b/components/soc/esp32h4/register/soc/lp_aon_reg.h index 67fd16aaff..194bdfc6ac 100644 --- a/components/soc/esp32h4/register/soc/lp_aon_reg.h +++ b/components/soc/esp32h4/register/soc/lp_aon_reg.h @@ -150,7 +150,7 @@ extern "C" { */ #define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) /** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; - * configure io0~31 hold enable,when io in hold status, all io configure and output + * configure io0~28 hold enable,when io in hold status, all io configure and output * will be latch , input function is useful */ #define LP_AON_GPIO_HOLD0 0xFFFFFFFFU @@ -160,13 +160,10 @@ extern "C" { /** LP_AON_GPIO_HOLD1_REG register * reserved - * This register is only for internal debugging purposes. Do not use it in - * applications. */ #define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) /** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; * reserved - * This field is only for internal debugging purposes. Do not use it in applications. */ #define LP_AON_GPIO_HOLD1 0xFFFFFFFFU #define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) @@ -248,6 +245,13 @@ extern "C" { * configure hp iomux reset bypass */ #define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_PULL_LDO_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_PULL_LDO_EN (BIT(27)) +#define LP_AON_IO_MUX_PULL_LDO_EN_M (LP_AON_IO_MUX_PULL_LDO_EN_V << LP_AON_IO_MUX_PULL_LDO_EN_S) +#define LP_AON_IO_MUX_PULL_LDO_EN_V 0x00000001U +#define LP_AON_IO_MUX_PULL_LDO_EN_S 27 /** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; * need_des */ @@ -608,45 +612,6 @@ extern "C" { #define LP_AON_IO_LDO_ADJUST_SW_EN_V 0x00000001U #define LP_AON_IO_LDO_ADJUST_SW_EN_S 31 -/** LP_AON_LP_GPIO_SECURITY_REG register - * need des - */ -#define LP_AON_LP_GPIO_SECURITY_REG (DR_REG_LP_AON_BASE + 0x8c) -/** LP_AON_LP_GPIO_LOCK : R/W; bitpos: [5:0]; default: 0; - * This field decides whether lp_gpio_config can be locked, or not. 0 (default): - * unlocked. 1: locked. - */ -#define LP_AON_LP_GPIO_LOCK 0x0000003FU -#define LP_AON_LP_GPIO_LOCK_M (LP_AON_LP_GPIO_LOCK_V << LP_AON_LP_GPIO_LOCK_S) -#define LP_AON_LP_GPIO_LOCK_V 0x0000003FU -#define LP_AON_LP_GPIO_LOCK_S 0 - -/** LP_AON_HP_GPIO_SECURITY_1_REG register - * need des - */ -#define LP_AON_HP_GPIO_SECURITY_1_REG (DR_REG_LP_AON_BASE + 0x90) -/** LP_AON_HP_GPIO_LOCK_P1 : R/W; bitpos: [31:0]; default: 0; - * This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0 - * (default): unlocked. 1: locked. - */ -#define LP_AON_HP_GPIO_LOCK_P1 0xFFFFFFFFU -#define LP_AON_HP_GPIO_LOCK_P1_M (LP_AON_HP_GPIO_LOCK_P1_V << LP_AON_HP_GPIO_LOCK_P1_S) -#define LP_AON_HP_GPIO_LOCK_P1_V 0xFFFFFFFFU -#define LP_AON_HP_GPIO_LOCK_P1_S 0 - -/** LP_AON_HP_GPIO_SECURITY_2_REG register - * need des - */ -#define LP_AON_HP_GPIO_SECURITY_2_REG (DR_REG_LP_AON_BASE + 0x94) -/** LP_AON_HP_GPIO_LOCK_P2 : R/W; bitpos: [7:0]; default: 0; - * This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0 - * (default): unlocked. 1: locked. - */ -#define LP_AON_HP_GPIO_LOCK_P2 0x000000FFU -#define LP_AON_HP_GPIO_LOCK_P2_M (LP_AON_HP_GPIO_LOCK_P2_V << LP_AON_HP_GPIO_LOCK_P2_S) -#define LP_AON_HP_GPIO_LOCK_P2_V 0x000000FFU -#define LP_AON_HP_GPIO_LOCK_P2_S 0 - /** LP_AON_SRAM_USAGE_CONF_REG register * HP memory usage configuration register */ @@ -674,11 +639,37 @@ extern "C" { #define LP_AON_ICACHE1_USAGE_V 0x00000001U #define LP_AON_ICACHE1_USAGE_S 1 +/** LP_AON_PUF_CONF_REG register + * PUF mem control config register + */ +#define LP_AON_PUF_CONF_REG (DR_REG_LP_AON_BASE + 0x19c) +/** LP_AON_PUF_SW : R/W; bitpos: [0]; default: 1; + * puf mem power switch control signal + */ +#define LP_AON_PUF_SW (BIT(0)) +#define LP_AON_PUF_SW_M (LP_AON_PUF_SW_V << LP_AON_PUF_SW_S) +#define LP_AON_PUF_SW_V 0x00000001U +#define LP_AON_PUF_SW_S 0 +/** LP_AON_PUF_ISO_EN : R/W; bitpos: [1]; default: 0; + * iso enable signal for puf mem + */ +#define LP_AON_PUF_ISO_EN (BIT(1)) +#define LP_AON_PUF_ISO_EN_M (LP_AON_PUF_ISO_EN_V << LP_AON_PUF_ISO_EN_S) +#define LP_AON_PUF_ISO_EN_V 0x00000001U +#define LP_AON_PUF_ISO_EN_S 1 +/** LP_AON_PUF_MEM_DISCHARGE : R/W; bitpos: [2]; default: 0; + * discharge signal for puf mem + */ +#define LP_AON_PUF_MEM_DISCHARGE (BIT(2)) +#define LP_AON_PUF_MEM_DISCHARGE_M (LP_AON_PUF_MEM_DISCHARGE_V << LP_AON_PUF_MEM_DISCHARGE_S) +#define LP_AON_PUF_MEM_DISCHARGE_V 0x00000001U +#define LP_AON_PUF_MEM_DISCHARGE_S 2 + /** LP_AON_DATE_REG register * reserved */ #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823056; +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 38814352; * version register */ #define LP_AON_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/lp_aon_struct.h b/components/soc/esp32h4/register/soc/lp_aon_struct.h index 8d9aa6ac36..bf31086ee5 100644 --- a/components/soc/esp32h4/register/soc/lp_aon_struct.h +++ b/components/soc/esp32h4/register/soc/lp_aon_struct.h @@ -163,7 +163,7 @@ typedef union { typedef union { struct { /** aon_gpio_hold0 : R/W; bitpos: [31:0]; default: 0; - * configure io0~31 hold enable,when io in hold status, all io configure and output + * configure io0~28 hold enable,when io in hold status, all io configure and output * will be latch , input function is useful */ uint32_t gpio_hold0:32; @@ -178,7 +178,6 @@ typedef union { struct { /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; * reserved - * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t gpio_hold1:32; }; @@ -251,7 +250,11 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:28; + uint32_t reserved_0:27; + /** aon_io_mux_pull_ldo_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t aon_io_mux_pull_ldo_en:1; /** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0; * need_des */ @@ -546,50 +549,6 @@ typedef union { uint32_t val; } lp_aon_io_ldo_cfg_reg_t; -/** Type of aon_lp_gpio_security register - * need des - */ -typedef union { - struct { - /** aon_lp_gpio_lock : R/W; bitpos: [5:0]; default: 0; - * This field decides whether lp_gpio_config can be locked, or not. 0 (default): - * unlocked. 1: locked. - */ - uint32_t aon_lp_gpio_lock:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} lp_aon_lp_gpio_security_reg_t; - -/** Type of aon_hp_gpio_security_1 register - * need des - */ -typedef union { - struct { - /** aon_hp_gpio_lock_p1 : R/W; bitpos: [31:0]; default: 0; - * This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0 - * (default): unlocked. 1: locked. - */ - uint32_t aon_hp_gpio_lock_p1:32; - }; - uint32_t val; -} lp_aon_hp_gpio_security_1_reg_t; - -/** Type of aon_hp_gpio_security_2 register - * need des - */ -typedef union { - struct { - /** aon_hp_gpio_lock_p2 : R/W; bitpos: [7:0]; default: 0; - * This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0 - * (default): unlocked. 1: locked. - */ - uint32_t aon_hp_gpio_lock_p2:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_aon_hp_gpio_security_2_reg_t; - /** Type of aon_sram_usage_conf register * HP memory usage configuration register */ @@ -616,12 +575,34 @@ typedef union { uint32_t val; } lp_aon_sram_usage_conf_reg_t; +/** Type of puf_conf register + * PUF mem control config register + */ +typedef union { + struct { + /** puf_sw : R/W; bitpos: [0]; default: 1; + * puf mem power switch control signal + */ + uint32_t puf_sw:1; + /** puf_iso_en : R/W; bitpos: [1]; default: 0; + * iso enable signal for puf mem + */ + uint32_t puf_iso_en:1; + /** puf_mem_discharge : R/W; bitpos: [2]; default: 0; + * discharge signal for puf mem + */ + uint32_t puf_mem_discharge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_aon_puf_conf_reg_t; + /** Type of aon_date register * reserved */ typedef union { struct { - /** aon_date : R/W; bitpos: [30:0]; default: 37823056; + /** aon_date : R/W; bitpos: [30:0]; default: 38814352; * version register */ uint32_t aon_date:31; @@ -662,12 +643,11 @@ typedef struct { volatile lp_aon_mem_ctrl_reg_t mem_ctrl; volatile lp_aon_hp_mem_ctrl_reg_t hp_mem_ctrl; volatile lp_aon_io_ldo_cfg_reg_t io_ldo_cfg; - uint32_t reserved_088; - volatile lp_aon_lp_gpio_security_reg_t lp_gpio_security; - volatile lp_aon_hp_gpio_security_1_reg_t hp_gpio_security_1; - volatile lp_aon_hp_gpio_security_2_reg_t hp_gpio_security_2; + uint32_t reserved_088[4]; volatile lp_aon_sram_usage_conf_reg_t sram_usage_conf; - uint32_t reserved_09c[216]; + uint32_t reserved_09c[64]; + volatile lp_aon_puf_conf_reg_t puf_conf; + uint32_t reserved_1a0[151]; volatile lp_aon_date_reg_t date; } lp_aon_dev_t; diff --git a/components/soc/esp32h4/register/soc/lp_tee_reg.h b/components/soc/esp32h4/register/soc/lp_tee_reg.h index 3c94229aa6..9372766663 100644 --- a/components/soc/esp32h4/register/soc/lp_tee_reg.h +++ b/components/soc/esp32h4/register/soc/lp_tee_reg.h @@ -14,7 +14,7 @@ extern "C" { /** LP_TEE_TRNG_CTRL_REG register * trng read/write control register */ -#define LP_TEE_TRNG_CTRL_REG (DR_REG_LP_BASE + 0x0) +#define LP_TEE_TRNG_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) /** LP_TEE_READ_TEE_TRNG : R/W; bitpos: [0]; default: 1; * Configures trng registers read permission in tee mode. * 0: can not be read @@ -91,7 +91,7 @@ extern "C" { /** LP_TEE_EFUSE_CTRL_REG register * efuse read/write control register */ -#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_BASE + 0x4) +#define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4) /** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1; * Configures efuse registers read permission in tee mode. * 0: can not be read @@ -168,7 +168,7 @@ extern "C" { /** LP_TEE_PMU_CTRL_REG register * pmu read/write control register */ -#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_BASE + 0x8) +#define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8) /** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1; * Configures pmu registers read permission in tee mode. * 0: can not be read @@ -245,7 +245,7 @@ extern "C" { /** LP_TEE_CLKRST_CTRL_REG register * clkrst read/write control register */ -#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_BASE + 0xc) +#define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc) /** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1; * Configures clkrst registers read permission in tee mode. * 0: can not be read @@ -322,7 +322,7 @@ extern "C" { /** LP_TEE_LP_AON_CTRL_CTRL_REG register * lp_aon_ctrl read/write control register */ -#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_BASE + 0x10) +#define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10) /** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1; * Configures lp_aon_ctrl registers read permission in tee mode. * 0: can not be read @@ -399,7 +399,7 @@ extern "C" { /** LP_TEE_LP_TIMER_CTRL_REG register * lp_timer read/write control register */ -#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_BASE + 0x14) +#define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14) /** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1; * Configures lp_timer registers read permission in tee mode. * 0: can not be read @@ -476,7 +476,7 @@ extern "C" { /** LP_TEE_LP_WDT_CTRL_REG register * lp_wdt read/write control register */ -#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_BASE + 0x18) +#define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18) /** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1; * Configures lp_wdt registers read permission in tee mode. * 0: can not be read @@ -553,7 +553,7 @@ extern "C" { /** LP_TEE_LPPERI_CTRL_REG register * lpperi read/write control register */ -#define LP_TEE_LPPERI_CTRL_REG (DR_REG_LP_BASE + 0x1c) +#define LP_TEE_LPPERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c) /** LP_TEE_READ_TEE_LPPERI : R/W; bitpos: [0]; default: 1; * Configures lpperi registers read permission in tee mode. * 0: can not be read @@ -630,7 +630,7 @@ extern "C" { /** LP_TEE_LP_ANA_PERI_CTRL_REG register * lp_ana_peri read/write control register */ -#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_BASE + 0x20) +#define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20) /** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1; * Configures lp_ana_peri registers read permission in tee mode. * 0: can not be read @@ -707,7 +707,7 @@ extern "C" { /** LP_TEE_LP_TOUCH_CTRL_REG register * lp_touch read/write control register */ -#define LP_TEE_LP_TOUCH_CTRL_REG (DR_REG_LP_BASE + 0x24) +#define LP_TEE_LP_TOUCH_CTRL_REG (DR_REG_LP_TEE_BASE + 0x24) /** LP_TEE_READ_TEE_LP_TOUCH : R/W; bitpos: [0]; default: 1; * Configures lp_touch registers read permission in tee mode. * 0: can not be read @@ -784,7 +784,7 @@ extern "C" { /** LP_TEE_TOUCH_AON_CTRL_REG register * touch_aon read/write control register */ -#define LP_TEE_TOUCH_AON_CTRL_REG (DR_REG_LP_BASE + 0x28) +#define LP_TEE_TOUCH_AON_CTRL_REG (DR_REG_LP_TEE_BASE + 0x28) /** LP_TEE_READ_TEE_TOUCH_AON : R/W; bitpos: [0]; default: 1; * Configures touch_aon registers read permission in tee mode. * 0: can not be read @@ -861,7 +861,7 @@ extern "C" { /** LP_TEE_LP_IO_CTRL_REG register * lp_io read/write control register */ -#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_BASE + 0x2c) +#define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c) /** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1; * Configures lp_io registers read permission in tee mode. * 0: can not be read @@ -938,7 +938,7 @@ extern "C" { /** LP_TEE_LP_BLE_TIMER_CTRL_REG register * lp_ble_timer read/write control register */ -#define LP_TEE_LP_BLE_TIMER_CTRL_REG (DR_REG_LP_BASE + 0x30) +#define LP_TEE_LP_BLE_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x30) /** LP_TEE_READ_TEE_LP_BLE_TIMER : R/W; bitpos: [0]; default: 1; * Configures lp_ble_timer registers read permission in tee mode. * 0: can not be read @@ -1015,7 +1015,7 @@ extern "C" { /** LP_TEE_LP_TEE_CTRL_REG register * lp_tee read/write control register */ -#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_BASE + 0x34) +#define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34) /** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1; * Configures lp_tee registers read permission in tee mode. * 0: can not be read @@ -1092,7 +1092,7 @@ extern "C" { /** LP_TEE_HUK_CTRL_REG register * lp_tee read/write control register */ -#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_BASE + 0x38) +#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38) /** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1; * Configures huk registers read permission in tee mode. * 0: can not be read @@ -1166,10 +1166,49 @@ extern "C" { #define LP_TEE_WRITE_REE2_HUK_V 0x00000001U #define LP_TEE_WRITE_REE2_HUK_S 7 +/** LP_TEE_LP_GPIO_SECURITY_REG register + * need des + */ +#define LP_TEE_LP_GPIO_SECURITY_REG (DR_REG_LP_TEE_BASE + 0xe4) +/** LP_TEE_LP_GPIO_LOCK : R/W; bitpos: [5:0]; default: 0; + * This field decides whether lp_gpio_config can be locked, or not. 0 (default): + * unlocked. 1: locked. + */ +#define LP_TEE_LP_GPIO_LOCK 0x0000003FU +#define LP_TEE_LP_GPIO_LOCK_M (LP_TEE_LP_GPIO_LOCK_V << LP_TEE_LP_GPIO_LOCK_S) +#define LP_TEE_LP_GPIO_LOCK_V 0x0000003FU +#define LP_TEE_LP_GPIO_LOCK_S 0 + +/** LP_TEE_HP_GPIO_SECURITY_1_REG register + * need des + */ +#define LP_TEE_HP_GPIO_SECURITY_1_REG (DR_REG_LP_TEE_BASE + 0xe8) +/** LP_TEE_HP_GPIO_LOCK_P1 : R/W; bitpos: [31:0]; default: 0; + * This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ +#define LP_TEE_HP_GPIO_LOCK_P1 0xFFFFFFFFU +#define LP_TEE_HP_GPIO_LOCK_P1_M (LP_TEE_HP_GPIO_LOCK_P1_V << LP_TEE_HP_GPIO_LOCK_P1_S) +#define LP_TEE_HP_GPIO_LOCK_P1_V 0xFFFFFFFFU +#define LP_TEE_HP_GPIO_LOCK_P1_S 0 + +/** LP_TEE_HP_GPIO_SECURITY_2_REG register + * need des + */ +#define LP_TEE_HP_GPIO_SECURITY_2_REG (DR_REG_LP_TEE_BASE + 0xec) +/** LP_TEE_HP_GPIO_LOCK_P2 : R/W; bitpos: [7:0]; default: 0; + * This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ +#define LP_TEE_HP_GPIO_LOCK_P2 0x000000FFU +#define LP_TEE_HP_GPIO_LOCK_P2_M (LP_TEE_HP_GPIO_LOCK_P2_V << LP_TEE_HP_GPIO_LOCK_P2_S) +#define LP_TEE_HP_GPIO_LOCK_P2_V 0x000000FFU +#define LP_TEE_HP_GPIO_LOCK_P2_S 0 + /** LP_TEE_BUS_ERR_CONF_REG register * Clock gating register */ -#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_BASE + 0xf0) +#define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0) /** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; * Configures whether return error response to cpu when access blocked * 0: disable error response @@ -1183,7 +1222,7 @@ extern "C" { /** LP_TEE_CLOCK_GATE_REG register * Clock gating register */ -#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xf8) +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8) /** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: enable automatic clock gating @@ -1197,8 +1236,8 @@ extern "C" { /** LP_TEE_DATE_REG register * Version control register */ -#define LP_TEE_DATE_REG (DR_REG_LP_BASE + 0xfc) -/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 37818640; +#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) +/** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 38813840; * Version control register */ #define LP_TEE_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/lp_tee_struct.h b/components/soc/esp32h4/register/soc/lp_tee_struct.h index 519a42e2c3..f6aba992b1 100644 --- a/components/soc/esp32h4/register/soc/lp_tee_struct.h +++ b/components/soc/esp32h4/register/soc/lp_tee_struct.h @@ -11,889 +11,935 @@ extern "C" { #endif /** Group: read write control register */ -/** Type of tee_trng_ctrl register +/** Type of trng_ctrl register * trng read/write control register */ typedef union { struct { - /** tee_read_tee_trng : R/W; bitpos: [0]; default: 1; + /** read_tee_trng : R/W; bitpos: [0]; default: 1; * Configures trng registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_trng:1; - /** tee_read_ree0_trng : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_trng:1; + /** read_ree0_trng : R/W; bitpos: [1]; default: 0; * Configures trng registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_trng:1; - /** tee_read_ree1_trng : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_trng:1; + /** read_ree1_trng : R/W; bitpos: [2]; default: 0; * Configures trng registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_trng:1; - /** tee_read_ree2_trng : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_trng:1; + /** read_ree2_trng : R/W; bitpos: [3]; default: 0; * Configures trng registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_trng:1; - /** tee_write_tee_trng : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_trng:1; + /** write_tee_trng : R/W; bitpos: [4]; default: 1; * Configures trng registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_trng:1; - /** tee_write_ree0_trng : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_trng:1; + /** write_ree0_trng : R/W; bitpos: [5]; default: 0; * Configures trng registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_trng:1; - /** tee_write_ree1_trng : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_trng:1; + /** write_ree1_trng : R/W; bitpos: [6]; default: 0; * Configures trng registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_trng:1; - /** tee_write_ree2_trng : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_trng:1; + /** write_ree2_trng : R/W; bitpos: [7]; default: 0; * Configures trng registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_trng:1; + uint32_t write_ree2_trng:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_trng_ctrl_reg_t; -/** Type of tee_efuse_ctrl register +/** Type of efuse_ctrl register * efuse read/write control register */ typedef union { struct { - /** tee_read_tee_efuse : R/W; bitpos: [0]; default: 1; + /** read_tee_efuse : R/W; bitpos: [0]; default: 1; * Configures efuse registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_efuse:1; - /** tee_read_ree0_efuse : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_efuse:1; + /** read_ree0_efuse : R/W; bitpos: [1]; default: 0; * Configures efuse registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_efuse:1; - /** tee_read_ree1_efuse : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_efuse:1; + /** read_ree1_efuse : R/W; bitpos: [2]; default: 0; * Configures efuse registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_efuse:1; - /** tee_read_ree2_efuse : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_efuse:1; + /** read_ree2_efuse : R/W; bitpos: [3]; default: 0; * Configures efuse registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_efuse:1; - /** tee_write_tee_efuse : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_efuse:1; + /** write_tee_efuse : R/W; bitpos: [4]; default: 1; * Configures efuse registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_efuse:1; - /** tee_write_ree0_efuse : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_efuse:1; + /** write_ree0_efuse : R/W; bitpos: [5]; default: 0; * Configures efuse registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_efuse:1; - /** tee_write_ree1_efuse : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_efuse:1; + /** write_ree1_efuse : R/W; bitpos: [6]; default: 0; * Configures efuse registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_efuse:1; - /** tee_write_ree2_efuse : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_efuse:1; + /** write_ree2_efuse : R/W; bitpos: [7]; default: 0; * Configures efuse registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_efuse:1; + uint32_t write_ree2_efuse:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_efuse_ctrl_reg_t; -/** Type of tee_pmu_ctrl register +/** Type of pmu_ctrl register * pmu read/write control register */ typedef union { struct { - /** tee_read_tee_pmu : R/W; bitpos: [0]; default: 1; + /** read_tee_pmu : R/W; bitpos: [0]; default: 1; * Configures pmu registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_pmu:1; - /** tee_read_ree0_pmu : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_pmu:1; + /** read_ree0_pmu : R/W; bitpos: [1]; default: 0; * Configures pmu registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_pmu:1; - /** tee_read_ree1_pmu : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_pmu:1; + /** read_ree1_pmu : R/W; bitpos: [2]; default: 0; * Configures pmu registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_pmu:1; - /** tee_read_ree2_pmu : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_pmu:1; + /** read_ree2_pmu : R/W; bitpos: [3]; default: 0; * Configures pmu registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_pmu:1; - /** tee_write_tee_pmu : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_pmu:1; + /** write_tee_pmu : R/W; bitpos: [4]; default: 1; * Configures pmu registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_pmu:1; - /** tee_write_ree0_pmu : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_pmu:1; + /** write_ree0_pmu : R/W; bitpos: [5]; default: 0; * Configures pmu registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_pmu:1; - /** tee_write_ree1_pmu : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_pmu:1; + /** write_ree1_pmu : R/W; bitpos: [6]; default: 0; * Configures pmu registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_pmu:1; - /** tee_write_ree2_pmu : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_pmu:1; + /** write_ree2_pmu : R/W; bitpos: [7]; default: 0; * Configures pmu registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_pmu:1; + uint32_t write_ree2_pmu:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_pmu_ctrl_reg_t; -/** Type of tee_clkrst_ctrl register +/** Type of clkrst_ctrl register * clkrst read/write control register */ typedef union { struct { - /** tee_read_tee_clkrst : R/W; bitpos: [0]; default: 1; + /** read_tee_clkrst : R/W; bitpos: [0]; default: 1; * Configures clkrst registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_clkrst:1; - /** tee_read_ree0_clkrst : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_clkrst:1; + /** read_ree0_clkrst : R/W; bitpos: [1]; default: 0; * Configures clkrst registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_clkrst:1; - /** tee_read_ree1_clkrst : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_clkrst:1; + /** read_ree1_clkrst : R/W; bitpos: [2]; default: 0; * Configures clkrst registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_clkrst:1; - /** tee_read_ree2_clkrst : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_clkrst:1; + /** read_ree2_clkrst : R/W; bitpos: [3]; default: 0; * Configures clkrst registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_clkrst:1; - /** tee_write_tee_clkrst : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_clkrst:1; + /** write_tee_clkrst : R/W; bitpos: [4]; default: 1; * Configures clkrst registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_clkrst:1; - /** tee_write_ree0_clkrst : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_clkrst:1; + /** write_ree0_clkrst : R/W; bitpos: [5]; default: 0; * Configures clkrst registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_clkrst:1; - /** tee_write_ree1_clkrst : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_clkrst:1; + /** write_ree1_clkrst : R/W; bitpos: [6]; default: 0; * Configures clkrst registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_clkrst:1; - /** tee_write_ree2_clkrst : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_clkrst:1; + /** write_ree2_clkrst : R/W; bitpos: [7]; default: 0; * Configures clkrst registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_clkrst:1; + uint32_t write_ree2_clkrst:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_clkrst_ctrl_reg_t; -/** Type of tee_lp_aon_ctrl_ctrl register +/** Type of lp_aon_ctrl_ctrl register * lp_aon_ctrl read/write control register */ typedef union { struct { - /** tee_read_tee_lp_aon_ctrl : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_aon_ctrl : R/W; bitpos: [0]; default: 1; * Configures lp_aon_ctrl registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_aon_ctrl:1; - /** tee_read_ree0_lp_aon_ctrl : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_aon_ctrl:1; + /** read_ree0_lp_aon_ctrl : R/W; bitpos: [1]; default: 0; * Configures lp_aon_ctrl registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_aon_ctrl:1; - /** tee_read_ree1_lp_aon_ctrl : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_aon_ctrl:1; + /** read_ree1_lp_aon_ctrl : R/W; bitpos: [2]; default: 0; * Configures lp_aon_ctrl registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_aon_ctrl:1; - /** tee_read_ree2_lp_aon_ctrl : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_aon_ctrl:1; + /** read_ree2_lp_aon_ctrl : R/W; bitpos: [3]; default: 0; * Configures lp_aon_ctrl registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_aon_ctrl:1; - /** tee_write_tee_lp_aon_ctrl : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_aon_ctrl:1; + /** write_tee_lp_aon_ctrl : R/W; bitpos: [4]; default: 1; * Configures lp_aon_ctrl registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_aon_ctrl:1; - /** tee_write_ree0_lp_aon_ctrl : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_aon_ctrl:1; + /** write_ree0_lp_aon_ctrl : R/W; bitpos: [5]; default: 0; * Configures lp_aon_ctrl registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_aon_ctrl:1; - /** tee_write_ree1_lp_aon_ctrl : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_aon_ctrl:1; + /** write_ree1_lp_aon_ctrl : R/W; bitpos: [6]; default: 0; * Configures lp_aon_ctrl registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_aon_ctrl:1; - /** tee_write_ree2_lp_aon_ctrl : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_aon_ctrl:1; + /** write_ree2_lp_aon_ctrl : R/W; bitpos: [7]; default: 0; * Configures lp_aon_ctrl registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_aon_ctrl:1; + uint32_t write_ree2_lp_aon_ctrl:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_aon_ctrl_ctrl_reg_t; -/** Type of tee_lp_timer_ctrl register +/** Type of lp_timer_ctrl register * lp_timer read/write control register */ typedef union { struct { - /** tee_read_tee_lp_timer : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_timer : R/W; bitpos: [0]; default: 1; * Configures lp_timer registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_timer:1; - /** tee_read_ree0_lp_timer : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_timer:1; + /** read_ree0_lp_timer : R/W; bitpos: [1]; default: 0; * Configures lp_timer registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_timer:1; - /** tee_read_ree1_lp_timer : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_timer:1; + /** read_ree1_lp_timer : R/W; bitpos: [2]; default: 0; * Configures lp_timer registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_timer:1; - /** tee_read_ree2_lp_timer : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_timer:1; + /** read_ree2_lp_timer : R/W; bitpos: [3]; default: 0; * Configures lp_timer registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_timer:1; - /** tee_write_tee_lp_timer : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_timer:1; + /** write_tee_lp_timer : R/W; bitpos: [4]; default: 1; * Configures lp_timer registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_timer:1; - /** tee_write_ree0_lp_timer : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_timer:1; + /** write_ree0_lp_timer : R/W; bitpos: [5]; default: 0; * Configures lp_timer registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_timer:1; - /** tee_write_ree1_lp_timer : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_timer:1; + /** write_ree1_lp_timer : R/W; bitpos: [6]; default: 0; * Configures lp_timer registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_timer:1; - /** tee_write_ree2_lp_timer : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_timer:1; + /** write_ree2_lp_timer : R/W; bitpos: [7]; default: 0; * Configures lp_timer registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_timer:1; + uint32_t write_ree2_lp_timer:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_timer_ctrl_reg_t; -/** Type of tee_lp_wdt_ctrl register +/** Type of lp_wdt_ctrl register * lp_wdt read/write control register */ typedef union { struct { - /** tee_read_tee_lp_wdt : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_wdt : R/W; bitpos: [0]; default: 1; * Configures lp_wdt registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_wdt:1; - /** tee_read_ree0_lp_wdt : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_wdt:1; + /** read_ree0_lp_wdt : R/W; bitpos: [1]; default: 0; * Configures lp_wdt registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_wdt:1; - /** tee_read_ree1_lp_wdt : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_wdt:1; + /** read_ree1_lp_wdt : R/W; bitpos: [2]; default: 0; * Configures lp_wdt registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_wdt:1; - /** tee_read_ree2_lp_wdt : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_wdt:1; + /** read_ree2_lp_wdt : R/W; bitpos: [3]; default: 0; * Configures lp_wdt registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_wdt:1; - /** tee_write_tee_lp_wdt : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_wdt:1; + /** write_tee_lp_wdt : R/W; bitpos: [4]; default: 1; * Configures lp_wdt registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_wdt:1; - /** tee_write_ree0_lp_wdt : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_wdt:1; + /** write_ree0_lp_wdt : R/W; bitpos: [5]; default: 0; * Configures lp_wdt registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_wdt:1; - /** tee_write_ree1_lp_wdt : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_wdt:1; + /** write_ree1_lp_wdt : R/W; bitpos: [6]; default: 0; * Configures lp_wdt registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_wdt:1; - /** tee_write_ree2_lp_wdt : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_wdt:1; + /** write_ree2_lp_wdt : R/W; bitpos: [7]; default: 0; * Configures lp_wdt registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_wdt:1; + uint32_t write_ree2_lp_wdt:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_wdt_ctrl_reg_t; -/** Type of tee_lpperi_ctrl register +/** Type of lpperi_ctrl register * lpperi read/write control register */ typedef union { struct { - /** tee_read_tee_lpperi : R/W; bitpos: [0]; default: 1; + /** read_tee_lpperi : R/W; bitpos: [0]; default: 1; * Configures lpperi registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lpperi:1; - /** tee_read_ree0_lpperi : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lpperi:1; + /** read_ree0_lpperi : R/W; bitpos: [1]; default: 0; * Configures lpperi registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lpperi:1; - /** tee_read_ree1_lpperi : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lpperi:1; + /** read_ree1_lpperi : R/W; bitpos: [2]; default: 0; * Configures lpperi registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lpperi:1; - /** tee_read_ree2_lpperi : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lpperi:1; + /** read_ree2_lpperi : R/W; bitpos: [3]; default: 0; * Configures lpperi registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lpperi:1; - /** tee_write_tee_lpperi : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lpperi:1; + /** write_tee_lpperi : R/W; bitpos: [4]; default: 1; * Configures lpperi registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lpperi:1; - /** tee_write_ree0_lpperi : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lpperi:1; + /** write_ree0_lpperi : R/W; bitpos: [5]; default: 0; * Configures lpperi registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lpperi:1; - /** tee_write_ree1_lpperi : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lpperi:1; + /** write_ree1_lpperi : R/W; bitpos: [6]; default: 0; * Configures lpperi registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lpperi:1; - /** tee_write_ree2_lpperi : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lpperi:1; + /** write_ree2_lpperi : R/W; bitpos: [7]; default: 0; * Configures lpperi registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lpperi:1; + uint32_t write_ree2_lpperi:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lpperi_ctrl_reg_t; -/** Type of tee_lp_ana_peri_ctrl register +/** Type of lp_ana_peri_ctrl register * lp_ana_peri read/write control register */ typedef union { struct { - /** tee_read_tee_lp_ana_peri : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_ana_peri : R/W; bitpos: [0]; default: 1; * Configures lp_ana_peri registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_ana_peri:1; - /** tee_read_ree0_lp_ana_peri : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_ana_peri:1; + /** read_ree0_lp_ana_peri : R/W; bitpos: [1]; default: 0; * Configures lp_ana_peri registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_ana_peri:1; - /** tee_read_ree1_lp_ana_peri : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_ana_peri:1; + /** read_ree1_lp_ana_peri : R/W; bitpos: [2]; default: 0; * Configures lp_ana_peri registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_ana_peri:1; - /** tee_read_ree2_lp_ana_peri : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_ana_peri:1; + /** read_ree2_lp_ana_peri : R/W; bitpos: [3]; default: 0; * Configures lp_ana_peri registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_ana_peri:1; - /** tee_write_tee_lp_ana_peri : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_ana_peri:1; + /** write_tee_lp_ana_peri : R/W; bitpos: [4]; default: 1; * Configures lp_ana_peri registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_ana_peri:1; - /** tee_write_ree0_lp_ana_peri : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_ana_peri:1; + /** write_ree0_lp_ana_peri : R/W; bitpos: [5]; default: 0; * Configures lp_ana_peri registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_ana_peri:1; - /** tee_write_ree1_lp_ana_peri : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_ana_peri:1; + /** write_ree1_lp_ana_peri : R/W; bitpos: [6]; default: 0; * Configures lp_ana_peri registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_ana_peri:1; - /** tee_write_ree2_lp_ana_peri : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_ana_peri:1; + /** write_ree2_lp_ana_peri : R/W; bitpos: [7]; default: 0; * Configures lp_ana_peri registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_ana_peri:1; + uint32_t write_ree2_lp_ana_peri:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_ana_peri_ctrl_reg_t; -/** Type of tee_lp_touch_ctrl register +/** Type of lp_touch_ctrl register * lp_touch read/write control register */ typedef union { struct { - /** tee_read_tee_lp_touch : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_touch : R/W; bitpos: [0]; default: 1; * Configures lp_touch registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_touch:1; - /** tee_read_ree0_lp_touch : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_touch:1; + /** read_ree0_lp_touch : R/W; bitpos: [1]; default: 0; * Configures lp_touch registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_touch:1; - /** tee_read_ree1_lp_touch : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_touch:1; + /** read_ree1_lp_touch : R/W; bitpos: [2]; default: 0; * Configures lp_touch registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_touch:1; - /** tee_read_ree2_lp_touch : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_touch:1; + /** read_ree2_lp_touch : R/W; bitpos: [3]; default: 0; * Configures lp_touch registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_touch:1; - /** tee_write_tee_lp_touch : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_touch:1; + /** write_tee_lp_touch : R/W; bitpos: [4]; default: 1; * Configures lp_touch registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_touch:1; - /** tee_write_ree0_lp_touch : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_touch:1; + /** write_ree0_lp_touch : R/W; bitpos: [5]; default: 0; * Configures lp_touch registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_touch:1; - /** tee_write_ree1_lp_touch : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_touch:1; + /** write_ree1_lp_touch : R/W; bitpos: [6]; default: 0; * Configures lp_touch registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_touch:1; - /** tee_write_ree2_lp_touch : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_touch:1; + /** write_ree2_lp_touch : R/W; bitpos: [7]; default: 0; * Configures lp_touch registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_touch:1; + uint32_t write_ree2_lp_touch:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_touch_ctrl_reg_t; -/** Type of tee_touch_aon_ctrl register +/** Type of touch_aon_ctrl register * touch_aon read/write control register */ typedef union { struct { - /** tee_read_tee_touch_aon : R/W; bitpos: [0]; default: 1; + /** read_tee_touch_aon : R/W; bitpos: [0]; default: 1; * Configures touch_aon registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_touch_aon:1; - /** tee_read_ree0_touch_aon : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_touch_aon:1; + /** read_ree0_touch_aon : R/W; bitpos: [1]; default: 0; * Configures touch_aon registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_touch_aon:1; - /** tee_read_ree1_touch_aon : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_touch_aon:1; + /** read_ree1_touch_aon : R/W; bitpos: [2]; default: 0; * Configures touch_aon registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_touch_aon:1; - /** tee_read_ree2_touch_aon : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_touch_aon:1; + /** read_ree2_touch_aon : R/W; bitpos: [3]; default: 0; * Configures touch_aon registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_touch_aon:1; - /** tee_write_tee_touch_aon : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_touch_aon:1; + /** write_tee_touch_aon : R/W; bitpos: [4]; default: 1; * Configures touch_aon registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_touch_aon:1; - /** tee_write_ree0_touch_aon : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_touch_aon:1; + /** write_ree0_touch_aon : R/W; bitpos: [5]; default: 0; * Configures touch_aon registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_touch_aon:1; - /** tee_write_ree1_touch_aon : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_touch_aon:1; + /** write_ree1_touch_aon : R/W; bitpos: [6]; default: 0; * Configures touch_aon registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_touch_aon:1; - /** tee_write_ree2_touch_aon : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_touch_aon:1; + /** write_ree2_touch_aon : R/W; bitpos: [7]; default: 0; * Configures touch_aon registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_touch_aon:1; + uint32_t write_ree2_touch_aon:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_touch_aon_ctrl_reg_t; -/** Type of tee_lp_io_ctrl register +/** Type of lp_io_ctrl register * lp_io read/write control register */ typedef union { struct { - /** tee_read_tee_lp_io : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_io : R/W; bitpos: [0]; default: 1; * Configures lp_io registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_io:1; - /** tee_read_ree0_lp_io : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_io:1; + /** read_ree0_lp_io : R/W; bitpos: [1]; default: 0; * Configures lp_io registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_io:1; - /** tee_read_ree1_lp_io : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_io:1; + /** read_ree1_lp_io : R/W; bitpos: [2]; default: 0; * Configures lp_io registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_io:1; - /** tee_read_ree2_lp_io : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_io:1; + /** read_ree2_lp_io : R/W; bitpos: [3]; default: 0; * Configures lp_io registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_io:1; - /** tee_write_tee_lp_io : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_io:1; + /** write_tee_lp_io : R/W; bitpos: [4]; default: 1; * Configures lp_io registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_io:1; - /** tee_write_ree0_lp_io : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_io:1; + /** write_ree0_lp_io : R/W; bitpos: [5]; default: 0; * Configures lp_io registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_io:1; - /** tee_write_ree1_lp_io : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_io:1; + /** write_ree1_lp_io : R/W; bitpos: [6]; default: 0; * Configures lp_io registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_io:1; - /** tee_write_ree2_lp_io : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_io:1; + /** write_ree2_lp_io : R/W; bitpos: [7]; default: 0; * Configures lp_io registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_io:1; + uint32_t write_ree2_lp_io:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_io_ctrl_reg_t; -/** Type of tee_lp_ble_timer_ctrl register +/** Type of lp_ble_timer_ctrl register * lp_ble_timer read/write control register */ typedef union { struct { - /** tee_read_tee_lp_ble_timer : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_ble_timer : R/W; bitpos: [0]; default: 1; * Configures lp_ble_timer registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_ble_timer:1; - /** tee_read_ree0_lp_ble_timer : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_lp_ble_timer:1; + /** read_ree0_lp_ble_timer : R/W; bitpos: [1]; default: 0; * Configures lp_ble_timer registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_ble_timer:1; - /** tee_read_ree1_lp_ble_timer : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_ble_timer:1; + /** read_ree1_lp_ble_timer : R/W; bitpos: [2]; default: 0; * Configures lp_ble_timer registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_ble_timer:1; - /** tee_read_ree2_lp_ble_timer : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_ble_timer:1; + /** read_ree2_lp_ble_timer : R/W; bitpos: [3]; default: 0; * Configures lp_ble_timer registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_ble_timer:1; - /** tee_write_tee_lp_ble_timer : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_ble_timer:1; + /** write_tee_lp_ble_timer : R/W; bitpos: [4]; default: 1; * Configures lp_ble_timer registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_ble_timer:1; - /** tee_write_ree0_lp_ble_timer : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_lp_ble_timer:1; + /** write_ree0_lp_ble_timer : R/W; bitpos: [5]; default: 0; * Configures lp_ble_timer registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_ble_timer:1; - /** tee_write_ree1_lp_ble_timer : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_ble_timer:1; + /** write_ree1_lp_ble_timer : R/W; bitpos: [6]; default: 0; * Configures lp_ble_timer registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_ble_timer:1; - /** tee_write_ree2_lp_ble_timer : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_ble_timer:1; + /** write_ree2_lp_ble_timer : R/W; bitpos: [7]; default: 0; * Configures lp_ble_timer registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_ble_timer:1; + uint32_t write_ree2_lp_ble_timer:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_ble_timer_ctrl_reg_t; -/** Type of tee_lp_tee_ctrl register +/** Type of lp_tee_ctrl register * lp_tee read/write control register */ typedef union { struct { - /** tee_read_tee_lp_tee : R/W; bitpos: [0]; default: 1; + /** read_tee_lp_tee : R/W; bitpos: [0]; default: 1; * Configures lp_tee registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_lp_tee:1; - /** tee_read_ree0_lp_tee : HRO; bitpos: [1]; default: 0; + uint32_t read_tee_lp_tee:1; + /** read_ree0_lp_tee : HRO; bitpos: [1]; default: 0; * Configures lp_tee registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_lp_tee:1; - /** tee_read_ree1_lp_tee : HRO; bitpos: [2]; default: 0; + uint32_t read_ree0_lp_tee:1; + /** read_ree1_lp_tee : HRO; bitpos: [2]; default: 0; * Configures lp_tee registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_lp_tee:1; - /** tee_read_ree2_lp_tee : HRO; bitpos: [3]; default: 0; + uint32_t read_ree1_lp_tee:1; + /** read_ree2_lp_tee : HRO; bitpos: [3]; default: 0; * Configures lp_tee registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_lp_tee:1; - /** tee_write_tee_lp_tee : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_lp_tee:1; + /** write_tee_lp_tee : R/W; bitpos: [4]; default: 1; * Configures lp_tee registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_lp_tee:1; - /** tee_write_ree0_lp_tee : HRO; bitpos: [5]; default: 0; + uint32_t write_tee_lp_tee:1; + /** write_ree0_lp_tee : HRO; bitpos: [5]; default: 0; * Configures lp_tee registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_lp_tee:1; - /** tee_write_ree1_lp_tee : HRO; bitpos: [6]; default: 0; + uint32_t write_ree0_lp_tee:1; + /** write_ree1_lp_tee : HRO; bitpos: [6]; default: 0; * Configures lp_tee registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_lp_tee:1; - /** tee_write_ree2_lp_tee : HRO; bitpos: [7]; default: 0; + uint32_t write_ree1_lp_tee:1; + /** write_ree2_lp_tee : HRO; bitpos: [7]; default: 0; * Configures lp_tee registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_lp_tee:1; + uint32_t write_ree2_lp_tee:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_lp_tee_ctrl_reg_t; -/** Type of tee_huk_ctrl register +/** Type of huk_ctrl register * lp_tee read/write control register */ typedef union { struct { - /** tee_read_tee_huk : R/W; bitpos: [0]; default: 1; + /** read_tee_huk : R/W; bitpos: [0]; default: 1; * Configures huk registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_tee_huk:1; - /** tee_read_ree0_huk : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_huk:1; + /** read_ree0_huk : R/W; bitpos: [1]; default: 0; * Configures huk registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree0_huk:1; - /** tee_read_ree1_huk : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_huk:1; + /** read_ree1_huk : R/W; bitpos: [2]; default: 0; * Configures huk registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree1_huk:1; - /** tee_read_ree2_huk : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_huk:1; + /** read_ree2_huk : R/W; bitpos: [3]; default: 0; * Configures huk registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t tee_read_ree2_huk:1; - /** tee_write_tee_huk : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_huk:1; + /** write_tee_huk : R/W; bitpos: [4]; default: 1; * Configures huk registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_tee_huk:1; - /** tee_write_ree0_huk : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_huk:1; + /** write_ree0_huk : R/W; bitpos: [5]; default: 0; * Configures huk registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree0_huk:1; - /** tee_write_ree1_huk : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_huk:1; + /** write_ree1_huk : R/W; bitpos: [6]; default: 0; * Configures huk registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree1_huk:1; - /** tee_write_ree2_huk : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_huk:1; + /** write_ree2_huk : R/W; bitpos: [7]; default: 0; * Configures huk registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t tee_write_ree2_huk:1; + uint32_t write_ree2_huk:1; uint32_t reserved_8:24; }; uint32_t val; } lp_tee_huk_ctrl_reg_t; +/** Group: configure_register */ +/** Type of lp_gpio_security register + * need des + */ +typedef union { + struct { + /** lp_gpio_lock : R/W; bitpos: [5:0]; default: 0; + * This field decides whether lp_gpio_config can be locked, or not. 0 (default): + * unlocked. 1: locked. + */ + uint32_t lp_gpio_lock:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_tee_lp_gpio_security_reg_t; + +/** Type of hp_gpio_security_1 register + * need des + */ +typedef union { + struct { + /** hp_gpio_lock_p1 : R/W; bitpos: [31:0]; default: 0; + * This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ + uint32_t hp_gpio_lock_p1:32; + }; + uint32_t val; +} lp_tee_hp_gpio_security_1_reg_t; + +/** Type of hp_gpio_security_2 register + * need des + */ +typedef union { + struct { + /** hp_gpio_lock_p2 : R/W; bitpos: [7:0]; default: 0; + * This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0 + * (default): unlocked. 1: locked. + */ + uint32_t hp_gpio_lock_p2:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_tee_hp_gpio_security_2_reg_t; + + /** Group: config register */ -/** Type of tee_bus_err_conf register +/** Type of bus_err_conf register * Clock gating register */ typedef union { struct { - /** tee_bus_err_resp_en : R/W; bitpos: [0]; default: 0; + /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; * Configures whether return error response to cpu when access blocked * 0: disable error response * 1: enable error response */ - uint32_t tee_bus_err_resp_en:1; + uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; }; uint32_t val; @@ -901,17 +947,17 @@ typedef union { /** Group: clock gating register */ -/** Type of tee_clock_gate register +/** Type of clock_gate register * Clock gating register */ typedef union { struct { - /** tee_clk_en : R/W; bitpos: [0]; default: 1; + /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. * 0: enable automatic clock gating * 1: keep the clock always on */ - uint32_t tee_clk_en:1; + uint32_t clk_en:1; uint32_t reserved_1:31; }; uint32_t val; @@ -919,15 +965,15 @@ typedef union { /** Group: Version control register */ -/** Type of tee_date register +/** Type of date register * Version control register */ typedef union { struct { - /** tee_date : R/W; bitpos: [27:0]; default: 37818640; + /** date : R/W; bitpos: [27:0]; default: 38813840; * Version control register */ - uint32_t tee_date:28; + uint32_t date:28; uint32_t reserved_28:4; }; uint32_t val; @@ -935,29 +981,31 @@ typedef union { typedef struct { - volatile lp_tee_trng_ctrl_reg_t tee_trng_ctrl; - volatile lp_tee_efuse_ctrl_reg_t tee_efuse_ctrl; - volatile lp_tee_pmu_ctrl_reg_t tee_pmu_ctrl; - volatile lp_tee_clkrst_ctrl_reg_t tee_clkrst_ctrl; - volatile lp_tee_lp_aon_ctrl_ctrl_reg_t tee_lp_aon_ctrl_ctrl; - volatile lp_tee_lp_timer_ctrl_reg_t tee_lp_timer_ctrl; - volatile lp_tee_lp_wdt_ctrl_reg_t tee_lp_wdt_ctrl; - volatile lp_tee_lpperi_ctrl_reg_t tee_lpperi_ctrl; - volatile lp_tee_lp_ana_peri_ctrl_reg_t tee_lp_ana_peri_ctrl; - volatile lp_tee_lp_touch_ctrl_reg_t tee_lp_touch_ctrl; - volatile lp_tee_touch_aon_ctrl_reg_t tee_touch_aon_ctrl; - volatile lp_tee_lp_io_ctrl_reg_t tee_lp_io_ctrl; - volatile lp_tee_lp_ble_timer_ctrl_reg_t tee_lp_ble_timer_ctrl; - volatile lp_tee_lp_tee_ctrl_reg_t tee_lp_tee_ctrl; - volatile lp_tee_huk_ctrl_reg_t tee_huk_ctrl; - uint32_t reserved_03c[45]; - volatile lp_tee_bus_err_conf_reg_t tee_bus_err_conf; + volatile lp_tee_trng_ctrl_reg_t trng_ctrl; + volatile lp_tee_efuse_ctrl_reg_t efuse_ctrl; + volatile lp_tee_pmu_ctrl_reg_t pmu_ctrl; + volatile lp_tee_clkrst_ctrl_reg_t clkrst_ctrl; + volatile lp_tee_lp_aon_ctrl_ctrl_reg_t lp_aon_ctrl_ctrl; + volatile lp_tee_lp_timer_ctrl_reg_t lp_timer_ctrl; + volatile lp_tee_lp_wdt_ctrl_reg_t lp_wdt_ctrl; + volatile lp_tee_lpperi_ctrl_reg_t lpperi_ctrl; + volatile lp_tee_lp_ana_peri_ctrl_reg_t lp_ana_peri_ctrl; + volatile lp_tee_lp_touch_ctrl_reg_t lp_touch_ctrl; + volatile lp_tee_touch_aon_ctrl_reg_t touch_aon_ctrl; + volatile lp_tee_lp_io_ctrl_reg_t lp_io_ctrl; + volatile lp_tee_lp_ble_timer_ctrl_reg_t lp_ble_timer_ctrl; + volatile lp_tee_lp_tee_ctrl_reg_t lp_tee_ctrl; + volatile lp_tee_huk_ctrl_reg_t huk_ctrl; + uint32_t reserved_03c[42]; + volatile lp_tee_lp_gpio_security_reg_t lp_gpio_security; + volatile lp_tee_hp_gpio_security_1_reg_t hp_gpio_security_1; + volatile lp_tee_hp_gpio_security_2_reg_t hp_gpio_security_2; + volatile lp_tee_bus_err_conf_reg_t bus_err_conf; uint32_t reserved_0f4; - volatile lp_tee_clock_gate_reg_t tee_clock_gate; - volatile lp_tee_date_reg_t tee_date; + volatile lp_tee_clock_gate_reg_t clock_gate; + volatile lp_tee_date_reg_t date; } lp_tee_dev_t; -extern lp_tee_dev_t LP_TEE; #ifndef __cplusplus _Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); diff --git a/components/soc/esp32h4/register/soc/lpperi_reg.h b/components/soc/esp32h4/register/soc/lpperi_reg.h index e37a668a69..f10532efd9 100644 --- a/components/soc/esp32h4/register/soc/lpperi_reg.h +++ b/components/soc/esp32h4/register/soc/lpperi_reg.h @@ -179,6 +179,20 @@ extern "C" { #define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU #define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_S 8 +/** LPPERI_PERI_PMS_INT_EN_REG register + * APM interrupt enable register + */ +#define LPPERI_PERI_PMS_INT_EN_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_PMS_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable lp peri pms interrupt. + * 0: disable + * 1: enable + */ +#define LPPERI_LP_PERI_PMS_INT_EN (BIT(0)) +#define LPPERI_LP_PERI_PMS_INT_EN_M (LPPERI_LP_PERI_PMS_INT_EN_V << LPPERI_LP_PERI_PMS_INT_EN_S) +#define LPPERI_LP_PERI_PMS_INT_EN_V 0x00000001U +#define LPPERI_LP_PERI_PMS_INT_EN_S 0 + /** LPPERI_INTERRUPT_SOURCE_REG register * record the lp cpu interrupt */ @@ -195,7 +209,7 @@ extern "C" { * version register */ #define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) -/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37819136; +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 38813744; * version register */ #define LPPERI_LPPERI_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/lpperi_struct.h b/components/soc/esp32h4/register/soc/lpperi_struct.h index e6150996eb..d36a50c1ab 100644 --- a/components/soc/esp32h4/register/soc/lpperi_struct.h +++ b/components/soc/esp32h4/register/soc/lpperi_struct.h @@ -167,6 +167,22 @@ typedef union { uint32_t val; } lpperi_lp_peri_pms_exception_info_reg_t; +/** Type of peri_pms_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** lp_peri_pms_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable lp peri pms interrupt. + * 0: disable + * 1: enable + */ + uint32_t lp_peri_pms_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lpperi_peri_pms_int_en_reg_t; + /** Group: Version register */ /** Type of date register @@ -174,7 +190,7 @@ typedef union { */ typedef union { struct { - /** lpperi_date : R/W; bitpos: [30:0]; default: 37819136; + /** lpperi_date : R/W; bitpos: [30:0]; default: 38813744; * version register */ uint32_t lpperi_date:31; @@ -193,7 +209,8 @@ typedef struct { uint32_t reserved_008[2]; volatile lpperi_lp_peri_pms_conf_reg_t lp_peri_pms_conf; volatile lpperi_lp_peri_pms_exception_info_reg_t lp_peri_pms_exception_info; - uint32_t reserved_018[2]; + volatile lpperi_peri_pms_int_en_reg_t peri_pms_int_en; + uint32_t reserved_01c; volatile lpperi_interrupt_source_reg_t interrupt_source; uint32_t reserved_024[246]; volatile lpperi_date_reg_t date; diff --git a/components/soc/esp32h4/register/soc/pmu_reg.h b/components/soc/esp32h4/register/soc/pmu_reg.h index fea1e13f77..4a301c49ce 100644 --- a/components/soc/esp32h4/register/soc/pmu_reg.h +++ b/components/soc/esp32h4/register/soc/pmu_reg.h @@ -476,7 +476,7 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) -/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16; * need_des */ #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU @@ -940,7 +940,7 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) -/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 16; * need_des */ #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU @@ -2476,7 +2476,7 @@ extern "C" { * need_des */ #define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) -/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 384; * need_des */ #define PMU_WAIT_XTL_STABLE 0x0000FFFFU @@ -3742,11 +3742,30 @@ extern "C" { #define PMU_TOUCH_FORCE_DONE_V 0x00000001U #define PMU_TOUCH_FORCE_DONE_S 31 +/** PMU_BLE_BANDGAP_CTRL_REG register + * need_des + */ +#define PMU_BLE_BANDGAP_CTRL_REG (DR_REG_PMU_BASE + 0x1c4) +/** PMU_EXT_OCODE : R/W; bitpos: [30:23]; default: 120; + * need_des + */ +#define PMU_EXT_OCODE 0x000000FFU +#define PMU_EXT_OCODE_M (PMU_EXT_OCODE_V << PMU_EXT_OCODE_S) +#define PMU_EXT_OCODE_V 0x000000FFU +#define PMU_EXT_OCODE_S 23 +/** PMU_EXT_FORCE_OCODE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_EXT_FORCE_OCODE (BIT(31)) +#define PMU_EXT_FORCE_OCODE_M (PMU_EXT_FORCE_OCODE_V << PMU_EXT_FORCE_OCODE_S) +#define PMU_EXT_FORCE_OCODE_V 0x00000001U +#define PMU_EXT_FORCE_OCODE_S 31 + /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37818464; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38814336; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/pmu_struct_mp.h b/components/soc/esp32h4/register/soc/pmu_struct_mp.h new file mode 100644 index 0000000000..5411c6eff1 --- /dev/null +++ b/components/soc/esp32h4/register/soc/pmu_struct_mp.h @@ -0,0 +1,3001 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_active_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_flash_mode:4; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_peri_pd_en:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** hp_active_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t hp_active_dcdc_ccm_enb:1; + /** hp_active_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_dcdc_clear_rdy:1; + /** hp_active_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 3; + * need_des + */ + uint32_t hp_active_dig_pmu_dpcur_bias:2; + /** hp_active_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 6; + * need_des + */ + uint32_t hp_active_dig_pmu_dsfmos:4; + /** hp_active_dcm_vset : R/W; bitpos: [21:17]; default: 23; + * need_des + */ + uint32_t hp_active_dcm_vset:5; + /** hp_active_dcm_mode : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t hp_active_dcm_mode:2; + /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_trx:1; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + uint32_t reserved_26:3; + /** hp_active_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_discnnt_dig_rtc:1; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:6; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:5; + /** hp_modem2active_backup_mode : R/W; bitpos: [27:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:5; + uint32_t reserved_28:1; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_active_hp_power_det_bypass:1; + uint32_t reserved_1:3; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 16; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtalx2:1; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** hp_sleep_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_flash_mode:4; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_peri_pd_en:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** hp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t hp_sleep_dcdc_ccm_enb:1; + /** hp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_dcdc_clear_rdy:1; + /** hp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; + * need_des + */ + uint32_t hp_sleep_dig_pmu_dpcur_bias:2; + /** hp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; + * need_des + */ + uint32_t hp_sleep_dig_pmu_dsfmos:4; + /** hp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; + * need_des + */ + uint32_t hp_sleep_dcm_vset:5; + /** hp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t hp_sleep_dcm_mode:2; + /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_trx:1; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + uint32_t reserved_26:3; + /** hp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_discnnt_dig_rtc:1; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + uint32_t reserved_10:6; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [24:20]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:5; + /** hp_active2sleep_backup_mode : R/W; bitpos: [29:25]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:5; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_power_det_bypass:1; + uint32_t reserved_1:15; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 16; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtalx2:1; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** hp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_io_mode:4; + /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_bod_source_sel:1; + /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_vddbat_mode:2; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_lppll:1; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtalx2:1; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** lp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t lp_sleep_vdd_io_mode:4; + /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_bod_source_sel:1; + /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_vddbat_mode:2; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_lppll:1; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** lp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t lp_sleep_dcdc_ccm_enb:1; + /** lp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_sleep_dcdc_clear_rdy:1; + /** lp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; + * need_des + */ + uint32_t lp_sleep_dig_pmu_dpcur_bias:2; + /** lp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; + * need_des + */ + uint32_t lp_sleep_dig_pmu_dsfmos:4; + /** lp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; + * need_des + */ + uint32_t lp_sleep_dcm_vset:5; + /** lp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; + * need_des + */ + uint32_t lp_sleep_dcm_mode:2; + uint32_t reserved_24:1; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + uint32_t reserved_26:3; + /** lp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_discnnt_dig_rtc:1; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + /** tie_low_global_xtalx2_icg : WT; bitpos: [7]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtalx2_icg:1; + /** tie_low_xpd_xtalx2 : WT; bitpos: [8]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtalx2:1; + uint32_t reserved_9:14; + /** tie_high_xtalx2 : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t tie_high_xtalx2:1; + /** tie_high_global_xtalx2_icg : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtalx2_icg:1; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** tie_high_dig_pad_slp_sel : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_dig_pad_slp_sel:1; + /** tie_low_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_low_dig_pad_slp_sel:1; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_pd_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_pd_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_wait_timer2 register + * need_des + */ +typedef union { + struct { + /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t dg_lp_iso_wait_timer:8; + /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; + * need_des + */ + uint32_t dg_lp_rst_wait_timer:8; + /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; + * need_des + */ + uint32_t dg_hp_iso_wait_timer:8; + /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; + * need_des + */ + uint32_t dg_hp_rst_wait_timer:8; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpperi_reserve register + * need_des + */ +typedef union { + struct { + /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_peri_reset:1; + /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_peri_iso:1; + /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_peri_pu:1; + /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_peri_no_reset:1; + /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_peri_no_iso:1; + /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_peri_pd:1; + /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_peri_mask:5; + uint32_t reserved_11:16; + /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_peri_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpperi_reserve_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_flash1p8_ldo register + * need_des + */ +typedef union { + struct { + /** flash1p8_ldo_rdy : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t flash1p8_ldo_rdy:1; + /** flash1p8_sw_en_xpd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_xpd:1; + /** flash1p8_sw_en_thru : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_thru:1; + /** flash1p8_sw_en_standby : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_standby:1; + /** flash1p8_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_power_adjust:1; + /** flash1p8_sw_en_endet : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t flash1p8_sw_en_endet:1; + uint32_t reserved_6:16; + /** flash1p8_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t flash1p8_bypass_ldo_rdy:1; + /** flash1p8_xpd : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t flash1p8_xpd:1; + /** flash1p8_thru : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t flash1p8_thru:1; + /** flash1p8_standby : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t flash1p8_standby:1; + /** flash1p8_power_adjust : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t flash1p8_power_adjust:4; + uint32_t reserved_30:1; + /** flash1p8_endet : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t flash1p8_endet:1; + }; + uint32_t val; +} pmu_power_flash1p8_ldo_reg_t; + +/** Type of power_flash1p2_ldo register + * need_des + */ +typedef union { + struct { + /** flash1p2_ldo_rdy : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t flash1p2_ldo_rdy:1; + /** flash1p2_sw_en_xpd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_xpd:1; + /** flash1p2_sw_en_thru : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_thru:1; + /** flash1p2_sw_en_standby : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_standby:1; + /** flash1p2_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_power_adjust:1; + /** flash1p2_sw_en_endet : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t flash1p2_sw_en_endet:1; + uint32_t reserved_6:16; + /** flash1p2_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t flash1p2_bypass_ldo_rdy:1; + /** flash1p2_xpd : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t flash1p2_xpd:1; + /** flash1p2_thru : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t flash1p2_thru:1; + /** flash1p2_standby : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t flash1p2_standby:1; + /** flash1p2_power_adjust : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t flash1p2_power_adjust:4; + uint32_t reserved_30:1; + /** flash1p2_endet : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t flash1p2_endet:1; + }; + uint32_t val; +} pmu_power_flash1p2_ldo_reg_t; + +/** Type of power_vdd_flash register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** flash_ldo_sw_en_tiel : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t flash_ldo_sw_en_tiel:1; + /** flash_ldo_power_sel : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t flash_ldo_power_sel:1; + /** flash_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t flash_ldo_sw_en_power_sel:1; + /** flash_ldo_wait_target : R/W; bitpos: [28:25]; default: 15; + * need_des + */ + uint32_t flash_ldo_wait_target:4; + /** flash_ldo_tiel_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t flash_ldo_tiel_en:1; + /** flash_ldo_tiel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t flash_ldo_tiel:1; + /** flash_ldo_sw_update : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t flash_ldo_sw_update:1; + }; + uint32_t val; +} pmu_power_vdd_flash_reg_t; + +/** Type of power_io_ldo register + * need_des + */ +typedef union { + struct { + /** io_ldo_rdy : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t io_ldo_rdy:1; + /** io_sw_en_xpd : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t io_sw_en_xpd:1; + uint32_t reserved_2:1; + /** io_sw_en_thru : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t io_sw_en_thru:1; + /** io_sw_en_standby : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t io_sw_en_standby:1; + /** io_sw_en_power_adjust : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t io_sw_en_power_adjust:1; + /** io_sw_en_endet : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t io_sw_en_endet:1; + uint32_t reserved_7:15; + /** io_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t io_bypass_ldo_rdy:1; + /** io_xpd : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t io_xpd:1; + /** io_thru : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t io_thru:1; + /** io_standby : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t io_standby:1; + /** io_power_adjust : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t io_power_adjust:4; + uint32_t reserved_30:1; + /** io_endet : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_endet:1; + }; + uint32_t val; +} pmu_power_io_ldo_reg_t; + +/** Type of power_vdd_io register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** io_ldo_power_sel : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t io_ldo_power_sel:1; + /** io_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t io_ldo_sw_en_power_sel:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} pmu_power_vdd_io_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 384; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** ana_wait_clk_sel : R/W; bitpos: [15]; default: 0; + * need_des + */ + uint32_t ana_wait_clk_sel:1; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** xpd_force_rftx : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t xpd_force_rftx:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_rftx_i2c:1; + /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_i2c:1; + /** xpd_rfpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_rfpll:1; + /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_force_rfpll:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of vddbat_cfg register + * need_des + */ +typedef union { + struct { + /** vddbat_mode : RO; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t vddbat_mode:2; + uint32_t reserved_2:29; + /** vddbat_sw_update : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vddbat_sw_update:1; + }; + uint32_t val; +} pmu_vddbat_cfg_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 256; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 1; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of dcm_ctrl register + * need_des + */ +typedef union { + struct { + /** dsfmos_use_por : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t dsfmos_use_por:1; + uint32_t reserved_1:21; + /** dcdc_dcm_update : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t dcdc_dcm_update:1; + /** dcdc_pcur_limit : R/W; bitpos: [25:23]; default: 1; + * need_des + */ + uint32_t dcdc_pcur_limit:3; + /** dcdc_bias_cal_done : RO; bitpos: [26]; default: 1; + * need_des + */ + uint32_t dcdc_bias_cal_done:1; + /** dcdc_ccm_sw_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t dcdc_ccm_sw_en:1; + /** dcdc_vcm_enb : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dcdc_vcm_enb:1; + /** dcdc_ccm_rdy : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t dcdc_ccm_rdy:1; + /** dcdc_vcm_rdy : RO; bitpos: [30]; default: 1; + * need_des + */ + uint32_t dcdc_vcm_rdy:1; + /** dcdc_rdy_clr : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dcdc_rdy_clr:1; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +/** Type of dcm_boost_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** dcdc_boost_ccm_ctrlen : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t dcdc_boost_ccm_ctrlen:1; + /** dcdc_boost_ccm_enb : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t dcdc_boost_ccm_enb:1; + /** dcdc_boost_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t dcdc_boost_en:1; + /** dcdc_boost_dreg : R/W; bitpos: [31:27]; default: 23; + * need_des + */ + uint32_t dcdc_boost_dreg:5; + }; + uint32_t val; +} pmu_dcm_boost_ctrl_reg_t; + +/** Type of touch_pwr_ctrl register + * need_des + */ +typedef union { + struct { + /** touch_sleep_cycles : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t touch_sleep_cycles:16; + uint32_t reserved_16:5; + /** touch_wait_cycles : R/W; bitpos: [29:21]; default: 0; + * need_des + */ + uint32_t touch_wait_cycles:9; + /** touch_sleep_timer_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t touch_sleep_timer_en:1; + /** touch_force_done : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t touch_force_done:1; + }; + uint32_t val; +} pmu_touch_pwr_ctrl_reg_t; + +/** Type of ble_bandgap_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** ext_ocode : R/W; bitpos: [30:23]; default: 120; + * need_des + */ + uint32_t ext_ocode:8; + /** ext_force_ocode : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_force_ocode:1; + }; + uint32_t val; +} pmu_ble_bandgap_ctrl_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 38814336; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 1; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + + +typedef struct { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + uint32_t reserved_034[13]; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + uint32_t reserved_0a4; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + uint32_t reserved_0b0; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_wait_timer2_reg_t power_wait_timer2; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_flash1p8_ldo_reg_t power_flash1p8_ldo; + volatile pmu_power_flash1p2_ldo_reg_t power_flash1p2_ldo; + volatile pmu_power_vdd_flash_reg_t power_vdd_flash; + volatile pmu_power_io_ldo_reg_t power_io_ldo; + volatile pmu_power_vdd_io_reg_t power_vdd_io; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_vddbat_cfg_reg_t vddbat_cfg; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl; + volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; + volatile pmu_ble_bandgap_ctrl_reg_t ble_bandgap_ctrl; + uint32_t reserved_1c8[141]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/soc/spi_mem_c_reg.h b/components/soc/esp32h4/register/soc/spi_mem_c_reg.h index 8ffb108440..9d501d4eeb 100644 --- a/components/soc/esp32h4/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32h4/register/soc/spi_mem_c_reg.h @@ -1321,6 +1321,29 @@ extern "C" { #define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) #define SPI_FMEM_PMS0_ECC_V 0x00000001U #define SPI_FMEM_PMS0_ECC_S 2 +/** SPI_FMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_FMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_FMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and + * SPI_FMEM_PMS0_SIZE_REG. + */ +#define SPI_FMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_FMEM_PMS0_NONSECURE_ECC_M (SPI_FMEM_PMS0_NONSECURE_ECC_V << SPI_FMEM_PMS0_NONSECURE_ECC_S) +#define SPI_FMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_FMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_FMEM_PMS1_ATTR_REG register * SPI1 flash PMS section 1 attribute register @@ -1349,6 +1372,29 @@ extern "C" { #define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) #define SPI_FMEM_PMS1_ECC_V 0x00000001U #define SPI_FMEM_PMS1_ECC_S 2 +/** SPI_FMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_FMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_FMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and + * SPI_FMEM_PMS1_SIZE_REG. + */ +#define SPI_FMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_FMEM_PMS1_NONSECURE_ECC_M (SPI_FMEM_PMS1_NONSECURE_ECC_V << SPI_FMEM_PMS1_NONSECURE_ECC_S) +#define SPI_FMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_FMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_FMEM_PMS2_ATTR_REG register * SPI1 flash PMS section 2 attribute register @@ -1377,6 +1423,29 @@ extern "C" { #define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) #define SPI_FMEM_PMS2_ECC_V 0x00000001U #define SPI_FMEM_PMS2_ECC_S 2 +/** SPI_FMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_FMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_FMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and + * SPI_FMEM_PMS2_SIZE_REG. + */ +#define SPI_FMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_FMEM_PMS2_NONSECURE_ECC_M (SPI_FMEM_PMS2_NONSECURE_ECC_V << SPI_FMEM_PMS2_NONSECURE_ECC_S) +#define SPI_FMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_FMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_FMEM_PMS3_ATTR_REG register * SPI1 flash PMS section 3 attribute register @@ -1405,6 +1474,29 @@ extern "C" { #define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) #define SPI_FMEM_PMS3_ECC_V 0x00000001U #define SPI_FMEM_PMS3_ECC_S 2 +/** SPI_FMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_FMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_FMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_FMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_FMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_FMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_FMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and + * SPI_FMEM_PMS3_SIZE_REG. + */ +#define SPI_FMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_FMEM_PMS3_NONSECURE_ECC_M (SPI_FMEM_PMS3_NONSECURE_ECC_V << SPI_FMEM_PMS3_NONSECURE_ECC_S) +#define SPI_FMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_FMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_FMEM_PMS0_ADDR_REG register * SPI1 flash PMS section 0 start address register @@ -1533,6 +1625,29 @@ extern "C" { #define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) #define SPI_SMEM_PMS0_ECC_V 0x00000001U #define SPI_SMEM_PMS0_ECC_S 2 +/** SPI_SMEM_PMS0_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS0_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS0_NONSECURE_RD_ATTR_S) +#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_NONSECURE_RD_ATTR_S 3 +/** SPI_SMEM_PMS0_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS0_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS0_NONSECURE_WR_ATTR_S) +#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_NONSECURE_WR_ATTR_S 4 +/** SPI_SMEM_PMS0_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 0 is configured by registers + * SPI_SMEM_PMS0_ADDR_REG and SPI_SMEM_PMS0_SIZE_REG. + */ +#define SPI_SMEM_PMS0_NONSECURE_ECC (BIT(5)) +#define SPI_SMEM_PMS0_NONSECURE_ECC_M (SPI_SMEM_PMS0_NONSECURE_ECC_V << SPI_SMEM_PMS0_NONSECURE_ECC_S) +#define SPI_SMEM_PMS0_NONSECURE_ECC_V 0x00000001U +#define SPI_SMEM_PMS0_NONSECURE_ECC_S 5 /** SPI_SMEM_PMS1_ATTR_REG register * SPI1 external RAM PMS section 1 attribute register @@ -1561,6 +1676,29 @@ extern "C" { #define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) #define SPI_SMEM_PMS1_ECC_V 0x00000001U #define SPI_SMEM_PMS1_ECC_S 2 +/** SPI_SMEM_PMS1_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS1_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS1_NONSECURE_RD_ATTR_S) +#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_NONSECURE_RD_ATTR_S 3 +/** SPI_SMEM_PMS1_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS1_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS1_NONSECURE_WR_ATTR_S) +#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_NONSECURE_WR_ATTR_S 4 +/** SPI_SMEM_PMS1_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 1 is configured by registers + * SPI_SMEM_PMS1_ADDR_REG and SPI_SMEM_PMS1_SIZE_REG. + */ +#define SPI_SMEM_PMS1_NONSECURE_ECC (BIT(5)) +#define SPI_SMEM_PMS1_NONSECURE_ECC_M (SPI_SMEM_PMS1_NONSECURE_ECC_V << SPI_SMEM_PMS1_NONSECURE_ECC_S) +#define SPI_SMEM_PMS1_NONSECURE_ECC_V 0x00000001U +#define SPI_SMEM_PMS1_NONSECURE_ECC_S 5 /** SPI_SMEM_PMS2_ATTR_REG register * SPI1 external RAM PMS section 2 attribute register @@ -1589,6 +1727,29 @@ extern "C" { #define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) #define SPI_SMEM_PMS2_ECC_V 0x00000001U #define SPI_SMEM_PMS2_ECC_S 2 +/** SPI_SMEM_PMS2_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS2_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS2_NONSECURE_RD_ATTR_S) +#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_NONSECURE_RD_ATTR_S 3 +/** SPI_SMEM_PMS2_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS2_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS2_NONSECURE_WR_ATTR_S) +#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_NONSECURE_WR_ATTR_S 4 +/** SPI_SMEM_PMS2_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 2 is configured by registers + * SPI_SMEM_PMS2_ADDR_REG and SPI_SMEM_PMS2_SIZE_REG. + */ +#define SPI_SMEM_PMS2_NONSECURE_ECC (BIT(5)) +#define SPI_SMEM_PMS2_NONSECURE_ECC_M (SPI_SMEM_PMS2_NONSECURE_ECC_V << SPI_SMEM_PMS2_NONSECURE_ECC_S) +#define SPI_SMEM_PMS2_NONSECURE_ECC_V 0x00000001U +#define SPI_SMEM_PMS2_NONSECURE_ECC_S 5 /** SPI_SMEM_PMS3_ATTR_REG register * SPI1 external RAM PMS section 3 attribute register @@ -1617,6 +1778,29 @@ extern "C" { #define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) #define SPI_SMEM_PMS3_ECC_V 0x00000001U #define SPI_SMEM_PMS3_ECC_S 2 +/** SPI_SMEM_PMS3_NONSECURE_RD_ATTR : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR (BIT(3)) +#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR_M (SPI_SMEM_PMS3_NONSECURE_RD_ATTR_V << SPI_SMEM_PMS3_NONSECURE_RD_ATTR_S) +#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_NONSECURE_RD_ATTR_S 3 +/** SPI_SMEM_PMS3_NONSECURE_WR_ATTR : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR (BIT(4)) +#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR_M (SPI_SMEM_PMS3_NONSECURE_WR_ATTR_V << SPI_SMEM_PMS3_NONSECURE_WR_ATTR_S) +#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_NONSECURE_WR_ATTR_S 4 +/** SPI_SMEM_PMS3_NONSECURE_ECC : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section 3 is configured by registers + * SPI_SMEM_PMS3_ADDR_REG and SPI_SMEM_PMS3_SIZE_REG. + */ +#define SPI_SMEM_PMS3_NONSECURE_ECC (BIT(5)) +#define SPI_SMEM_PMS3_NONSECURE_ECC_M (SPI_SMEM_PMS3_NONSECURE_ECC_V << SPI_SMEM_PMS3_NONSECURE_ECC_S) +#define SPI_SMEM_PMS3_NONSECURE_ECC_V 0x00000001U +#define SPI_SMEM_PMS3_NONSECURE_ECC_S 5 /** SPI_SMEM_PMS0_ADDR_REG register * SPI1 external RAM PMS section 0 start address register @@ -3566,7 +3750,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 38813840; * SPI0 register version. */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/spi_mem_c_struct.h b/components/soc/esp32h4/register/soc/spi_mem_c_struct.h index 30c1d2bb56..eceaf120d6 100644 --- a/components/soc/esp32h4/register/soc/spi_mem_c_struct.h +++ b/components/soc/esp32h4/register/soc/spi_mem_c_struct.h @@ -1174,7 +1174,21 @@ typedef union { * SPI_FMEM_PMSn_SIZE_REG. */ uint32_t fmem_pmsn_ecc:1; - uint32_t reserved_3:29; + /** fmem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 flash non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_rd_attr:1; + /** fmem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 flash non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_nonsecure_wr_attr:1; + /** fmem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 flash non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. + * The flash PMS section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_fmem_pmsn_attr_reg_t; @@ -1227,7 +1241,21 @@ typedef union { * SPI_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; - uint32_t reserved_3:29; + /** smem_pmsn_nonsecure_rd_attr : R/W; bitpos: [3]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_rd_attr:1; + /** smem_pmsn_nonsecure_wr_attr : R/W; bitpos: [4]; default: 1; + * 1: SPI1 external RAM non-secure PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_nonsecure_wr_attr:1; + /** smem_pmsn_nonsecure_ecc : R/W; bitpos: [5]; default: 0; + * SPI1 external RAM non-secure PMS section n ECC mode, 1: enable ECC mode. 0: Disable + * it. The external RAM PMS section n is configured by registers + * SPI_SMEM_PMSn_ADDR_REG and SPI_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_nonsecure_ecc:1; + uint32_t reserved_6:26; }; uint32_t val; } spi_smem_pmsn_attr_reg_t; @@ -2679,7 +2707,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37822512; + /** date : R/W; bitpos: [27:0]; default: 38813840; * SPI0 register version. */ uint32_t date:28; diff --git a/components/soc/esp32h4/register/soc/touch_aon_reg.h b/components/soc/esp32h4/register/soc/touch_aon_reg.h index c64cd4b969..7c1aafde75 100644 --- a/components/soc/esp32h4/register/soc/touch_aon_reg.h +++ b/components/soc/esp32h4/register/soc/touch_aon_reg.h @@ -14,7 +14,7 @@ extern "C" { /** TOUCH_AON_APPROACH_WORK_MEAS_NUM_REG register * need_des */ -#define TOUCH_AON_APPROACH_WORK_MEAS_NUM_REG (DR_REG_TOUCH_BASE + 0x0) +#define TOUCH_AON_APPROACH_WORK_MEAS_NUM_REG (DR_REG_TOUCH_AON_BASE + 0x0) /** TOUCH_AON_TOUCH_APPROACH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100; * need_des */ @@ -40,7 +40,7 @@ extern "C" { /** TOUCH_AON_SCAN_CTRL1_REG register * need_des */ -#define TOUCH_AON_SCAN_CTRL1_REG (DR_REG_TOUCH_BASE + 0x4) +#define TOUCH_AON_SCAN_CTRL1_REG (DR_REG_TOUCH_AON_BASE + 0x4) /** TOUCH_AON_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [0]; default: 0; * need_des */ @@ -73,7 +73,14 @@ extern "C" { /** TOUCH_AON_SCAN_CTRL2_REG register * need_des */ -#define TOUCH_AON_SCAN_CTRL2_REG (DR_REG_TOUCH_BASE + 0x8) +#define TOUCH_AON_SCAN_CTRL2_REG (DR_REG_TOUCH_AON_BASE + 0x8) +/** TOUCH_AON_FREQ_SCAN_CNT_RISE : R/W; bitpos: [1:0]; default: 1; + * need_des + */ +#define TOUCH_AON_FREQ_SCAN_CNT_RISE 0x00000003U +#define TOUCH_AON_FREQ_SCAN_CNT_RISE_M (TOUCH_AON_FREQ_SCAN_CNT_RISE_V << TOUCH_AON_FREQ_SCAN_CNT_RISE_S) +#define TOUCH_AON_FREQ_SCAN_CNT_RISE_V 0x00000003U +#define TOUCH_AON_FREQ_SCAN_CNT_RISE_S 0 /** TOUCH_AON_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:6]; default: 65535; * need_des */ @@ -113,7 +120,7 @@ extern "C" { /** TOUCH_AON_WORK_REG register * need_des */ -#define TOUCH_AON_WORK_REG (DR_REG_TOUCH_BASE + 0xc) +#define TOUCH_AON_WORK_REG (DR_REG_TOUCH_AON_BASE + 0xc) /** TOUCH_AON_DIV_NUM2 : R/W; bitpos: [18:16]; default: 0; * need_des */ @@ -160,7 +167,7 @@ extern "C" { /** TOUCH_AON_WORK_MEAS_NUM_REG register * need_des */ -#define TOUCH_AON_WORK_MEAS_NUM_REG (DR_REG_TOUCH_BASE + 0x10) +#define TOUCH_AON_WORK_MEAS_NUM_REG (DR_REG_TOUCH_AON_BASE + 0x10) /** TOUCH_AON_TOUCH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100; * need_des */ @@ -186,7 +193,7 @@ extern "C" { /** TOUCH_AON_FILTER1_REG register * need_des */ -#define TOUCH_AON_FILTER1_REG (DR_REG_TOUCH_BASE + 0x14) +#define TOUCH_AON_FILTER1_REG (DR_REG_TOUCH_AON_BASE + 0x14) /** TOUCH_AON_TOUCH_NN_DISUPDATE_BENCHMARK_EN : R/W; bitpos: [0]; default: 0; * Reserved */ @@ -268,7 +275,7 @@ extern "C" { /** TOUCH_AON_FILTER2_REG register * need_des */ -#define TOUCH_AON_FILTER2_REG (DR_REG_TOUCH_BASE + 0x18) +#define TOUCH_AON_FILTER2_REG (DR_REG_TOUCH_AON_BASE + 0x18) /** TOUCH_AON_TOUCH_OUTEN : R/W; bitpos: [29:15]; default: 16383; * need_des */ @@ -294,7 +301,7 @@ extern "C" { /** TOUCH_AON_FILTER3_REG register * need_des */ -#define TOUCH_AON_FILTER3_REG (DR_REG_TOUCH_BASE + 0x1c) +#define TOUCH_AON_FILTER3_REG (DR_REG_TOUCH_AON_BASE + 0x1c) /** TOUCH_AON_TOUCH_BENCHMARK_SW : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -327,7 +334,7 @@ extern "C" { /** TOUCH_AON_SLP0_REG register * need_des */ -#define TOUCH_AON_SLP0_REG (DR_REG_TOUCH_BASE + 0x20) +#define TOUCH_AON_SLP0_REG (DR_REG_TOUCH_AON_BASE + 0x20) /** TOUCH_AON_TOUCH_SLP_TH0 : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -353,7 +360,7 @@ extern "C" { /** TOUCH_AON_SLP1_REG register * need_des */ -#define TOUCH_AON_SLP1_REG (DR_REG_TOUCH_BASE + 0x24) +#define TOUCH_AON_SLP1_REG (DR_REG_TOUCH_AON_BASE + 0x24) /** TOUCH_AON_TOUCH_SLP_TH2 : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -372,7 +379,7 @@ extern "C" { /** TOUCH_AON_CLR_REG register * need_des */ -#define TOUCH_AON_CLR_REG (DR_REG_TOUCH_BASE + 0x28) +#define TOUCH_AON_CLR_REG (DR_REG_TOUCH_AON_BASE + 0x28) /** TOUCH_AON_TOUCH_CHANNEL_CLR : WT; bitpos: [14:0]; default: 0; * need_des */ @@ -391,7 +398,7 @@ extern "C" { /** TOUCH_AON_APPROACH_REG register * need_des */ -#define TOUCH_AON_APPROACH_REG (DR_REG_TOUCH_BASE + 0x2c) +#define TOUCH_AON_APPROACH_REG (DR_REG_TOUCH_AON_BASE + 0x2c) /** TOUCH_AON_TOUCH_APPROACH_PAD0 : R/W; bitpos: [3:0]; default: 15; * need_des */ @@ -424,7 +431,7 @@ extern "C" { /** TOUCH_AON_FREQ0_SCAN_PARA_REG register * need_des */ -#define TOUCH_AON_FREQ0_SCAN_PARA_REG (DR_REG_TOUCH_BASE + 0x30) +#define TOUCH_AON_FREQ0_SCAN_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x30) /** TOUCH_AON_TOUCH_FREQ0_DCAP_LPF : R/W; bitpos: [6:0]; default: 0; * need_des */ @@ -471,7 +478,7 @@ extern "C" { /** TOUCH_AON_FREQ1_SCAN_PARA_REG register * need_des */ -#define TOUCH_AON_FREQ1_SCAN_PARA_REG (DR_REG_TOUCH_BASE + 0x34) +#define TOUCH_AON_FREQ1_SCAN_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x34) /** TOUCH_AON_TOUCH_FREQ1_DCAP_LPF : R/W; bitpos: [6:0]; default: 0; * need_des */ @@ -518,7 +525,7 @@ extern "C" { /** TOUCH_AON_FREQ2_SCAN_PARA_REG register * need_des */ -#define TOUCH_AON_FREQ2_SCAN_PARA_REG (DR_REG_TOUCH_BASE + 0x38) +#define TOUCH_AON_FREQ2_SCAN_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x38) /** TOUCH_AON_TOUCH_FREQ2_DCAP_LPF : R/W; bitpos: [6:0]; default: 0; * need_des */ @@ -565,7 +572,7 @@ extern "C" { /** TOUCH_AON_ANA_PARA_REG register * need_des */ -#define TOUCH_AON_ANA_PARA_REG (DR_REG_TOUCH_BASE + 0x3c) +#define TOUCH_AON_ANA_PARA_REG (DR_REG_TOUCH_AON_BASE + 0x3c) /** TOUCH_AON_TOUCH_TOUCH_BUF_DRV : R/W; bitpos: [2:0]; default: 0; * need_des */ @@ -591,7 +598,7 @@ extern "C" { /** TOUCH_AON_MUX0_REG register * need_des */ -#define TOUCH_AON_MUX0_REG (DR_REG_TOUCH_BASE + 0x40) +#define TOUCH_AON_MUX0_REG (DR_REG_TOUCH_AON_BASE + 0x40) /** TOUCH_AON_TOUCH_DATA_SEL : R/W; bitpos: [9:8]; default: 0; * need_des */ @@ -652,7 +659,7 @@ extern "C" { /** TOUCH_AON_MUX1_REG register * need_des */ -#define TOUCH_AON_MUX1_REG (DR_REG_TOUCH_BASE + 0x44) +#define TOUCH_AON_MUX1_REG (DR_REG_TOUCH_AON_BASE + 0x44) /** TOUCH_AON_TOUCH_START : R/W; bitpos: [14:0]; default: 0; * need_des */ @@ -671,7 +678,7 @@ extern "C" { /** TOUCH_AON_PAD0_TH0_REG register * need_des */ -#define TOUCH_AON_PAD0_TH0_REG (DR_REG_TOUCH_BASE + 0x48) +#define TOUCH_AON_PAD0_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x48) /** TOUCH_AON_TOUCH_PAD0_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -683,7 +690,7 @@ extern "C" { /** TOUCH_AON_PAD0_TH1_REG register * need_des */ -#define TOUCH_AON_PAD0_TH1_REG (DR_REG_TOUCH_BASE + 0x4c) +#define TOUCH_AON_PAD0_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x4c) /** TOUCH_AON_TOUCH_PAD0_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -695,7 +702,7 @@ extern "C" { /** TOUCH_AON_PAD0_TH2_REG register * need_des */ -#define TOUCH_AON_PAD0_TH2_REG (DR_REG_TOUCH_BASE + 0x50) +#define TOUCH_AON_PAD0_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x50) /** TOUCH_AON_TOUCH_PAD0_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -707,7 +714,7 @@ extern "C" { /** TOUCH_AON_PAD1_TH0_REG register * need_des */ -#define TOUCH_AON_PAD1_TH0_REG (DR_REG_TOUCH_BASE + 0x54) +#define TOUCH_AON_PAD1_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x54) /** TOUCH_AON_TOUCH_PAD1_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -719,7 +726,7 @@ extern "C" { /** TOUCH_AON_PAD1_TH1_REG register * need_des */ -#define TOUCH_AON_PAD1_TH1_REG (DR_REG_TOUCH_BASE + 0x58) +#define TOUCH_AON_PAD1_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x58) /** TOUCH_AON_TOUCH_PAD1_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -731,7 +738,7 @@ extern "C" { /** TOUCH_AON_PAD1_TH2_REG register * need_des */ -#define TOUCH_AON_PAD1_TH2_REG (DR_REG_TOUCH_BASE + 0x5c) +#define TOUCH_AON_PAD1_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x5c) /** TOUCH_AON_TOUCH_PAD1_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -743,7 +750,7 @@ extern "C" { /** TOUCH_AON_PAD2_TH0_REG register * need_des */ -#define TOUCH_AON_PAD2_TH0_REG (DR_REG_TOUCH_BASE + 0x60) +#define TOUCH_AON_PAD2_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x60) /** TOUCH_AON_TOUCH_PAD2_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -755,7 +762,7 @@ extern "C" { /** TOUCH_AON_PAD2_TH1_REG register * need_des */ -#define TOUCH_AON_PAD2_TH1_REG (DR_REG_TOUCH_BASE + 0x64) +#define TOUCH_AON_PAD2_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x64) /** TOUCH_AON_TOUCH_PAD2_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -767,7 +774,7 @@ extern "C" { /** TOUCH_AON_PAD2_TH2_REG register * need_des */ -#define TOUCH_AON_PAD2_TH2_REG (DR_REG_TOUCH_BASE + 0x68) +#define TOUCH_AON_PAD2_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x68) /** TOUCH_AON_TOUCH_PAD2_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -779,7 +786,7 @@ extern "C" { /** TOUCH_AON_PAD3_TH0_REG register * need_des */ -#define TOUCH_AON_PAD3_TH0_REG (DR_REG_TOUCH_BASE + 0x6c) +#define TOUCH_AON_PAD3_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x6c) /** TOUCH_AON_TOUCH_PAD3_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -791,7 +798,7 @@ extern "C" { /** TOUCH_AON_PAD3_TH1_REG register * need_des */ -#define TOUCH_AON_PAD3_TH1_REG (DR_REG_TOUCH_BASE + 0x70) +#define TOUCH_AON_PAD3_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x70) /** TOUCH_AON_TOUCH_PAD3_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -803,7 +810,7 @@ extern "C" { /** TOUCH_AON_PAD3_TH2_REG register * need_des */ -#define TOUCH_AON_PAD3_TH2_REG (DR_REG_TOUCH_BASE + 0x74) +#define TOUCH_AON_PAD3_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x74) /** TOUCH_AON_TOUCH_PAD3_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -815,7 +822,7 @@ extern "C" { /** TOUCH_AON_PAD4_TH0_REG register * need_des */ -#define TOUCH_AON_PAD4_TH0_REG (DR_REG_TOUCH_BASE + 0x78) +#define TOUCH_AON_PAD4_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x78) /** TOUCH_AON_TOUCH_PAD4_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -827,7 +834,7 @@ extern "C" { /** TOUCH_AON_PAD4_TH1_REG register * need_des */ -#define TOUCH_AON_PAD4_TH1_REG (DR_REG_TOUCH_BASE + 0x7c) +#define TOUCH_AON_PAD4_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x7c) /** TOUCH_AON_TOUCH_PAD4_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -839,7 +846,7 @@ extern "C" { /** TOUCH_AON_PAD4_TH2_REG register * need_des */ -#define TOUCH_AON_PAD4_TH2_REG (DR_REG_TOUCH_BASE + 0x80) +#define TOUCH_AON_PAD4_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x80) /** TOUCH_AON_TOUCH_PAD4_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -851,7 +858,7 @@ extern "C" { /** TOUCH_AON_PAD5_TH0_REG register * need_des */ -#define TOUCH_AON_PAD5_TH0_REG (DR_REG_TOUCH_BASE + 0x84) +#define TOUCH_AON_PAD5_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x84) /** TOUCH_AON_TOUCH_PAD5_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -863,7 +870,7 @@ extern "C" { /** TOUCH_AON_PAD5_TH1_REG register * need_des */ -#define TOUCH_AON_PAD5_TH1_REG (DR_REG_TOUCH_BASE + 0x88) +#define TOUCH_AON_PAD5_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x88) /** TOUCH_AON_TOUCH_PAD5_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -875,7 +882,7 @@ extern "C" { /** TOUCH_AON_PAD5_TH2_REG register * need_des */ -#define TOUCH_AON_PAD5_TH2_REG (DR_REG_TOUCH_BASE + 0x8c) +#define TOUCH_AON_PAD5_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x8c) /** TOUCH_AON_TOUCH_PAD5_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -887,7 +894,7 @@ extern "C" { /** TOUCH_AON_PAD6_TH0_REG register * need_des */ -#define TOUCH_AON_PAD6_TH0_REG (DR_REG_TOUCH_BASE + 0x90) +#define TOUCH_AON_PAD6_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x90) /** TOUCH_AON_TOUCH_PAD6_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -899,7 +906,7 @@ extern "C" { /** TOUCH_AON_PAD6_TH1_REG register * need_des */ -#define TOUCH_AON_PAD6_TH1_REG (DR_REG_TOUCH_BASE + 0x94) +#define TOUCH_AON_PAD6_TH1_REG (DR_REG_TOUCH_AON_BASE + 0x94) /** TOUCH_AON_TOUCH_PAD6_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -911,7 +918,7 @@ extern "C" { /** TOUCH_AON_PAD6_TH2_REG register * need_des */ -#define TOUCH_AON_PAD6_TH2_REG (DR_REG_TOUCH_BASE + 0x98) +#define TOUCH_AON_PAD6_TH2_REG (DR_REG_TOUCH_AON_BASE + 0x98) /** TOUCH_AON_TOUCH_PAD6_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -923,7 +930,7 @@ extern "C" { /** TOUCH_AON_PAD7_TH0_REG register * need_des */ -#define TOUCH_AON_PAD7_TH0_REG (DR_REG_TOUCH_BASE + 0x9c) +#define TOUCH_AON_PAD7_TH0_REG (DR_REG_TOUCH_AON_BASE + 0x9c) /** TOUCH_AON_TOUCH_PAD7_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -935,7 +942,7 @@ extern "C" { /** TOUCH_AON_PAD7_TH1_REG register * need_des */ -#define TOUCH_AON_PAD7_TH1_REG (DR_REG_TOUCH_BASE + 0xa0) +#define TOUCH_AON_PAD7_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xa0) /** TOUCH_AON_TOUCH_PAD7_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -947,7 +954,7 @@ extern "C" { /** TOUCH_AON_PAD7_TH2_REG register * need_des */ -#define TOUCH_AON_PAD7_TH2_REG (DR_REG_TOUCH_BASE + 0xa4) +#define TOUCH_AON_PAD7_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xa4) /** TOUCH_AON_TOUCH_PAD7_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -959,7 +966,7 @@ extern "C" { /** TOUCH_AON_PAD8_TH0_REG register * need_des */ -#define TOUCH_AON_PAD8_TH0_REG (DR_REG_TOUCH_BASE + 0xa8) +#define TOUCH_AON_PAD8_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xa8) /** TOUCH_AON_TOUCH_PAD8_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -971,7 +978,7 @@ extern "C" { /** TOUCH_AON_PAD8_TH1_REG register * need_des */ -#define TOUCH_AON_PAD8_TH1_REG (DR_REG_TOUCH_BASE + 0xac) +#define TOUCH_AON_PAD8_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xac) /** TOUCH_AON_TOUCH_PAD8_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -983,7 +990,7 @@ extern "C" { /** TOUCH_AON_PAD8_TH2_REG register * need_des */ -#define TOUCH_AON_PAD8_TH2_REG (DR_REG_TOUCH_BASE + 0xb0) +#define TOUCH_AON_PAD8_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xb0) /** TOUCH_AON_TOUCH_PAD8_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -995,7 +1002,7 @@ extern "C" { /** TOUCH_AON_PAD9_TH0_REG register * need_des */ -#define TOUCH_AON_PAD9_TH0_REG (DR_REG_TOUCH_BASE + 0xb4) +#define TOUCH_AON_PAD9_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xb4) /** TOUCH_AON_TOUCH_PAD9_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1007,7 +1014,7 @@ extern "C" { /** TOUCH_AON_PAD9_TH1_REG register * need_des */ -#define TOUCH_AON_PAD9_TH1_REG (DR_REG_TOUCH_BASE + 0xb8) +#define TOUCH_AON_PAD9_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xb8) /** TOUCH_AON_TOUCH_PAD9_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1019,7 +1026,7 @@ extern "C" { /** TOUCH_AON_PAD9_TH2_REG register * need_des */ -#define TOUCH_AON_PAD9_TH2_REG (DR_REG_TOUCH_BASE + 0xbc) +#define TOUCH_AON_PAD9_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xbc) /** TOUCH_AON_TOUCH_PAD9_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1031,7 +1038,7 @@ extern "C" { /** TOUCH_AON_PAD10_TH0_REG register * need_des */ -#define TOUCH_AON_PAD10_TH0_REG (DR_REG_TOUCH_BASE + 0xc0) +#define TOUCH_AON_PAD10_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xc0) /** TOUCH_AON_TOUCH_PAD10_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1043,7 +1050,7 @@ extern "C" { /** TOUCH_AON_PAD10_TH1_REG register * need_des */ -#define TOUCH_AON_PAD10_TH1_REG (DR_REG_TOUCH_BASE + 0xc4) +#define TOUCH_AON_PAD10_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xc4) /** TOUCH_AON_TOUCH_PAD10_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1055,7 +1062,7 @@ extern "C" { /** TOUCH_AON_PAD10_TH2_REG register * need_des */ -#define TOUCH_AON_PAD10_TH2_REG (DR_REG_TOUCH_BASE + 0xc8) +#define TOUCH_AON_PAD10_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xc8) /** TOUCH_AON_TOUCH_PAD10_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1067,7 +1074,7 @@ extern "C" { /** TOUCH_AON_PAD11_TH0_REG register * need_des */ -#define TOUCH_AON_PAD11_TH0_REG (DR_REG_TOUCH_BASE + 0xcc) +#define TOUCH_AON_PAD11_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xcc) /** TOUCH_AON_TOUCH_PAD11_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1079,7 +1086,7 @@ extern "C" { /** TOUCH_AON_PAD11_TH1_REG register * need_des */ -#define TOUCH_AON_PAD11_TH1_REG (DR_REG_TOUCH_BASE + 0xd0) +#define TOUCH_AON_PAD11_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xd0) /** TOUCH_AON_TOUCH_PAD11_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1091,7 +1098,7 @@ extern "C" { /** TOUCH_AON_PAD11_TH2_REG register * need_des */ -#define TOUCH_AON_PAD11_TH2_REG (DR_REG_TOUCH_BASE + 0xd4) +#define TOUCH_AON_PAD11_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xd4) /** TOUCH_AON_TOUCH_PAD11_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1103,7 +1110,7 @@ extern "C" { /** TOUCH_AON_PAD12_TH0_REG register * need_des */ -#define TOUCH_AON_PAD12_TH0_REG (DR_REG_TOUCH_BASE + 0xd8) +#define TOUCH_AON_PAD12_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xd8) /** TOUCH_AON_TOUCH_PAD12_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1115,7 +1122,7 @@ extern "C" { /** TOUCH_AON_PAD12_TH1_REG register * need_des */ -#define TOUCH_AON_PAD12_TH1_REG (DR_REG_TOUCH_BASE + 0xdc) +#define TOUCH_AON_PAD12_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xdc) /** TOUCH_AON_TOUCH_PAD12_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1127,7 +1134,7 @@ extern "C" { /** TOUCH_AON_PAD12_TH2_REG register * need_des */ -#define TOUCH_AON_PAD12_TH2_REG (DR_REG_TOUCH_BASE + 0xe0) +#define TOUCH_AON_PAD12_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xe0) /** TOUCH_AON_TOUCH_PAD12_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1139,7 +1146,7 @@ extern "C" { /** TOUCH_AON_PAD13_TH0_REG register * need_des */ -#define TOUCH_AON_PAD13_TH0_REG (DR_REG_TOUCH_BASE + 0xe4) +#define TOUCH_AON_PAD13_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xe4) /** TOUCH_AON_TOUCH_PAD13_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1151,7 +1158,7 @@ extern "C" { /** TOUCH_AON_PAD13_TH1_REG register * need_des */ -#define TOUCH_AON_PAD13_TH1_REG (DR_REG_TOUCH_BASE + 0xe8) +#define TOUCH_AON_PAD13_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xe8) /** TOUCH_AON_TOUCH_PAD13_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1163,7 +1170,7 @@ extern "C" { /** TOUCH_AON_PAD13_TH2_REG register * need_des */ -#define TOUCH_AON_PAD13_TH2_REG (DR_REG_TOUCH_BASE + 0xec) +#define TOUCH_AON_PAD13_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xec) /** TOUCH_AON_TOUCH_PAD13_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1175,7 +1182,7 @@ extern "C" { /** TOUCH_AON_PAD14_TH0_REG register * need_des */ -#define TOUCH_AON_PAD14_TH0_REG (DR_REG_TOUCH_BASE + 0xf0) +#define TOUCH_AON_PAD14_TH0_REG (DR_REG_TOUCH_AON_BASE + 0xf0) /** TOUCH_AON_TOUCH_PAD14_TH0 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1187,7 +1194,7 @@ extern "C" { /** TOUCH_AON_PAD14_TH1_REG register * need_des */ -#define TOUCH_AON_PAD14_TH1_REG (DR_REG_TOUCH_BASE + 0xf4) +#define TOUCH_AON_PAD14_TH1_REG (DR_REG_TOUCH_AON_BASE + 0xf4) /** TOUCH_AON_TOUCH_PAD14_TH1 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1199,7 +1206,7 @@ extern "C" { /** TOUCH_AON_PAD14_TH2_REG register * need_des */ -#define TOUCH_AON_PAD14_TH2_REG (DR_REG_TOUCH_BASE + 0xf8) +#define TOUCH_AON_PAD14_TH2_REG (DR_REG_TOUCH_AON_BASE + 0xf8) /** TOUCH_AON_TOUCH_PAD14_TH2 : R/W; bitpos: [31:16]; default: 0; * Reserved */ @@ -1211,8 +1218,8 @@ extern "C" { /** TOUCH_AON_DATE_REG register * need_des */ -#define TOUCH_AON_DATE_REG (DR_REG_TOUCH_BASE + 0xfc) -/** TOUCH_AON_DATE : R/W; bitpos: [30:0]; default: 2360864; +#define TOUCH_AON_DATE_REG (DR_REG_TOUCH_AON_BASE + 0xfc) +/** TOUCH_AON_DATE : R/W; bitpos: [30:0]; default: 38813808; * need_des */ #define TOUCH_AON_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h4/register/soc/touch_aon_struct.h b/components/soc/esp32h4/register/soc/touch_aon_struct.h index e768a1097c..bb69c774b4 100644 --- a/components/soc/esp32h4/register/soc/touch_aon_struct.h +++ b/components/soc/esp32h4/register/soc/touch_aon_struct.h @@ -63,7 +63,11 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:6; + /** freq_scan_cnt_rise : R/W; bitpos: [1:0]; default: 1; + * need_des + */ + uint32_t freq_scan_cnt_rise:2; + uint32_t reserved_2:4; /** aon_touch_timeout_num : R/W; bitpos: [21:6]; default: 65535; * need_des */ @@ -1149,7 +1153,7 @@ typedef union { */ typedef union { struct { - /** aon_date : R/W; bitpos: [30:0]; default: 2360864; + /** date : R/W; bitpos: [30:0]; default: 38813808; * need_des */ uint32_t aon_date:31; diff --git a/components/soc/esp32h4/register/soc/touch_reg.h b/components/soc/esp32h4/register/soc/touch_reg.h index 7c274eb81a..aa5322a74e 100644 --- a/components/soc/esp32h4/register/soc/touch_reg.h +++ b/components/soc/esp32h4/register/soc/touch_reg.h @@ -57,6 +57,13 @@ extern "C" { #define TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << TOUCH_APPROACH_LOOP_DONE_INT_RAW_S) #define TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U #define TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5 +/** TOUCH_BASELINE_UPDATE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * need_des + */ +#define TOUCH_BASELINE_UPDATE_INT_RAW (BIT(6)) +#define TOUCH_BASELINE_UPDATE_INT_RAW_M (TOUCH_BASELINE_UPDATE_INT_RAW_V << TOUCH_BASELINE_UPDATE_INT_RAW_S) +#define TOUCH_BASELINE_UPDATE_INT_RAW_V 0x00000001U +#define TOUCH_BASELINE_UPDATE_INT_RAW_S 6 /** TOUCH_INT_ST_REG register * need_des @@ -104,6 +111,13 @@ extern "C" { #define TOUCH_APPROACH_LOOP_DONE_INT_ST_M (TOUCH_APPROACH_LOOP_DONE_INT_ST_V << TOUCH_APPROACH_LOOP_DONE_INT_ST_S) #define TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U #define TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5 +/** TOUCH_BASELINE_UPDATE_INT_ST : RO; bitpos: [6]; default: 0; + * need_des + */ +#define TOUCH_BASELINE_UPDATE_INT_ST (BIT(6)) +#define TOUCH_BASELINE_UPDATE_INT_ST_M (TOUCH_BASELINE_UPDATE_INT_ST_V << TOUCH_BASELINE_UPDATE_INT_ST_S) +#define TOUCH_BASELINE_UPDATE_INT_ST_V 0x00000001U +#define TOUCH_BASELINE_UPDATE_INT_ST_S 6 /** TOUCH_INT_ENA_REG register * need_des @@ -151,6 +165,13 @@ extern "C" { #define TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << TOUCH_APPROACH_LOOP_DONE_INT_ENA_S) #define TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U #define TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5 +/** TOUCH_BASELINE_UPDATE_INT_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define TOUCH_BASELINE_UPDATE_INT_ENA (BIT(6)) +#define TOUCH_BASELINE_UPDATE_INT_ENA_M (TOUCH_BASELINE_UPDATE_INT_ENA_V << TOUCH_BASELINE_UPDATE_INT_ENA_S) +#define TOUCH_BASELINE_UPDATE_INT_ENA_V 0x00000001U +#define TOUCH_BASELINE_UPDATE_INT_ENA_S 6 /** TOUCH_INT_CLR_REG register * need_des @@ -198,6 +219,13 @@ extern "C" { #define TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << TOUCH_APPROACH_LOOP_DONE_INT_CLR_S) #define TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U #define TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5 +/** TOUCH_BASELINE_UPDATE_INT_CLR : WT; bitpos: [6]; default: 0; + * need_des + */ +#define TOUCH_BASELINE_UPDATE_INT_CLR (BIT(6)) +#define TOUCH_BASELINE_UPDATE_INT_CLR_M (TOUCH_BASELINE_UPDATE_INT_CLR_V << TOUCH_BASELINE_UPDATE_INT_CLR_S) +#define TOUCH_BASELINE_UPDATE_INT_CLR_V 0x00000001U +#define TOUCH_BASELINE_UPDATE_INT_CLR_S 6 /** TOUCH_CHN_STATUS_REG register * need_des diff --git a/components/soc/esp32h4/register/soc/touch_struct.h b/components/soc/esp32h4/register/soc/touch_struct.h index 22dd9ea846..fe29b6cb54 100644 --- a/components/soc/esp32h4/register/soc/touch_struct.h +++ b/components/soc/esp32h4/register/soc/touch_struct.h @@ -40,7 +40,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_raw:1; - uint32_t reserved_6:26; + /** baseline_update_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * need_des + */ + uint32_t baseline_update_int_raw:1; + uint32_t reserved_7:25; }; uint32_t val; } touch_int_raw_reg_t; @@ -74,7 +78,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_st:1; - uint32_t reserved_6:26; + /** baseline_update_int_st : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t baseline_update_int_st:1; + uint32_t reserved_7:25; }; uint32_t val; } touch_int_st_reg_t; @@ -108,7 +116,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_ena:1; - uint32_t reserved_6:26; + /** baseline_update_int_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t baseline_update_int_ena:1; + uint32_t reserved_7:25; }; uint32_t val; } touch_int_ena_reg_t; @@ -142,7 +154,11 @@ typedef union { * need_des */ uint32_t approach_loop_done_int_clr:1; - uint32_t reserved_6:26; + /** baseline_update_int_clr : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t baseline_update_int_clr:1; + uint32_t reserved_7:25; }; uint32_t val; } touch_int_clr_reg_t;