Fix function prototypes

components/esp32s2beta/brownout.c

@@ -31,7 +31,7 @@
 #define BROWNOUT_DET_LVL 0
 #endif //CONFIG_ESP32S2_BROWNOUT_DET_LVL
 
-static void rtc_brownout_isr_handler()
+static void rtc_brownout_isr_handler(void *arg)
 {
     /* Normally RTC ISR clears the interrupt flag after the application-supplied
      * handler returns. Since restart is called here, the flag needs to be
@@ -46,7 +46,7 @@ static void rtc_brownout_isr_handler()
     esp_restart_noos();
 }
 
-void esp_brownout_init()
+void esp_brownout_init(void)
 {
 // TODO: implement brownout threshold configuration for esp32s2beta - IDF-751
 

components/esp32s2beta/cache_err_int.c

@@ -32,7 +32,7 @@
 #include "sdkconfig.h"
 #include "esp32s2beta/dport_access.h"
 
-void esp_cache_err_int_init()
+void esp_cache_err_int_init(void)
 {
     uint32_t core_id = xPortGetCoreID();
     ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
@@ -64,7 +64,7 @@ void esp_cache_err_int_init()
     ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
 }
 
-int IRAM_ATTR esp_cache_err_get_cpuid()
+int IRAM_ATTR esp_cache_err_get_cpuid(void)
 {
     return PRO_CPU_NUM;
 }

components/esp32s2beta/clk.c

@@ -169,7 +169,7 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
     esp_clk_slowclk_cal_set(cal_val);
 }
 
-void rtc_clk_select_rtc_slow_clk()
+void rtc_clk_select_rtc_slow_clk(void)
 {
     select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
 }

components/esp32s2beta/cpu_start.c

@@ -106,7 +106,7 @@ static bool s_spiram_okay=true;
  * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
  */
 
-void IRAM_ATTR call_start_cpu0()
+void IRAM_ATTR call_start_cpu0(void)
 {
     RESET_REASON rst_reas;
 
@@ -347,7 +347,7 @@ void start_cpu0_default(void)
 }
 
 #ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
-size_t __cxx_eh_arena_size_get()
+size_t __cxx_eh_arena_size_get(void)
 {
     return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE;
 }

components/esp32s2beta/crosscore_int.c

@@ -46,7 +46,7 @@ static volatile uint32_t reason[ portNUM_PROCESSORS ];
 ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
 the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
 */
-static inline void IRAM_ATTR esp_crosscore_isr_handle_yield()
+static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
 {
     portYIELD_FROM_ISR();
 }
@@ -82,7 +82,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
 
 //Initialize the crosscore interrupt on this core. Call this once
 //on each active core.
-void esp_crosscore_int_init() {
+void esp_crosscore_int_init(void) {
     portENTER_CRITICAL(&reason_spinlock);
     reason[xPortGetCoreID()]=0;
     portEXIT_CRITICAL(&reason_spinlock);

components/esp32s2beta/esp_clk_internal.h

@@ -41,4 +41,4 @@ void esp_perip_clk_init(void);
 /* Selects an external clock source (32 kHz) for RTC.
  * Only internal use in unit test.
  */
-void rtc_clk_select_rtc_slow_clk();
+void rtc_clk_select_rtc_slow_clk(void);

components/esp32s2beta/esp_timer_esp32s2beta.c

@@ -151,7 +151,7 @@ portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED;
 #define TIMER_IS_AFTER_OVERFLOW(a) (ALARM_OVERFLOW_VAL < (a) && (a) <= FRC_TIMER_LOAD_VALUE(1))
 
 // Check if timer overflow has happened (but was not handled by ISR yet)
-static inline bool IRAM_ATTR timer_overflow_happened()
+static inline bool IRAM_ATTR timer_overflow_happened(void)
 {
     if (s_overflow_happened) {
         return true;
@@ -177,17 +177,17 @@ static inline void IRAM_ATTR timer_count_reload(void)
     REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL);
 }
 
-void esp_timer_impl_lock()
+void esp_timer_impl_lock(void)
 {
     portENTER_CRITICAL(&s_time_update_lock);
 }
 
-void esp_timer_impl_unlock()
+void esp_timer_impl_unlock(void)
 {
     portEXIT_CRITICAL(&s_time_update_lock);
 }
 
-uint64_t IRAM_ATTR esp_timer_impl_get_time()
+uint64_t IRAM_ATTR esp_timer_impl_get_time(void)
 {
     uint32_t timer_val;
     uint64_t time_base;
@@ -372,7 +372,7 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
     return ESP_OK;
 }
 
-void esp_timer_impl_deinit()
+void esp_timer_impl_deinit(void)
 {
     esp_intr_disable(s_timer_interrupt_handle);
 
@@ -387,13 +387,13 @@ void esp_timer_impl_deinit()
 // FIXME: This value is safe for 80MHz APB frequency.
 // Should be modified to depend on clock frequency.
 
-uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us()
+uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void)
 {
     return 50;
 }
 
 #ifdef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
-uint32_t esp_timer_impl_get_overflow_val()
+uint32_t esp_timer_impl_get_overflow_val(void)
 {
     return s_alarm_overflow_val;
 }

components/esp32s2beta/include/esp32s2beta/brownout.h

@@ -16,6 +16,6 @@
 #ifndef __ESP_BROWNOUT_H
 #define __ESP_BROWNOUT_H
 
-void esp_brownout_init();
+void esp_brownout_init(void);
 
 #endif

components/esp32s2beta/include/esp32s2beta/cache_err_int.h

@@ -20,7 +20,7 @@
  * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
  * from the startup code.
  */
-void esp_cache_err_int_init();
+void esp_cache_err_int_init(void);
 
 
 /**
@@ -30,4 +30,4 @@ void esp_cache_err_int_init();
  *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
  *  - (-1) otherwise
  */
-int esp_cache_err_get_cpuid();
+int esp_cache_err_get_cpuid(void);

components/esp32s2beta/include/esp32s2beta/clk.h

@@ -28,7 +28,7 @@
  *
  * @return the calibration value obtained using rtc_clk_cal, at startup time
  */
-uint32_t esp_clk_slowclk_cal_get();
+uint32_t esp_clk_slowclk_cal_get(void);
 
 /**
  * @brief Update the calibration value of RTC slow clock
@@ -72,4 +72,4 @@ int esp_clk_apb_freq(void);
  *
  * @return Value or RTC counter, expressed in microseconds
  */
-uint64_t esp_clk_rtc_time();
+uint64_t esp_clk_rtc_time(void);

components/esp32s2beta/include/esp32s2beta/spiram.h

@@ -26,7 +26,7 @@
  *
  * @return ESP_OK on success
  */
-esp_err_t esp_spiram_init();
+esp_err_t esp_spiram_init(void);
 
 /**
  * @brief Configure Cache/MMU for access to external SPI RAM.
@@ -37,7 +37,7 @@ esp_err_t esp_spiram_init();
  *
  * @attention this function must be called with flash cache disabled.
  */
-void esp_spiram_init_cache();
+void esp_spiram_init_cache(void);
 
 
 /**
@@ -48,13 +48,13 @@ void esp_spiram_init_cache();
  *
  * @return true on success, false on failed memory test
  */
-bool esp_spiram_test();
+bool esp_spiram_test(void);
 
 
 /**
  * @brief Add the initialized SPI RAM to the heap allocator.
  */
-esp_err_t esp_spiram_add_to_heapalloc();
+esp_err_t esp_spiram_add_to_heapalloc(void);
 
 
 /**
@@ -62,7 +62,7 @@ esp_err_t esp_spiram_add_to_heapalloc();
  *
  * @return Size in bytes, or 0 if no external RAM chip support compiled in.
  */
-size_t esp_spiram_get_size();
+size_t esp_spiram_get_size(void);
 
 
 /**
@@ -72,7 +72,7 @@ size_t esp_spiram_get_size();
  *
  * This is meant for use from within the SPI flash code.
  */
-void esp_spiram_writeback_cache();
+void esp_spiram_writeback_cache(void);
 
 
 

components/esp32s2beta/include/esp_clk.h

@@ -28,7 +28,7 @@
  *
  * @return the calibration value obtained using rtc_clk_cal, at startup time
  */
-uint32_t esp_clk_slowclk_cal_get();
+uint32_t esp_clk_slowclk_cal_get(void);
 
 /**
  * @brief Update the calibration value of RTC slow clock
@@ -72,4 +72,4 @@ int esp_clk_apb_freq(void);
  *
  * @return Value or RTC counter, expressed in microseconds
  */
-uint64_t esp_clk_rtc_time();
+uint64_t esp_clk_rtc_time(void);

components/esp32s2beta/include/esp_intr_alloc.h

@@ -281,13 +281,13 @@ esp_err_t esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram);
 /**
  * @brief Disable interrupts that aren't specifically marked as running from IRAM
  */
-void esp_intr_noniram_disable();
+void esp_intr_noniram_disable(void);
 
 
 /**
  * @brief Re-enable interrupts disabled by esp_intr_noniram_disable
  */
-void esp_intr_noniram_enable();
+void esp_intr_noniram_enable(void);
 
 /**@}*/
 

components/esp32s2beta/include/esp_sleep.h

@@ -94,7 +94,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
  *      - ESP_OK on success
  *      - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
  */
-esp_err_t esp_sleep_enable_ulp_wakeup();
+esp_err_t esp_sleep_enable_ulp_wakeup(void);
 
 /**
  * @brief Enable wakeup by timer
@@ -120,7 +120,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
  *      - ESP_OK on success
  *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
  */
-esp_err_t esp_sleep_enable_touchpad_wakeup();
+esp_err_t esp_sleep_enable_touchpad_wakeup(void);
 
 /**
  * @brief Get the touch pad which caused wakeup
@@ -129,7 +129,7 @@ esp_err_t esp_sleep_enable_touchpad_wakeup();
  *
  * @return touch pad which caused wakeup
  */
-touch_pad_t esp_sleep_get_touchpad_wakeup_status();
+touch_pad_t esp_sleep_get_touchpad_wakeup_status(void);
 
 /**
  * @brief Enable wakeup using a pin
@@ -197,7 +197,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
  *
  * @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
  */
-uint64_t esp_sleep_get_ext1_wakeup_status();
+uint64_t esp_sleep_get_ext1_wakeup_status(void);
 
 /**
  * @brief Set power down mode for an RTC power domain in sleep mode
@@ -218,7 +218,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
  *
  * This function does not return.
  */
-void esp_deep_sleep_start() __attribute__((noreturn));
+void esp_deep_sleep_start(void) __attribute__((noreturn));
 
 /**
  * @brief Enter light sleep with the configured wakeup options
@@ -227,7 +227,7 @@ void esp_deep_sleep_start() __attribute__((noreturn));
  *  - ESP_OK on success (returned after wakeup)
  *  - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped
  */
-esp_err_t esp_light_sleep_start();
+esp_err_t esp_light_sleep_start(void);
 
 /**
  * @brief Enter deep-sleep mode
@@ -269,7 +269,7 @@ void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated)
  *
  * @return wakeup cause, or ESP_DEEP_SLEEP_WAKEUP_UNDEFINED if reset happened for reason other than deep sleep wakeup
  */
-esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause();
+esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void);
 
 
 /**

components/esp32s2beta/include/esp_spiram.h

@@ -25,7 +25,7 @@
  *
  * @return ESP_OK on success
  */
-esp_err_t esp_spiram_init();
+esp_err_t esp_spiram_init(void);
 
 /**
  * @brief Configure Cache/MMU for access to external SPI RAM.
@@ -36,7 +36,7 @@ esp_err_t esp_spiram_init();
  *
  * @attention this function must be called with flash cache disabled.
  */
-void esp_spiram_init_cache();
+void esp_spiram_init_cache(void);
 
 
 /**
@@ -47,13 +47,13 @@ void esp_spiram_init_cache();
  *
  * @return true on success, false on failed memory test
  */
-bool esp_spiram_test();
+bool esp_spiram_test(void);
 
 
 /**
  * @brief Add the initialized SPI RAM to the heap allocator.
  */
-esp_err_t esp_spiram_add_to_heapalloc();
+esp_err_t esp_spiram_add_to_heapalloc(void);
 
 
 /**
@@ -61,7 +61,7 @@ esp_err_t esp_spiram_add_to_heapalloc();
  *
  * @return Size in bytes, or 0 if no external RAM chip support compiled in.
  */
-size_t esp_spiram_get_size();
+size_t esp_spiram_get_size(void);
 
 
 /**
@@ -71,7 +71,7 @@ size_t esp_spiram_get_size();
  *
  * This is meant for use from within the SPI flash code.
  */
-void esp_spiram_writeback_cache();
+void esp_spiram_writeback_cache(void);
 
 
 

components/esp32s2beta/int_wdt.c

@@ -70,7 +70,7 @@ static void IRAM_ATTR tick_hook(void) {
 #endif
 
 
-void esp_int_wdt_init() {
+void esp_int_wdt_init(void) {
     periph_module_enable(PERIPH_TIMG1_MODULE);
     TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG1.wdt_config0.sys_reset_length=7;                 //3.2uS
@@ -90,7 +90,7 @@ void esp_int_wdt_init() {
     timer_group_intr_enable(TIMER_GROUP_1, TIMG_WDT_INT_ENA_M);
 }
 
-void esp_int_wdt_cpu_init()
+void esp_int_wdt_cpu_init(void)
 {
     esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
     ESP_INTR_DISABLE(WDT_INT_NUM);

components/esp32s2beta/intr_alloc.c

@@ -841,7 +841,7 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
 }
 
 
-void IRAM_ATTR esp_intr_noniram_disable()
+void IRAM_ATTR esp_intr_noniram_disable(void)
 {
     int oldint;
     int cpu=xPortGetCoreID();
@@ -860,7 +860,7 @@ void IRAM_ATTR esp_intr_noniram_disable()
     non_iram_int_disabled[cpu]=oldint&non_iram_int_mask[cpu];
 }
 
-void IRAM_ATTR esp_intr_noniram_enable()
+void IRAM_ATTR esp_intr_noniram_enable(void)
 {
     int cpu=xPortGetCoreID();
     int intmask=non_iram_int_disabled[cpu];

components/esp32s2beta/panic.c

@@ -125,7 +125,7 @@ void  __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, s
 
 static bool abort_called;
 
-static __attribute__((noreturn)) inline void invoke_abort()
+static __attribute__((noreturn)) inline void invoke_abort(void)
 {
     abort_called = true;
 #if CONFIG_ESP32_APPTRACE_ENABLE
@@ -144,7 +144,7 @@ static __attribute__((noreturn)) inline void invoke_abort()
     }
 }
 
-void abort()
+void abort(void)
 {
 #if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
     ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
@@ -169,11 +169,11 @@ static const char *edesc[] = {
 #define NUM_EDESCS (sizeof(edesc) / sizeof(char *))
 
 static void commonErrorHandler(XtExcFrame *frame);
-static inline void disableAllWdts();
+static inline void disableAllWdts(void);
 
 //The fact that we've panic'ed probably means the other CPU is now running wild, possibly
 //messing up the serial output, so we stall it here.
-static void haltOtherCore()
+static void haltOtherCore(void)
 {
     esp_cpu_stall( xPortGetCoreID() == 0 ? 1 : 0 );
 }
@@ -349,7 +349,7 @@ void xt_unhandled_exception(XtExcFrame *frame)
   all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
   one second.
 */
-static void reconfigureAllWdts()
+static void reconfigureAllWdts(void)
 {
     TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
     TIMERG0.wdt_feed = 1;
@@ -369,7 +369,7 @@ static void reconfigureAllWdts()
 /*
   This disables all the watchdogs for when we call the gdbstub.
 */
-static inline void disableAllWdts()
+static inline void disableAllWdts(void)
 {
     TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
     TIMERG0.wdt_config0.en = 0;
@@ -379,7 +379,7 @@ static inline void disableAllWdts()
     TIMERG1.wdt_wprotect = 0;
 }
 
-static void esp_panic_wdt_start()
+static void esp_panic_wdt_start(void)
 {
     if (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN)) {
         return;
@@ -396,7 +396,7 @@ static void esp_panic_wdt_start()
     WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
 }
 
-void esp_panic_wdt_stop()
+void esp_panic_wdt_stop(void)
 {
     WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
     WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
@@ -405,9 +405,9 @@ void esp_panic_wdt_stop()
     WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
 }
 
-static void esp_panic_dig_reset() __attribute__((noreturn));
+static void esp_panic_dig_reset(void) __attribute__((noreturn));
 
-static void esp_panic_dig_reset()
+static void esp_panic_dig_reset(void)
 {
     // make sure all the panic handler output is sent from UART FIFO
     uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);

components/esp32s2beta/pm_esp32s2beta.c

@@ -146,9 +146,9 @@ static const char* s_mode_names[] = {
 
 static const char* TAG = "pm_esp32";
 
-static void update_ccompare();
+static void update_ccompare(void);
 static void do_switch(pm_mode_t new_mode);
-static void leave_idle();
+static void leave_idle(void);
 static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
 
 
@@ -242,7 +242,7 @@ esp_err_t esp_pm_configure(const void* vconfig)
     return ESP_OK;
 }
 
-static pm_mode_t IRAM_ATTR get_lowest_allowed_mode()
+static pm_mode_t IRAM_ATTR get_lowest_allowed_mode(void)
 {
     /* TODO: optimize using ffs/clz */
     if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
@@ -413,7 +413,7 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
  * would happen without the frequency change.
  * Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
  */
-static void IRAM_ATTR update_ccompare()
+static void IRAM_ATTR update_ccompare(void)
 {
     uint32_t ccount = XTHAL_GET_CCOUNT();
     uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
@@ -427,7 +427,7 @@ static void IRAM_ATTR update_ccompare()
     }
 }
 
-static void IRAM_ATTR leave_idle()
+static void IRAM_ATTR leave_idle(void)
 {
     int core_id = xPortGetCoreID();
     if (s_core_idle[core_id]) {
@@ -437,7 +437,7 @@ static void IRAM_ATTR leave_idle()
     }
 }
 
-void esp_pm_impl_idle_hook()
+void esp_pm_impl_idle_hook(void)
 {
     int core_id = xPortGetCoreID();
     uint32_t state = portENTER_CRITICAL_NESTED();
@@ -449,7 +449,7 @@ void esp_pm_impl_idle_hook()
     ESP_PM_TRACE_ENTER(IDLE, core_id);
 }
 
-void esp_pm_impl_waiti()
+void esp_pm_impl_waiti(void)
 {
 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
     int core_id = xPortGetCoreID();
@@ -467,7 +467,7 @@ void esp_pm_impl_waiti()
 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
 }
 
-void IRAM_ATTR esp_pm_impl_isr_hook()
+void IRAM_ATTR esp_pm_impl_isr_hook(void)
 {
     int core_id = xPortGetCoreID();
     ESP_PM_TRACE_ENTER(ISR_HOOK, core_id);
@@ -563,7 +563,7 @@ void esp_pm_impl_dump_stats(FILE* out)
 }
 #endif // WITH_PROFILING
 
-void esp_pm_impl_init()
+void esp_pm_impl_init(void)
 {
     s_cpu_freq_to_ticks[RTC_CPU_FREQ_XTAL] = rtc_clk_xtal_freq_get();
 #ifdef CONFIG_PM_TRACE

components/esp32s2beta/pm_trace.c

@@ -30,7 +30,7 @@ static const int DRAM_ATTR s_trace_io[] = {
         BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP
 };
 
-void esp_pm_trace_init()
+void esp_pm_trace_init(void)
 {
     for (size_t i = 0; i < sizeof(s_trace_io)/sizeof(s_trace_io[0]); ++i) {
         int io = __builtin_ffs(s_trace_io[i]);

components/esp32s2beta/sleep_modes.c

@@ -87,10 +87,10 @@ static _lock_t lock_rtc_memory_crc;
 
 static const char* TAG = "sleep";
 
-static uint32_t get_power_down_flags();
-static void ext0_wakeup_prepare();
-static void ext1_wakeup_prepare();
-static void timer_wakeup_prepare();
+static uint32_t get_power_down_flags(void);
+static void ext0_wakeup_prepare(void);
+static void ext1_wakeup_prepare(void);
+static void timer_wakeup_prepare(void);
 
 /* Wake from deep sleep stub
    See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
@@ -133,7 +133,7 @@ void esp_deep_sleep(uint64_t time_in_us)
     esp_deep_sleep_start();
 }
 
-static void IRAM_ATTR suspend_uarts()
+static void IRAM_ATTR suspend_uarts(void)
 {
     for (int i = 0; i < 2; ++i) {
         REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
@@ -141,7 +141,7 @@ static void IRAM_ATTR suspend_uarts()
     }
 }
 
-static void IRAM_ATTR resume_uarts()
+static void IRAM_ATTR resume_uarts(void)
 {
     for (int i = 0; i < 2; ++i) {
         REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
@@ -192,7 +192,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
     return result;
 }
 
-void IRAM_ATTR esp_deep_sleep_start()
+void IRAM_ATTR esp_deep_sleep_start(void)
 {
     // record current RTC time
     s_config.rtc_ticks_at_sleep_start = rtc_time_get();
@@ -230,7 +230,7 @@ static void rtc_wdt_enable(int time_ms)
     WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
 }
 
-static void rtc_wdt_disable()
+static void rtc_wdt_disable(void)
 {
     WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
     WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
@@ -268,7 +268,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
     return err;
 }
 
-esp_err_t esp_light_sleep_start()
+esp_err_t esp_light_sleep_start(void)
 {
     static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL(&light_sleep_lock);
@@ -367,7 +367,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
     return ESP_OK;
 }
 
-esp_err_t esp_sleep_enable_ulp_wakeup()
+esp_err_t esp_sleep_enable_ulp_wakeup(void)
 {
     return ESP_ERR_NOT_SUPPORTED;
 }
@@ -379,7 +379,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
     return ESP_OK;
 }
 
-static void timer_wakeup_prepare()
+static void timer_wakeup_prepare(void)
 {
     uint32_t period = esp_clk_slowclk_cal_get();
     int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
@@ -391,7 +391,7 @@ static void timer_wakeup_prepare()
     rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + rtc_count_delta);
 }
 
-esp_err_t esp_sleep_enable_touchpad_wakeup()
+esp_err_t esp_sleep_enable_touchpad_wakeup(void)
 {
     if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
         ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
@@ -401,7 +401,7 @@ esp_err_t esp_sleep_enable_touchpad_wakeup()
     return ESP_OK;
 }
 
-touch_pad_t esp_sleep_get_touchpad_wakeup_status()
+touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
 {
     if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
         return TOUCH_PAD_MAX;
@@ -430,7 +430,7 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
     return ESP_OK;
 }
 
-static void ext0_wakeup_prepare()
+static void ext0_wakeup_prepare(void)
 {
     int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
     // Set GPIO to be used for wakeup
@@ -472,7 +472,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
     return ESP_OK;
 }
 
-static void ext1_wakeup_prepare()
+static void ext1_wakeup_prepare(void)
 {
     // Configure all RTC IOs selected as ext1 wakeup inputs
     uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
@@ -508,7 +508,7 @@ static void ext1_wakeup_prepare()
             s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
 }
 
-uint64_t esp_sleep_get_ext1_wakeup_status()
+uint64_t esp_sleep_get_ext1_wakeup_status(void)
 {
     if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
         return 0;
@@ -529,7 +529,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status()
     return gpio_mask;
 }
 
-esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause()
+esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
 {
     if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
         return ESP_SLEEP_WAKEUP_UNDEFINED;
@@ -561,7 +561,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
     return ESP_OK;
 }
 
-static uint32_t get_power_down_flags()
+static uint32_t get_power_down_flags(void)
 {
     // Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
 

components/esp32s2beta/spiram.c

@@ -68,7 +68,7 @@ static bool spiram_inited=false;
  true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
  initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
 */
-bool esp_spiram_test()
+bool esp_spiram_test(void)
 {
     volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - CONFIG_SPIRAM_SIZE);
     size_t p;
@@ -128,7 +128,7 @@ bool esp_spiram_test()
 #define SPIRAM_MID_BIG_SIZE_MAP_SIZE            DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE
 
 
-void IRAM_ATTR esp_spiram_init_cache()
+void IRAM_ATTR esp_spiram_init_cache(void)
 {
     Cache_Suspend_DCache();
     /* map the address from SPIRAM end to the start, map the address in order: DRAM1, DRAM1, DPORT, DBUS3 */
@@ -175,12 +175,12 @@ static uint32_t page0_page = 0xffff;
 static uint32_t instrcution_in_spiram = 0;
 static uint32_t rodata_in_spiram = 0;
 
-uint32_t esp_spiram_instruction_access_enabled()
+uint32_t esp_spiram_instruction_access_enabled(void)
 {
     return instrcution_in_spiram;
 }
 
-uint32_t esp_spiram_rodata_access_enabled()
+uint32_t esp_spiram_rodata_access_enabled(void)
 {
     return rodata_in_spiram;
 }
@@ -233,7 +233,7 @@ esp_err_t esp_spiram_enable_rodata_access(void)
     return ESP_OK;
 }
 
-esp_err_t esp_spiram_init()
+esp_err_t esp_spiram_init(void)
 {
     esp_err_t r;
     r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
@@ -256,7 +256,7 @@ esp_err_t esp_spiram_init()
 }
 
 
-esp_err_t esp_spiram_add_to_heapalloc()
+esp_err_t esp_spiram_add_to_heapalloc(void)
 {
     uint32_t size_for_flash = (pages_for_flash << 16);
     ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (CONFIG_SPIRAM_SIZE - (pages_for_flash << 16))/1024);
@@ -319,7 +319,7 @@ esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
     return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+size-1);
 }
 
-size_t esp_spiram_get_size()
+size_t esp_spiram_get_size(void)
 {
     return CONFIG_SPIRAM_SIZE;
 }
@@ -328,7 +328,7 @@ size_t esp_spiram_get_size()
  Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
  otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
 */
-void IRAM_ATTR esp_spiram_writeback_cache()
+void IRAM_ATTR esp_spiram_writeback_cache(void)
 {
     extern void Cache_WriteBack_All(void);
     int cache_was_disabled=0;

components/esp32s2beta/spiram_psram.c

@@ -698,7 +698,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
     PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK);
 }
 
-psram_size_t psram_get_size()
+psram_size_t psram_get_size(void)
 {
     if (PSRAM_IS_32MBIT_VER0(s_psram_id)) {
         return PSRAM_SIZE_32MBITS;

components/esp32s2beta/spiram_psram.h

@@ -53,7 +53,7 @@ typedef enum {
  *     - PSRAM_SIZE_MAX if psram not enabled or not valid
  *     - PSRAM size
  */
-psram_size_t psram_get_size();
+psram_size_t psram_get_size(void);
 
 /**
  * @brief psram cache enable function

components/esp32s2beta/system_api.c

@@ -44,7 +44,7 @@ static uint8_t base_mac_addr[6] = { 0 };
 #define SHUTDOWN_HANDLERS_NO 2
 static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
 
-void system_init()
+void system_init(void)
 {
 }
 
@@ -227,7 +227,7 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
     return ESP_ERR_INVALID_STATE;
 }
 
-void esp_restart_noos() __attribute__ ((noreturn));
+void esp_restart_noos(void) __attribute__ ((noreturn));
 
 void IRAM_ATTR esp_restart(void)
 {
@@ -248,7 +248,7 @@ void IRAM_ATTR esp_restart(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos()
+void IRAM_ATTR esp_restart_noos(void)
 {
     // Disable interrupts
     xt_ints_off(0xFFFFFFFF);

components/esp32s2beta/task_wdt.c

@@ -102,7 +102,7 @@ static twdt_task_t *find_task_in_twdt_list(TaskHandle_t handle, bool *all_reset)
  * Resets the hardware timer and has_reset flags of each task on the list.
  * Called within critical
  */
-static void reset_hw_timer()
+static void reset_hw_timer(void)
 {
     //All tasks have reset; time to reset the hardware timer.
     TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
@@ -214,7 +214,7 @@ esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
     return ESP_OK;
 }
 
-esp_err_t esp_task_wdt_deinit()
+esp_err_t esp_task_wdt_deinit(void)
 {
     portENTER_CRITICAL(&twdt_spinlock);
     //TWDT must already be initialized
@@ -282,7 +282,7 @@ esp_err_t esp_task_wdt_add(TaskHandle_t handle)
     return ESP_OK;
 }
 
-esp_err_t esp_task_wdt_reset()
+esp_err_t esp_task_wdt_reset(void)
 {
     portENTER_CRITICAL(&twdt_spinlock);
     //TWDT must already be initialized
@@ -370,7 +370,7 @@ esp_err_t esp_task_wdt_status(TaskHandle_t handle)
     return ESP_ERR_NOT_FOUND;
 }
 
-void esp_task_wdt_feed()
+void esp_task_wdt_feed(void)
 {
     portENTER_CRITICAL(&twdt_spinlock);
     //Return immediately if TWDT has not been initialized