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Fix function prototypes

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This commit is contained in:
Angus Gratton
2019-08-12 12:06:07 +10:00
committed by Angus Gratton
parent c47e1756f8
commit 18c5cfadae
46 changed files with 189 additions and 189 deletions
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components/esp_rom/include/esp32s2beta/rom/cache.h
+6 -6
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@@ -798,7 +798,7 @@ void Cache_Resume_DCache(uint32_t autoload);
*
* @return None
*/
void Cache_Drom0_Source_ICache();
void Cache_Drom0_Source_ICache(void);
/**
* @brief Make Drom0 bus access from DCache.
@@ -807,7 +807,7 @@ void Cache_Drom0_Source_ICache();
*
* @return None
*/
void Cache_Drom0_Source_DCache();
void Cache_Drom0_Source_DCache(void);
/**
* @brief Return if Drom0 bus access from ICache.
@@ -816,7 +816,7 @@ void Cache_Drom0_Source_DCache();
*
* @return uint32_t: 0 for no, other for yes
*/
uint32_t Cache_Drom0_Using_ICache();
uint32_t Cache_Drom0_Using_ICache(void);
/**
* @brief Return if Drom0 bus access from DCache.
@@ -825,7 +825,7 @@ uint32_t Cache_Drom0_Using_ICache();
*
* @return uint32_t: 0 for no, other for yes
*/
uint32_t Cache_Drom0_Using_DCache();
uint32_t Cache_Drom0_Using_DCache(void);
/**
* @brief Get ICache cache line size
@@ -834,7 +834,7 @@ uint32_t Cache_Drom0_Using_DCache();
*
* @return uint32_t: 16, 32, 64 Byte
*/
uint32_t Cache_Get_ICache_Line_Size();
uint32_t Cache_Get_ICache_Line_Size(void);
/**
* @brief Get DCache cache line size
@@ -843,7 +843,7 @@ uint32_t Cache_Get_ICache_Line_Size();
*
* @return uint32_t: 16, 32, 64 Byte
*/
uint32_t Cache_Get_DCache_Line_Size();
uint32_t Cache_Get_DCache_Line_Size(void);
/**
* @brief Set default mode from boot.
components/esp_rom/include/esp32s2beta/rom/spi_flash.h
+2 -2
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@@ -511,8 +511,8 @@ typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void* data, uint32_t len);
void SPI_Write_Encrypt_Enable();
void SPI_Write_Encrypt_Disable();
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*
components/esp_rom/include/esp32s2beta/rom/tbconsole.h
+1 -1
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@@ -18,7 +18,7 @@
extern "C" {
#endif
void start_tb_console();
void start_tb_console(void);
#ifdef __cplusplus
}