mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-03 00:21:44 +01:00
feat: enabled aes and sha support for esp32c5
This commit enabled AES and SHA support for esp32c5.
This commit is contained in:
@@ -59,10 +59,18 @@ config SOC_SYSTIMER_SUPPORTED
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bool
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default y
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config SOC_AES_SUPPORTED
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bool
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default y
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config SOC_MPI_SUPPORTED
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bool
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default y
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config SOC_SHA_SUPPORTED
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bool
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default y
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config SOC_RSA_SUPPORTED
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bool
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default y
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@@ -107,6 +115,22 @@ config SOC_XTAL_SUPPORT_48M
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bool
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default y
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config SOC_AES_SUPPORT_DMA
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bool
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default y
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config SOC_AES_GDMA
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bool
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default y
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config SOC_AES_SUPPORT_AES_128
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bool
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default y
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config SOC_AES_SUPPORT_AES_256
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bool
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default y
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config SOC_ADC_PERIPH_NUM
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int
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default 1
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@@ -363,6 +387,34 @@ config SOC_RSA_MAX_BIT_LEN
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int
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default 3072
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config SOC_SHA_DMA_MAX_BUFFER_SIZE
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int
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default 3968
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config SOC_SHA_SUPPORT_DMA
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bool
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default y
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config SOC_SHA_SUPPORT_RESUME
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bool
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default y
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config SOC_SHA_GDMA
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bool
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default y
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config SOC_SHA_SUPPORT_SHA1
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bool
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default y
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config SOC_SHA_SUPPORT_SHA224
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bool
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default y
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config SOC_SHA_SUPPORT_SHA256
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bool
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default y
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config SOC_SPI_PERIPH_NUM
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int
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default 2
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -45,9 +45,9 @@
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// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684
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#define SOC_I2C_SUPPORTED 1
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#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
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// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627
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#define SOC_AES_SUPPORTED 1
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#define SOC_MPI_SUPPORTED 1
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// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624
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#define SOC_SHA_SUPPORTED 1
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#define SOC_RSA_SUPPORTED 1
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// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616
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// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619
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@@ -83,13 +83,13 @@
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#define SOC_XTAL_SUPPORT_48M 1
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/*-------------------------- AES CAPS -----------------------------------------*/
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// #define SOC_AES_SUPPORT_DMA (1)
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#define SOC_AES_SUPPORT_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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// #define SOC_AES_GDMA (1)
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#define SOC_AES_GDMA (1)
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// #define SOC_AES_SUPPORT_AES_128 (1)
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// #define SOC_AES_SUPPORT_AES_256 (1)
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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@@ -353,19 +353,19 @@
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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// #define SOC_SHA_SUPPORT_DMA (1)
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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// #define SOC_SHA_SUPPORT_RESUME (1)
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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// #define SOC_SHA_GDMA (1)
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#define SOC_SHA_GDMA (1)
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/* Supported HW algorithms */
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// #define SOC_SHA_SUPPORT_SHA1 (1)
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// #define SOC_SHA_SUPPORT_SHA224 (1)
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// #define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*--------------------------- ECDSA CAPS ---------------------------------------*/
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// #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
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12
components/soc/esp32c5/mp/include/soc/hwcrypto_reg.h
Normal file
12
components/soc/esp32c5/mp/include/soc/hwcrypto_reg.h
Normal file
@@ -0,0 +1,12 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/aes_reg.h"
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#include "soc/ds_reg.h"
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#include "soc/hmac_reg.h"
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#include "soc/rsa_reg.h"
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#include "soc/sha_reg.h"
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