diff --git a/components/esp32/system_api_esp32.c b/components/esp32/system_api_esp32.c
index 04972ce7e5..658c9f313f 100644
--- a/components/esp32/system_api_esp32.c
+++ b/components/esp32/system_api_esp32.c
@@ -116,7 +116,7 @@ void IRAM_ATTR esp_restart_noos(void)
     // Reset timer/spi/uart
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
             //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
-            DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); 
+            DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); 
     DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
 
     // Set CPU back to XTAL source, no PLL, same as hard reset
diff --git a/components/esp32s2/system_api_esp32s2.c b/components/esp32s2/system_api_esp32s2.c
index 3112823c40..bad5c7bb61 100644
--- a/components/esp32s2/system_api_esp32s2.c
+++ b/components/esp32s2/system_api_esp32s2.c
@@ -95,7 +95,7 @@ void IRAM_ATTR esp_restart_noos(void)
 
     // Reset timer/spi/uart
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
-                            DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
+                            DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST);
     DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
 
     // Set CPU back to XTAL source, no PLL, same as hard reset
diff --git a/components/esp_system/port/esp32s2/clk.c b/components/esp_system/port/esp32s2/clk.c
index 0a376644c5..0306d5d029 100644
--- a/components/esp_system/port/esp32s2/clk.c
+++ b/components/esp_system/port/esp32s2/clk.c
@@ -241,7 +241,6 @@ void esp_perip_clk_init(void)
                            DPORT_LEDC_CLK_EN |
                            DPORT_TIMERGROUP1_CLK_EN |
                            DPORT_SPI3_CLK_EN |
-                           DPORT_SPI4_CLK_EN |
                            DPORT_PWM0_CLK_EN |
                            DPORT_TWAI_CLK_EN |
                            DPORT_PWM1_CLK_EN |
@@ -280,7 +279,6 @@ void esp_perip_clk_init(void)
                         DPORT_RMT_CLK_EN |
                         DPORT_UHCI1_CLK_EN |
                         DPORT_SPI3_CLK_EN |
-                        DPORT_SPI4_CLK_EN |
                         DPORT_I2C_EXT1_CLK_EN |
                         DPORT_I2S1_CLK_EN |
                         DPORT_SPI2_DMA_CLK_EN |
diff --git a/components/soc/soc/esp32s2/include/soc/system_reg.h b/components/soc/soc/esp32s2/include/soc/system_reg.h
index cc7183c84b..4e335cc7ab 100644
--- a/components/soc/soc/esp32s2/include/soc/system_reg.h
+++ b/components/soc/soc/esp32s2/include/soc/system_reg.h
@@ -190,12 +190,6 @@ extern "C" {
 
 #define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG
 #define DPORT_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x040)
-/* DPORT_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
-/*description: */
-#define DPORT_SPI4_CLK_EN  (BIT(31))
-#define DPORT_SPI4_CLK_EN_M  (BIT(31))
-#define DPORT_SPI4_CLK_EN_V  0x1
-#define DPORT_SPI4_CLK_EN_S  31
 /* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
 /*description: */
 #define DPORT_ADC2_ARB_CLK_EN  (BIT(30))
@@ -424,12 +418,6 @@ extern "C" {
 
 #define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG
 #define DPORT_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x048)
-/* DPORT_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define DPORT_SPI4_RST  (BIT(31))
-#define DPORT_SPI4_RST_M  (BIT(31))
-#define DPORT_SPI4_RST_V  0x1
-#define DPORT_SPI4_RST_S  31
 /* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
 /*description: */
 #define DPORT_ADC2_ARB_RST  (BIT(30))