From 3992f734bf2b0b37f0c7238f25a0047b7c5924f5 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 5 Jun 2025 20:06:50 +0800 Subject: [PATCH 1/5] feat(i2s): support i2s on esp32-h4 --- .../esp_driver_i2s/test_apps/i2s/README.md | 4 +- .../test_apps/i2s/main/CMakeLists.txt | 7 +- .../test_apps/i2s_multi_dev/README.md | 4 +- components/hal/esp32h4/include/hal/i2s_ll.h | 1349 +++++++++++++++++ components/hal/include/hal/i2s_types.h | 3 + components/soc/esp32h4/i2s_periph.c | 34 + .../esp32h4/include/soc/Kconfig.soc_caps.in | 68 + .../soc/esp32h4/include/soc/clk_tree_defs.h | 18 + components/soc/esp32h4/include/soc/soc_caps.h | 31 +- components/soc/esp32h4/register/soc/i2s_reg.h | 217 --- .../soc/esp32h4/register/soc/i2s_struct.h | 188 +-- .../soc/esp32h4/register/soc/pcr_struct.h | 8 +- .../i2s/i2s_basic/i2s_pdm/README.md | 4 +- .../i2s/i2s_basic/i2s_std/README.md | 4 +- .../i2s/i2s_basic/i2s_tdm/README.md | 4 +- .../i2s/i2s_codec/i2s_es8311/README.md | 4 +- 16 files changed, 1520 insertions(+), 427 deletions(-) create mode 100644 components/hal/esp32h4/include/hal/i2s_ll.h create mode 100644 components/soc/esp32h4/i2s_periph.c diff --git a/components/esp_driver_i2s/test_apps/i2s/README.md b/components/esp_driver_i2s/test_apps/i2s/README.md index 844e5ee973..3cf5555ec0 100644 --- a/components/esp_driver_i2s/test_apps/i2s/README.md +++ b/components/esp_driver_i2s/test_apps/i2s/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt b/components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt index 827d77dba5..a1770e6576 100644 --- a/components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt +++ b/components/esp_driver_i2s/test_apps/i2s/main/CMakeLists.txt @@ -1,12 +1,15 @@ set(srcs "test_app_main.c" "test_i2s.c" - "test_i2s_iram.c" - "test_i2s_sleep.c") + "test_i2s_iram.c") if(CONFIG_SOC_I2S_SUPPORTS_ETM AND CONFIG_SOC_GPIO_SUPPORT_ETM) set(srcs ${srcs} "test_i2s_etm.c") endif() +if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED) + list(APPEND srcs "test_i2s_sleep.c") +endif() + idf_component_register(SRCS ${srcs} PRIV_REQUIRES unity esp_driver_pcnt spi_flash esp_driver_gpio esp_driver_i2s esp_driver_uart esp_psram diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md b/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md index c91eb572ca..de31cbb585 100644 --- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | diff --git a/components/hal/esp32h4/include/hal/i2s_ll.h b/components/hal/esp32h4/include/hal/i2s_ll.h new file mode 100644 index 0000000000..4abbb4f07d --- /dev/null +++ b/components/hal/esp32h4/include/hal/i2s_ll.h @@ -0,0 +1,1349 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for I2S register operations +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/i2s_periph.h" +#include "soc/i2s_struct.h" +#include "soc/pcr_struct.h" +#include "soc/soc_etm_struct.h" +#include "soc/soc_etm_source.h" +#include "hal/i2s_types.h" +#include "hal/hal_utils.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL) +#define I2S_LL_GET_ID(hw) (((hw) == &I2S0)? 0 : -1) + +#define I2S_LL_TDM_CH_MASK (0xffff) +#define I2S_LL_PDM_BCK_FACTOR (64) + +#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width +#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width +/* Add SOC_I2S_TDM_FULL_DATA_WIDTH in the soc_caps to indicate there is no limitation to support full data width (i.e., 16 slots * 32 bits) */ +#define I2S_LL_SLOT_FRAME_BIT_MAX 512 // Up-to 512 bits in one frame, determined by MAX(half_sample_bits) * 2 + +#define I2S_LL_PLL_F96M_CLK_FREQ (96 * 1000000) // PLL_F96M_CLK: 96MHz +#define I2S_LL_PLL_F64M_CLK_FREQ (64 * 1000000) // PLL_F64M_CLK: 64MHz +#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F96M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT + +#define I2S_LL_ETM_EVENT_TABLE(i2s_port, chan_dir, event) \ + (uint32_t[SOC_I2S_NUM][2][I2S_ETM_EVENT_MAX]){{ \ + [I2S_DIR_RX - 1] = { \ + [I2S_ETM_EVENT_DONE] = I2S0_EVT_RX_DONE, \ + [I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_RECEIVED, \ + }, \ + [I2S_DIR_TX - 1] = { \ + [I2S_ETM_EVENT_DONE] = I2S0_EVT_TX_DONE, \ + [I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_SENT, \ + }}}[i2s_port][(chan_dir) - 1][event] + + +#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \ + (uint32_t[SOC_I2S_NUM][2][I2S_ETM_TASK_MAX]){{ \ + [I2S_DIR_RX - 1] = { \ + [I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \ + [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \ + [I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \ + }, \ + [I2S_DIR_TX - 1] = { \ + [I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \ + [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_TX, \ + [I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \ + }}}[i2s_port][(chan_dir) - 1][task] +#define I2S_LL_ETM_MAX_THRESH_NUM (0x3FFFUL) + +/** + * + * @param i2s_id The port id of I2S + * @param enable Set true to enable the buf clock + */ +static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable) +{ + (void)i2s_id; + PCR.i2s_conf.i2s_clk_en = enable; +} + +/** + * @brief Reset the I2S module + * + * @param i2s_id The port id of I2S + */ +static inline void i2s_ll_reset_register(int i2s_id) +{ + (void)i2s_id; + PCR.i2s_conf.i2s_rst_en = 1; + PCR.i2s_conf.i2s_rst_en = 0; +} + +/** + * @brief I2S module general init, enable I2S clock. + * + * @param hw Peripheral I2S hardware instance address. + * @param enable set true to enable the core clock + */ +static inline void i2s_ll_enable_core_clock(i2s_dev_t *hw, bool enable) +{ + (void)hw; + (void)enable; + // No need to do anything +} + +/** + * @brief Enable I2S tx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 1; +} + +/** + * @brief Enable I2S rx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 1; +} + +/** + * @brief Disable I2S tx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0; +} + +/** + * @brief Disable I2S rx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0; +} + +/** + * @brief I2S mclk use tx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0; +} + +/** + * @brief I2S mclk use rx module clock + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_mclk_bind_to_rx_clk(i2s_dev_t *hw) +{ + (void)hw; + PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 1; +} + +/** + * @brief Enable I2S TX slave mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slave_en Set true to enable slave mode + */ +static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en) +{ + hw->tx_conf.tx_slave_mod = slave_en; +} + +/** + * @brief Enable I2S RX slave mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slave_en Set true to enable slave mode + */ +static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en) +{ + hw->rx_conf.rx_slave_mod = slave_en; +} + +/** + * @brief Reset I2S TX module + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_reset(i2s_dev_t *hw) +{ + hw->tx_conf.tx_reset = 1; + hw->tx_conf.tx_reset = 0; +} + +/** + * @brief Reset I2S RX module + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_reset(i2s_dev_t *hw) +{ + hw->rx_conf.rx_reset = 1; + hw->rx_conf.rx_reset = 0; +} + +/** + * @brief Reset I2S TX FIFO + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_reset_fifo(i2s_dev_t *hw) +{ + hw->tx_conf.tx_fifo_reset = 1; + hw->tx_conf.tx_fifo_reset = 0; +} + +/** + * @brief Reset I2S RX FIFO + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw) +{ + hw->rx_conf.rx_fifo_reset = 1; + hw->rx_conf.rx_fifo_reset = 0; +} + +/** + * @brief Set TX source clock + * + * @param hw Peripheral I2S hardware instance address. + * @param src I2S source clock. + */ +static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) +{ + (void)hw; + switch (src) + { + case I2S_CLK_SRC_XTAL: + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0; + break; + case I2S_CLK_SRC_PLL_96M: + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 1; + break; + // case I2S_CLK_SRC_PLL_64M: + // PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2; + // break; + case I2S_CLK_SRC_EXTERNAL: + PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 3; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } +} + +/** + * @brief Set RX source clock + * + * @param hw Peripheral I2S hardware instance address. + * @param src I2S source clock + */ +static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) +{ + (void)hw; + switch (src) + { + case I2S_CLK_SRC_XTAL: + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0; + break; + case I2S_CLK_SRC_PLL_96M: + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 1; + break; + // case I2S_CLK_SRC_PLL_64M: + // PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 2; + // break; + case I2S_CLK_SRC_EXTERNAL: + PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 3; + break; + default: + HAL_ASSERT(false && "unsupported clock source"); + break; + } +} + +/** + * @brief Set I2S tx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bck div num + */ +static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + hw->tx_conf.tx_bck_div_num = val - 1; +} + +/** + * @brief Set I2S tx raw clock division + * + * @param hw Peripheral I2S hardware instance address. + * @param div_int Integer part of division + * @param x div x + * @param y div y + * @param z div z + * @param yn1 yn1 + */ +static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) +{ + (void)hw; + /* Workaround for the double division issue. + * The division coefficients must be set in particular sequence. + * And it has to switch to a small division first before setting the target division. */ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, 2); + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = 0; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = 1; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = 0; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = 0; + + /* Set the target mclk division coefficients */ + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = yn1; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = z; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = y; + PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = x; + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int); +} + +/** + * @brief Set I2S rx raw clock division + * + * @param hw Peripheral I2S hardware instance address. + * @param div_int Integer part of division + * @param x div x + * @param y div y + * @param z div z + * @param yn1 yn1 + */ +static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) +{ + (void)hw; + /* Workaround for the double division issue. + * The division coefficients must be set in particular sequence. + * And it has to switch to a small division first before setting the target division. */ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, 2); + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = 0; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = 1; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = 0; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = 0; + + /* Set the target mclk division coefficients */ + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = yn1; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = z; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = y; + PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = x; + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, div_int); +} + +/** + * @brief Configure I2S TX module clock divider + * + * @param hw Peripheral I2S hardware instance address. + * @param mclk_div The mclk division coefficients + */ +static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div) +{ + uint32_t div_x = 0; + uint32_t div_y = 0; + uint32_t div_z = 0; + uint32_t div_yn1 = 0; + /* If any of denominator and numerator is 0, set all the coefficients to 0 */ + if (mclk_div->denominator && mclk_div->numerator) { + div_yn1 = mclk_div->numerator * 2 > mclk_div->denominator; + div_z = div_yn1 ? mclk_div->denominator - mclk_div->numerator : mclk_div->numerator; + div_x = mclk_div->denominator / div_z - 1; + div_y = mclk_div->denominator % div_z; + } + i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integer, div_x, div_y, div_z, div_yn1); +} + +/** + * @brief Set I2S rx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bck div num + */ +static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + hw->rx_conf.rx_bck_div_num = val - 1; +} + +/** + * @brief Configure I2S RX module clock divider + * @note mclk on ESP32H2 is shared by both TX and RX channel + * + * @param hw Peripheral I2S hardware instance address. + * @param mclk_div The mclk division coefficients + */ +static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div) +{ + uint32_t div_x = 0; + uint32_t div_y = 0; + uint32_t div_z = 0; + uint32_t div_yn1 = 0; + /* If any of denominator and numerator is 0, set all the coefficients to 0 */ + if (mclk_div->denominator && mclk_div->numerator) { + div_yn1 = mclk_div->numerator * 2 > mclk_div->denominator; + div_z = div_yn1 ? mclk_div->denominator - mclk_div->numerator : mclk_div->numerator; + div_x = mclk_div->denominator / div_z - 1; + div_y = mclk_div->denominator % div_z; + } + i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integer, div_x, div_y, div_z, div_yn1); +} + +/** + * @brief Update the TX configuration + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_update(i2s_dev_t *hw) +{ + hw->tx_conf.tx_update = 1; + while (hw->tx_conf.tx_update); +} + +/** + * @brief Update the RX configuration + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_update(i2s_dev_t *hw) +{ + hw->rx_conf.rx_update = 1; + while (hw->rx_conf.rx_update); +} + +/** + * @brief Start I2S TX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_start(i2s_dev_t *hw) +{ + // Have to update registers before start + i2s_ll_tx_update(hw); + hw->tx_conf.tx_start = 1; +} + +/** + * @brief Start I2S RX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_start(i2s_dev_t *hw) +{ + // Have to update registers before start + i2s_ll_rx_update(hw); + hw->rx_conf.rx_start = 1; +} + +/** + * @brief Stop I2S TX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_stop(i2s_dev_t *hw) +{ + hw->tx_conf.tx_start = 0; +} + +/** + * @brief Stop I2S RX + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_stop(i2s_dev_t *hw) +{ + hw->rx_conf.rx_start = 0; +} + +/** + * @brief Configure TX WS signal width + * + * @param hw Peripheral I2S hardware instance address. + * @param width WS width in BCK cycle + */ +static inline void i2s_ll_tx_set_ws_width(i2s_dev_t *hw, int width) +{ + hw->tx_conf1.tx_tdm_ws_width = width - 1; +} + +/** + * @brief Configure RX WS signal width + * + * @param hw Peripheral I2S hardware instance address. + * @param width WS width in BCK cycle + */ +static inline void i2s_ll_rx_set_ws_width(i2s_dev_t *hw, int width) +{ + hw->rx_conf1.rx_tdm_ws_width = width - 1; +} + +/** + * @brief Configure the received length to trigger in_suc_eof interrupt + * + * @param hw Peripheral I2S hardware instance address. + * @param eof_num the byte length to trigger in_suc_eof interrupt + */ +static inline void i2s_ll_rx_set_eof_num(i2s_dev_t *hw, int eof_num) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_eof_num, rx_eof_num, eof_num); +} + +/** + * @brief Configure TX chan bit and audio data bit + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_bit The chan bit width + * @param data_bit The audio data bit width + */ +static inline void i2s_ll_tx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit) +{ + hw->tx_conf1.tx_bits_mod = data_bit - 1; + hw->tx_conf1.tx_tdm_chan_bits = chan_bit - 1; +} + +/** + * @brief Configure RX chan bit and audio data bit + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_bit The chan bit width + * @param data_bit The audio data bit width + */ +static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit) +{ + hw->rx_conf1.rx_bits_mod = data_bit - 1; + hw->rx_conf1.rx_tdm_chan_bits = chan_bit - 1; +} + +/** + * @brief Configure RX half_sample_bit + * + * @param hw Peripheral I2S hardware instance address. + * @param half_sample_bits half sample bit width + */ +static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_conf1, tx_half_sample_bits, half_sample_bits - 1); +} + +/** + * @brief Configure RX half_sample_bit + * + * @param hw Peripheral I2S hardware instance address. + * @param half_sample_bits half sample bit width + */ +static inline void i2s_ll_rx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_conf1, rx_half_sample_bits, half_sample_bits - 1); +} + +/** + * @brief Enable TX MSB shift, the data will be launch at the first BCK clock + * + * @param hw Peripheral I2S hardware instance address. + * @param msb_shift_enable Set true to enable MSB shift + */ +static inline void i2s_ll_tx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable) +{ + hw->tx_conf.tx_msb_shift = msb_shift_enable; +} + +/** + * @brief Enable RX MSB shift, the data will be launch at the first BCK clock + * + * @param hw Peripheral I2S hardware instance address. + * @param msb_shift_enable Set true to enable MSB shift + */ +static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable) +{ + hw->rx_conf.rx_msb_shift = msb_shift_enable; +} + +/** + * @brief Configure TX total chan number + * + * @param hw Peripheral I2S hardware instance address. + * @param total_num Total chan number + */ +static inline void i2s_ll_tx_set_chan_num(i2s_dev_t *hw, int total_num) +{ + hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num - 1; +} + +/** + * @brief Configure RX total chan number + * + * @param hw Peripheral I2S hardware instance address. + * @param total_num Total chan number + */ +static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num) +{ + hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; +} + +/** + * @brief Set the bimap of the active TX chan, only the active chan can launch audio data. + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_mask mask of tx active chan + */ +static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) +{ + uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val; + tdm_ctrl &= 0xFFFF0000; + tdm_ctrl |= chan_mask; + hw->tx_tdm_ctrl.val = tdm_ctrl; +} + +/** + * @brief Set the bimap of the active RX chan, only the active chan can receive audio data. + * + * @param hw Peripheral I2S hardware instance address. + * @param chan_mask mask of rx active chan + */ +static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) +{ + uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val; + tdm_ctrl &= 0xFFFF0000; + tdm_ctrl |= chan_mask; + hw->rx_tdm_ctrl.val = tdm_ctrl; +} + +/** + * @brief Set I2S tx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slot_mask select slot to send data + */ +static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask) +{ + /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot + * Otherwise always enable the first two slots */ + hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1 + uint32_t chan_mask = 0; + switch (slot_mask) + { + case I2S_STD_SLOT_LEFT: + chan_mask |= 0x01; + break; + case I2S_STD_SLOT_RIGHT: + chan_mask |= 0x02; + break; + case I2S_STD_SLOT_BOTH: + chan_mask |= 0x03; + break; + default: + break; + } + i2s_ll_tx_set_active_chan_mask(hw, chan_mask); +} + +/** + * @brief Set I2S rx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param slot_mask select slot to receive data + */ +static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask) +{ + /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot + * Otherwise always enable the first two slots */ + hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 + uint32_t chan_mask = 0; + switch (slot_mask) + { + case I2S_STD_SLOT_LEFT: + chan_mask |= 0x01; + break; + case I2S_STD_SLOT_RIGHT: + chan_mask |= 0x02; + break; + case I2S_STD_SLOT_BOTH: + chan_mask |= 0x03; + break; + default: + break; + } + i2s_ll_rx_set_active_chan_mask(hw, chan_mask); +} + +/** + * @brief PDM slot mode + * + * @param hw Peripheral I2S hardware instance address. + * @param mod Channel mode + * while tx_ws_idle_pol = 0: + * 0: stereo + * 1: Both slots transmit left + * 2: Both slots transmit right + * 3: Left transmits `conf_single_data` right transmits data + * 4: Right transmits `conf_single_data` left transmits data + * while tx_ws_idle_pol = 1: + 0: stereo + * 1: Both slots transmit right + * 2: Both slots transmit left + * 3: Right transmits `conf_single_data` left transmits data + * 4: Left transmits `conf_single_data` right transmits data + */ +static inline void i2s_ll_tx_set_pdm_chan_mod(i2s_dev_t *hw, uint32_t mod) +{ + hw->tx_conf.tx_chan_mod = mod; +} + +/** + * @brief Set TX WS signal pol level + * + * @param hw Peripheral I2S hardware instance address. + * @param ws_pol_level pin level of WS(output) when receiving left channel data + */ +static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level) +{ + hw->tx_conf.tx_ws_idle_pol = ws_pol_level; +} + +/** + * @brief Set RX WS signal pol level + * + * @param hw Peripheral I2S hardware instance address. + * @param ws_pol_level pin level of WS(input) when receiving left channel data + */ +static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level) +{ + hw->rx_conf.rx_ws_idle_pol = ws_pol_level; +} + +/** + * @brief Enable I2S TX TDM mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_tdm(i2s_dev_t *hw) +{ + hw->tx_conf.tx_pdm_en = false; + hw->tx_conf.tx_tdm_en = true; + hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = false; +} + +/** + * @brief Enable I2S RX TDM mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw) +{ + hw->rx_conf.rx_pdm_en = false; + hw->rx_conf.rx_tdm_en = true; +} + +/** + * @brief Enable I2S TX STD mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_tx_enable_std(i2s_dev_t *hw) +{ + i2s_ll_tx_enable_tdm(hw); +} + +/** + * @brief Enable I2S RX STD mode + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_rx_enable_std(i2s_dev_t *hw) +{ + i2s_ll_rx_enable_tdm(hw); +} + +/** + * @brief Enable I2S TX PDM mode + * + * @param hw Peripheral I2S hardware instance address. + * @param pcm2pdm_en Set true to enable TX PCM to PDM filter + */ +static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw, bool pcm2pdm_en) +{ + hw->tx_conf.tx_pdm_en = true; + hw->tx_conf.tx_tdm_en = false; + hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = pcm2pdm_en; +} + +/** + * @brief Enable I2S RX PDM mode + * + * @param hw Peripheral I2S hardware instance address. + * @param pdm2pcm_en Set true to enable RX PDM to PCM filter + */ +static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm2pcm_en) +{ + HAL_ASSERT(!pdm2pcm_en); // H2 does not have PDM2PCM filter + hw->rx_conf.rx_pdm_en = true; + hw->rx_conf.rx_tdm_en = false; +} + +/** + * @brief Set I2S TX PDM prescale + * + * @param hw Peripheral I2S hardware instance address. + * @param prescale I2S TX PDM prescale + */ +static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale); +} + +/** + * @brief Set I2S TX PDM high pass filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_hp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_hp_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM low pass filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_lp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_lp_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM sinc filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_sinc_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sinc_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM sigma-delta filter scaling + * + * @param hw Peripheral I2S hardware instance address. + * @param sig_scale I2S TX PDM signal scaling before transmit to the filter + */ +static inline void i2s_ll_tx_set_pdm_sd_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_in_shift = sig_scale; +} + +/** + * @brief Set I2S TX PDM high pass filter param0 + * + * @param hw Peripheral I2S hardware instance address. + * @param param The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + */ +static inline void i2s_ll_tx_set_pdm_hp_filter_param0(i2s_dev_t *hw, uint32_t param) +{ + hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_0 = param; +} + +/** + * @brief Set I2S TX PDM high pass filter param5 + * + * @param hw Peripheral I2S hardware instance address. + * @param param The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + */ +static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t param) +{ + hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_5 = param; +} + +/** + * @brief Enable I2S TX PDM high pass filter + * + * @param hw Peripheral I2S hardware instance address. + * @param enable Set true to enable I2S TX PDM high pass filter, set false to bypass it + */ +static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable) +{ + // Must enable on H4 + HAL_ASSERT(enable); +} + +/** + * @brief Set I2S TX PDM sigma-delta codec dither + * + * @param hw Peripheral I2S hardware instance address. + * @param dither I2S TX PDM sigmadelta dither value + */ +static inline void i2s_ll_tx_set_pdm_sd_dither(i2s_dev_t *hw, uint32_t dither) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither = dither; +} + +/** + * @brief Set I2S TX PDM sigma-delta codec dither + * + * @param hw Peripheral I2S hardware instance address. + * @param dither2 I2S TX PDM sigmadelta dither2 value + */ +static inline void i2s_ll_tx_set_pdm_sd_dither2(i2s_dev_t *hw, uint32_t dither2) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither2 = dither2; +} + +/** + * @brief Set the PDM TX over sampling ratio + * + * @param hw Peripheral I2S hardware instance address. + * @param ovr Over sampling ratio + */ +static inline void i2s_ll_tx_set_pdm_over_sample_ratio(i2s_dev_t *hw, uint32_t ovr) +{ + hw->tx_pcm2pdm_conf.tx_pdm_sinc_osr2 = ovr; +} + +/** + * @brief Configure I2S TX PDM sample rate + * Fpdm = 64*Fpcm*fp/fs + * + * @param hw Peripheral I2S hardware instance address. + * @param fp The fp value of TX PDM filter module group0. + * @param fs The fs value of TX PDM filter module group0. + */ +static inline void i2s_ll_tx_set_pdm_fpfs(i2s_dev_t *hw, uint32_t fp, uint32_t fs) +{ + hw->tx_pcm2pdm_conf1.tx_pdm_fp = fp; + hw->tx_pcm2pdm_conf1.tx_pdm_fs = fs; +} + +/** + * @brief Get I2S TX PDM fp configuration parameter + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - fp configuration parameter + */ +static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw) +{ + return hw->tx_pcm2pdm_conf1.tx_pdm_fp; +} + +/** + * @brief Get I2S TX PDM fs configuration parameter + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - fs configuration parameter + */ +static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw) +{ + return hw->tx_pcm2pdm_conf1.tx_pdm_fs; +} + +/** + * @brief Configura TX a/u-law decompress or compress + * + * @param hw Peripheral I2S hardware instance address. + * @param pcm_cfg PCM configuration parameter + */ +static inline void i2s_ll_tx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg) +{ + hw->tx_conf.tx_pcm_conf = pcm_cfg; + hw->tx_conf.tx_pcm_bypass = !pcm_cfg; +} + +/** + * @brief Configure RX a/u-law decompress or compress + * + * @param hw Peripheral I2S hardware instance address. + * @param pcm_cfg PCM configuration parameter + */ +static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg) +{ + hw->rx_conf.rx_pcm_conf = pcm_cfg; + hw->rx_conf.rx_pcm_bypass = !pcm_cfg; +} + +/** + * @brief Enable TX audio data left alignment + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable left alignment + */ +static inline void i2s_ll_tx_enable_left_align(i2s_dev_t *hw, bool ena) +{ + hw->tx_conf.tx_left_align = ena; +} + +/** + * @brief Enable RX audio data left alignment + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable left alignment + */ +static inline void i2s_ll_rx_enable_left_align(i2s_dev_t *hw, bool ena) +{ + hw->rx_conf.rx_left_align = ena; +} + +/** + * @brief Enable TX big endian mode + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable big endian mode + */ +static inline void i2s_ll_rx_enable_big_endian(i2s_dev_t *hw, bool ena) +{ + hw->rx_conf.rx_big_endian = ena; +} + +/** + * @brief Enable RX big endian mode + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to enable big endian mode + */ +static inline void i2s_ll_tx_enable_big_endian(i2s_dev_t *hw, bool ena) +{ + hw->tx_conf.tx_big_endian = ena; +} + +/** + * @brief Configure TX bit order + * + * @param hw Peripheral I2S hardware instance address. + * @param lsb_order_ena Set true to enable LSB bit order + */ +static inline void i2s_ll_tx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena) +{ + hw->tx_conf.tx_bit_order = lsb_order_ena; +} + +/** + * @brief Configure RX bit order + * + * @param hw Peripheral I2S hardware instance address. + * @param lsb_order_ena Set true to enable LSB bit order + */ +static inline void i2s_ll_rx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena) +{ + hw->rx_conf.rx_bit_order = lsb_order_ena; +} + +/** + * @brief Configure TX skip mask enable + * + * @param hw Peripheral I2S hardware instance address. + * @param skip_mask_ena Set true to skip inactive channels. + */ +static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena) +{ + hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena; +} + + +/** + * @brief Configure single data + * + * @param hw Peripheral I2S hardware instance address. + * @param data Single data to be set + */ +static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data) +{ + hw->conf_single_data.val = data; +} + +/** + * @brief Enable TX mono mode + * @note MONO in hardware means only one channel got data, but another doesn't + * MONO in software means two channel share same data + * This function aims to use MONO in software meaning + * so 'tx_mono' and 'tx_chan_equal' should be enabled at the same time + * + * @param hw Peripheral I2S hardware instance address. + * @param mono_ena Set true to enable mono mde. + */ +static inline void i2s_ll_tx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena) +{ + hw->tx_conf.tx_mono = mono_ena; + hw->tx_conf.tx_chan_equal = mono_ena; +} + +/** + * @brief Enable RX mono mode + * + * @param hw Peripheral I2S hardware instance address. + * @param mono_ena Set true to enable mono mde. + */ +static inline void i2s_ll_rx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena) +{ + hw->rx_conf.rx_mono = mono_ena; + hw->rx_conf.rx_mono_fst_vld = mono_ena; +} + +/** + * @brief Enable loopback mode + * + * @param hw Peripheral I2S hardware instance address. + * @param ena Set true to share BCK and WS signal for tx module and rx module. + */ +static inline void i2s_ll_share_bck_ws(i2s_dev_t *hw, bool ena) +{ + hw->tx_conf.sig_loopback = ena; +} + +/** + * @brief PDM TX DMA data take mode + * + * @param hw Peripheral I2S hardware instance address. + * @param is_mono The DMA data only has one slot (mono) or contains two slots (stereo) + * @param is_fst_valid Whether take the DMA data at the first half period + * Only take effet when 'is_mono' is true + */ +static inline void i2s_ll_tx_pdm_dma_take_mode(i2s_dev_t *hw, bool is_mono, bool is_fst_valid) +{ + hw->tx_conf.tx_mono = is_mono; + hw->tx_conf.tx_mono_fst_vld = is_fst_valid; +} + +/** + * @brief PDM TX slot mode + * @note Mode Left Slot Right Slot Chan Mode WS Pol + * ----------------------------------------------------------------- + * Stereo Left Right 0 x + * ----------------------------------------------------------------- + * Mono Left Left 1 0 + * Mono Right Right 2 0 + * Mono Single Right 3 0 + * Mono Left Single 4 0 + * ----------------------------------------------------------------- + * Mono Right Right 1 1 + * Mono Left Left 2 1 + * Mono Left Single 3 1 + * Mono Single Right 4 1 + * @note The 'Single' above means always sending the value of `conf_single_data` reg + * The default value of `conf_single_data` reg is '0', it is not public for now + * + * @param hw Peripheral I2S hardware instance address. + * @param is_mono The DMA data only has one slot (mono) or contains two slots (stereo) + * @param is_copy Whether the un-selected slot copies the data from the selected one + * If not, the un-selected slot will transmit the data from 'conf_single_data' + * @param mask The slot mask to select the slot + */ +static inline void i2s_ll_tx_pdm_slot_mode(i2s_dev_t *hw, bool is_mono, bool is_copy, i2s_pdm_slot_mask_t mask) +{ + if (is_mono) { + /* The default tx_ws_idle_pol is false */ + if (is_copy) { + hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2; + } else { + hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3; + } + } else { + hw->tx_conf.tx_chan_mod = 0; + } +} + +/** + * @brief PDM TX line mode + * @note Mode DAC Mode 2 lines output + * ------------------------------------------- + * PDM codec 0 1 + * DAC 1-line 1 0 + * DAC 2-line 1 1 + * + * @param hw Peripheral I2S hardware instance address. + * @param line_mode PDM TX line mode + */ +static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode) +{ + hw->tx_pcm2pdm_conf.tx_pdm_dac_mode_en = line_mode > I2S_PDM_TX_ONE_LINE_CODEC; + hw->tx_pcm2pdm_conf.tx_pdm_dac_2out_en = line_mode != I2S_PDM_TX_ONE_LINE_DAC; +} + + +/** + * @brief Reset TX FIFO synchronization counter + * + * @param hw Peripheral I2S hardware instance address. + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_reset_fifo_sync_counter(i2s_dev_t *hw) +{ + hw->fifo_cnt.tx_fifo_cnt_rst = 1; + hw->fifo_cnt.tx_fifo_cnt_rst = 0; +} + +/** + * @brief Get TX FIFO synchronization count value + * + * @param hw Peripheral I2S hardware instance address. + * @return + * bclk count value + */ +__attribute__((always_inline)) +static inline uint32_t i2s_ll_tx_get_fifo_sync_count(i2s_dev_t *hw) +{ + return hw->fifo_cnt.tx_fifo_cnt; +} + +/** + * @brief Reset TX bclk synchronization counter + * + * @param hw Peripheral I2S hardware instance address. + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_reset_bclk_sync_counter(i2s_dev_t *hw) +{ + hw->bck_cnt.tx_bck_cnt_rst = 1; + hw->bck_cnt.tx_bck_cnt_rst = 0; +} + +/** + * @brief Get TX bclk synchronization count value + * + * @param hw Peripheral I2S hardware instance address. + * @return + * fifo count value + */ +__attribute__((always_inline)) +static inline uint32_t i2s_ll_tx_get_bclk_sync_count(i2s_dev_t *hw) +{ + return hw->bck_cnt.tx_bck_cnt; +} + +/** + * @brief Set the TX ETM threshold of REACH_THRESH event + * + * @param hw Peripheral I2S hardware instance address. + * @param thresh The threshold that send + */ +static inline void i2s_ll_tx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh) +{ + hw->etm_conf.etm_tx_send_word_num = thresh; +} + +/** + * @brief Set the RX ETM threshold of REACH_THRESH event + * + * @param hw Peripheral I2S hardware instance address. + * @param thresh The threshold that received + */ +static inline void i2s_ll_rx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh) +{ + hw->etm_conf.etm_rx_receive_word_num = thresh; +} + + +/** + * @brief Get I2S ETM TX done event status + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - true TX done event triggered + * - false TX done event not triggered + */ +static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw) +{ + uint32_t i2s_id = I2S_LL_GET_ID(hw); + switch (i2s_id) { + case 0: + return SOC_ETM.etm_evt_st4.etm_i2s0_evt_tx_done_st; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Get I2S ETM TX done event status + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - true TX done event triggered + * - false TX done event not triggered + */ +static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw) +{ + uint32_t i2s_id = I2S_LL_GET_ID(hw); + switch (i2s_id) { + case 0: + return SOC_ETM.etm_evt_st4.etm_i2s0_evt_rx_done_st; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Get I2S ETM TX done event status + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - true TX done event triggered + * - false TX done event not triggered + */ +static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw) +{ + uint32_t i2s_id = I2S_LL_GET_ID(hw); + switch (i2s_id) { + case 0: + return SOC_ETM.etm_evt_st4.etm_i2s0_evt_x_words_sent_st; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Get I2S ETM TX done event status + * + * @param hw Peripheral I2S hardware instance address. + * @return + * - true TX done event triggered + * - false TX done event not triggered + */ +static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw) +{ + uint32_t i2s_id = I2S_LL_GET_ID(hw); + switch (i2s_id) { + case 0: + return SOC_ETM.etm_evt_st4.etm_i2s0_evt_x_words_received_st; + default: + HAL_ASSERT(false); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/i2s_types.h b/components/hal/include/hal/i2s_types.h index e08329e210..773a8d1ac5 100644 --- a/components/hal/include/hal/i2s_types.h +++ b/components/hal/include/hal/i2s_types.h @@ -233,6 +233,9 @@ typedef enum { typedef enum { I2S_ETM_TASK_START, /*!< Start the I2S channel */ I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */ +#if SOC_I2S_SUPPORTS_ETM_SYNC + I2S_ETM_TASK_SYNC_CHECK, /*!< Stop the I2S channel */ +#endif I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */ } i2s_etm_task_type_t; diff --git a/components/soc/esp32h4/i2s_periph.c b/components/soc/esp32h4/i2s_periph.c new file mode 100644 index 0000000000..b3b72dc12d --- /dev/null +++ b/components/soc/esp32h4/i2s_periph.c @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/i2s_periph.h" +#include "soc/i2s_reg.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { + { + .mck_out_sig = I2S_MCLK_OUT_IDX, + .mck_in_sig = I2S_MCLK_IN_IDX, + + .m_tx_bck_sig = I2SO_BCK_OUT_IDX, + .m_rx_bck_sig = I2SI_BCK_OUT_IDX, + .m_tx_ws_sig = I2SO_WS_OUT_IDX, + .m_rx_ws_sig = I2SI_WS_OUT_IDX, + + .s_tx_bck_sig = I2SO_BCK_IN_IDX, + .s_rx_bck_sig = I2SI_BCK_IN_IDX, + .s_tx_ws_sig = I2SO_WS_IN_IDX, + .s_rx_ws_sig = I2SI_WS_IN_IDX, + + .data_out_sig = I2SO_SD_OUT_IDX, + .data_in_sig = I2SI_SD_IN_IDX, + + .irq = ETS_I2S_INTR_SOURCE, + } +}; diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index c550a04cff..b79482ea9f 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -31,6 +31,10 @@ config SOC_EFUSE_SUPPORTED bool default y +config SOC_I2S_SUPPORTED + bool + default y + config SOC_I2C_SUPPORTED bool default y @@ -291,6 +295,70 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION bool default y +config SOC_I2S_NUM + int + default 1 + +config SOC_I2S_HW_VERSION_2 + bool + default y + +config SOC_I2S_SUPPORTS_ETM_SYNC + bool + default y + +config SOC_I2S_SUPPORTS_XTAL + bool + default y + +config SOC_I2S_SUPPORTS_PLL_F96M + bool + default y + +config SOC_I2S_SUPPORTS_PLL_F64M + bool + default y + +config SOC_I2S_SUPPORTS_PCM + bool + default y + +config SOC_I2S_SUPPORTS_PDM + bool + default y + +config SOC_I2S_SUPPORTS_PDM_TX + bool + default y + +config SOC_I2S_SUPPORTS_PCM2PDM + bool + default y + +config SOC_I2S_SUPPORTS_PDM_RX + bool + default y + +config SOC_I2S_SUPPORTS_TX_SYNC_CNT + bool + default y + +config SOC_I2S_PDM_MAX_TX_LINES + int + default 2 + +config SOC_I2S_PDM_MAX_RX_LINES + int + default 1 + +config SOC_I2S_SUPPORTS_TDM + bool + default y + +config SOC_I2S_TDM_FULL_DATA_WIDTH + bool + default y + config SOC_LEDC_CHANNEL_NUM int default 6 diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index e70bc7122f..15aba105a5 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -299,6 +299,24 @@ typedef enum { I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ } soc_periph_i2c_clk_src_t; +///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of I2S + */ +#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} + +/** + * @brief I2S clock source enum + */ +typedef enum { + I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */ + I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */ + // I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */ + I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ +} soc_periph_i2s_clk_src_t; + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index efc5dd5fdc..d62089c6af 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -54,7 +54,7 @@ #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268 #define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268 // #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313 -// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32H4] IDF-12385 +#define SOC_I2S_SUPPORTED 1 // #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12402 // #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12348 // #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366 @@ -268,15 +268,26 @@ #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- I2S CAPS ----------------------------------------*/ -// #define SOC_I2S_NUM (1U) -// #define SOC_I2S_HW_VERSION_2 (1) -// #define SOC_I2S_SUPPORTS_XTAL (1) -// #define SOC_I2S_SUPPORTS_PLL_F160M (1) -// #define SOC_I2S_SUPPORTS_PCM (1) -// #define SOC_I2S_SUPPORTS_PDM (1) -// #define SOC_I2S_SUPPORTS_PDM_TX (1) -// #define SOC_I2S_PDM_MAX_TX_LINES (2) -// #define SOC_I2S_SUPPORTS_TDM (1) +#define SOC_I2S_NUM (1U) +#define SOC_I2S_HW_VERSION_2 (1) +// #define SOC_I2S_SUPPORTS_ETM (1) +#define SOC_I2S_SUPPORTS_ETM_SYNC (1) +#define SOC_I2S_SUPPORTS_XTAL (1) +#define SOC_I2S_SUPPORTS_PLL_F96M (1) +#define SOC_I2S_SUPPORTS_PLL_F64M (1) +#define SOC_I2S_SUPPORTS_PCM (1) +#define SOC_I2S_SUPPORTS_PDM (1) +#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data +#define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter +#define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data +#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1) +#define SOC_I2S_PDM_MAX_TX_LINES (2) +#define SOC_I2S_PDM_MAX_RX_LINES (1U) +#define SOC_I2S_SUPPORTS_TDM (1) +#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ + +// TODO: [ESP32H4] IDF-12386 +// #define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */ /*-------------------------- LEDC CAPS ---------------------------------------*/ // #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) diff --git a/components/soc/esp32h4/register/soc/i2s_reg.h b/components/soc/esp32h4/register/soc/i2s_reg.h index 1a39a2dc57..dfbf964bd6 100644 --- a/components/soc/esp32h4/register/soc/i2s_reg.h +++ b/components/soc/esp32h4/register/soc/i2s_reg.h @@ -573,173 +573,6 @@ extern "C" { #define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU #define I2S_TX_TDM_CHAN_BITS_S 27 -/** I2S_RX_RECOMB_CTRL_REG register - * I2S RX configure register 1 - */ -#define I2S_RX_RECOMB_CTRL_REG (DR_REG_I2S_BASE + 0x30) -/** I2S_RX_RECOMB_EN : R/W; bitpos: [0]; default: 0; - * Set this bit to enable i2s rx data recombination. - */ -#define I2S_RX_RECOMB_EN (BIT(0)) -#define I2S_RX_RECOMB_EN_M (I2S_RX_RECOMB_EN_V << I2S_RX_RECOMB_EN_S) -#define I2S_RX_RECOMB_EN_V 0x00000001U -#define I2S_RX_RECOMB_EN_S 0 -/** I2S_RX_RECOMB_EXT_CH_NUM : R/W; bitpos: [2:1]; default: 0; - * The channel number that i2s will extract the data into. - */ -#define I2S_RX_RECOMB_EXT_CH_NUM 0x00000003U -#define I2S_RX_RECOMB_EXT_CH_NUM_M (I2S_RX_RECOMB_EXT_CH_NUM_V << I2S_RX_RECOMB_EXT_CH_NUM_S) -#define I2S_RX_RECOMB_EXT_CH_NUM_V 0x00000003U -#define I2S_RX_RECOMB_EXT_CH_NUM_S 1 -/** I2S_RX_RECOMB_UPDATE : WT; bitpos: [31]; default: 0; - * Set this bit to update i2s data recombination configuration, must be performed - * after changing the config of any recombined-dma-channel. - */ -#define I2S_RX_RECOMB_UPDATE (BIT(31)) -#define I2S_RX_RECOMB_UPDATE_M (I2S_RX_RECOMB_UPDATE_V << I2S_RX_RECOMB_UPDATE_S) -#define I2S_RX_RECOMB_UPDATE_V 0x00000001U -#define I2S_RX_RECOMB_UPDATE_S 31 - -/** I2S_RX_RECOMB_DMA_CH0_REG register - * I2S RX recombined-dma-channel configuration register - */ -#define I2S_RX_RECOMB_DMA_CH0_REG (DR_REG_I2S_BASE + 0x34) -/** I2S_RX_RECOMB_DMA_CH0_VALID : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH0_VALID (BIT(0)) -#define I2S_RX_RECOMB_DMA_CH0_VALID_M (I2S_RX_RECOMB_DMA_CH0_VALID_V << I2S_RX_RECOMB_DMA_CH0_VALID_S) -#define I2S_RX_RECOMB_DMA_CH0_VALID_V 0x00000001U -#define I2S_RX_RECOMB_DMA_CH0_VALID_S 0 -/** I2S_RX_RECOMB_DMA_CH0_STYLE : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ -#define I2S_RX_RECOMB_DMA_CH0_STYLE 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH0_STYLE_M (I2S_RX_RECOMB_DMA_CH0_STYLE_V << I2S_RX_RECOMB_DMA_CH0_STYLE_S) -#define I2S_RX_RECOMB_DMA_CH0_STYLE_V 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH0_STYLE_S 1 -/** I2S_RX_RECOMB_DMA_CH0_ORDER : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ -#define I2S_RX_RECOMB_DMA_CH0_ORDER 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH0_ORDER_M (I2S_RX_RECOMB_DMA_CH0_ORDER_V << I2S_RX_RECOMB_DMA_CH0_ORDER_S) -#define I2S_RX_RECOMB_DMA_CH0_ORDER_V 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH0_ORDER_S 5 -/** I2S_RX_RECOMB_DMA_CH0_EOF_NUM : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S) -#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S 13 - -/** I2S_RX_RECOMB_DMA_CH1_REG register - * I2S RX recombined-dma-channel configuration register - */ -#define I2S_RX_RECOMB_DMA_CH1_REG (DR_REG_I2S_BASE + 0x38) -/** I2S_RX_RECOMB_DMA_CH1_VALID : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH1_VALID (BIT(0)) -#define I2S_RX_RECOMB_DMA_CH1_VALID_M (I2S_RX_RECOMB_DMA_CH1_VALID_V << I2S_RX_RECOMB_DMA_CH1_VALID_S) -#define I2S_RX_RECOMB_DMA_CH1_VALID_V 0x00000001U -#define I2S_RX_RECOMB_DMA_CH1_VALID_S 0 -/** I2S_RX_RECOMB_DMA_CH1_STYLE : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ -#define I2S_RX_RECOMB_DMA_CH1_STYLE 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH1_STYLE_M (I2S_RX_RECOMB_DMA_CH1_STYLE_V << I2S_RX_RECOMB_DMA_CH1_STYLE_S) -#define I2S_RX_RECOMB_DMA_CH1_STYLE_V 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH1_STYLE_S 1 -/** I2S_RX_RECOMB_DMA_CH1_ORDER : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ -#define I2S_RX_RECOMB_DMA_CH1_ORDER 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH1_ORDER_M (I2S_RX_RECOMB_DMA_CH1_ORDER_V << I2S_RX_RECOMB_DMA_CH1_ORDER_S) -#define I2S_RX_RECOMB_DMA_CH1_ORDER_V 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH1_ORDER_S 5 -/** I2S_RX_RECOMB_DMA_CH1_EOF_NUM : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S) -#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S 13 - -/** I2S_RX_RECOMB_DMA_CH2_REG register - * I2S RX recombined-dma-channel configuration register - */ -#define I2S_RX_RECOMB_DMA_CH2_REG (DR_REG_I2S_BASE + 0x3c) -/** I2S_RX_RECOMB_DMA_CH2_VALID : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH2_VALID (BIT(0)) -#define I2S_RX_RECOMB_DMA_CH2_VALID_M (I2S_RX_RECOMB_DMA_CH2_VALID_V << I2S_RX_RECOMB_DMA_CH2_VALID_S) -#define I2S_RX_RECOMB_DMA_CH2_VALID_V 0x00000001U -#define I2S_RX_RECOMB_DMA_CH2_VALID_S 0 -/** I2S_RX_RECOMB_DMA_CH2_STYLE : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ -#define I2S_RX_RECOMB_DMA_CH2_STYLE 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH2_STYLE_M (I2S_RX_RECOMB_DMA_CH2_STYLE_V << I2S_RX_RECOMB_DMA_CH2_STYLE_S) -#define I2S_RX_RECOMB_DMA_CH2_STYLE_V 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH2_STYLE_S 1 -/** I2S_RX_RECOMB_DMA_CH2_ORDER : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ -#define I2S_RX_RECOMB_DMA_CH2_ORDER 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH2_ORDER_M (I2S_RX_RECOMB_DMA_CH2_ORDER_V << I2S_RX_RECOMB_DMA_CH2_ORDER_S) -#define I2S_RX_RECOMB_DMA_CH2_ORDER_V 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH2_ORDER_S 5 -/** I2S_RX_RECOMB_DMA_CH2_EOF_NUM : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S) -#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S 13 - -/** I2S_RX_RECOMB_DMA_CH3_REG register - * I2S RX recombined-dma-channel configuration register - */ -#define I2S_RX_RECOMB_DMA_CH3_REG (DR_REG_I2S_BASE + 0x40) -/** I2S_RX_RECOMB_DMA_CH3_VALID : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH3_VALID (BIT(0)) -#define I2S_RX_RECOMB_DMA_CH3_VALID_M (I2S_RX_RECOMB_DMA_CH3_VALID_V << I2S_RX_RECOMB_DMA_CH3_VALID_S) -#define I2S_RX_RECOMB_DMA_CH3_VALID_V 0x00000001U -#define I2S_RX_RECOMB_DMA_CH3_VALID_S 0 -/** I2S_RX_RECOMB_DMA_CH3_STYLE : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ -#define I2S_RX_RECOMB_DMA_CH3_STYLE 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH3_STYLE_M (I2S_RX_RECOMB_DMA_CH3_STYLE_V << I2S_RX_RECOMB_DMA_CH3_STYLE_S) -#define I2S_RX_RECOMB_DMA_CH3_STYLE_V 0x0000000FU -#define I2S_RX_RECOMB_DMA_CH3_STYLE_S 1 -/** I2S_RX_RECOMB_DMA_CH3_ORDER : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ -#define I2S_RX_RECOMB_DMA_CH3_ORDER 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH3_ORDER_M (I2S_RX_RECOMB_DMA_CH3_ORDER_V << I2S_RX_RECOMB_DMA_CH3_ORDER_S) -#define I2S_RX_RECOMB_DMA_CH3_ORDER_V 0x000000FFU -#define I2S_RX_RECOMB_DMA_CH3_ORDER_S 5 -/** I2S_RX_RECOMB_DMA_CH3_EOF_NUM : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ -#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S) -#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V 0x0000FFFFU -#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S 13 - /** I2S_TX_PCM2PDM_CONF_REG register * I2S TX PCM2PDM configuration register */ @@ -857,56 +690,6 @@ extern "C" { #define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U #define I2S_TX_IIR_HP_MULT12_0_S 23 -/** I2S_RX_PDM2PCM_CONF_REG register - * I2S RX configure register - */ -#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x4c) -/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0; - * 1: Enable PDM2PCM RX mode. 0: DIsable. - */ -#define I2S_RX_PDM2PCM_EN (BIT(19)) -#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S) -#define I2S_RX_PDM2PCM_EN_V 0x00000001U -#define I2S_RX_PDM2PCM_EN_S 19 -/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0; - * Configure the down sampling rate of PDM RX filter group1 module. 1: The down - * sampling rate is 128. 0: down sampling rate is 64. - */ -#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20)) -#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S) -#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U -#define I2S_RX_PDM_SINC_DSR_16_EN_S 20 -/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1; - * Configure PDM RX amplify number. - */ -#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU -#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S) -#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU -#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21 -/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0; - * I2S PDM RX bypass hp filter or not. - */ -#define I2S_RX_PDM_HP_BYPASS (BIT(25)) -#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S) -#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U -#define I2S_RX_PDM_HP_BYPASS_S 25 -/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6; - * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + - * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) - */ -#define I2S_RX_IIR_HP_MULT12_5 0x00000007U -#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S) -#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U -#define I2S_RX_IIR_HP_MULT12_5_S 26 -/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7; - * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + - * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) - */ -#define I2S_RX_IIR_HP_MULT12_0 0x00000007U -#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S) -#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U -#define I2S_RX_IIR_HP_MULT12_0_S 29 - /** I2S_RX_TDM_CTRL_REG register * I2S TX TDM mode control register */ diff --git a/components/soc/esp32h4/register/soc/i2s_struct.h b/components/soc/esp32h4/register/soc/i2s_struct.h index b3c62eff53..8f80f0c893 100644 --- a/components/soc/esp32h4/register/soc/i2s_struct.h +++ b/components/soc/esp32h4/register/soc/i2s_struct.h @@ -260,178 +260,6 @@ typedef union { uint32_t val; } i2s_rx_conf1_reg_t; -/** Type of rx_recomb_ctrl register - * I2S RX configure register 1 - */ -typedef union { - struct { - /** rx_recomb_en : R/W; bitpos: [0]; default: 0; - * Set this bit to enable i2s rx data recombination. - */ - uint32_t rx_recomb_en:1; - /** rx_recomb_ext_ch_num : R/W; bitpos: [2:1]; default: 0; - * The channel number that i2s will extract the data into. - */ - uint32_t rx_recomb_ext_ch_num:2; - uint32_t reserved_3:28; - /** rx_recomb_update : WT; bitpos: [31]; default: 0; - * Set this bit to update i2s data recombination configuration, must be performed - * after changing the config of any recombined-dma-channel. - */ - uint32_t rx_recomb_update:1; - }; - uint32_t val; -} i2s_rx_recomb_ctrl_reg_t; - -/** Type of rx_recomb_dma_ch0 register - * I2S RX recombined-dma-channel configuration register - */ -typedef union { - struct { - /** rx_recomb_dma_ch0_valid : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ - uint32_t rx_recomb_dma_ch0_valid:1; - /** rx_recomb_dma_ch0_style : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ - uint32_t rx_recomb_dma_ch0_style:4; - /** rx_recomb_dma_ch0_order : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ - uint32_t rx_recomb_dma_ch0_order:8; - /** rx_recomb_dma_ch0_eof_num : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ - uint32_t rx_recomb_dma_ch0_eof_num:16; - uint32_t reserved_29:3; - }; - uint32_t val; -} i2s_rx_recomb_dma_ch0_reg_t; - -/** Type of rx_recomb_dma_ch1 register - * I2S RX recombined-dma-channel configuration register - */ -typedef union { - struct { - /** rx_recomb_dma_ch1_valid : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ - uint32_t rx_recomb_dma_ch1_valid:1; - /** rx_recomb_dma_ch1_style : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ - uint32_t rx_recomb_dma_ch1_style:4; - /** rx_recomb_dma_ch1_order : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ - uint32_t rx_recomb_dma_ch1_order:8; - /** rx_recomb_dma_ch1_eof_num : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ - uint32_t rx_recomb_dma_ch1_eof_num:16; - uint32_t reserved_29:3; - }; - uint32_t val; -} i2s_rx_recomb_dma_ch1_reg_t; - -/** Type of rx_recomb_dma_ch2 register - * I2S RX recombined-dma-channel configuration register - */ -typedef union { - struct { - /** rx_recomb_dma_ch2_valid : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ - uint32_t rx_recomb_dma_ch2_valid:1; - /** rx_recomb_dma_ch2_style : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ - uint32_t rx_recomb_dma_ch2_style:4; - /** rx_recomb_dma_ch2_order : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ - uint32_t rx_recomb_dma_ch2_order:8; - /** rx_recomb_dma_ch2_eof_num : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ - uint32_t rx_recomb_dma_ch2_eof_num:16; - uint32_t reserved_29:3; - }; - uint32_t val; -} i2s_rx_recomb_dma_ch2_reg_t; - -/** Type of rx_recomb_dma_ch3 register - * I2S RX recombined-dma-channel configuration register - */ -typedef union { - struct { - /** rx_recomb_dma_ch3_valid : R/W; bitpos: [0]; default: 0; - * Set this bit to enable the adc-dma-channel. - */ - uint32_t rx_recomb_dma_ch3_valid:1; - /** rx_recomb_dma_ch3_style : R/W; bitpos: [4:1]; default: 0; - * Set this field to set the recombined-dma-channel style. If choose to use i2s - * extracted ch 1&3 in 4 channels, the style should be: 6'b1010. - */ - uint32_t rx_recomb_dma_ch3_style:4; - /** rx_recomb_dma_ch3_order : R/W; bitpos: [12:5]; default: 0; - * Set this field to set the recombined-dma-channel order. If choose to use the order - * ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}. - */ - uint32_t rx_recomb_dma_ch3_order:8; - /** rx_recomb_dma_ch3_eof_num : R/W; bitpos: [28:13]; default: 0; - * Set this field to set the receive eof byte length of the recombined-dma-channel. - */ - uint32_t rx_recomb_dma_ch3_eof_num:16; - uint32_t reserved_29:3; - }; - uint32_t val; -} i2s_rx_recomb_dma_ch3_reg_t; - -/** Type of rx_pdm2pcm_conf register - * I2S RX configure register - */ -typedef union { - struct { - uint32_t reserved_0:19; - /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0; - * 1: Enable PDM2PCM RX mode. 0: DIsable. - */ - uint32_t rx_pdm2pcm_en:1; - /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0; - * Configure the down sampling rate of PDM RX filter group1 module. 1: The down - * sampling rate is 128. 0: down sampling rate is 64. - */ - uint32_t rx_pdm_sinc_dsr_16_en:1; - /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1; - * Configure PDM RX amplify number. - */ - uint32_t rx_pdm2pcm_amplify_num:4; - /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0; - * I2S PDM RX bypass hp filter or not. - */ - uint32_t rx_pdm_hp_bypass:1; - /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6; - * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + - * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) - */ - uint32_t rx_iir_hp_mult12_5:3; - /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7; - * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + - * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) - */ - uint32_t rx_iir_hp_mult12_0:3; - }; - uint32_t val; -} i2s_rx_pdm2pcm_conf_reg_t; - /** Type of rx_tdm_ctrl register * I2S TX TDM mode control register */ @@ -526,7 +354,7 @@ typedef union { uint32_t val; } i2s_rx_tdm_ctrl_reg_t; -/** Type of rxeof_num register +/** Type of rx_eof_num register * I2S RX data number control register. */ typedef union { @@ -539,7 +367,7 @@ typedef union { uint32_t reserved_16:16; }; uint32_t val; -} i2s_rxeof_num_reg_t; +} i2s_rx_eof_num_reg_t; /** Group: TX Control and configuration registers */ @@ -1225,21 +1053,17 @@ typedef struct { volatile i2s_tx_conf_reg_t tx_conf; volatile i2s_rx_conf1_reg_t rx_conf1; volatile i2s_tx_conf1_reg_t tx_conf1; - volatile i2s_rx_recomb_ctrl_reg_t rx_recomb_ctrl; - volatile i2s_rx_recomb_dma_ch0_reg_t rx_recomb_dma_ch0; - volatile i2s_rx_recomb_dma_ch1_reg_t rx_recomb_dma_ch1; - volatile i2s_rx_recomb_dma_ch2_reg_t rx_recomb_dma_ch2; - volatile i2s_rx_recomb_dma_ch3_reg_t rx_recomb_dma_ch3; + uint32_t reserved_030[5]; volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; - volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf; + uint32_t reserved_04c; volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; volatile i2s_rx_timing_reg_t rx_timing; volatile i2s_tx_timing_reg_t tx_timing; volatile i2s_lc_hung_conf_reg_t lc_hung_conf; - volatile i2s_rxeof_num_reg_t rxeof_num; - volatile i2s_conf_sigle_data_reg_t conf_sigle_data; + volatile i2s_rx_eof_num_reg_t rx_eof_num; + volatile i2s_conf_single_data_reg_t conf_single_data; volatile i2s_state_reg_t state; volatile i2s_etm_conf_reg_t etm_conf; volatile i2s_ideal_cnt_reg_t ideal_cnt; diff --git a/components/soc/esp32h4/register/soc/pcr_struct.h b/components/soc/esp32h4/register/soc/pcr_struct.h index 7f01570130..c2b58f5aee 100644 --- a/components/soc/esp32h4/register/soc/pcr_struct.h +++ b/components/soc/esp32h4/register/soc/pcr_struct.h @@ -728,8 +728,8 @@ typedef union { /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; * Configures the clock source of I2S TX. * 0 (default): XTAL_CLK - * 1: PLL_F240M_CLK - * 2: PLL_F160M_CLK + * 1: PLL_F96M_CLK + * 2: PLL_F64M_CLK * 3: I2S_MCLK_in */ uint32_t i2s_tx_clkm_sel:2; @@ -785,8 +785,8 @@ typedef union { /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; * Configures the clock source of I2S RX. * 0 (default): XTAL_CLK - * 1: PLL_F240M_CLK - * 2: PLL_F160M_CLK + * 1: PLL_F96M_CLK + * 2: PLL_F64M_CLK * 3: I2S_MCLK_in */ uint32_t i2s_rx_clkm_sel:2; diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md b/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md index 125d839e4e..b559645dec 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md +++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # I2S Basic PDM Mode Example diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/README.md b/examples/peripherals/i2s/i2s_basic/i2s_std/README.md index 9ab8188df3..f9920f45ec 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_std/README.md +++ b/examples/peripherals/i2s/i2s_basic/i2s_std/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | # I2S Basic Standard Mode Example diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md b/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md index 1755a1f951..b34c9f696e 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md +++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # I2S Basic TDM Mode Example diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md index 11e6d9bef8..7c81092e3a 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | # I2S ES8311 Example From 026370e5b3760856f2288597a2659504e4668f6e Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 9 Jun 2025 15:28:02 +0800 Subject: [PATCH 2/5] feat(etm): support etm on esp32-h4 --- components/hal/esp32h4/include/hal/etm_ll.h | 119 ++++ .../hal/esp32h4/include/hal/gpio_etm_ll.h | 136 ++++ components/soc/esp32h4/etm_periph.c | 10 + .../esp32h4/include/soc/Kconfig.soc_caps.in | 40 ++ components/soc/esp32h4/include/soc/soc_caps.h | 20 +- .../soc/esp32h4/ld/esp32h4.peripherals.ld | 1 + .../esp32h4/register/soc/gpio_ext_struct.h | 622 +----------------- .../soc/esp32h4/register/soc/i2s_struct.h | 4 +- .../soc/esp32h4/register/soc/soc_etm_struct.h | 112 +--- .../gptimer_capture_hc_sr04/README.md | 4 +- 10 files changed, 341 insertions(+), 727 deletions(-) create mode 100644 components/hal/esp32h4/include/hal/etm_ll.h create mode 100644 components/hal/esp32h4/include/hal/gpio_etm_ll.h create mode 100644 components/soc/esp32h4/etm_periph.c diff --git a/components/hal/esp32h4/include/hal/etm_ll.h b/components/hal/esp32h4/include/hal/etm_ll.h new file mode 100644 index 0000000000..228a664ac1 --- /dev/null +++ b/components/hal/esp32h4/include/hal/etm_ll.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/soc_etm_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETM_LL_SUPPORT_STATUS 1 // Support to get and clear the status of the ETM event and task + +/** + * @brief Enable the clock for ETM register + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.etm_conf.etm_clk_en = enable; +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.etm_conf.etm_rst_en = 1; + PCR.etm_conf.etm_rst_en = 0; +} + +/** + * @brief Enable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->etm_ch_ena_ad0_set.val = 1 << chan; + } else { + hw->etm_ch_ena_ad1_set.val = 1 << (chan - 32); + } +} + +/** + * @brief Disable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->etm_ch_ena_ad0_clr.val = 1 << chan; + } else { + hw->etm_ch_ena_ad1_clr.val = 1 << (chan - 32); + } +} + +/** + * @brief Check whether the ETM channel is enabled or not + * + * @param hw ETM register base address + * @param chan Channel ID + * @return true if the channel is enabled, false otherwise + */ +static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + return hw->etm_ch_ena_ad0.val & (1 << chan); + } else { + return hw->etm_ch_ena_ad1.val & (1 << (chan - 32)); + } +} + +/** + * @brief Set the input event for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param event Event ID + */ +static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, etm_chn_evt_id, event); +} + +/** + * @brief Set the output task for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param task Task ID + */ +static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, etm_chn_task_id, task); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/gpio_etm_ll.h b/components/hal/esp32h4/include/hal/gpio_etm_ll.h new file mode 100644 index 0000000000..45d1433d11 --- /dev/null +++ b/components/hal/esp32h4/include/hal/gpio_etm_ll.h @@ -0,0 +1,136 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/gpio_ext_struct.h" +#include "soc/soc_etm_source.h" + +#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) + +#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) +#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) +#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) + +#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set which GPIO to be bound to the event channel + * + * @note Different channels can be bound to one GPIO + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) +{ + dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel = gpio_num; +} + +/** + * @brief Whether to enable the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) +{ + dev->etm_event_chn_cfg[chan].ext_etm_chn_event_en = enable; +} + +/** + * @brief Get which GPIO is bound to the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @return GPIO number + */ +static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan) +{ + return dev->etm_event_chn_cfg[chan].ext_etm_chn_event_sel; +} + +/** + * @brief Set which GPIO to be bound to the task channel + * + * @note One channel can be bound to multiple different GPIOs + * + * @param dev Register base address + * @param chan GPIO ETM Task channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x07 << (g_idx * 6)); + reg_val |= ((chan & 0x07) << (g_idx * 6)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Whether to enable the GPIO to be managed by the task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x01 << (g_idx * 6 + 5)); + reg_val |= ((enable & 0x01) << (g_idx * 6 + 5)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Check whether a GPIO has been enabled and managed by a task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return True if enabled, false otherwise + */ +static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5)); +} + +/** + * @brief Get the channel number that the GPIO is bound to + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return GPIO ETM Task channel number + */ +static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/etm_periph.c b/components/soc/esp32h4/etm_periph.c new file mode 100644 index 0000000000..d54078bd9f --- /dev/null +++ b/components/soc/esp32h4/etm_periph.c @@ -0,0 +1,10 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/etm_periph.h" +#include "soc/soc_etm_reg.h" + +// TODO: [ESP32H4] IDF-12356 Support sleep retention diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index b79482ea9f..4ba8aa3374 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -19,6 +19,10 @@ config SOC_GPTIMER_SUPPORTED bool default y +config SOC_ETM_SUPPORTED + bool + default y + config SOC_ASYNC_MEMCPY_SUPPORTED bool default y @@ -203,6 +207,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 5 +config SOC_GDMA_SUPPORT_ETM + bool + default y + config SOC_GDMA_SUPPORT_SLEEP_RETENTION bool default y @@ -211,6 +219,14 @@ config SOC_AHB_GDMA_SUPPORT_PSRAM bool default y +config SOC_ETM_GROUPS + int + default 1 + +config SOC_ETM_CHANNELS_PER_GROUP + int + default 50 + config SOC_GPIO_PORT int default 1 @@ -227,6 +243,18 @@ config SOC_GPIO_OUT_RANGE_MAX int default 39 +config SOC_GPIO_SUPPORT_ETM + bool + default y + +config SOC_GPIO_ETM_EVENTS_PER_GROUP + int + default 8 + +config SOC_GPIO_ETM_TASKS_PER_GROUP + int + default 8 + config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y @@ -303,6 +331,10 @@ config SOC_I2S_HW_VERSION_2 bool default y +config SOC_I2S_SUPPORTS_ETM + bool + default y + config SOC_I2S_SUPPORTS_ETM_SYNC bool default y @@ -467,6 +499,14 @@ config SOC_LP_TIMER_BIT_WIDTH_HI int default 16 +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + +config SOC_TIMER_SUPPORT_ETM + bool + default y + config SOC_TIMER_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index d62089c6af..4ec809c29f 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -41,7 +41,7 @@ // #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12338 // #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12352 -// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12355 +#define SOC_ETM_SUPPORTED 1 // #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347 // #define SOC_BT_SUPPORTED 1 // #define SOC_IEEE802154_SUPPORTED 1 @@ -191,13 +191,14 @@ #define SOC_AHB_GDMA_VERSION 2 #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 5 -// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383 +#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 #define SOC_AHB_GDMA_SUPPORT_PSRAM 1 /*-------------------------- ETM CAPS --------------------------------------*/ -// #define SOC_ETM_GROUPS 1U // Number of ETM groups -// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define SOC_ETM_GROUPS 1U // Number of ETM groups +#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12356 Support sleep retention /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-H4 has 1 GPIO peripheral @@ -212,9 +213,9 @@ // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 // TODO: [ESP32H4] IDF-12391 // GPIO peripheral has the ETM extension -// #define SOC_GPIO_SUPPORT_ETM 1 // TODO: [ESP32H4] IDF-12394 -// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 -// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 +#define SOC_GPIO_SUPPORT_ETM 1 +#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 +#define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // Target has the full LP IO subsystem // On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. @@ -270,7 +271,7 @@ /*-------------------------- I2S CAPS ----------------------------------------*/ #define SOC_I2S_NUM (1U) #define SOC_I2S_HW_VERSION_2 (1) -// #define SOC_I2S_SUPPORTS_ETM (1) +#define SOC_I2S_SUPPORTS_ETM (1) #define SOC_I2S_SUPPORTS_ETM_SYNC (1) #define SOC_I2S_SUPPORTS_XTAL (1) #define SOC_I2S_SUPPORTS_PLL_F96M (1) @@ -438,7 +439,7 @@ #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) -// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part @@ -446,6 +447,7 @@ /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ // #define SOC_TIMER_SUPPORT_ETM (1) // TODO: [ESP32H4] IDF-12355 +#define SOC_TIMER_SUPPORT_ETM (1) #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld index 41efe6e6ac..75d9913d03 100644 --- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld @@ -43,6 +43,7 @@ PROVIDE ( TIMERG1 = 0x60091000 ); PROVIDE ( IO_MUX = 0x60092000 ); PROVIDE ( GPIO = 0x60093000 ); PROVIDE ( GPIO_EXT = 0x60093E00 ); +PROVIDE ( GPIO_ETM = 0x60093F18 ); PROVIDE ( PCR = 0x60094000 ); PROVIDE ( SPIMEM0 = 0x60098000 ); PROVIDE ( SPIMEM1 = 0x60099000 ); diff --git a/components/soc/esp32h4/register/soc/gpio_ext_struct.h b/components/soc/esp32h4/register/soc/gpio_ext_struct.h index 74fb747353..da06484c0b 100644 --- a/components/soc/esp32h4/register/soc/gpio_ext_struct.h +++ b/components/soc/esp32h4/register/soc/gpio_ext_struct.h @@ -117,7 +117,7 @@ typedef union { uint32_t val; } gpio_ext_etm_event_chn_cfg_reg_t; -/** Type of ext_etm_task_p0_cfg register +/** Type of ext_etm_task_pn_cfg register * GPIO selection register 0 for ETM */ typedef union { @@ -200,602 +200,7 @@ typedef union { uint32_t reserved_30:2; }; uint32_t val; -} gpio_ext_etm_task_p0_cfg_reg_t; - -/** Type of ext_etm_task_p1_cfg register - * GPIO selection register 1 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO5. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio5_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO5 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio5_en:1; - /** ext_etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO6. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio6_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio6_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO6 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio6_en:1; - /** ext_etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO7. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio7_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio7_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO7 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio7_en:1; - /** ext_etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO8. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio8_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio8_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO8 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio8_en:1; - /** ext_etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO9. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio9_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio9_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO9 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio9_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p1_cfg_reg_t; - -/** Type of ext_etm_task_p2_cfg register - * GPIO selection register 2 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO10. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio10_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio10_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO10 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio10_en:1; - /** ext_etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO11. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio11_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio11_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO11 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio11_en:1; - /** ext_etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO12. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio12_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio12_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO12 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio12_en:1; - /** ext_etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO13. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio13_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio13_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO13 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio13_en:1; - /** ext_etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO14. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio14_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio14_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO14 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio14_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p2_cfg_reg_t; - -/** Type of ext_etm_task_p3_cfg register - * GPIO selection register 3 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO15. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio15_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio15_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO15 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio15_en:1; - /** ext_etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO16. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio16_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio16_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO16 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio16_en:1; - /** ext_etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO17. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio17_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio17_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO17 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio17_en:1; - /** ext_etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO18. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio18_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio18_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO18 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio18_en:1; - /** ext_etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO19. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio19_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio19_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO19 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio19_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p3_cfg_reg_t; - -/** Type of ext_etm_task_p4_cfg register - * GPIO selection register 4 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO20. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio20_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio20_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO20 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio20_en:1; - /** ext_etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO21. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio21_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio21_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO21 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio21_en:1; - /** ext_etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO22. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio22_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio22_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO22 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio22_en:1; - /** ext_etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO23. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio23_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio23_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO23 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio23_en:1; - /** ext_etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO24. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio24_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio24_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO24 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio24_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p4_cfg_reg_t; - -/** Type of ext_etm_task_p5_cfg register - * GPIO selection register 5 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO25. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio25_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio25_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO25 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio25_en:1; - /** ext_etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO26. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio26_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio26_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO26 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio26_en:1; - /** ext_etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO27. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio27_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio27_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO27 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio27_en:1; - /** ext_etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO28. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio28_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio28_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO28 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio28_en:1; - /** ext_etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO29. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio29_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio29_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO29 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio29_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p5_cfg_reg_t; - -/** Type of ext_etm_task_p6_cfg register - * GPIO selection register 6 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio30_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO30. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio30_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio30_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO30 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio30_en:1; - /** ext_etm_task_gpio31_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO31. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio31_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio31_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO31 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio31_en:1; - /** ext_etm_task_gpio32_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO32. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio32_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio32_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO32 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio32_en:1; - /** ext_etm_task_gpio33_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO33. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio33_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio33_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO33 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio33_en:1; - /** ext_etm_task_gpio34_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO34. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio34_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio34_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO34 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio34_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p6_cfg_reg_t; - -/** Type of ext_etm_task_p7_cfg register - * GPIO selection register 7 for ETM - */ -typedef union { - struct { - /** ext_etm_task_gpio35_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO35. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio35_sel:3; - uint32_t reserved_3:2; - /** ext_etm_task_gpio35_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO35 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio35_en:1; - /** ext_etm_task_gpio36_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO36. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio36_sel:3; - uint32_t reserved_9:2; - /** ext_etm_task_gpio36_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO36 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio36_en:1; - /** ext_etm_task_gpio37_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO37. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio37_sel:3; - uint32_t reserved_15:2; - /** ext_etm_task_gpio37_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO37 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio37_en:1; - /** ext_etm_task_gpio38_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO38. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio38_sel:3; - uint32_t reserved_21:2; - /** ext_etm_task_gpio38_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO38 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio38_en:1; - /** ext_etm_task_gpio39_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO39. - * 0: Select channel 0 - * 1: Select channel 1 - * ...... - * 7: Select channel 7 - */ - uint32_t ext_etm_task_gpio39_sel:3; - uint32_t reserved_27:2; - /** ext_etm_task_gpio39_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO39 to response ETM task. - * 0: Not enable - * 1: Enable - */ - uint32_t ext_etm_task_gpio39_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p7_cfg_reg_t; +} gpio_ext_etm_task_pn_cfg_reg_t; /** Group: Version Register */ @@ -813,6 +218,11 @@ typedef union { uint32_t val; } gpio_ext_version_reg_t; +typedef struct gpio_etm_dev_t { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[8]; +} gpio_etm_dev_t; typedef struct { uint32_t reserved_000; @@ -821,24 +231,16 @@ typedef struct { uint32_t reserved_018[48]; volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8]; uint32_t reserved_0f8[8]; - volatile gpio_ext_etm_event_chn_cfg_reg_t ext_etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_p0_cfg_reg_t ext_etm_task_p0_cfg; - volatile gpio_ext_etm_task_p1_cfg_reg_t ext_etm_task_p1_cfg; - volatile gpio_ext_etm_task_p2_cfg_reg_t ext_etm_task_p2_cfg; - volatile gpio_ext_etm_task_p3_cfg_reg_t ext_etm_task_p3_cfg; - volatile gpio_ext_etm_task_p4_cfg_reg_t ext_etm_task_p4_cfg; - volatile gpio_ext_etm_task_p5_cfg_reg_t ext_etm_task_p5_cfg; - volatile gpio_ext_etm_task_p6_cfg_reg_t ext_etm_task_p6_cfg; - volatile gpio_ext_etm_task_p7_cfg_reg_t ext_etm_task_p7_cfg; + volatile gpio_etm_dev_t etm; uint32_t reserved_178[33]; volatile gpio_ext_version_reg_t ext_version; -} gpio_dev_t; +} gpio_ext_dev_t; -extern gpio_dev_t GPIO_EXT; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; #ifndef __cplusplus -_Static_assert(sizeof(gpio_dev_t) == 0x200, "Invalid size of gpio_dev_t structure"); +_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h4/register/soc/i2s_struct.h b/components/soc/esp32h4/register/soc/i2s_struct.h index 8f80f0c893..a13672b0e1 100644 --- a/components/soc/esp32h4/register/soc/i2s_struct.h +++ b/components/soc/esp32h4/register/soc/i2s_struct.h @@ -829,7 +829,7 @@ typedef union { } i2s_lc_hung_conf_reg_t; /** Type of conf_sigle_data register - * I2S signal data register + * I2S single data register */ typedef union { struct { @@ -839,7 +839,7 @@ typedef union { uint32_t single_data:32; }; uint32_t val; -} i2s_conf_sigle_data_reg_t; +} i2s_conf_single_data_reg_t; /** Group: TX status registers */ diff --git a/components/soc/esp32h4/register/soc/soc_etm_struct.h b/components/soc/esp32h4/register/soc/soc_etm_struct.h index 2308b910e3..20e093ee20 100644 --- a/components/soc/esp32h4/register/soc/soc_etm_struct.h +++ b/components/soc/esp32h4/register/soc/soc_etm_struct.h @@ -5985,113 +5985,17 @@ typedef union { } soc_etm_date_reg_t; -typedef struct { +typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad0_reg_t etm_ch_ena_ad0; volatile soc_etm_ch_ena_ad0_set_reg_t etm_ch_ena_ad0_set; volatile soc_etm_ch_ena_ad0_clr_reg_t etm_ch_ena_ad0_clr; volatile soc_etm_ch_ena_ad1_reg_t etm_ch_ena_ad1; volatile soc_etm_ch_ena_ad1_set_reg_t etm_ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t etm_ch_ena_ad1_clr; - volatile soc_etm_chn_evt_id_reg_t etm_ch0_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch0_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch1_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch1_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch2_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch2_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch3_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch3_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch4_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch4_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch5_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch5_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch6_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch6_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch7_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch7_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch8_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch8_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch9_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch9_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch10_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch10_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch11_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch11_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch12_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch12_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch13_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch13_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch14_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch14_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch15_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch15_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch16_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch16_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch17_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch17_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch18_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch18_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch19_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch19_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch20_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch20_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch21_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch21_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch22_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch22_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch23_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch23_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch24_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch24_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch25_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch25_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch26_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch26_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch27_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch27_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch28_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch28_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch29_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch29_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch30_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch30_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch31_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch31_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch32_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch32_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch33_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch33_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch34_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch34_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch35_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch35_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch36_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch36_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch37_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch37_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch38_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch38_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch39_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch39_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch40_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch40_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch41_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch41_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch42_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch42_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch43_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch43_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch44_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch44_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch45_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch45_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch46_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch46_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch47_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch47_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch48_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch48_task_id; - volatile soc_etm_chn_evt_id_reg_t etm_ch49_evt_id; - volatile soc_etm_chn_task_id_reg_t etm_ch49_task_id; + volatile struct { + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; + } channel[50]; volatile soc_etm_evt_st0_reg_t etm_evt_st0; volatile soc_etm_evt_st0_clr_reg_t etm_evt_st0_clr; volatile soc_etm_evt_st1_reg_t etm_evt_st1; @@ -6120,12 +6024,12 @@ typedef struct { volatile soc_etm_task_st5_clr_reg_t etm_task_st5_clr; volatile soc_etm_clk_en_reg_t etm_clk_en; volatile soc_etm_date_reg_t etm_date; -} soc_dev_t; +} soc_etm_dev_t; -extern soc_dev_t SOC_ETM; +extern soc_etm_dev_t SOC_ETM; #ifndef __cplusplus -_Static_assert(sizeof(soc_dev_t) == 0x218, "Invalid size of soc_dev_t structure"); +_Static_assert(sizeof(soc_etm_dev_t) == 0x218, "Invalid size of soc_etm_dev_t structure"); #endif #ifdef __cplusplus diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md index 4843828bc2..4c19e7787c 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | +| ----------------- | -------- | -------- | --------- | -------- | -------- | -------- | # HC-SR04 Example based on GPTimer Capture and ETM From 0a110478ea4905ba1fde5a2680919738e8df51f3 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 17 Jun 2025 11:44:55 +0800 Subject: [PATCH 3/5] feat(modem_etm): support modem etm on h4 --- .../include/esp_private/etm_interface.h | 1 + .../modem/include/modem/modem_etm.h | 86 +++++++++++++++++++ components/esp_hw_support/modem/modem_etm.c | 69 +++++++++++++++ .../hal/esp32h4/include/hal/modem_etm_ll.h | 83 ++++++++++++++++++ .../esp32h4/include/soc/Kconfig.soc_caps.in | 4 + 5 files changed, 243 insertions(+) create mode 100644 components/esp_hw_support/modem/include/modem/modem_etm.h create mode 100644 components/esp_hw_support/modem/modem_etm.c create mode 100644 components/hal/esp32h4/include/hal/modem_etm_ll.h diff --git a/components/esp_hw_support/include/esp_private/etm_interface.h b/components/esp_hw_support/include/esp_private/etm_interface.h index 201ea67e4d..5b22a38dea 100644 --- a/components/esp_hw_support/include/esp_private/etm_interface.h +++ b/components/esp_hw_support/include/esp_private/etm_interface.h @@ -29,6 +29,7 @@ typedef enum { ETM_TRIG_PERIPH_TSENS, /*!< ETM trigger source: Temperature Sensor */ ETM_TRIG_PERIPH_I2S, /*!< ETM trigger source: I2S */ ETM_TRIG_PERIPH_LP_CORE, /*!< ETM trigger source: Low-Power Core */ + ETM_TRIG_PERIPH_MODEM, /*!< ETM trigger source: Modem */ } etm_trigger_peripheral_t; /** diff --git a/components/esp_hw_support/modem/include/modem/modem_etm.h b/components/esp_hw_support/modem/include/modem/modem_etm.h new file mode 100644 index 0000000000..517c706a9f --- /dev/null +++ b/components/esp_hw_support/modem/include/modem/modem_etm.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Modem ETM event type + * + * @note The event type is used to identify the event type. + */ +typedef enum { + MODEM_ETM_EVENT_G0 = 0, /*!< Modem ETM event group 0 */ + MODEM_ETM_EVENT_G1 = 1, /*!< Modem ETM event group 1 */ + MODEM_ETM_EVENT_G2 = 2, /*!< Modem ETM event group 2 */ + MODEM_ETM_EVENT_G3 = 3, /*!< Modem ETM event group 3 */ + MODEM_ETM_EVENT_MAX, +} modem_etm_event_type_t; + +/** + * @brief Modem ETM task type + * + * @note The task type is used to identify the task type. + */ +typedef enum { + MODEM_ETM_TASK_G0 = 0, /*!< Modem ETM task group 0 */ + MODEM_ETM_TASK_G1 = 1, /*!< Modem ETM task group 1 */ + MODEM_ETM_TASK_G2 = 2, /*!< Modem ETM task group 2 */ + MODEM_ETM_TASK_G3 = 3, /*!< Modem ETM task group 3 */ + MODEM_ETM_TASK_MAX, +} modem_etm_task_type_t; + +/** + * @brief Modem ETM event configuration + * + * @note The event configuration is used to configure the event. + */ +typedef struct { + modem_etm_event_type_t event_type; /*!< Modem ETM event type */ +} modem_etm_event_config_t; + +/** + * @brief Modem ETM task configuration + * + * @note The task configuration is used to configure the task. + */ +typedef struct { + modem_etm_task_type_t task_type; /*!< Modem ETM task type */ +} modem_etm_task_config_t; + + +/** + * @brief Create a new modem ETM event + * + * @param config The modem ETM event configuration + * @param out_event The output modem ETM event handle + * @return + * - ESP_OK: Success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: No memory + */ +esp_err_t modem_new_etm_event(const modem_etm_event_config_t *config, esp_etm_event_handle_t *out_event); + +/** + * @brief Create a new modem ETM task + * + * @param config The modem ETM task configuration + * @param out_task The output modem ETM task handle + * @return + * - ESP_OK: Success + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: No memory + */ +esp_err_t modem_new_etm_task(const modem_etm_task_config_t *config, esp_etm_task_handle_t *out_task); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/modem/modem_etm.c b/components/esp_hw_support/modem/modem_etm.c new file mode 100644 index 0000000000..23c8952b38 --- /dev/null +++ b/components/esp_hw_support/modem/modem_etm.c @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "esp_check.h" +#include "esp_heap_caps.h" +#include "modem/modem_etm.h" +#include "hal/modem_ll.h" +#include "esp_private/etm_interface.h" + +#define ETM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT + +static const char *TAG = "modem-etm"; + +static esp_err_t s_modem_del_etm_event(esp_etm_event_t *event) +{ + free(event); + return ESP_OK; +} + +static esp_err_t s_modem_del_etm_task(esp_etm_task_t *task) +{ + free(task); + return ESP_OK; +} + +esp_err_t modem_new_etm_event(const modem_etm_event_config_t *config, esp_etm_event_handle_t *out_event) +{ + ESP_RETURN_ON_FALSE(config && out_event, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(config->event_type < MODEM_ETM_EVENT_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid event type"); + esp_etm_event_t *event = heap_caps_calloc(1, sizeof(esp_etm_event_t), ETM_MEM_ALLOC_CAPS); + ESP_RETURN_ON_FALSE(event, ESP_ERR_NO_MEM, TAG, "no memory for ETM event"); + + // Get the event id from the modem ETM event table + uint32_t event_id = MODEM_LL_ETM_EVENT_TABLE((uint32_t)config->event_type); + + // fill the ETM event object + event->event_id = event_id; + event->trig_periph = ETM_TRIG_PERIPH_MODEM; + event->del = s_modem_del_etm_event; + *out_event = event; + + return ESP_OK; +} + +esp_err_t modem_new_etm_task(const modem_etm_task_config_t *config, esp_etm_task_handle_t *out_task) +{ + ESP_RETURN_ON_FALSE(config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); + ESP_RETURN_ON_FALSE(config->task_type < MODEM_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type"); + esp_etm_task_t *task = heap_caps_calloc(1, sizeof(esp_etm_task_t), ETM_MEM_ALLOC_CAPS); + ESP_RETURN_ON_FALSE(task, ESP_ERR_NO_MEM, TAG, "no memory for ETM task"); + + // Get the task id from the modem ETM task table + uint32_t task_id = MODEM_LL_ETM_TASK_TABLE((uint32_t)config->task_type); + + // fill the ETM task object + task->task_id = task_id; + task->trig_periph = ETM_TRIG_PERIPH_MODEM; + task->del = s_modem_del_etm_task; + *out_task = task; + + return ESP_OK; +} diff --git a/components/hal/esp32h4/include/hal/modem_etm_ll.h b/components/hal/esp32h4/include/hal/modem_etm_ll.h new file mode 100644 index 0000000000..45790ebd03 --- /dev/null +++ b/components/hal/esp32h4/include/hal/modem_etm_ll.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "soc/soc_etm_struct.h" +#include "soc/soc_etm_reg.h" +#include "soc/soc_etm_source.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MODEM_LL_ETM_EVENT_TABLE(event_type) \ + (uint32_t[4]){ \ + [0] = MODEM_EVT_G0, \ + [1] = MODEM_EVT_G1, \ + [2] = MODEM_EVT_G2, \ + [3] = MODEM_EVT_G3, \ + }[event_type] + +#define MODEM_LL_ETM_TASK_TABLE(task_type) \ + (uint32_t[4]){ \ + [0] = MODEM_TASK_G0, \ + [1] = MODEM_TASK_G1, \ + [2] = MODEM_TASK_G2, \ + [3] = MODEM_TASK_G3, \ + }[task_type] + +static inline bool modem_etm_ll_get_group_event_status(int group_id) +{ + switch (group_id) { + case 0: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g0_st; + case 1: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g1_st; + case 2: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g2_st; + case 3: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g3_st; + default: + HAL_ASSERT(false); + } + return false; +} + +static inline bool modem_etm_ll_get_group_task_status(int group_id) +{ + switch (group_id) { + case 0: + return SOC_ETM.etm_task_st5.etm_modem_task_g0_st; + case 1: + return SOC_ETM.etm_task_st5.etm_modem_task_g1_st; + case 2: + return SOC_ETM.etm_task_st5.etm_modem_task_g2_st; + case 3: + return SOC_ETM.etm_task_st5.etm_modem_task_g3_st; + default: + HAL_ASSERT(false); + } + return false; +} + +static inline void modem_etm_ll_clear_group_event_status(int group_id) +{ + SOC_ETM.etm_evt_st6_clr.val = SOC_ETM_MODEM_EVT_G0_ST_CLR << group_id; +} + +static inline void modem_etm_ll_clear_group_task_status(int group_id) +{ + SOC_ETM.etm_task_st5_clr.val = SOC_ETM_MODEM_TASK_G0_ST_CLR << group_id; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 4ba8aa3374..720f4839f0 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -491,6 +491,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE bool default y +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + config SOC_LP_TIMER_BIT_WIDTH_LO int default 32 From 424991faafdb180a1b849d741b601e0846fbb865 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 15 Jul 2025 15:44:07 +0800 Subject: [PATCH 4/5] feat(i2s): support new sync feature on H4 --- components/esp_driver_i2s/Kconfig | 7 ++ components/esp_driver_i2s/i2s_common.c | 44 +++++++ components/esp_driver_i2s/i2s_etm.c | 7 +- .../include/esp_private/i2s_sync.h | 76 +++++++++++- components/esp_driver_i2s/linker.lf | 14 +++ components/hal/esp32h4/include/hal/i2s_ll.h | 109 +++++++++++++++++- components/hal/include/hal/i2s_types.h | 2 +- 7 files changed, 255 insertions(+), 4 deletions(-) create mode 100644 components/esp_driver_i2s/linker.lf diff --git a/components/esp_driver_i2s/Kconfig b/components/esp_driver_i2s/Kconfig index dc57c8c211..8f4641babb 100644 --- a/components/esp_driver_i2s/Kconfig +++ b/components/esp_driver_i2s/Kconfig @@ -8,6 +8,13 @@ menu "ESP-Driver:I2S Configurations" Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be executable when the cache is disabled (e.g. SPI Flash write). + config I2S_CTRL_FUNC_IN_IRAM + bool "Place I2S control functions into IRAM" + default n + help + Place I2S control functions into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + config I2S_ENABLE_DEBUG_LOG bool "Enable I2S debug log" default n diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index a99bdd1d23..48b88f2f1e 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -47,6 +47,7 @@ #include "driver/gpio.h" #include "esp_private/gpio.h" +#include "esp_private/i2s_sync.h" #include "driver/i2s_common.h" #include "i2s_private.h" @@ -1483,3 +1484,46 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle) i2s_ll_tx_reset_fifo_sync_counter(tx_handle->controller->hal.dev); } #endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT + +#if SOC_I2S_SUPPORTS_ETM_SYNC +uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle) +{ + return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev); +} + +void i2s_sync_reset_fifo_sync_diff_count(i2s_chan_handle_t tx_handle) +{ + i2s_ll_tx_reset_fifo_sync_diff_counter(tx_handle->controller->hal.dev); +} + +esp_err_t i2s_sync_enable_hw_fifo_sync(i2s_chan_handle_t tx_handle, bool enable) +{ + if (tx_handle->dir == I2S_DIR_RX) { + return ESP_ERR_NOT_SUPPORTED; + } + i2s_ll_tx_enable_hw_fifo_sync(tx_handle->controller->hal.dev, enable); + return ESP_OK; +} + +esp_err_t i2s_sync_config_hw_fifo_sync(i2s_chan_handle_t tx_handle, const i2s_sync_fifo_sync_config_t *config) +{ + if (!(tx_handle && config)) { + return ESP_ERR_INVALID_ARG; + } + if (tx_handle->dir == I2S_DIR_RX) { + return ESP_ERR_NOT_SUPPORTED; + } + if (config->sw_high_thresh < config->hw_low_thresh) { + return ESP_ERR_INVALID_ARG; + } + + i2s_ll_tx_set_etm_sync_ideal_cnt(tx_handle->controller->hal.dev, config->ideal_cnt); + i2s_ll_tx_set_fifo_sync_diff_conter_sw_threshold(tx_handle->controller->hal.dev, config->sw_high_thresh); + i2s_ll_tx_set_fifo_sync_diff_conter_hw_threshold(tx_handle->controller->hal.dev, config->hw_low_thresh); + i2s_ll_tx_set_hw_fifo_sync_suppl_mode(tx_handle->controller->hal.dev, (uint32_t)config->suppl_mode); + if (config->suppl_mode == I2S_SYNC_SUPPL_MODE_STATIC_DATA) { + i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(tx_handle->controller->hal.dev, config->suppl_data); + } + return ESP_OK; +} +#endif diff --git a/components/esp_driver_i2s/i2s_etm.c b/components/esp_driver_i2s/i2s_etm.c index c73058a4c7..725775dd31 100644 --- a/components/esp_driver_i2s/i2s_etm.c +++ b/components/esp_driver_i2s/i2s_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -84,6 +84,11 @@ esp_err_t i2s_new_etm_task(i2s_chan_handle_t handle, const i2s_etm_task_config_t { ESP_RETURN_ON_FALSE(handle && config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(config->task_type < I2S_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type"); +#if SOC_I2S_SUPPORTS_ETM_SYNC + ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_CHECK || handle->dir == I2S_DIR_TX, + ESP_ERR_NOT_SUPPORTED, TAG, "rx is not supported"); +#endif + i2s_etm_task_t *task = heap_caps_calloc(1, sizeof(i2s_etm_task_t), ETM_MEM_ALLOC_CAPS); ESP_RETURN_ON_FALSE(task, ESP_ERR_NO_MEM, TAG, "no memory for ETM task"); diff --git a/components/esp_driver_i2s/include/esp_private/i2s_sync.h b/components/esp_driver_i2s/include/esp_private/i2s_sync.h index 83c4190397..68660ad7ab 100644 --- a/components/esp_driver_i2s/include/esp_private/i2s_sync.h +++ b/components/esp_driver_i2s/include/esp_private/i2s_sync.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,6 +31,7 @@ extern "C" { /** * @brief Get the counter number of BCLK ticks * @note The BCLK tick count reflects the real data that have sent on line + * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered * * @param[in] tx_handle The I2S tx channel handle * @return @@ -43,6 +44,7 @@ uint32_t i2s_sync_get_bclk_count(i2s_chan_handle_t tx_handle); * @note The FIFO count reflects how many slots have processed * Normally, fifo_cnt = slot_bit_width * bclk_cnt * If fifo_cnt < slot_bit_width * bclk_cnt, that means some data are still stuck in the I2S controller + * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered * * @param[in] tx_handle The I2S tx channel handle * @return @@ -66,6 +68,78 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle); #endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT +#if SOC_I2S_SUPPORTS_ETM_SYNC +/** + * @brief I2S hardware FIFO synchronization supplement mode + * @note When the FIFO sync difference count is out of threshold, the hardware will supplement data automatically + * This type is to specify which data will be supplemented + */ +typedef enum { + I2S_SYNC_SUPPL_MODE_LAST_DATA = 0, /*!< Supplement with the last transmitted data */ + I2S_SYNC_SUPPL_MODE_STATIC_DATA = 1, /*!< Supplement with static data specified in config */ +} i2s_sync_suppl_mode_t; + +/** + * @brief I2S hardware FIFO synchronization configuration + * @note This configuration is used for multi I2S port synchronization via ETM + */ +typedef struct { + uint32_t hw_low_thresh; /*!< Lower threshold for FIFO sync difference counter + - If difference count < hw_low_thresh, do nothing + - If difference count >= hw_low_thresh, the hardware will supplement data automatically */ + uint32_t sw_high_thresh; /*!< Upper threshold for FIFO sync difference counter + - If difference count <= sw_high_thresh, the hardware supplement data automatically + - If difference count > sw_high_thresh, sync interrupt triggered and + the software is responsible to decide how to handle this severe asynchronization */ + uint32_t ideal_cnt; /*!< Ideal count for FIFO sync difference counter, it depends on the ETM sync task interval and the data rate */ + i2s_sync_suppl_mode_t suppl_mode; /*!< Data supplement mode when FIFO sync difference is out of threshold */ + uint32_t suppl_data; /*!< Static supplement data, only valid when suppl_mode is I2S_SYNC_SUPPL_MODE_STATIC_DATA */ +} i2s_sync_fifo_sync_config_t; + +/** + * @brief Get the counter number of FIFO sync difference + * @note The FIFO sync difference count reflects the difference between current FIFO count and ideal count + * + * @param[in] tx_handle The I2S tx channel handle + * @return + * - FIFO sync difference count + */ +uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle); + +/** + * @brief Reset the FIFO sync difference counter + * + * @param[in] tx_handle The I2S tx channel handle + */ +void i2s_sync_reset_fifo_sync_diff_count(i2s_chan_handle_t tx_handle); + +/** + * @brief Enable or disable hardware FIFO synchronization + * @note When enabled, hardware will automatically supplement data when FIFO sync difference is greater than hw_low_thresh + * + * @param[in] tx_handle The I2S tx channel handle + * @param[in] enable true to enable, false to disable + * @return + * - ESP_OK on success + * - ESP_ERR_NOT_SUPPORTED if called on RX channel + */ +esp_err_t i2s_sync_enable_hw_fifo_sync(i2s_chan_handle_t tx_handle, bool enable); + +/** + * @brief Configure hardware FIFO synchronization parameters + * @note This function configures the thresholds and supplement mode for hardware FIFO sync + * + * @param[in] tx_handle The I2S tx channel handle + * @param[in] config Configuration for hardware FIFO synchronization + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_ARG if invalid arguments + * - ESP_ERR_NOT_SUPPORTED if called on RX channel + */ +esp_err_t i2s_sync_config_hw_fifo_sync(i2s_chan_handle_t tx_handle, const i2s_sync_fifo_sync_config_t *config); + +#endif + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_i2s/linker.lf b/components/esp_driver_i2s/linker.lf new file mode 100644 index 0000000000..9bb2330d24 --- /dev/null +++ b/components/esp_driver_i2s/linker.lf @@ -0,0 +1,14 @@ +[mapping:i2s_driver] +archive: libesp_driver_i2s.a +entries: + if I2S_CTRL_FUNC_IN_IRAM = y: + if SOC_I2S_SUPPORTS_TX_SYNC_CNT = y: + i2s_common: i2s_sync_get_bclk_count (noflash) + i2s_common: i2s_sync_get_fifo_count (noflash) + i2s_common: i2s_sync_reset_bclk_count (noflash) + i2s_common: i2s_sync_reset_fifo_count (noflash) + if SOC_I2S_SUPPORTS_ETM_SYNC = y: + i2s_common: i2s_sync_get_fifo_sync_diff_count (noflash) + i2s_common: i2s_sync_reset_fifo_sync_diff_count (noflash) + i2s_common: i2s_sync_enable_hw_fifo_sync (noflash) + i2s_common: i2s_sync_config_hw_fifo_sync (noflash) diff --git a/components/hal/esp32h4/include/hal/i2s_ll.h b/components/hal/esp32h4/include/hal/i2s_ll.h index 4abbb4f07d..9197e0d2b4 100644 --- a/components/hal/esp32h4/include/hal/i2s_ll.h +++ b/components/hal/esp32h4/include/hal/i2s_ll.h @@ -60,7 +60,7 @@ extern "C" { [I2S_DIR_RX - 1] = { \ [I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \ [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \ - [I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \ + [I2S_ETM_TASK_SYNC_CHECK] = -1, \ }, \ [I2S_DIR_TX - 1] = { \ [I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \ @@ -1245,6 +1245,113 @@ static inline uint32_t i2s_ll_tx_get_bclk_sync_count(i2s_dev_t *hw) return hw->bck_cnt.tx_bck_cnt; } +/** + * @brief Enable TX FIFO synchronization hardware mode + * + * @param hw Peripheral I2S hardware instance address. + * @param enable Set true to enable hardware mode + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_enable_hw_fifo_sync(i2s_dev_t *hw, bool enable) +{ + hw->hw_sync_conf.tx_hw_sync_en = enable; +} + +/** + * @brief Get TX FIFO synchronization difference count value + * + * @param hw Peripheral I2S hardware instance address. + * @return + * fifo count value + */ +__attribute__((always_inline)) +static inline uint32_t i2s_ll_tx_get_fifo_sync_diff_count(i2s_dev_t *hw) +{ + return hw->cnt_diff.tx_cnt_diff; +} + +/** + * @brief Reset TX FIFO synchronization difference counter + * + * @param hw Peripheral I2S hardware instance address. + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_reset_fifo_sync_diff_counter(i2s_dev_t *hw) +{ + hw->cnt_diff.tx_cnt_diff_rst = 1; + hw->cnt_diff.tx_cnt_diff_rst = 0; +} + +/** + * @brief Set TX FIFO synchronization difference counter software threshold + * @note It determines the up threshold that the hardware synchronize the data automatically. + * - If diff_count <= sw_threshold, the hardware will synchronize the data automatically. + * - If diff_count > sw_threshold, the automatic synchronization is not proper for this case, + * interrupt will be triggered to let the software decide how to handle this case. + * + * @param hw Peripheral I2S hardware instance address. + * @param thresh The threshold that send + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_set_fifo_sync_diff_conter_sw_threshold(i2s_dev_t *hw, uint32_t thresh) +{ + hw->sync_sw_thres.tx_cnt_diff_sw_thres = thresh; +} + +/** + * @brief Set TX FIFO synchronization difference counter hardware threshold + * @note It determines the down threshold that the hardware synchronize the data automatically. + * - If diff_count < hw_threshold, synchronization check pass, do nothing + * - If diff_count >= hw_threshold, the hardware will synchronize the data automatically. + * + * @param hw Peripheral I2S hardware instance address. + * @param thresh The threshold that send + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_set_fifo_sync_diff_conter_hw_threshold(i2s_dev_t *hw, uint32_t thresh) +{ + hw->sync_hw_thres.tx_cnt_diff_hw_thres = thresh; +} + +/** + * @brief Set TX FIFO synchronization hardware data supplementation mode + * @note It determines the supplementation data when the actual sent data is less than the `diff_count - threshold` + * + * @param hw Peripheral I2S hardware instance address. + * @param mode Data supplementation mode + * - 0: Supplement the last data + * - 1: Supplement the data configured in `hw_sync_data` reg + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_set_hw_fifo_sync_suppl_mode(i2s_dev_t *hw, uint32_t mode) +{ + hw->hw_sync_conf.tx_hw_sync_suppl_mode = mode; +} + +/** + * @brief Set TX FIFO synchronization hardware supplementation data when `tx_hw_sync_suppl_mode` is 1 + * + * @param hw Peripheral I2S hardware instance address. + * @param data Data to be supplemented when `tx_hw_sync_suppl_mode` is 1 + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(i2s_dev_t *hw, uint32_t data) +{ + hw->hw_sync_data.tx_hw_sync_suppl_data = data; +} + +/** + * @brief Set the TX ETM synchronization ideal count + * + * @param hw Peripheral I2S hardware instance address. + * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_CHECK triggered. + */ +__attribute__((always_inline)) +static inline void i2s_ll_tx_set_etm_sync_ideal_cnt(i2s_dev_t *hw, uint32_t ideal_cnt) +{ + hw->ideal_cnt.tx_ideal_cnt = ideal_cnt; +} + /** * @brief Set the TX ETM threshold of REACH_THRESH event * diff --git a/components/hal/include/hal/i2s_types.h b/components/hal/include/hal/i2s_types.h index 773a8d1ac5..90c0d7a213 100644 --- a/components/hal/include/hal/i2s_types.h +++ b/components/hal/include/hal/i2s_types.h @@ -234,7 +234,7 @@ typedef enum { I2S_ETM_TASK_START, /*!< Start the I2S channel */ I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */ #if SOC_I2S_SUPPORTS_ETM_SYNC - I2S_ETM_TASK_SYNC_CHECK, /*!< Stop the I2S channel */ + I2S_ETM_TASK_SYNC_CHECK, /*!< Check the I2S TX channel sync status */ #endif I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */ } i2s_etm_task_type_t; From 263a056486a73fa5e5a5f7cbf4ba6f046e7b48e2 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 16 Jul 2025 12:08:09 +0800 Subject: [PATCH 5/5] feat: add i2s & etm sleep retention entry on H4 --- components/esp_driver_i2s/CMakeLists.txt | 1 + components/esp_driver_i2s/i2s_common.c | 10 +- components/esp_driver_i2s/i2s_etm.c | 6 +- .../include/esp_private/i2s_sync.h | 7 +- components/esp_driver_i2s/linker.lf | 5 +- .../test_apps/i2s/sdkconfig.ci.iram_safe | 1 + components/hal/esp32h4/include/hal/i2s_ll.h | 6 +- components/hal/include/hal/i2s_types.h | 4 +- components/soc/esp32/register/soc/i2s_reg.h | 17 +- components/soc/esp32c3/include/soc/soc.h | 1 - components/soc/esp32c3/register/soc/i2s_reg.h | 14 +- components/soc/esp32c5/include/soc/soc.h | 1 - components/soc/esp32c5/register/soc/i2s_reg.h | 2 + components/soc/esp32c6/include/soc/soc.h | 1 - components/soc/esp32c6/register/soc/i2s_reg.h | 2 + components/soc/esp32c61/include/soc/soc.h | 1 - .../soc/esp32c61/register/soc/i2s_reg.h | 2 + components/soc/esp32h2/include/soc/soc.h | 1 - components/soc/esp32h2/register/soc/i2s_reg.h | 2 + components/soc/esp32h4/etm_periph.c | 36 ++- components/soc/esp32h4/i2s_periph.c | 43 +++ .../esp32h4/include/soc/Kconfig.soc_caps.in | 20 +- components/soc/esp32h4/include/soc/soc_caps.h | 7 +- components/soc/esp32h4/register/soc/i2s_reg.h | 60 ++-- .../soc/esp32h4/register/soc/soc_etm_reg.h | 268 +++++++++--------- components/soc/esp32p4/include/soc/soc.h | 1 - .../esp32p4/register/hw_ver1/soc/i2s_reg.h | 2 + components/soc/esp32s2/include/soc/soc.h | 1 - components/soc/esp32s2/register/soc/i2s_reg.h | 14 +- components/soc/esp32s3/include/soc/soc.h | 1 - components/soc/esp32s3/register/soc/i2s_reg.h | 13 +- 31 files changed, 317 insertions(+), 233 deletions(-) diff --git a/components/esp_driver_i2s/CMakeLists.txt b/components/esp_driver_i2s/CMakeLists.txt index 2498fa6126..f8bcfb91dc 100644 --- a/components/esp_driver_i2s/CMakeLists.txt +++ b/components/esp_driver_i2s/CMakeLists.txt @@ -37,4 +37,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${include} PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm + LDFRAGMENTS linker.lf ) diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index 48b88f2f1e..e4178cad53 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -575,7 +575,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz) } #if SOC_GDMA_SUPPORTED -static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +static bool i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data; BaseType_t need_yield1 = 0; @@ -606,7 +606,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e return need_yield1 | need_yield2 | user_need_yield; } -static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +static bool i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data; BaseType_t need_yield1 = 0; @@ -653,7 +653,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e #else -static void IRAM_ATTR i2s_dma_rx_callback(void *arg) +static void i2s_dma_rx_callback(void *arg) { BaseType_t need_yield1 = 0; BaseType_t need_yield2 = 0; @@ -691,7 +691,7 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg) } } -static void IRAM_ATTR i2s_dma_tx_callback(void *arg) +static void i2s_dma_tx_callback(void *arg) { BaseType_t need_yield1 = 0; BaseType_t need_yield2 = 0; @@ -1485,7 +1485,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle) } #endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT -#if SOC_I2S_SUPPORTS_ETM_SYNC +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle) { return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev); diff --git a/components/esp_driver_i2s/i2s_etm.c b/components/esp_driver_i2s/i2s_etm.c index 725775dd31..cdecd3e2b0 100644 --- a/components/esp_driver_i2s/i2s_etm.c +++ b/components/esp_driver_i2s/i2s_etm.c @@ -84,9 +84,9 @@ esp_err_t i2s_new_etm_task(i2s_chan_handle_t handle, const i2s_etm_task_config_t { ESP_RETURN_ON_FALSE(handle && config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(config->task_type < I2S_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type"); -#if SOC_I2S_SUPPORTS_ETM_SYNC - ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_CHECK || handle->dir == I2S_DIR_TX, - ESP_ERR_NOT_SUPPORTED, TAG, "rx is not supported"); +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC + ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_FIFO || handle->dir == I2S_DIR_TX, + ESP_ERR_NOT_SUPPORTED, TAG, "rx does not support sync check"); #endif i2s_etm_task_t *task = heap_caps_calloc(1, sizeof(i2s_etm_task_t), ETM_MEM_ALLOC_CAPS); diff --git a/components/esp_driver_i2s/include/esp_private/i2s_sync.h b/components/esp_driver_i2s/include/esp_private/i2s_sync.h index 68660ad7ab..f066bf0ea8 100644 --- a/components/esp_driver_i2s/include/esp_private/i2s_sync.h +++ b/components/esp_driver_i2s/include/esp_private/i2s_sync.h @@ -21,6 +21,7 @@ #include #include "driver/i2s_types.h" +#include "esp_err.h" #ifdef __cplusplus extern "C" { @@ -31,7 +32,7 @@ extern "C" { /** * @brief Get the counter number of BCLK ticks * @note The BCLK tick count reflects the real data that have sent on line - * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered + * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered * * @param[in] tx_handle The I2S tx channel handle * @return @@ -44,7 +45,7 @@ uint32_t i2s_sync_get_bclk_count(i2s_chan_handle_t tx_handle); * @note The FIFO count reflects how many slots have processed * Normally, fifo_cnt = slot_bit_width * bclk_cnt * If fifo_cnt < slot_bit_width * bclk_cnt, that means some data are still stuck in the I2S controller - * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered + * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered * * @param[in] tx_handle The I2S tx channel handle * @return @@ -68,7 +69,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle); #endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT -#if SOC_I2S_SUPPORTS_ETM_SYNC +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC /** * @brief I2S hardware FIFO synchronization supplement mode * @note When the FIFO sync difference count is out of threshold, the hardware will supplement data automatically diff --git a/components/esp_driver_i2s/linker.lf b/components/esp_driver_i2s/linker.lf index 9bb2330d24..ed2ae42edf 100644 --- a/components/esp_driver_i2s/linker.lf +++ b/components/esp_driver_i2s/linker.lf @@ -1,13 +1,16 @@ [mapping:i2s_driver] archive: libesp_driver_i2s.a entries: + if I2S_ISR_IRAM_SAFE = y: + i2s_common: i2s_dma_rx_callback (noflash) + i2s_common: i2s_dma_tx_callback (noflash) if I2S_CTRL_FUNC_IN_IRAM = y: if SOC_I2S_SUPPORTS_TX_SYNC_CNT = y: i2s_common: i2s_sync_get_bclk_count (noflash) i2s_common: i2s_sync_get_fifo_count (noflash) i2s_common: i2s_sync_reset_bclk_count (noflash) i2s_common: i2s_sync_reset_fifo_count (noflash) - if SOC_I2S_SUPPORTS_ETM_SYNC = y: + if SOC_I2S_SUPPORTS_TX_FIFO_SYNC = y: i2s_common: i2s_sync_get_fifo_sync_diff_count (noflash) i2s_common: i2s_sync_reset_fifo_sync_diff_count (noflash) i2s_common: i2s_sync_enable_hw_fifo_sync (noflash) diff --git a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe index 0128347673..8351f4355c 100644 --- a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe +++ b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe @@ -1,5 +1,6 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_I2S_ISR_IRAM_SAFE=y +CONFIG_I2S_CTRL_FUNC_IN_IRAM=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y diff --git a/components/hal/esp32h4/include/hal/i2s_ll.h b/components/hal/esp32h4/include/hal/i2s_ll.h index 9197e0d2b4..d1a97be56a 100644 --- a/components/hal/esp32h4/include/hal/i2s_ll.h +++ b/components/hal/esp32h4/include/hal/i2s_ll.h @@ -60,12 +60,12 @@ extern "C" { [I2S_DIR_RX - 1] = { \ [I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \ [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \ - [I2S_ETM_TASK_SYNC_CHECK] = -1, \ + [I2S_ETM_TASK_SYNC_FIFO] = -1, \ }, \ [I2S_DIR_TX - 1] = { \ [I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \ [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_TX, \ - [I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \ + [I2S_ETM_TASK_SYNC_FIFO] = I2S0_TASK_SYNC_CHECK, \ }}}[i2s_port][(chan_dir) - 1][task] #define I2S_LL_ETM_MAX_THRESH_NUM (0x3FFFUL) @@ -1344,7 +1344,7 @@ static inline void i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(i2s_dev_t *hw, u * @brief Set the TX ETM synchronization ideal count * * @param hw Peripheral I2S hardware instance address. - * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_CHECK triggered. + * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_FIFO triggered. */ __attribute__((always_inline)) static inline void i2s_ll_tx_set_etm_sync_ideal_cnt(i2s_dev_t *hw, uint32_t ideal_cnt) diff --git a/components/hal/include/hal/i2s_types.h b/components/hal/include/hal/i2s_types.h index 90c0d7a213..8709b3f062 100644 --- a/components/hal/include/hal/i2s_types.h +++ b/components/hal/include/hal/i2s_types.h @@ -233,8 +233,8 @@ typedef enum { typedef enum { I2S_ETM_TASK_START, /*!< Start the I2S channel */ I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */ -#if SOC_I2S_SUPPORTS_ETM_SYNC - I2S_ETM_TASK_SYNC_CHECK, /*!< Check the I2S TX channel sync status */ +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC + I2S_ETM_TASK_SYNC_FIFO, /*!< Check the I2S TX channel sync status */ #endif I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */ } i2s_etm_task_type_t; diff --git a/components/soc/esp32/register/soc/i2s_reg.h b/components/soc/esp32/register/soc/i2s_reg.h index 12dc09a677..1af259d79d 100644 --- a/components/soc/esp32/register/soc/i2s_reg.h +++ b/components/soc/esp32/register/soc/i2s_reg.h @@ -1,15 +1,17 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ +#pragma once #include "soc/soc.h" -#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) +#ifdef __cplusplus +extern "C" { +#endif +#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) #define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) /* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */ @@ -1511,7 +1513,6 @@ #define I2S_I2SDATE_V 0xFFFFFFFF #define I2S_I2SDATE_S 0 - - - -#endif /*_SOC_I2S_REG_H_ */ +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index da0dbb8a84..82cdcb061b 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI diff --git a/components/soc/esp32c3/register/soc/i2s_reg.h b/components/soc/esp32c3/register/soc/i2s_reg.h index 7412fe1a13..576392baef 100644 --- a/components/soc/esp32c3/register/soc/i2s_reg.h +++ b/components/soc/esp32c3/register/soc/i2s_reg.h @@ -1,16 +1,18 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ +#pragma once +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc/soc.h" + +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3 + #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ @@ -1037,7 +1039,3 @@ T12_5[2:0]).*/ #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 3413beeeba..a5b205e9bb 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -18,7 +18,6 @@ #define REG_UHCI_BASE(i) (DR_REG_UHCI_BASE) // only one UHCI on C5 #define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 #define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5 diff --git a/components/soc/esp32c5/register/soc/i2s_reg.h b/components/soc/esp32c5/register/soc/i2s_reg.h index 62199e9d66..0c54601fdb 100644 --- a/components/soc/esp32c5/register/soc/i2s_reg.h +++ b/components/soc/esp32c5/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index af3ed6c919..f38495b1c0 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6 diff --git a/components/soc/esp32c6/register/soc/i2s_reg.h b/components/soc/esp32c6/register/soc/i2s_reg.h index 4f259c1131..d7dd6b6ab6 100644 --- a/components/soc/esp32c6/register/soc/i2s_reg.h +++ b/components/soc/esp32c6/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index 838fd98a68..fa4b36f2fd 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -19,7 +19,6 @@ #define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 #define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61 diff --git a/components/soc/esp32c61/register/soc/i2s_reg.h b/components/soc/esp32c61/register/soc/i2s_reg.h index 9c999162fa..934ac15e72 100644 --- a/components/soc/esp32c61/register/soc/i2s_reg.h +++ b/components/soc/esp32c61/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index df2b8f2a01..d7f5cddd5e 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI diff --git a/components/soc/esp32h2/register/soc/i2s_reg.h b/components/soc/esp32h2/register/soc/i2s_reg.h index 95b982407e..e1e4477442 100644 --- a/components/soc/esp32h2/register/soc/i2s_reg.h +++ b/components/soc/esp32h2/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32h4/etm_periph.c b/components/soc/esp32h4/etm_periph.c index d54078bd9f..82e5ac6ffb 100644 --- a/components/soc/esp32h4/etm_periph.c +++ b/components/soc/esp32h4/etm_periph.c @@ -7,4 +7,38 @@ #include "soc/etm_periph.h" #include "soc/soc_etm_reg.h" -// TODO: [ESP32H4] IDF-12356 Support sleep retention +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32h4/i2s_periph.c b/components/soc/esp32h4/i2s_periph.c index b3b72dc12d..2e3b4d82b4 100644 --- a/components/soc/esp32h4/i2s_periph.c +++ b/components/soc/esp32h4/i2s_periph.c @@ -32,3 +32,46 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { .irq = ETS_I2S_INTR_SOURCE, } }; + +/** + * I2S Registers to be saved during sleep retention + * - I2S_INT_ENA_REG + * - I2S_RX_CONF_REG + * - I2S_TX_CONF_REG + * - I2S_RX_CONF1_REG + * - I2S_TX_CONF1_REG + * - I2S_TX_PCM2PDM_CONF_REG + * - I2S_TX_PCM2PDM_CONF1_REG + * - I2S_RX_TDM_CTRL_REG + * - I2S_TX_TDM_CTRL_REG + * - I2S_RXEOF_NUM_REG + * - I2S_ETM_CONF_REG + * - I2S_IDEAL_CNT_REG + * - I2S_SYNC_SW_THRES_REG + * - I2S_SYNC_HW_THRES_REG + * - I2S_HW_SYNC_CONF_REG + * - I2S_HW_SYNC_DATA_REG +*/ + +#define I2S_RETENTION_REGS_CNT 16 +#define I2S_RETENTION_REGS_BASE(i) (I2S_INT_ENA_REG(i)) +static const uint32_t i2s_regs_map[4] = {0xf191b079, 0x0, 0x0, 0x0}; +#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \ + REGDMA_I2S_LINK(0x00), \ + I2S_RETENTION_REGS_BASE(i2s_port), \ + I2S_RETENTION_REGS_BASE(i2s_port), \ + I2S_RETENTION_REGS_CNT, 0, 0, \ + i2s_regs_map[0], i2s_regs_map[1], \ + i2s_regs_map[2], i2s_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; +static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0); + +const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = { + [0] = { + .retention_module = SLEEP_RETENTION_MODULE_I2S0, + .entry_array = i2s0_regs_retention, + .array_size = ARRAY_SIZE(i2s0_regs_retention) + }, +}; diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 720f4839f0..63bcc7ae6c 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -227,6 +227,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 @@ -335,10 +339,6 @@ config SOC_I2S_SUPPORTS_ETM bool default y -config SOC_I2S_SUPPORTS_ETM_SYNC - bool - default y - config SOC_I2S_SUPPORTS_XTAL bool default y @@ -375,6 +375,10 @@ config SOC_I2S_SUPPORTS_TX_SYNC_CNT bool default y +config SOC_I2S_SUPPORTS_TX_FIFO_SYNC + bool + default y + config SOC_I2S_PDM_MAX_TX_LINES int default 2 @@ -391,6 +395,10 @@ config SOC_I2S_TDM_FULL_DATA_WIDTH bool default y +config SOC_I2S_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_LEDC_CHANNEL_NUM int default 6 @@ -503,10 +511,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI int default 16 -config SOC_SYSTIMER_SUPPORT_ETM - bool - default y - config SOC_TIMER_SUPPORT_ETM bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 4ec809c29f..1004c6da4c 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -198,7 +198,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group -// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12356 Support sleep retention +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-H4 has 1 GPIO peripheral @@ -272,7 +272,6 @@ #define SOC_I2S_NUM (1U) #define SOC_I2S_HW_VERSION_2 (1) #define SOC_I2S_SUPPORTS_ETM (1) -#define SOC_I2S_SUPPORTS_ETM_SYNC (1) #define SOC_I2S_SUPPORTS_XTAL (1) #define SOC_I2S_SUPPORTS_PLL_F96M (1) #define SOC_I2S_SUPPORTS_PLL_F64M (1) @@ -282,13 +281,13 @@ #define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter #define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data #define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1) +#define SOC_I2S_SUPPORTS_TX_FIFO_SYNC (1) #define SOC_I2S_PDM_MAX_TX_LINES (2) #define SOC_I2S_PDM_MAX_RX_LINES (1U) #define SOC_I2S_SUPPORTS_TDM (1) #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ -// TODO: [ESP32H4] IDF-12386 -// #define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */ +#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */ /*-------------------------- LEDC CAPS ---------------------------------------*/ // #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) diff --git a/components/soc/esp32h4/register/soc/i2s_reg.h b/components/soc/esp32h4/register/soc/i2s_reg.h index dfbf964bd6..009cc75002 100644 --- a/components/soc/esp32h4/register/soc/i2s_reg.h +++ b/components/soc/esp32h4/register/soc/i2s_reg.h @@ -11,10 +11,12 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S0_BASE) // only one I2S on H4 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ -#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc) /** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt status bit for the i2s_rx_done_int interrupt */ @@ -54,7 +56,7 @@ extern "C" { /** I2S_INT_ST_REG register * I2S interrupt status register. */ -#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10) /** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status bit for the i2s_rx_done_int interrupt */ @@ -94,7 +96,7 @@ extern "C" { /** I2S_INT_ENA_REG register * I2S interrupt enable register. */ -#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14) /** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the i2s_rx_done_int interrupt */ @@ -134,7 +136,7 @@ extern "C" { /** I2S_INT_CLR_REG register * I2S interrupt clear register. */ -#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18) /** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the i2s_rx_done_int interrupt */ @@ -174,7 +176,7 @@ extern "C" { /** I2S_RX_CONF_REG register * I2S RX configure register */ -#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20) +#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20) /** I2S_RX_RESET : WT; bitpos: [0]; default: 0; * Set this bit to reset receiver */ @@ -326,7 +328,7 @@ extern "C" { /** I2S_TX_CONF_REG register * I2S TX configure register */ -#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24) +#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24) /** I2S_TX_RESET : WT; bitpos: [0]; default: 0; * Set this bit to reset transmitter */ @@ -502,7 +504,7 @@ extern "C" { /** I2S_RX_CONF1_REG register * I2S RX configure register 1 */ -#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28) +#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28) /** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * * T_bck @@ -539,7 +541,7 @@ extern "C" { /** I2S_TX_CONF1_REG register * I2S TX configure register 1 */ -#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c) +#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c) /** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * * T_bck @@ -576,7 +578,7 @@ extern "C" { /** I2S_TX_PCM2PDM_CONF_REG register * I2S TX PCM2PDM configuration register */ -#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x44) +#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x44) /** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; * I2S TX PDM OSR2 value */ @@ -658,7 +660,7 @@ extern "C" { /** I2S_TX_PCM2PDM_CONF1_REG register * I2S TX PCM2PDM configuration register */ -#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x48) +#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x48) /** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; * I2S TX PDM Fp */ @@ -693,7 +695,7 @@ extern "C" { /** I2S_RX_TDM_CTRL_REG register * I2S TX TDM mode control register */ -#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50) +#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50) /** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just * input 0 in this channel. @@ -833,7 +835,7 @@ extern "C" { /** I2S_TX_TDM_CTRL_REG register * I2S TX TDM mode control register */ -#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54) +#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54) /** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output * 0 in this channel. @@ -982,7 +984,7 @@ extern "C" { /** I2S_RX_TIMING_REG register * I2S RX timing control register */ -#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58) +#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58) /** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: * delay by neg edge. 3: not used. @@ -1051,7 +1053,7 @@ extern "C" { /** I2S_TX_TIMING_REG register * I2S TX timing control register */ -#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c) +#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c) /** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: * delay by neg edge. 3: not used. @@ -1104,7 +1106,7 @@ extern "C" { /** I2S_LC_HUNG_CONF_REG register * I2S HUNG configure register. */ -#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60) +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60) /** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered * when fifo hung counter is equal to this value @@ -1132,7 +1134,7 @@ extern "C" { /** I2S_RXEOF_NUM_REG register * I2S RX data number control register. */ -#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64) +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64) /** I2S_RX_EOF_NUM : R/W; bitpos: [15:0]; default: 64; * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0]) * . It will trigger in_suc_eof interrupt in the configured DMA RX channel. @@ -1145,7 +1147,7 @@ extern "C" { /** I2S_CONF_SIGLE_DATA_REG register * I2S signal data register */ -#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68) +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68) /** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; * The configured constant channel data to be sent out. */ @@ -1157,7 +1159,7 @@ extern "C" { /** I2S_STATE_REG register * I2S TX status register */ -#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c) +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c) /** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; * 1: i2s_tx is idle state. 0: i2s_tx is working. */ @@ -1169,7 +1171,7 @@ extern "C" { /** I2S_ETM_CONF_REG register * I2S ETM configure register */ -#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70) +#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70) /** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [13:0]; default: 64; * I2S ETM send x words event. When sending word number of * reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event. @@ -1190,7 +1192,7 @@ extern "C" { /** I2S_IDEAL_CNT_REG register * I2S sync counter register */ -#define I2S_IDEAL_CNT_REG (DR_REG_I2S_BASE + 0x74) +#define I2S_IDEAL_CNT_REG(i) (REG_I2S_BASE(i) + 0x74) /** I2S_TX_IDEAL_CNT : R/W; bitpos: [30:0]; default: 0; * tx fifo counter ideal value. */ @@ -1202,7 +1204,7 @@ extern "C" { /** I2S_FIFO_CNT_REG register * I2S sync counter register */ -#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x78) +#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x78) /** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0; * tx fifo counter value. */ @@ -1221,7 +1223,7 @@ extern "C" { /** I2S_BCK_CNT_REG register * I2S sync counter register */ -#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x7c) +#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x7c) /** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0; * tx bck counter value. */ @@ -1240,7 +1242,7 @@ extern "C" { /** I2S_CNT_DIFF_REG register * I2S sync counter register */ -#define I2S_CNT_DIFF_REG (DR_REG_I2S_BASE + 0x80) +#define I2S_CNT_DIFF_REG(i) (REG_I2S_BASE(i) + 0x80) /** I2S_TX_CNT_DIFF : RO; bitpos: [30:0]; default: 0; * tx bck counter value. */ @@ -1259,7 +1261,7 @@ extern "C" { /** I2S_SYNC_SW_THRES_REG register * I2S sync counter register */ -#define I2S_SYNC_SW_THRES_REG (DR_REG_I2S_BASE + 0x84) +#define I2S_SYNC_SW_THRES_REG(i) (REG_I2S_BASE(i) + 0x84) /** I2S_TX_CNT_DIFF_SW_THRES : R/W; bitpos: [30:0]; default: 0; * tx fifo counter difference software threshold value, when difference larger than * this threshold, interrupt will occur and hardware sync will not be executed. @@ -1272,7 +1274,7 @@ extern "C" { /** I2S_SYNC_HW_THRES_REG register * I2S sync counter register */ -#define I2S_SYNC_HW_THRES_REG (DR_REG_I2S_BASE + 0x88) +#define I2S_SYNC_HW_THRES_REG(i) (REG_I2S_BASE(i) + 0x88) /** I2S_TX_CNT_DIFF_HW_THRES : R/W; bitpos: [30:0]; default: 0; * tx fifo counter difference hardware threshold value, which means that only when * difference larger than this threshold will hardware start hardware sync. @@ -1285,7 +1287,7 @@ extern "C" { /** I2S_HW_SYNC_CONF_REG register * I2S TX hardware sync function configuration register */ -#define I2S_HW_SYNC_CONF_REG (DR_REG_I2S_BASE + 0x8c) +#define I2S_HW_SYNC_CONF_REG(i) (REG_I2S_BASE(i) + 0x8c) /** I2S_TX_HW_SYNC_EN : R/W; bitpos: [0]; default: 0; * Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable */ @@ -1305,7 +1307,7 @@ extern "C" { /** I2S_HW_SYNC_DATA_REG register * I2S TX hardware sync function configuration register */ -#define I2S_HW_SYNC_DATA_REG (DR_REG_I2S_BASE + 0x90) +#define I2S_HW_SYNC_DATA_REG(i) (REG_I2S_BASE(i) + 0x90) /** I2S_TX_HW_SYNC_SUPPL_DATA : R/W; bitpos: [31:0]; default: 0; * Configure the i2s tx hardware sync supplementation data when * I2S_TX_HW_SYNC_SUPPL_MODE is 1. @@ -1318,7 +1320,7 @@ extern "C" { /** I2S_CLK_GATE_REG register * Clock gate register */ -#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0xf8) +#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0xf8) /** I2S_CLK_EN : R/W; bitpos: [0]; default: 0; * set this bit to enable clock gate */ @@ -1330,7 +1332,7 @@ extern "C" { /** I2S_DATE_REG register * Version control register */ -#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc) +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0xfc) /** I2S_DATE : R/W; bitpos: [27:0]; default: 37818432; * I2S version control register */ diff --git a/components/soc/esp32h4/register/soc/soc_etm_reg.h b/components/soc/esp32h4/register/soc/soc_etm_reg.h index 30e259bef9..ac8a7ed36a 100644 --- a/components/soc/esp32h4/register/soc/soc_etm_reg.h +++ b/components/soc/esp32h4/register/soc/soc_etm_reg.h @@ -14,7 +14,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD0_REG register * Channel enable status register */ -#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_BASE + 0x0) +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) /** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; * Represents ch0 enable status. * 0: Disable @@ -307,7 +307,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD0_SET_REG register * Channel enable set register */ -#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_BASE + 0x4) +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) /** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; * Configures whether or not to enable ch0. * 0: Invalid, No effect @@ -600,7 +600,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD0_CLR_REG register * Channel enable clear register */ -#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_BASE + 0x8) +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) /** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ch0 enable. * 0: Invalid, No effect @@ -893,7 +893,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD1_REG register * Channel enable status register */ -#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_BASE + 0xc) +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) /** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; * Represents ch32 enable status. * 0: Disable @@ -1060,7 +1060,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD1_SET_REG register * Channel enable set register */ -#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_BASE + 0x10) +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) /** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; * Configures whether or not to enable ch32. * 0: Invalid, No effect @@ -1227,7 +1227,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD1_CLR_REG register * Channel enable clear register */ -#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_BASE + 0x14) +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) /** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ch32 enable. * 0: Invalid, No effect @@ -1394,7 +1394,7 @@ extern "C" { /** SOC_ETM_CH0_EVT_ID_REG register * Channel0 event id register */ -#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_BASE + 0x18) +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) /** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch0_evt_id */ @@ -1406,7 +1406,7 @@ extern "C" { /** SOC_ETM_CH0_TASK_ID_REG register * Channel0 task id register */ -#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_BASE + 0x1c) +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) /** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch0_task_id */ @@ -1418,7 +1418,7 @@ extern "C" { /** SOC_ETM_CH1_EVT_ID_REG register * Channel1 event id register */ -#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_BASE + 0x20) +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) /** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch1_evt_id */ @@ -1430,7 +1430,7 @@ extern "C" { /** SOC_ETM_CH1_TASK_ID_REG register * Channel1 task id register */ -#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_BASE + 0x24) +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) /** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch1_task_id */ @@ -1442,7 +1442,7 @@ extern "C" { /** SOC_ETM_CH2_EVT_ID_REG register * Channel2 event id register */ -#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_BASE + 0x28) +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) /** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch2_evt_id */ @@ -1454,7 +1454,7 @@ extern "C" { /** SOC_ETM_CH2_TASK_ID_REG register * Channel2 task id register */ -#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_BASE + 0x2c) +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) /** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch2_task_id */ @@ -1466,7 +1466,7 @@ extern "C" { /** SOC_ETM_CH3_EVT_ID_REG register * Channel3 event id register */ -#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_BASE + 0x30) +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) /** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch3_evt_id */ @@ -1478,7 +1478,7 @@ extern "C" { /** SOC_ETM_CH3_TASK_ID_REG register * Channel3 task id register */ -#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_BASE + 0x34) +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) /** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch3_task_id */ @@ -1490,7 +1490,7 @@ extern "C" { /** SOC_ETM_CH4_EVT_ID_REG register * Channel4 event id register */ -#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_BASE + 0x38) +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) /** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch4_evt_id */ @@ -1502,7 +1502,7 @@ extern "C" { /** SOC_ETM_CH4_TASK_ID_REG register * Channel4 task id register */ -#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_BASE + 0x3c) +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) /** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch4_task_id */ @@ -1514,7 +1514,7 @@ extern "C" { /** SOC_ETM_CH5_EVT_ID_REG register * Channel5 event id register */ -#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_BASE + 0x40) +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) /** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch5_evt_id */ @@ -1526,7 +1526,7 @@ extern "C" { /** SOC_ETM_CH5_TASK_ID_REG register * Channel5 task id register */ -#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_BASE + 0x44) +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) /** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch5_task_id */ @@ -1538,7 +1538,7 @@ extern "C" { /** SOC_ETM_CH6_EVT_ID_REG register * Channel6 event id register */ -#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_BASE + 0x48) +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) /** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch6_evt_id */ @@ -1550,7 +1550,7 @@ extern "C" { /** SOC_ETM_CH6_TASK_ID_REG register * Channel6 task id register */ -#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_BASE + 0x4c) +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) /** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch6_task_id */ @@ -1562,7 +1562,7 @@ extern "C" { /** SOC_ETM_CH7_EVT_ID_REG register * Channel7 event id register */ -#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_BASE + 0x50) +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) /** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch7_evt_id */ @@ -1574,7 +1574,7 @@ extern "C" { /** SOC_ETM_CH7_TASK_ID_REG register * Channel7 task id register */ -#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_BASE + 0x54) +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) /** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch7_task_id */ @@ -1586,7 +1586,7 @@ extern "C" { /** SOC_ETM_CH8_EVT_ID_REG register * Channel8 event id register */ -#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_BASE + 0x58) +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) /** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch8_evt_id */ @@ -1598,7 +1598,7 @@ extern "C" { /** SOC_ETM_CH8_TASK_ID_REG register * Channel8 task id register */ -#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_BASE + 0x5c) +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) /** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch8_task_id */ @@ -1610,7 +1610,7 @@ extern "C" { /** SOC_ETM_CH9_EVT_ID_REG register * Channel9 event id register */ -#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_BASE + 0x60) +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) /** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch9_evt_id */ @@ -1622,7 +1622,7 @@ extern "C" { /** SOC_ETM_CH9_TASK_ID_REG register * Channel9 task id register */ -#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_BASE + 0x64) +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) /** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch9_task_id */ @@ -1634,7 +1634,7 @@ extern "C" { /** SOC_ETM_CH10_EVT_ID_REG register * Channel10 event id register */ -#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_BASE + 0x68) +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) /** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch10_evt_id */ @@ -1646,7 +1646,7 @@ extern "C" { /** SOC_ETM_CH10_TASK_ID_REG register * Channel10 task id register */ -#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_BASE + 0x6c) +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) /** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch10_task_id */ @@ -1658,7 +1658,7 @@ extern "C" { /** SOC_ETM_CH11_EVT_ID_REG register * Channel11 event id register */ -#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_BASE + 0x70) +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) /** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch11_evt_id */ @@ -1670,7 +1670,7 @@ extern "C" { /** SOC_ETM_CH11_TASK_ID_REG register * Channel11 task id register */ -#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_BASE + 0x74) +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) /** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch11_task_id */ @@ -1682,7 +1682,7 @@ extern "C" { /** SOC_ETM_CH12_EVT_ID_REG register * Channel12 event id register */ -#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_BASE + 0x78) +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) /** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch12_evt_id */ @@ -1694,7 +1694,7 @@ extern "C" { /** SOC_ETM_CH12_TASK_ID_REG register * Channel12 task id register */ -#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_BASE + 0x7c) +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) /** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch12_task_id */ @@ -1706,7 +1706,7 @@ extern "C" { /** SOC_ETM_CH13_EVT_ID_REG register * Channel13 event id register */ -#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_BASE + 0x80) +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) /** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch13_evt_id */ @@ -1718,7 +1718,7 @@ extern "C" { /** SOC_ETM_CH13_TASK_ID_REG register * Channel13 task id register */ -#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_BASE + 0x84) +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) /** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch13_task_id */ @@ -1730,7 +1730,7 @@ extern "C" { /** SOC_ETM_CH14_EVT_ID_REG register * Channel14 event id register */ -#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_BASE + 0x88) +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) /** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch14_evt_id */ @@ -1742,7 +1742,7 @@ extern "C" { /** SOC_ETM_CH14_TASK_ID_REG register * Channel14 task id register */ -#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_BASE + 0x8c) +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) /** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch14_task_id */ @@ -1754,7 +1754,7 @@ extern "C" { /** SOC_ETM_CH15_EVT_ID_REG register * Channel15 event id register */ -#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_BASE + 0x90) +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) /** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch15_evt_id */ @@ -1766,7 +1766,7 @@ extern "C" { /** SOC_ETM_CH15_TASK_ID_REG register * Channel15 task id register */ -#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_BASE + 0x94) +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) /** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch15_task_id */ @@ -1778,7 +1778,7 @@ extern "C" { /** SOC_ETM_CH16_EVT_ID_REG register * Channel16 event id register */ -#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_BASE + 0x98) +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) /** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch16_evt_id */ @@ -1790,7 +1790,7 @@ extern "C" { /** SOC_ETM_CH16_TASK_ID_REG register * Channel16 task id register */ -#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_BASE + 0x9c) +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) /** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch16_task_id */ @@ -1802,7 +1802,7 @@ extern "C" { /** SOC_ETM_CH17_EVT_ID_REG register * Channel17 event id register */ -#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_BASE + 0xa0) +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) /** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch17_evt_id */ @@ -1814,7 +1814,7 @@ extern "C" { /** SOC_ETM_CH17_TASK_ID_REG register * Channel17 task id register */ -#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_BASE + 0xa4) +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) /** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch17_task_id */ @@ -1826,7 +1826,7 @@ extern "C" { /** SOC_ETM_CH18_EVT_ID_REG register * Channel18 event id register */ -#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_BASE + 0xa8) +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) /** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch18_evt_id */ @@ -1838,7 +1838,7 @@ extern "C" { /** SOC_ETM_CH18_TASK_ID_REG register * Channel18 task id register */ -#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_BASE + 0xac) +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) /** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch18_task_id */ @@ -1850,7 +1850,7 @@ extern "C" { /** SOC_ETM_CH19_EVT_ID_REG register * Channel19 event id register */ -#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_BASE + 0xb0) +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) /** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch19_evt_id */ @@ -1862,7 +1862,7 @@ extern "C" { /** SOC_ETM_CH19_TASK_ID_REG register * Channel19 task id register */ -#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_BASE + 0xb4) +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) /** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch19_task_id */ @@ -1874,7 +1874,7 @@ extern "C" { /** SOC_ETM_CH20_EVT_ID_REG register * Channel20 event id register */ -#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_BASE + 0xb8) +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) /** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch20_evt_id */ @@ -1886,7 +1886,7 @@ extern "C" { /** SOC_ETM_CH20_TASK_ID_REG register * Channel20 task id register */ -#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_BASE + 0xbc) +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) /** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch20_task_id */ @@ -1898,7 +1898,7 @@ extern "C" { /** SOC_ETM_CH21_EVT_ID_REG register * Channel21 event id register */ -#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_BASE + 0xc0) +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) /** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch21_evt_id */ @@ -1910,7 +1910,7 @@ extern "C" { /** SOC_ETM_CH21_TASK_ID_REG register * Channel21 task id register */ -#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_BASE + 0xc4) +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) /** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch21_task_id */ @@ -1922,7 +1922,7 @@ extern "C" { /** SOC_ETM_CH22_EVT_ID_REG register * Channel22 event id register */ -#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_BASE + 0xc8) +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) /** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch22_evt_id */ @@ -1934,7 +1934,7 @@ extern "C" { /** SOC_ETM_CH22_TASK_ID_REG register * Channel22 task id register */ -#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_BASE + 0xcc) +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) /** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch22_task_id */ @@ -1946,7 +1946,7 @@ extern "C" { /** SOC_ETM_CH23_EVT_ID_REG register * Channel23 event id register */ -#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_BASE + 0xd0) +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) /** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch23_evt_id */ @@ -1958,7 +1958,7 @@ extern "C" { /** SOC_ETM_CH23_TASK_ID_REG register * Channel23 task id register */ -#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_BASE + 0xd4) +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) /** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch23_task_id */ @@ -1970,7 +1970,7 @@ extern "C" { /** SOC_ETM_CH24_EVT_ID_REG register * Channel24 event id register */ -#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_BASE + 0xd8) +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) /** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch24_evt_id */ @@ -1982,7 +1982,7 @@ extern "C" { /** SOC_ETM_CH24_TASK_ID_REG register * Channel24 task id register */ -#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_BASE + 0xdc) +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) /** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch24_task_id */ @@ -1994,7 +1994,7 @@ extern "C" { /** SOC_ETM_CH25_EVT_ID_REG register * Channel25 event id register */ -#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_BASE + 0xe0) +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) /** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch25_evt_id */ @@ -2006,7 +2006,7 @@ extern "C" { /** SOC_ETM_CH25_TASK_ID_REG register * Channel25 task id register */ -#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_BASE + 0xe4) +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) /** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch25_task_id */ @@ -2018,7 +2018,7 @@ extern "C" { /** SOC_ETM_CH26_EVT_ID_REG register * Channel26 event id register */ -#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_BASE + 0xe8) +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) /** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch26_evt_id */ @@ -2030,7 +2030,7 @@ extern "C" { /** SOC_ETM_CH26_TASK_ID_REG register * Channel26 task id register */ -#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_BASE + 0xec) +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) /** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch26_task_id */ @@ -2042,7 +2042,7 @@ extern "C" { /** SOC_ETM_CH27_EVT_ID_REG register * Channel27 event id register */ -#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_BASE + 0xf0) +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) /** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch27_evt_id */ @@ -2054,7 +2054,7 @@ extern "C" { /** SOC_ETM_CH27_TASK_ID_REG register * Channel27 task id register */ -#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_BASE + 0xf4) +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) /** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch27_task_id */ @@ -2066,7 +2066,7 @@ extern "C" { /** SOC_ETM_CH28_EVT_ID_REG register * Channel28 event id register */ -#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_BASE + 0xf8) +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) /** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch28_evt_id */ @@ -2078,7 +2078,7 @@ extern "C" { /** SOC_ETM_CH28_TASK_ID_REG register * Channel28 task id register */ -#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_BASE + 0xfc) +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) /** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch28_task_id */ @@ -2090,7 +2090,7 @@ extern "C" { /** SOC_ETM_CH29_EVT_ID_REG register * Channel29 event id register */ -#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_BASE + 0x100) +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) /** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch29_evt_id */ @@ -2102,7 +2102,7 @@ extern "C" { /** SOC_ETM_CH29_TASK_ID_REG register * Channel29 task id register */ -#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_BASE + 0x104) +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) /** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch29_task_id */ @@ -2114,7 +2114,7 @@ extern "C" { /** SOC_ETM_CH30_EVT_ID_REG register * Channel30 event id register */ -#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_BASE + 0x108) +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) /** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch30_evt_id */ @@ -2126,7 +2126,7 @@ extern "C" { /** SOC_ETM_CH30_TASK_ID_REG register * Channel30 task id register */ -#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_BASE + 0x10c) +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) /** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch30_task_id */ @@ -2138,7 +2138,7 @@ extern "C" { /** SOC_ETM_CH31_EVT_ID_REG register * Channel31 event id register */ -#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_BASE + 0x110) +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) /** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch31_evt_id */ @@ -2150,7 +2150,7 @@ extern "C" { /** SOC_ETM_CH31_TASK_ID_REG register * Channel31 task id register */ -#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_BASE + 0x114) +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) /** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch31_task_id */ @@ -2162,7 +2162,7 @@ extern "C" { /** SOC_ETM_CH32_EVT_ID_REG register * Channel32 event id register */ -#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_BASE + 0x118) +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) /** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch32_evt_id */ @@ -2174,7 +2174,7 @@ extern "C" { /** SOC_ETM_CH32_TASK_ID_REG register * Channel32 task id register */ -#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_BASE + 0x11c) +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) /** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch32_task_id */ @@ -2186,7 +2186,7 @@ extern "C" { /** SOC_ETM_CH33_EVT_ID_REG register * Channel33 event id register */ -#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_BASE + 0x120) +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) /** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch33_evt_id */ @@ -2198,7 +2198,7 @@ extern "C" { /** SOC_ETM_CH33_TASK_ID_REG register * Channel33 task id register */ -#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_BASE + 0x124) +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) /** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch33_task_id */ @@ -2210,7 +2210,7 @@ extern "C" { /** SOC_ETM_CH34_EVT_ID_REG register * Channel34 event id register */ -#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_BASE + 0x128) +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) /** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch34_evt_id */ @@ -2222,7 +2222,7 @@ extern "C" { /** SOC_ETM_CH34_TASK_ID_REG register * Channel34 task id register */ -#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_BASE + 0x12c) +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) /** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch34_task_id */ @@ -2234,7 +2234,7 @@ extern "C" { /** SOC_ETM_CH35_EVT_ID_REG register * Channel35 event id register */ -#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_BASE + 0x130) +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) /** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch35_evt_id */ @@ -2246,7 +2246,7 @@ extern "C" { /** SOC_ETM_CH35_TASK_ID_REG register * Channel35 task id register */ -#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_BASE + 0x134) +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) /** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch35_task_id */ @@ -2258,7 +2258,7 @@ extern "C" { /** SOC_ETM_CH36_EVT_ID_REG register * Channel36 event id register */ -#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_BASE + 0x138) +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) /** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch36_evt_id */ @@ -2270,7 +2270,7 @@ extern "C" { /** SOC_ETM_CH36_TASK_ID_REG register * Channel36 task id register */ -#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_BASE + 0x13c) +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) /** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch36_task_id */ @@ -2282,7 +2282,7 @@ extern "C" { /** SOC_ETM_CH37_EVT_ID_REG register * Channel37 event id register */ -#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_BASE + 0x140) +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) /** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch37_evt_id */ @@ -2294,7 +2294,7 @@ extern "C" { /** SOC_ETM_CH37_TASK_ID_REG register * Channel37 task id register */ -#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_BASE + 0x144) +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) /** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch37_task_id */ @@ -2306,7 +2306,7 @@ extern "C" { /** SOC_ETM_CH38_EVT_ID_REG register * Channel38 event id register */ -#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_BASE + 0x148) +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) /** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch38_evt_id */ @@ -2318,7 +2318,7 @@ extern "C" { /** SOC_ETM_CH38_TASK_ID_REG register * Channel38 task id register */ -#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_BASE + 0x14c) +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) /** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch38_task_id */ @@ -2330,7 +2330,7 @@ extern "C" { /** SOC_ETM_CH39_EVT_ID_REG register * Channel39 event id register */ -#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_BASE + 0x150) +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) /** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch39_evt_id */ @@ -2342,7 +2342,7 @@ extern "C" { /** SOC_ETM_CH39_TASK_ID_REG register * Channel39 task id register */ -#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_BASE + 0x154) +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) /** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch39_task_id */ @@ -2354,7 +2354,7 @@ extern "C" { /** SOC_ETM_CH40_EVT_ID_REG register * Channel40 event id register */ -#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_BASE + 0x158) +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) /** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch40_evt_id */ @@ -2366,7 +2366,7 @@ extern "C" { /** SOC_ETM_CH40_TASK_ID_REG register * Channel40 task id register */ -#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_BASE + 0x15c) +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) /** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch40_task_id */ @@ -2378,7 +2378,7 @@ extern "C" { /** SOC_ETM_CH41_EVT_ID_REG register * Channel41 event id register */ -#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_BASE + 0x160) +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) /** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch41_evt_id */ @@ -2390,7 +2390,7 @@ extern "C" { /** SOC_ETM_CH41_TASK_ID_REG register * Channel41 task id register */ -#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_BASE + 0x164) +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) /** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch41_task_id */ @@ -2402,7 +2402,7 @@ extern "C" { /** SOC_ETM_CH42_EVT_ID_REG register * Channel42 event id register */ -#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_BASE + 0x168) +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) /** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch42_evt_id */ @@ -2414,7 +2414,7 @@ extern "C" { /** SOC_ETM_CH42_TASK_ID_REG register * Channel42 task id register */ -#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_BASE + 0x16c) +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) /** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch42_task_id */ @@ -2426,7 +2426,7 @@ extern "C" { /** SOC_ETM_CH43_EVT_ID_REG register * Channel43 event id register */ -#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_BASE + 0x170) +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) /** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch43_evt_id */ @@ -2438,7 +2438,7 @@ extern "C" { /** SOC_ETM_CH43_TASK_ID_REG register * Channel43 task id register */ -#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_BASE + 0x174) +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) /** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch43_task_id */ @@ -2450,7 +2450,7 @@ extern "C" { /** SOC_ETM_CH44_EVT_ID_REG register * Channel44 event id register */ -#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_BASE + 0x178) +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) /** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch44_evt_id */ @@ -2462,7 +2462,7 @@ extern "C" { /** SOC_ETM_CH44_TASK_ID_REG register * Channel44 task id register */ -#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_BASE + 0x17c) +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) /** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch44_task_id */ @@ -2474,7 +2474,7 @@ extern "C" { /** SOC_ETM_CH45_EVT_ID_REG register * Channel45 event id register */ -#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_BASE + 0x180) +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) /** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch45_evt_id */ @@ -2486,7 +2486,7 @@ extern "C" { /** SOC_ETM_CH45_TASK_ID_REG register * Channel45 task id register */ -#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_BASE + 0x184) +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) /** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch45_task_id */ @@ -2498,7 +2498,7 @@ extern "C" { /** SOC_ETM_CH46_EVT_ID_REG register * Channel46 event id register */ -#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_BASE + 0x188) +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) /** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch46_evt_id */ @@ -2510,7 +2510,7 @@ extern "C" { /** SOC_ETM_CH46_TASK_ID_REG register * Channel46 task id register */ -#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_BASE + 0x18c) +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) /** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch46_task_id */ @@ -2522,7 +2522,7 @@ extern "C" { /** SOC_ETM_CH47_EVT_ID_REG register * Channel47 event id register */ -#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_BASE + 0x190) +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) /** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch47_evt_id */ @@ -2534,7 +2534,7 @@ extern "C" { /** SOC_ETM_CH47_TASK_ID_REG register * Channel47 task id register */ -#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_BASE + 0x194) +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) /** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch47_task_id */ @@ -2546,7 +2546,7 @@ extern "C" { /** SOC_ETM_CH48_EVT_ID_REG register * Channel48 event id register */ -#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_BASE + 0x198) +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) /** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch48_evt_id */ @@ -2558,7 +2558,7 @@ extern "C" { /** SOC_ETM_CH48_TASK_ID_REG register * Channel48 task id register */ -#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_BASE + 0x19c) +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) /** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch48_task_id */ @@ -2570,7 +2570,7 @@ extern "C" { /** SOC_ETM_CH49_EVT_ID_REG register * Channel49 event id register */ -#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_BASE + 0x1a0) +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) /** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch49_evt_id */ @@ -2582,7 +2582,7 @@ extern "C" { /** SOC_ETM_CH49_TASK_ID_REG register * Channel49 task id register */ -#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_BASE + 0x1a4) +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) /** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch49_task_id */ @@ -2594,7 +2594,7 @@ extern "C" { /** SOC_ETM_EVT_ST0_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_BASE + 0x1a8) +#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GPIO_evt_ch0_rise_edge trigger status. * 0: Not triggered @@ -2887,7 +2887,7 @@ extern "C" { /** SOC_ETM_EVT_ST0_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_BASE + 0x1ac) +#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. * 0: Invalid, No effect @@ -3180,7 +3180,7 @@ extern "C" { /** SOC_ETM_EVT_ST1_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_BASE + 0x1b0) +#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_evt_duty_chng_end_ch6 trigger status. * 0: Not triggered @@ -3473,7 +3473,7 @@ extern "C" { /** SOC_ETM_EVT_ST1_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_BASE + 0x1b4) +#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status. * 0: Invalid, No effect @@ -3766,7 +3766,7 @@ extern "C" { /** SOC_ETM_EVT_ST2_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_BASE + 0x1b8) +#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) /** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM0_evt_op0_tea trigger status. * 0: Not triggered @@ -4059,7 +4059,7 @@ extern "C" { /** SOC_ETM_EVT_ST2_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_BASE + 0x1bc) +#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) /** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status. * 0: Invalid, No effect @@ -4352,7 +4352,7 @@ extern "C" { /** SOC_ETM_EVT_ST3_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_BASE + 0x1c0) +#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) /** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM1_evt_timer2_tez trigger status. * 0: Not triggered @@ -4645,7 +4645,7 @@ extern "C" { /** SOC_ETM_EVT_ST3_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_BASE + 0x1c4) +#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) /** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status. * 0: Invalid, No effect @@ -4938,7 +4938,7 @@ extern "C" { /** SOC_ETM_EVT_ST4_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_BASE + 0x1c8) +#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8) /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents ADC_evt_eq_above_thresh0 trigger status. * 0: Not triggered @@ -5231,7 +5231,7 @@ extern "C" { /** SOC_ETM_EVT_ST4_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_BASE + 0x1cc) +#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. * 0: Invalid, No effect @@ -5524,7 +5524,7 @@ extern "C" { /** SOC_ETM_EVT_ST5_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST5_REG (DR_REG_SOC_BASE + 0x1d0) +#define SOC_ETM_EVT_ST5_REG (DR_REG_SOC_ETM_BASE + 0x1d0) /** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GDMA_evt_in_suc_eof_ch1 trigger status. * 0: Not triggered @@ -5817,7 +5817,7 @@ extern "C" { /** SOC_ETM_EVT_ST5_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST5_CLR_REG (DR_REG_SOC_BASE + 0x1d4) +#define SOC_ETM_EVT_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) /** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status. * 0: Invalid, No effect @@ -6110,7 +6110,7 @@ extern "C" { /** SOC_ETM_EVT_ST6_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST6_REG (DR_REG_SOC_BASE + 0x1d8) +#define SOC_ETM_EVT_ST6_REG (DR_REG_SOC_ETM_BASE + 0x1d8) /** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH3_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GDMA_evt_out_fifo_empty_ch3 trigger status. * 0: Not triggered @@ -6277,7 +6277,7 @@ extern "C" { /** SOC_ETM_EVT_ST6_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST6_CLR_REG (DR_REG_SOC_BASE + 0x1dc) +#define SOC_ETM_EVT_ST6_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) /** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH3_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch3 trigger status. * 0: Invalid, No effect @@ -6444,7 +6444,7 @@ extern "C" { /** SOC_ETM_TASK_ST0_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_BASE + 0x1e0) +#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1e0) /** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GPIO_task_ch0_set trigger status. * 0: Not triggered @@ -6737,7 +6737,7 @@ extern "C" { /** SOC_ETM_TASK_ST0_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_BASE + 0x1e4) +#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) /** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GPIO_task_ch0_set trigger status. * 0: Invalid, No effect @@ -7030,7 +7030,7 @@ extern "C" { /** SOC_ETM_TASK_ST1_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_BASE + 0x1e8) +#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1e8) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_task_duty_scale_update_ch4 trigger status. * 0: Not triggered @@ -7323,7 +7323,7 @@ extern "C" { /** SOC_ETM_TASK_ST1_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_BASE + 0x1ec) +#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. * 0: Invalid, No effect @@ -7616,7 +7616,7 @@ extern "C" { /** SOC_ETM_TASK_ST2_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_BASE + 0x1f0) +#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1f0) /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_task_timer0_pause trigger status. * 0: Not triggered @@ -7909,7 +7909,7 @@ extern "C" { /** SOC_ETM_TASK_ST2_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_BASE + 0x1f4) +#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4) /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear LEDC_task_timer0_pause trigger status. * 0: Invalid, No effect @@ -8202,7 +8202,7 @@ extern "C" { /** SOC_ETM_TASK_ST3_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_BASE + 0x1f8) +#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1f8) /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents TG0_task_cnt_cap_timer0 trigger status. * 0: Not triggered @@ -8495,7 +8495,7 @@ extern "C" { /** SOC_ETM_TASK_ST3_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_BASE + 0x1fc) +#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1fc) /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. * 0: Invalid, No effect @@ -8788,7 +8788,7 @@ extern "C" { /** SOC_ETM_TASK_ST4_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_BASE + 0x200) +#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x200) /** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM1_task_cmpr1_b_up trigger status. * 0: Not triggered @@ -9081,7 +9081,7 @@ extern "C" { /** SOC_ETM_TASK_ST4_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_BASE + 0x204) +#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x204) /** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status. * 0: Invalid, No effect @@ -9374,7 +9374,7 @@ extern "C" { /** SOC_ETM_TASK_ST5_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST5_REG (DR_REG_SOC_BASE + 0x208) +#define SOC_ETM_TASK_ST5_REG (DR_REG_SOC_ETM_BASE + 0x208) /** SOC_ETM_I2S0_TASK_SYNC_CHECK_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents I2S0_task_sync_check trigger status. * 0: Not triggered @@ -9586,7 +9586,7 @@ extern "C" { /** SOC_ETM_TASK_ST5_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST5_CLR_REG (DR_REG_SOC_BASE + 0x20c) +#define SOC_ETM_TASK_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x20c) /** SOC_ETM_I2S0_TASK_SYNC_CHECK_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear I2S0_task_sync_check trigger status. * 0: Invalid, No effect @@ -9798,7 +9798,7 @@ extern "C" { /** SOC_ETM_CLK_EN_REG register * ETM clock enable register */ -#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_BASE + 0x210) +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x210) /** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; * Configures whether or not to open register clock gate. * 0: Open the clock gate only when application writes registers @@ -9812,7 +9812,7 @@ extern "C" { /** SOC_ETM_DATE_REG register * ETM date register */ -#define SOC_ETM_DATE_REG (DR_REG_SOC_BASE + 0x214) +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x214) /** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 37777745; * Configures the version. */ diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 05bc87b136..2e8bc781fd 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -19,7 +19,6 @@ #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6 #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 #define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 diff --git a/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h index 88ada789e7..228e289ac0 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 08601b2574..604ac9d078 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -22,7 +22,6 @@ #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 diff --git a/components/soc/esp32s2/register/soc/i2s_reg.h b/components/soc/esp32s2/register/soc/i2s_reg.h index b19e25a604..7f2f7d0721 100644 --- a/components/soc/esp32s2/register/soc/i2s_reg.h +++ b/components/soc/esp32s2/register/soc/i2s_reg.h @@ -1,16 +1,18 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ +#pragma once +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc/soc.h" + +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) + #define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) /* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ /*description: */ @@ -1378,7 +1380,3 @@ extern "C" { #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index b9468b90fb..0d26f1eba1 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -30,7 +30,6 @@ #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 diff --git a/components/soc/esp32s3/register/soc/i2s_reg.h b/components/soc/esp32s3/register/soc/i2s_reg.h index 1629384434..872469a066 100644 --- a/components/soc/esp32s3/register/soc/i2s_reg.h +++ b/components/soc/esp32s3/register/soc/i2s_reg.h @@ -1,17 +1,18 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ - +#pragma once #include "soc/soc.h" + #ifdef __cplusplus extern "C" { #endif +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) + #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xC) /* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/ @@ -1092,7 +1093,3 @@ when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/ #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2S_REG_H_ */