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esp32: App can boot on FPGA image

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Includes fix for detecting ESP32 ECO3 on FPGA
This commit is contained in:
Angus Gratton
2020-08-27 19:12:00 +10:00
parent bbbbd5cf0c
commit 1a626ef6ca
5 changed files with 19 additions and 5 deletions
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5
components/bootloader_support/src/bootloader_efuse_esp32.c
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@@ -27,6 +27,11 @@ uint8_t bootloader_common_get_chip_revision(void)
case 3: case 3:
chip_ver = 2; chip_ver = 2;
break; break;
#if CONFIG_IDF_ENV_FPGA
case 4: /* Empty efuses, but APB_CTRL_DATE_REG bit is set */
chip_ver = 3;
break;
#endif
case 7: case 7:
chip_ver = 3; chip_ver = 3;
break; break;

5
components/esp32/Kconfig
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@@ -40,10 +40,14 @@ menu "ESP32-specific"
choice ESP32_DEFAULT_CPU_FREQ_MHZ choice ESP32_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency" prompt "CPU frequency"
default ESP32_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA
default ESP32_DEFAULT_CPU_FREQ_160 default ESP32_DEFAULT_CPU_FREQ_160
help help
CPU frequency to be set on application startup. CPU frequency to be set on application startup.
config ESP32_DEFAULT_CPU_FREQ_40
bool "40 MHz"
depends on IDF_ENV_FPGA
config ESP32_DEFAULT_CPU_FREQ_80 config ESP32_DEFAULT_CPU_FREQ_80
bool "80 MHz" bool "80 MHz"
config ESP32_DEFAULT_CPU_FREQ_160 config ESP32_DEFAULT_CPU_FREQ_160
@@ -54,6 +58,7 @@ menu "ESP32-specific"
config ESP32_DEFAULT_CPU_FREQ_MHZ config ESP32_DEFAULT_CPU_FREQ_MHZ
int int
default 40 if ESP32_DEFAULT_CPU_FREQ_40
default 80 if ESP32_DEFAULT_CPU_FREQ_80 default 80 if ESP32_DEFAULT_CPU_FREQ_80
default 160 if ESP32_DEFAULT_CPU_FREQ_160 default 160 if ESP32_DEFAULT_CPU_FREQ_160
default 240 if ESP32_DEFAULT_CPU_FREQ_240 default 240 if ESP32_DEFAULT_CPU_FREQ_240

3
components/esp_hw_support/port/esp32/rtc_clk.c
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@@ -768,6 +768,9 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
uint32_t rtc_clk_apb_freq_get(void) uint32_t rtc_clk_apb_freq_get(void)
{ {
#if CONFIG_IDF_ENV_FPGA
return CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * MHZ;
#endif // CONFIG_IDF_ENV_FPGA
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12; uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
// round to the nearest MHz // round to the nearest MHz
freq_hz += MHZ / 2; freq_hz += MHZ / 2;

8
components/esp_hw_support/port/esp32/rtc_clk_init.c
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@@ -140,7 +140,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void) static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
{ {
#ifndef CONFIG_IDF_ENV_FPGA #if CONFIG_IDF_ENV_FPGA
return RTC_XTAL_FREQ_40M;
#endif // CONFIG_IDF_ENV_FPGA
/* Enable 8M/256 clock if needed */ /* Enable 8M/256 clock if needed */
const bool clk_8m_enabled = rtc_clk_8m_enabled(); const bool clk_8m_enabled = rtc_clk_8m_enabled();
const bool clk_8md256_enabled = rtc_clk_8md256_enabled(); const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
@@ -173,8 +175,4 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
} }
/* Restore 8M and 8md256 clocks to original state */ /* Restore 8M and 8md256 clocks to original state */
rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled); rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
#else // CONFIG_IDF_ENV_FPGA
return RTC_XTAL_FREQ_40M;
#endif // CONFIG_IDF_ENV_FPGA
} }

3
components/esp_system/fpga_overrides.c
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@@ -13,6 +13,9 @@
// limitations under the License. // limitations under the License.
#include "sdkconfig.h" #include "sdkconfig.h"
#include "soc/soc.h" #include "soc/soc.h"
#ifndef CONFIG_IDF_TARGET_ESP32
#include "soc/system_reg.h"
#endif // not CONFIG_IDF_TARGET_ESP32
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "esp_log.h" #include "esp_log.h"