feat(psram): add psram noinit segment support on S2/S3/P4/C5

Closes https://github.com/espressif/esp-idf/issues/14253

components/esp_common/test_apps/.build-test-rules.yml

@@ -3,6 +3,7 @@
 components/esp_common/test_apps/esp_common:
   disable:
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
-    - if: CONFIG_NAME == "psram" and IDF_TARGET in ["esp32c5"]
+    - if: CONFIG_NAME == "psram_noinit" and SOC_SPIRAM_SUPPORTED != 1
+    - if: CONFIG_NAME == "psram_noinit" and IDF_TARGET in ["esp32c61"]
       temporary: true
-      reason: esp32c5 is not supported yet # TODO: IDF-8689
+      reason: esp32c61 is not supported yet # TODO: IDF-9293

components/esp_common/test_apps/esp_common/main/CMakeLists.txt

@@ -1,4 +1,4 @@
 idf_component_register(SRCS "test_app_main.c" "test_attr.c"
                        INCLUDE_DIRS "."
-                       PRIV_REQUIRES unity esp_psram
+                       PRIV_REQUIRES unity esp_mm esp_psram
                        WHOLE_ARCHIVE)

components/esp_common/test_apps/esp_common/main/test_attr.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,10 +10,17 @@
 #include "esp_log.h"
 #include "soc/soc.h"
 #include "esp_system.h"
+#include "hal/cache_ll.h"
+#include "hal/cache_hal.h"
+#include "esp_cache.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp_private/esp_psram_extram.h"
 #endif
 
+#define ALIGN_UP(num, align)    (((num) + ((align) - 1)) & ~((align) - 1))
+
+static const char *TAG = "attr_test";
+
 extern int _rtc_noinit_start;
 extern int _rtc_noinit_end;
 extern int _rtc_data_start;
@@ -44,6 +51,7 @@ static EXT_RAM_NOINIT_ATTR uint32_t s_noinit_ext;
 
 static bool data_in_segment(void *ptr, int *seg_start, int *seg_end)
 {
+    ESP_LOGV(TAG, "ptr:%p seg_start:%p seg_end:%p", ptr, seg_start, seg_end);
     return ((intptr_t)ptr < (intptr_t)seg_end) && \
            ((intptr_t)ptr >= (intptr_t)seg_start);
 }
@@ -94,7 +102,13 @@ static void write_spiram_and_reset(void)
     }
     printf("Flushing cache\n");
     // Flush the cache out to SPIRAM before resetting.
+#if CONFIG_IDF_TARGET_ESP32
     esp_psram_extram_writeback_cache();
+#else
+    size_t psram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
+    uint32_t ext_noinit_size = sizeof(s_noinit_buffer);
+    TEST_ESP_OK(esp_cache_msync(&s_noinit_buffer, ALIGN_UP(ext_noinit_size, psram_alignment), ESP_CACHE_MSYNC_FLAG_DIR_C2M));
+#endif
 
     printf("Restarting\n");
     // Reset to test that noinit memory is left intact.

components/esp_common/test_apps/esp_common/pytest_esp_common.py

@@ -1,5 +1,7 @@
 # SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
+from typing import Any
+
 import pytest
 from pytest_embedded import Dut
 
@@ -19,6 +21,10 @@ def test_esp_common(dut: Dut) -> None:
 
 # psram noinit attr tests with psram enabled
 @pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
@@ -33,6 +39,10 @@ def test_esp_attr_psram_noinit(dut: Dut) -> None:
 
 # psram noinit memory tests with psram enabled
 @pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.generic
 @pytest.mark.supported_targets
 @pytest.mark.parametrize(
@@ -42,8 +52,8 @@ def test_esp_attr_psram_noinit(dut: Dut) -> None:
     ],
     indirect=True,
 )
-def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
-    dut.run_all_single_board_cases()
+def test_esp_attr_psram_noinit_multiple_stages(case_tester: Any) -> None:
+    case_tester.run_all_multi_stage_cases()
 
 
 # psram attr tests with psram enabled
@@ -51,6 +61,7 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',

components/esp_common/test_apps/esp_common/sdkconfig.ci.psram_noinit

@@ -1,6 +1,5 @@
 # For EXT_RAM_NOINIT_ATTR
 
-CONFIG_IDF_TARGET="esp32"
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y

components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4

@@ -3,4 +3,6 @@
 CONFIG_IDF_TARGET="esp32p4"
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_XIP_FROM_PSRAM=y
+CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
+CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y

components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2

@@ -3,5 +3,6 @@
 CONFIG_IDF_TARGET="esp32s2"
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
+CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_RODATA=y
 CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y

components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3

@@ -3,5 +3,6 @@
 CONFIG_IDF_TARGET="esp32s3"
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
+CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_RODATA=y
 CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y