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feat(adc): support ADC calibration on ESP32C61

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This commit is contained in:
gaoxu
2025-07-10 17:49:05 +08:00
committed by Gao Xu
parent 2e619615de
commit 1e76669a8b
10 changed files with 294 additions and 95 deletions
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112
components/efuse/esp32c61/esp_efuse_rtc_calib.c
View File

@@ -20,29 +20,121 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t cali_version = 0;
// TODO: [ESP32C61] IDF-9303
abort();
uint32_t blk_ver = efuse_hal_blk_version();
if ((blk_ver >= 1) && (blk_ver < 100)) {
cali_version = ESP_EFUSE_ADC_CALIB_VER1;
} else {
ESP_LOGW("eFuse", "calibration efuse version does not match, set default version to 0");
}
return cali_version;
}
uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
{
// TODO: [ESP32C61] IDF-9303
abort();
return 0;
/* Version validation should be guaranteed in the caller */
assert(atten >=0 && atten < 4);
assert(adc_unit == 0);
const esp_efuse_desc_t** init_code_efuse;
if (atten == 0) {
init_code_efuse = ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0;
} else if (atten == 1) {
init_code_efuse = ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1;
} else if (atten == 2) {
init_code_efuse = ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2;
} else {
init_code_efuse = ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3;
}
int init_code_size = esp_efuse_get_field_size(init_code_efuse);
assert(init_code_size == 10);
uint32_t init_code = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
return init_code + 1600; // version 1 logic
}
int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten)
{
// TODO: [ESP32C61] IDF-9303
abort();
return 0;
/* Version validation should be guaranteed in the caller */
assert(atten < 4);
assert(adc_channel < SOC_ADC_CHANNEL_NUM(adc_unit));
assert(adc_unit == 0);
const esp_efuse_desc_t** chan_diff_efuse = NULL;
switch (adc_channel) {
case 0:
chan_diff_efuse = ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF;
break;
case 1:
chan_diff_efuse = ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF;
break;
case 2:
chan_diff_efuse = ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF;
break;
case 3:
chan_diff_efuse = ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF;
break;
default:
assert(false);
break;
}
int chan_diff_size = esp_efuse_get_field_size(chan_diff_efuse);
assert(chan_diff_size == 4);
uint32_t chan_diff = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(chan_diff_efuse, &chan_diff, chan_diff_size));
return RTC_CALIB_GET_SIGNED_VAL(chan_diff, 3) * (4 - atten);
}
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
{
// TODO: [ESP32C61] IDF-9303
abort();
assert(adc_unit == 0);
const esp_efuse_desc_t** cal_vol_adc1_efuse[4] = {
ESP_EFUSE_ADC1_HI_DOUT_ATTEN0,
ESP_EFUSE_ADC1_HI_DOUT_ATTEN1,
ESP_EFUSE_ADC1_HI_DOUT_ATTEN2,
ESP_EFUSE_ADC1_HI_DOUT_ATTEN3,
};
const uint32_t input_vout_mv[1][4] = {
{600, 800, 1200, 2300}, // Calibration V1 coefficients
};
if ((version < ESP_EFUSE_ADC_CALIB_VER_MIN) ||
(version > ESP_EFUSE_ADC_CALIB_VER_MAX)) {
return ESP_ERR_INVALID_ARG;
}
if (atten >= 4 || atten < 0) {
return ESP_ERR_INVALID_ARG;
}
assert(cal_vol_adc1_efuse[atten][0]->bit_count == 10);
uint32_t cal_vol = 0;
esp_err_t ret = ESP_OK;
ret = esp_efuse_read_field_blob(cal_vol_adc1_efuse[atten], &cal_vol, cal_vol_adc1_efuse[atten][0]->bit_count);
if (ret != ESP_OK) {
return ret;
}
uint32_t chk_offset;
if (atten == 0) {
chk_offset = 2250;
} else if (atten == 1) {
chk_offset = 2250;
} else if (atten == 2) {
chk_offset = 2300;
} else {
chk_offset = 2300;
}
*out_digi = chk_offset + RTC_CALIB_GET_SIGNED_VAL(cal_vol, 9);
*out_vol_mv = input_vout_mv[VER2IDX(version)][atten];
return ESP_OK;
}

5
components/efuse/esp32c61/include/esp_efuse_rtc_calib.h
View File

@@ -11,13 +11,10 @@
extern "C" {
#endif
// TODO: [ESP32C61] IDF-9303, file inherit from verify code, pls check
//This is the ADC calibration value version burnt in efuse
#define ESP_EFUSE_ADC_CALIB_VER1 1
#define ESP_EFUSE_ADC_CALIB_VER2 2
#define ESP_EFUSE_ADC_CALIB_VER_MIN ESP_EFUSE_ADC_CALIB_VER1
#define ESP_EFUSE_ADC_CALIB_VER_MAX ESP_EFUSE_ADC_CALIB_VER2
#define ESP_EFUSE_ADC_CALIB_VER_MAX ESP_EFUSE_ADC_CALIB_VER1
#define VER2IDX(ver) ((ver) - 1) // Version number to index number of the array
/**
* @brief Get the RTC calibration efuse version

60
components/esp_adc/esp32c61/curve_fitting_coefficients.c Normal file
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@@ -0,0 +1,60 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <stdint.h>
#include "esp_efuse_rtc_calib.h"
#include "../curve_fitting_coefficients.h"
#define COEFF_VERSION_NUM 1 // Currently C5 has one versions of curve calibration schemes
#define COEFF_GROUP_NUM 4
#define TERM_MAX 3
/**
* @note Error Calculation
* Coefficients for calculating the reading voltage error.
* Four sets of coefficients for atten0 ~ atten3 respectively.
*
* For each item, first element is the Coefficient, second element is the Multiple. (Coefficient / Multiple) is the real coefficient.
*
* @note {0,0} stands for unused item
* @note In case of the overflow, these coefficients are recorded as Absolute Value
* @note For atten0 ~ 3, error = (K0 * X^0) + (K1 * X^1)
* @note Above formula is rewritten from the original documentation, please note that the coefficients are re-ordered.
*/
const static uint64_t adc1_error_coef_atten[COEFF_VERSION_NUM][COEFF_GROUP_NUM][TERM_MAX][2] = {
/* Coefficients of calibration version 1 */
{
{{8668885650149671, 1e16}, {15630376830615, 1e16}, {0, 1}}, //atten0
{{1090569589734153, 1e15}, {13859487941542, 1e16}, {0, 1}}, //atten1
{{14231790752153335, 1e16}, {122016745867, 1e14}, {0, 1}}, //atten2
{{13204544579940347, 1e16}, {11762579610906, 1e16}, {7639928529, 1e16}}, //atten3
},
};
/**
* Term sign ADC1
*/
const static int32_t adc1_error_sign[COEFF_VERSION_NUM][COEFF_GROUP_NUM][TERM_MAX] = {
/* Coefficient sign of calibration version 1 */
{
{-1, 1, 1}, //atten0
{-1, 1, 1}, //atten1
{-1, 1, 1}, //atten2
{-1, -1, 1}, //atten3
},
};
void curve_fitting_get_second_step_coeff(const adc_cali_curve_fitting_config_t *config, cali_chars_second_step_t *ctx)
{
uint32_t adc_calib_ver = esp_efuse_rtc_calib_get_ver();
assert((adc_calib_ver >= ESP_EFUSE_ADC_CALIB_VER_MIN) &&
(adc_calib_ver <= ESP_EFUSE_ADC_CALIB_VER_MAX));
ctx->term_num = 3;
ctx->coeff = adc1_error_coef_atten[VER2IDX(adc_calib_ver)][config->atten];
ctx->sign = adc1_error_sign[VER2IDX(adc_calib_ver)][config->atten];
}

3
components/esp_adc/esp32c61/include/adc_cali_schemes.h
View File

@@ -12,5 +12,4 @@
* @brief Supported calibration schemes
*/
// TODO: [ESP32C61] IDF-9303
// #define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED 1
#define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED 1

4
components/esp_adc/test_apps/adc/main/test_common_adc.h
View File

@@ -104,10 +104,10 @@ extern "C" {
#define ADC_TEST_HIGH_THRESH 200
#elif CONFIG_IDF_TARGET_ESP32C61
#define ADC_TEST_LOW_VAL 2140
#define ADC_TEST_LOW_VAL 0
#define ADC_TEST_LOW_THRESH 200
#define ADC_TEST_HIGH_VAL 4095
#define ADC_TEST_HIGH_VAL 3329
#define ADC_TEST_HIGH_VAL_DMA 4095
#define ADC_TEST_HIGH_THRESH 200

2
components/esp_hw_support/port/esp32c61/ocode_init.c
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@@ -14,8 +14,6 @@
#include "esp_private/regi2c_ctrl.h"
#include "esp_hw_log.h"
// TODO: IDF-9303
static const char *TAG = "ocode_init";
static void set_ocode_by_efuse(int ocode_scheme_ver)

41
components/hal/esp32c61/include/hal/adc_ll.h
View File

@@ -641,6 +641,47 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
/*---------------------------------------------------------------
Calibration
---------------------------------------------------------------*/
/* ADC calibration code. */
/**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET).
*/
__attribute__((always_inline))
static inline void adc_ll_calibration_init(adc_unit_t adc_n)
{
(void)adc_n;
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
}
/**
* Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration.
*
* @note Different ADC units and different attenuation options use different calibration data (initial data).
*
* @param adc_n ADC index number.
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage.
*/
static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gnd)
{
/* Enable/disable internal connect GND (for calibration). */
if (internal_gnd) {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
}
}
/**
* Resume register status after calibration.
*
* @param adc_n ADC index number.
*/
static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
}
/**
* Set the calibration result to ADC.
*

12
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -263,6 +263,18 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED
bool
default y
config SOC_ADC_TEMPERATURE_SHARE_INTR
bool
default y

142
components/soc/esp32c61/include/soc/regi2c_saradc.h
View File

@@ -15,97 +15,97 @@
* function in adc_ll.h.
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define I2C_SAR_ADC 0x69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0
#define I2C_SARADC_DTEST 0x7
#define I2C_SARADC_DTEST_MSB 1
#define I2C_SARADC_DTEST_LSB 0
#define I2C_SARADC_DTEST 0x7
#define I2C_SARADC_DTEST_MSB 0x1
#define I2C_SARADC_DTEST_LSB 0x0
#define I2C_SARADC_ENT_TSENS 0x7
#define I2C_SARADC_ENT_TSENS_MSB 2
#define I2C_SARADC_ENT_TSENS_LSB 2
#define I2C_SARADC_ENT_TSENS 0x7
#define I2C_SARADC_ENT_TSENS_MSB 0x2
#define I2C_SARADC_ENT_TSENS_LSB 0x2
#define I2C_SARADC_ENT_SAR 0x7
#define I2C_SARADC_ENT_SAR_MSB 3
#define I2C_SARADC_ENT_SAR_LSB 3
#define I2C_SARADC_ENT_SAR 0x7
#define I2C_SARADC_ENT_SAR_MSB 0x3
#define I2C_SARADC_ENT_SAR_LSB 0x3
#define I2C_SARADC1_ENCAL_REF 0x7
#define I2C_SARADC1_ENCAL_REF_MSB 4
#define I2C_SARADC1_ENCAL_REF_LSB 4
#define I2C_SARADC1_ENCAL_REF 0x7
#define I2C_SARADC1_ENCAL_REF_MSB 0x4
#define I2C_SARADC1_ENCAL_REF_LSB 0x4
#define I2C_SAR1_ENCAL_GND 0x7
#define I2C_SAR1_ENCAL_GND_MSB 5
#define I2C_SAR1_ENCAL_GND_LSB 5
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x5
#define I2C_SARADC2_ENCAL_REF 0x7
#define I2C_SARADC2_ENCAL_REF_MSB 6
#define I2C_SARADC2_ENCAL_REF_LSB 6
#define I2C_SARADC2_ENCAL_REF 0x7
#define I2C_SARADC2_ENCAL_REF_MSB 0x6
#define I2C_SARADC2_ENCAL_REF_LSB 0x6
#define I2C_SAR2_ENCAL_GND 0x7
#define I2C_SAR2_ENCAL_GND_MSB 7
#define I2C_SAR2_ENCAL_GND_LSB 7
#define I2C_SAR2_ENCAL_GND 0x7
#define I2C_SAR2_ENCAL_GND_MSB 0x7
#define I2C_SAR2_ENCAL_GND_LSB 0x7
#define POWER_GLITCH_XPD_VDET_PERIF 10
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0
#define POWER_GLITCH_XPD_VDET_PERIF 0x10
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0x0
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0x0
#define POWER_GLITCH_XPD_VDET_VDDPST 10
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1
#define POWER_GLITCH_XPD_VDET_VDDPST 0x10
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 0x1
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 0x1
#define POWER_GLITCH_XPD_VDET_PLLBB 10
#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 2
#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 2
#define POWER_GLITCH_XPD_VDET_PLLBB 0x10
#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 0x2
#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 0x2
#define POWER_GLITCH_XPD_VDET_PLL 10
#define POWER_GLITCH_XPD_VDET_PLL_MSB 3
#define POWER_GLITCH_XPD_VDET_PLL_LSB 3
#define POWER_GLITCH_XPD_VDET_PLL 0x10
#define POWER_GLITCH_XPD_VDET_PLL_MSB 0x3
#define POWER_GLITCH_XPD_VDET_PLL_LSB 0x3
#define POWER_GLITCH_DREF_VDET_PERIF 11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0
#define POWER_GLITCH_DREF_VDET_PERIF 0x11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 0x2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0x0
#define POWER_GLITCH_DREF_VDET_VDDPST 11
#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 6
#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 4
#define POWER_GLITCH_DREF_VDET_VDDPST 0x11
#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 0x6
#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 0x4
#define POWER_GLITCH_DREF_VDET_PLLBB 12
#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 2
#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0
#define POWER_GLITCH_DREF_VDET_PLLBB 0x12
#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 0x2
#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0x0
#define POWER_GLITCH_DREF_VDET_PLL 12
#define POWER_GLITCH_DREF_VDET_PLL_MSB 6
#define POWER_GLITCH_DREF_VDET_PLL_LSB 4
#define POWER_GLITCH_DREF_VDET_PLL 0x12
#define POWER_GLITCH_DREF_VDET_PLL_MSB 0x6
#define POWER_GLITCH_DREF_VDET_PLL_LSB 0x4

8
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -104,10 +104,10 @@
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
// /*!< Calibration */ // TODO: [ESP32C61] IDF-9303
// \#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
// \#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
// \#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Interrupt */
#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)