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https://github.com/espressif/esp-idf.git
synced 2025-08-05 21:54:33 +02:00
Waits for all previously fetched WSR and XSR instructions to be performed before interpreting the register fields of the next
instruction delete logs about livelock
This commit is contained in:
@@ -64,6 +64,7 @@ xt_highint4:
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addmi a0, a0, (1<<14)
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addmi a0, a0, (1<<14)
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addmi a0, a0, (1<<14)
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addmi a0, a0, (1<<14)
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wsr a0, INTENABLE
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wsr a0, INTENABLE
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rsync
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1:
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1:
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#endif
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#endif
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@@ -98,6 +99,7 @@ xt_highint4:
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movi a2, ~(1<<16)
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movi a2, ~(1<<16)
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and a0, a2, a0
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and a0, a2, a0
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wsr a0, INTENABLE
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wsr a0, INTENABLE
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rsync
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#endif
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#endif
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/* disable exception mode, window overflow */
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/* disable exception mode, window overflow */
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@@ -253,11 +253,6 @@ void IRAM_ATTR call_start_cpu0()
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fail initializing it properly. */
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fail initializing it properly. */
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heap_caps_init();
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heap_caps_init();
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for (int i = 0; i < 64; i++) {
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ets_printf(((i+1)%8) ? DRAM_STR("%08x ") : DRAM_STR("%08x\n"), *(((volatile uint32_t *)SOC_RTC_DATA_LOW) + i));
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*(((volatile uint32_t *)SOC_RTC_DATA_LOW) + i) = 0;
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}
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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start_cpu0();
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start_cpu0();
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}
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}
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@@ -206,7 +206,7 @@ xt_highint5:
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nop
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nop
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.endr
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.endr
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/* Disable Normally Mode */
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/* Enable Normally Mode */
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movi a2, ERI_ADDR(APB_ITCTRL)
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movi a2, ERI_ADDR(APB_ITCTRL)
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rer a0, a2
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rer a0, a2
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movi a2, ~0x1
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movi a2, ~0x1
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@@ -289,24 +289,6 @@ xt_highint5:
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.align 4
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.align 4
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.handle_livelock_int:
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.handle_livelock_int:
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movi a0, SOC_RTC_DATA_LOW
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movi a5, _l5_intr_livelock_sync
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l32i a5, a5, 0
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s32i a5, a0, 0
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memw
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movi a5, _l5_intr_livelock_sync
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l32i a5, a5, 4
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s32i a5, a0, 4
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memw
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movi a5, _l5_intr_livelock_app
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l32i a5, a5, 0
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s32i a5, a0, 8
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memw
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movi a5, _l5_intr_livelock_counter
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l32i a5, a5, 0
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s32i a5, a0, 12
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memw
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getcoreid a5
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getcoreid a5
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/* Save A2, A3, A4 so we can use those registers */
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/* Save A2, A3, A4 so we can use those registers */
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