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Add debug log for int enable

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This commit is contained in:
gengyuchao
2020-07-29 20:33:33 +08:00
committed by maojianxin
parent a0226f1793
commit 1f286c2ba9
2 changed files with 23 additions and 2 deletions
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15
components/bt/bt.c
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@@ -1450,6 +1450,8 @@ void IRAM_ATTR __attribute__((noinline)) r_assert(const char *condition, int par
#define BT_INT_STA_REG (0x3FF7100C) #define BT_INT_STA_REG (0x3FF7100C)
#define BLE_INT_STA_REG (0x3FF71210) #define BLE_INT_STA_REG (0x3FF71210)
int _int_enable_flag=0;
extern bool connection_is_alive(); extern bool connection_is_alive();
extern uint32_t real_bt_isr_count ; extern uint32_t real_bt_isr_count ;
extern uint32_t connection_LinkSuperTimeout; extern uint32_t connection_LinkSuperTimeout;
@@ -1477,7 +1479,7 @@ static bool check_bt_is_alive()
last_clk_ts = currect_clkint_ts; last_clk_ts = currect_clkint_ts;
return BT_IS_ALIVE; return BT_IS_ALIVE;
} }
void esp_crosscore_int_send_get_int(int core_id);
void esp_bt_check_need_restart() void esp_bt_check_need_restart()
{ {
if(connection_is_alive() && (check_bt_is_alive()==false)) if(connection_is_alive() && (check_bt_is_alive()==false))
@@ -1485,8 +1487,17 @@ void esp_bt_check_need_restart()
uint32_t intenable; uint32_t intenable;
asm volatile ("rsr %0, INTENABLE\n" :"=r"(intenable)); asm volatile ("rsr %0, INTENABLE\n" :"=r"(intenable));
ets_printf("!! Check BT is not alive. Abort !!"); ets_printf("!! Check BT is not alive. Abort !!");
RMT_DBG_LOG_ERROR("BT not alive,INT R:0x%x EN 0x%x",*((uint32_t*)BT_INT_STA_REG),intenable); RMT_DBG_LOG_ERROR("BT not alive,INT %d R:0x%x EN 0x%x",xPortGetCoreID(),*((uint32_t*)BT_INT_STA_REG),intenable);
RMT_DBG_LOG_ERROR("BLE INT R:0x%x",*((uint32_t*)BLE_INT_STA_REG)); RMT_DBG_LOG_ERROR("BLE INT R:0x%x",*((uint32_t*)BLE_INT_STA_REG));
if (xPortGetCoreID()!=CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE){
int times_out = 5;
esp_crosscore_int_send_get_int(CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE);
while(times_out-- > 0 && _int_enable_flag == 0 )
{
vTaskDelay(100/portTICK_PERIOD_MS);
}
RMT_DBG_LOG_ERROR("BT not alive,INT Core %d EN 0x%x",CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE,_int_enable_flag);
}
abort(); abort();
} }
} }

10
components/esp32/crosscore_int.c
View File

@@ -36,6 +36,7 @@
#define REASON_YIELD BIT(0) #define REASON_YIELD BIT(0)
#define REASON_FREQ_SWITCH BIT(1) #define REASON_FREQ_SWITCH BIT(1)
#define REASON_GET_INT BIT(2)
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED; static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[ portNUM_PROCESSORS ]; static volatile uint32_t reason[ portNUM_PROCESSORS ];
@@ -76,6 +77,10 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
* to allow DFS features without the extra latency of the ISR hook. * to allow DFS features without the extra latency of the ISR hook.
*/ */
} }
if(my_reason_val & REASON_GET_INT) {
extern int _int_enable_flag;
asm volatile ("rsr %0, INTENABLE\n" :"=r"(_int_enable_flag));
}
} }
//Initialize the crosscore interrupt on this core. Call this once //Initialize the crosscore interrupt on this core. Call this once
@@ -117,3 +122,8 @@ void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH); esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
} }
void IRAM_ATTR esp_crosscore_int_send_get_int(int core_id)
{
esp_crosscore_int_send(core_id, REASON_GET_INT);
}