diff --git a/components/esp_rom/include/esp32/rom/spi_flash.h b/components/esp_rom/include/esp32/rom/spi_flash.h
index b78a6130aa..f4b17ae5be 100644
--- a/components/esp_rom/include/esp32/rom/spi_flash.h
+++ b/components/esp_rom/include/esp32/rom/spi_flash.h
@@ -124,6 +124,7 @@ extern "C" {
 
 //Extra dummy for flash read
 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M   0
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M   0
 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M   1
 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M   2
 
diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c
index d7e96ec544..158c4feb51 100644
--- a/components/spi_flash/flash_ops.c
+++ b/components/spi_flash/flash_ops.c
@@ -450,6 +450,43 @@ out:
 }
 #endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL
 
+#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
+extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
+extern uint8_t g_rom_spiflash_dummy_len_plus[];
+void IRAM_ATTR flash_rom_init(void)
+{
+    uint32_t freqdiv = 0;
+    uint32_t dummy_bit = 0;
+
+#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
+    dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
+    dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
+    dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M;
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
+    dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
+#endif
+
+#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
+    freqdiv = 1;
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
+    freqdiv = 2;
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
+    freqdiv = 3;
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
+    freqdiv = 4;
+#endif
+
+    g_rom_spiflash_dummy_len_plus[1] = dummy_bit;
+    esp_rom_spiflash_config_clk(freqdiv, 1);
+}
+#else
+void IRAM_ATTR flash_rom_init(void)
+{
+    return;
+}
+#endif // !CONFIG_SPI_FLASH_USE_LEGACY_IMPL
 esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size)
 {
     CHECK_WRITE_ADDRESS(dest_addr, size);
@@ -498,6 +535,7 @@ esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src,
             }
 
             spi_flash_guard_start();
+            flash_rom_init();
             rc = esp_rom_spiflash_write_encrypted(row_addr, (uint32_t *)encrypt_buf, 32);
             spi_flash_guard_end();
             if (rc != ESP_ROM_SPIFLASH_RESULT_OK) {
diff --git a/tools/ci/config/target-test.yml b/tools/ci/config/target-test.yml
index d3504e01ed..86450ac21b 100644
--- a/tools/ci/config/target-test.yml
+++ b/tools/ci/config/target-test.yml
@@ -330,6 +330,14 @@ UT_020:
     - Example_SPI_Multi_device
     - psram
 
+UT_021:
+  extends: .unit_test_template
+  parallel: 2
+  tags:
+    - ESP32_IDF
+    - psram
+    - UT_T1_FlashEncryption
+
 UT_022:
   extends: .unit_test_template
   tags:
diff --git a/tools/unit-test-app/configs/flash_encryption_psram b/tools/unit-test-app/configs/flash_encryption_psram
new file mode 100644
index 0000000000..12ce59a17e
--- /dev/null
+++ b/tools/unit-test-app/configs/flash_encryption_psram
@@ -0,0 +1,14 @@
+# This config is for ESP32 only
+CONFIG_IDF_TARGET="esp32"
+TEST_COMPONENTS=spi_flash
+TEST_GROUPS=flash_encryption
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
+CONFIG_ESP32_SPIRAM_SUPPORT=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y