diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index 397d1b47d7..5089f2497e 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -12,7 +12,7 @@ #include "bootloader_mem.h" #include "esp_cpu.h" -#if CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 #include "soc/hp_apm_reg.h" #include "soc/lp_apm_reg.h" #include "soc/lp_apm0_reg.h" @@ -20,7 +20,7 @@ void bootloader_init_mem(void) { -#if CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // disable apm filter // TODO: IDF-5909 REG_WRITE(LP_APM_FUNC_CTRL_REG, 0); REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0); diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index b86929672d..bed539e6c0 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -47,7 +47,7 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "dma/async_memcpy_impl_cp_dma.c") endif() - if(CONFIG_SOC_GDMA_SUPPORTED OR CONFIG_SOC_CP_DMA_SUPPORTED) + if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED) list(APPEND srcs "dma/esp_async_memcpy.c") endif() diff --git a/components/esp_hw_support/dma/async_memcpy_impl_gdma.c b/components/esp_hw_support/dma/async_memcpy_impl_gdma.c index 831b466123..dd5d4a0f56 100644 --- a/components/esp_hw_support/dma/async_memcpy_impl_gdma.c +++ b/components/esp_hw_support/dma/async_memcpy_impl_gdma.c @@ -15,6 +15,9 @@ #include "esp_attr.h" #include "esp_err.h" #include "esp_async_memcpy_impl.h" +#if SOC_APM_SUPPORTED +#include "hal/apm_ll.h" +#endif IRAM_ATTR static bool async_memcpy_impl_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { @@ -71,6 +74,14 @@ esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl) gdma_apply_strategy(impl->tx_channel, &strategy_config); gdma_apply_strategy(impl->rx_channel, &strategy_config); +#if SOC_APM_SUPPORTED + // APM GDMA master for M2M should have the same offset of its GDMA trigger + ESP_STATIC_ASSERT((APM_LL_MASTER_GDMA_M2M - 16) == SOC_GDMA_TRIG_PERIPH_M2M0); + // APM strategy: trusted mode + // TODO: IDF-5354 GDMA for M2M usage only need read and write permissions, we should disable the execute permission by the APM controller + apm_ll_set_master_secure_mode(APM_LL_MASTER_GDMA_M2M, APM_LL_SECURE_MODE_TEE); +#endif // SOC_APM_SUPPORTED + gdma_rx_event_callbacks_t cbs = { .on_recv_eof = async_memcpy_impl_rx_eof_callback }; diff --git a/components/esp_hw_support/include/esp_private/gdma.h b/components/esp_hw_support/include/esp_private/gdma.h index 109c8f31df..f3cce1d820 100644 --- a/components/esp_hw_support/include/esp_private/gdma.h +++ b/components/esp_hw_support/include/esp_private/gdma.h @@ -32,7 +32,7 @@ typedef struct gdma_channel_t *gdma_channel_handle_t; */ typedef enum { GDMA_TRIG_PERIPH_M2M, /*!< GDMA trigger peripheral: M2M */ - GDMA_TRIG_PERIPH_UART, /*!< GDMA trigger peripheral: UART */ + GDMA_TRIG_PERIPH_UHCI, /*!< GDMA trigger peripheral: UHCI */ GDMA_TRIG_PERIPH_SPI, /*!< GDMA trigger peripheral: SPI */ GDMA_TRIG_PERIPH_I2S, /*!< GDMA trigger peripheral: I2S */ GDMA_TRIG_PERIPH_AES, /*!< GDMA trigger peripheral: AES */ @@ -126,13 +126,13 @@ typedef struct { */ typedef struct { gdma_trigger_peripheral_t periph; /*!< Target peripheral which will trigger DMA operations */ - int instance_id; /*!< Peripheral instance ID. Supported IDs are listed in `soc/gdma_channel.h`, e.g. SOC_GDMA_TRIG_PERIPH_UART0 */ + int instance_id; /*!< Peripheral instance ID. Supported IDs are listed in `soc/gdma_channel.h`, e.g. SOC_GDMA_TRIG_PERIPH_UHCI0 */ } gdma_trigger_t; /** * @brief Helper macro to initialize GDMA trigger * @note value of `peri` must be selected from `gdma_trigger_peripheral_t` enum. - * e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UART,0) + * e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S,0) * */ #define GDMA_MAKE_TRIGGER(peri, id) \ diff --git a/components/hal/esp32c6/include/hal/apm_ll.h b/components/hal/esp32c6/include/hal/apm_ll.h new file mode 100644 index 0000000000..555aa3d290 --- /dev/null +++ b/components/hal/esp32c6/include/hal/apm_ll.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "soc/tee_reg.h" + +#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief APM Master ID + */ +typedef enum { + APM_LL_MASTER_HPCORE = 0, + APM_LL_MASTER_LPCORE = 1, + APM_LL_MASTER_REGDMA = 2, + APM_LL_MASTER_SDIOSLV = 3, + APM_LL_MASTER_MODEM = 4, + APM_LL_MASTER_MEM_MONITOR = 5, + APM_LL_MASTER_TRACE = 6, + APM_LL_MASTER_GDMA_SPI2 = 16, + APM_LL_MASTER_GDMA_M2M = 17, // a dummy GDMA trigger, used by M2M copy + APM_LL_MASTER_GDMA_UHCI0 = 18, + APM_LL_MASTER_GDMA_I2S0 = 19, + APM_LL_MASTER_GDMA_AES = 22, + APM_LL_MASTER_GDMA_SHA = 23, + APM_LL_MASTER_GDMA_ADC = 24, + APM_LL_MASTER_GDMA_PARLIO = 25, +} apm_ll_master_id_t; + +/** + * @brief APM Secure Mode + */ +typedef enum { + APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ + APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */ + APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */ + APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */ +} apm_ll_secure_mode_t; + +/** + * @brief Set secure mode + * + * @param master_id APM master ID + * @param mode Secure mode + */ +static inline void apm_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t mode) +{ + REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), mode); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c6/include/hal/gdma_ll.h b/components/hal/esp32c6/include/hal/gdma_ll.h index 719c16f68f..254bfbdd15 100644 --- a/components/hal/esp32c6/include/hal/gdma_ll.h +++ b/components/hal/esp32c6/include/hal/gdma_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "soc/gdma_struct.h" #include "soc/gdma_reg.h" #include "soc/soc_etm_source.h" +#include "soc/gdma_channel.h" #ifdef __cplusplus extern "C" { @@ -89,8 +90,8 @@ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bo dev->channel[channel].in.in_conf0.mem_trans_en = enable; if (enable) { // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a dummy value - dev->channel[channel].in.in_peri_sel.peri_in_sel = 1; - dev->channel[channel].out.out_peri_sel.peri_out_sel = 1; + dev->channel[channel].in.in_peri_sel.peri_in_sel = SOC_GDMA_TRIG_PERIPH_M2M0; + dev->channel[channel].out.out_peri_sel.peri_out_sel = SOC_GDMA_TRIG_PERIPH_M2M0; } } diff --git a/components/hal/esp32h2/include/hal/apm_ll.h b/components/hal/esp32h2/include/hal/apm_ll.h new file mode 100644 index 0000000000..555aa3d290 --- /dev/null +++ b/components/hal/esp32h2/include/hal/apm_ll.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "soc/tee_reg.h" + +#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief APM Master ID + */ +typedef enum { + APM_LL_MASTER_HPCORE = 0, + APM_LL_MASTER_LPCORE = 1, + APM_LL_MASTER_REGDMA = 2, + APM_LL_MASTER_SDIOSLV = 3, + APM_LL_MASTER_MODEM = 4, + APM_LL_MASTER_MEM_MONITOR = 5, + APM_LL_MASTER_TRACE = 6, + APM_LL_MASTER_GDMA_SPI2 = 16, + APM_LL_MASTER_GDMA_M2M = 17, // a dummy GDMA trigger, used by M2M copy + APM_LL_MASTER_GDMA_UHCI0 = 18, + APM_LL_MASTER_GDMA_I2S0 = 19, + APM_LL_MASTER_GDMA_AES = 22, + APM_LL_MASTER_GDMA_SHA = 23, + APM_LL_MASTER_GDMA_ADC = 24, + APM_LL_MASTER_GDMA_PARLIO = 25, +} apm_ll_master_id_t; + +/** + * @brief APM Secure Mode + */ +typedef enum { + APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ + APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */ + APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */ + APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */ +} apm_ll_secure_mode_t; + +/** + * @brief Set secure mode + * + * @param master_id APM master ID + * @param mode Secure mode + */ +static inline void apm_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t mode) +{ + REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), mode); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/gdma_ll.h b/components/hal/esp32h2/include/hal/gdma_ll.h new file mode 100644 index 0000000000..254bfbdd15 --- /dev/null +++ b/components/hal/esp32h2/include/hal/gdma_ll.h @@ -0,0 +1,535 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include /* Required for NULL constant */ +#include +#include +#include "hal/gdma_types.h" +#include "soc/gdma_struct.h" +#include "soc/gdma_reg.h" +#include "soc/soc_etm_source.h" +#include "soc/gdma_channel.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) + +#define GDMA_LL_RX_EVENT_MASK (0x7F) +#define GDMA_LL_TX_EVENT_MASK (0x3F) + +#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5) +#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4) +#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6) +#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5) +#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3) +#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4) +#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2) +#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3) +#define GDMA_LL_EVENT_TX_EOF (1<<1) +#define GDMA_LL_EVENT_TX_DONE (1<<0) +#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) +#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) +#define GDMA_LL_EVENT_RX_DONE (1<<0) + +#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \ + }}}[group][chan][event] + +#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \ + (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \ + }, \ + { \ + [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \ + }}}[group][chan][event] + +#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \ + }}}[group][chan][task] + +#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \ + (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \ + }, \ + { \ + [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \ + }}}[group][chan][task] + +///////////////////////////////////// Common ///////////////////////////////////////// +/** + * @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default + */ +static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.mem_trans_en = enable; + if (enable) { + // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a dummy value + dev->channel[channel].in.in_peri_sel.peri_in_sel = SOC_GDMA_TRIG_PERIPH_M2M0; + dev->channel[channel].out.out_peri_sel.peri_out_sel = SOC_GDMA_TRIG_PERIPH_M2M0; + } +} + +/** + * @brief Enable DMA clock gating + */ +static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable) +{ + dev->misc_conf.clk_en = enable; +} + +///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Get DMA RX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +{ + return dev->in_intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; +} + +/** + * @brief Enable DMA RX channel interrupt + */ +static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->in_intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); + } else { + dev->in_intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); + } +} + +/** + * @brief Clear DMA RX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->in_intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); +} + +/** + * @brief Get DMA RX channel interrupt status register address + */ +static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->in_intr[channel].st); +} + +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf1.in_check_owner = enable; +} + +/** + * @brief Enable DMA RX channel burst reading data, disabled by default + */ +static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_data_burst_en = enable; +} + +/** + * @brief Enable DMA RX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.indscr_burst_en = enable; +} + +/** + * @brief Reset DMA RX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_conf0.in_rst = 1; + dev->channel[channel].in.in_conf0.in_rst = 0; +} + +/** + * @brief Check if DMA RX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x01; +} + +/** + * @brief Check if DMA RX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in RX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].in.infifo_status.infifo_cnt; +} + +/** + * @brief Pop data from DMA RX FIFO + */ +static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_pop.infifo_pop = 1; + return dev->channel[channel].in.in_pop.infifo_rdata; +} + +/** + * @brief Set the descriptor link base address for RX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].in.in_link.inlink_addr = addr; +} + +/** + * @brief Start dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_start = 1; +} + +/** + * @brief Stop dealing with RX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_stop = 1; +} + +/** + * @brief Restart a new inlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].in.in_link.inlink_restart = 1; +} + +/** + * @brief Enable DMA RX to return the address of current descriptor when receives error + */ +static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_link.inlink_auto_ret = enable; +} + +/** + * @brief Check if DMA RX FSM is in IDLE state + */ +static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_link.inlink_park; +} + +/** + * @brief Get RX success EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_suc_eof_des_addr.val; +} + +/** + * @brief Get RX error EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_err_eof_des_addr.val; +} + +/** + * @brief Get current RX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].in.in_dscr.val; +} + +/** + * @brief Set priority for DMA RX channel + */ +static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].in.in_pri.rx_pri = prio; +} + +/** + * @brief Connect DMA RX channel to a given peripheral + */ +static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) +{ + dev->channel[channel].in.in_peri_sel.peri_in_sel = periph_id; +} + +/** + * @brief Whether to enable the ETM subsystem for RX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].in.in_conf0.in_etm_en = enable; +} + +///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Get DMA TX channel interrupt status word + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) +{ + return dev->out_intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; +} + +/** + * @brief Enable DMA TX channel interrupt + */ +static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) +{ + if (enable) { + dev->out_intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK); + } else { + dev->out_intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK); + } +} + +/** + * @brief Clear DMA TX channel interrupt + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) +{ + dev->out_intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK); +} + +/** + * @brief Get DMA TX channel interrupt status register address + */ +static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) +{ + return (volatile void *)(&dev->out_intr[channel].st); +} + +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf1.out_check_owner = enable; +} + +/** + * @brief Enable DMA TX channel burst sending data, disabled by default + */ +static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_data_burst_en = enable; +} + +/** + * @brief Enable DMA TX channel burst reading descriptor link, disabled by default + */ +static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.outdscr_burst_en = enable; +} + +/** + * @brief Set TX channel EOF mode + */ +static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) +{ + dev->channel[channel].out.out_conf0.out_eof_mode = mode; +} + +/** + * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default + */ +static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_auto_wrback = enable; +} + +/** + * @brief Reset DMA TX channel FSM and FIFO pointer + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_conf0.out_rst = 1; + dev->channel[channel].out.out_conf0.out_rst = 0; +} + +/** + * @brief Check if DMA TX FIFO is full + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x01; +} + +/** + * @brief Check if DMA TX FIFO is empty + * @param fifo_level only supports level 1 + */ +static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.val & 0x02; +} + +/** + * @brief Get number of bytes in TX FIFO + * @param fifo_level only supports level 1 + */ +static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) +{ + return dev->channel[channel].out.outfifo_status.outfifo_cnt; +} + +/** + * @brief Push data into DMA TX FIFO + */ +static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) +{ + dev->channel[channel].out.out_push.outfifo_wdata = data; + dev->channel[channel].out.out_push.outfifo_push = 1; +} + +/** + * @brief Set the descriptor link base address for TX channel + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) +{ + dev->channel[channel].out.out_link.outlink_addr = addr; +} + +/** + * @brief Start dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_start = 1; +} + +/** + * @brief Stop dealing with TX descriptors + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_stop = 1; +} + +/** + * @brief Restart a new outlink right after the last descriptor + */ +__attribute__((always_inline)) +static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) +{ + dev->channel[channel].out.out_link.outlink_restart = 1; +} + +/** + * @brief Check if DMA TX FSM is in IDLE state + */ +static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_link.outlink_park; +} + +/** + * @brief Get TX EOF descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_eof_des_addr.val; +} + +/** + * @brief Get current TX descriptor's address + */ +__attribute__((always_inline)) +static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) +{ + return dev->channel[channel].out.out_dscr.val; +} + +/** + * @brief Set priority for DMA TX channel + */ +static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) +{ + dev->channel[channel].out.out_pri.tx_pri = prio; +} + +/** + * @brief Connect DMA TX channel to a given peripheral + */ +static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) +{ + dev->channel[channel].out.out_peri_sel.peri_out_sel = periph_id; +} + +/** + * @brief Whether to enable the ETM subsystem for TX channel + * + * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel. + */ +static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->channel[channel].out.out_conf0.out_etm_en = enable; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c2/include/soc/gdma_channel.h b/components/soc/esp32c2/include/soc/gdma_channel.h index 1c84a35249..d45217826b 100644 --- a/components/soc/esp32c2/include/soc/gdma_channel.h +++ b/components/soc/esp32c2/include/soc/gdma_channel.h @@ -9,6 +9,6 @@ // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7) #define SOC_GDMA_TRIG_PERIPH_ADC0 (8) diff --git a/components/soc/esp32c3/include/soc/gdma_channel.h b/components/soc/esp32c3/include/soc/gdma_channel.h index ca3f0f7951..5f0b818bd2 100644 --- a/components/soc/esp32c3/include/soc/gdma_channel.h +++ b/components/soc/esp32c3/include/soc/gdma_channel.h @@ -9,7 +9,7 @@ // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_AES0 (6) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7) diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index d1cbdd392d..92b931a8c3 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -127,6 +127,10 @@ config SOC_BOD_SUPPORTED bool default y +config SOC_APM_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y diff --git a/components/soc/esp32c6/include/soc/gdma_channel.h b/components/soc/esp32c6/include/soc/gdma_channel.h index 6ae11185f8..6025fcd94a 100644 --- a/components/soc/esp32c6/include/soc/gdma_channel.h +++ b/components/soc/esp32c6/include/soc/gdma_channel.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,9 +7,9 @@ #pragma once // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` -#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_M2M0 (1) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_AES0 (6) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7) diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index f3f54e108a..21e92fad43 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -60,6 +60,7 @@ #define SOC_FLASH_ENC_SUPPORTED 1 #define SOC_SECURE_BOOT_SUPPORTED 1 #define SOC_BOD_SUPPORTED 1 +#define SOC_APM_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 diff --git a/components/soc/esp32c6/include/soc/tee_reg.h b/components/soc/esp32c6/include/soc/tee_reg.h index fd340089ee..b2839c4c3a 100644 --- a/components/soc/esp32c6/include/soc/tee_reg.h +++ b/components/soc/esp32c6/include/soc/tee_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -446,10 +446,10 @@ extern "C" { /** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706; * reg_tee_date */ -#define TEE_DATE_REG 0x0FFFFFFFU -#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) -#define TEE_DATE_REG_V 0x0FFFFFFFU -#define TEE_DATE_REG_S 0 +#define TEE_DATE 0x0FFFFFFFU +#define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) +#define TEE_DATE_V 0x0FFFFFFFU +#define TEE_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 4f1a922874..ca1ab0dd4e 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -3,6 +3,14 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_GDMA_SUPPORTED + bool + default y + +config SOC_ASYNC_MEMCPY_SUPPORTED + bool + default y + config SOC_IEEE802154_BLE_ONLY bool default y @@ -31,6 +39,10 @@ config SOC_BOD_SUPPORTED bool default y +config SOC_APM_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_32M bool default y @@ -183,6 +195,10 @@ config SOC_GDMA_PAIRS_PER_GROUP int default 3 +config SOC_GDMA_SUPPORT_ETM + bool + default y + config SOC_GPIO_PORT int default 1 diff --git a/components/soc/esp32h2/include/soc/gdma_channel.h b/components/soc/esp32h2/include/soc/gdma_channel.h index de9e2dd659..6025fcd94a 100644 --- a/components/soc/esp32h2/include/soc/gdma_channel.h +++ b/components/soc/esp32h2/include/soc/gdma_channel.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,10 +7,11 @@ #pragma once // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` -#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_M2M0 (1) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_AES0 (6) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7) #define SOC_GDMA_TRIG_PERIPH_ADC0 (8) +#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9) diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 482a2a43ce..2641065101 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -27,14 +27,14 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ // #define SOC_ADC_SUPPORTED 1 // TODO: IDF-6214 // #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: IDF-6241 -// #define SOC_GDMA_SUPPORTED 1 // TODO: IDF-6222 +#define SOC_GDMA_SUPPORTED 1 +#define SOC_ASYNC_MEMCPY_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 // TODO: IDF-6221 // #define SOC_MCPWM_SUPPORTED 1 // TODO: IDF-6237 // #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-6217 // #define SOC_BT_SUPPORTED 1 // TODO: IDF-6416 // #define SOC_IEEE802154_SUPPORTED 1 // TODO: IDF-6577 #define SOC_IEEE802154_BLE_ONLY 1 -// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: IDF-6238 // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: IDF-6239 // #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: IDF-6229 // #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: IDF-6281 @@ -57,6 +57,7 @@ // #define SOC_FLASH_ENC_SUPPORTED 1 // TODO: IDF-6282 // #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: IDF-6281 #define SOC_BOD_SUPPORTED 1 +#define SOC_APM_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_32M 1 @@ -136,10 +137,10 @@ See TRM DS chapter for more details */ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) -// TODO: IDF-6222 (Copy from esp32c6, need check) /*-------------------------- GDMA CAPS -------------------------------------*/ #define SOC_GDMA_GROUPS (1U) // Number of GDMA groups #define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group +#define SOC_GDMA_SUPPORT_ETM (1) // Support ETM submodule /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C6 has 1 GPIO peripheral diff --git a/components/soc/esp32h2/include/soc/tee_reg.h b/components/soc/esp32h2/include/soc/tee_reg.h index fd340089ee..b2839c4c3a 100644 --- a/components/soc/esp32h2/include/soc/tee_reg.h +++ b/components/soc/esp32h2/include/soc/tee_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -446,10 +446,10 @@ extern "C" { /** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672706; * reg_tee_date */ -#define TEE_DATE_REG 0x0FFFFFFFU -#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) -#define TEE_DATE_REG_V 0x0FFFFFFFU -#define TEE_DATE_REG_S 0 +#define TEE_DATE 0x0FFFFFFFU +#define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) +#define TEE_DATE_V 0x0FFFFFFFU +#define TEE_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32h4/include/soc/gdma_channel.h b/components/soc/esp32h4/include/soc/gdma_channel.h index ca3f0f7951..5f0b818bd2 100644 --- a/components/soc/esp32h4/include/soc/gdma_channel.h +++ b/components/soc/esp32h4/include/soc/gdma_channel.h @@ -9,7 +9,7 @@ // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_AES0 (6) #define SOC_GDMA_TRIG_PERIPH_SHA0 (7) diff --git a/components/soc/esp32s3/include/soc/gdma_channel.h b/components/soc/esp32s3/include/soc/gdma_channel.h index 373cf6cabd..6178c1f1ab 100644 --- a/components/soc/esp32s3/include/soc/gdma_channel.h +++ b/components/soc/esp32s3/include/soc/gdma_channel.h @@ -10,7 +10,7 @@ #define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) #define SOC_GDMA_TRIG_PERIPH_SPI2 (0) #define SOC_GDMA_TRIG_PERIPH_SPI3 (1) -#define SOC_GDMA_TRIG_PERIPH_UART0 (2) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) #define SOC_GDMA_TRIG_PERIPH_I2S0 (3) #define SOC_GDMA_TRIG_PERIPH_I2S1 (4) #define SOC_GDMA_TRIG_PERIPH_LCD0 (5) diff --git a/examples/bluetooth/hci/controller_hci_uart_esp32c3_and_esp32s3/main/main.c b/examples/bluetooth/hci/controller_hci_uart_esp32c3_and_esp32s3/main/main.c index 0cacc7b4ca..8770990c8e 100644 --- a/examples/bluetooth/hci/controller_hci_uart_esp32c3_and_esp32s3/main/main.c +++ b/examples/bluetooth/hci/controller_hci_uart_esp32c3_and_esp32s3/main/main.c @@ -221,8 +221,8 @@ void uhci_uart_install(void) }; ESP_ERROR_CHECK(gdma_new_channel(&rx_channel_config, &s_rx_channel)); - gdma_connect(s_tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UART, 0)); - gdma_connect(s_rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UART, 0)); + gdma_connect(s_tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)); + gdma_connect(s_rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)); gdma_strategy_config_t strategy_config = { .auto_update_desc = false,