Merge branch 'test/rtc_8m_d256' into 'master'

rtc: fixed 8MD256 can't be used as RTC slow src on ESP32

See merge request espressif/esp-idf!17989

components/esp_hw_support/port/esp32/rtc_clk.c

@@ -249,8 +249,7 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
-        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
+        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         if (d256_en) {
             CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
         } else {

components/esp_hw_support/port/esp32c2/rtc_clk.c

@@ -39,7 +39,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {

components/esp_hw_support/port/esp32c3/rtc_clk.c

@@ -89,7 +89,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {

components/esp_hw_support/port/esp32s2/rtc_clk.c

@@ -96,7 +96,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {

components/esp_hw_support/port/esp32s3/rtc_clk.c

@@ -98,7 +98,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
         CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
-        /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {

components/esp_system/test_apps/rtc_8md256/CMakeLists.txt

@@ -0,0 +1,5 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(rtc_8md256)

components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt

@@ -0,0 +1,7 @@
+set(srcs "test_app_main.c"
+         "test_rtc_8md256.c")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       WHOLE_ARCHIVE)

components/esp_system/test_apps/rtc_8md256/main/test_app_main.c

@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "unity_test_utils.h"
+
+#define LEAKS (400)
+
+
+void setUp(void)
+{
+    unity_utils_record_free_mem();
+}
+
+void tearDown(void)
+{
+    unity_utils_evaluate_leaks_direct(LEAKS);
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}

components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "esp_sleep.h"
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "esp_log.h"
+#include "freertos/task.h"
+#include "driver/uart.h"
+#include "freertos/FreeRTOS.h"
+#include "soc/soc_caps.h"
+
+static const char TAG[] = "rtc_8m";
+
+static void test_deepsleep(bool force_rtc_periph)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+    if (force_rtc_periph) {
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+    }
+#else
+    (void)force_rtc_periph;
+#endif
+
+    ESP_LOGI(TAG, "Entering deep sleep");
+    esp_deep_sleep_start();
+}
+
+TEST_CASE("Can use 8MD256 as RTC clock source in deepsleep", "[pm]")
+{
+    test_deepsleep(false);
+}
+
+static void test_lightsleep(bool force_rtc_periph)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+    if (force_rtc_periph) {
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+    }
+#else
+    (void)force_rtc_periph;
+#endif
+
+    while (true) {
+        printf("Entering light sleep\n");
+        /* To make sure the complete line is printed before entering sleep mode,
+         * need to wait until UART TX FIFO is empty:
+         */
+        uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM);
+
+        /* Enter sleep mode */
+        esp_light_sleep_start();
+
+        /* Determine wake up reason */
+        const char* wakeup_reason;
+        switch (esp_sleep_get_wakeup_cause()) {
+            case ESP_SLEEP_WAKEUP_TIMER:
+                wakeup_reason = "timer";
+                break;
+            default:
+                wakeup_reason = "other";
+                break;
+        }
+        printf("Returned from light sleep, reason: %s\n", wakeup_reason);
+        vTaskDelay(1000/portTICK_PERIOD_MS);
+    }
+}
+
+TEST_CASE("Can use 8MD256 as RTC clock source in lightsleep", "[pm]")
+{
+    test_lightsleep(false);
+}
+
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+TEST_CASE("Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)", "[pm]")
+{
+    test_deepsleep(true);
+}
+
+TEST_CASE("Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)", "[pm]")
+{
+    test_lightsleep(true);
+}
+#endif

components/esp_system/test_apps/rtc_8md256/pytest_rtc_8md256.py

@@ -0,0 +1,55 @@
+# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import pytest
+from pytest_embedded import Dut
+
+
+def deepsleep_test(dut: Dut, case_name: str) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    reset_reason = 'DEEPSLEEP_RESET' if dut.target == 'esp32' else 'DSLEEP'
+    if dut.target == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'rst:.*\(%s\)' % reset_reason, timeout=40)
+    else:
+        dut.expect(r'rst:.*\(%s\)' % reset_reason, timeout=10)
+
+
+@pytest.mark.supported_targets
+@pytest.mark.generic
+def test_rtc_8md256_deepsleep(dut: Dut) -> None:
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep"')
+
+
+# Only targets with SOC_PM_SUPPORT_RTC_PERIPH_PD defined
+@pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.generic
+def test_rtc_8md256_deepsleep_force_rtcperiph(dut: Dut) -> None:
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)"')
+
+
+def lightsleep_test(dut: Dut, case_name: str) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    if dut.target == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=40)
+    else:
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=10)
+
+
+@pytest.mark.supported_targets
+@pytest.mark.generic
+def test_rtc_8md256_lightsleep(dut: Dut) -> None:
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep"')
+
+
+@pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.generic
+def test_rtc_8md256_lightsleep_force_rtcperiph(dut: Dut) -> None:
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)"')

components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults

@@ -0,0 +1,3 @@
+CONFIG_FREERTOS_HZ=1000
+CONFIG_ESP_TASK_WDT=n
+CONFIG_RTC_CLK_SRC_INT_8MD256=y

components/soc/esp32/include/soc/rtc.h

@@ -577,6 +577,9 @@ typedef struct rtc_sleep_config_s {
 #define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES    (1)
 #define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES       (1)
 
+#define RTC_CNTL_CK8M_WAIT_DEFAULT          20
+#define RTC_CK8M_ENABLE_WAIT_DEFAULT        5
+
 /**
  * @brief Prepare the chip to enter sleep mode
  *

components/soc/esp32/include/soc/rtc_cntl_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
@@ -341,7 +333,6 @@
 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
 #define RTC_CNTL_CK8M_WAIT_V  0xFF
 #define RTC_CNTL_CK8M_WAIT_S  6
-#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
 /*description: CPU stall wait cycles in fast_clk_rtc*/
 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F

components/soc/esp32c3/include/soc/rtc_cntl_reg.h

@@ -300,7 +300,6 @@ extern "C" {
 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
 #define RTC_CNTL_CK8M_WAIT_V  0xFF
 #define RTC_CNTL_CK8M_WAIT_S  6
-#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
 /*description: CPU stall wait cycles in fast_clk_rtc*/
 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F

components/soc/esp32h2/include/rev1/soc/rtc_cntl_reg.h

@@ -312,7 +312,6 @@ extern "C" {
 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
 #define RTC_CNTL_CK8M_WAIT_V  0xFF
 #define RTC_CNTL_CK8M_WAIT_S  6
-#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
 /*description: CPU stall wait cycles in fast_clk_rtc*/
 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F

tools/ci/check_copyright_ignore.txt

@@ -1223,7 +1223,6 @@ components/soc/esp32/include/soc/ledc_struct.h
 components/soc/esp32/include/soc/nrx_reg.h
 components/soc/esp32/include/soc/pid.h
 components/soc/esp32/include/soc/reset_reasons.h
-components/soc/esp32/include/soc/rtc_cntl_reg.h
 components/soc/esp32/include/soc/rtc_cntl_struct.h
 components/soc/esp32/include/soc/rtc_i2c_reg.h
 components/soc/esp32/include/soc/rtc_io_channel.h