diff --git a/components/hal/cache_hal.c b/components/hal/cache_hal.c
index 608fff08ef..db7db4b573 100644
--- a/components/hal/cache_hal.c
+++ b/components/hal/cache_hal.c
@@ -12,6 +12,7 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_types.h"
 #include "hal/cache_ll.h"
+#include "hal/mmu_ll.h"
 #include "soc/soc_caps.h"
 
 #if CONFIG_IDF_TARGET_ESP32S2
@@ -112,3 +113,10 @@ void cache_hal_enable(cache_type_t type)
     }
 #endif
 }
+
+void cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)
+{
+    //Now only esp32 has 2 MMUs, this file doesn't build on esp32
+    HAL_ASSERT(mmu_ll_check_valid_ext_vaddr_region(0, vaddr, size));
+    Cache_Invalidate_Addr(vaddr, size);
+}
diff --git a/components/hal/include/hal/cache_hal.h b/components/hal/include/hal/cache_hal.h
index a8f5c52238..c147aaf868 100644
--- a/components/hal/include/hal/cache_hal.h
+++ b/components/hal/include/hal/cache_hal.h
@@ -36,6 +36,14 @@ void cache_hal_disable(cache_type_t type);
  */
 void cache_hal_enable(cache_type_t type);
 
+/**
+ * Invalidate a Cache item for either ICache or DCache.
+ *
+ * @param vaddr  Start address of the region to be invalidated
+ * @param size   Size of the region to be invalidated
+ */
+void cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size);
+
 #ifdef __cplusplus
 }
 #endif