Merge branch 'feature/fpga_bootloader' into 'master'

Boot ESP32 & ESP32-S2 apps on FPGA

See merge request espressif/esp-idf!8270

components/bootloader/subproject/main/ld/esp32/bootloader.ld

@@ -43,6 +43,7 @@ SECTIONS
     *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random)
     *libbootloader_support.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)

components/bootloader/subproject/main/ld/esp32s2/bootloader.ld

@@ -30,6 +30,7 @@ SECTIONS
     *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random)
     *libbootloader_support.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)

components/bootloader/subproject/main/ld/esp32s3/bootloader.ld

@@ -31,6 +31,7 @@ SECTIONS
     *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
     *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random)
     *libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
     *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)

components/bootloader_support/src/bootloader_common_loader.c

@@ -67,6 +67,8 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
         ESP_LOGE(TAG, "mismatch chip ID, expected %d, found %d", chip_id, img_hdr->chip_id);
         err = ESP_FAIL;
     }
+
+#ifndef CONFIG_IDF_ENV_FPGA
     uint8_t revision = bootloader_common_get_chip_revision();
     if (revision < img_hdr->min_chip_rev) {
         /* To fix this error, please update mininum supported chip revision from configuration,
@@ -78,6 +80,8 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
         ESP_LOGI(TAG, "chip revision: %d, min. %s chip revision: %d", revision, type == ESP_IMAGE_BOOTLOADER ? "bootloader" : "application", img_hdr->min_chip_rev);
 #endif
     }
+#endif // CONFIG_IDF_ENV_FPGA
+
     return err;
 }
 

components/bootloader_support/src/bootloader_efuse_esp32.c

@@ -27,6 +27,11 @@ uint8_t bootloader_common_get_chip_revision(void)
     case 3:
         chip_ver = 2;
         break;
+#if CONFIG_IDF_ENV_FPGA
+    case 4: /* Empty efuses, but APB_CTRL_DATE_REG bit is set */
+        chip_ver = 3;
+        break;
+#endif
     case 7:
         chip_ver = 3;
         break;

components/bootloader_support/src/bootloader_random.c

@@ -46,4 +46,26 @@
     }
 }
 
+#ifndef CONFIG_IDF_ENV_FPGA
+
+#else // CONFIG_IDF_ENV_FPGA
+#include "esp_log.h"
+
+static void s_non_functional(const char *func)
+{
+    ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func);
+}
+
+void bootloader_random_enable()
+{
+    s_non_functional(__func__);
+}
+
+void bootloader_random_disable()
+{
+    s_non_functional(__func__);
+}
+
+#endif // CONFIG_IDF_ENV_FPGA
+
 #endif // BOOTLOADER_BUILD

components/esp32/Kconfig

@@ -40,10 +40,14 @@ menu "ESP32-specific"
 
     choice ESP32_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
+        default ESP32_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA
         default ESP32_DEFAULT_CPU_FREQ_160
         help
             CPU frequency to be set on application startup.
 
+        config ESP32_DEFAULT_CPU_FREQ_40
+            bool "40 MHz"
+            depends on IDF_ENV_FPGA
         config ESP32_DEFAULT_CPU_FREQ_80
             bool "80 MHz"
         config ESP32_DEFAULT_CPU_FREQ_160
@@ -54,6 +58,7 @@ menu "ESP32-specific"
 
     config ESP32_DEFAULT_CPU_FREQ_MHZ
         int
+        default 40 if ESP32_DEFAULT_CPU_FREQ_40
         default 80 if ESP32_DEFAULT_CPU_FREQ_80
         default 160 if ESP32_DEFAULT_CPU_FREQ_160
         default 240 if ESP32_DEFAULT_CPU_FREQ_240
@@ -527,6 +532,7 @@ menu "ESP32-specific"
 
     config ESP32_BROWNOUT_DET
         bool "Hardware brownout detect & reset"
+        depends on !IDF_ENV_FPGA
         default y
         help
             The ESP32 has a built-in brownout detector which can detect if the voltage is lower than

components/esp32c3/Kconfig

@@ -66,6 +66,7 @@ menu "ESP32C3-Specific"
 
     config ESP32C3_BROWNOUT_DET
         bool "Hardware brownout detect & reset"
+        depends on !IDF_ENV_FPGA
         default y
         help
             The ESP32-C3 has a built-in brownout detector which can detect if the voltage is lower than

components/esp32s2/Kconfig

@@ -266,6 +266,7 @@ menu "ESP32S2-specific"
 
     config ESP32S2_BROWNOUT_DET
         bool "Hardware brownout detect & reset"
+        depends on !IDF_ENV_FPGA
         default y
         help
             The ESP32-S2 has a built-in brownout detector which can detect if the voltage is lower than

components/esp32s3/Kconfig

@@ -331,6 +331,7 @@ menu "ESP32S3-Specific"
 
     config ESP32S3_BROWNOUT_DET
         bool "Hardware brownout detect & reset"
+        depends on !IDF_ENV_FPGA
         default y
         help
             The ESP32-S3 has a built-in brownout detector which can detect if the voltage is lower than

components/esp_hw_support/port/esp32/rtc_clk.c

@@ -768,6 +768,9 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
 
 uint32_t rtc_clk_apb_freq_get(void)
 {
+#if CONFIG_IDF_ENV_FPGA
+    return CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * MHZ;
+#endif // CONFIG_IDF_ENV_FPGA
     uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
     // round to the nearest MHz
     freq_hz += MHZ / 2;

components/esp_hw_support/port/esp32/rtc_clk_init.c

@@ -140,6 +140,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
 {
+#if CONFIG_IDF_ENV_FPGA
+    return RTC_XTAL_FREQ_40M;
+#endif // CONFIG_IDF_ENV_FPGA
     /* Enable 8M/256 clock if needed */
     const bool clk_8m_enabled = rtc_clk_8m_enabled();
     const bool clk_8md256_enabled = rtc_clk_8md256_enabled();

components/esp_hw_support/port/esp32s2/rtc_clk.c

@@ -305,7 +305,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* ou
     uint32_t divider;
     uint32_t real_freq_mhz;
 
-    uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get();
+    uint32_t xtal_freq = RTC_XTAL_FREQ;
     if (freq_mhz <= xtal_freq) {
         divider = xtal_freq / freq_mhz;
         real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
@@ -346,10 +346,9 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* ou
 
 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
 {
-    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
     uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL);
     if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) {
-        rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
+        rtc_clk_cpu_freq_to_xtal(RTC_XTAL_FREQ, 1);
     }
     if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && config->source_freq_mhz != s_cur_pll_freq) {
         rtc_clk_bbpll_disable();
@@ -360,7 +359,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
         }
     } else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
         rtc_clk_bbpll_enable();
-        rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
+        rtc_clk_bbpll_configure(RTC_XTAL_FREQ, config->source_freq_mhz);
         rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
     } else if (config->source == RTC_CPU_FREQ_SRC_8M) {
         rtc_clk_cpu_freq_to_8m();
@@ -378,7 +377,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
         case DPORT_SOC_CLK_SEL_XTAL: {
             source = RTC_CPU_FREQ_SRC_XTAL;
             div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1;
-            source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
+            source_freq_mhz = RTC_XTAL_FREQ;
             freq_mhz = source_freq_mhz / div;
         }
         break;
@@ -437,10 +436,8 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
 
 void rtc_clk_cpu_freq_set_xtal(void)
 {
-    int freq_mhz = (int) rtc_clk_xtal_freq_get();
-
-    rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
     /* BBPLL is kept enabled */
+    rtc_clk_cpu_freq_to_xtal(RTC_XTAL_FREQ, 1);
 }
 
 /**
@@ -475,17 +472,8 @@ static void rtc_clk_cpu_freq_to_8m(void)
 
 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
-    uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
+    // Note, inside esp32s2-only code it's better to use RTC_XTAL_FREQ constant
-    if (!clk_val_is_valid(xtal_freq_reg)) {
+    return RTC_XTAL_FREQ;
-        SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
-        return RTC_XTAL_FREQ_40M;
-    }
-    return reg_val_to_clk_val(xtal_freq_reg);
-}
-
-void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
-{
-    WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
 }
 
 void rtc_clk_apb_freq_update(uint32_t apb_freq)

components/esp_hw_support/port/esp32s2/rtc_clk_init.c

@@ -58,7 +58,6 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
     esp_rom_uart_tx_wait_idle(0);
-    rtc_clk_xtal_freq_update(xtal_freq);
     rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
     /* Set CPU frequency */

components/esp_hw_support/port/esp32s2/rtc_init.c

@@ -26,7 +26,8 @@
 #include "soc_log.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
-static const char *TAG = "rtc_init";
+
+__attribute__((unused)) static const char *TAG = "rtc_init";
 
 static void set_ocode_by_efuse(int calib_version);
 static void calibrate_ocode(void);
@@ -152,6 +153,8 @@ void rtc_init(rtc_config_t cfg)
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
     }
+
+#if !CONFIG_IDF_ENV_FPGA
     if (cfg.cali_ocode) {
         uint32_t rtc_calib_version = 0;
         esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32);
@@ -161,6 +164,7 @@ void rtc_init(rtc_config_t cfg)
             calibrate_ocode();
         }
     }
+#endif // !CONFIG_IDF_ENV_FPGA
 
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);

components/esp_hw_support/port/esp32s3/rtc_sleep.c

@@ -35,6 +35,7 @@
  */
 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
 {
+#if !CONFIG_IDF_ENV_FPGA
     REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
     REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
     REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
@@ -47,6 +48,7 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
     REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
     REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
     REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
+#endif
     if (cfg.sram_fpu) {
         REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
     } else {

components/esp_system/fpga_overrides.c

@@ -13,6 +13,9 @@
 // limitations under the License.
 #include "sdkconfig.h"
 #include "soc/soc.h"
+#ifndef CONFIG_IDF_TARGET_ESP32
+#include "soc/system_reg.h"
+#endif // not CONFIG_IDF_TARGET_ESP32
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "esp_log.h"

components/esp_system/port/cpu_start.c

@@ -484,6 +484,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
     intr_matrix_clear();
 
+#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
 #ifdef CONFIG_ESP_CONSOLE_UART
     uint32_t clock_hz = rtc_clk_apb_freq_get();
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@@ -492,6 +493,7 @@ void IRAM_ATTR call_start_cpu0(void)
     esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
+#endif
 
 #if SOC_RTCIO_HOLD_SUPPORTED
     rtcio_hal_unhold_all();

components/esp_system/port/soc/esp32s2/clk.c

@@ -83,8 +83,6 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
     }
     rtc_init(cfg);
 
-    assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
-
     rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
@@ -145,6 +143,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
 
 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
 {
+#ifdef CONFIG_IDF_ENV_FPGA
+    return;
+#endif
     rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
     uint32_t cal_val = 0;
     /* number of times to repeat 32k XTAL calibration
@@ -283,11 +284,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                         DPORT_SPI3_DMA_CLK_EN;
     common_perip_clk1 = 0;
 
+#ifndef CONFIG_IDF_ENV_FPGA
     /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
      * the current is not reduced when disable I2S clock.
      */
     REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
     REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
+#endif // CONFIG_IDF_ENV_FPGA
 
     /* Disable some peripheral clocks. */
     DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);

components/soc/esp32s2/include/soc/rtc.h

@@ -143,6 +143,13 @@ typedef enum {
     RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
 } rtc_xtal_freq_t;
 
+/** @brief Fixed crystal frequency for this SoC
+
+    On an SoC where only one crystal frequency is supported,
+    using this macro is an alternative to calling rtc_clk_xtal_freq_get()
+ */
+#define RTC_XTAL_FREQ RTC_XTAL_FREQ_40M
+
 /**
  * @brief CPU frequency values
  */
@@ -315,23 +322,16 @@ void rtc_clk_init(rtc_clk_config_t cfg);
 /**
  * @brief Get main XTAL frequency
  *
- * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * Result is a constant as XTAL frequency is fixed.
- * rtc_clk_init function
  *
- * @return XTAL frequency, one of rtc_xtal_freq_t
+ * @note Function is included for ESP32 compatible code only. Code which only
+ * needs to support this SoC can use the macro RTC_XTAL_FREQ for this SoC's
+ * fixed crystal value.
+ *
+ * @return XTAL frequency in MHz, RTC_XTAL_FREQ_40M
  */
 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
 
-/**
- * @brief Update XTAL frequency
- *
- * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
- * after startup.
- *
- * @param xtal_freq New frequency value
- */
-void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
-
 /**
  * @brief Enable or disable 32 kHz XTAL oscillator
  * @param en  true to enable, false to disable