From 205cd469e90d6b054b2fc233d410381f32e794a1 Mon Sep 17 00:00:00 2001 From: Shu Chen Date: Thu, 10 Jun 2021 10:28:23 +0800 Subject: [PATCH] esp32h2: update driver/hal/soc components to support esp32h2 --- components/driver/CMakeLists.txt | 9 + components/driver/esp32h2/adc.c | 8 +- components/driver/esp32h2/rtc_tempsensor.c | 2 +- .../driver/include/driver/adc2_wifi_private.h | 2 +- components/driver/include/driver/adc_common.h | 20 +- components/driver/include/driver/gpio.h | 2 + components/driver/periph_ctrl.c | 2 + components/driver/uart.c | 2 + components/esp32h2/CMakeLists.txt | 28 +- components/esp32h2/Kconfig | 137 +- components/esp32h2/Makefile.projbuild | 2 +- components/esp32h2/esp_ds.c | 10 +- components/esp32h2/esp_hmac.c | 8 +- components/esp32h2/include/esp32h2/memprot.h | 2 +- components/esp32h2/include/esp32h2/rtc.h | 2 +- components/esp32h2/include/esp_ds.h | 8 +- components/esp32h2/ld/esp32h2.ld | 12 +- components/esp32h2/ld/esp32h2.project.ld.in | 4 +- components/esp32h2/memprot.c | 4 +- components/esp32h2/test/CMakeLists.txt | 2 +- components/esp32h2/test/test_ds.c | 14 +- components/esp32h2/test/test_sha.c | 2 +- components/hal/CMakeLists.txt | 13 + components/hal/adc_hal.c | 10 +- components/hal/esp32h2/adc_hal.c | 8 +- components/hal/esp32h2/include/hal/adc_ll.h | 49 +- .../hal/esp32h2/include/hal/clk_gate_ll.h | 51 - components/hal/esp32h2/include/hal/cpu_ll.h | 2 +- components/hal/esp32h2/include/hal/gpio_ll.h | 4 +- .../hal/esp32h2/include/hal/gpspi_flash_ll.h | 2 +- components/hal/esp32h2/include/hal/hmac_hal.h | 6 +- components/hal/esp32h2/include/hal/hmac_ll.h | 2 +- components/hal/esp32h2/include/hal/i2s_ll.h | 134 +- .../hal/esp32h2/include/hal/memprot_ll.h | 2 +- components/hal/esp32h2/include/hal/mpu_ll.h | 2 +- .../hal/esp32h2/include/hal/rtc_cntl_ll.h | 9 +- components/hal/esp32h2/include/hal/spi_ll.h | 6 +- .../hal/esp32h2/include/hal/spimem_flash_ll.h | 2 +- components/hal/esp32h2/include/hal/timer_ll.h | 4 +- components/hal/esp32h2/include/hal/twai_ll.h | 2 +- .../hal/esp32h2/include/hal/uhci_types.h | 2 +- components/hal/esp32h2/rtc_cntl_hal.c | 2 +- components/hal/include/hal/adc_hal.h | 20 +- components/hal/include/hal/adc_types.h | 14 +- components/hal/include/hal/gpio_types.h | 44 + components/hal/include/hal/rtc_hal.h | 2 +- components/hal/include/hal/rtc_io_hal.h | 2 +- components/hal/include/hal/sha_types.h | 3 + components/hal/linker.lf | 2 +- components/hal/spi_flash_hal_iram.c | 2 +- components/hal/wdt_hal_iram.c | 2 +- components/soc/esp32h2/gpio_periph.c | 19 + components/soc/esp32h2/i2s_periph.c | 2 +- .../soc/esp32h2/include/soc/apb_ctrl_reg.h | 220 +- .../soc/esp32h2/include/soc/apb_ctrl_struct.h | 100 +- .../soc/esp32h2/include/soc/apb_saradc_reg.h | 21 +- .../esp32h2/include/soc/apb_saradc_struct.h | 6 +- .../soc/esp32h2/include/soc/clkrst_reg.h | 1056 ++++ .../soc/esp32h2/include/soc/dport_access.h | 2 +- .../soc/esp32h2/include/soc/efuse_reg.h | 2 +- components/soc/esp32h2/include/soc/gpio_reg.h | 4350 +++++++++++------ .../soc/esp32h2/include/soc/gpio_sig_map.h | 92 +- components/soc/esp32h2/include/soc/i2s_caps.h | 22 + components/soc/esp32h2/include/soc/i2s_reg.h | 33 + .../soc/esp32h2/include/soc/i2s_struct.h | 38 +- .../esp32h2/include/soc/interrupt_core0_reg.h | 147 +- .../soc/esp32h2/include/soc/io_mux_reg.h | 102 +- .../soc/esp32h2/include/soc/periph_defs.h | 7 + components/soc/esp32h2/include/soc/rtc.h | 33 +- components/soc/esp32h2/include/soc/rtc_caps.h | 22 + .../soc/esp32h2/include/soc/rtc_cntl_reg.h | 836 +++- .../soc/esp32h2/include/soc/rtc_cntl_struct.h | 868 ++-- .../soc/esp32h2/include/soc/rtc_io_caps.h | 21 + .../soc/esp32h2/include/soc/sensitive_reg.h | 750 ++- .../esp32h2/include/soc/sensitive_struct.h | 341 +- components/soc/esp32h2/include/soc/soc.h | 73 +- components/soc/esp32h2/include/soc/spi_caps.h | 38 + components/soc/esp32h2/include/soc/spi_reg.h | 371 +- .../soc/esp32h2/include/soc/spi_struct.h | 97 +- .../soc/esp32h2/include/soc/syscon_reg.h | 272 +- .../soc/esp32h2/include/soc/syscon_struct.h | 82 +- .../soc/esp32h2/include/soc/system_reg.h | 787 +-- .../soc/esp32h2/include/soc/system_struct.h | 274 +- .../soc/esp32h2/include/soc/systimer_reg.h | 917 ++-- .../soc/esp32h2/include/soc/timer_group_reg.h | 5 + .../soc/esp32h2/include/soc/twai_struct.h | 2 +- components/soc/esp32h2/soc_memory_layout.c | 2 +- components/soc/include/soc/lldesc.h | 2 + components/soc/memory_layout_utils.c | 3 + 89 files changed, 7679 insertions(+), 5021 deletions(-) create mode 100644 components/soc/esp32h2/include/soc/clkrst_reg.h create mode 100644 components/soc/esp32h2/include/soc/i2s_caps.h create mode 100644 components/soc/esp32h2/include/soc/rtc_caps.h create mode 100644 components/soc/esp32h2/include/soc/rtc_io_caps.h create mode 100644 components/soc/esp32h2/include/soc/spi_caps.h diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 07a683a832..53a435518a 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -74,6 +74,15 @@ if(IDF_TARGET STREQUAL "esp32c3") "esp32c3/rtc_tempsensor.c") endif() +if(IDF_TARGET STREQUAL "esp32h2") + list(APPEND srcs "gdma.c" + "spi_slave_hd.c" + "adc_common.c" + "esp32h2/adc.c" + "esp32h2/adc2_init_cal.c" + "esp32h2/rtc_tempsensor.c") +endif() + idf_component_register(SRCS "${srcs}" INCLUDE_DIRS ${includes} PRIV_INCLUDE_DIRS "include/driver" diff --git a/components/driver/esp32h2/adc.c b/components/driver/esp32h2/adc.c index 693810da4a..84b2cd5344 100644 --- a/components/driver/esp32h2/adc.c +++ b/components/driver/esp32h2/adc.c @@ -17,7 +17,7 @@ #include "freertos/semphr.h" #include "freertos/timers.h" #include "freertos/ringbuf.h" -#include "esp32c3/rom/ets_sys.h" +#include "esp32h2/rom/ets_sys.h" #include "driver/periph_ctrl.h" #include "driver/gpio.h" #include "driver/adc.h" @@ -53,7 +53,7 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi /** * 1. sar_adc1_lock: this mutex lock is to protect the SARADC1 module. - * 2. sar_adc2_lock: this mutex lock is to protect the SARADC2 module. On C3, it is controlled by the digital controller + * 2. sar_adc2_lock: this mutex lock is to protect the SARADC2 module. On H2, it is controlled by the digital controller * and PWDET controller. * 3. adc_reg_lock: this spin lock is to protect the shared registers used by ADC1 / ADC2 single read mode. */ @@ -462,7 +462,7 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio) esp_err_t adc1_config_width(adc_bits_width_t width_bit) { - //On ESP32C3, the data width is always 12-bits. + //On ESP32H2, the data width is always 12-bits. if (width_bit != ADC_WIDTH_BIT_12) { return ESP_ERR_INVALID_ARG; } @@ -526,7 +526,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out) { - //On ESP32C3, the data width is always 12-bits. + //On ESP32H2, the data width is always 12-bits. if (width_bit != ADC_WIDTH_BIT_12) { return ESP_ERR_INVALID_ARG; } diff --git a/components/driver/esp32h2/rtc_tempsensor.c b/components/driver/esp32h2/rtc_tempsensor.c index 7d03401eee..7226d9b529 100644 --- a/components/driver/esp32h2/rtc_tempsensor.c +++ b/components/driver/esp32h2/rtc_tempsensor.c @@ -18,7 +18,7 @@ #include "soc/system_reg.h" #include "driver/temp_sensor.h" #include "regi2c_ctrl.h" -#include "esp32c3/rom/ets_sys.h" +#include "esp32h2/rom/ets_sys.h" #include "esp_efuse_rtc_calib.h" static const char *TAG = "tsens"; diff --git a/components/driver/include/driver/adc2_wifi_private.h b/components/driver/include/driver/adc2_wifi_private.h index 71481213a3..f8b355196b 100644 --- a/components/driver/include/driver/adc2_wifi_private.h +++ b/components/driver/include/driver/adc2_wifi_private.h @@ -35,7 +35,7 @@ esp_err_t adc2_wifi_acquire(void); */ esp_err_t adc2_wifi_release(void); -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /** * @brief This API help ADC2 calibration constructor be linked. * diff --git a/components/driver/include/driver/adc_common.h b/components/driver/include/driver/adc_common.h index 3fa15d7143..392eb8a15d 100644 --- a/components/driver/include/driver/adc_common.h +++ b/components/driver/include/driver/adc_common.h @@ -45,7 +45,7 @@ typedef enum { ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */ ADC1_CHANNEL_MAX, } adc1_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /**** `adc1_channel_t` will be deprecated functions, combine into `adc_channel_t` ********/ typedef enum { ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ @@ -72,7 +72,7 @@ typedef enum { ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */ ADC2_CHANNEL_MAX, } adc2_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /**** `adc2_channel_t` will be deprecated functions, combine into `adc_channel_t` ********/ typedef enum { ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */ @@ -103,7 +103,7 @@ typedef enum { #define ADC_WIDTH_11Bit ADC_WIDTH_BIT_11 #define ADC_WIDTH_12Bit ADC_WIDTH_BIT_12 -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /** * @brief Digital ADC DMA read max timeout value, it may make the ``adc_digi_read_bytes`` block forever if the OS supports */ @@ -121,7 +121,7 @@ typedef enum { ADC_ENCODE_MAX, } adc_i2s_encode_t; -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 //This feature is currently supported on ESP32C3, will be supported on other chips soon /** * @brief Digital ADC DMA configuration @@ -167,7 +167,7 @@ void adc_power_acquire(void); */ void adc_power_release(void); -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * @brief Initialize ADC pad * @param adc_unit ADC unit index @@ -177,7 +177,7 @@ void adc_power_release(void); * - ESP_ERR_INVALID_ARG Parameter error */ esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel); -#endif //#if !CONFIG_IDF_TARGET_ESP32C3 +#endif //#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /*--------------------------------------------------------------- ADC Single Read Setting @@ -276,7 +276,7 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit); */ int adc1_get_raw(adc1_channel_t channel); -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * @brief Set ADC data invert * @param adc_unit ADC unit index @@ -317,7 +317,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit); * to be called to configure ADC1 channels, before ADC1 is used by the ULP. */ void adc1_ulp_enable(void); -#endif //#if !CONFIG_IDF_TARGET_ESP32C3 +#endif //#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * @brief Get the GPIO number of a specific ADC2 channel. @@ -477,7 +477,7 @@ esp_err_t adc_digi_deinit(void); */ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config); -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 //This feature is currently supported on ESP32C3, will be supported on other chips soon /*--------------------------------------------------------------- DMA setting @@ -537,7 +537,7 @@ esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_l */ esp_err_t adc_digi_deinitialize(void); -#endif //#if CONFIG_IDF_TARGET_ESP32C3 +#endif //#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 #ifdef __cplusplus } diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index e100f9bae7..eeb63f74f8 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -33,6 +33,8 @@ #include "esp32c3/rom/gpio.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/gpio.h" #endif #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS diff --git a/components/driver/periph_ctrl.c b/components/driver/periph_ctrl.c index 9f6b75e6e5..8373848038 100644 --- a/components/driver/periph_ctrl.c +++ b/components/driver/periph_ctrl.c @@ -42,6 +42,7 @@ void periph_module_reset(periph_module_t periph) portEXIT_CRITICAL_SAFE(&periph_spinlock); } +#if CONFIG_WIFI_ENABLED IRAM_ATTR void wifi_bt_common_module_enable(void) { portENTER_CRITICAL_SAFE(&periph_spinlock); @@ -71,3 +72,4 @@ void wifi_module_disable(void) { periph_ll_wifi_module_disable_clk_set_rst(); } +#endif // CONFIG_WIFI_ENABLED diff --git a/components/driver/uart.c b/components/driver/uart.c index ab616179e8..2b66018c2c 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -32,6 +32,8 @@ #include "esp32s3/clk.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/clk.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/clk.h" #endif #ifdef CONFIG_UART_ISR_IN_IRAM diff --git a/components/esp32h2/CMakeLists.txt b/components/esp32h2/CMakeLists.txt index a785c520dc..faeb758285 100644 --- a/components/esp32h2/CMakeLists.txt +++ b/components/esp32h2/CMakeLists.txt @@ -1,13 +1,13 @@ idf_build_get_property(target IDF_TARGET) idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER) -if(NOT "${target}" STREQUAL "esp32c3") +if(NOT "${target}" STREQUAL "esp32h2") return() endif() if(BOOTLOADER_BUILD) - # For bootloader, all we need from esp32c3 is headers + # For bootloader, all we need from esp32h2 is headers idf_component_register(INCLUDE_DIRS include REQUIRES riscv) - target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32c3.peripherals.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32h2.peripherals.ld") else() # Regular app build @@ -31,32 +31,32 @@ else() INCLUDE_DIRS "${include_dirs}" REQUIRES "${requires}" PRIV_REQUIRES "${priv_requires}" - REQUIRED_IDF_TARGETS esp32c3) + REQUIRED_IDF_TARGETS esp32h2) - target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_BINARY_DIR}/esp32c3_out.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_BINARY_DIR}/esp32h2_out.ld") # Process the template file through the linker script generation mechanism, and use the output for linking the # final binary - target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/ld/esp32c3.project.ld.in" - PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32c3.project.ld") - target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32c3.peripherals.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/ld/esp32h2.project.ld.in" + PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/esp32h2.project.ld") + target_linker_script(${COMPONENT_LIB} INTERFACE "ld/esp32h2.peripherals.ld") target_link_libraries(${COMPONENT_LIB} PUBLIC gcc) target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0") idf_build_get_property(config_dir CONFIG_DIR) - # Preprocess esp32c3.ld linker script to include configuration, becomes esp32c3_out.ld + # Preprocess esp32h2.ld linker script to include configuration, becomes esp32h2_out.ld set(LD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/ld) add_custom_command( - OUTPUT esp32c3_out.ld - COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32c3_out.ld -I ${config_dir} ${LD_DIR}/esp32c3.ld - MAIN_DEPENDENCY ${LD_DIR}/esp32c3.ld + OUTPUT esp32h2_out.ld + COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o esp32h2_out.ld -I ${config_dir} ${LD_DIR}/esp32h2.ld + MAIN_DEPENDENCY ${LD_DIR}/esp32h2.ld DEPENDS ${sdkconfig_header} COMMENT "Generating linker script..." VERBATIM) - add_custom_target(esp32c3_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32c3_out.ld) - add_dependencies(${COMPONENT_LIB} esp32c3_linker_script) + add_custom_target(esp32h2_linker_script DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/esp32h2_out.ld) + add_dependencies(${COMPONENT_LIB} esp32h2_linker_script) # disable stack protection in files which are involved in initialization of that feature set_source_files_properties( diff --git a/components/esp32h2/Kconfig b/components/esp32h2/Kconfig index 26d4bacfb9..4413c4b0e5 100644 --- a/components/esp32h2/Kconfig +++ b/components/esp32h2/Kconfig @@ -1,54 +1,48 @@ -menu "ESP32C3-Specific" - visible if IDF_TARGET_ESP32C3 +menu "ESP32H2-Specific" + visible if IDF_TARGET_ESP32H2 - choice ESP32C3_DEFAULT_CPU_FREQ_MHZ + choice ESP32H2_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" - default ESP32C3_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA - default ESP32C3_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA + default ESP32H2_DEFAULT_CPU_FREQ_64 if IDF_ENV_FPGA + default ESP32H2_DEFAULT_CPU_FREQ_96 if !IDF_ENV_FPGA help CPU frequency to be set on application startup. - config ESP32C3_DEFAULT_CPU_FREQ_40 - bool "40 MHz" - depends on IDF_ENV_FPGA - config ESP32C3_DEFAULT_CPU_FREQ_80 - bool "80 MHz" - config ESP32C3_DEFAULT_CPU_FREQ_160 - bool "160 MHz" + config ESP32H2_DEFAULT_CPU_FREQ_16 + bool "16 MHz" + config ESP32H2_DEFAULT_CPU_FREQ_32 + bool "32 MHz" + config ESP32H2_DEFAULT_CPU_FREQ_64 + bool "64 MHz" + config ESP32H2_DEFAULT_CPU_FREQ_96 + bool "96 MHz" + depends on !IDF_ENV_FPGA endchoice - config ESP32C3_DEFAULT_CPU_FREQ_MHZ + config ESP32H2_DEFAULT_CPU_FREQ_MHZ int - default 40 if ESP32C3_DEFAULT_CPU_FREQ_40 - default 80 if ESP32C3_DEFAULT_CPU_FREQ_80 - default 160 if ESP32C3_DEFAULT_CPU_FREQ_160 + default 16 if ESP32H2_DEFAULT_CPU_FREQ_16 + default 32 if ESP32H2_DEFAULT_CPU_FREQ_32 + default 64 if ESP32H2_DEFAULT_CPU_FREQ_64 + default 96 if ESP32H2_DEFAULT_CPU_FREQ_96 - choice ESP32C3_REV_MIN - prompt "Minimum Supported ESP32-C3 Revision" - default ESP32C3_REV_MIN_3 + choice ESP32H2_REV_MIN + prompt "Minimum Supported ESP32-H2 Revision" + default ESP32H2_REV_MIN_0 help Minimum revision that ESP-IDF would support. Only supporting higher chip revisions can reduce binary size. - config ESP32C3_REV_MIN_0 + config ESP32H2_REV_MIN_0 bool "Rev 0" - config ESP32C3_REV_MIN_1 - bool "Rev 1" - config ESP32C3_REV_MIN_2 - bool "Rev 2" - config ESP32C3_REV_MIN_3 - bool "Rev 3" endchoice - config ESP32C3_REV_MIN + config ESP32H2_REV_MIN int - default 0 if ESP32C3_REV_MIN_0 - default 1 if ESP32C3_REV_MIN_1 - default 2 if ESP32C3_REV_MIN_2 - default 3 if ESP32C3_REV_MIN_3 + default 0 if ESP32H2_REV_MIN_0 - config ESP32C3_DEBUG_OCDAWARE + config ESP32H2_DEBUG_OCDAWARE bool "Make exception and panic handlers JTAG/OCD aware" default y select FREERTOS_DEBUG_OCDAWARE @@ -56,15 +50,15 @@ menu "ESP32C3-Specific" The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and instead of panicking, have the debugger stop on the offending instruction. - config ESP32C3_DEBUG_STUBS_ENABLE + config ESP32H2_DEBUG_STUBS_ENABLE bool "OpenOCD debug stubs" default COMPILER_OPTIMIZATION_LEVEL_DEBUG - depends on !ESP32C3_TRAX + depends on !ESP32H2_TRAX help Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging, e.g. GCOV data dump. - config ESP32C3_BROWNOUT_DET + config ESP32H2_BROWNOUT_DET bool "Hardware brownout detect & reset" default y help @@ -72,10 +66,10 @@ menu "ESP32C3-Specific" a specific value. If this happens, it will reset the chip in order to prevent unintended behaviour. - choice ESP32C3_BROWNOUT_DET_LVL_SEL + choice ESP32H2_BROWNOUT_DET_LVL_SEL prompt "Brownout voltage level" - depends on ESP32C3_BROWNOUT_DET - default ESP32C3_BROWNOUT_DET_LVL_SEL_7 + depends on ESP32H2_BROWNOUT_DET + default ESP32H2_BROWNOUT_DET_LVL_SEL_7 help The brownout detector will reset the chip when the supply voltage is approximately below this level. Note that there may be some variation of brownout voltage level @@ -83,32 +77,32 @@ menu "ESP32C3-Specific" #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages #of the brownout threshold levels. - config ESP32C3_BROWNOUT_DET_LVL_SEL_7 + config ESP32H2_BROWNOUT_DET_LVL_SEL_7 bool "2.51V" - config ESP32C3_BROWNOUT_DET_LVL_SEL_6 + config ESP32H2_BROWNOUT_DET_LVL_SEL_6 bool "2.64V" - config ESP32C3_BROWNOUT_DET_LVL_SEL_5 + config ESP32H2_BROWNOUT_DET_LVL_SEL_5 bool "2.76V" - config ESP32C3_BROWNOUT_DET_LVL_SEL_4 + config ESP32H2_BROWNOUT_DET_LVL_SEL_4 bool "2.92V" - config ESP32C3_BROWNOUT_DET_LVL_SEL_3 + config ESP32H2_BROWNOUT_DET_LVL_SEL_3 bool "3.10V" - config ESP32C3_BROWNOUT_DET_LVL_SEL_2 + config ESP32H2_BROWNOUT_DET_LVL_SEL_2 bool "3.27V" endchoice - config ESP32C3_BROWNOUT_DET_LVL + config ESP32H2_BROWNOUT_DET_LVL int - default 2 if ESP32C3_BROWNOUT_DET_LVL_SEL_2 - default 3 if ESP32C3_BROWNOUT_DET_LVL_SEL_3 - default 4 if ESP32C3_BROWNOUT_DET_LVL_SEL_4 - default 5 if ESP32C3_BROWNOUT_DET_LVL_SEL_5 - default 6 if ESP32C3_BROWNOUT_DET_LVL_SEL_6 - default 7 if ESP32C3_BROWNOUT_DET_LVL_SEL_7 + default 2 if ESP32H2_BROWNOUT_DET_LVL_SEL_2 + default 3 if ESP32H2_BROWNOUT_DET_LVL_SEL_3 + default 4 if ESP32H2_BROWNOUT_DET_LVL_SEL_4 + default 5 if ESP32H2_BROWNOUT_DET_LVL_SEL_5 + default 6 if ESP32H2_BROWNOUT_DET_LVL_SEL_6 + default 7 if ESP32H2_BROWNOUT_DET_LVL_SEL_7 - choice ESP32C3_TIME_SYSCALL + choice ESP32H2_TIME_SYSCALL prompt "Timers used for gettimeofday function" - default ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER + default ESP32H2_TIME_SYSCALL_USE_RTC_SYSTIMER help This setting defines which hardware timers are used to implement 'gettimeofday' and 'time' functions in C library. @@ -128,44 +122,43 @@ menu "ESP32C3-Specific" - When RTC is used for timekeeping, two RTC_STORE registers are used to keep time in deep sleep mode. - config ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER + config ESP32H2_TIME_SYSCALL_USE_RTC_SYSTIMER bool "RTC and high-resolution timer" select ESP_TIME_FUNCS_USE_RTC_TIMER select ESP_TIME_FUNCS_USE_ESP_TIMER - config ESP32C3_TIME_SYSCALL_USE_RTC + config ESP32H2_TIME_SYSCALL_USE_RTC bool "RTC" select ESP_TIME_FUNCS_USE_RTC_TIMER - config ESP32C3_TIME_SYSCALL_USE_SYSTIMER + config ESP32H2_TIME_SYSCALL_USE_SYSTIMER bool "High-resolution timer" select ESP_TIME_FUNCS_USE_ESP_TIMER - config ESP32C3_TIME_SYSCALL_USE_NONE + config ESP32H2_TIME_SYSCALL_USE_NONE bool "None" select ESP_TIME_FUNCS_USE_NONE endchoice - choice ESP32C3_RTC_CLK_SRC + choice ESP32H2_RTC_CLK_SRC prompt "RTC clock source" - default ESP32C3_RTC_CLK_SRC_INT_RC + default ESP32H2_RTC_CLK_SRC_INT_RC help Choose which clock is used as RTC clock source. - config ESP32C3_RTC_CLK_SRC_INT_RC + config ESP32H2_RTC_CLK_SRC_INT_RC bool "Internal 150kHz RC oscillator" - config ESP32C3_RTC_CLK_SRC_EXT_CRYS + config ESP32H2_RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" select ESP_SYSTEM_RTC_EXT_XTAL - config ESP32C3_RTC_CLK_SRC_EXT_OSC + config ESP32H2_RTC_CLK_SRC_EXT_OSC bool "External 32kHz oscillator at 32K_XP pin" - config ESP32C3_RTC_CLK_SRC_INT_8MD256 + config ESP32H2_RTC_CLK_SRC_INT_8MD256 bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" endchoice - config ESP32C3_RTC_CLK_CAL_CYCLES + config ESP32H2_RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC + default 3000 if ESP32H2_RTC_CLK_SRC_EXT_CRYS || ESP32H2_RTC_CLK_SRC_EXT_OSC || ESP32H2_RTC_CLK_SRC_INT_8MD256 + default 576 if ESP32H2_RTC_CLK_SRC_INT_RC + range 0 125000 help When the startup code initializes RTC_SLOW_CLK, it can perform calibration by comparing the RTC_SLOW_CLK frequency with main XTAL @@ -182,7 +175,7 @@ menu "ESP32C3-Specific" In case more value will help improve the definition of the launch of the crystal. If the crystal could not start, it will be switched to internal RC. - config ESP32C3_NO_BLOBS + config ESP32H2_NO_BLOBS bool "No Binary Blobs" depends on !BT_ENABLED default n @@ -190,12 +183,12 @@ menu "ESP32C3-Specific" If enabled, this disables the linking of binary libraries in the application build. Note that after enabling this Wi-Fi/Bluetooth will not work. - config ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND + config ESP32H2_LIGHTSLEEP_GPIO_RESET_WORKAROUND bool "light sleep GPIO reset workaround" default y select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE help - ESP32C3 will reset at wake-up if GPIO is received a small electrostatic pulse during + ESP32H2 will reset at wake-up if GPIO is received a small electrostatic pulse during light sleep, with specific condition - GPIO needs to be configured as input-mode only @@ -209,4 +202,4 @@ menu "ESP32C3-Specific" This option provides a software workaround for this issue. Configure to isolate all GPIO pins in sleep state. -endmenu # ESP32C3-Specific +endmenu # ESP32H2-Specific diff --git a/components/esp32h2/Makefile.projbuild b/components/esp32h2/Makefile.projbuild index cb10139573..d79da62ad4 100644 --- a/components/esp32h2/Makefile.projbuild +++ b/components/esp32h2/Makefile.projbuild @@ -1 +1 @@ -# ESP32-C3 is not supported in the GNU Make build system. +# ESP32-H2 is not supported in the GNU Make build system. diff --git a/components/esp32h2/esp_ds.c b/components/esp32h2/esp_ds.c index 3dbaa79dc5..1ae6ab8221 100644 --- a/components/esp32h2/esp_ds.c +++ b/components/esp32h2/esp_ds.c @@ -23,7 +23,7 @@ #include "hal/ds_hal.h" #include "hal/ds_ll.h" #include "hal/hmac_hal.h" -#include "esp32c3/rom/digital_signature.h" +#include "esp32h2/rom/digital_signature.h" #include "esp_timer.h" #include "esp_ds.h" @@ -123,7 +123,7 @@ esp_err_t esp_ds_start_sign(const void *message, uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); if (conf_error) { ds_disable_release(); - return ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL; + return ESP32H2_ERR_HW_CRYPTO_DS_HMAC_FAIL; } ds_hal_start(); @@ -133,7 +133,7 @@ esp_err_t esp_ds_start_sign(const void *message, while (ds_ll_busy() != 0) { if ((esp_timer_get_time() - start_time) > SOC_DS_KEY_CHECK_MAX_WAIT_US) { ds_disable_release(); - return ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY; + return ESP32H2_ERR_HW_CRYPTO_DS_INVALID_KEY; } } @@ -178,11 +178,11 @@ esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx) esp_err_t return_value = ESP_OK; if (sig_check_result == DS_SIGNATURE_MD_FAIL || sig_check_result == DS_SIGNATURE_PADDING_AND_MD_FAIL) { - return_value = ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST; + return_value = ESP32H2_ERR_HW_CRYPTO_DS_INVALID_DIGEST; } if (sig_check_result == DS_SIGNATURE_PADDING_FAIL) { - return_value = ESP32C3_ERR_HW_CRYPTO_DS_INVALID_PADDING; + return_value = ESP32H2_ERR_HW_CRYPTO_DS_INVALID_PADDING; } free(esp_ds_ctx); diff --git a/components/esp32h2/esp_hmac.c b/components/esp32h2/esp_hmac.c index 9f71353e30..9ca245f2d8 100644 --- a/components/esp32h2/esp_hmac.c +++ b/components/esp32h2/esp_hmac.c @@ -14,8 +14,8 @@ #include #include "driver/periph_ctrl.h" -#include "esp32c3/rom/hmac.h" -#include "esp32c3/rom/ets_sys.h" +#include "esp32h2/rom/hmac.h" +#include "esp32h2/rom/ets_sys.h" #include "esp_hmac.h" #include "esp_crypto_lock.h" @@ -30,13 +30,13 @@ * @note This function does not check the data length, it is the responsibility of the other functions in this * module to make sure that \c data_len is at most SHA256_BLOCK_SZ - 1 so the padding fits in. * Otherwise, this function has undefined behavior. - * Note however, that for the actual HMAC implementation on ESP32C3, the length also needs to be applied at the end + * Note however, that for the actual HMAC implementation on ESP32H2, the length also needs to be applied at the end * of the block. This function alone deosn't do that. */ static void write_and_padd(uint8_t *block, const uint8_t *data, uint16_t data_len) { memcpy(block, data, data_len); - // Apply a one bit, followed by zero bits (refer to the ESP32C3 TRM). + // Apply a one bit, followed by zero bits (refer to the ESP32H2 TRM). block[data_len] = 0x80; bzero(block + data_len + 1, SHA256_BLOCK_SZ - data_len - 1); } diff --git a/components/esp32h2/include/esp32h2/memprot.h b/components/esp32h2/include/esp32h2/memprot.h index 094f28f42e..58d06eba18 100644 --- a/components/esp32h2/include/esp32h2/memprot.h +++ b/components/esp32h2/include/esp32h2/memprot.h @@ -244,7 +244,7 @@ bool esp_memprot_get_monitor_en(mem_type_prot_t mem_type); /** * @brief Gets CPU ID for currently active PMS violation interrupt * - * @return CPU ID (CPU_PRO for ESP32C3) + * @return CPU ID (CPU_PRO for ESP32H2) */ int IRAM_ATTR esp_memprot_intr_get_cpuid(void); diff --git a/components/esp32h2/include/esp32h2/rtc.h b/components/esp32h2/include/esp32h2/rtc.h index b090ae5cfb..cca748df91 100644 --- a/components/esp32h2/include/esp32h2/rtc.h +++ b/components/esp32h2/include/esp32h2/rtc.h @@ -21,7 +21,7 @@ extern "C" { #endif /** - * @file esp32c3/rtc.h + * @file esp32h2/rtc.h * * This file contains declarations of rtc related functions. */ diff --git a/components/esp32h2/include/esp_ds.h b/components/esp32h2/include/esp_ds.h index 911e44c837..79e963fc6b 100644 --- a/components/esp32h2/include/esp_ds.h +++ b/components/esp32h2/include/esp_ds.h @@ -21,12 +21,12 @@ extern "C" { #endif -#define ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL ESP_ERR_HW_CRYPTO_BASE + 0x1 /*!< HMAC peripheral problem */ -#define ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY ESP_ERR_HW_CRYPTO_BASE + 0x2 /*!< given HMAC key isn't correct, +#define ESP32H2_ERR_HW_CRYPTO_DS_HMAC_FAIL ESP_ERR_HW_CRYPTO_BASE + 0x1 /*!< HMAC peripheral problem */ +#define ESP32H2_ERR_HW_CRYPTO_DS_INVALID_KEY ESP_ERR_HW_CRYPTO_BASE + 0x2 /*!< given HMAC key isn't correct, HMAC peripheral problem */ -#define ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST ESP_ERR_HW_CRYPTO_BASE + 0x4 /*!< message digest check failed, +#define ESP32H2_ERR_HW_CRYPTO_DS_INVALID_DIGEST ESP_ERR_HW_CRYPTO_BASE + 0x4 /*!< message digest check failed, result is invalid */ -#define ESP32C3_ERR_HW_CRYPTO_DS_INVALID_PADDING ESP_ERR_HW_CRYPTO_BASE + 0x5 /*!< padding check failed, but result +#define ESP32H2_ERR_HW_CRYPTO_DS_INVALID_PADDING ESP_ERR_HW_CRYPTO_BASE + 0x5 /*!< padding check failed, but result is produced anyway and can be read*/ #define ESP_DS_IV_BIT_LEN 128 diff --git a/components/esp32h2/ld/esp32h2.ld b/components/esp32h2/ld/esp32h2.ld index 63a26c4276..f89de9d4a9 100644 --- a/components/esp32h2/ld/esp32h2.ld +++ b/components/esp32h2/ld/esp32h2.ld @@ -1,5 +1,5 @@ /** - * ESP32-C3 Linker Script Memory Layout + * ESP32-H2 Linker Script Memory Layout * This file describes the memory layout (memory blocks) by virtual memory addresses. * This linker script is passed through the C preprocessor to include configuration options. * Please use preprocessor features sparingly! @@ -27,12 +27,12 @@ #define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG -#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE -ASSERT((CONFIG_ESP32C3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.") +#if CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE +ASSERT((CONFIG_ESP32H2_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.") #define DRAM0_0_SEG_LEN CONFIG_ESP3C3_FIXED_STATIC_RAM_SIZE #else #define DRAM0_0_SEG_LEN I_D_SRAM_SIZE -#endif // CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE +#endif // CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE MEMORY { /** @@ -76,12 +76,12 @@ MEMORY rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC } -#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE +#if CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE /* static data ends at defined address */ _static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN; #else _static_data_end = _bss_end; -#endif // CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE +#endif // CONFIG_ESP32H2_USE_FIXED_STATIC_RAM_SIZE /* Heap ends at top of dram0_0_seg */ _heap_end = 0x40000000; diff --git a/components/esp32h2/ld/esp32h2.project.ld.in b/components/esp32h2/ld/esp32h2.project.ld.in index 58f27c9e19..459c8cb6f7 100644 --- a/components/esp32h2/ld/esp32h2.project.ld.in +++ b/components/esp32h2/ld/esp32h2.project.ld.in @@ -52,7 +52,7 @@ SECTIONS * named rtc_wake_stub*.c and the data marked with * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. * The memory location of the data is dependent on - * CONFIG_ESP32C3_RTCDATA_IN_FAST_MEM option. + * CONFIG_ESP32H2_RTCDATA_IN_FAST_MEM option. */ .rtc.data : { @@ -81,7 +81,7 @@ SECTIONS * and will be retained during deep sleep. * User data marked with RTC_NOINIT_ATTR will be placed * into this section. See the file "esp_attr.h" for more information. - * The memory location of the data is dependent on CONFIG_ESP32C3_RTCDATA_IN_FAST_MEM option. + * The memory location of the data is dependent on CONFIG_ESP32H2_RTCDATA_IN_FAST_MEM option. */ .rtc_noinit (NOLOAD): { diff --git a/components/esp32h2/memprot.c b/components/esp32h2/memprot.c index 20cc054ad5..5897ad67f0 100644 --- a/components/esp32h2/memprot.c +++ b/components/esp32h2/memprot.c @@ -23,9 +23,9 @@ #include "soc/periph_defs.h" #include "esp_intr_alloc.h" #include "hal/memprot_ll.h" -#include "esp32c3/memprot.h" +#include "esp32h2/memprot.h" #include "riscv/interrupt.h" -#include "esp32c3/rom/ets_sys.h" +#include "esp32h2/rom/ets_sys.h" #include "esp_log.h" extern int _iram_text_end; diff --git a/components/esp32h2/test/CMakeLists.txt b/components/esp32h2/test/CMakeLists.txt index 068a0a8549..78352046b0 100644 --- a/components/esp32h2/test/CMakeLists.txt +++ b/components/esp32h2/test/CMakeLists.txt @@ -1,4 +1,4 @@ -if(IDF_TARGET STREQUAL "esp32c3") +if(IDF_TARGET STREQUAL "esp32h2") idf_component_register(SRC_DIRS . INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR} REQUIRES unity test_utils esp_common mbedtls diff --git a/components/esp32h2/test/test_ds.c b/components/esp32h2/test/test_ds.c index aaffce8439..e57d8a2cec 100644 --- a/components/esp32h2/test/test_ds.c +++ b/components/esp32h2/test/test_ds.c @@ -13,9 +13,9 @@ // limitations under the License. #include "unity.h" -#include "esp32c3/rom/efuse.h" -#include "esp32c3/rom/digital_signature.h" -#include "esp32c3/rom/hmac.h" +#include "esp32h2/rom/efuse.h" +#include "esp32h2/rom/digital_signature.h" +#include "esp32h2/rom/hmac.h" #include #include "esp_ds.h" @@ -256,7 +256,7 @@ TEST_CASE("Digital Signature wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ const char *message = "test"; // HMAC fails in that case because it checks for the correct purpose - TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx)); + TEST_ASSERT_EQUAL(ESP32H2_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx)); } // This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys(). @@ -269,7 +269,7 @@ TEST_CASE("Digital Signature Blocking wrong HMAC key purpose (FPGA only)", "[hw_ uint8_t signature_data [128 * 4]; // HMAC fails in that case because it checks for the correct purpose - TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data)); + TEST_ASSERT_EQUAL(ESP32H2_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data)); } TEST_CASE("Digital Signature Operation (FPGA only)", "[hw_crypto] [ds]") @@ -356,7 +356,7 @@ TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]") esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx); TEST_ASSERT_EQUAL(ESP_OK, ds_r); ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); - TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); + TEST_ASSERT_EQUAL(ESP32H2_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS/8); ds_data.iv[bit / 8] ^= 1 << (bit % 8); @@ -372,7 +372,7 @@ TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]") esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx); TEST_ASSERT_EQUAL(ESP_OK, ds_r); ds_r = esp_ds_finish_sign(signature, esp_ds_ctx); - TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); + TEST_ASSERT_EQUAL(ESP32H2_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r); TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS/8); ds_data.c[bit / 8] ^= 1 << (bit % 8); diff --git a/components/esp32h2/test/test_sha.c b/components/esp32h2/test/test_sha.c index 052433d6ac..e15fe43522 100644 --- a/components/esp32h2/test/test_sha.c +++ b/components/esp32h2/test/test_sha.c @@ -2,7 +2,7 @@ #include #include #include "esp_types.h" -#include "esp32c3/clk.h" +#include "esp32h2/clk.h" #include "esp_log.h" #include "esp_timer.h" #include "esp_heap_caps.h" diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index c18501f48e..d4a1a86df4 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -98,6 +98,19 @@ if(NOT BOOTLOADER_BUILD) "esp32c3/hmac_hal.c" "esp32c3/rtc_cntl_hal.c") endif() + + if(${target} STREQUAL "esp32h2") + list(APPEND srcs + "ds_hal.c" + "gdma_hal.c" + "spi_flash_hal_gpspi.c" + "spi_slave_hd_hal.c" + "systimer_hal.c" + "esp32h2/adc_hal.c" + "esp32h2/brownout_hal.c" + "esp32h2/hmac_hal.c" + "esp32h2/rtc_cntl_hal.c") + endif() endif() idf_component_register(SRCS ${srcs} diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index d67f583a27..c4b873f724 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -20,7 +20,7 @@ #include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 #include "soc/gdma_channel.h" #include "soc/soc.h" #include "esp_rom_sys.h" @@ -87,7 +87,7 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel) return (uint32_t)adc_ll_rtc_get_convert_value(adc_n); } -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd) { adc_ll_onetime_sample_enable(ADC_NUM_1, false); @@ -187,7 +187,7 @@ uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc } #endif //SOC_ADC_HW_CALIBRATION_V1 -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 //This feature is currently supported on ESP32C3, will be supported on other chips soon /*--------------------------------------------------------------- DMA setting @@ -383,7 +383,7 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw) return ret; } -#else // !CONFIG_IDF_TARGET_ESP32C3 +#else // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw) { adc_ll_rtc_enable_channel(adc_n, channel); @@ -397,4 +397,4 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw) return ESP_OK; } -#endif //#if !CONFIG_IDF_TARGET_ESP32C3 +#endif //#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C3 diff --git a/components/hal/esp32h2/adc_hal.c b/components/hal/esp32h2/adc_hal.c index e4b893bdb6..4490db606f 100644 --- a/components/hal/esp32h2/adc_hal.c +++ b/components/hal/esp32h2/adc_hal.c @@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -// The HAL layer for ADC (ESP32-C3 specific part) +// The HAL layer for ADC (ESP32-H2 specific part) #include #include "soc/soc_caps.h" @@ -58,7 +58,7 @@ static void adc_hal_digi_clk_config(void) void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) { - //only one pattern table is supported on C3, but LL still needs one argument. + //only one pattern table is supported on H2, but LL still needs one argument. const int pattern_both = 0; if (cfg->adc_pattern_len) { @@ -84,7 +84,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) static void filter_update(adc_digi_filter_idx_t idx) { - //ESP32-C3 has no enable bit, the filter will be enabled when the filter channel is configured + //ESP32-H2 has no enable bit, the filter will be enabled when the filter channel is configured if (s_filter_enabled[idx]) { adc_ll_digi_filter_set_factor(idx, &s_filter[idx]); } else { @@ -123,7 +123,7 @@ void adc_hal_digi_filter_enable(adc_digi_filter_idx_t filter_idx, bool enable) static void update_monitor(adc_digi_monitor_idx_t idx) { - //ESP32-C3 has no enable bit, the monitor will be enabled when the monitor channel is configured + //ESP32-H2 has no enable bit, the monitor will be enabled when the monitor channel is configured if (s_monitor_enabled[idx]) { adc_ll_digi_monitor_set_mode(idx, &s_monitor_config[idx]); } else { diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h index a2fd21f2b5..3ec07b06a9 100644 --- a/components/hal/esp32h2/include/hal/adc_ll.h +++ b/components/hal/esp32h2/include/hal/adc_ll.h @@ -444,7 +444,7 @@ static inline void adc_ll_digi_reset(void) static inline void adc_ll_pwdet_set_cct(uint32_t cct) { /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; + // RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; // ESP32H2-TODO } /** @@ -456,7 +456,8 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct) static inline uint32_t adc_ll_pwdet_get_cct(void) { /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; + // return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; + return 0; // ESP32H2-TODO } /** @@ -684,45 +685,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par */ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) { - if (en) { - REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - - REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); - SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); - SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); - SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); - APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF; - APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF; - APB_SARADC.onetime_sample.adc1_onetime_sample = 1; - APB_SARADC.onetime_sample.onetime_channel = channel; - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); - if (adc == ADC_NUM_1) { - /* Config test mux to route v_ref to ADC1 Channels */ - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); - } else { - /* Config test mux to route v_ref to ADC2 Channels */ - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); - } - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); - APB_SARADC.onetime_sample.adc1_onetime_sample = 0; - APB_SARADC.onetime_sample.onetime_channel = 0xf; - REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); - REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); - CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); - CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); - CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); - } + // ESP32H2-TODO } /*--------------------------------------------------------------- @@ -786,13 +749,13 @@ static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable) static inline uint32_t adc_ll_adc1_read(void) { - //On ESP32C3, valid data width is 12-bit + //On ESP32H2, valid data width is 12-bit return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff); } static inline uint32_t adc_ll_adc2_read(void) { - //On ESP32C3, valid data width is 12-bit + //On ESP32H2, valid data width is 12-bit return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff); } diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h index f7382650d5..adfa13261d 100644 --- a/components/hal/esp32h2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -68,18 +68,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return SYSTEM_CRYPTO_HMAC_CLK_EN; case PERIPH_DS_MODULE: return SYSTEM_CRYPTO_DS_CLK_EN; - case PERIPH_RNG_MODULE: - return SYSTEM_WIFI_CLK_RNG_EN; - case PERIPH_WIFI_MODULE: - return SYSTEM_WIFI_CLK_WIFI_EN_M; - case PERIPH_BT_MODULE: - return SYSTEM_WIFI_CLK_BT_EN_M; - case PERIPH_WIFI_BT_COMMON_MODULE: - return SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M; - case PERIPH_BT_BASEBAND_MODULE: - return SYSTEM_BT_BASEBAND_EN; - case PERIPH_BT_LC_MODULE: - return SYSTEM_BT_LC_EN; default: return 0; } @@ -157,14 +145,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) { switch (periph) { - case PERIPH_RNG_MODULE: - case PERIPH_WIFI_MODULE: - case PERIPH_BT_MODULE: - case PERIPH_WIFI_BT_COMMON_MODULE: - case PERIPH_BT_BASEBAND_MODULE: - case PERIPH_BT_LC_MODULE: - return SYSTEM_WIFI_CLK_EN_REG; - case PERIPH_HMAC_MODULE: case PERIPH_DS_MODULE: case PERIPH_AES_MODULE: @@ -180,14 +160,6 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) { switch (periph) { - case PERIPH_RNG_MODULE: - case PERIPH_WIFI_MODULE: - case PERIPH_BT_MODULE: - case PERIPH_WIFI_BT_COMMON_MODULE: - case PERIPH_BT_BASEBAND_MODULE: - case PERIPH_BT_LC_MODULE: - return SYSTEM_WIFI_RST_EN_REG; - case PERIPH_HMAC_MODULE: case PERIPH_DS_MODULE: case PERIPH_AES_MODULE: @@ -212,18 +184,6 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } -static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) -{ - DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - -static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) -{ - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - static inline void periph_ll_reset(periph_module_t periph) { DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); @@ -236,17 +196,6 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; } -static inline void periph_ll_wifi_module_enable_clk_clear_rst(void) -{ - DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} - -static inline void periph_ll_wifi_module_disable_clk_set_rst(void) -{ - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M); - DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0); -} #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/cpu_ll.h b/components/hal/esp32h2/include/hal/cpu_ll.h index 4e9d449409..0b05675d32 100644 --- a/components/hal/esp32h2/include/hal/cpu_ll.h +++ b/components/hal/esp32h2/include/hal/cpu_ll.h @@ -69,7 +69,7 @@ static inline void* cpu_ll_get_sp(void) static inline void cpu_ll_init_hwloop(void) { - // Nothing needed here for ESP32-C3 + // Nothing needed here for ESP32-H2 } static inline void cpu_ll_set_breakpoint(int id, uint32_t pc) diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h index 6ba4d601b9..e35a71db39 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/hal/gpio_ll.h @@ -18,7 +18,7 @@ * See readme.md in soc/include/hal/readme.md ******************************************************************************/ -// The LL layer for ESP32-C3 GPIO register operations +// The LL layer for ESP32-H2 GPIO register operations #pragma once @@ -125,7 +125,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin */ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) { - *status = 0; // Less than 32 GPIOs in ESP32-C3 + *status = 0; // Less than 32 GPIOs in ESP32-H2 } /** diff --git a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h index f80fc83b26..6c4fbdc6c4 100644 --- a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h @@ -34,7 +34,7 @@ extern "C" { #endif -//NOTE: These macros are changed on c3 for build. MODIFY these when bringup flash. +//NOTE: These macros are changed on h2 for build. MODIFY these when bringup flash. #define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) ) #define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 ) diff --git a/components/hal/esp32h2/include/hal/hmac_hal.h b/components/hal/esp32h2/include/hal/hmac_hal.h index e8e29d07fd..7a03814544 100644 --- a/components/hal/esp32h2/include/hal/hmac_hal.h +++ b/components/hal/esp32h2/include/hal/hmac_hal.h @@ -51,7 +51,7 @@ void hmac_hal_start(void); * @note Writing out-of-range values is undefined behavior. The user has to ensure that the parameters are in range. * * @param config The target of the HMAC. Possible targets are described in \c hmac_hal_output_t. - * See the ESP32C3 TRM for more details. + * See the ESP32H2 TRM for more details. * @param key_id The ID of the hardware key slot to be used. * * @return 0 if the configuration was successful, non-zero if not. @@ -65,7 +65,7 @@ uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id); * * The message must not be longer than one block (512 bits) and the padding has to be applied by software before * writing. The padding has to be able to fit into the block after the message. - * For more information on HMAC padding, see the ESP32C3 TRM. + * For more information on HMAC padding, see the ESP32H2 TRM. */ void hmac_hal_write_one_block_512(const void *block); @@ -80,7 +80,7 @@ void hmac_hal_write_one_block_512(const void *block); * Before writing the last block which contains the padding, a call to \c hmac_hal_next_block_padding() is necessary * to indicate to the hardware that a block with padding will be written. * - * For more information on HMAC padding, see the ESP32C3 TRM. + * For more information on HMAC padding, see the ESP32h2 TRM. */ void hmac_hal_write_block_512(const void *block); diff --git a/components/hal/esp32h2/include/hal/hmac_ll.h b/components/hal/esp32h2/include/hal/hmac_ll.h index 8e257a7d32..0ddaf1db97 100644 --- a/components/hal/esp32h2/include/hal/hmac_ll.h +++ b/components/hal/esp32h2/include/hal/hmac_ll.h @@ -159,7 +159,7 @@ static inline void hmac_ll_msg_padding(void) * @brief Signals that all blocks have been written and a padding block will automatically be applied by hardware. * * Only applies if the message length is a multiple of 512 bits. - * See ESP32C3 TRM HMAC chapter for more details. + * See ESP32H2 TRM HMAC chapter for more details. */ static inline void hmac_ll_msg_end(void) { diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h index 4a6042cf12..c54d7de83a 100644 --- a/components/hal/esp32h2/include/hal/i2s_ll.h +++ b/components/hal/esp32h2/include/hal/i2s_ll.h @@ -47,7 +47,7 @@ extern "C" { */ static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -59,7 +59,7 @@ static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) */ static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -71,7 +71,7 @@ static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) */ static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -83,7 +83,7 @@ static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -95,7 +95,7 @@ static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -107,7 +107,7 @@ static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -119,7 +119,7 @@ static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -131,7 +131,7 @@ static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) */ static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -143,7 +143,7 @@ static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) */ static inline void i2s_ll_reset_tx(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -155,7 +155,7 @@ static inline void i2s_ll_reset_tx(i2s_dev_t *hw) */ static inline void i2s_ll_reset_rx(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -167,7 +167,7 @@ static inline void i2s_ll_reset_rx(i2s_dev_t *hw) */ static inline void i2s_ll_start_out_link(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -178,7 +178,7 @@ static inline void i2s_ll_start_out_link(i2s_dev_t *hw) */ static inline void i2s_ll_start_tx(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -189,7 +189,7 @@ static inline void i2s_ll_start_tx(i2s_dev_t *hw) */ static inline void i2s_ll_start_in_link(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -200,7 +200,7 @@ static inline void i2s_ll_start_in_link(i2s_dev_t *hw) */ static inline void i2s_ll_start_rx(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -211,7 +211,7 @@ static inline void i2s_ll_start_rx(i2s_dev_t *hw) */ static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -222,7 +222,7 @@ static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) */ static inline void i2s_ll_stop_tx(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -233,7 +233,7 @@ static inline void i2s_ll_stop_tx(i2s_dev_t *hw) */ static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -244,7 +244,7 @@ static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) */ static inline void i2s_ll_stop_rx(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -255,7 +255,7 @@ static inline void i2s_ll_stop_rx(i2s_dev_t *hw) */ static inline void i2s_ll_enable_dma(i2s_dev_t *hw) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // //Enable and configure DMA // typeof(hw->lc_conf) lc_conf; // lc_conf.val = 0; @@ -271,7 +271,7 @@ static inline void i2s_ll_enable_dma(i2s_dev_t *hw) */ static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->int_st.val; } @@ -283,7 +283,7 @@ static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -295,7 +295,7 @@ static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->out_eof_des_addr; } @@ -307,7 +307,7 @@ static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->in_eof_des_addr; } @@ -319,7 +319,7 @@ static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->fifo_conf.tx_fifo_mod; } @@ -331,7 +331,7 @@ static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -343,7 +343,7 @@ static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->fifo_conf.rx_fifo_mod; } @@ -355,7 +355,7 @@ static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -367,7 +367,7 @@ static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -379,7 +379,7 @@ static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -391,7 +391,7 @@ static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -403,7 +403,7 @@ static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -415,7 +415,7 @@ static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -427,7 +427,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->pdm_freq_conf.tx_pdm_fp; } @@ -439,7 +439,7 @@ static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->pdm_freq_conf.tx_pdm_fs; } @@ -451,7 +451,7 @@ static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -463,7 +463,7 @@ static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -475,7 +475,7 @@ static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->pdm_conf.rx_sinc_dsr_16_en; } @@ -487,7 +487,7 @@ static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) */ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -499,7 +499,7 @@ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -511,7 +511,7 @@ static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -523,7 +523,7 @@ static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -535,7 +535,7 @@ static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -547,7 +547,7 @@ static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -559,7 +559,7 @@ static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -571,7 +571,7 @@ static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -583,7 +583,7 @@ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -595,7 +595,7 @@ static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -607,7 +607,7 @@ static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -619,7 +619,7 @@ static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -631,7 +631,7 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -711,7 +711,7 @@ static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw) */ static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -723,7 +723,7 @@ static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -735,7 +735,7 @@ static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -747,7 +747,7 @@ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -759,7 +759,7 @@ static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -771,7 +771,7 @@ static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -783,7 +783,7 @@ static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -795,7 +795,7 @@ static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -807,7 +807,7 @@ static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -819,7 +819,7 @@ static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->conf.tx_msb_right; } @@ -831,7 +831,7 @@ static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 // *val = hw->conf.rx_msb_right; } @@ -843,7 +843,7 @@ static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -855,7 +855,7 @@ static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -867,7 +867,7 @@ static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -879,7 +879,7 @@ static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -891,7 +891,7 @@ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } @@ -903,7 +903,7 @@ static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val) { - abort(); // TODO ESP32-C3 IDF-2098 + abort(); // TODO ESP32-H2 IDF-2098 } diff --git a/components/hal/esp32h2/include/hal/memprot_ll.h b/components/hal/esp32h2/include/hal/memprot_ll.h index 5da2b452d3..cc3fe68c7d 100644 --- a/components/hal/esp32h2/include/hal/memprot_ll.h +++ b/components/hal/esp32h2/include/hal/memprot_ll.h @@ -29,7 +29,7 @@ extern "C" { #define IRAM_SRAM_START 0x4037C000 #define DRAM_SRAM_START 0x3FC7C000 -/* ICache size is fixed to 16KB on ESP32-C3 */ +/* ICache size is fixed to 16KB on ESP32-H2 */ #ifndef ICACHE_SIZE #define ICACHE_SIZE 0x4000 #endif diff --git a/components/hal/esp32h2/include/hal/mpu_ll.h b/components/hal/esp32h2/include/hal/mpu_ll.h index 77fa580cdb..e38408b49e 100644 --- a/components/hal/esp32h2/include/hal/mpu_ll.h +++ b/components/hal/esp32h2/include/hal/mpu_ll.h @@ -20,7 +20,7 @@ extern "C" { #endif -/* This LL is currently unused for ESP32-C3 - cleanup is TODO ESP32-C3 IDF-2375 */ +/* This LL is currently unused for ESP32-H2 - IDF-2375 */ static inline uint32_t mpu_ll_id_to_addr(unsigned id) { diff --git a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h index 72385568a4..48fa2a4e6e 100644 --- a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h @@ -49,17 +49,12 @@ static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void) static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) { - /* write memory address to register */ - REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_LINK_ADDR, (uint32_t)addr); - /* Enable clock */ - REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); - /* Enable retention when cpu sleep enable */ - REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); + // ESP32H2-TODO: IDF-3383 } static inline void rtc_cntl_ll_disable_cpu_retention(void) { - REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); + // ESP32H2-TODO: IDF-3383 } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 6719905e09..f2bedc8e54 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -27,7 +27,7 @@ #include "hal/hal_defs.h" #include "esp_types.h" #include "soc/spi_periph.h" -#include "esp32c3/rom/lldesc.h" +#include "esp32h2/rom/lldesc.h" #include "esp_attr.h" #ifdef __cplusplus @@ -220,7 +220,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw) /** * Reset SPI CPU TX FIFO * - * On ESP32C3, this function is not seperated + * On ESP32H2, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ @@ -233,7 +233,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) /** * Reset SPI CPU RX FIFO * - * On ESP32C3, this function is not seperated + * On ESP32H2, this function is not seperated * * @param hw Beginning address of the peripheral registers. */ diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h index 7641c3d723..14613abe02 100644 --- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h @@ -126,7 +126,7 @@ static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev) } /** - * Initialize auto suspend mode, and esp32c3 doesn't support disable auto-suspend. + * Initialize auto suspend mode, and esp32h2 doesn't support disable auto-suspend. * * @param dev Beginning address of the peripheral registers. * @param auto_sus Enable/disable Flash Auto-Suspend. diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h index f3880b9a59..b08b2f1fc7 100644 --- a/components/hal/esp32h2/include/hal/timer_ll.h +++ b/components/hal/esp32h2/include/hal/timer_ll.h @@ -362,7 +362,7 @@ static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t tim */ static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en) { - // edge interrupt is not supported on C3 + // edge interrupt is not supported on H2 } /** @@ -377,7 +377,7 @@ static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t time */ static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num) { - // edge interrupt is not supported on C3 + // edge interrupt is not supported on H2 return false; } diff --git a/components/hal/esp32h2/include/hal/twai_ll.h b/components/hal/esp32h2/include/hal/twai_ll.h index 6c9ae1b9fd..ed6fbc5795 100644 --- a/components/hal/esp32h2/include/hal/twai_ll.h +++ b/components/hal/esp32h2/include/hal/twai_ll.h @@ -347,7 +347,7 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask) * @param triple_sampling Triple Sampling enable/disable * * @note Must be called in reset mode - * @note ESP32C3 brp can be any even number between 2 to 32768 + * @note ESP32H2 brp can be any even number between 2 to 32768 */ static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling) { diff --git a/components/hal/esp32h2/include/hal/uhci_types.h b/components/hal/esp32h2/include/hal/uhci_types.h index 7b7f41d0f9..9cfff67fbb 100644 --- a/components/hal/esp32h2/include/hal/uhci_types.h +++ b/components/hal/esp32h2/include/hal/uhci_types.h @@ -15,7 +15,7 @@ // Though the UHCI driver hasn't been published, some types are defined here -// for users to develop over the HAL. See example: controller_hci_uart_esp32c3 +// for users to develop over the HAL. See example: controller_hci_uart_esp32h2 #pragma once diff --git a/components/hal/esp32h2/rtc_cntl_hal.c b/components/hal/esp32h2/rtc_cntl_hal.c index aae2bfaed8..e88fe73734 100644 --- a/components/hal/esp32h2/rtc_cntl_hal.c +++ b/components/hal/esp32h2/rtc_cntl_hal.c @@ -16,7 +16,7 @@ #include "hal/rtc_hal.h" #include "soc/soc_caps.h" -#include "esp32c3/rom/lldesc.h" +#include "esp32h2/rom/lldesc.h" #include "esp_attr.h" #define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h index 06f2e6247a..1c1a399a4d 100644 --- a/components/hal/include/hal/adc_hal.h +++ b/components/hal/include/hal/adc_hal.h @@ -5,7 +5,7 @@ #include "hal/adc_ll.h" #include "esp_err.h" -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 #include "soc/gdma_struct.h" #include "hal/gdma_ll.h" #include "hal/dma_types.h" @@ -75,7 +75,7 @@ void adc_hal_init(void); */ #define adc_hal_digi_set_clk_div(div) adc_ll_digi_set_clk_div(div) -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`. * @@ -94,7 +94,7 @@ void adc_hal_init(void); * @prarm ctrl ADC controller. */ #define adc_hal_set_controller(adc_n, ctrl) adc_ll_set_controller(adc_n, ctrl) -#endif //#if !CONFIG_IDF_TARGET_ESP32C3 +#endif //#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 /** @@ -137,7 +137,7 @@ void adc_hal_init(void); /*--------------------------------------------------------------- RTC controller setting ---------------------------------------------------------------*/ -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * Set adc output data format for RTC controller. * @@ -152,7 +152,7 @@ void adc_hal_init(void); * @prarm adc_n ADC unit. */ #define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en) -#endif //#if !CONFIG_IDF_TARGET_ESP32C3 +#endif //#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels. @@ -193,7 +193,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg); /*--------------------------------------------------------------- ADC Single Read ---------------------------------------------------------------*/ -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 /** * Set the attenuation of a particular channel on ADCn. * @@ -229,7 +229,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg); */ #define adc_hal_set_atten(adc_n, channel, atten) adc_ll_set_atten(adc_n, channel, atten) -#else // CONFIG_IDF_TARGET_ESP32C3 +#else // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /** * Set the attenuation for ADC to single read * @@ -261,7 +261,7 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw); ADC calibration setting ---------------------------------------------------------------*/ #if SOC_ADC_HW_CALIBRATION_V1 -// ESP32-S2 and C3 support HW offset calibration. +// ESP32-S2, C3 and H2 support HW offset calibration. /** * @brief Initialize default parameter for the calibration block. @@ -298,7 +298,7 @@ uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc #endif //SOC_ADC_HW_CALIBRATION_V1 -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /*--------------------------------------------------------------- DMA setting ---------------------------------------------------------------*/ @@ -380,4 +380,4 @@ void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask); */ void adc_hal_digi_stop(adc_hal_context_t *hal); -#endif //#if CONFIG_IDF_TARGET_ESP32C3 +#endif //#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index b70d0948b3..bf71cb43a8 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -136,7 +136,7 @@ typedef struct { #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 uint8_t reserved: 2; /*!< reserved0 */ uint8_t channel: 4; /*!< ADC channel index. */ -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 uint8_t channel: 3; /*!< ADC channel index. */ uint8_t unit: 1; /*!< ADC unit index. */ uint8_t reserved: 2; /*!< reserved0 */ @@ -184,7 +184,7 @@ typedef struct { }; } adc_digi_output_data_t; #endif -#if CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 /** * @brief ADC digital controller (DMA mode) output data format. * Used to analyze the acquired ADC (DMA) data. @@ -269,7 +269,7 @@ typedef struct { adc_digi_pattern_table_t *adc2_pattern; /*! threshold, Generates monitor interrupt. */ @@ -430,7 +430,7 @@ typedef struct { adc_channel_t channel; /*! -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 #include "soc/soc_caps.h" #include "hal/rtc_io_ll.h" #endif diff --git a/components/hal/include/hal/sha_types.h b/components/hal/include/hal/sha_types.h index 3b8807fa80..275ca60c63 100644 --- a/components/hal/include/hal/sha_types.h +++ b/components/hal/include/hal/sha_types.h @@ -29,6 +29,9 @@ typedef SHA_TYPE esp_sha_type; #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/sha.h" typedef SHA_TYPE esp_sha_type; +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/sha.h" +typedef SHA_TYPE esp_sha_type; #endif #ifdef __cplusplus diff --git a/components/hal/linker.lf b/components/hal/linker.lf index 48bd7a958f..0a4033a942 100644 --- a/components/hal/linker.lf +++ b/components/hal/linker.lf @@ -14,7 +14,7 @@ entries: cpu_hal (noflash) soc_hal (noflash) wdt_hal_iram (noflash) - if IDF_TARGET_ESP32C3 = n: + if IDF_TARGET_ESP32C3 = n && IDF_TARGET_ESP32H2 = n: if TWAI_ISR_IN_IRAM = y: twai_hal_iram (noflash) else: diff --git a/components/hal/spi_flash_hal_iram.c b/components/hal/spi_flash_hal_iram.c index 2fd5ea8a66..c532a1ba37 100644 --- a/components/hal/spi_flash_hal_iram.c +++ b/components/hal/spi_flash_hal_iram.c @@ -27,7 +27,7 @@ void spi_flash_hal_setup_auto_resume_mode(spi_flash_host_inst_t *host); // HAL for // - MEMSPI -// - SPI1~3 on ESP32/S2/S3/C3 +// - SPI1~3 on ESP32/S2/S3/C3/H2 // The common part is in spi_flash_hal_common.inc void spi_flash_hal_erase_chip(spi_flash_host_inst_t *host) diff --git a/components/hal/wdt_hal_iram.c b/components/hal/wdt_hal_iram.c index 1ef7d0e4b7..35939a553f 100644 --- a/components/hal/wdt_hal_iram.c +++ b/components/hal/wdt_hal_iram.c @@ -69,7 +69,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale mwdt_ll_disable_stage(hal->mwdt_dev, 1); mwdt_ll_disable_stage(hal->mwdt_dev, 2); mwdt_ll_disable_stage(hal->mwdt_dev, 3); -#if !CONFIG_IDF_TARGET_ESP32C3 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 //Enable or disable level interrupt. Edge interrupt is always disabled. mwdt_ll_set_edge_intr(hal->mwdt_dev, false); mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr); diff --git a/components/soc/esp32h2/gpio_periph.c b/components/soc/esp32h2/gpio_periph.c index e72f7e20a7..130b7d6abd 100644 --- a/components/soc/esp32h2/gpio_periph.c +++ b/components/soc/esp32h2/gpio_periph.c @@ -37,6 +37,25 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { IO_MUX_GPIO19_REG, IO_MUX_GPIO20_REG, IO_MUX_GPIO21_REG, + IO_MUX_GPIO22_REG, + IO_MUX_GPIO23_REG, + IO_MUX_GPIO24_REG, + IO_MUX_GPIO25_REG, + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG, + IO_MUX_GPIO28_REG, + IO_MUX_GPIO29_REG, + IO_MUX_GPIO30_REG, + IO_MUX_GPIO31_REG, + IO_MUX_GPIO32_REG, + IO_MUX_GPIO33_REG, + IO_MUX_GPIO34_REG, + IO_MUX_GPIO35_REG, + IO_MUX_GPIO36_REG, + IO_MUX_GPIO37_REG, + IO_MUX_GPIO38_REG, + IO_MUX_GPIO39_REG, + IO_MUX_GPIO40_REG, }; const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { diff --git a/components/soc/esp32h2/i2s_periph.c b/components/soc/esp32h2/i2s_periph.c index b20ff7fbf8..0f6705e007 100644 --- a/components/soc/esp32h2/i2s_periph.c +++ b/components/soc/esp32h2/i2s_periph.c @@ -20,7 +20,7 @@ */ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { { - // TODO ESP32-C3 IDF-2098 + // TODO ESP32-H2 IDF-2098 // .o_bck_in_sig = I2S0O_BCK_IN_IDX, // .o_ws_in_sig = I2S0O_WS_IN_IDX, diff --git a/components/soc/esp32h2/include/soc/apb_ctrl_reg.h b/components/soc/esp32h2/include/soc/apb_ctrl_reg.h index 055b919b08..584be8ecfb 100644 --- a/components/soc/esp32h2/include/soc/apb_ctrl_reg.h +++ b/components/soc/esp32h2/include/soc/apb_ctrl_reg.h @@ -19,120 +19,6 @@ extern "C" { #endif #include "soc.h" -#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000) -/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_RST_TICK_CNT (BIT(12)) -#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) -#define APB_CTRL_RST_TICK_CNT_V 0x1 -#define APB_CTRL_RST_TICK_CNT_S 12 -/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_CLK_EN (BIT(11)) -#define APB_CTRL_CLK_EN_M (BIT(11)) -#define APB_CTRL_CLK_EN_V 0x1 -#define APB_CTRL_CLK_EN_S 11 -/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_CLK_320M_EN (BIT(10)) -#define APB_CTRL_CLK_320M_EN_M (BIT(10)) -#define APB_CTRL_CLK_320M_EN_V 0x1 -#define APB_CTRL_CLK_320M_EN_S 10 -/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: */ -#define APB_CTRL_PRE_DIV_CNT 0x000003FF -#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) -#define APB_CTRL_PRE_DIV_CNT_V 0x3FF -#define APB_CTRL_PRE_DIV_CNT_S 0 - -#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004) -/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: */ -#define APB_CTRL_TICK_ENABLE (BIT(16)) -#define APB_CTRL_TICK_ENABLE_M (BIT(16)) -#define APB_CTRL_TICK_ENABLE_V 0x1 -#define APB_CTRL_TICK_ENABLE_S 16 -/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ -/*description: */ -#define APB_CTRL_CK8M_TICK_NUM 0x000000FF -#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) -#define APB_CTRL_CK8M_TICK_NUM_V 0xFF -#define APB_CTRL_CK8M_TICK_NUM_S 8 -/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ -/*description: */ -#define APB_CTRL_XTAL_TICK_NUM 0x000000FF -#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) -#define APB_CTRL_XTAL_TICK_NUM_V 0xFF -#define APB_CTRL_XTAL_TICK_NUM_S 0 - -#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008) -/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) -#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) -#define APB_CTRL_CLK_XTAL_OEN_V 0x1 -#define APB_CTRL_CLK_XTAL_OEN_S 10 -/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) -#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) -#define APB_CTRL_CLK40X_BB_OEN_V 0x1 -#define APB_CTRL_CLK40X_BB_OEN_S 9 -/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) -#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) -#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 -#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 -/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) -#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) -#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 -#define APB_CTRL_CLK_ADC_INF_OEN_S 7 -/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_320M_OEN (BIT(6)) -#define APB_CTRL_CLK_320M_OEN_M (BIT(6)) -#define APB_CTRL_CLK_320M_OEN_V 0x1 -#define APB_CTRL_CLK_320M_OEN_S 6 -/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK160_OEN (BIT(5)) -#define APB_CTRL_CLK160_OEN_M (BIT(5)) -#define APB_CTRL_CLK160_OEN_V 0x1 -#define APB_CTRL_CLK160_OEN_S 5 -/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK80_OEN (BIT(4)) -#define APB_CTRL_CLK80_OEN_M (BIT(4)) -#define APB_CTRL_CLK80_OEN_V 0x1 -#define APB_CTRL_CLK80_OEN_S 4 -/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK_BB_OEN (BIT(3)) -#define APB_CTRL_CLK_BB_OEN_M (BIT(3)) -#define APB_CTRL_CLK_BB_OEN_V 0x1 -#define APB_CTRL_CLK_BB_OEN_S 3 -/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK44_OEN (BIT(2)) -#define APB_CTRL_CLK44_OEN_M (BIT(2)) -#define APB_CTRL_CLK44_OEN_V 0x1 -#define APB_CTRL_CLK44_OEN_S 2 -/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK22_OEN (BIT(1)) -#define APB_CTRL_CLK22_OEN_M (BIT(1)) -#define APB_CTRL_CLK22_OEN_V 0x1 -#define APB_CTRL_CLK22_OEN_S 1 -/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_CLK20_OEN (BIT(0)) -#define APB_CTRL_CLK20_OEN_M (BIT(0)) -#define APB_CTRL_CLK20_OEN_V 0x1 -#define APB_CTRL_CLK20_OEN_S 0 - #define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C) /* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ @@ -149,22 +35,6 @@ extern "C" { #define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF #define APB_CTRL_WIFI_BB_CFG_2_S 0 -#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014) -/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ -/*description: */ -#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF -#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S)) -#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF -#define APB_CTRL_WIFI_CLK_EN_S 0 - -#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018) -/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_WIFI_RST 0xFFFFFFFF -#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S)) -#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF -#define APB_CTRL_WIFI_RST_S 0 - #define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C) /* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ @@ -386,12 +256,6 @@ extern "C" { #define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27)) #define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1 #define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27 -/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ -/*description: */ -#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF -#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S)) -#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF -#define APB_CTRL_RETENTION_LINK_ADDR_S 0 #define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0x0A4) /* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ @@ -480,30 +344,68 @@ extern "C" { #define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S)) #define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F #define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4 -/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ +/* APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ -#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003 +#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE (BIT(3)) +#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3)) +#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_V 0x1 +#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_S 3 +/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000007 #define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S)) -#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3 -#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1 +#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x7 +#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 0 #define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B8) -/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/* APB_CTRL_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ /*description: */ -#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF -#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S)) -#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF -#define APB_CTRL_BACKUP_APB_START_ADDR_S 0 +#define APB_CTRL_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_M ((APB_CTRL_PERI_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_APB_START_ADDR_S)) +#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_S 0 #define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC) -/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/* APB_CTRL_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ /*description: */ -#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF -#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S)) -#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF -#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0 +#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_M ((APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S)) +#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S 0 -#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0C0) +#define APB_CTRL_PERI_BACKUP_MAP0_REG (DR_REG_APB_CTRL_BASE + 0x0C0) +/* APB_CTRL_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_MAP0 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP0_M ((APB_CTRL_PERI_BACKUP_MAP0_V)<<(APB_CTRL_PERI_BACKUP_MAP0_S)) +#define APB_CTRL_PERI_BACKUP_MAP0_V 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP0_S 0 + +#define APB_CTRL_PERI_BACKUP_MAP1_REG (DR_REG_APB_CTRL_BASE + 0x0C4) +/* APB_CTRL_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_MAP1 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP1_M ((APB_CTRL_PERI_BACKUP_MAP1_V)<<(APB_CTRL_PERI_BACKUP_MAP1_S)) +#define APB_CTRL_PERI_BACKUP_MAP1_V 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP1_S 0 + +#define APB_CTRL_PERI_BACKUP_MAP2_REG (DR_REG_APB_CTRL_BASE + 0x0C8) +/* APB_CTRL_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_MAP2 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP2_M ((APB_CTRL_PERI_BACKUP_MAP2_V)<<(APB_CTRL_PERI_BACKUP_MAP2_S)) +#define APB_CTRL_PERI_BACKUP_MAP2_V 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP2_S 0 + +#define APB_CTRL_PERI_BACKUP_MAP3_REG (DR_REG_APB_CTRL_BASE + 0x0CC) +/* APB_CTRL_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_CTRL_PERI_BACKUP_MAP3 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP3_M ((APB_CTRL_PERI_BACKUP_MAP3_V)<<(APB_CTRL_PERI_BACKUP_MAP3_S)) +#define APB_CTRL_PERI_BACKUP_MAP3_V 0xFFFFFFFF +#define APB_CTRL_PERI_BACKUP_MAP3_S 0 + +#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0D0) /* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1)) @@ -517,7 +419,7 @@ extern "C" { #define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1 #define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0 -#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0C4) +#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0D4) /* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1)) @@ -531,7 +433,7 @@ extern "C" { #define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1 #define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0 -#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0C8) +#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0D8) /* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1)) @@ -545,7 +447,7 @@ extern "C" { #define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1 #define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0 -#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0D0) +#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0DC) /* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1)) @@ -559,8 +461,16 @@ extern "C" { #define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1 #define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0 +#define APB_CTRL_CLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0E0) +/* APB_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(0)) +#define APB_CTRL_CLK_EN_M (BIT(0)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 0 + #define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) -/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */ +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */ /*description: Version control*/ #define APB_CTRL_DATE 0xFFFFFFFF #define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) diff --git a/components/soc/esp32h2/include/soc/apb_ctrl_struct.h b/components/soc/esp32h2/include/soc/apb_ctrl_struct.h index 9b832df8dd..53edfec0dd 100644 --- a/components/soc/esp32h2/include/soc/apb_ctrl_struct.h +++ b/components/soc/esp32h2/include/soc/apb_ctrl_struct.h @@ -18,46 +18,13 @@ extern "C" { #endif typedef volatile struct { - union { - struct { - uint32_t pre_div: 10; - uint32_t clk_320m_en: 1; - uint32_t clk_en: 1; - uint32_t rst_tick: 1; - uint32_t reserved13: 19; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t xtal_tick: 8; - uint32_t ck8m_tick: 8; - uint32_t tick_enable: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } tick_conf; - union { - struct { - uint32_t clk20_oen: 1; - uint32_t clk22_oen: 1; - uint32_t clk44_oen: 1; - uint32_t clk_bb_oen: 1; - uint32_t clk80_oen: 1; - uint32_t clk160_oen: 1; - uint32_t clk_320m_oen: 1; - uint32_t clk_adc_inf_oen: 1; - uint32_t clk_dac_cpu_oen: 1; - uint32_t clk40x_bb_oen: 1; - uint32_t clk_xtal_oen: 1; - uint32_t reserved11: 21; - }; - uint32_t val; - } clk_out_en; - uint32_t wifi_bb_cfg; /**/ - uint32_t wifi_bb_cfg_2; /**/ - uint32_t wifi_clk_en; /**/ - uint32_t wifi_rst_en; /**/ + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t reserved_14; + uint32_t reserved_18; union { struct { uint32_t peri_io_swap: 8; @@ -101,10 +68,10 @@ typedef volatile struct { }; uint32_t val; } flash_ace3_attr; - uint32_t flash_ace0_addr; /**/ - uint32_t flash_ace1_addr; /**/ - uint32_t flash_ace2_addr; /**/ - uint32_t flash_ace3_addr; /**/ + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ union { struct { uint32_t flash_ace0_size:13; @@ -154,7 +121,7 @@ typedef volatile struct { }; uint32_t val; } spi_mem_pms_ctrl; - uint32_t spi_mem_reject_addr; /**/ + uint32_t spi_mem_reject_addr; /**/ union { struct { uint32_t sdio_win_access_en: 1; @@ -190,7 +157,7 @@ typedef volatile struct { } front_end_mem_pd; union { struct { - uint32_t retention_link_addr: 27; + uint32_t reserved0: 27; uint32_t nobypass_cpu_iso_rst: 1; uint32_t reserved28: 4; }; @@ -220,23 +187,26 @@ typedef volatile struct { }; uint32_t val; } mem_power_up; - uint32_t rnd_data; /**/ + uint32_t rnd_data; /**/ union { struct { - uint32_t reserved0: 1; - uint32_t peri_backup_flow_err: 2; - uint32_t reserved3: 1; - uint32_t peri_backup_burst_limit: 5; - uint32_t peri_backup_tout_thres: 10; - uint32_t peri_backup_size: 10; - uint32_t peri_backup_start: 1; - uint32_t peri_backup_to_mem: 1; - uint32_t peri_backup_ena: 1; + uint32_t peri_backup_flow_err: 3; + uint32_t peri_backup_addr_map_mode: 1; + uint32_t peri_backup_burst_limit: 5; + uint32_t peri_backup_tout_thres: 10; + uint32_t peri_backup_size: 10; + uint32_t peri_backup_start: 1; + uint32_t peri_backup_to_mem: 1; + uint32_t peri_backup_ena: 1; }; uint32_t val; } peri_backup_config; - uint32_t peri_backup_addr; /**/ - uint32_t peri_backup_mem_addr; /**/ + uint32_t peri_backup_addr; /**/ + uint32_t peri_backup_mem_addr; /**/ + uint32_t peri_backup_map0; /**/ + uint32_t peri_backup_map1; /**/ + uint32_t peri_backup_map2; /**/ + uint32_t peri_backup_map3; /**/ union { struct { uint32_t peri_backup_done: 1; @@ -261,7 +231,6 @@ typedef volatile struct { }; uint32_t val; } peri_backup_int_ena; - uint32_t reserved_cc; union { struct { uint32_t peri_backup_done: 1; @@ -270,10 +239,13 @@ typedef volatile struct { }; uint32_t val; } peri_backup_int_clr; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } ctrlclk_conf; uint32_t reserved_e4; uint32_t reserved_e8; uint32_t reserved_ec; @@ -472,7 +444,7 @@ typedef volatile struct { uint32_t reserved_3f0; uint32_t reserved_3f4; uint32_t reserved_3f8; - uint32_t date; /*Version control*/ + uint32_t date; /*Version control*/ } apb_ctrl_dev_t; extern apb_ctrl_dev_t APB_CTRL; #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/apb_saradc_reg.h b/components/soc/esp32h2/include/soc/apb_saradc_reg.h index 69785ca84d..526738f7e8 100644 --- a/components/soc/esp32h2/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32h2/include/soc/apb_saradc_reg.h @@ -204,6 +204,12 @@ extern "C" { #define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S)) #define APB_SARADC_ONETIME_ATTEN_V 0x3 #define APB_SARADC_ONETIME_ATTEN_S 23 +/* APB_SARADC_ONETIME_EN_TEST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ONETIME_EN_TEST (BIT(22)) +#define APB_SARADC_ONETIME_EN_TEST_M (BIT(22)) +#define APB_SARADC_ONETIME_EN_TEST_V 0x1 +#define APB_SARADC_ONETIME_EN_TEST_S 22 #define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024) /* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ @@ -344,6 +350,19 @@ extern "C" { #define APB_SARADC_THRES1_EN_M (BIT(30)) #define APB_SARADC_THRES1_EN_V 0x1 #define APB_SARADC_THRES1_EN_S 30 +/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES2_EN (BIT(29)) +#define APB_SARADC_THRES2_EN_M (BIT(29)) +#define APB_SARADC_THRES2_EN_V 0x1 +#define APB_SARADC_THRES2_EN_S 29 +/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES3_EN (BIT(28)) +#define APB_SARADC_THRES3_EN_M (BIT(28)) +#define APB_SARADC_THRES3_EN_V 0x1 +#define APB_SARADC_THRES3_EN_S 28 +/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */ /*description: */ #define APB_SARADC_THRES_ALL_EN (BIT(27)) #define APB_SARADC_THRES_ALL_EN_M (BIT(27)) @@ -615,7 +634,7 @@ extern "C" { #define APB_SARADC_CALI_CFG_S 0 #define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) -/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */ +/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02102260 ; */ /*description: */ #define APB_SARADC_DATE 0xFFFFFFFF #define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S)) diff --git a/components/soc/esp32h2/include/soc/apb_saradc_struct.h b/components/soc/esp32h2/include/soc/apb_saradc_struct.h index c3ea73f150..67242d822d 100644 --- a/components/soc/esp32h2/include/soc/apb_saradc_struct.h +++ b/components/soc/esp32h2/include/soc/apb_saradc_struct.h @@ -76,7 +76,8 @@ typedef volatile struct { } sar_patt_tab[2]; union { struct { - uint32_t reserved0: 23; + uint32_t reserved0: 22; + uint32_t onetime_en_test: 1; uint32_t onetime_atten: 2; uint32_t onetime_channel: 4; uint32_t onetime_start: 1; @@ -148,7 +149,8 @@ typedef volatile struct { struct { uint32_t reserved0: 27; uint32_t thres_all_en: 1; - uint32_t reserved28: 2; + uint32_t thres3_en: 1; + uint32_t thres2_en: 1; uint32_t thres1_en: 1; uint32_t thres0_en: 1; }; diff --git a/components/soc/esp32h2/include/soc/clkrst_reg.h b/components/soc/esp32h2/include/soc/clkrst_reg.h new file mode 100644 index 0000000000..d73b4ab228 --- /dev/null +++ b/components/soc/esp32h2/include/soc/clkrst_reg.h @@ -0,0 +1,1056 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_CLKRST_REG_H_ +#define _SOC_CLKRST_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0000) +/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h3 ; */ +/*description: */ +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 16 +/* SYSTEM_SPLL_FREQ : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define SYSTEM_SPLL_FREQ 0x000000FF +#define SYSTEM_SPLL_FREQ_M ((SYSTEM_SPLL_FREQ_V)<<(SYSTEM_SPLL_FREQ_S)) +#define SYSTEM_SPLL_FREQ_V 0xFF +#define SYSTEM_SPLL_FREQ_S 8 +/* SYSTEM_XTAL_FREQ : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SYSTEM_CLK_XTAL_FREQ 0x000000FF +#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_XTAL_FREQ_V)<<(SYSTEM_XTAL_FREQ_S)) +#define SYSTEM_CLK_XTAL_FREQ_V 0xFF +#define SYSTEM_CLK_XTAL_FREQ_S 0 + +#define SYSTEM_CPUCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0004) +/* SYSTEM_CPU_DIV_DENOMINATOR : R/W ;bitpos:[21:16] ;default: 6'h0 ; */ +/*description: */ +#define SYSTEM_CPU_DIV_DENOMINATOR 0x0000003F +#define SYSTEM_CPU_DIV_DENOMINATOR_M ((SYSTEM_CPU_DIV_DENOMINATOR_V)<<(SYSTEM_CPU_DIV_DENOMINATOR_S)) +#define SYSTEM_CPU_DIV_DENOMINATOR_V 0x3F +#define SYSTEM_CPU_DIV_DENOMINATOR_S 16 +/* SYSTEM_CPU_DIV_NUMERATOR : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ +/*description: */ +#define SYSTEM_CPU_DIV_NUMERATOR 0x0000003F +#define SYSTEM_CPU_DIV_NUMERATOR_M ((SYSTEM_CPU_DIV_NUMERATOR_V)<<(SYSTEM_CPU_DIV_NUMERATOR_S)) +#define SYSTEM_CPU_DIV_NUMERATOR_V 0x3F +#define SYSTEM_CPU_DIV_NUMERATOR_S 8 +/* SYSTEM_CPU_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SYSTEM_CPU_DIV_NUM 0x000000FF +#define SYSTEM_CPU_DIV_NUM_M ((SYSTEM_CPU_DIV_NUM_V)<<(SYSTEM_CPU_DIV_NUM_S)) +#define SYSTEM_CPU_DIV_NUM_V 0xFF +#define SYSTEM_CPU_DIV_NUM_S 0 + +#define SYSTEM_PRE_DIV_CNT SYSTEM_CPU_DIV_NUM +#define SYSTEM_PRE_DIV_CNT_M SYSTEM_CPU_DIV_NUM_M +#define SYSTEM_PRE_DIV_CNT_V SYSTEM_CPU_DIV_NUM_V +#define SYSTEM_PRE_DIV_CNT_S SYSTEM_CPU_DIV_NUM_S + +#define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0008) +/* SYSTEM_AHB_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define SYSTEM_AHB_DIV_NUM 0x000000FF +#define SYSTEM_AHB_DIV_NUM_M ((SYSTEM_AHB_DIV_NUM_V)<<(SYSTEM_AHB_DIV_NUM_S)) +#define SYSTEM_AHB_DIV_NUM_V 0xFF +#define SYSTEM_AHB_DIV_NUM_S 8 +/* SYSTEM_APB_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SYSTEM_APB_DIV_NUM 0x000000FF +#define SYSTEM_APB_DIV_NUM_M ((SYSTEM_APB_DIV_NUM_V)<<(SYSTEM_APB_DIV_NUM_S)) +#define SYSTEM_APB_DIV_NUM_V 0xFF +#define SYSTEM_APB_DIV_NUM_S 0 + +#define SYSTEM_MODCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x000C) +/* SYSTEM_MODEM_CLK_SEL : R/W ;bitpos:[1:0] ;default: 1'h1 ; */ +/*description: */ +#define SYSTEM_MODEM_CLK_SEL 0x00000003 +#define SYSTEM_MODEM_CLK_SEL_M ((SYSTEM_MODEM_CLK_SEL_V)<<(SYSTEM_MODEM_CLK_SEL_S)) +#define SYSTEM_MODEM_CLK_SEL_V 0x3 +#define SYSTEM_MODEM_CLK_SEL_S 0 + +#define SYSTEM_CLK_OUT_EN_REG (DR_REG_CLKRST_BASE + 0x0010) +/* SYSTEM_CLK_RFADC_OEN : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_RFADC_OEN (BIT(12)) +#define SYSTEM_CLK_RFADC_OEN_M (BIT(12)) +#define SYSTEM_CLK_RFADC_OEN_V 0x1 +#define SYSTEM_CLK_RFADC_OEN_S 12 +/* SYSTEM_CLK_RFDAC_OEN : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_RFDAC_OEN (BIT(11)) +#define SYSTEM_CLK_RFDAC_OEN_M (BIT(11)) +#define SYSTEM_CLK_RFDAC_OEN_V 0x1 +#define SYSTEM_CLK_RFDAC_OEN_S 11 +/* SYSTEM_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_XTAL_OEN (BIT(10)) +#define SYSTEM_CLK_XTAL_OEN_M (BIT(10)) +#define SYSTEM_CLK_XTAL_OEN_V 0x1 +#define SYSTEM_CLK_XTAL_OEN_S 10 +/* SYSTEM_CLK_SPLL_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_SPLL_OEN (BIT(9)) +#define SYSTEM_CLK_SPLL_OEN_M (BIT(9)) +#define SYSTEM_CLK_SPLL_OEN_V 0x1 +#define SYSTEM_CLK_SPLL_OEN_S 9 +/* SYSTEM_CLK_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_CPU_OEN (BIT(8)) +#define SYSTEM_CLK_CPU_OEN_M (BIT(8)) +#define SYSTEM_CLK_CPU_OEN_V 0x1 +#define SYSTEM_CLK_CPU_OEN_S 8 +/* SYSTEM_CLK_AHB_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_AHB_OEN (BIT(7)) +#define SYSTEM_CLK_AHB_OEN_M (BIT(7)) +#define SYSTEM_CLK_AHB_OEN_V 0x1 +#define SYSTEM_CLK_AHB_OEN_S 7 +/* SYSTEM_CLK_APB_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_APB_OEN (BIT(6)) +#define SYSTEM_CLK_APB_OEN_M (BIT(6)) +#define SYSTEM_CLK_APB_OEN_V 0x1 +#define SYSTEM_CLK_APB_OEN_S 6 +/* SYSTEM_CLK_32M_BT_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_32M_BT_OEN (BIT(5)) +#define SYSTEM_CLK_32M_BT_OEN_M (BIT(5)) +#define SYSTEM_CLK_32M_BT_OEN_V 0x1 +#define SYSTEM_CLK_32M_BT_OEN_S 5 +/* SYSTEM_CLK_16M_BT_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_16M_BT_OEN (BIT(4)) +#define SYSTEM_CLK_16M_BT_OEN_M (BIT(4)) +#define SYSTEM_CLK_16M_BT_OEN_V 0x1 +#define SYSTEM_CLK_16M_BT_OEN_S 4 +/* SYSTEM_CLK_8M_BT_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_8M_BT_OEN (BIT(3)) +#define SYSTEM_CLK_8M_BT_OEN_M (BIT(3)) +#define SYSTEM_CLK_8M_BT_OEN_V 0x1 +#define SYSTEM_CLK_8M_BT_OEN_S 3 + +#define SYSTEM_MODEM_CLK_EN_REG (DR_REG_CLKRST_BASE + 0x0014) +/* SYSTEM_DATA_DUMP_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DATA_DUMP_CLK_EN (BIT(21)) +#define SYSTEM_DATA_DUMP_CLK_EN_M (BIT(21)) +#define SYSTEM_DATA_DUMP_CLK_EN_V 0x1 +#define SYSTEM_DATA_DUMP_CLK_EN_S 21 +/* SYSTEM_RFADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RFADC_CLK_EN (BIT(20)) +#define SYSTEM_RFADC_CLK_EN_M (BIT(20)) +#define SYSTEM_RFADC_CLK_EN_V 0x1 +#define SYSTEM_RFADC_CLK_EN_S 20 +/* SYSTEM_RFDAC_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RFDAC_CLK_EN (BIT(19)) +#define SYSTEM_RFDAC_CLK_EN_M (BIT(19)) +#define SYSTEM_RFDAC_CLK_EN_V 0x1 +#define SYSTEM_RFDAC_CLK_EN_S 19 +/* SYSTEM_BTLC_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BTLC_CLK_EN (BIT(18)) +#define SYSTEM_BTLC_CLK_EN_M (BIT(18)) +#define SYSTEM_BTLC_CLK_EN_V 0x1 +#define SYSTEM_BTLC_CLK_EN_S 18 +/* SYSTEM_BLE_SEC_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_CLK_EN (BIT(17)) +#define SYSTEM_BLE_SEC_CLK_EN_M (BIT(17)) +#define SYSTEM_BLE_SEC_CLK_EN_V 0x1 +#define SYSTEM_BLE_SEC_CLK_EN_S 17 +/* SYSTEM_BLE_SEC_AAR_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_AAR_CLK_EN (BIT(16)) +#define SYSTEM_BLE_SEC_AAR_CLK_EN_M (BIT(16)) +#define SYSTEM_BLE_SEC_AAR_CLK_EN_V 0x1 +#define SYSTEM_BLE_SEC_AAR_CLK_EN_S 16 +/* SYSTEM_BLE_SEC_CCM_CLK_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_CCM_CLK_EN (BIT(15)) +#define SYSTEM_BLE_SEC_CCM_CLK_EN_M (BIT(15)) +#define SYSTEM_BLE_SEC_CCM_CLK_EN_V 0x1 +#define SYSTEM_BLE_SEC_CCM_CLK_EN_S 15 +/* SYSTEM_BLE_SEC_ECB_CLK_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_ECB_CLK_EN (BIT(14)) +#define SYSTEM_BLE_SEC_ECB_CLK_EN_M (BIT(14)) +#define SYSTEM_BLE_SEC_ECB_CLK_EN_V 0x1 +#define SYSTEM_BLE_SEC_ECB_CLK_EN_S 14 +/* SYSTEM_IEEE802154MAC_CLK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_IEEE802154MAC_CLK_EN (BIT(13)) +#define SYSTEM_IEEE802154MAC_CLK_EN_M (BIT(13)) +#define SYSTEM_IEEE802154MAC_CLK_EN_V 0x1 +#define SYSTEM_IEEE802154MAC_CLK_EN_S 13 +/* SYSTEM_IEEE802154BB_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_IEEE802154BB_CLK_EN (BIT(12)) +#define SYSTEM_IEEE802154BB_CLK_EN_M (BIT(12)) +#define SYSTEM_IEEE802154BB_CLK_EN_V 0x1 +#define SYSTEM_IEEE802154BB_CLK_EN_S 12 +/* SYSTEM_COEX_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COEX_CLK_EN (BIT(11)) +#define SYSTEM_COEX_CLK_EN_M (BIT(11)) +#define SYSTEM_COEX_CLK_EN_V 0x1 +#define SYSTEM_COEX_CLK_EN_S 11 +/* SYSTEM_I2CMST_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_I2CMST_CLK_EN (BIT(10)) +#define SYSTEM_I2CMST_CLK_EN_M (BIT(10)) +#define SYSTEM_I2CMST_CLK_EN_V 0x1 +#define SYSTEM_I2CMST_CLK_EN_S 10 +/* SYSTEM_I2C_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_I2C_CLK_EN (BIT(9)) +#define SYSTEM_I2C_CLK_EN_M (BIT(9)) +#define SYSTEM_I2C_CLK_EN_V 0x1 +#define SYSTEM_I2C_CLK_EN_S 9 +/* SYSTEM_RW_BTMAC_CLK_EN : R/W ;bitpos:[8] ;default: 2'b0 ; */ +/*description: */ +#define SYSTEM_RW_BTMAC_CLK_EN (BIT(8)) +#define SYSTEM_RW_BTMAC_CLK_EN_M (BIT(8)) +#define SYSTEM_RW_BTMAC_CLK_EN_V 0x1 +#define SYSTEM_RW_BTMAC_CLK_EN_S 8 +/* SYSTEM_MACPWR_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_MACPWR_CLK_EN (BIT(7)) +#define SYSTEM_MACPWR_CLK_EN_M (BIT(7)) +#define SYSTEM_MACPWR_CLK_EN_V 0x1 +#define SYSTEM_MACPWR_CLK_EN_S 7 +/* SYSTEM_EMAC_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EMAC_CLK_EN (BIT(6)) +#define SYSTEM_EMAC_CLK_EN_M (BIT(6)) +#define SYSTEM_EMAC_CLK_EN_V 0x1 +#define SYSTEM_EMAC_CLK_EN_S 6 +/* SYSTEM_SDIO_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SDIO_CLK_EN (BIT(5)) +#define SYSTEM_SDIO_CLK_EN_M (BIT(5)) +#define SYSTEM_SDIO_CLK_EN_V 0x1 +#define SYSTEM_SDIO_CLK_EN_S 5 +/* SYSTEM_BTMAC_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BTMAC_CLK_EN (BIT(4)) +#define SYSTEM_BTMAC_CLK_EN_M (BIT(4)) +#define SYSTEM_BTMAC_CLK_EN_V 0x1 +#define SYSTEM_BTMAC_CLK_EN_S 4 +/* SYSTEM_BT_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BT_CLK_EN (BIT(3)) +#define SYSTEM_BT_CLK_EN_M (BIT(3)) +#define SYSTEM_BT_CLK_EN_V 0x1 +#define SYSTEM_BT_CLK_EN_S 3 +/* SYSTEM_MAC_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MAC_CLK_EN (BIT(2)) +#define SYSTEM_MAC_CLK_EN_M (BIT(2)) +#define SYSTEM_MAC_CLK_EN_V 0x1 +#define SYSTEM_MAC_CLK_EN_S 2 +/* SYSTEM_FE_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_FE_CLK_EN (BIT(1)) +#define SYSTEM_FE_CLK_EN_M (BIT(1)) +#define SYSTEM_FE_CLK_EN_V 0x1 +#define SYSTEM_FE_CLK_EN_S 1 +/* SYSTEM_FE_CAL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_FE_CAL_CLK_EN (BIT(0)) +#define SYSTEM_FE_CAL_CLK_EN_M (BIT(0)) +#define SYSTEM_FE_CAL_CLK_EN_V 0x1 +#define SYSTEM_FE_CAL_CLK_EN_S 0 + +#define SYSTEM_MODEM_RST_EN_REG (DR_REG_CLKRST_BASE + 0x0018) +/* SYSTEM_DATA_DUMP_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DATA_DUMP_RST (BIT(20)) +#define SYSTEM_DATA_DUMP_RST_M (BIT(20)) +#define SYSTEM_DATA_DUMP_RST_V 0x1 +#define SYSTEM_DATA_DUMP_RST_S 20 +/* SYSTEM_APB_RET_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_APB_RET_RST (BIT(19)) +#define SYSTEM_APB_RET_RST_M (BIT(19)) +#define SYSTEM_APB_RET_RST_V 0x1 +#define SYSTEM_APB_RET_RST_S 19 +/* SYSTEM_BLE_SEC_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_RST (BIT(18)) +#define SYSTEM_BLE_SEC_RST_M (BIT(18)) +#define SYSTEM_BLE_SEC_RST_V 0x1 +#define SYSTEM_BLE_SEC_RST_S 18 +/* SYSTEM_BLE_SEC_AAR_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_AAR_RST (BIT(17)) +#define SYSTEM_BLE_SEC_AAR_RST_M (BIT(17)) +#define SYSTEM_BLE_SEC_AAR_RST_V 0x1 +#define SYSTEM_BLE_SEC_AAR_RST_S 17 +/* SYSTEM_BLE_SEC_CCM_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_CCM_RST (BIT(16)) +#define SYSTEM_BLE_SEC_CCM_RST_M (BIT(16)) +#define SYSTEM_BLE_SEC_CCM_RST_V 0x1 +#define SYSTEM_BLE_SEC_CCM_RST_S 16 +/* SYSTEM_BLE_SEC_ECB_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BLE_SEC_ECB_RST (BIT(15)) +#define SYSTEM_BLE_SEC_ECB_RST_M (BIT(15)) +#define SYSTEM_BLE_SEC_ECB_RST_V 0x1 +#define SYSTEM_BLE_SEC_ECB_RST_S 15 +/* SYSTEM_IEEE802154MAC_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_IEEE802154MAC_RST (BIT(14)) +#define SYSTEM_IEEE802154MAC_RST_M (BIT(14)) +#define SYSTEM_IEEE802154MAC_RST_V 0x1 +#define SYSTEM_IEEE802154MAC_RST_S 14 +/* SYSTEM_IEEE802154BB_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_IEEE802154BB_RST (BIT(13)) +#define SYSTEM_IEEE802154BB_RST_M (BIT(13)) +#define SYSTEM_IEEE802154BB_RST_V 0x1 +#define SYSTEM_IEEE802154BB_RST_S 13 +/* SYSTEM_COEX_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COEX_RST (BIT(12)) +#define SYSTEM_COEX_RST_M (BIT(12)) +#define SYSTEM_COEX_RST_V 0x1 +#define SYSTEM_COEX_RST_S 12 +/* SYSTEM_BT_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BT_REG_RST (BIT(11)) +#define SYSTEM_BT_REG_RST_M (BIT(11)) +#define SYSTEM_BT_REG_RST_V 0x1 +#define SYSTEM_BT_REG_RST_S 11 +/* SYSTEM_RW_BTLPRST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RW_BTLPRST (BIT(10)) +#define SYSTEM_RW_BTLPRST_M (BIT(10)) +#define SYSTEM_RW_BTLPRST_V 0x1 +#define SYSTEM_RW_BTLPRST_S 10 +/* SYSTEM_RW_BTRST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RW_BTRST (BIT(9)) +#define SYSTEM_RW_BTRST_M (BIT(9)) +#define SYSTEM_RW_BTRST_V 0x1 +#define SYSTEM_RW_BTRST_S 9 +/* SYSTEM_RW_BTLP_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RW_BTLP_RST (BIT(8)) +#define SYSTEM_RW_BTLP_RST_M (BIT(8)) +#define SYSTEM_RW_BTLP_RST_V 0x1 +#define SYSTEM_RW_BTLP_RST_S 8 +/* SYSTEM_RW_BTMAC_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RW_BTMAC_RST (BIT(7)) +#define SYSTEM_RW_BTMAC_RST_M (BIT(7)) +#define SYSTEM_RW_BTMAC_RST_V 0x1 +#define SYSTEM_RW_BTMAC_RST_S 7 +/* SYSTEM_MACPWR_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MACPWR_RST (BIT(6)) +#define SYSTEM_MACPWR_RST_M (BIT(6)) +#define SYSTEM_MACPWR_RST_V 0x1 +#define SYSTEM_MACPWR_RST_S 6 +/* SYSTEM_EMAC_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EMAC_RST (BIT(5)) +#define SYSTEM_EMAC_RST_M (BIT(5)) +#define SYSTEM_EMAC_RST_V 0x1 +#define SYSTEM_EMAC_RST_S 5 +/* SYSTEM_SDIO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SDIO_RST (BIT(4)) +#define SYSTEM_SDIO_RST_M (BIT(4)) +#define SYSTEM_SDIO_RST_V 0x1 +#define SYSTEM_SDIO_RST_S 4 +/* SYSTEM_BTMAC_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BTMAC_RST (BIT(3)) +#define SYSTEM_BTMAC_RST_M (BIT(3)) +#define SYSTEM_BTMAC_RST_V 0x1 +#define SYSTEM_BTMAC_RST_S 3 +/* SYSTEM_BT_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_BT_RST (BIT(2)) +#define SYSTEM_BT_RST_M (BIT(2)) +#define SYSTEM_BT_RST_V 0x1 +#define SYSTEM_BT_RST_S 2 +/* SYSTEM_MAC_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MAC_RST (BIT(1)) +#define SYSTEM_MAC_RST_M (BIT(1)) +#define SYSTEM_MAC_RST_V 0x1 +#define SYSTEM_MAC_RST_S 1 +/* SYSTEM_FE_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_FE_RST (BIT(0)) +#define SYSTEM_FE_RST_M (BIT(0)) +#define SYSTEM_FE_RST_V 0x1 +#define SYSTEM_FE_RST_S 0 + +#define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_CLKRST_BASE + 0x001C) +/* SYSTEM_MSPI_DIV_NUM : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: */ +#define SYSTEM_MSPI_DIV_NUM 0x000000FF +#define SYSTEM_MSPI_DIV_NUM_M ((SYSTEM_MSPI_DIV_NUM_V)<<(SYSTEM_MSPI_DIV_NUM_S)) +#define SYSTEM_MSPI_DIV_NUM_V 0xFF +#define SYSTEM_MSPI_DIV_NUM_S 24 +/* SYSTEM_CAN_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ +/*description: */ +#define SYSTEM_CAN_DIV_NUM 0x000000FF +#define SYSTEM_CAN_DIV_NUM_M ((SYSTEM_CAN_DIV_NUM_V)<<(SYSTEM_CAN_DIV_NUM_S)) +#define SYSTEM_CAN_DIV_NUM_V 0xFF +#define SYSTEM_CAN_DIV_NUM_S 16 +/* SYSTEM_USB_DEVICE_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_DIV_NUM 0x000000FF +#define SYSTEM_USB_DEVICE_DIV_NUM_M ((SYSTEM_USB_DEVICE_DIV_NUM_V)<<(SYSTEM_USB_DEVICE_DIV_NUM_S)) +#define SYSTEM_USB_DEVICE_DIV_NUM_V 0xFF +#define SYSTEM_USB_DEVICE_DIV_NUM_S 8 +/* SYSTEM_SEC_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ +/*description: */ +#define SYSTEM_SEC_DIV_NUM 0x000000FF +#define SYSTEM_SEC_DIV_NUM_M ((SYSTEM_SEC_DIV_NUM_V)<<(SYSTEM_SEC_DIV_NUM_S)) +#define SYSTEM_SEC_DIV_NUM_V 0xFF +#define SYSTEM_SEC_DIV_NUM_S 0 + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_CLKRST_BASE + 0x0020) +/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ +/*description: */ +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 +/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 +/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 +/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 +/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 +/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 +#define SYSTEM_USB_DEVICE_CLK_EN_S 23 +/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 +/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_V 0x1 +#define SYSTEM_I2S1_CLK_EN_S 21 +/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 +/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 +/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 +/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 +/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 +/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 +/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 +/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 +/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 +/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 +/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 +/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 +/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 +/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 4 +/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 +/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 +/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 +/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_CLKRST_BASE + 0x0024) +/* SYSTEM_PVT_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_PVT_CLK_EN (BIT(15)) +#define SYSTEM_PVT_CLK_EN_M (BIT(15)) +#define SYSTEM_PVT_CLK_EN_V 0x1 +#define SYSTEM_PVT_CLK_EN_S 15 +/* SYSTEM_REGRET_CLK_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REGRET_CLK_EN (BIT(14)) +#define SYSTEM_REGRET_CLK_EN_M (BIT(14)) +#define SYSTEM_REGRET_CLK_EN_V 0x1 +#define SYSTEM_REGRET_CLK_EN_S 14 +/* SYSTEM_TIMERGROUP3_CLK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP3_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP3_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP3_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP3_CLK_EN_S 13 +/* SYSTEM_ETM_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ETM_CLK_EN (BIT(12)) +#define SYSTEM_ETM_CLK_EN_M (BIT(12)) +#define SYSTEM_ETM_CLK_EN_V 0x1 +#define SYSTEM_ETM_CLK_EN_S 12 +/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TSENS_CLK_EN (BIT(11)) +#define SYSTEM_TSENS_CLK_EN_M (BIT(11)) +#define SYSTEM_TSENS_CLK_EN_V 0x1 +#define SYSTEM_TSENS_CLK_EN_S 11 +/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART2_CLK_EN (BIT(10)) +#define SYSTEM_UART2_CLK_EN_M (BIT(10)) +#define SYSTEM_UART2_CLK_EN_V 0x1 +#define SYSTEM_UART2_CLK_EN_S 10 +/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_CLK_EN (BIT(9)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(9)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 9 +/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(8)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(8)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 8 +/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DMA_CLK_EN (BIT(7)) +#define SYSTEM_DMA_CLK_EN_M (BIT(7)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 7 +/* SYSTEM_CRYPTO_ECC_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(6)) +#define SYSTEM_CRYPTO_ECC_CLK_EN_M (BIT(6)) +#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_ECC_CLK_EN_S 6 +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 +/* SYSTEM_RETENTION_TOP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RETENTION_TOP_CLK_EN (BIT(0)) +#define SYSTEM_RETENTION_TOP_CLK_EN_M (BIT(0)) +#define SYSTEM_RETENTION_TOP_CLK_EN_V 0x1 +#define SYSTEM_RETENTION_TOP_CLK_EN_S 0 + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_CLKRST_BASE + 0x0028) +/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 +/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 +/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 +/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 +/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 +/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 +/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 +/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 +/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_USB_DEVICE_RST (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_M (BIT(23)) +#define SYSTEM_USB_DEVICE_RST_V 0x1 +#define SYSTEM_USB_DEVICE_RST_S 23 +/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 +/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (BIT(21)) +#define SYSTEM_I2S1_RST_V 0x1 +#define SYSTEM_I2S1_RST_S 21 +/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 +/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 +/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 +/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 +/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 +/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 +/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 +/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 +/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 +/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 +/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 +/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 +/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 +/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 +/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 +/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 +/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (BIT(4)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 4 +/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 +/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 +/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 +/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_CLKRST_BASE + 0x002C) +/* SYSTEM_PVT_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PVT_RST (BIT(15)) +#define SYSTEM_PVT_RST_M (BIT(15)) +#define SYSTEM_PVT_RST_V 0x1 +#define SYSTEM_PVT_RST_S 15 +/* SYSTEM_REGRET_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REGRET_RST (BIT(14)) +#define SYSTEM_REGRET_RST_M (BIT(14)) +#define SYSTEM_REGRET_RST_V 0x1 +#define SYSTEM_REGRET_RST_S 14 +/* SYSTEM_TIMERGROUP3_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP3_RST (BIT(13)) +#define SYSTEM_TIMERGROUP3_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP3_RST_V 0x1 +#define SYSTEM_TIMERGROUP3_RST_S 13 +/* SYSTEM_ETM_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ETM_RST (BIT(12)) +#define SYSTEM_ETM_RST_M (BIT(12)) +#define SYSTEM_ETM_RST_V 0x1 +#define SYSTEM_ETM_RST_S 12 +/* SYSTEM_TSENS_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TSENS_RST (BIT(11)) +#define SYSTEM_TSENS_RST_M (BIT(11)) +#define SYSTEM_TSENS_RST_V 0x1 +#define SYSTEM_TSENS_RST_S 11 +/* SYSTEM_UART2_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART2_RST (BIT(10)) +#define SYSTEM_UART2_RST_M (BIT(10)) +#define SYSTEM_UART2_RST_V 0x1 +#define SYSTEM_UART2_RST_S 10 +/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_RST (BIT(9)) +#define SYSTEM_LCD_CAM_RST_M (BIT(9)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 9 +/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_RST (BIT(8)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(8)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 8 +/* SYSTEM_DMA_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DMA_RST (BIT(7)) +#define SYSTEM_DMA_RST_M (BIT(7)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 7 +/* SYSTEM_CRYPTO_ECC_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_ECC_RST (BIT(6)) +#define SYSTEM_CRYPTO_ECC_RST_M (BIT(6)) +#define SYSTEM_CRYPTO_ECC_RST_V 0x1 +#define SYSTEM_CRYPTO_ECC_RST_S 6 +/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 +/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 +/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 +/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 +/* SYSTEM_RETENTION_TOP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RETENTION_TOP_RST (BIT(0)) +#define SYSTEM_RETENTION_TOP_RST_M (BIT(0)) +#define SYSTEM_RETENTION_TOP_RST_V 0x1 +#define SYSTEM_RETENTION_TOP_RST_S 0 + +#define SYSTEM_FPGA_DBG_REG (DR_REG_CLKRST_BASE + 0x0030) +/* SYSTEM_FPGA_DEBUG : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define SYSTEM_FPGA_DEBUG 0xFFFFFFFF +#define SYSTEM_FPGA_DEBUG_M ((SYSTEM_FPGA_DEBUG_V)<<(SYSTEM_FPGA_DEBUG_S)) +#define SYSTEM_FPGA_DEBUG_V 0xFFFFFFFF +#define SYSTEM_FPGA_DEBUG_S 0 + +#define SYSTEMCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0034) +/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define SYSTEM_CLKRST_DATE_REG (DR_REG_CLKRST_BASE + 0x038) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103191 ; */ +/*description: */ +#define CLKRST_DATE 0x0FFFFFFF +#define CLKRST_DATE_M ((CLKRST_DATE_V)<<(CLKRST_DATE_S)) +#define CLKRST_DATE_V 0xFFFFFFF +#define CLKRST_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_CLKRST_REG_H_ */ + + + diff --git a/components/soc/esp32h2/include/soc/dport_access.h b/components/soc/esp32h2/include/soc/dport_access.h index e6dfa2bec0..d6c6a30911 100644 --- a/components/soc/esp32h2/include/soc/dport_access.h +++ b/components/soc/esp32h2/include/soc/dport_access.h @@ -18,7 +18,7 @@ #include #include "esp_attr.h" #include "esp_attr.h" -#include "esp32c3/dport_access.h" +#include "esp32h2/dport_access.h" #include "soc.h" #include "uart_reg.h" diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/include/soc/efuse_reg.h index ddaff7285c..b7b11b9852 100644 --- a/components/soc/esp32h2/include/soc/efuse_reg.h +++ b/components/soc/esp32h2/include/soc/efuse_reg.h @@ -767,7 +767,7 @@ extern "C" { #define EFUSE_SYS_DATA_PART0_0_V 0xFF #define EFUSE_SYS_DATA_PART0_0_S 25 /* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: Package version 0:ESP32-C3 */ +/*description: Package version 0:ESP32-H2 */ #define EFUSE_PKG_VERSION 0x00000007 #define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) #define EFUSE_PKG_VERSION_V 0x7 diff --git a/components/soc/esp32h2/include/soc/gpio_reg.h b/components/soc/esp32h2/include/soc/gpio_reg.h index a674277f99..56b07a3d8e 100644 --- a/components/soc/esp32h2/include/soc/gpio_reg.h +++ b/components/soc/esp32h2/include/soc/gpio_reg.h @@ -56,29 +56,53 @@ extern "C" { #define GPIO_BT_SEL_S 0 #define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_OUT_DATA 0x03FFFFFF +#define GPIO_OUT_DATA 0xFFFFFFFF #define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) -#define GPIO_OUT_DATA_V 0x3FFFFFF +#define GPIO_OUT_DATA_V 0xFFFFFFFF #define GPIO_OUT_DATA_S 0 #define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_OUT_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_OUT_W1TS 0x03FFFFFF +#define GPIO_OUT_W1TS 0xFFFFFFFF #define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) -#define GPIO_OUT_W1TS_V 0x3FFFFFF +#define GPIO_OUT_W1TS_V 0xFFFFFFFF #define GPIO_OUT_W1TS_S 0 #define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xC) -/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_OUT_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_OUT_W1TC 0x03FFFFFF +#define GPIO_OUT_W1TC 0xFFFFFFFF #define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) -#define GPIO_OUT_W1TC_V 0x3FFFFFF +#define GPIO_OUT_W1TC_V 0xFFFFFFFF #define GPIO_OUT_W1TC_S 0 +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) +/* GPIO_OUT1_DATA : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_OUT1_DATA 0x00001FFF +#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) +#define GPIO_OUT1_DATA_V 0x1FFF +#define GPIO_OUT1_DATA_S 0 + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) +/* GPIO_OUT1_W1TS : WO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_OUT1_W1TS 0x00001FFF +#define GPIO_OUT1_W1TS_M ((GPIO_OUT1_W1TS_V)<<(GPIO_OUT1_W1TS_S)) +#define GPIO_OUT1_W1TS_V 0x1FFF +#define GPIO_OUT1_W1TS_S 0 + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) +/* GPIO_OUT1_W1TC : WO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_OUT1_W1TC 0x00001FFF +#define GPIO_OUT1_W1TC_M ((GPIO_OUT1_W1TC_V)<<(GPIO_OUT1_W1TC_S)) +#define GPIO_OUT1_W1TC_V 0x1FFF +#define GPIO_OUT1_W1TC_S 0 + #define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1C) /* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ @@ -88,29 +112,53 @@ extern "C" { #define GPIO_SDIO_SEL_S 0 #define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) -/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_ENABLE_DATA 0x03FFFFFF +#define GPIO_ENABLE_DATA 0xFFFFFFFF #define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) -#define GPIO_ENABLE_DATA_V 0x3FFFFFF +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF #define GPIO_ENABLE_DATA_S 0 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) -/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_ENABLE_W1TS 0x03FFFFFF +#define GPIO_ENABLE_W1TS 0xFFFFFFFF #define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) -#define GPIO_ENABLE_W1TS_V 0x3FFFFFF +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFF #define GPIO_ENABLE_W1TS_S 0 #define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) -/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_ENABLE_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_ENABLE_W1TC 0x03FFFFFF +#define GPIO_ENABLE_W1TC 0xFFFFFFFF #define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) -#define GPIO_ENABLE_W1TC_V 0x3FFFFFF +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFF #define GPIO_ENABLE_W1TC_S 0 +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2C) +/* GPIO_ENABLE1_DATA : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_ENABLE1_DATA 0x00001FFF +#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) +#define GPIO_ENABLE1_DATA_V 0x1FFF +#define GPIO_ENABLE1_DATA_S 0 + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) +/* GPIO_ENABLE1_W1TS : WO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_ENABLE1_W1TS 0x00001FFF +#define GPIO_ENABLE1_W1TS_M ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S)) +#define GPIO_ENABLE1_W1TS_V 0x1FFF +#define GPIO_ENABLE1_W1TS_S 0 + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) +/* GPIO_ENABLE1_W1TC : WO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_ENABLE1_W1TC 0x00001FFF +#define GPIO_ENABLE1_W1TC_M ((GPIO_ENABLE1_W1TC_V)<<(GPIO_ENABLE1_W1TC_S)) +#define GPIO_ENABLE1_W1TC_V 0x1FFF +#define GPIO_ENABLE1_W1TC_S 0 + #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) /* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ /*description: */ @@ -120,61 +168,117 @@ extern "C" { #define GPIO_STRAPPING_S 0 #define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3C) -/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default: ; */ +/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ /*description: */ -#define GPIO_IN_DATA 0x03FFFFFF +#define GPIO_IN_DATA 0xFFFFFFFF #define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) -#define GPIO_IN_DATA_V 0x3FFFFFF +#define GPIO_IN_DATA_V 0xFFFFFFFF #define GPIO_IN_DATA_S 0 -#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) -/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) +/* GPIO_IN1_DATA : RO ;bitpos:[12:0] ;default: ; */ /*description: */ -#define GPIO_STATUS_INT 0x03FFFFFF +#define GPIO_IN1_DATA 0x00001FFF +#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) +#define GPIO_IN1_DATA_V 0x1FFF +#define GPIO_IN1_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_STATUS_INT 0xFFFFFFFF #define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) -#define GPIO_STATUS_INT_V 0x3FFFFFF +#define GPIO_STATUS_INT_V 0xFFFFFFFF #define GPIO_STATUS_INT_S 0 #define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) -/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_STATUS_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_STATUS_W1TS 0x03FFFFFF +#define GPIO_STATUS_W1TS 0xFFFFFFFF #define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) -#define GPIO_STATUS_W1TS_V 0x3FFFFFF +#define GPIO_STATUS_W1TS_V 0xFFFFFFFF #define GPIO_STATUS_W1TS_S 0 #define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4C) -/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_STATUS_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_STATUS_W1TC 0x03FFFFFF +#define GPIO_STATUS_W1TC 0xFFFFFFFF #define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) -#define GPIO_STATUS_W1TC_V 0x3FFFFFF +#define GPIO_STATUS_W1TC_V 0xFFFFFFFF #define GPIO_STATUS_W1TC_S 0 -#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) -/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) +/* GPIO_STATUS1_INT : R/W ;bitpos:[12:0] ;default: 13'h0 ; */ /*description: */ -#define GPIO_PROCPU_INT 0x03FFFFFF +#define GPIO_STATUS1_INT 0x00001FFF +#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) +#define GPIO_STATUS1_INT_V 0x1FFF +#define GPIO_STATUS1_INT_S 0 + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) +/* GPIO_STATUS1_W1TS : WO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_STATUS1_W1TS 0x00001FFF +#define GPIO_STATUS1_W1TS_M ((GPIO_STATUS1_W1TS_V)<<(GPIO_STATUS1_W1TS_S)) +#define GPIO_STATUS1_W1TS_V 0x1FFF +#define GPIO_STATUS1_W1TS_S 0 + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) +/* GPIO_STATUS1_W1TC : WO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_STATUS1_W1TC 0x00001FFF +#define GPIO_STATUS1_W1TC_M ((GPIO_STATUS1_W1TC_V)<<(GPIO_STATUS1_W1TC_S)) +#define GPIO_STATUS1_W1TC_V 0x1FFF +#define GPIO_STATUS1_W1TC_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) +/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_PROCPU_INT 0xFFFFFFFF #define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) -#define GPIO_PROCPU_INT_V 0x3FFFFFF +#define GPIO_PROCPU_INT_V 0xFFFFFFFF #define GPIO_PROCPU_INT_S 0 #define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) -/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_PROCPU_NMI_INT 0x03FFFFFF +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF #define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) -#define GPIO_PROCPU_NMI_INT_V 0x3FFFFFF +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF #define GPIO_PROCPU_NMI_INT_S 0 #define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) -/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define GPIO_SDIO_INT 0x03FFFFFF +#define GPIO_SDIO_INT 0xFFFFFFFF #define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) -#define GPIO_SDIO_INT_V 0x3FFFFFF +#define GPIO_SDIO_INT_V 0xFFFFFFFF #define GPIO_SDIO_INT_S 0 +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) +/* GPIO_PROCPU_INT_H : RO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_PROCPU_INT_H 0x00001FFF +#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) +#define GPIO_PROCPU_INT_H_V 0x1FFF +#define GPIO_PROCPU_INT_H_S 0 + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6C) +/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_PROCPU_NMI_INT_H 0x00001FFF +#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) +#define GPIO_PROCPU_NMI_INT_H_V 0x1FFF +#define GPIO_PROCPU_NMI_INT_H_S 0 + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) +/* GPIO_SDIO_INT_H : RO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_SDIO_INT_H 0x00001FFF +#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) +#define GPIO_SDIO_INT_H_V 0x1FFF +#define GPIO_SDIO_INT_H_S 0 + #define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) /* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ /*description: */ @@ -1319,2572 +1423,3416 @@ extern "C" { #define GPIO_PIN25_SYNC2_BYPASS_V 0x3 #define GPIO_PIN25_SYNC2_BYPASS_S 0 -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) -/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xDC) +/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ /*description: */ -#define GPIO_STATUS_INTERRUPT_NEXT 0x03FFFFFF +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) +#define GPIO_PIN26_INT_ENA_V 0x1F +#define GPIO_PIN26_INT_ENA_S 13 +/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) +#define GPIO_PIN26_CONFIG_V 0x3 +#define GPIO_PIN26_CONFIG_S 11 +/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) +#define GPIO_PIN26_INT_TYPE_V 0x7 +#define GPIO_PIN26_INT_TYPE_S 7 +/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_M ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S)) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_V 0x1 +#define GPIO_PIN26_PAD_DRIVER_S 2 +/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_M ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S)) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN26_SYNC2_BYPASS_S 0 + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xE0) +/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) +#define GPIO_PIN27_INT_ENA_V 0x1F +#define GPIO_PIN27_INT_ENA_S 13 +/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) +#define GPIO_PIN27_CONFIG_V 0x3 +#define GPIO_PIN27_CONFIG_S 11 +/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) +#define GPIO_PIN27_INT_TYPE_V 0x7 +#define GPIO_PIN27_INT_TYPE_S 7 +/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_M ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S)) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_V 0x1 +#define GPIO_PIN27_PAD_DRIVER_S 2 +/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_M ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S)) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN27_SYNC2_BYPASS_S 0 + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xE4) +/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) +#define GPIO_PIN28_INT_ENA_V 0x1F +#define GPIO_PIN28_INT_ENA_S 13 +/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) +#define GPIO_PIN28_CONFIG_V 0x3 +#define GPIO_PIN28_CONFIG_S 11 +/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) +#define GPIO_PIN28_INT_TYPE_V 0x7 +#define GPIO_PIN28_INT_TYPE_S 7 +/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_M ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S)) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_V 0x1 +#define GPIO_PIN28_PAD_DRIVER_S 2 +/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_M ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S)) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN28_SYNC2_BYPASS_S 0 + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xE8) +/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) +#define GPIO_PIN29_INT_ENA_V 0x1F +#define GPIO_PIN29_INT_ENA_S 13 +/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) +#define GPIO_PIN29_CONFIG_V 0x3 +#define GPIO_PIN29_CONFIG_S 11 +/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) +#define GPIO_PIN29_INT_TYPE_V 0x7 +#define GPIO_PIN29_INT_TYPE_S 7 +/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_M ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S)) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_V 0x1 +#define GPIO_PIN29_PAD_DRIVER_S 2 +/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_M ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S)) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN29_SYNC2_BYPASS_S 0 + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xEC) +/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) +#define GPIO_PIN30_INT_ENA_V 0x1F +#define GPIO_PIN30_INT_ENA_S 13 +/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) +#define GPIO_PIN30_CONFIG_V 0x3 +#define GPIO_PIN30_CONFIG_S 11 +/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) +#define GPIO_PIN30_INT_TYPE_V 0x7 +#define GPIO_PIN30_INT_TYPE_S 7 +/* GPIO_PIN30_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC1_BYPASS_M ((GPIO_PIN30_SYNC1_BYPASS_V)<<(GPIO_PIN30_SYNC1_BYPASS_S)) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_V 0x1 +#define GPIO_PIN30_PAD_DRIVER_S 2 +/* GPIO_PIN30_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC2_BYPASS_M ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S)) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN30_SYNC2_BYPASS_S 0 + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xF0) +/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) +#define GPIO_PIN31_INT_ENA_V 0x1F +#define GPIO_PIN31_INT_ENA_S 13 +/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) +#define GPIO_PIN31_CONFIG_V 0x3 +#define GPIO_PIN31_CONFIG_S 11 +/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) +#define GPIO_PIN31_INT_TYPE_V 0x7 +#define GPIO_PIN31_INT_TYPE_S 7 +/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC1_BYPASS_M ((GPIO_PIN31_SYNC1_BYPASS_V)<<(GPIO_PIN31_SYNC1_BYPASS_S)) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_V 0x1 +#define GPIO_PIN31_PAD_DRIVER_S 2 +/* GPIO_PIN31_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC2_BYPASS_M ((GPIO_PIN31_SYNC2_BYPASS_V)<<(GPIO_PIN31_SYNC2_BYPASS_S)) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN31_SYNC2_BYPASS_S 0 + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xF4) +/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) +#define GPIO_PIN32_INT_ENA_V 0x1F +#define GPIO_PIN32_INT_ENA_S 13 +/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) +#define GPIO_PIN32_CONFIG_V 0x3 +#define GPIO_PIN32_CONFIG_S 11 +/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) +#define GPIO_PIN32_INT_TYPE_V 0x7 +#define GPIO_PIN32_INT_TYPE_S 7 +/* GPIO_PIN32_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC1_BYPASS_M ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S)) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN32_SYNC1_BYPASS_S 3 +/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_V 0x1 +#define GPIO_PIN32_PAD_DRIVER_S 2 +/* GPIO_PIN32_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC2_BYPASS_M ((GPIO_PIN32_SYNC2_BYPASS_V)<<(GPIO_PIN32_SYNC2_BYPASS_S)) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN32_SYNC2_BYPASS_S 0 + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xF8) +/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) +#define GPIO_PIN33_INT_ENA_V 0x1F +#define GPIO_PIN33_INT_ENA_S 13 +/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) +#define GPIO_PIN33_CONFIG_V 0x3 +#define GPIO_PIN33_CONFIG_S 11 +/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) +#define GPIO_PIN33_INT_TYPE_V 0x7 +#define GPIO_PIN33_INT_TYPE_S 7 +/* GPIO_PIN33_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC1_BYPASS_M ((GPIO_PIN33_SYNC1_BYPASS_V)<<(GPIO_PIN33_SYNC1_BYPASS_S)) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN33_SYNC1_BYPASS_S 3 +/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_V 0x1 +#define GPIO_PIN33_PAD_DRIVER_S 2 +/* GPIO_PIN33_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC2_BYPASS_M ((GPIO_PIN33_SYNC2_BYPASS_V)<<(GPIO_PIN33_SYNC2_BYPASS_S)) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN33_SYNC2_BYPASS_S 0 + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xFC) +/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) +#define GPIO_PIN34_INT_ENA_V 0x1F +#define GPIO_PIN34_INT_ENA_S 13 +/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) +#define GPIO_PIN34_CONFIG_V 0x3 +#define GPIO_PIN34_CONFIG_S 11 +/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 +/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) +#define GPIO_PIN34_INT_TYPE_V 0x7 +#define GPIO_PIN34_INT_TYPE_S 7 +/* GPIO_PIN34_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN34_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC1_BYPASS_M ((GPIO_PIN34_SYNC1_BYPASS_V)<<(GPIO_PIN34_SYNC1_BYPASS_S)) +#define GPIO_PIN34_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN34_SYNC1_BYPASS_S 3 +/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_V 0x1 +#define GPIO_PIN34_PAD_DRIVER_S 2 +/* GPIO_PIN34_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN34_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC2_BYPASS_M ((GPIO_PIN34_SYNC2_BYPASS_V)<<(GPIO_PIN34_SYNC2_BYPASS_S)) +#define GPIO_PIN34_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN34_SYNC2_BYPASS_S 0 + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) +/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) +#define GPIO_PIN35_INT_ENA_V 0x1F +#define GPIO_PIN35_INT_ENA_S 13 +/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) +#define GPIO_PIN35_CONFIG_V 0x3 +#define GPIO_PIN35_CONFIG_S 11 +/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 +/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) +#define GPIO_PIN35_INT_TYPE_V 0x7 +#define GPIO_PIN35_INT_TYPE_S 7 +/* GPIO_PIN35_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN35_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC1_BYPASS_M ((GPIO_PIN35_SYNC1_BYPASS_V)<<(GPIO_PIN35_SYNC1_BYPASS_S)) +#define GPIO_PIN35_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN35_SYNC1_BYPASS_S 3 +/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_V 0x1 +#define GPIO_PIN35_PAD_DRIVER_S 2 +/* GPIO_PIN35_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN35_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC2_BYPASS_M ((GPIO_PIN35_SYNC2_BYPASS_V)<<(GPIO_PIN35_SYNC2_BYPASS_S)) +#define GPIO_PIN35_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN35_SYNC2_BYPASS_S 0 + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) +/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) +#define GPIO_PIN36_INT_ENA_V 0x1F +#define GPIO_PIN36_INT_ENA_S 13 +/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) +#define GPIO_PIN36_CONFIG_V 0x3 +#define GPIO_PIN36_CONFIG_S 11 +/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 +/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) +#define GPIO_PIN36_INT_TYPE_V 0x7 +#define GPIO_PIN36_INT_TYPE_S 7 +/* GPIO_PIN36_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN36_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC1_BYPASS_M ((GPIO_PIN36_SYNC1_BYPASS_V)<<(GPIO_PIN36_SYNC1_BYPASS_S)) +#define GPIO_PIN36_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN36_SYNC1_BYPASS_S 3 +/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_V 0x1 +#define GPIO_PIN36_PAD_DRIVER_S 2 +/* GPIO_PIN36_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN36_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC2_BYPASS_M ((GPIO_PIN36_SYNC2_BYPASS_V)<<(GPIO_PIN36_SYNC2_BYPASS_S)) +#define GPIO_PIN36_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN36_SYNC2_BYPASS_S 0 + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) +/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) +#define GPIO_PIN37_INT_ENA_V 0x1F +#define GPIO_PIN37_INT_ENA_S 13 +/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) +#define GPIO_PIN37_CONFIG_V 0x3 +#define GPIO_PIN37_CONFIG_S 11 +/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 +/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) +#define GPIO_PIN37_INT_TYPE_V 0x7 +#define GPIO_PIN37_INT_TYPE_S 7 +/* GPIO_PIN37_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN37_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC1_BYPASS_M ((GPIO_PIN37_SYNC1_BYPASS_V)<<(GPIO_PIN37_SYNC1_BYPASS_S)) +#define GPIO_PIN37_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN37_SYNC1_BYPASS_S 3 +/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_V 0x1 +#define GPIO_PIN37_PAD_DRIVER_S 2 +/* GPIO_PIN37_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN37_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC2_BYPASS_M ((GPIO_PIN37_SYNC2_BYPASS_V)<<(GPIO_PIN37_SYNC2_BYPASS_S)) +#define GPIO_PIN37_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN37_SYNC2_BYPASS_S 0 + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10C) +/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) +#define GPIO_PIN38_INT_ENA_V 0x1F +#define GPIO_PIN38_INT_ENA_S 13 +/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) +#define GPIO_PIN38_CONFIG_V 0x3 +#define GPIO_PIN38_CONFIG_S 11 +/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 +/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) +#define GPIO_PIN38_INT_TYPE_V 0x7 +#define GPIO_PIN38_INT_TYPE_S 7 +/* GPIO_PIN38_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN38_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC1_BYPASS_M ((GPIO_PIN38_SYNC1_BYPASS_V)<<(GPIO_PIN38_SYNC1_BYPASS_S)) +#define GPIO_PIN38_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN38_SYNC1_BYPASS_S 3 +/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_V 0x1 +#define GPIO_PIN38_PAD_DRIVER_S 2 +/* GPIO_PIN38_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN38_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC2_BYPASS_M ((GPIO_PIN38_SYNC2_BYPASS_V)<<(GPIO_PIN38_SYNC2_BYPASS_S)) +#define GPIO_PIN38_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN38_SYNC2_BYPASS_S 0 + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) +/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) +#define GPIO_PIN39_INT_ENA_V 0x1F +#define GPIO_PIN39_INT_ENA_S 13 +/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) +#define GPIO_PIN39_CONFIG_V 0x3 +#define GPIO_PIN39_CONFIG_S 11 +/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 +/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) +#define GPIO_PIN39_INT_TYPE_V 0x7 +#define GPIO_PIN39_INT_TYPE_S 7 +/* GPIO_PIN39_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN39_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC1_BYPASS_M ((GPIO_PIN39_SYNC1_BYPASS_V)<<(GPIO_PIN39_SYNC1_BYPASS_S)) +#define GPIO_PIN39_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN39_SYNC1_BYPASS_S 3 +/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_V 0x1 +#define GPIO_PIN39_PAD_DRIVER_S 2 +/* GPIO_PIN39_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN39_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC2_BYPASS_M ((GPIO_PIN39_SYNC2_BYPASS_V)<<(GPIO_PIN39_SYNC2_BYPASS_S)) +#define GPIO_PIN39_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN39_SYNC2_BYPASS_S 0 + +#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) +/* GPIO_PIN40_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN40_INT_ENA 0x0000001F +#define GPIO_PIN40_INT_ENA_M ((GPIO_PIN40_INT_ENA_V)<<(GPIO_PIN40_INT_ENA_S)) +#define GPIO_PIN40_INT_ENA_V 0x1F +#define GPIO_PIN40_INT_ENA_S 13 +/* GPIO_PIN40_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN40_CONFIG 0x00000003 +#define GPIO_PIN40_CONFIG_M ((GPIO_PIN40_CONFIG_V)<<(GPIO_PIN40_CONFIG_S)) +#define GPIO_PIN40_CONFIG_V 0x3 +#define GPIO_PIN40_CONFIG_S 11 +/* GPIO_PIN40_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN40_WAKEUP_ENABLE_S 10 +/* GPIO_PIN40_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN40_INT_TYPE 0x00000007 +#define GPIO_PIN40_INT_TYPE_M ((GPIO_PIN40_INT_TYPE_V)<<(GPIO_PIN40_INT_TYPE_S)) +#define GPIO_PIN40_INT_TYPE_V 0x7 +#define GPIO_PIN40_INT_TYPE_S 7 +/* GPIO_PIN40_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN40_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC1_BYPASS_M ((GPIO_PIN40_SYNC1_BYPASS_V)<<(GPIO_PIN40_SYNC1_BYPASS_S)) +#define GPIO_PIN40_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN40_SYNC1_BYPASS_S 3 +/* GPIO_PIN40_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN40_PAD_DRIVER (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_V 0x1 +#define GPIO_PIN40_PAD_DRIVER_S 2 +/* GPIO_PIN40_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN40_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC2_BYPASS_M ((GPIO_PIN40_SYNC2_BYPASS_V)<<(GPIO_PIN40_SYNC2_BYPASS_S)) +#define GPIO_PIN40_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN40_SYNC2_BYPASS_S 0 + +#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) +/* GPIO_PIN41_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN41_INT_ENA 0x0000001F +#define GPIO_PIN41_INT_ENA_M ((GPIO_PIN41_INT_ENA_V)<<(GPIO_PIN41_INT_ENA_S)) +#define GPIO_PIN41_INT_ENA_V 0x1F +#define GPIO_PIN41_INT_ENA_S 13 +/* GPIO_PIN41_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN41_CONFIG 0x00000003 +#define GPIO_PIN41_CONFIG_M ((GPIO_PIN41_CONFIG_V)<<(GPIO_PIN41_CONFIG_S)) +#define GPIO_PIN41_CONFIG_V 0x3 +#define GPIO_PIN41_CONFIG_S 11 +/* GPIO_PIN41_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN41_WAKEUP_ENABLE_S 10 +/* GPIO_PIN41_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN41_INT_TYPE 0x00000007 +#define GPIO_PIN41_INT_TYPE_M ((GPIO_PIN41_INT_TYPE_V)<<(GPIO_PIN41_INT_TYPE_S)) +#define GPIO_PIN41_INT_TYPE_V 0x7 +#define GPIO_PIN41_INT_TYPE_S 7 +/* GPIO_PIN41_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN41_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC1_BYPASS_M ((GPIO_PIN41_SYNC1_BYPASS_V)<<(GPIO_PIN41_SYNC1_BYPASS_S)) +#define GPIO_PIN41_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN41_SYNC1_BYPASS_S 3 +/* GPIO_PIN41_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN41_PAD_DRIVER (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_V 0x1 +#define GPIO_PIN41_PAD_DRIVER_S 2 +/* GPIO_PIN41_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN41_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC2_BYPASS_M ((GPIO_PIN41_SYNC2_BYPASS_V)<<(GPIO_PIN41_SYNC2_BYPASS_S)) +#define GPIO_PIN41_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN41_SYNC2_BYPASS_S 0 + +#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11C) +/* GPIO_PIN42_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN42_INT_ENA 0x0000001F +#define GPIO_PIN42_INT_ENA_M ((GPIO_PIN42_INT_ENA_V)<<(GPIO_PIN42_INT_ENA_S)) +#define GPIO_PIN42_INT_ENA_V 0x1F +#define GPIO_PIN42_INT_ENA_S 13 +/* GPIO_PIN42_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN42_CONFIG 0x00000003 +#define GPIO_PIN42_CONFIG_M ((GPIO_PIN42_CONFIG_V)<<(GPIO_PIN42_CONFIG_S)) +#define GPIO_PIN42_CONFIG_V 0x3 +#define GPIO_PIN42_CONFIG_S 11 +/* GPIO_PIN42_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN42_WAKEUP_ENABLE_S 10 +/* GPIO_PIN42_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN42_INT_TYPE 0x00000007 +#define GPIO_PIN42_INT_TYPE_M ((GPIO_PIN42_INT_TYPE_V)<<(GPIO_PIN42_INT_TYPE_S)) +#define GPIO_PIN42_INT_TYPE_V 0x7 +#define GPIO_PIN42_INT_TYPE_S 7 +/* GPIO_PIN42_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN42_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC1_BYPASS_M ((GPIO_PIN42_SYNC1_BYPASS_V)<<(GPIO_PIN42_SYNC1_BYPASS_S)) +#define GPIO_PIN42_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN42_SYNC1_BYPASS_S 3 +/* GPIO_PIN42_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN42_PAD_DRIVER (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_V 0x1 +#define GPIO_PIN42_PAD_DRIVER_S 2 +/* GPIO_PIN42_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN42_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC2_BYPASS_M ((GPIO_PIN42_SYNC2_BYPASS_V)<<(GPIO_PIN42_SYNC2_BYPASS_S)) +#define GPIO_PIN42_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN42_SYNC2_BYPASS_S 0 + +#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) +/* GPIO_PIN43_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN43_INT_ENA 0x0000001F +#define GPIO_PIN43_INT_ENA_M ((GPIO_PIN43_INT_ENA_V)<<(GPIO_PIN43_INT_ENA_S)) +#define GPIO_PIN43_INT_ENA_V 0x1F +#define GPIO_PIN43_INT_ENA_S 13 +/* GPIO_PIN43_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN43_CONFIG 0x00000003 +#define GPIO_PIN43_CONFIG_M ((GPIO_PIN43_CONFIG_V)<<(GPIO_PIN43_CONFIG_S)) +#define GPIO_PIN43_CONFIG_V 0x3 +#define GPIO_PIN43_CONFIG_S 11 +/* GPIO_PIN43_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN43_WAKEUP_ENABLE_S 10 +/* GPIO_PIN43_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN43_INT_TYPE 0x00000007 +#define GPIO_PIN43_INT_TYPE_M ((GPIO_PIN43_INT_TYPE_V)<<(GPIO_PIN43_INT_TYPE_S)) +#define GPIO_PIN43_INT_TYPE_V 0x7 +#define GPIO_PIN43_INT_TYPE_S 7 +/* GPIO_PIN43_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN43_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC1_BYPASS_M ((GPIO_PIN43_SYNC1_BYPASS_V)<<(GPIO_PIN43_SYNC1_BYPASS_S)) +#define GPIO_PIN43_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN43_SYNC1_BYPASS_S 3 +/* GPIO_PIN43_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN43_PAD_DRIVER (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_V 0x1 +#define GPIO_PIN43_PAD_DRIVER_S 2 +/* GPIO_PIN43_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN43_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC2_BYPASS_M ((GPIO_PIN43_SYNC2_BYPASS_V)<<(GPIO_PIN43_SYNC2_BYPASS_S)) +#define GPIO_PIN43_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN43_SYNC2_BYPASS_S 0 + +#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) +/* GPIO_PIN44_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN44_INT_ENA 0x0000001F +#define GPIO_PIN44_INT_ENA_M ((GPIO_PIN44_INT_ENA_V)<<(GPIO_PIN44_INT_ENA_S)) +#define GPIO_PIN44_INT_ENA_V 0x1F +#define GPIO_PIN44_INT_ENA_S 13 +/* GPIO_PIN44_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN44_CONFIG 0x00000003 +#define GPIO_PIN44_CONFIG_M ((GPIO_PIN44_CONFIG_V)<<(GPIO_PIN44_CONFIG_S)) +#define GPIO_PIN44_CONFIG_V 0x3 +#define GPIO_PIN44_CONFIG_S 11 +/* GPIO_PIN44_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN44_WAKEUP_ENABLE_S 10 +/* GPIO_PIN44_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN44_INT_TYPE 0x00000007 +#define GPIO_PIN44_INT_TYPE_M ((GPIO_PIN44_INT_TYPE_V)<<(GPIO_PIN44_INT_TYPE_S)) +#define GPIO_PIN44_INT_TYPE_V 0x7 +#define GPIO_PIN44_INT_TYPE_S 7 +/* GPIO_PIN44_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN44_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC1_BYPASS_M ((GPIO_PIN44_SYNC1_BYPASS_V)<<(GPIO_PIN44_SYNC1_BYPASS_S)) +#define GPIO_PIN44_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN44_SYNC1_BYPASS_S 3 +/* GPIO_PIN44_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN44_PAD_DRIVER (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_V 0x1 +#define GPIO_PIN44_PAD_DRIVER_S 2 +/* GPIO_PIN44_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN44_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC2_BYPASS_M ((GPIO_PIN44_SYNC2_BYPASS_V)<<(GPIO_PIN44_SYNC2_BYPASS_S)) +#define GPIO_PIN44_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN44_SYNC2_BYPASS_S 0 + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) +/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFF #define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3FFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFF #define GPIO_STATUS_INTERRUPT_NEXT_S 0 +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) +/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[12:0] ;default: 13'h0 ; */ +/*description: */ +#define GPIO_STATUS_INTERRUPT_NEXT1 0x00001FFF +#define GPIO_STATUS_INTERRUPT_NEXT1_M ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S)) +#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x1FFF +#define GPIO_STATUS_INTERRUPT_NEXT1_S 0 + #define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) -/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG0_IN_SEL (BIT(6)) -#define GPIO_SIG0_IN_SEL_M (BIT(6)) +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (BIT(7)) #define GPIO_SIG0_IN_SEL_V 0x1 -#define GPIO_SIG0_IN_SEL_S 6 -/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG0_IN_SEL_S 7 +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC0_IN_INV_SEL_V 0x1 -#define GPIO_FUNC0_IN_INV_SEL_S 5 -/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC0_IN_SEL 0x0000001F +#define GPIO_FUNC0_IN_SEL 0x0000003F #define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) -#define GPIO_FUNC0_IN_SEL_V 0x1F +#define GPIO_FUNC0_IN_SEL_V 0x3F #define GPIO_FUNC0_IN_SEL_S 0 #define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) -/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG1_IN_SEL (BIT(6)) -#define GPIO_SIG1_IN_SEL_M (BIT(6)) +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (BIT(7)) #define GPIO_SIG1_IN_SEL_V 0x1 -#define GPIO_SIG1_IN_SEL_S 6 -/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG1_IN_SEL_S 7 +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC1_IN_INV_SEL_V 0x1 -#define GPIO_FUNC1_IN_INV_SEL_S 5 -/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC1_IN_INV_SEL_S 6 +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC1_IN_SEL 0x0000001F +#define GPIO_FUNC1_IN_SEL 0x0000003F #define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) -#define GPIO_FUNC1_IN_SEL_V 0x1F +#define GPIO_FUNC1_IN_SEL_V 0x3F #define GPIO_FUNC1_IN_SEL_S 0 #define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15C) -/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG2_IN_SEL (BIT(6)) -#define GPIO_SIG2_IN_SEL_M (BIT(6)) +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (BIT(7)) #define GPIO_SIG2_IN_SEL_V 0x1 -#define GPIO_SIG2_IN_SEL_S 6 -/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG2_IN_SEL_S 7 +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC2_IN_INV_SEL_V 0x1 -#define GPIO_FUNC2_IN_INV_SEL_S 5 -/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC2_IN_INV_SEL_S 6 +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC2_IN_SEL 0x0000001F +#define GPIO_FUNC2_IN_SEL 0x0000003F #define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) -#define GPIO_FUNC2_IN_SEL_V 0x1F +#define GPIO_FUNC2_IN_SEL_V 0x3F #define GPIO_FUNC2_IN_SEL_S 0 #define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) -/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG3_IN_SEL (BIT(6)) -#define GPIO_SIG3_IN_SEL_M (BIT(6)) +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (BIT(7)) #define GPIO_SIG3_IN_SEL_V 0x1 -#define GPIO_SIG3_IN_SEL_S 6 -/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG3_IN_SEL_S 7 +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC3_IN_INV_SEL_V 0x1 -#define GPIO_FUNC3_IN_INV_SEL_S 5 -/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC3_IN_INV_SEL_S 6 +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC3_IN_SEL 0x0000001F +#define GPIO_FUNC3_IN_SEL 0x0000003F #define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) -#define GPIO_FUNC3_IN_SEL_V 0x1F +#define GPIO_FUNC3_IN_SEL_V 0x3F #define GPIO_FUNC3_IN_SEL_S 0 #define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) -/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG4_IN_SEL (BIT(6)) -#define GPIO_SIG4_IN_SEL_M (BIT(6)) +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (BIT(7)) #define GPIO_SIG4_IN_SEL_V 0x1 -#define GPIO_SIG4_IN_SEL_S 6 -/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG4_IN_SEL_S 7 +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC4_IN_INV_SEL_V 0x1 -#define GPIO_FUNC4_IN_INV_SEL_S 5 -/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC4_IN_INV_SEL_S 6 +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC4_IN_SEL 0x0000001F +#define GPIO_FUNC4_IN_SEL 0x0000003F #define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) -#define GPIO_FUNC4_IN_SEL_V 0x1F +#define GPIO_FUNC4_IN_SEL_V 0x3F #define GPIO_FUNC4_IN_SEL_S 0 #define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) -/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG5_IN_SEL (BIT(6)) -#define GPIO_SIG5_IN_SEL_M (BIT(6)) +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (BIT(7)) #define GPIO_SIG5_IN_SEL_V 0x1 -#define GPIO_SIG5_IN_SEL_S 6 -/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG5_IN_SEL_S 7 +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC5_IN_INV_SEL_V 0x1 -#define GPIO_FUNC5_IN_INV_SEL_S 5 -/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC5_IN_INV_SEL_S 6 +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC5_IN_SEL 0x0000001F +#define GPIO_FUNC5_IN_SEL 0x0000003F #define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) -#define GPIO_FUNC5_IN_SEL_V 0x1F +#define GPIO_FUNC5_IN_SEL_V 0x3F #define GPIO_FUNC5_IN_SEL_S 0 #define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16C) -/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG6_IN_SEL (BIT(6)) -#define GPIO_SIG6_IN_SEL_M (BIT(6)) +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (BIT(7)) #define GPIO_SIG6_IN_SEL_V 0x1 -#define GPIO_SIG6_IN_SEL_S 6 -/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG6_IN_SEL_S 7 +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC6_IN_INV_SEL_V 0x1 -#define GPIO_FUNC6_IN_INV_SEL_S 5 -/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC6_IN_SEL 0x0000001F +#define GPIO_FUNC6_IN_SEL 0x0000003F #define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) -#define GPIO_FUNC6_IN_SEL_V 0x1F +#define GPIO_FUNC6_IN_SEL_V 0x3F #define GPIO_FUNC6_IN_SEL_S 0 #define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) -/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG7_IN_SEL (BIT(6)) -#define GPIO_SIG7_IN_SEL_M (BIT(6)) +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (BIT(7)) #define GPIO_SIG7_IN_SEL_V 0x1 -#define GPIO_SIG7_IN_SEL_S 6 -/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG7_IN_SEL_S 7 +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC7_IN_INV_SEL_V 0x1 -#define GPIO_FUNC7_IN_INV_SEL_S 5 -/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC7_IN_SEL 0x0000001F +#define GPIO_FUNC7_IN_SEL 0x0000003F #define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) -#define GPIO_FUNC7_IN_SEL_V 0x1F +#define GPIO_FUNC7_IN_SEL_V 0x3F #define GPIO_FUNC7_IN_SEL_S 0 #define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) -/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG8_IN_SEL (BIT(6)) -#define GPIO_SIG8_IN_SEL_M (BIT(6)) +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (BIT(7)) #define GPIO_SIG8_IN_SEL_V 0x1 -#define GPIO_SIG8_IN_SEL_S 6 -/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG8_IN_SEL_S 7 +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC8_IN_INV_SEL_V 0x1 -#define GPIO_FUNC8_IN_INV_SEL_S 5 -/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC8_IN_SEL 0x0000001F +#define GPIO_FUNC8_IN_SEL 0x0000003F #define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) -#define GPIO_FUNC8_IN_SEL_V 0x1F +#define GPIO_FUNC8_IN_SEL_V 0x3F #define GPIO_FUNC8_IN_SEL_S 0 #define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) -/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG9_IN_SEL (BIT(6)) -#define GPIO_SIG9_IN_SEL_M (BIT(6)) +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (BIT(7)) #define GPIO_SIG9_IN_SEL_V 0x1 -#define GPIO_SIG9_IN_SEL_S 6 -/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG9_IN_SEL_S 7 +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC9_IN_INV_SEL_V 0x1 -#define GPIO_FUNC9_IN_INV_SEL_S 5 -/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC9_IN_SEL 0x0000001F +#define GPIO_FUNC9_IN_SEL 0x0000003F #define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) -#define GPIO_FUNC9_IN_SEL_V 0x1F +#define GPIO_FUNC9_IN_SEL_V 0x3F #define GPIO_FUNC9_IN_SEL_S 0 #define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17C) -/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG10_IN_SEL (BIT(6)) -#define GPIO_SIG10_IN_SEL_M (BIT(6)) +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (BIT(7)) #define GPIO_SIG10_IN_SEL_V 0x1 -#define GPIO_SIG10_IN_SEL_S 6 -/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG10_IN_SEL_S 7 +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC10_IN_INV_SEL_V 0x1 -#define GPIO_FUNC10_IN_INV_SEL_S 5 -/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC10_IN_SEL 0x0000001F +#define GPIO_FUNC10_IN_SEL 0x0000003F #define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) -#define GPIO_FUNC10_IN_SEL_V 0x1F +#define GPIO_FUNC10_IN_SEL_V 0x3F #define GPIO_FUNC10_IN_SEL_S 0 #define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) -/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG11_IN_SEL (BIT(6)) -#define GPIO_SIG11_IN_SEL_M (BIT(6)) +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (BIT(7)) #define GPIO_SIG11_IN_SEL_V 0x1 -#define GPIO_SIG11_IN_SEL_S 6 -/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG11_IN_SEL_S 7 +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC11_IN_INV_SEL_V 0x1 -#define GPIO_FUNC11_IN_INV_SEL_S 5 -/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC11_IN_SEL 0x0000001F +#define GPIO_FUNC11_IN_SEL 0x0000003F #define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) -#define GPIO_FUNC11_IN_SEL_V 0x1F +#define GPIO_FUNC11_IN_SEL_V 0x3F #define GPIO_FUNC11_IN_SEL_S 0 #define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) -/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG12_IN_SEL (BIT(6)) -#define GPIO_SIG12_IN_SEL_M (BIT(6)) +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (BIT(7)) #define GPIO_SIG12_IN_SEL_V 0x1 -#define GPIO_SIG12_IN_SEL_S 6 -/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG12_IN_SEL_S 7 +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC12_IN_INV_SEL_V 0x1 -#define GPIO_FUNC12_IN_INV_SEL_S 5 -/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC12_IN_SEL 0x0000001F +#define GPIO_FUNC12_IN_SEL 0x0000003F #define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) -#define GPIO_FUNC12_IN_SEL_V 0x1F +#define GPIO_FUNC12_IN_SEL_V 0x3F #define GPIO_FUNC12_IN_SEL_S 0 #define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) -/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG13_IN_SEL (BIT(6)) -#define GPIO_SIG13_IN_SEL_M (BIT(6)) +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (BIT(7)) #define GPIO_SIG13_IN_SEL_V 0x1 -#define GPIO_SIG13_IN_SEL_S 6 -/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG13_IN_SEL_S 7 +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC13_IN_INV_SEL_V 0x1 -#define GPIO_FUNC13_IN_INV_SEL_S 5 -/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC13_IN_SEL 0x0000001F +#define GPIO_FUNC13_IN_SEL 0x0000003F #define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) -#define GPIO_FUNC13_IN_SEL_V 0x1F +#define GPIO_FUNC13_IN_SEL_V 0x3F #define GPIO_FUNC13_IN_SEL_S 0 #define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18C) -/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG14_IN_SEL (BIT(6)) -#define GPIO_SIG14_IN_SEL_M (BIT(6)) +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (BIT(7)) #define GPIO_SIG14_IN_SEL_V 0x1 -#define GPIO_SIG14_IN_SEL_S 6 -/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG14_IN_SEL_S 7 +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC14_IN_INV_SEL_V 0x1 -#define GPIO_FUNC14_IN_INV_SEL_S 5 -/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC14_IN_SEL 0x0000001F +#define GPIO_FUNC14_IN_SEL 0x0000003F #define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) -#define GPIO_FUNC14_IN_SEL_V 0x1F +#define GPIO_FUNC14_IN_SEL_V 0x3F #define GPIO_FUNC14_IN_SEL_S 0 #define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) -/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG15_IN_SEL (BIT(6)) -#define GPIO_SIG15_IN_SEL_M (BIT(6)) +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (BIT(7)) #define GPIO_SIG15_IN_SEL_V 0x1 -#define GPIO_SIG15_IN_SEL_S 6 -/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG15_IN_SEL_S 7 +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC15_IN_INV_SEL_V 0x1 -#define GPIO_FUNC15_IN_INV_SEL_S 5 -/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC15_IN_SEL 0x0000001F +#define GPIO_FUNC15_IN_SEL 0x0000003F #define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) -#define GPIO_FUNC15_IN_SEL_V 0x1F +#define GPIO_FUNC15_IN_SEL_V 0x3F #define GPIO_FUNC15_IN_SEL_S 0 #define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) -/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG16_IN_SEL (BIT(6)) -#define GPIO_SIG16_IN_SEL_M (BIT(6)) +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (BIT(7)) #define GPIO_SIG16_IN_SEL_V 0x1 -#define GPIO_SIG16_IN_SEL_S 6 -/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG16_IN_SEL_S 7 +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC16_IN_INV_SEL_V 0x1 -#define GPIO_FUNC16_IN_INV_SEL_S 5 -/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC16_IN_SEL 0x0000001F +#define GPIO_FUNC16_IN_SEL 0x0000003F #define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) -#define GPIO_FUNC16_IN_SEL_V 0x1F +#define GPIO_FUNC16_IN_SEL_V 0x3F #define GPIO_FUNC16_IN_SEL_S 0 #define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) -/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG17_IN_SEL (BIT(6)) -#define GPIO_SIG17_IN_SEL_M (BIT(6)) +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (BIT(7)) #define GPIO_SIG17_IN_SEL_V 0x1 -#define GPIO_SIG17_IN_SEL_S 6 -/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG17_IN_SEL_S 7 +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC17_IN_INV_SEL_V 0x1 -#define GPIO_FUNC17_IN_INV_SEL_S 5 -/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC17_IN_SEL 0x0000001F +#define GPIO_FUNC17_IN_SEL 0x0000003F #define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) -#define GPIO_FUNC17_IN_SEL_V 0x1F +#define GPIO_FUNC17_IN_SEL_V 0x3F #define GPIO_FUNC17_IN_SEL_S 0 #define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19C) -/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG18_IN_SEL (BIT(6)) -#define GPIO_SIG18_IN_SEL_M (BIT(6)) +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (BIT(7)) #define GPIO_SIG18_IN_SEL_V 0x1 -#define GPIO_SIG18_IN_SEL_S 6 -/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG18_IN_SEL_S 7 +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC18_IN_INV_SEL_V 0x1 -#define GPIO_FUNC18_IN_INV_SEL_S 5 -/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC18_IN_INV_SEL_S 6 +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC18_IN_SEL 0x0000001F +#define GPIO_FUNC18_IN_SEL 0x0000003F #define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) -#define GPIO_FUNC18_IN_SEL_V 0x1F +#define GPIO_FUNC18_IN_SEL_V 0x3F #define GPIO_FUNC18_IN_SEL_S 0 #define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A0) -/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG19_IN_SEL (BIT(6)) -#define GPIO_SIG19_IN_SEL_M (BIT(6)) +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (BIT(7)) #define GPIO_SIG19_IN_SEL_V 0x1 -#define GPIO_SIG19_IN_SEL_S 6 -/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG19_IN_SEL_S 7 +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC19_IN_INV_SEL_V 0x1 -#define GPIO_FUNC19_IN_INV_SEL_S 5 -/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC19_IN_SEL 0x0000001F +#define GPIO_FUNC19_IN_SEL 0x0000003F #define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) -#define GPIO_FUNC19_IN_SEL_V 0x1F +#define GPIO_FUNC19_IN_SEL_V 0x3F #define GPIO_FUNC19_IN_SEL_S 0 #define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A4) -/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG20_IN_SEL (BIT(6)) -#define GPIO_SIG20_IN_SEL_M (BIT(6)) +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (BIT(7)) #define GPIO_SIG20_IN_SEL_V 0x1 -#define GPIO_SIG20_IN_SEL_S 6 -/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG20_IN_SEL_S 7 +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC20_IN_INV_SEL_V 0x1 -#define GPIO_FUNC20_IN_INV_SEL_S 5 -/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC20_IN_INV_SEL_S 6 +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC20_IN_SEL 0x0000001F +#define GPIO_FUNC20_IN_SEL 0x0000003F #define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) -#define GPIO_FUNC20_IN_SEL_V 0x1F +#define GPIO_FUNC20_IN_SEL_V 0x3F #define GPIO_FUNC20_IN_SEL_S 0 #define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A8) -/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG21_IN_SEL (BIT(6)) -#define GPIO_SIG21_IN_SEL_M (BIT(6)) +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (BIT(7)) #define GPIO_SIG21_IN_SEL_V 0x1 -#define GPIO_SIG21_IN_SEL_S 6 -/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG21_IN_SEL_S 7 +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC21_IN_INV_SEL_V 0x1 -#define GPIO_FUNC21_IN_INV_SEL_S 5 -/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC21_IN_SEL 0x0000001F +#define GPIO_FUNC21_IN_SEL 0x0000003F #define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) -#define GPIO_FUNC21_IN_SEL_V 0x1F +#define GPIO_FUNC21_IN_SEL_V 0x3F #define GPIO_FUNC21_IN_SEL_S 0 #define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1AC) -/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG22_IN_SEL (BIT(6)) -#define GPIO_SIG22_IN_SEL_M (BIT(6)) +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (BIT(7)) #define GPIO_SIG22_IN_SEL_V 0x1 -#define GPIO_SIG22_IN_SEL_S 6 -/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG22_IN_SEL_S 7 +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC22_IN_INV_SEL_V 0x1 -#define GPIO_FUNC22_IN_INV_SEL_S 5 -/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC22_IN_SEL 0x0000001F +#define GPIO_FUNC22_IN_SEL 0x0000003F #define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) -#define GPIO_FUNC22_IN_SEL_V 0x1F +#define GPIO_FUNC22_IN_SEL_V 0x3F #define GPIO_FUNC22_IN_SEL_S 0 #define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B0) -/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG23_IN_SEL (BIT(6)) -#define GPIO_SIG23_IN_SEL_M (BIT(6)) +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (BIT(7)) #define GPIO_SIG23_IN_SEL_V 0x1 -#define GPIO_SIG23_IN_SEL_S 6 -/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG23_IN_SEL_S 7 +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC23_IN_INV_SEL_V 0x1 -#define GPIO_FUNC23_IN_INV_SEL_S 5 -/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC23_IN_SEL 0x0000001F +#define GPIO_FUNC23_IN_SEL 0x0000003F #define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) -#define GPIO_FUNC23_IN_SEL_V 0x1F +#define GPIO_FUNC23_IN_SEL_V 0x3F #define GPIO_FUNC23_IN_SEL_S 0 #define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B4) -/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG24_IN_SEL (BIT(6)) -#define GPIO_SIG24_IN_SEL_M (BIT(6)) +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (BIT(7)) #define GPIO_SIG24_IN_SEL_V 0x1 -#define GPIO_SIG24_IN_SEL_S 6 -/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG24_IN_SEL_S 7 +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC24_IN_INV_SEL_V 0x1 -#define GPIO_FUNC24_IN_INV_SEL_S 5 -/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC24_IN_SEL 0x0000001F +#define GPIO_FUNC24_IN_SEL 0x0000003F #define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) -#define GPIO_FUNC24_IN_SEL_V 0x1F +#define GPIO_FUNC24_IN_SEL_V 0x3F #define GPIO_FUNC24_IN_SEL_S 0 #define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B8) -/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG25_IN_SEL (BIT(6)) -#define GPIO_SIG25_IN_SEL_M (BIT(6)) +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (BIT(7)) #define GPIO_SIG25_IN_SEL_V 0x1 -#define GPIO_SIG25_IN_SEL_S 6 -/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG25_IN_SEL_S 7 +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC25_IN_INV_SEL_V 0x1 -#define GPIO_FUNC25_IN_INV_SEL_S 5 -/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC25_IN_INV_SEL_S 6 +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC25_IN_SEL 0x0000001F +#define GPIO_FUNC25_IN_SEL 0x0000003F #define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) -#define GPIO_FUNC25_IN_SEL_V 0x1F +#define GPIO_FUNC25_IN_SEL_V 0x3F #define GPIO_FUNC25_IN_SEL_S 0 #define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1BC) -/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG26_IN_SEL (BIT(6)) -#define GPIO_SIG26_IN_SEL_M (BIT(6)) +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (BIT(7)) #define GPIO_SIG26_IN_SEL_V 0x1 -#define GPIO_SIG26_IN_SEL_S 6 -/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG26_IN_SEL_S 7 +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC26_IN_INV_SEL_V 0x1 -#define GPIO_FUNC26_IN_INV_SEL_S 5 -/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC26_IN_INV_SEL_S 6 +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC26_IN_SEL 0x0000001F +#define GPIO_FUNC26_IN_SEL 0x0000003F #define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) -#define GPIO_FUNC26_IN_SEL_V 0x1F +#define GPIO_FUNC26_IN_SEL_V 0x3F #define GPIO_FUNC26_IN_SEL_S 0 #define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C0) -/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG27_IN_SEL (BIT(6)) -#define GPIO_SIG27_IN_SEL_M (BIT(6)) +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (BIT(7)) #define GPIO_SIG27_IN_SEL_V 0x1 -#define GPIO_SIG27_IN_SEL_S 6 -/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG27_IN_SEL_S 7 +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC27_IN_INV_SEL_V 0x1 -#define GPIO_FUNC27_IN_INV_SEL_S 5 -/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC27_IN_INV_SEL_S 6 +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC27_IN_SEL 0x0000001F +#define GPIO_FUNC27_IN_SEL 0x0000003F #define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) -#define GPIO_FUNC27_IN_SEL_V 0x1F +#define GPIO_FUNC27_IN_SEL_V 0x3F #define GPIO_FUNC27_IN_SEL_S 0 #define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C4) -/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG28_IN_SEL (BIT(6)) -#define GPIO_SIG28_IN_SEL_M (BIT(6)) +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (BIT(7)) #define GPIO_SIG28_IN_SEL_V 0x1 -#define GPIO_SIG28_IN_SEL_S 6 -/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG28_IN_SEL_S 7 +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC28_IN_INV_SEL_V 0x1 -#define GPIO_FUNC28_IN_INV_SEL_S 5 -/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC28_IN_SEL 0x0000001F +#define GPIO_FUNC28_IN_SEL 0x0000003F #define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) -#define GPIO_FUNC28_IN_SEL_V 0x1F +#define GPIO_FUNC28_IN_SEL_V 0x3F #define GPIO_FUNC28_IN_SEL_S 0 #define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C8) -/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG29_IN_SEL (BIT(6)) -#define GPIO_SIG29_IN_SEL_M (BIT(6)) +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (BIT(7)) #define GPIO_SIG29_IN_SEL_V 0x1 -#define GPIO_SIG29_IN_SEL_S 6 -/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG29_IN_SEL_S 7 +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC29_IN_INV_SEL_V 0x1 -#define GPIO_FUNC29_IN_INV_SEL_S 5 -/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC29_IN_SEL 0x0000001F +#define GPIO_FUNC29_IN_SEL 0x0000003F #define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) -#define GPIO_FUNC29_IN_SEL_V 0x1F +#define GPIO_FUNC29_IN_SEL_V 0x3F #define GPIO_FUNC29_IN_SEL_S 0 #define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1CC) -/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG30_IN_SEL (BIT(6)) -#define GPIO_SIG30_IN_SEL_M (BIT(6)) +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (BIT(7)) #define GPIO_SIG30_IN_SEL_V 0x1 -#define GPIO_SIG30_IN_SEL_S 6 -/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG30_IN_SEL_S 7 +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC30_IN_INV_SEL_V 0x1 -#define GPIO_FUNC30_IN_INV_SEL_S 5 -/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC30_IN_SEL 0x0000001F +#define GPIO_FUNC30_IN_SEL 0x0000003F #define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) -#define GPIO_FUNC30_IN_SEL_V 0x1F +#define GPIO_FUNC30_IN_SEL_V 0x3F #define GPIO_FUNC30_IN_SEL_S 0 #define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D0) -/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG31_IN_SEL (BIT(6)) -#define GPIO_SIG31_IN_SEL_M (BIT(6)) +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (BIT(7)) #define GPIO_SIG31_IN_SEL_V 0x1 -#define GPIO_SIG31_IN_SEL_S 6 -/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG31_IN_SEL_S 7 +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC31_IN_INV_SEL_V 0x1 -#define GPIO_FUNC31_IN_INV_SEL_S 5 -/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC31_IN_SEL 0x0000001F +#define GPIO_FUNC31_IN_SEL 0x0000003F #define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) -#define GPIO_FUNC31_IN_SEL_V 0x1F +#define GPIO_FUNC31_IN_SEL_V 0x3F #define GPIO_FUNC31_IN_SEL_S 0 #define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D4) -/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG32_IN_SEL (BIT(6)) -#define GPIO_SIG32_IN_SEL_M (BIT(6)) +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (BIT(7)) #define GPIO_SIG32_IN_SEL_V 0x1 -#define GPIO_SIG32_IN_SEL_S 6 -/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG32_IN_SEL_S 7 +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC32_IN_INV_SEL_V 0x1 -#define GPIO_FUNC32_IN_INV_SEL_S 5 -/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC32_IN_SEL 0x0000001F +#define GPIO_FUNC32_IN_SEL 0x0000003F #define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) -#define GPIO_FUNC32_IN_SEL_V 0x1F +#define GPIO_FUNC32_IN_SEL_V 0x3F #define GPIO_FUNC32_IN_SEL_S 0 #define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D8) -/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG33_IN_SEL (BIT(6)) -#define GPIO_SIG33_IN_SEL_M (BIT(6)) +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (BIT(7)) #define GPIO_SIG33_IN_SEL_V 0x1 -#define GPIO_SIG33_IN_SEL_S 6 -/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG33_IN_SEL_S 7 +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC33_IN_INV_SEL_V 0x1 -#define GPIO_FUNC33_IN_INV_SEL_S 5 -/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC33_IN_SEL 0x0000001F +#define GPIO_FUNC33_IN_SEL 0x0000003F #define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) -#define GPIO_FUNC33_IN_SEL_V 0x1F +#define GPIO_FUNC33_IN_SEL_V 0x3F #define GPIO_FUNC33_IN_SEL_S 0 #define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1DC) -/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG34_IN_SEL (BIT(6)) -#define GPIO_SIG34_IN_SEL_M (BIT(6)) +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (BIT(7)) #define GPIO_SIG34_IN_SEL_V 0x1 -#define GPIO_SIG34_IN_SEL_S 6 -/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG34_IN_SEL_S 7 +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC34_IN_INV_SEL_V 0x1 -#define GPIO_FUNC34_IN_INV_SEL_S 5 -/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC34_IN_SEL 0x0000001F +#define GPIO_FUNC34_IN_SEL 0x0000003F #define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) -#define GPIO_FUNC34_IN_SEL_V 0x1F +#define GPIO_FUNC34_IN_SEL_V 0x3F #define GPIO_FUNC34_IN_SEL_S 0 #define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E0) -/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG35_IN_SEL (BIT(6)) -#define GPIO_SIG35_IN_SEL_M (BIT(6)) +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (BIT(7)) #define GPIO_SIG35_IN_SEL_V 0x1 -#define GPIO_SIG35_IN_SEL_S 6 -/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG35_IN_SEL_S 7 +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC35_IN_INV_SEL_V 0x1 -#define GPIO_FUNC35_IN_INV_SEL_S 5 -/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC35_IN_SEL 0x0000001F +#define GPIO_FUNC35_IN_SEL 0x0000003F #define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) -#define GPIO_FUNC35_IN_SEL_V 0x1F +#define GPIO_FUNC35_IN_SEL_V 0x3F #define GPIO_FUNC35_IN_SEL_S 0 #define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E4) -/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG36_IN_SEL (BIT(6)) -#define GPIO_SIG36_IN_SEL_M (BIT(6)) +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (BIT(7)) #define GPIO_SIG36_IN_SEL_V 0x1 -#define GPIO_SIG36_IN_SEL_S 6 -/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG36_IN_SEL_S 7 +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC36_IN_INV_SEL_V 0x1 -#define GPIO_FUNC36_IN_INV_SEL_S 5 -/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC36_IN_INV_SEL_S 6 +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC36_IN_SEL 0x0000001F +#define GPIO_FUNC36_IN_SEL 0x0000003F #define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) -#define GPIO_FUNC36_IN_SEL_V 0x1F +#define GPIO_FUNC36_IN_SEL_V 0x3F #define GPIO_FUNC36_IN_SEL_S 0 #define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E8) -/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG37_IN_SEL (BIT(6)) -#define GPIO_SIG37_IN_SEL_M (BIT(6)) +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (BIT(7)) #define GPIO_SIG37_IN_SEL_V 0x1 -#define GPIO_SIG37_IN_SEL_S 6 -/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG37_IN_SEL_S 7 +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC37_IN_INV_SEL_V 0x1 -#define GPIO_FUNC37_IN_INV_SEL_S 5 -/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC37_IN_INV_SEL_S 6 +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC37_IN_SEL 0x0000001F +#define GPIO_FUNC37_IN_SEL 0x0000003F #define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) -#define GPIO_FUNC37_IN_SEL_V 0x1F +#define GPIO_FUNC37_IN_SEL_V 0x3F #define GPIO_FUNC37_IN_SEL_S 0 #define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1EC) -/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG38_IN_SEL (BIT(6)) -#define GPIO_SIG38_IN_SEL_M (BIT(6)) +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (BIT(7)) #define GPIO_SIG38_IN_SEL_V 0x1 -#define GPIO_SIG38_IN_SEL_S 6 -/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG38_IN_SEL_S 7 +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC38_IN_INV_SEL_V 0x1 -#define GPIO_FUNC38_IN_INV_SEL_S 5 -/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC38_IN_INV_SEL_S 6 +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC38_IN_SEL 0x0000001F +#define GPIO_FUNC38_IN_SEL 0x0000003F #define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) -#define GPIO_FUNC38_IN_SEL_V 0x1F +#define GPIO_FUNC38_IN_SEL_V 0x3F #define GPIO_FUNC38_IN_SEL_S 0 #define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F0) -/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG39_IN_SEL (BIT(6)) -#define GPIO_SIG39_IN_SEL_M (BIT(6)) +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (BIT(7)) #define GPIO_SIG39_IN_SEL_V 0x1 -#define GPIO_SIG39_IN_SEL_S 6 -/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG39_IN_SEL_S 7 +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC39_IN_INV_SEL_V 0x1 -#define GPIO_FUNC39_IN_INV_SEL_S 5 -/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC39_IN_INV_SEL_S 6 +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC39_IN_SEL 0x0000001F +#define GPIO_FUNC39_IN_SEL 0x0000003F #define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) -#define GPIO_FUNC39_IN_SEL_V 0x1F +#define GPIO_FUNC39_IN_SEL_V 0x3F #define GPIO_FUNC39_IN_SEL_S 0 #define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F4) -/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG40_IN_SEL (BIT(6)) -#define GPIO_SIG40_IN_SEL_M (BIT(6)) +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (BIT(7)) #define GPIO_SIG40_IN_SEL_V 0x1 -#define GPIO_SIG40_IN_SEL_S 6 -/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG40_IN_SEL_S 7 +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC40_IN_INV_SEL_V 0x1 -#define GPIO_FUNC40_IN_INV_SEL_S 5 -/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC40_IN_SEL 0x0000001F +#define GPIO_FUNC40_IN_SEL 0x0000003F #define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) -#define GPIO_FUNC40_IN_SEL_V 0x1F +#define GPIO_FUNC40_IN_SEL_V 0x3F #define GPIO_FUNC40_IN_SEL_S 0 #define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F8) -/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG41_IN_SEL (BIT(6)) -#define GPIO_SIG41_IN_SEL_M (BIT(6)) +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (BIT(7)) #define GPIO_SIG41_IN_SEL_V 0x1 -#define GPIO_SIG41_IN_SEL_S 6 -/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG41_IN_SEL_S 7 +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC41_IN_INV_SEL_V 0x1 -#define GPIO_FUNC41_IN_INV_SEL_S 5 -/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC41_IN_SEL 0x0000001F +#define GPIO_FUNC41_IN_SEL 0x0000003F #define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) -#define GPIO_FUNC41_IN_SEL_V 0x1F +#define GPIO_FUNC41_IN_SEL_V 0x3F #define GPIO_FUNC41_IN_SEL_S 0 #define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1FC) -/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG42_IN_SEL (BIT(6)) -#define GPIO_SIG42_IN_SEL_M (BIT(6)) +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (BIT(7)) #define GPIO_SIG42_IN_SEL_V 0x1 -#define GPIO_SIG42_IN_SEL_S 6 -/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG42_IN_SEL_S 7 +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC42_IN_INV_SEL_V 0x1 -#define GPIO_FUNC42_IN_INV_SEL_S 5 -/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC42_IN_SEL 0x0000001F +#define GPIO_FUNC42_IN_SEL 0x0000003F #define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) -#define GPIO_FUNC42_IN_SEL_V 0x1F +#define GPIO_FUNC42_IN_SEL_V 0x3F #define GPIO_FUNC42_IN_SEL_S 0 #define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) -/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG43_IN_SEL (BIT(6)) -#define GPIO_SIG43_IN_SEL_M (BIT(6)) +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (BIT(7)) #define GPIO_SIG43_IN_SEL_V 0x1 -#define GPIO_SIG43_IN_SEL_S 6 -/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG43_IN_SEL_S 7 +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC43_IN_INV_SEL_V 0x1 -#define GPIO_FUNC43_IN_INV_SEL_S 5 -/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC43_IN_INV_SEL_S 6 +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC43_IN_SEL 0x0000001F +#define GPIO_FUNC43_IN_SEL 0x0000003F #define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) -#define GPIO_FUNC43_IN_SEL_V 0x1F +#define GPIO_FUNC43_IN_SEL_V 0x3F #define GPIO_FUNC43_IN_SEL_S 0 #define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) -/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG44_IN_SEL (BIT(6)) -#define GPIO_SIG44_IN_SEL_M (BIT(6)) +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (BIT(7)) #define GPIO_SIG44_IN_SEL_V 0x1 -#define GPIO_SIG44_IN_SEL_S 6 -/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG44_IN_SEL_S 7 +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC44_IN_INV_SEL_V 0x1 -#define GPIO_FUNC44_IN_INV_SEL_S 5 -/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC44_IN_INV_SEL_S 6 +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC44_IN_SEL 0x0000001F +#define GPIO_FUNC44_IN_SEL 0x0000003F #define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) -#define GPIO_FUNC44_IN_SEL_V 0x1F +#define GPIO_FUNC44_IN_SEL_V 0x3F #define GPIO_FUNC44_IN_SEL_S 0 #define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) -/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG45_IN_SEL (BIT(6)) -#define GPIO_SIG45_IN_SEL_M (BIT(6)) +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (BIT(7)) #define GPIO_SIG45_IN_SEL_V 0x1 -#define GPIO_SIG45_IN_SEL_S 6 -/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG45_IN_SEL_S 7 +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC45_IN_INV_SEL_V 0x1 -#define GPIO_FUNC45_IN_INV_SEL_S 5 -/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC45_IN_SEL 0x0000001F +#define GPIO_FUNC45_IN_SEL 0x0000003F #define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) -#define GPIO_FUNC45_IN_SEL_V 0x1F +#define GPIO_FUNC45_IN_SEL_V 0x3F #define GPIO_FUNC45_IN_SEL_S 0 #define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20C) -/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG46_IN_SEL (BIT(6)) -#define GPIO_SIG46_IN_SEL_M (BIT(6)) +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (BIT(7)) #define GPIO_SIG46_IN_SEL_V 0x1 -#define GPIO_SIG46_IN_SEL_S 6 -/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG46_IN_SEL_S 7 +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC46_IN_INV_SEL_V 0x1 -#define GPIO_FUNC46_IN_INV_SEL_S 5 -/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC46_IN_SEL 0x0000001F +#define GPIO_FUNC46_IN_SEL 0x0000003F #define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) -#define GPIO_FUNC46_IN_SEL_V 0x1F +#define GPIO_FUNC46_IN_SEL_V 0x3F #define GPIO_FUNC46_IN_SEL_S 0 #define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) -/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG47_IN_SEL (BIT(6)) -#define GPIO_SIG47_IN_SEL_M (BIT(6)) +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (BIT(7)) #define GPIO_SIG47_IN_SEL_V 0x1 -#define GPIO_SIG47_IN_SEL_S 6 -/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG47_IN_SEL_S 7 +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC47_IN_INV_SEL_V 0x1 -#define GPIO_FUNC47_IN_INV_SEL_S 5 -/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC47_IN_SEL 0x0000001F +#define GPIO_FUNC47_IN_SEL 0x0000003F #define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) -#define GPIO_FUNC47_IN_SEL_V 0x1F +#define GPIO_FUNC47_IN_SEL_V 0x3F #define GPIO_FUNC47_IN_SEL_S 0 #define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) -/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG48_IN_SEL (BIT(6)) -#define GPIO_SIG48_IN_SEL_M (BIT(6)) +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (BIT(7)) #define GPIO_SIG48_IN_SEL_V 0x1 -#define GPIO_SIG48_IN_SEL_S 6 -/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG48_IN_SEL_S 7 +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC48_IN_INV_SEL_V 0x1 -#define GPIO_FUNC48_IN_INV_SEL_S 5 -/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC48_IN_SEL 0x0000001F +#define GPIO_FUNC48_IN_SEL 0x0000003F #define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) -#define GPIO_FUNC48_IN_SEL_V 0x1F +#define GPIO_FUNC48_IN_SEL_V 0x3F #define GPIO_FUNC48_IN_SEL_S 0 #define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) -/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG49_IN_SEL (BIT(6)) -#define GPIO_SIG49_IN_SEL_M (BIT(6)) +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (BIT(7)) #define GPIO_SIG49_IN_SEL_V 0x1 -#define GPIO_SIG49_IN_SEL_S 6 -/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG49_IN_SEL_S 7 +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC49_IN_INV_SEL_V 0x1 -#define GPIO_FUNC49_IN_INV_SEL_S 5 -/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC49_IN_SEL 0x0000001F +#define GPIO_FUNC49_IN_SEL 0x0000003F #define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) -#define GPIO_FUNC49_IN_SEL_V 0x1F +#define GPIO_FUNC49_IN_SEL_V 0x3F #define GPIO_FUNC49_IN_SEL_S 0 #define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21C) -/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG50_IN_SEL (BIT(6)) -#define GPIO_SIG50_IN_SEL_M (BIT(6)) +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (BIT(7)) #define GPIO_SIG50_IN_SEL_V 0x1 -#define GPIO_SIG50_IN_SEL_S 6 -/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG50_IN_SEL_S 7 +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC50_IN_INV_SEL_V 0x1 -#define GPIO_FUNC50_IN_INV_SEL_S 5 -/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC50_IN_SEL 0x0000001F +#define GPIO_FUNC50_IN_SEL 0x0000003F #define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) -#define GPIO_FUNC50_IN_SEL_V 0x1F +#define GPIO_FUNC50_IN_SEL_V 0x3F #define GPIO_FUNC50_IN_SEL_S 0 #define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) -/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG51_IN_SEL (BIT(6)) -#define GPIO_SIG51_IN_SEL_M (BIT(6)) +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (BIT(7)) #define GPIO_SIG51_IN_SEL_V 0x1 -#define GPIO_SIG51_IN_SEL_S 6 -/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG51_IN_SEL_S 7 +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC51_IN_INV_SEL_V 0x1 -#define GPIO_FUNC51_IN_INV_SEL_S 5 -/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC51_IN_SEL 0x0000001F +#define GPIO_FUNC51_IN_SEL 0x0000003F #define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) -#define GPIO_FUNC51_IN_SEL_V 0x1F +#define GPIO_FUNC51_IN_SEL_V 0x3F #define GPIO_FUNC51_IN_SEL_S 0 #define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) -/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG52_IN_SEL (BIT(6)) -#define GPIO_SIG52_IN_SEL_M (BIT(6)) +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (BIT(7)) #define GPIO_SIG52_IN_SEL_V 0x1 -#define GPIO_SIG52_IN_SEL_S 6 -/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG52_IN_SEL_S 7 +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC52_IN_INV_SEL_V 0x1 -#define GPIO_FUNC52_IN_INV_SEL_S 5 -/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC52_IN_SEL 0x0000001F +#define GPIO_FUNC52_IN_SEL 0x0000003F #define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) -#define GPIO_FUNC52_IN_SEL_V 0x1F +#define GPIO_FUNC52_IN_SEL_V 0x3F #define GPIO_FUNC52_IN_SEL_S 0 #define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) -/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG53_IN_SEL (BIT(6)) -#define GPIO_SIG53_IN_SEL_M (BIT(6)) +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (BIT(7)) #define GPIO_SIG53_IN_SEL_V 0x1 -#define GPIO_SIG53_IN_SEL_S 6 -/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG53_IN_SEL_S 7 +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC53_IN_INV_SEL_V 0x1 -#define GPIO_FUNC53_IN_INV_SEL_S 5 -/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC53_IN_SEL 0x0000001F +#define GPIO_FUNC53_IN_SEL 0x0000003F #define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) -#define GPIO_FUNC53_IN_SEL_V 0x1F +#define GPIO_FUNC53_IN_SEL_V 0x3F #define GPIO_FUNC53_IN_SEL_S 0 #define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22C) -/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG54_IN_SEL (BIT(6)) -#define GPIO_SIG54_IN_SEL_M (BIT(6)) +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (BIT(7)) #define GPIO_SIG54_IN_SEL_V 0x1 -#define GPIO_SIG54_IN_SEL_S 6 -/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG54_IN_SEL_S 7 +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC54_IN_INV_SEL_V 0x1 -#define GPIO_FUNC54_IN_INV_SEL_S 5 -/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC54_IN_SEL 0x0000001F +#define GPIO_FUNC54_IN_SEL 0x0000003F #define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) -#define GPIO_FUNC54_IN_SEL_V 0x1F +#define GPIO_FUNC54_IN_SEL_V 0x3F #define GPIO_FUNC54_IN_SEL_S 0 #define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) -/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG55_IN_SEL (BIT(6)) -#define GPIO_SIG55_IN_SEL_M (BIT(6)) +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (BIT(7)) #define GPIO_SIG55_IN_SEL_V 0x1 -#define GPIO_SIG55_IN_SEL_S 6 -/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG55_IN_SEL_S 7 +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC55_IN_INV_SEL_V 0x1 -#define GPIO_FUNC55_IN_INV_SEL_S 5 -/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC55_IN_SEL 0x0000001F +#define GPIO_FUNC55_IN_SEL 0x0000003F #define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) -#define GPIO_FUNC55_IN_SEL_V 0x1F +#define GPIO_FUNC55_IN_SEL_V 0x3F #define GPIO_FUNC55_IN_SEL_S 0 #define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) -/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG56_IN_SEL (BIT(6)) -#define GPIO_SIG56_IN_SEL_M (BIT(6)) +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (BIT(7)) #define GPIO_SIG56_IN_SEL_V 0x1 -#define GPIO_SIG56_IN_SEL_S 6 -/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG56_IN_SEL_S 7 +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC56_IN_INV_SEL_V 0x1 -#define GPIO_FUNC56_IN_INV_SEL_S 5 -/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC56_IN_SEL 0x0000001F +#define GPIO_FUNC56_IN_SEL 0x0000003F #define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) -#define GPIO_FUNC56_IN_SEL_V 0x1F +#define GPIO_FUNC56_IN_SEL_V 0x3F #define GPIO_FUNC56_IN_SEL_S 0 #define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) -/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG57_IN_SEL (BIT(6)) -#define GPIO_SIG57_IN_SEL_M (BIT(6)) +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (BIT(7)) #define GPIO_SIG57_IN_SEL_V 0x1 -#define GPIO_SIG57_IN_SEL_S 6 -/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG57_IN_SEL_S 7 +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC57_IN_INV_SEL_V 0x1 -#define GPIO_FUNC57_IN_INV_SEL_S 5 -/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC57_IN_INV_SEL_S 6 +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC57_IN_SEL 0x0000001F +#define GPIO_FUNC57_IN_SEL 0x0000003F #define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) -#define GPIO_FUNC57_IN_SEL_V 0x1F +#define GPIO_FUNC57_IN_SEL_V 0x3F #define GPIO_FUNC57_IN_SEL_S 0 #define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23C) -/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG58_IN_SEL (BIT(6)) -#define GPIO_SIG58_IN_SEL_M (BIT(6)) +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (BIT(7)) #define GPIO_SIG58_IN_SEL_V 0x1 -#define GPIO_SIG58_IN_SEL_S 6 -/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG58_IN_SEL_S 7 +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC58_IN_INV_SEL_V 0x1 -#define GPIO_FUNC58_IN_INV_SEL_S 5 -/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC58_IN_INV_SEL_S 6 +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC58_IN_SEL 0x0000001F +#define GPIO_FUNC58_IN_SEL 0x0000003F #define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) -#define GPIO_FUNC58_IN_SEL_V 0x1F +#define GPIO_FUNC58_IN_SEL_V 0x3F #define GPIO_FUNC58_IN_SEL_S 0 #define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) -/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG59_IN_SEL (BIT(6)) -#define GPIO_SIG59_IN_SEL_M (BIT(6)) +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (BIT(7)) #define GPIO_SIG59_IN_SEL_V 0x1 -#define GPIO_SIG59_IN_SEL_S 6 -/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG59_IN_SEL_S 7 +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC59_IN_INV_SEL_V 0x1 -#define GPIO_FUNC59_IN_INV_SEL_S 5 -/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC59_IN_INV_SEL_S 6 +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC59_IN_SEL 0x0000001F +#define GPIO_FUNC59_IN_SEL 0x0000003F #define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) -#define GPIO_FUNC59_IN_SEL_V 0x1F +#define GPIO_FUNC59_IN_SEL_V 0x3F #define GPIO_FUNC59_IN_SEL_S 0 #define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) -/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG60_IN_SEL (BIT(6)) -#define GPIO_SIG60_IN_SEL_M (BIT(6)) +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (BIT(7)) #define GPIO_SIG60_IN_SEL_V 0x1 -#define GPIO_SIG60_IN_SEL_S 6 -/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG60_IN_SEL_S 7 +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC60_IN_INV_SEL_V 0x1 -#define GPIO_FUNC60_IN_INV_SEL_S 5 -/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC60_IN_INV_SEL_S 6 +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC60_IN_SEL 0x0000001F +#define GPIO_FUNC60_IN_SEL 0x0000003F #define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) -#define GPIO_FUNC60_IN_SEL_V 0x1F +#define GPIO_FUNC60_IN_SEL_V 0x3F #define GPIO_FUNC60_IN_SEL_S 0 #define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) -/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG61_IN_SEL (BIT(6)) -#define GPIO_SIG61_IN_SEL_M (BIT(6)) +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (BIT(7)) #define GPIO_SIG61_IN_SEL_V 0x1 -#define GPIO_SIG61_IN_SEL_S 6 -/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG61_IN_SEL_S 7 +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC61_IN_INV_SEL_V 0x1 -#define GPIO_FUNC61_IN_INV_SEL_S 5 -/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC61_IN_INV_SEL_S 6 +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC61_IN_SEL 0x0000001F +#define GPIO_FUNC61_IN_SEL 0x0000003F #define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) -#define GPIO_FUNC61_IN_SEL_V 0x1F +#define GPIO_FUNC61_IN_SEL_V 0x3F #define GPIO_FUNC61_IN_SEL_S 0 #define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24C) -/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG62_IN_SEL (BIT(6)) -#define GPIO_SIG62_IN_SEL_M (BIT(6)) +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (BIT(7)) #define GPIO_SIG62_IN_SEL_V 0x1 -#define GPIO_SIG62_IN_SEL_S 6 -/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG62_IN_SEL_S 7 +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC62_IN_INV_SEL_V 0x1 -#define GPIO_FUNC62_IN_INV_SEL_S 5 -/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC62_IN_INV_SEL_S 6 +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC62_IN_SEL 0x0000001F +#define GPIO_FUNC62_IN_SEL 0x0000003F #define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) -#define GPIO_FUNC62_IN_SEL_V 0x1F +#define GPIO_FUNC62_IN_SEL_V 0x3F #define GPIO_FUNC62_IN_SEL_S 0 #define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) -/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG63_IN_SEL (BIT(6)) -#define GPIO_SIG63_IN_SEL_M (BIT(6)) +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (BIT(7)) #define GPIO_SIG63_IN_SEL_V 0x1 -#define GPIO_SIG63_IN_SEL_S 6 -/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG63_IN_SEL_S 7 +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC63_IN_INV_SEL_V 0x1 -#define GPIO_FUNC63_IN_INV_SEL_S 5 -/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC63_IN_SEL 0x0000001F +#define GPIO_FUNC63_IN_SEL 0x0000003F #define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) -#define GPIO_FUNC63_IN_SEL_V 0x1F +#define GPIO_FUNC63_IN_SEL_V 0x3F #define GPIO_FUNC63_IN_SEL_S 0 #define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) -/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG64_IN_SEL (BIT(6)) -#define GPIO_SIG64_IN_SEL_M (BIT(6)) +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (BIT(7)) #define GPIO_SIG64_IN_SEL_V 0x1 -#define GPIO_SIG64_IN_SEL_S 6 -/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG64_IN_SEL_S 7 +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC64_IN_INV_SEL_V 0x1 -#define GPIO_FUNC64_IN_INV_SEL_S 5 -/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC64_IN_SEL 0x0000001F +#define GPIO_FUNC64_IN_SEL 0x0000003F #define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) -#define GPIO_FUNC64_IN_SEL_V 0x1F +#define GPIO_FUNC64_IN_SEL_V 0x3F #define GPIO_FUNC64_IN_SEL_S 0 #define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) -/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG65_IN_SEL (BIT(6)) -#define GPIO_SIG65_IN_SEL_M (BIT(6)) +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (BIT(7)) #define GPIO_SIG65_IN_SEL_V 0x1 -#define GPIO_SIG65_IN_SEL_S 6 -/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG65_IN_SEL_S 7 +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC65_IN_INV_SEL_V 0x1 -#define GPIO_FUNC65_IN_INV_SEL_S 5 -/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC65_IN_SEL 0x0000001F +#define GPIO_FUNC65_IN_SEL 0x0000003F #define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) -#define GPIO_FUNC65_IN_SEL_V 0x1F +#define GPIO_FUNC65_IN_SEL_V 0x3F #define GPIO_FUNC65_IN_SEL_S 0 #define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25C) -/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG66_IN_SEL (BIT(6)) -#define GPIO_SIG66_IN_SEL_M (BIT(6)) +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (BIT(7)) #define GPIO_SIG66_IN_SEL_V 0x1 -#define GPIO_SIG66_IN_SEL_S 6 -/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG66_IN_SEL_S 7 +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC66_IN_INV_SEL_V 0x1 -#define GPIO_FUNC66_IN_INV_SEL_S 5 -/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC66_IN_SEL 0x0000001F +#define GPIO_FUNC66_IN_SEL 0x0000003F #define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) -#define GPIO_FUNC66_IN_SEL_V 0x1F +#define GPIO_FUNC66_IN_SEL_V 0x3F #define GPIO_FUNC66_IN_SEL_S 0 #define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) -/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG67_IN_SEL (BIT(6)) -#define GPIO_SIG67_IN_SEL_M (BIT(6)) +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (BIT(7)) #define GPIO_SIG67_IN_SEL_V 0x1 -#define GPIO_SIG67_IN_SEL_S 6 -/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG67_IN_SEL_S 7 +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC67_IN_INV_SEL_V 0x1 -#define GPIO_FUNC67_IN_INV_SEL_S 5 -/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC67_IN_SEL 0x0000001F +#define GPIO_FUNC67_IN_SEL 0x0000003F #define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) -#define GPIO_FUNC67_IN_SEL_V 0x1F +#define GPIO_FUNC67_IN_SEL_V 0x3F #define GPIO_FUNC67_IN_SEL_S 0 #define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) -/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG68_IN_SEL (BIT(6)) -#define GPIO_SIG68_IN_SEL_M (BIT(6)) +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (BIT(7)) #define GPIO_SIG68_IN_SEL_V 0x1 -#define GPIO_SIG68_IN_SEL_S 6 -/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG68_IN_SEL_S 7 +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC68_IN_INV_SEL_V 0x1 -#define GPIO_FUNC68_IN_INV_SEL_S 5 -/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC68_IN_SEL 0x0000001F +#define GPIO_FUNC68_IN_SEL 0x0000003F #define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) -#define GPIO_FUNC68_IN_SEL_V 0x1F +#define GPIO_FUNC68_IN_SEL_V 0x3F #define GPIO_FUNC68_IN_SEL_S 0 #define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) -/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG69_IN_SEL (BIT(6)) -#define GPIO_SIG69_IN_SEL_M (BIT(6)) +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (BIT(7)) #define GPIO_SIG69_IN_SEL_V 0x1 -#define GPIO_SIG69_IN_SEL_S 6 -/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG69_IN_SEL_S 7 +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC69_IN_INV_SEL_V 0x1 -#define GPIO_FUNC69_IN_INV_SEL_S 5 -/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC69_IN_SEL 0x0000001F +#define GPIO_FUNC69_IN_SEL 0x0000003F #define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) -#define GPIO_FUNC69_IN_SEL_V 0x1F +#define GPIO_FUNC69_IN_SEL_V 0x3F #define GPIO_FUNC69_IN_SEL_S 0 #define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26C) -/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG70_IN_SEL (BIT(6)) -#define GPIO_SIG70_IN_SEL_M (BIT(6)) +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (BIT(7)) #define GPIO_SIG70_IN_SEL_V 0x1 -#define GPIO_SIG70_IN_SEL_S 6 -/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG70_IN_SEL_S 7 +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC70_IN_INV_SEL_V 0x1 -#define GPIO_FUNC70_IN_INV_SEL_S 5 -/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC70_IN_SEL 0x0000001F +#define GPIO_FUNC70_IN_SEL 0x0000003F #define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) -#define GPIO_FUNC70_IN_SEL_V 0x1F +#define GPIO_FUNC70_IN_SEL_V 0x3F #define GPIO_FUNC70_IN_SEL_S 0 #define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) -/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG71_IN_SEL (BIT(6)) -#define GPIO_SIG71_IN_SEL_M (BIT(6)) +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (BIT(7)) #define GPIO_SIG71_IN_SEL_V 0x1 -#define GPIO_SIG71_IN_SEL_S 6 -/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG71_IN_SEL_S 7 +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC71_IN_INV_SEL_V 0x1 -#define GPIO_FUNC71_IN_INV_SEL_S 5 -/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC71_IN_SEL 0x0000001F +#define GPIO_FUNC71_IN_SEL 0x0000003F #define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) -#define GPIO_FUNC71_IN_SEL_V 0x1F +#define GPIO_FUNC71_IN_SEL_V 0x3F #define GPIO_FUNC71_IN_SEL_S 0 #define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) -/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG72_IN_SEL (BIT(6)) -#define GPIO_SIG72_IN_SEL_M (BIT(6)) +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (BIT(7)) #define GPIO_SIG72_IN_SEL_V 0x1 -#define GPIO_SIG72_IN_SEL_S 6 -/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG72_IN_SEL_S 7 +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC72_IN_INV_SEL_V 0x1 -#define GPIO_FUNC72_IN_INV_SEL_S 5 -/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC72_IN_SEL 0x0000001F +#define GPIO_FUNC72_IN_SEL 0x0000003F #define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) -#define GPIO_FUNC72_IN_SEL_V 0x1F +#define GPIO_FUNC72_IN_SEL_V 0x3F #define GPIO_FUNC72_IN_SEL_S 0 #define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) -/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG73_IN_SEL (BIT(6)) -#define GPIO_SIG73_IN_SEL_M (BIT(6)) +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (BIT(7)) #define GPIO_SIG73_IN_SEL_V 0x1 -#define GPIO_SIG73_IN_SEL_S 6 -/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG73_IN_SEL_S 7 +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC73_IN_INV_SEL_V 0x1 -#define GPIO_FUNC73_IN_INV_SEL_S 5 -/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC73_IN_SEL 0x0000001F +#define GPIO_FUNC73_IN_SEL 0x0000003F #define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) -#define GPIO_FUNC73_IN_SEL_V 0x1F +#define GPIO_FUNC73_IN_SEL_V 0x3F #define GPIO_FUNC73_IN_SEL_S 0 #define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27C) -/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG74_IN_SEL (BIT(6)) -#define GPIO_SIG74_IN_SEL_M (BIT(6)) +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (BIT(7)) #define GPIO_SIG74_IN_SEL_V 0x1 -#define GPIO_SIG74_IN_SEL_S 6 -/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG74_IN_SEL_S 7 +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC74_IN_INV_SEL_V 0x1 -#define GPIO_FUNC74_IN_INV_SEL_S 5 -/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC74_IN_INV_SEL_S 6 +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC74_IN_SEL 0x0000001F +#define GPIO_FUNC74_IN_SEL 0x0000003F #define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) -#define GPIO_FUNC74_IN_SEL_V 0x1F +#define GPIO_FUNC74_IN_SEL_V 0x3F #define GPIO_FUNC74_IN_SEL_S 0 #define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) -/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG75_IN_SEL (BIT(6)) -#define GPIO_SIG75_IN_SEL_M (BIT(6)) +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (BIT(7)) #define GPIO_SIG75_IN_SEL_V 0x1 -#define GPIO_SIG75_IN_SEL_S 6 -/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG75_IN_SEL_S 7 +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC75_IN_INV_SEL_V 0x1 -#define GPIO_FUNC75_IN_INV_SEL_S 5 -/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC75_IN_INV_SEL_S 6 +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC75_IN_SEL 0x0000001F +#define GPIO_FUNC75_IN_SEL 0x0000003F #define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) -#define GPIO_FUNC75_IN_SEL_V 0x1F +#define GPIO_FUNC75_IN_SEL_V 0x3F #define GPIO_FUNC75_IN_SEL_S 0 #define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) -/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG76_IN_SEL (BIT(6)) -#define GPIO_SIG76_IN_SEL_M (BIT(6)) +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (BIT(7)) #define GPIO_SIG76_IN_SEL_V 0x1 -#define GPIO_SIG76_IN_SEL_S 6 -/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG76_IN_SEL_S 7 +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC76_IN_INV_SEL_V 0x1 -#define GPIO_FUNC76_IN_INV_SEL_S 5 -/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC76_IN_INV_SEL_S 6 +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC76_IN_SEL 0x0000001F +#define GPIO_FUNC76_IN_SEL 0x0000003F #define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) -#define GPIO_FUNC76_IN_SEL_V 0x1F +#define GPIO_FUNC76_IN_SEL_V 0x3F #define GPIO_FUNC76_IN_SEL_S 0 #define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) -/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG77_IN_SEL (BIT(6)) -#define GPIO_SIG77_IN_SEL_M (BIT(6)) +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (BIT(7)) #define GPIO_SIG77_IN_SEL_V 0x1 -#define GPIO_SIG77_IN_SEL_S 6 -/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG77_IN_SEL_S 7 +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC77_IN_INV_SEL_V 0x1 -#define GPIO_FUNC77_IN_INV_SEL_S 5 -/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC77_IN_SEL 0x0000001F +#define GPIO_FUNC77_IN_SEL 0x0000003F #define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) -#define GPIO_FUNC77_IN_SEL_V 0x1F +#define GPIO_FUNC77_IN_SEL_V 0x3F #define GPIO_FUNC77_IN_SEL_S 0 #define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28C) -/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG78_IN_SEL (BIT(6)) -#define GPIO_SIG78_IN_SEL_M (BIT(6)) +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (BIT(7)) #define GPIO_SIG78_IN_SEL_V 0x1 -#define GPIO_SIG78_IN_SEL_S 6 -/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG78_IN_SEL_S 7 +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC78_IN_INV_SEL_V 0x1 -#define GPIO_FUNC78_IN_INV_SEL_S 5 -/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC78_IN_INV_SEL_S 6 +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC78_IN_SEL 0x0000001F +#define GPIO_FUNC78_IN_SEL 0x0000003F #define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) -#define GPIO_FUNC78_IN_SEL_V 0x1F +#define GPIO_FUNC78_IN_SEL_V 0x3F #define GPIO_FUNC78_IN_SEL_S 0 #define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) -/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG79_IN_SEL (BIT(6)) -#define GPIO_SIG79_IN_SEL_M (BIT(6)) +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (BIT(7)) #define GPIO_SIG79_IN_SEL_V 0x1 -#define GPIO_SIG79_IN_SEL_S 6 -/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG79_IN_SEL_S 7 +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC79_IN_INV_SEL_V 0x1 -#define GPIO_FUNC79_IN_INV_SEL_S 5 -/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC79_IN_INV_SEL_S 6 +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC79_IN_SEL 0x0000001F +#define GPIO_FUNC79_IN_SEL 0x0000003F #define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) -#define GPIO_FUNC79_IN_SEL_V 0x1F +#define GPIO_FUNC79_IN_SEL_V 0x3F #define GPIO_FUNC79_IN_SEL_S 0 #define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) -/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG80_IN_SEL (BIT(6)) -#define GPIO_SIG80_IN_SEL_M (BIT(6)) +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (BIT(7)) #define GPIO_SIG80_IN_SEL_V 0x1 -#define GPIO_SIG80_IN_SEL_S 6 -/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG80_IN_SEL_S 7 +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC80_IN_INV_SEL_V 0x1 -#define GPIO_FUNC80_IN_INV_SEL_S 5 -/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC80_IN_INV_SEL_S 6 +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC80_IN_SEL 0x0000001F +#define GPIO_FUNC80_IN_SEL 0x0000003F #define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) -#define GPIO_FUNC80_IN_SEL_V 0x1F +#define GPIO_FUNC80_IN_SEL_V 0x3F #define GPIO_FUNC80_IN_SEL_S 0 #define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) -/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG81_IN_SEL (BIT(6)) -#define GPIO_SIG81_IN_SEL_M (BIT(6)) +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (BIT(7)) #define GPIO_SIG81_IN_SEL_V 0x1 -#define GPIO_SIG81_IN_SEL_S 6 -/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG81_IN_SEL_S 7 +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC81_IN_INV_SEL_V 0x1 -#define GPIO_FUNC81_IN_INV_SEL_S 5 -/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC81_IN_SEL 0x0000001F +#define GPIO_FUNC81_IN_SEL 0x0000003F #define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) -#define GPIO_FUNC81_IN_SEL_V 0x1F +#define GPIO_FUNC81_IN_SEL_V 0x3F #define GPIO_FUNC81_IN_SEL_S 0 #define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29C) -/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG82_IN_SEL (BIT(6)) -#define GPIO_SIG82_IN_SEL_M (BIT(6)) +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (BIT(7)) #define GPIO_SIG82_IN_SEL_V 0x1 -#define GPIO_SIG82_IN_SEL_S 6 -/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG82_IN_SEL_S 7 +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC82_IN_INV_SEL_V 0x1 -#define GPIO_FUNC82_IN_INV_SEL_S 5 -/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC82_IN_SEL 0x0000001F +#define GPIO_FUNC82_IN_SEL 0x0000003F #define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) -#define GPIO_FUNC82_IN_SEL_V 0x1F +#define GPIO_FUNC82_IN_SEL_V 0x3F #define GPIO_FUNC82_IN_SEL_S 0 #define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A0) -/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG83_IN_SEL (BIT(6)) -#define GPIO_SIG83_IN_SEL_M (BIT(6)) +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (BIT(7)) #define GPIO_SIG83_IN_SEL_V 0x1 -#define GPIO_SIG83_IN_SEL_S 6 -/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG83_IN_SEL_S 7 +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC83_IN_INV_SEL_V 0x1 -#define GPIO_FUNC83_IN_INV_SEL_S 5 -/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC83_IN_SEL 0x0000001F +#define GPIO_FUNC83_IN_SEL 0x0000003F #define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) -#define GPIO_FUNC83_IN_SEL_V 0x1F +#define GPIO_FUNC83_IN_SEL_V 0x3F #define GPIO_FUNC83_IN_SEL_S 0 #define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A4) -/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG84_IN_SEL (BIT(6)) -#define GPIO_SIG84_IN_SEL_M (BIT(6)) +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (BIT(7)) #define GPIO_SIG84_IN_SEL_V 0x1 -#define GPIO_SIG84_IN_SEL_S 6 -/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG84_IN_SEL_S 7 +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC84_IN_INV_SEL_V 0x1 -#define GPIO_FUNC84_IN_INV_SEL_S 5 -/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC84_IN_SEL 0x0000001F +#define GPIO_FUNC84_IN_SEL 0x0000003F #define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) -#define GPIO_FUNC84_IN_SEL_V 0x1F +#define GPIO_FUNC84_IN_SEL_V 0x3F #define GPIO_FUNC84_IN_SEL_S 0 #define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A8) -/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG85_IN_SEL (BIT(6)) -#define GPIO_SIG85_IN_SEL_M (BIT(6)) +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (BIT(7)) #define GPIO_SIG85_IN_SEL_V 0x1 -#define GPIO_SIG85_IN_SEL_S 6 -/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG85_IN_SEL_S 7 +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC85_IN_INV_SEL_V 0x1 -#define GPIO_FUNC85_IN_INV_SEL_S 5 -/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC85_IN_SEL 0x0000001F +#define GPIO_FUNC85_IN_SEL 0x0000003F #define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) -#define GPIO_FUNC85_IN_SEL_V 0x1F +#define GPIO_FUNC85_IN_SEL_V 0x3F #define GPIO_FUNC85_IN_SEL_S 0 #define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2AC) -/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG86_IN_SEL (BIT(6)) -#define GPIO_SIG86_IN_SEL_M (BIT(6)) +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (BIT(7)) #define GPIO_SIG86_IN_SEL_V 0x1 -#define GPIO_SIG86_IN_SEL_S 6 -/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG86_IN_SEL_S 7 +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC86_IN_INV_SEL_V 0x1 -#define GPIO_FUNC86_IN_INV_SEL_S 5 -/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC86_IN_SEL 0x0000001F +#define GPIO_FUNC86_IN_SEL 0x0000003F #define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) -#define GPIO_FUNC86_IN_SEL_V 0x1F +#define GPIO_FUNC86_IN_SEL_V 0x3F #define GPIO_FUNC86_IN_SEL_S 0 #define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B0) -/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG87_IN_SEL (BIT(6)) -#define GPIO_SIG87_IN_SEL_M (BIT(6)) +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (BIT(7)) #define GPIO_SIG87_IN_SEL_V 0x1 -#define GPIO_SIG87_IN_SEL_S 6 -/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG87_IN_SEL_S 7 +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC87_IN_INV_SEL_V 0x1 -#define GPIO_FUNC87_IN_INV_SEL_S 5 -/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC87_IN_SEL 0x0000001F +#define GPIO_FUNC87_IN_SEL 0x0000003F #define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) -#define GPIO_FUNC87_IN_SEL_V 0x1F +#define GPIO_FUNC87_IN_SEL_V 0x3F #define GPIO_FUNC87_IN_SEL_S 0 #define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B4) -/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG88_IN_SEL (BIT(6)) -#define GPIO_SIG88_IN_SEL_M (BIT(6)) +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (BIT(7)) #define GPIO_SIG88_IN_SEL_V 0x1 -#define GPIO_SIG88_IN_SEL_S 6 -/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG88_IN_SEL_S 7 +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC88_IN_INV_SEL_V 0x1 -#define GPIO_FUNC88_IN_INV_SEL_S 5 -/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC88_IN_SEL 0x0000001F +#define GPIO_FUNC88_IN_SEL 0x0000003F #define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) -#define GPIO_FUNC88_IN_SEL_V 0x1F +#define GPIO_FUNC88_IN_SEL_V 0x3F #define GPIO_FUNC88_IN_SEL_S 0 #define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B8) -/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG89_IN_SEL (BIT(6)) -#define GPIO_SIG89_IN_SEL_M (BIT(6)) +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (BIT(7)) #define GPIO_SIG89_IN_SEL_V 0x1 -#define GPIO_SIG89_IN_SEL_S 6 -/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG89_IN_SEL_S 7 +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC89_IN_INV_SEL_V 0x1 -#define GPIO_FUNC89_IN_INV_SEL_S 5 -/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC89_IN_SEL 0x0000001F +#define GPIO_FUNC89_IN_SEL 0x0000003F #define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) -#define GPIO_FUNC89_IN_SEL_V 0x1F +#define GPIO_FUNC89_IN_SEL_V 0x3F #define GPIO_FUNC89_IN_SEL_S 0 #define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2BC) -/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG90_IN_SEL (BIT(6)) -#define GPIO_SIG90_IN_SEL_M (BIT(6)) +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (BIT(7)) #define GPIO_SIG90_IN_SEL_V 0x1 -#define GPIO_SIG90_IN_SEL_S 6 -/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG90_IN_SEL_S 7 +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC90_IN_INV_SEL_V 0x1 -#define GPIO_FUNC90_IN_INV_SEL_S 5 -/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC90_IN_SEL 0x0000001F +#define GPIO_FUNC90_IN_SEL 0x0000003F #define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) -#define GPIO_FUNC90_IN_SEL_V 0x1F +#define GPIO_FUNC90_IN_SEL_V 0x3F #define GPIO_FUNC90_IN_SEL_S 0 #define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C0) -/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG91_IN_SEL (BIT(6)) -#define GPIO_SIG91_IN_SEL_M (BIT(6)) +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (BIT(7)) #define GPIO_SIG91_IN_SEL_V 0x1 -#define GPIO_SIG91_IN_SEL_S 6 -/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG91_IN_SEL_S 7 +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC91_IN_INV_SEL_V 0x1 -#define GPIO_FUNC91_IN_INV_SEL_S 5 -/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC91_IN_SEL 0x0000001F +#define GPIO_FUNC91_IN_SEL 0x0000003F #define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) -#define GPIO_FUNC91_IN_SEL_V 0x1F +#define GPIO_FUNC91_IN_SEL_V 0x3F #define GPIO_FUNC91_IN_SEL_S 0 #define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C4) -/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG92_IN_SEL (BIT(6)) -#define GPIO_SIG92_IN_SEL_M (BIT(6)) +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (BIT(7)) #define GPIO_SIG92_IN_SEL_V 0x1 -#define GPIO_SIG92_IN_SEL_S 6 -/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG92_IN_SEL_S 7 +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC92_IN_INV_SEL_V 0x1 -#define GPIO_FUNC92_IN_INV_SEL_S 5 -/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC92_IN_SEL 0x0000001F +#define GPIO_FUNC92_IN_SEL 0x0000003F #define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) -#define GPIO_FUNC92_IN_SEL_V 0x1F +#define GPIO_FUNC92_IN_SEL_V 0x3F #define GPIO_FUNC92_IN_SEL_S 0 #define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C8) -/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG93_IN_SEL (BIT(6)) -#define GPIO_SIG93_IN_SEL_M (BIT(6)) +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (BIT(7)) #define GPIO_SIG93_IN_SEL_V 0x1 -#define GPIO_SIG93_IN_SEL_S 6 -/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG93_IN_SEL_S 7 +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC93_IN_INV_SEL_V 0x1 -#define GPIO_FUNC93_IN_INV_SEL_S 5 -/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC93_IN_SEL 0x0000001F +#define GPIO_FUNC93_IN_SEL 0x0000003F #define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) -#define GPIO_FUNC93_IN_SEL_V 0x1F +#define GPIO_FUNC93_IN_SEL_V 0x3F #define GPIO_FUNC93_IN_SEL_S 0 #define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2CC) -/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG94_IN_SEL (BIT(6)) -#define GPIO_SIG94_IN_SEL_M (BIT(6)) +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (BIT(7)) #define GPIO_SIG94_IN_SEL_V 0x1 -#define GPIO_SIG94_IN_SEL_S 6 -/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG94_IN_SEL_S 7 +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC94_IN_INV_SEL_V 0x1 -#define GPIO_FUNC94_IN_INV_SEL_S 5 -/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC94_IN_SEL 0x0000001F +#define GPIO_FUNC94_IN_SEL 0x0000003F #define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) -#define GPIO_FUNC94_IN_SEL_V 0x1F +#define GPIO_FUNC94_IN_SEL_V 0x3F #define GPIO_FUNC94_IN_SEL_S 0 #define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D0) -/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG95_IN_SEL (BIT(6)) -#define GPIO_SIG95_IN_SEL_M (BIT(6)) +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (BIT(7)) #define GPIO_SIG95_IN_SEL_V 0x1 -#define GPIO_SIG95_IN_SEL_S 6 -/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG95_IN_SEL_S 7 +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC95_IN_INV_SEL_V 0x1 -#define GPIO_FUNC95_IN_INV_SEL_S 5 -/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC95_IN_SEL 0x0000001F +#define GPIO_FUNC95_IN_SEL 0x0000003F #define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) -#define GPIO_FUNC95_IN_SEL_V 0x1F +#define GPIO_FUNC95_IN_SEL_V 0x3F #define GPIO_FUNC95_IN_SEL_S 0 #define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D4) -/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG96_IN_SEL (BIT(6)) -#define GPIO_SIG96_IN_SEL_M (BIT(6)) +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (BIT(7)) #define GPIO_SIG96_IN_SEL_V 0x1 -#define GPIO_SIG96_IN_SEL_S 6 -/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG96_IN_SEL_S 7 +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC96_IN_INV_SEL_V 0x1 -#define GPIO_FUNC96_IN_INV_SEL_S 5 -/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC96_IN_INV_SEL_S 6 +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC96_IN_SEL 0x0000001F +#define GPIO_FUNC96_IN_SEL 0x0000003F #define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) -#define GPIO_FUNC96_IN_SEL_V 0x1F +#define GPIO_FUNC96_IN_SEL_V 0x3F #define GPIO_FUNC96_IN_SEL_S 0 #define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D8) -/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG97_IN_SEL (BIT(6)) -#define GPIO_SIG97_IN_SEL_M (BIT(6)) +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (BIT(7)) #define GPIO_SIG97_IN_SEL_V 0x1 -#define GPIO_SIG97_IN_SEL_S 6 -/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG97_IN_SEL_S 7 +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC97_IN_INV_SEL_V 0x1 -#define GPIO_FUNC97_IN_INV_SEL_S 5 -/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC97_IN_SEL 0x0000001F +#define GPIO_FUNC97_IN_SEL 0x0000003F #define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) -#define GPIO_FUNC97_IN_SEL_V 0x1F +#define GPIO_FUNC97_IN_SEL_V 0x3F #define GPIO_FUNC97_IN_SEL_S 0 #define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2DC) -/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG98_IN_SEL (BIT(6)) -#define GPIO_SIG98_IN_SEL_M (BIT(6)) +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (BIT(7)) #define GPIO_SIG98_IN_SEL_V 0x1 -#define GPIO_SIG98_IN_SEL_S 6 -/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG98_IN_SEL_S 7 +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC98_IN_INV_SEL_V 0x1 -#define GPIO_FUNC98_IN_INV_SEL_S 5 -/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC98_IN_SEL 0x0000001F +#define GPIO_FUNC98_IN_SEL 0x0000003F #define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) -#define GPIO_FUNC98_IN_SEL_V 0x1F +#define GPIO_FUNC98_IN_SEL_V 0x3F #define GPIO_FUNC98_IN_SEL_S 0 #define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E0) -/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG99_IN_SEL (BIT(6)) -#define GPIO_SIG99_IN_SEL_M (BIT(6)) +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (BIT(7)) #define GPIO_SIG99_IN_SEL_V 0x1 -#define GPIO_SIG99_IN_SEL_S 6 -/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG99_IN_SEL_S 7 +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC99_IN_INV_SEL_V 0x1 -#define GPIO_FUNC99_IN_INV_SEL_S 5 -/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC99_IN_SEL 0x0000001F +#define GPIO_FUNC99_IN_SEL 0x0000003F #define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) -#define GPIO_FUNC99_IN_SEL_V 0x1F +#define GPIO_FUNC99_IN_SEL_V 0x3F #define GPIO_FUNC99_IN_SEL_S 0 #define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E4) -/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG100_IN_SEL (BIT(6)) -#define GPIO_SIG100_IN_SEL_M (BIT(6)) +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (BIT(7)) #define GPIO_SIG100_IN_SEL_V 0x1 -#define GPIO_SIG100_IN_SEL_S 6 -/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG100_IN_SEL_S 7 +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC100_IN_INV_SEL_V 0x1 -#define GPIO_FUNC100_IN_INV_SEL_S 5 -/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC100_IN_SEL 0x0000001F +#define GPIO_FUNC100_IN_SEL 0x0000003F #define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) -#define GPIO_FUNC100_IN_SEL_V 0x1F +#define GPIO_FUNC100_IN_SEL_V 0x3F #define GPIO_FUNC100_IN_SEL_S 0 #define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E8) -/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG101_IN_SEL (BIT(6)) -#define GPIO_SIG101_IN_SEL_M (BIT(6)) +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (BIT(7)) #define GPIO_SIG101_IN_SEL_V 0x1 -#define GPIO_SIG101_IN_SEL_S 6 -/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG101_IN_SEL_S 7 +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC101_IN_INV_SEL_V 0x1 -#define GPIO_FUNC101_IN_INV_SEL_S 5 -/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC101_IN_SEL 0x0000001F +#define GPIO_FUNC101_IN_SEL 0x0000003F #define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) -#define GPIO_FUNC101_IN_SEL_V 0x1F +#define GPIO_FUNC101_IN_SEL_V 0x3F #define GPIO_FUNC101_IN_SEL_S 0 #define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2EC) -/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG102_IN_SEL (BIT(6)) -#define GPIO_SIG102_IN_SEL_M (BIT(6)) +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (BIT(7)) #define GPIO_SIG102_IN_SEL_V 0x1 -#define GPIO_SIG102_IN_SEL_S 6 -/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG102_IN_SEL_S 7 +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC102_IN_INV_SEL_V 0x1 -#define GPIO_FUNC102_IN_INV_SEL_S 5 -/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC102_IN_SEL 0x0000001F +#define GPIO_FUNC102_IN_SEL 0x0000003F #define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) -#define GPIO_FUNC102_IN_SEL_V 0x1F +#define GPIO_FUNC102_IN_SEL_V 0x3F #define GPIO_FUNC102_IN_SEL_S 0 #define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F0) -/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG103_IN_SEL (BIT(6)) -#define GPIO_SIG103_IN_SEL_M (BIT(6)) +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (BIT(7)) #define GPIO_SIG103_IN_SEL_V 0x1 -#define GPIO_SIG103_IN_SEL_S 6 -/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG103_IN_SEL_S 7 +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC103_IN_INV_SEL_V 0x1 -#define GPIO_FUNC103_IN_INV_SEL_S 5 -/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC103_IN_SEL 0x0000001F +#define GPIO_FUNC103_IN_SEL 0x0000003F #define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) -#define GPIO_FUNC103_IN_SEL_V 0x1F +#define GPIO_FUNC103_IN_SEL_V 0x3F #define GPIO_FUNC103_IN_SEL_S 0 #define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F4) -/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG104_IN_SEL (BIT(6)) -#define GPIO_SIG104_IN_SEL_M (BIT(6)) +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (BIT(7)) #define GPIO_SIG104_IN_SEL_V 0x1 -#define GPIO_SIG104_IN_SEL_S 6 -/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG104_IN_SEL_S 7 +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC104_IN_INV_SEL_V 0x1 -#define GPIO_FUNC104_IN_INV_SEL_S 5 -/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC104_IN_SEL 0x0000001F +#define GPIO_FUNC104_IN_SEL 0x0000003F #define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) -#define GPIO_FUNC104_IN_SEL_V 0x1F +#define GPIO_FUNC104_IN_SEL_V 0x3F #define GPIO_FUNC104_IN_SEL_S 0 #define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F8) -/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG105_IN_SEL (BIT(6)) -#define GPIO_SIG105_IN_SEL_M (BIT(6)) +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (BIT(7)) #define GPIO_SIG105_IN_SEL_V 0x1 -#define GPIO_SIG105_IN_SEL_S 6 -/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG105_IN_SEL_S 7 +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC105_IN_INV_SEL_V 0x1 -#define GPIO_FUNC105_IN_INV_SEL_S 5 -/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC105_IN_SEL 0x0000001F +#define GPIO_FUNC105_IN_SEL 0x0000003F #define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) -#define GPIO_FUNC105_IN_SEL_V 0x1F +#define GPIO_FUNC105_IN_SEL_V 0x3F #define GPIO_FUNC105_IN_SEL_S 0 #define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2FC) -/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG106_IN_SEL (BIT(6)) -#define GPIO_SIG106_IN_SEL_M (BIT(6)) +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (BIT(7)) #define GPIO_SIG106_IN_SEL_V 0x1 -#define GPIO_SIG106_IN_SEL_S 6 -/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG106_IN_SEL_S 7 +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC106_IN_INV_SEL_V 0x1 -#define GPIO_FUNC106_IN_INV_SEL_S 5 -/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC106_IN_SEL 0x0000001F +#define GPIO_FUNC106_IN_SEL 0x0000003F #define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) -#define GPIO_FUNC106_IN_SEL_V 0x1F +#define GPIO_FUNC106_IN_SEL_V 0x3F #define GPIO_FUNC106_IN_SEL_S 0 #define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG107_IN_SEL (BIT(6)) -#define GPIO_SIG107_IN_SEL_M (BIT(6)) +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (BIT(7)) #define GPIO_SIG107_IN_SEL_V 0x1 -#define GPIO_SIG107_IN_SEL_S 6 -/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG107_IN_SEL_S 7 +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC107_IN_INV_SEL_V 0x1 -#define GPIO_FUNC107_IN_INV_SEL_S 5 -/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC107_IN_SEL 0x0000001F +#define GPIO_FUNC107_IN_SEL 0x0000003F #define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) -#define GPIO_FUNC107_IN_SEL_V 0x1F +#define GPIO_FUNC107_IN_SEL_V 0x3F #define GPIO_FUNC107_IN_SEL_S 0 #define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG108_IN_SEL (BIT(6)) -#define GPIO_SIG108_IN_SEL_M (BIT(6)) +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (BIT(7)) #define GPIO_SIG108_IN_SEL_V 0x1 -#define GPIO_SIG108_IN_SEL_S 6 -/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG108_IN_SEL_S 7 +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC108_IN_INV_SEL_V 0x1 -#define GPIO_FUNC108_IN_INV_SEL_S 5 -/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC108_IN_SEL 0x0000001F +#define GPIO_FUNC108_IN_SEL 0x0000003F #define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) -#define GPIO_FUNC108_IN_SEL_V 0x1F +#define GPIO_FUNC108_IN_SEL_V 0x3F #define GPIO_FUNC108_IN_SEL_S 0 #define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG109_IN_SEL (BIT(6)) -#define GPIO_SIG109_IN_SEL_M (BIT(6)) +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (BIT(7)) #define GPIO_SIG109_IN_SEL_V 0x1 -#define GPIO_SIG109_IN_SEL_S 6 -/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG109_IN_SEL_S 7 +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC109_IN_INV_SEL_V 0x1 -#define GPIO_FUNC109_IN_INV_SEL_S 5 -/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC109_IN_SEL 0x0000001F +#define GPIO_FUNC109_IN_SEL 0x0000003F #define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) -#define GPIO_FUNC109_IN_SEL_V 0x1F +#define GPIO_FUNC109_IN_SEL_V 0x3F #define GPIO_FUNC109_IN_SEL_S 0 #define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30C) -/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG110_IN_SEL (BIT(6)) -#define GPIO_SIG110_IN_SEL_M (BIT(6)) +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (BIT(7)) #define GPIO_SIG110_IN_SEL_V 0x1 -#define GPIO_SIG110_IN_SEL_S 6 -/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG110_IN_SEL_S 7 +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC110_IN_INV_SEL_V 0x1 -#define GPIO_FUNC110_IN_INV_SEL_S 5 -/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC110_IN_SEL 0x0000001F +#define GPIO_FUNC110_IN_SEL 0x0000003F #define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) -#define GPIO_FUNC110_IN_SEL_V 0x1F +#define GPIO_FUNC110_IN_SEL_V 0x3F #define GPIO_FUNC110_IN_SEL_S 0 #define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) -/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG111_IN_SEL (BIT(6)) -#define GPIO_SIG111_IN_SEL_M (BIT(6)) +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (BIT(7)) #define GPIO_SIG111_IN_SEL_V 0x1 -#define GPIO_SIG111_IN_SEL_S 6 -/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG111_IN_SEL_S 7 +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC111_IN_INV_SEL_V 0x1 -#define GPIO_FUNC111_IN_INV_SEL_S 5 -/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC111_IN_SEL 0x0000001F +#define GPIO_FUNC111_IN_SEL 0x0000003F #define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) -#define GPIO_FUNC111_IN_SEL_V 0x1F +#define GPIO_FUNC111_IN_SEL_V 0x3F #define GPIO_FUNC111_IN_SEL_S 0 #define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) -/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG112_IN_SEL (BIT(6)) -#define GPIO_SIG112_IN_SEL_M (BIT(6)) +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (BIT(7)) #define GPIO_SIG112_IN_SEL_V 0x1 -#define GPIO_SIG112_IN_SEL_S 6 -/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG112_IN_SEL_S 7 +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC112_IN_INV_SEL_V 0x1 -#define GPIO_FUNC112_IN_INV_SEL_S 5 -/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC112_IN_SEL 0x0000001F +#define GPIO_FUNC112_IN_SEL 0x0000003F #define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) -#define GPIO_FUNC112_IN_SEL_V 0x1F +#define GPIO_FUNC112_IN_SEL_V 0x3F #define GPIO_FUNC112_IN_SEL_S 0 #define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) -/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG113_IN_SEL (BIT(6)) -#define GPIO_SIG113_IN_SEL_M (BIT(6)) +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (BIT(7)) #define GPIO_SIG113_IN_SEL_V 0x1 -#define GPIO_SIG113_IN_SEL_S 6 -/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG113_IN_SEL_S 7 +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC113_IN_INV_SEL_V 0x1 -#define GPIO_FUNC113_IN_INV_SEL_S 5 -/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC113_IN_SEL 0x0000001F +#define GPIO_FUNC113_IN_SEL 0x0000003F #define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) -#define GPIO_FUNC113_IN_SEL_V 0x1F +#define GPIO_FUNC113_IN_SEL_V 0x3F #define GPIO_FUNC113_IN_SEL_S 0 #define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31C) -/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG114_IN_SEL (BIT(6)) -#define GPIO_SIG114_IN_SEL_M (BIT(6)) +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (BIT(7)) #define GPIO_SIG114_IN_SEL_V 0x1 -#define GPIO_SIG114_IN_SEL_S 6 -/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG114_IN_SEL_S 7 +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC114_IN_INV_SEL_V 0x1 -#define GPIO_FUNC114_IN_INV_SEL_S 5 -/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC114_IN_SEL 0x0000001F +#define GPIO_FUNC114_IN_SEL 0x0000003F #define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) -#define GPIO_FUNC114_IN_SEL_V 0x1F +#define GPIO_FUNC114_IN_SEL_V 0x3F #define GPIO_FUNC114_IN_SEL_S 0 #define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) -/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG115_IN_SEL (BIT(6)) -#define GPIO_SIG115_IN_SEL_M (BIT(6)) +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (BIT(7)) #define GPIO_SIG115_IN_SEL_V 0x1 -#define GPIO_SIG115_IN_SEL_S 6 -/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG115_IN_SEL_S 7 +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC115_IN_INV_SEL_V 0x1 -#define GPIO_FUNC115_IN_INV_SEL_S 5 -/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC115_IN_SEL 0x0000001F +#define GPIO_FUNC115_IN_SEL 0x0000003F #define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) -#define GPIO_FUNC115_IN_SEL_V 0x1F +#define GPIO_FUNC115_IN_SEL_V 0x3F #define GPIO_FUNC115_IN_SEL_S 0 #define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) -/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG116_IN_SEL (BIT(6)) -#define GPIO_SIG116_IN_SEL_M (BIT(6)) +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (BIT(7)) #define GPIO_SIG116_IN_SEL_V 0x1 -#define GPIO_SIG116_IN_SEL_S 6 -/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG116_IN_SEL_S 7 +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC116_IN_INV_SEL_V 0x1 -#define GPIO_FUNC116_IN_INV_SEL_S 5 -/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC116_IN_SEL 0x0000001F +#define GPIO_FUNC116_IN_SEL 0x0000003F #define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) -#define GPIO_FUNC116_IN_SEL_V 0x1F +#define GPIO_FUNC116_IN_SEL_V 0x3F #define GPIO_FUNC116_IN_SEL_S 0 #define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) -/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG117_IN_SEL (BIT(6)) -#define GPIO_SIG117_IN_SEL_M (BIT(6)) +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (BIT(7)) #define GPIO_SIG117_IN_SEL_V 0x1 -#define GPIO_SIG117_IN_SEL_S 6 -/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG117_IN_SEL_S 7 +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC117_IN_INV_SEL_V 0x1 -#define GPIO_FUNC117_IN_INV_SEL_S 5 -/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC117_IN_SEL 0x0000001F +#define GPIO_FUNC117_IN_SEL 0x0000003F #define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) -#define GPIO_FUNC117_IN_SEL_V 0x1F +#define GPIO_FUNC117_IN_SEL_V 0x3F #define GPIO_FUNC117_IN_SEL_S 0 #define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32C) -/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG118_IN_SEL (BIT(6)) -#define GPIO_SIG118_IN_SEL_M (BIT(6)) +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (BIT(7)) #define GPIO_SIG118_IN_SEL_V 0x1 -#define GPIO_SIG118_IN_SEL_S 6 -/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG118_IN_SEL_S 7 +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC118_IN_INV_SEL_V 0x1 -#define GPIO_FUNC118_IN_INV_SEL_S 5 -/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC118_IN_SEL 0x0000001F +#define GPIO_FUNC118_IN_SEL 0x0000003F #define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) -#define GPIO_FUNC118_IN_SEL_V 0x1F +#define GPIO_FUNC118_IN_SEL_V 0x3F #define GPIO_FUNC118_IN_SEL_S 0 #define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG119_IN_SEL (BIT(6)) -#define GPIO_SIG119_IN_SEL_M (BIT(6)) +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (BIT(7)) #define GPIO_SIG119_IN_SEL_V 0x1 -#define GPIO_SIG119_IN_SEL_S 6 -/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG119_IN_SEL_S 7 +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC119_IN_INV_SEL_V 0x1 -#define GPIO_FUNC119_IN_INV_SEL_S 5 -/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC119_IN_SEL 0x0000001F +#define GPIO_FUNC119_IN_SEL 0x0000003F #define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) -#define GPIO_FUNC119_IN_SEL_V 0x1F +#define GPIO_FUNC119_IN_SEL_V 0x3F #define GPIO_FUNC119_IN_SEL_S 0 #define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG120_IN_SEL (BIT(6)) -#define GPIO_SIG120_IN_SEL_M (BIT(6)) +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (BIT(7)) #define GPIO_SIG120_IN_SEL_V 0x1 -#define GPIO_SIG120_IN_SEL_S 6 -/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG120_IN_SEL_S 7 +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC120_IN_INV_SEL_V 0x1 -#define GPIO_FUNC120_IN_INV_SEL_S 5 -/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC120_IN_SEL 0x0000001F +#define GPIO_FUNC120_IN_SEL 0x0000003F #define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) -#define GPIO_FUNC120_IN_SEL_V 0x1F +#define GPIO_FUNC120_IN_SEL_V 0x3F #define GPIO_FUNC120_IN_SEL_S 0 #define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG121_IN_SEL (BIT(6)) -#define GPIO_SIG121_IN_SEL_M (BIT(6)) +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (BIT(7)) #define GPIO_SIG121_IN_SEL_V 0x1 -#define GPIO_SIG121_IN_SEL_S 6 -/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG121_IN_SEL_S 7 +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC121_IN_INV_SEL_V 0x1 -#define GPIO_FUNC121_IN_INV_SEL_S 5 -/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC121_IN_SEL 0x0000001F +#define GPIO_FUNC121_IN_SEL 0x0000003F #define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) -#define GPIO_FUNC121_IN_SEL_V 0x1F +#define GPIO_FUNC121_IN_SEL_V 0x3F #define GPIO_FUNC121_IN_SEL_S 0 #define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33C) -/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG122_IN_SEL (BIT(6)) -#define GPIO_SIG122_IN_SEL_M (BIT(6)) +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (BIT(7)) #define GPIO_SIG122_IN_SEL_V 0x1 -#define GPIO_SIG122_IN_SEL_S 6 -/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG122_IN_SEL_S 7 +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC122_IN_INV_SEL_V 0x1 -#define GPIO_FUNC122_IN_INV_SEL_S 5 -/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC122_IN_SEL 0x0000001F +#define GPIO_FUNC122_IN_SEL 0x0000003F #define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) -#define GPIO_FUNC122_IN_SEL_V 0x1F +#define GPIO_FUNC122_IN_SEL_V 0x3F #define GPIO_FUNC122_IN_SEL_S 0 #define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG123_IN_SEL (BIT(6)) -#define GPIO_SIG123_IN_SEL_M (BIT(6)) +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (BIT(7)) #define GPIO_SIG123_IN_SEL_V 0x1 -#define GPIO_SIG123_IN_SEL_S 6 -/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG123_IN_SEL_S 7 +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC123_IN_INV_SEL_V 0x1 -#define GPIO_FUNC123_IN_INV_SEL_S 5 -/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC123_IN_SEL 0x0000001F +#define GPIO_FUNC123_IN_SEL 0x0000003F #define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) -#define GPIO_FUNC123_IN_SEL_V 0x1F +#define GPIO_FUNC123_IN_SEL_V 0x3F #define GPIO_FUNC123_IN_SEL_S 0 #define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG124_IN_SEL (BIT(6)) -#define GPIO_SIG124_IN_SEL_M (BIT(6)) +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (BIT(7)) #define GPIO_SIG124_IN_SEL_V 0x1 -#define GPIO_SIG124_IN_SEL_S 6 -/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG124_IN_SEL_S 7 +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC124_IN_INV_SEL_V 0x1 -#define GPIO_FUNC124_IN_INV_SEL_S 5 -/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC124_IN_SEL 0x0000001F +#define GPIO_FUNC124_IN_SEL 0x0000003F #define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) -#define GPIO_FUNC124_IN_SEL_V 0x1F +#define GPIO_FUNC124_IN_SEL_V 0x3F #define GPIO_FUNC124_IN_SEL_S 0 #define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG125_IN_SEL (BIT(6)) -#define GPIO_SIG125_IN_SEL_M (BIT(6)) +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (BIT(7)) #define GPIO_SIG125_IN_SEL_V 0x1 -#define GPIO_SIG125_IN_SEL_S 6 -/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG125_IN_SEL_S 7 +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC125_IN_INV_SEL_V 0x1 -#define GPIO_FUNC125_IN_INV_SEL_S 5 -/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC125_IN_INV_SEL_S 6 +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC125_IN_SEL 0x0000001F +#define GPIO_FUNC125_IN_SEL 0x0000003F #define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) -#define GPIO_FUNC125_IN_SEL_V 0x1F +#define GPIO_FUNC125_IN_SEL_V 0x3F #define GPIO_FUNC125_IN_SEL_S 0 #define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34C) -/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG126_IN_SEL (BIT(6)) -#define GPIO_SIG126_IN_SEL_M (BIT(6)) +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (BIT(7)) #define GPIO_SIG126_IN_SEL_V 0x1 -#define GPIO_SIG126_IN_SEL_S 6 -/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG126_IN_SEL_S 7 +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC126_IN_INV_SEL_V 0x1 -#define GPIO_FUNC126_IN_INV_SEL_S 5 -/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC126_IN_INV_SEL_S 6 +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC126_IN_SEL 0x0000001F +#define GPIO_FUNC126_IN_SEL 0x0000003F #define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) -#define GPIO_FUNC126_IN_SEL_V 0x1F +#define GPIO_FUNC126_IN_SEL_V 0x3F #define GPIO_FUNC126_IN_SEL_S 0 #define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ /*description: */ -#define GPIO_SIG127_IN_SEL (BIT(6)) -#define GPIO_SIG127_IN_SEL_M (BIT(6)) +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (BIT(7)) #define GPIO_SIG127_IN_SEL_V 0x1 -#define GPIO_SIG127_IN_SEL_S 6 -/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ +#define GPIO_SIG127_IN_SEL_S 7 +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ /*description: */ -#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC127_IN_INV_SEL_V 0x1 -#define GPIO_FUNC127_IN_INV_SEL_S 5 -/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC127_IN_INV_SEL_S 6 +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: */ -#define GPIO_FUNC127_IN_SEL 0x0000001F +#define GPIO_FUNC127_IN_SEL 0x0000003F #define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) -#define GPIO_FUNC127_IN_SEL_V 0x1F +#define GPIO_FUNC127_IN_SEL_V 0x3F #define GPIO_FUNC127_IN_SEL_S 0 #define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) @@ -4563,6 +5511,500 @@ extern "C" { #define GPIO_FUNC25_OUT_SEL_V 0xFF #define GPIO_FUNC25_OUT_SEL_S 0 +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5BC) +/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC26_OEN_INV_SEL_S 10 +/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_OEN_SEL (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC26_OEN_SEL_V 0x1 +#define GPIO_FUNC26_OEN_SEL_S 9 +/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC26_OUT_INV_SEL_S 8 +/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC26_OUT_SEL 0x000000FF +#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) +#define GPIO_FUNC26_OUT_SEL_V 0xFF +#define GPIO_FUNC26_OUT_SEL_S 0 + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C0) +/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC27_OEN_INV_SEL_S 10 +/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_OEN_SEL (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC27_OEN_SEL_V 0x1 +#define GPIO_FUNC27_OEN_SEL_S 9 +/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC27_OUT_INV_SEL_S 8 +/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC27_OUT_SEL 0x000000FF +#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) +#define GPIO_FUNC27_OUT_SEL_V 0xFF +#define GPIO_FUNC27_OUT_SEL_S 0 + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C4) +/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC28_OEN_INV_SEL_S 10 +/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_OEN_SEL (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC28_OEN_SEL_V 0x1 +#define GPIO_FUNC28_OEN_SEL_S 9 +/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC28_OUT_INV_SEL_S 8 +/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC28_OUT_SEL 0x000000FF +#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) +#define GPIO_FUNC28_OUT_SEL_V 0xFF +#define GPIO_FUNC28_OUT_SEL_S 0 + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C8) +/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC29_OEN_INV_SEL_S 10 +/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_OEN_SEL (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC29_OEN_SEL_V 0x1 +#define GPIO_FUNC29_OEN_SEL_S 9 +/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC29_OUT_INV_SEL_S 8 +/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC29_OUT_SEL 0x000000FF +#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) +#define GPIO_FUNC29_OUT_SEL_V 0xFF +#define GPIO_FUNC29_OUT_SEL_S 0 + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5CC) +/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC30_OEN_INV_SEL_S 10 +/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_OEN_SEL (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC30_OEN_SEL_V 0x1 +#define GPIO_FUNC30_OEN_SEL_S 9 +/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC30_OUT_INV_SEL_S 8 +/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC30_OUT_SEL 0x000000FF +#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) +#define GPIO_FUNC30_OUT_SEL_V 0xFF +#define GPIO_FUNC30_OUT_SEL_S 0 + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D0) +/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC31_OEN_INV_SEL_S 10 +/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_OEN_SEL (BIT(9)) +#define GPIO_FUNC31_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC31_OEN_SEL_V 0x1 +#define GPIO_FUNC31_OEN_SEL_S 9 +/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC31_OUT_INV_SEL_S 8 +/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC31_OUT_SEL 0x000000FF +#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) +#define GPIO_FUNC31_OUT_SEL_V 0xFF +#define GPIO_FUNC31_OUT_SEL_S 0 + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D4) +/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC32_OEN_INV_SEL_S 10 +/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_OEN_SEL (BIT(9)) +#define GPIO_FUNC32_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC32_OEN_SEL_V 0x1 +#define GPIO_FUNC32_OEN_SEL_S 9 +/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC32_OUT_INV_SEL_S 8 +/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC32_OUT_SEL 0x000000FF +#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) +#define GPIO_FUNC32_OUT_SEL_V 0xFF +#define GPIO_FUNC32_OUT_SEL_S 0 + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D8) +/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC33_OEN_INV_SEL_S 10 +/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_OEN_SEL (BIT(9)) +#define GPIO_FUNC33_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC33_OEN_SEL_V 0x1 +#define GPIO_FUNC33_OEN_SEL_S 9 +/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC33_OUT_INV_SEL_S 8 +/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC33_OUT_SEL 0x000000FF +#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) +#define GPIO_FUNC33_OUT_SEL_V 0xFF +#define GPIO_FUNC33_OUT_SEL_S 0 + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5DC) +/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC34_OEN_INV_SEL_S 10 +/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_OEN_SEL (BIT(9)) +#define GPIO_FUNC34_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC34_OEN_SEL_V 0x1 +#define GPIO_FUNC34_OEN_SEL_S 9 +/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC34_OUT_INV_SEL_S 8 +/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC34_OUT_SEL 0x000000FF +#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) +#define GPIO_FUNC34_OUT_SEL_V 0xFF +#define GPIO_FUNC34_OUT_SEL_S 0 + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E0) +/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC35_OEN_INV_SEL_S 10 +/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_OEN_SEL (BIT(9)) +#define GPIO_FUNC35_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC35_OEN_SEL_V 0x1 +#define GPIO_FUNC35_OEN_SEL_S 9 +/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC35_OUT_INV_SEL_S 8 +/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC35_OUT_SEL 0x000000FF +#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) +#define GPIO_FUNC35_OUT_SEL_V 0xFF +#define GPIO_FUNC35_OUT_SEL_S 0 + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E4) +/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC36_OEN_INV_SEL_S 10 +/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_OEN_SEL (BIT(9)) +#define GPIO_FUNC36_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC36_OEN_SEL_V 0x1 +#define GPIO_FUNC36_OEN_SEL_S 9 +/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC36_OUT_INV_SEL_S 8 +/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC36_OUT_SEL 0x000000FF +#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) +#define GPIO_FUNC36_OUT_SEL_V 0xFF +#define GPIO_FUNC36_OUT_SEL_S 0 + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E8) +/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC37_OEN_INV_SEL_S 10 +/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_OEN_SEL (BIT(9)) +#define GPIO_FUNC37_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC37_OEN_SEL_V 0x1 +#define GPIO_FUNC37_OEN_SEL_S 9 +/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC37_OUT_INV_SEL_S 8 +/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC37_OUT_SEL 0x000000FF +#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) +#define GPIO_FUNC37_OUT_SEL_V 0xFF +#define GPIO_FUNC37_OUT_SEL_S 0 + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5EC) +/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC38_OEN_INV_SEL_S 10 +/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_OEN_SEL (BIT(9)) +#define GPIO_FUNC38_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC38_OEN_SEL_V 0x1 +#define GPIO_FUNC38_OEN_SEL_S 9 +/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC38_OUT_INV_SEL_S 8 +/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC38_OUT_SEL 0x000000FF +#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) +#define GPIO_FUNC38_OUT_SEL_V 0xFF +#define GPIO_FUNC38_OUT_SEL_S 0 + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F0) +/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC39_OEN_INV_SEL_S 10 +/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_OEN_SEL (BIT(9)) +#define GPIO_FUNC39_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC39_OEN_SEL_V 0x1 +#define GPIO_FUNC39_OEN_SEL_S 9 +/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC39_OUT_INV_SEL_S 8 +/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC39_OUT_SEL 0x000000FF +#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) +#define GPIO_FUNC39_OUT_SEL_V 0xFF +#define GPIO_FUNC39_OUT_SEL_S 0 + +#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F4) +/* GPIO_FUNC40_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC40_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC40_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC40_OEN_INV_SEL_S 10 +/* GPIO_FUNC40_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_OEN_SEL (BIT(9)) +#define GPIO_FUNC40_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC40_OEN_SEL_V 0x1 +#define GPIO_FUNC40_OEN_SEL_S 9 +/* GPIO_FUNC40_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC40_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC40_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC40_OUT_INV_SEL_S 8 +/* GPIO_FUNC40_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC40_OUT_SEL 0x000000FF +#define GPIO_FUNC40_OUT_SEL_M ((GPIO_FUNC40_OUT_SEL_V)<<(GPIO_FUNC40_OUT_SEL_S)) +#define GPIO_FUNC40_OUT_SEL_V 0xFF +#define GPIO_FUNC40_OUT_SEL_S 0 + +#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F8) +/* GPIO_FUNC41_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC41_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC41_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC41_OEN_INV_SEL_S 10 +/* GPIO_FUNC41_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_OEN_SEL (BIT(9)) +#define GPIO_FUNC41_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC41_OEN_SEL_V 0x1 +#define GPIO_FUNC41_OEN_SEL_S 9 +/* GPIO_FUNC41_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC41_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC41_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC41_OUT_INV_SEL_S 8 +/* GPIO_FUNC41_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC41_OUT_SEL 0x000000FF +#define GPIO_FUNC41_OUT_SEL_M ((GPIO_FUNC41_OUT_SEL_V)<<(GPIO_FUNC41_OUT_SEL_S)) +#define GPIO_FUNC41_OUT_SEL_V 0xFF +#define GPIO_FUNC41_OUT_SEL_S 0 + +#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5FC) +/* GPIO_FUNC42_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC42_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC42_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC42_OEN_INV_SEL_S 10 +/* GPIO_FUNC42_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_OEN_SEL (BIT(9)) +#define GPIO_FUNC42_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC42_OEN_SEL_V 0x1 +#define GPIO_FUNC42_OEN_SEL_S 9 +/* GPIO_FUNC42_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC42_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC42_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC42_OUT_INV_SEL_S 8 +/* GPIO_FUNC42_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC42_OUT_SEL 0x000000FF +#define GPIO_FUNC42_OUT_SEL_M ((GPIO_FUNC42_OUT_SEL_V)<<(GPIO_FUNC42_OUT_SEL_S)) +#define GPIO_FUNC42_OUT_SEL_V 0xFF +#define GPIO_FUNC42_OUT_SEL_S 0 + +#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) +/* GPIO_FUNC43_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC43_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC43_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC43_OEN_INV_SEL_S 10 +/* GPIO_FUNC43_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_OEN_SEL (BIT(9)) +#define GPIO_FUNC43_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC43_OEN_SEL_V 0x1 +#define GPIO_FUNC43_OEN_SEL_S 9 +/* GPIO_FUNC43_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC43_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC43_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC43_OUT_INV_SEL_S 8 +/* GPIO_FUNC43_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC43_OUT_SEL 0x000000FF +#define GPIO_FUNC43_OUT_SEL_M ((GPIO_FUNC43_OUT_SEL_V)<<(GPIO_FUNC43_OUT_SEL_S)) +#define GPIO_FUNC43_OUT_SEL_V 0xFF +#define GPIO_FUNC43_OUT_SEL_S 0 + +#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) +/* GPIO_FUNC44_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC44_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC44_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC44_OEN_INV_SEL_S 10 +/* GPIO_FUNC44_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_OEN_SEL (BIT(9)) +#define GPIO_FUNC44_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC44_OEN_SEL_V 0x1 +#define GPIO_FUNC44_OEN_SEL_S 9 +/* GPIO_FUNC44_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC44_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC44_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC44_OUT_INV_SEL_S 8 +/* GPIO_FUNC44_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ +/*description: */ +#define GPIO_FUNC44_OUT_SEL 0x000000FF +#define GPIO_FUNC44_OUT_SEL_M ((GPIO_FUNC44_OUT_SEL_V)<<(GPIO_FUNC44_OUT_SEL_S)) +#define GPIO_FUNC44_OUT_SEL_V 0xFF +#define GPIO_FUNC44_OUT_SEL_S 0 + #define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62C) /* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ @@ -4572,7 +6014,7 @@ extern "C" { #define GPIO_CLK_EN_S 0 #define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) -/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */ +/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */ /*description: */ #define GPIO_DATE 0x0FFFFFFF #define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) diff --git a/components/soc/esp32h2/include/soc/gpio_sig_map.h b/components/soc/esp32h2/include/soc/gpio_sig_map.h index 45be68b3e5..ca4b29f643 100644 --- a/components/soc/esp32h2/include/soc/gpio_sig_map.h +++ b/components/soc/esp32h2/include/soc/gpio_sig_map.h @@ -49,30 +49,38 @@ #define I2SI_BCK_OUT_IDX 16 #define I2SI_WS_IN_IDX 17 #define I2SI_WS_OUT_IDX 17 -#define GPIO_BT_PRIORITY_IDX 18 -#define GPIO_WLAN_PRIO_IDX 18 -#define GPIO_BT_ACTIVE_IDX 19 -#define GPIO_WLAN_ACTIVE_IDX 19 -#define BB_DIAG0_IDX 20 -#define BB_DIAG1_IDX 21 -#define BB_DIAG2_IDX 22 -#define BB_DIAG3_IDX 23 -#define BB_DIAG4_IDX 24 -#define BB_DIAG5_IDX 25 -#define BB_DIAG6_IDX 26 -#define BB_DIAG7_IDX 27 -#define BB_DIAG8_IDX 28 -#define BB_DIAG9_IDX 29 -#define BB_DIAG10_IDX 30 -#define BB_DIAG11_IDX 31 -#define BB_DIAG12_IDX 32 -#define BB_DIAG13_IDX 33 -#define BB_DIAG14_IDX 34 -#define BB_DIAG15_IDX 35 -#define BB_DIAG16_IDX 36 -#define BB_DIAG17_IDX 37 -#define BB_DIAG18_IDX 38 -#define BB_DIAG19_IDX 39 +#define CO_EXT_PRIORITY_IN_IDX 18 +#define I2SO_SD1_OUT_IDX 18 +#define CO_EXT_ACTIVE_IN_IDX 19 +#define CO_EXT_ACTIVE_OUT_IDX 19 +#define CPU_TESTBUS0_IDX 20 +#define CPU_TESTBUS1_IDX 21 +#define CPU_TESTBUS2_IDX 22 +#define CPU_TESTBUS3_IDX 23 +#define CPU_TESTBUS4_IDX 24 +#define CPU_TESTBUS5_IDX 25 +#define CPU_TESTBUS6_IDX 26 +#define CPU_TESTBUS7_IDX 27 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define USB_JTAG_TCK_IDX 36 +#define USB_JTAG_TMS_IDX 37 +#define USB_JTAG_TDI_IDX 38 +#define USB_JTAG_TDO_IDX 39 #define USB_EXTPHY_VP_IDX 40 #define USB_EXTPHY_OEN_IDX 40 #define USB_EXTPHY_VM_IDX 41 @@ -100,6 +108,14 @@ #define GPIO_SD1_OUT_IDX 56 #define GPIO_SD2_OUT_IDX 57 #define GPIO_SD3_OUT_IDX 58 +#define EVENT_MATRIX_IN0_IDX 59 +#define TASK_MATRIX_OUT0_IDX 59 +#define EVENT_MATRIX_IN1_IDX 60 +#define TASK_MATRIX_OUT1_IDX 60 +#define EVENT_MATRIX_IN2_IDX 61 +#define TASK_MATRIX_OUT2_IDX 61 +#define EVENT_MATRIX_IN3_IDX 62 +#define TASK_MATRIX_OUT3_IDX 62 #define FSPICLK_IN_IDX 63 #define FSPICLK_OUT_IDX 63 #define FSPIQ_IN_IDX 64 @@ -155,30 +171,26 @@ #define SIG_IN_FUNC100_IDX 100 #define SYNCERR_IDX 101 #define SYNCFOUND_FLAG_IDX 102 -#define EVT_CNTL_IMMEDIATE_ABORT_IDX 103 -#define LINKLBL_IDX 104 +#define CH_IDX_IDX 103 +#define RX_WINDOW_IDX 104 #define DATA_EN_IDX 105 #define DATA_IDX 106 #define PKT_TX_ON_IDX 107 #define PKT_RX_ON_IDX 108 -#define RW_TX_ON_IDX 109 -#define RW_RX_ON_IDX 110 -#define EVT_REQ_P_IDX 111 -#define EVT_STOP_P_IDX 112 -#define BT_MODE_ON_IDX 113 -#define GPIO_LC_DIAG0_IDX 114 -#define GPIO_LC_DIAG1_IDX 115 -#define GPIO_LC_DIAG2_IDX 116 -#define CH_IDX_IDX 117 -#define RX_WINDOW_IDX 118 -#define UPDATE_RX_IDX 119 -#define RX_STATUS_IDX 120 -#define CLK_GPIO_IDX 121 -#define NBT_BLE_IDX 122 +#define TXRU_ON_IDX 109 +#define RXRU_ON_IDX 110 +#define LELC_ST3_IDX 111 +#define LELC_ST2_IDX 112 +#define LELC_ST1_IDX 113 +#define LELC_ST0_IDX 114 +#define CRCOK_IDX 115 +#define CLK_GPIO_IDX 116 +#define RADIO_START_IDX 117 #define CLK_OUT_OUT1_IDX 123 #define CLK_OUT_OUT2_IDX 124 #define CLK_OUT_OUT3_IDX 125 #define SPICS1_OUT_IDX 126 +#define USB_JTAG_TRST_IDX 127 #define SIG_GPIO_OUT_IDX 128 #define GPIO_MAP_DATE_IDX 0x2006130 #endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32h2/include/soc/i2s_caps.h b/components/soc/esp32h2/include/soc/i2s_caps.h new file mode 100644 index 0000000000..69dfb68373 --- /dev/null +++ b/components/soc/esp32h2/include/soc/i2s_caps.h @@ -0,0 +1,22 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_I2S_APLL_MIN_FREQ (250000000) +#define SOC_I2S_APLL_MAX_FREQ (500000000) +#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware +#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated + +#define SOC_I2S_NUM (1) diff --git a/components/soc/esp32h2/include/soc/i2s_reg.h b/components/soc/esp32h2/include/soc/i2s_reg.h index a5c4ed3e35..821a4a69a3 100644 --- a/components/soc/esp32h2/include/soc/i2s_reg.h +++ b/components/soc/esp32h2/include/soc/i2s_reg.h @@ -124,6 +124,18 @@ extern "C" { #define I2S_RX_DONE_INT_CLR_S 0 #define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) +/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22)) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 +#define I2S_RX_PDM_SINC_DSR_16_EN_S 22 +/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: 1: Enable PDM2PCM RX mode. 0: DIsable.*/ +#define I2S_RX_PDM2PCM_EN (BIT(21)) +#define I2S_RX_PDM2PCM_EN_M (BIT(21)) +#define I2S_RX_PDM2PCM_EN_V 0x1 +#define I2S_RX_PDM2PCM_EN_S 21 /* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ /*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/ #define I2S_RX_PDM_EN (BIT(20)) @@ -935,6 +947,27 @@ T12_5[2:0]).*/ #define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S)) #define I2S_RX_WS_OUT_DM_V 0x3 #define I2S_RX_WS_OUT_DM_S 16 +/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD3_IN_DM 0x00000003 +#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V)<<(I2S_RX_SD3_IN_DM_S)) +#define I2S_RX_SD3_IN_DM_V 0x3 +#define I2S_RX_SD3_IN_DM_S 12 +/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD2_IN_DM 0x00000003 +#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V)<<(I2S_RX_SD2_IN_DM_S)) +#define I2S_RX_SD2_IN_DM_V 0x3 +#define I2S_RX_SD2_IN_DM_S 8 +/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD1_IN_DM 0x00000003 +#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V)<<(I2S_RX_SD1_IN_DM_S)) +#define I2S_RX_SD1_IN_DM_V 0x3 +#define I2S_RX_SD1_IN_DM_S 4 /* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/include/soc/i2s_struct.h index 2f9c862b85..9d3537004c 100644 --- a/components/soc/esp32h2/include/soc/i2s_struct.h +++ b/components/soc/esp32h2/include/soc/i2s_struct.h @@ -83,7 +83,9 @@ typedef volatile struct { uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/ uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/ uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/ - uint32_t reserved23: 11; /*Reserve*/ + uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/ + uint32_t rx_sinc_dsr_16_en: 1; + uint32_t reserved23: 9; /*Reserve*/ }; uint32_t val; } rx_conf; @@ -136,8 +138,7 @@ typedef volatile struct { uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/ uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/ uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/ - uint32_t tx_bck_no_dly: 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/ - uint32_t reserved31: 1; /* Reserved*/ + uint32_t reserved30: 2; /*Reserved*/ }; uint32_t val; } tx_conf1; @@ -263,7 +264,13 @@ typedef volatile struct { union { struct { uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved2 : 14; /* Reserved*/ + uint32_t reserved2: 2; + uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved6: 2; + uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved10: 2; + uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved14: 2; uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ uint32_t reserved18: 2; uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ @@ -277,18 +284,16 @@ typedef volatile struct { } rx_timing; union { struct { - uint32_t tx_sd_out_dm : 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved2 : 2; /* Reserved*/ - uint32_t tx_sd1_out_dm : 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved6 : 10; /* Reserved*/ - uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved18 : 2; /* Reserved*/ - uint32_t tx_bck_out_dm : 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved22 : 2; /* Reserved*/ - uint32_t tx_ws_in_dm : 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved26 : 2; /* Reserved*/ - uint32_t tx_bck_in_dm : 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved30 : 2; /* Reserved*/ + uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved2: 14; /*Reserved*/ + uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18: 2; + uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22: 2; + uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26: 2; + uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30: 2; }; uint32_t val; } tx_timing; @@ -329,6 +334,7 @@ typedef volatile struct { } date; } i2s_dev_t; extern i2s_dev_t I2S0; + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/include/soc/interrupt_core0_reg.h b/components/soc/esp32h2/include/soc/interrupt_core0_reg.h index f606cdafca..2864335f87 100644 --- a/components/soc/esp32h2/include/soc/interrupt_core0_reg.h +++ b/components/soc/esp32h2/include/soc/interrupt_core0_reg.h @@ -518,7 +518,63 @@ extern "C" { #define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F #define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) +/* INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG3_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M ((INTERRUPT_CORE0_TG3_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG3_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) +/* INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG3_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S)) +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/* INTERRUPT_CORE0_IEEE802154MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_M ((INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V)<<(INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S)) +#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/* INTERRUPT_CORE0_IEEE802154BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_M ((INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V)<<(INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S)) +#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) +/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S)) +#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_COEX_INT_MAP_S 0 + +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/* INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M ((INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V)<<(INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S)) +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) /* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF @@ -526,7 +582,7 @@ extern "C" { #define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF #define INTERRUPT_CORE0_INTR_STATUS_0_S 0 -#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) +#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) /* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF @@ -534,7 +590,15 @@ extern "C" { #define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF #define INTERRUPT_CORE0_INTR_STATUS_1_S 0 -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S)) +#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 + +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) /* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define INTERRUPT_CORE0_CLK_EN (BIT(0)) @@ -542,7 +606,7 @@ extern "C" { #define INTERRUPT_CORE0_CLK_EN_V 0x1 #define INTERRUPT_CORE0_CLK_EN_S 0 -#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) /* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF @@ -550,7 +614,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF #define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0 -#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) /* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF @@ -558,7 +622,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF #define INTERRUPT_CORE0_CPU_INT_TYPE_S 0 -#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) /* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF @@ -566,7 +630,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF #define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0 -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) /* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF @@ -574,7 +638,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF #define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) /* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F @@ -582,7 +646,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) /* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F @@ -590,7 +654,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) /* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F @@ -598,7 +662,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) /* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F @@ -606,7 +670,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) /* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F @@ -614,7 +678,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) /* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F @@ -622,7 +686,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) +#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) /* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F @@ -630,7 +694,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) /* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F @@ -638,7 +702,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) /* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F @@ -646,7 +710,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) /* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F @@ -654,7 +718,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) +#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) /* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F @@ -662,7 +726,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) /* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F @@ -670,7 +734,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) /* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F @@ -678,7 +742,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) /* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F @@ -686,7 +750,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) +#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) /* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F @@ -694,7 +758,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) /* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F @@ -702,7 +766,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) /* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F @@ -710,7 +774,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) /* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F @@ -718,7 +782,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) +#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) /* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F @@ -726,7 +790,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) /* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F @@ -734,7 +798,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) /* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F @@ -742,7 +806,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) /* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F @@ -750,7 +814,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) +#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) /* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F @@ -758,7 +822,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) /* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F @@ -766,7 +830,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) /* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F @@ -774,7 +838,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) /* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F @@ -782,7 +846,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) +#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19C) /* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F @@ -790,7 +854,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0) /* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F @@ -798,7 +862,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4) /* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F @@ -806,7 +870,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8) /* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F @@ -814,7 +878,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) +#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC) /* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F @@ -822,7 +886,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF #define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0 -#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0) /* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F @@ -831,7 +895,7 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0 #define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) -#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4) /* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ #define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F @@ -840,13 +904,14 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INT_THRESH_S 0 #define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) -/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */ +/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2011090 ; */ /*description: */ #define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF #define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S)) #define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF #define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 +#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/include/soc/io_mux_reg.h index 3f338ea92d..006c0fa732 100644 --- a/components/soc/esp32h2/include/soc/io_mux_reg.h +++ b/components/soc/esp32h2/include/soc/io_mux_reg.h @@ -116,6 +116,30 @@ #define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U #define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U #define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_GPIO28_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_GPIO30_U +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_GPIO31_U +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U +#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_GPIO40_U +#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_GPIO41_U +#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_GPIO42_U +#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_GPIO43_U +#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_GPIO44_U +#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U /* Value to set in IO Mux to use a pin as GPIO. */ #define PIN_FUNC_GPIO 1 @@ -266,9 +290,85 @@ #define FUNC_U0TXD_GPIO21 1 #define FUNC_U0TXD_U0TXD 0 +#define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE +0x5c) +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE +0x60) +#define FUNC_GPIO23_GPIO23 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE +0x64) +#define FUNC_GPIO24_GPIO24 1 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE +0x68) +#define FUNC_GPIO25_GPIO25 1 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE +0x6c) +#define FUNC_GPIO26_GPIO26 1 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE +0x70) +#define FUNC_GPIO27_GPIO27 1 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO28_U (REG_IO_MUX_BASE +0x74) +#define FUNC_GPIO28_GPIO28 1 +#define FUNC_GPIO28_GPIO28_0 0 + +#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE +0x78) +#define FUNC_GPIO29_GPIO29 1 +#define FUNC_GPIO29_GPIO29_0 0 + +#define PERIPHS_IO_MUX_GPIO30_U (REG_IO_MUX_BASE +0x7c) +#define FUNC_GPIO30_GPIO30 1 +#define FUNC_GPIO30_GPIO30_0 0 + +#define PERIPHS_IO_MUX_GPIO31_U (REG_IO_MUX_BASE +0x80) +#define FUNC_GPIO31_GPIO31 1 +#define FUNC_GPIO31_GPIO31_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (REG_IO_MUX_BASE +0x84) +#define FUNC_GPIO32_GPIO32 1 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (REG_IO_MUX_BASE +0xa0) +#define FUNC_GPIO39_GPIO39 1 +#define FUNC_GPIO39_GPIO39_0 0 + +#define PERIPHS_IO_MUX_GPIO40_U (REG_IO_MUX_BASE +0xa4) +#define FUNC_GPIO40_GPIO40 1 +#define FUNC_GPIO40_GPIO40_0 0 + #define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) #define IO_MUX_DATE 0xFFFFFFFF #define IO_MUX_DATE_S 0 -#define IO_MUX_DATE_VERSION 0x2006050 +#define IO_MUX_DATE_VERSION 0x2012310 #endif diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h index da304aef31..fe14929998 100644 --- a/components/soc/esp32h2/include/soc/periph_defs.h +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -112,6 +112,13 @@ typedef enum { ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, ETS_BAK_PMS_VIOLATE_INTR_SOURCE, ETS_CACHE_CORE0_ACS_INTR_SOURCE, + ETS_TG3_TO_INTR_SOURCE, + ETS_TG3_WDT_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_IEEE802154MAC_INTR_SOURCE, + ETS_IEEE802154BB_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_RTC_BLE_INTR_SOURCE, ETS_MAX_INTR_SOURCE, } periph_interrput_t; diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index 3fda6cb8a7..68ffd792d6 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -69,15 +69,21 @@ extern "C" { * Valid if RTC_CNTL_DBG_ATTEN is 0. */ #define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias -#define RTC_CNTL_DBIAS_0V90 13 //digital voltage -#define RTC_CNTL_DBIAS_0V95 16 -#define RTC_CNTL_DBIAS_1V00 18 -#define RTC_CNTL_DBIAS_1V05 20 -#define RTC_CNTL_DBIAS_1V10 23 -#define RTC_CNTL_DBIAS_1V15 25 -#define RTC_CNTL_DBIAS_1V20 28 -#define RTC_CNTL_DBIAS_1V25 30 -#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact +#define RTC_CNTL_DBIAS_1V00 0 +#define RTC_CNTL_DBIAS_1V05 4 +#define RTC_CNTL_DBIAS_1V10 5 +#define RTC_CNTL_DBIAS_1V15 6 +#define RTC_CNTL_DBIAS_1V20 7 +/* The value of 1V00 can be adjusted between 0~3*/ + +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 #define DELAY_FAST_CLK_SWITCH 3 #define DELAY_SLOW_CLK_SWITCH 300 @@ -122,15 +128,6 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 -/* -The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value -storing in efuse (based on ATE 5k ECO3 chips) -*/ -#define K_RTC_MID_MUL10000 215 -#define K_DIG_MID_MUL10000 213 -#define V_RTC_MID_MUL10000 10800 -#define V_DIG_MID_MUL10000 10860 - /** * @brief Possible main XTAL frequency values. * diff --git a/components/soc/esp32h2/include/soc/rtc_caps.h b/components/soc/esp32h2/include/soc/rtc_caps.h new file mode 100644 index 0000000000..aa71a3ec2b --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc_caps.h @@ -0,0 +1,22 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128) +#define RTC_CNTL_CPU_PD_REG_FILE_NUM (108) +#define RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) +#define RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) + +#define RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (RTC_CNTL_CPU_PD_REG_FILE_NUM * (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_reg.h b/components/soc/esp32h2/include/soc/rtc_cntl_reg.h index b25f644832..981c630fc3 100644 --- a/components/soc/esp32h2/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32h2/include/soc/rtc_cntl_reg.h @@ -98,6 +98,18 @@ extern "C" { #define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) #define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 #define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 +/* RTC_CNTL_XPD_RFPLL_FORCE : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XPD_RFPLL_FORCE (BIT(19)) +#define RTC_CNTL_XPD_RFPLL_FORCE_M (BIT(19)) +#define RTC_CNTL_XPD_RFPLL_FORCE_V 0x1 +#define RTC_CNTL_XPD_RFPLL_FORCE_S 19 +/* RTC_CNTL_XPD_RFPLL : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XPD_RFPLL (BIT(18)) +#define RTC_CNTL_XPD_RFPLL_M (BIT(18)) +#define RTC_CNTL_XPD_RFPLL_V 0x1 +#define RTC_CNTL_XPD_RFPLL_S 18 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ /*description: wait bias_sleep and current source wakeup*/ #define RTC_CNTL_XTL_EN_WAIT 0x0000000F @@ -478,6 +490,18 @@ extern "C" { #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 +/* RTC_CNTL_XPD_TRX_FORCE_PU : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_XPD_TRX_FORCE_PU (BIT(17)) +#define RTC_CNTL_XPD_TRX_FORCE_PU_M (BIT(17)) +#define RTC_CNTL_XPD_TRX_FORCE_PU_V 0x1 +#define RTC_CNTL_XPD_TRX_FORCE_PU_S 17 +/* RTC_CNTL_XPD_TRX_FORCE_PD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XPD_TRX_FORCE_PD (BIT(16)) +#define RTC_CNTL_XPD_TRX_FORCE_PD_M (BIT(16)) +#define RTC_CNTL_XPD_TRX_FORCE_PD_V 0x1 +#define RTC_CNTL_XPD_TRX_FORCE_PD_S 16 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) /* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ @@ -578,14 +602,26 @@ extern "C" { #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) -/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:13] ;default: 18'b1100 ; */ /*description: wakeup enable bitmap*/ -#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA 0x0007FFFF #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) -#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF -#define RTC_CNTL_WAKEUP_ENA_S 15 +#define RTC_CNTL_WAKEUP_ENA_V 0x7FFFF +#define RTC_CNTL_WAKEUP_ENA_S 13 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA : ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_S 21 /* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) @@ -642,6 +678,18 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +/* RTC_CNTL_VSET_DCDC_DONE_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_S 21 /* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) @@ -698,6 +746,18 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_S 21 /* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) @@ -754,6 +814,18 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +/* RTC_CNTL_VSET_DCDC_DONE_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_S 21 /* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) @@ -972,12 +1044,12 @@ extern "C" { #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 -/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:11] ;default: 18'd0 ; */ /*description: sleep reject enable*/ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0007FFFF #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) -#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x7FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 11 #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ @@ -1030,66 +1102,48 @@ extern "C" { #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 #define RTC_CNTL_CK8M_FORCE_PD_S 25 -/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:15] ;default: 10'd600 ; */ /*description: CK8M_DFREQ*/ -#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ 0x000003FF #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) -#define RTC_CNTL_CK8M_DFREQ_V 0xFF -#define RTC_CNTL_CK8M_DFREQ_S 17 -/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +#define RTC_CNTL_CK8M_DFREQ_V 0x3FF +#define RTC_CNTL_CK8M_DFREQ_S 15 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[14] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(14)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(14)) #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 -/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 14 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[13] ;default: 1'd0 ; */ /*description: XTAL force no gating during sleep*/ -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(13)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(13)) #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 -/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 13 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ /*description: divider = reg_ck8m_div_sel + 1*/ #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 -#define RTC_CNTL_CK8M_DIV_SEL_S 12 -/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +#define RTC_CNTL_CK8M_DIV_SEL_S 10 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[6] ;default: 1'd0 ; */ /*description: enable CK8M for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN (BIT(6)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(6)) #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_EN_S 10 -/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 -/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +#define RTC_CNTL_DIG_CLK8M_EN_S 6 +/* RTC_CNTL_DIG_RC32K_EN : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: enable RC32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_RC32K_EN (BIT(5)) +#define RTC_CNTL_DIG_RC32K_EN_M (BIT(5)) +#define RTC_CNTL_DIG_RC32K_EN_V 0x1 +#define RTC_CNTL_DIG_RC32K_EN_S 5 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[4] ;default: 1'd0 ; */ /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(4)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(4)) #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 -#define RTC_CNTL_DIG_XTAL32K_EN_S 8 -/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 1: CK8M_D256_OUT is actually CK8M*/ -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 -#define RTC_CNTL_ENB_CK8M_DIV_S 7 -/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: disable CK8M and CK8M_D256_OUT*/ -#define RTC_CNTL_ENB_CK8M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_V 0x1 -#define RTC_CNTL_ENB_CK8M_S 6 -/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ -/*description: CK8M_D256_OUT divider. 00: div128*/ -#define RTC_CNTL_CK8M_DIV 0x00000003 -#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) -#define RTC_CNTL_CK8M_DIV_V 0x3 -#define RTC_CNTL_CK8M_DIV_S 4 +#define RTC_CNTL_DIG_XTAL32K_EN_S 4 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ /*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ #define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) @@ -1108,6 +1162,12 @@ extern "C" { #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 +/* RTC_CNTL_BLE_TMR_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_TMR_RST (BIT(0)) +#define RTC_CNTL_BLE_TMR_RST_M (BIT(0)) +#define RTC_CNTL_BLE_TMR_RST_V 0x1 +#define RTC_CNTL_BLE_TMR_RST_S 0 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ @@ -1128,6 +1188,24 @@ extern "C" { #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 +/* RTC_CNTL_ANA_CLK_PD_IDLE : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_PD_IDLE (BIT(21)) +#define RTC_CNTL_ANA_CLK_PD_IDLE_M (BIT(21)) +#define RTC_CNTL_ANA_CLK_PD_IDLE_V 0x1 +#define RTC_CNTL_ANA_CLK_PD_IDLE_S 21 +/* RTC_CNTL_ANA_CLK_PD_MONITOR : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_PD_MONITOR (BIT(20)) +#define RTC_CNTL_ANA_CLK_PD_MONITOR_M (BIT(20)) +#define RTC_CNTL_ANA_CLK_PD_MONITOR_V 0x1 +#define RTC_CNTL_ANA_CLK_PD_MONITOR_S 20 +/* RTC_CNTL_ANA_CLK_PD_SLP : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_PD_SLP (BIT(19)) +#define RTC_CNTL_ANA_CLK_PD_SLP_M (BIT(19)) +#define RTC_CNTL_ANA_CLK_PD_SLP_V 0x1 +#define RTC_CNTL_ANA_CLK_PD_SLP_S 19 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ @@ -1228,6 +1306,24 @@ extern "C" { #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +/* RTC_CNTL_XPD_DCDC_IDLE : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_XPD_DCDC_IDLE (BIT(28)) +#define RTC_CNTL_XPD_DCDC_IDLE_M (BIT(28)) +#define RTC_CNTL_XPD_DCDC_IDLE_V 0x1 +#define RTC_CNTL_XPD_DCDC_IDLE_S 28 +/* RTC_CNTL_XPD_DCDC_MONITOR : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_XPD_DCDC_MONITOR (BIT(27)) +#define RTC_CNTL_XPD_DCDC_MONITOR_M (BIT(27)) +#define RTC_CNTL_XPD_DCDC_MONITOR_V 0x1 +#define RTC_CNTL_XPD_DCDC_MONITOR_S 27 +/* RTC_CNTL_XPD_DCDC_SLP : R/W ;bitpos:[26] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_XPD_DCDC_SLP (BIT(26)) +#define RTC_CNTL_XPD_DCDC_SLP_M (BIT(26)) +#define RTC_CNTL_XPD_DCDC_SLP_V 0x1 +#define RTC_CNTL_XPD_DCDC_SLP_S 26 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ /*description: DBG_ATTEN when rtc in monitor state*/ #define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F @@ -1288,18 +1384,6 @@ extern "C" { #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 -/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8 -/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF -#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF -#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 0 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ @@ -1327,22 +1411,188 @@ extern "C" { #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 - -/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/* RTC_CNTL_VDD_DRV_B_SLP_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VDD_DRV_B_SLP_EN (BIT(27)) +#define RTC_CNTL_VDD_DRV_B_SLP_EN_M (BIT(27)) +#define RTC_CNTL_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_VDD_DRV_B_SLP_EN_S 27 +/* RTC_CNTL_VDD_DRV_B_SLP : R/W ;bitpos:[26:21] ;default: 6'd0 ; */ +/*description: */ +#define RTC_CNTL_VDD_DRV_B_SLP 0x0000003F +#define RTC_CNTL_VDD_DRV_B_SLP_M ((RTC_CNTL_VDD_DRV_B_SLP_V)<<(RTC_CNTL_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_VDD_DRV_B_SLP_V 0x3F +#define RTC_CNTL_VDD_DRV_B_SLP_S 21 +/* RTC_CNTL_VDD_DRV_B_ACTIVE : R/W ;bitpos:[20:15] ;default: 6'd0 ; */ /*description: SCK_DCAP*/ +#define RTC_CNTL_VDD_DRV_B_ACTIVE 0x0000003F +#define RTC_CNTL_VDD_DRV_B_ACTIVE_M ((RTC_CNTL_VDD_DRV_B_ACTIVE_V)<<(RTC_CNTL_VDD_DRV_B_ACTIVE_S)) +#define RTC_CNTL_VDD_DRV_B_ACTIVE_V 0x3F +#define RTC_CNTL_VDD_DRV_B_ACTIVE_S 15 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[11:4] ;default: 8'd0 ; */ +/*description: */ #define RTC_CNTL_SCK_DCAP 0x000000FF #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF -#define RTC_CNTL_SCK_DCAP_S 14 -#define RTC_CNTL_SCK_DCAP_DEFAULT 255 -/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +#define RTC_CNTL_SCK_DCAP_S 4 +/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ -#define RTC_CNTL_DIG_CAL_EN (BIT(7)) -#define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN (BIT(3)) +#define RTC_CNTL_DIG_CAL_EN_M (BIT(3)) #define RTC_CNTL_DIG_CAL_EN_V 0x1 -#define RTC_CNTL_DIG_CAL_EN_S 7 +#define RTC_CNTL_DIG_CAL_EN_S 3 +/* RTC_CNTL_DBIAS_SWITCH_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DBIAS_SWITCH_IDLE (BIT(2)) +#define RTC_CNTL_DBIAS_SWITCH_IDLE_M (BIT(2)) +#define RTC_CNTL_DBIAS_SWITCH_IDLE_V 0x1 +#define RTC_CNTL_DBIAS_SWITCH_IDLE_S 2 +/* RTC_CNTL_DBIAS_SWITCH_MONITOR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DBIAS_SWITCH_MONITOR (BIT(1)) +#define RTC_CNTL_DBIAS_SWITCH_MONITOR_M (BIT(1)) +#define RTC_CNTL_DBIAS_SWITCH_MONITOR_V 0x1 +#define RTC_CNTL_DBIAS_SWITCH_MONITOR_S 1 +/* RTC_CNTL_DBIAS_SWITCH_SLP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DBIAS_SWITCH_SLP (BIT(0)) +#define RTC_CNTL_DBIAS_SWITCH_SLP_M (BIT(0)) +#define RTC_CNTL_DBIAS_SWITCH_SLP_V 0x1 +#define RTC_CNTL_DBIAS_SWITCH_SLP_S 0 -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0084) +#define RTC_CNTL_RTCULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0084) +/* RTC_CNTL_REGULATOR0_DBIAS_SEL : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: 1: select sw dbias_active 0: select pvt value*/ +#define RTC_CNTL_REGULATOR0_DBIAS_SEL (BIT(31)) +#define RTC_CNTL_REGULATOR0_DBIAS_SEL_M (BIT(31)) +#define RTC_CNTL_REGULATOR0_DBIAS_SEL_V 0x1 +#define RTC_CNTL_REGULATOR0_DBIAS_SEL_S 31 +/* RTC_CNTL_REGULATOR0_DBIAS_ACTIVE : R/W ;bitpos:[29:25] ;default: 5'b10100 ; */ +/*description: the rtc regulator0 dbias when chip in active state*/ +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE 0x0000001F +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_M ((RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V)<<(RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S)) +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V 0x1F +#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_REGULATOR0_DBIAS_SLP : R/W ;bitpos:[24:20] ;default: 5'b10100 ; */ +/*description: the rtc regulator0 dbias when chip in sleep state*/ +#define RTC_CNTL_REGULATOR0_DBIAS_SLP 0x0000001F +#define RTC_CNTL_REGULATOR0_DBIAS_SLP_M ((RTC_CNTL_REGULATOR0_DBIAS_SLP_V)<<(RTC_CNTL_REGULATOR0_DBIAS_SLP_S)) +#define RTC_CNTL_REGULATOR0_DBIAS_SLP_V 0x1F +#define RTC_CNTL_REGULATOR0_DBIAS_SLP_S 20 +/* RTC_CNTL_PVT_RTC_DBIAS : RO ;bitpos:[19:15] ;default: 5'b10100 ; */ +/*description: get pvt dbias value*/ +#define RTC_CNTL_PVT_RTC_DBIAS 0x0000001F +#define RTC_CNTL_PVT_RTC_DBIAS_M ((RTC_CNTL_PVT_RTC_DBIAS_V)<<(RTC_CNTL_PVT_RTC_DBIAS_S)) +#define RTC_CNTL_PVT_RTC_DBIAS_V 0x1F +#define RTC_CNTL_PVT_RTC_DBIAS_S 15 + +#define RTC_CNTL_RTCULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0088) +/* RTC_CNTL_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[28:25] ;default: 4'b1000 ; */ +/*description: the rtc regulator1 dbias when chip in active state*/ +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE 0x0000000F +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S)) +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V 0xF +#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[23:20] ;default: 4'b1000 ; */ +/*description: the rtc regulator1 dbias when chip in sleep state*/ +#define RTC_CNTL_REGULATOR1_DBIAS_SLP 0x0000000F +#define RTC_CNTL_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_REGULATOR1_DBIAS_SLP_S)) +#define RTC_CNTL_REGULATOR1_DBIAS_SLP_V 0xF +#define RTC_CNTL_REGULATOR1_DBIAS_SLP_S 20 + +#define RTC_CNTL_DIGULATOR_REG (DR_REG_RTCCNTL_BASE + 0x008C) +/* RTC_CNTL_DG_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_DG_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_DG_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU (BIT(29)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_S 29 +/* RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD (BIT(28)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_S 28 +/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(27)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(27)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 27 +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[26:3] ;default: 24'd0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x00FFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 3 + +#define RTC_CNTL_DIGULATOR_DRVB_REG (DR_REG_RTCCNTL_BASE + 0x0090) +/* RTC_CNTL_DG_VDD_DRV_B_ACTIVE : R/W ;bitpos:[23:0] ;default: 24'd0 ; */ +/*description: */ +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE 0x00FFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_M ((RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V)<<(RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S)) +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V 0xFFFFFF +#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S 0 + +#define RTC_CNTL_DIGULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0094) +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: 1: select sw dbias_active 0: select pvt value*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL (BIT(31)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_M (BIT(31)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_V 0x1 +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_S 31 +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: initial pvt dbias value*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT (BIT(30)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_M (BIT(30)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_V 0x1 +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_S 30 +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE : R/W ;bitpos:[29:25] ;default: 5'b10100 ; */ +/*description: the dig regulator0 dbias when chip in active state*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE 0x0000001F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_M ((RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V)<<(RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V 0x1F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP : R/W ;bitpos:[24:20] ;default: 5'b10100 ; */ +/*description: the dig regulator0 dbias when chip in sleep state*/ +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP 0x0000001F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_M ((RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V)<<(RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V 0x1F +#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S 20 +/* RTC_CNTL_PVT_DIG_DBIAS : RO ;bitpos:[19:15] ;default: 5'b10100 ; */ +/*description: get pvt dbias value*/ +#define RTC_CNTL_PVT_DIG_DBIAS 0x0000001F +#define RTC_CNTL_PVT_DIG_DBIAS_M ((RTC_CNTL_PVT_DIG_DBIAS_V)<<(RTC_CNTL_PVT_DIG_DBIAS_S)) +#define RTC_CNTL_PVT_DIG_DBIAS_V 0x1F +#define RTC_CNTL_PVT_DIG_DBIAS_S 15 + +#define RTC_CNTL_DIGULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0098) +/* RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[28:25] ;default: 4'b1000 ; */ +/*description: the dig regulator1 dbias when chip in active state*/ +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE 0x0000000F +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S)) +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V 0xF +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S 25 +/* RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[23:20] ;default: 4'b1000 ; */ +/*description: the dig regulator1 dbias when chip in sleep state*/ +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP 0x0000000F +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V 0xF +#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S 20 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x009C) /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ /*description: rtc pad force hold*/ #define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) @@ -1350,7 +1600,7 @@ extern "C" { #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x00A0) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) @@ -1381,6 +1631,12 @@ extern "C" { #define RTC_CNTL_BT_PD_EN_M (BIT(27)) #define RTC_CNTL_BT_PD_EN_V 0x1 #define RTC_CNTL_BT_PD_EN_S 27 +/* RTC_CNTL_DG_WRAP_RET_PD_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_RET_PD_EN (BIT(26)) +#define RTC_CNTL_DG_WRAP_RET_PD_EN_M (BIT(26)) +#define RTC_CNTL_DG_WRAP_RET_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_RET_PD_EN_S 26 /* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ /*description: */ #define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) @@ -1393,18 +1649,6 @@ extern "C" { #define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) #define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 #define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 -/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: digital core force power up*/ -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 -/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: digital core force power down*/ -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ /*description: wifi force power up*/ #define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) @@ -1453,6 +1697,30 @@ extern "C" { #define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) #define RTC_CNTL_BT_FORCE_PD_V 0x1 #define RTC_CNTL_BT_FORCE_PD_S 11 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(10)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 10 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(9)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 9 +/* RTC_CNTL_DG_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_MEM_FORCE_PU (BIT(8)) +#define RTC_CNTL_DG_MEM_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_DG_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_PU_S 8 +/* RTC_CNTL_DG_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_MEM_FORCE_PD (BIT(7)) +#define RTC_CNTL_DG_MEM_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_DG_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_PD_S 7 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ /*description: memories in digital core force no PD in sleep*/ #define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) @@ -1478,7 +1746,41 @@ extern "C" { #define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 #define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x008C) +#define RTC_CNTL_DIG_POWER_SWITCH0_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +/* RTC_CNTL_XPD_MEM_SWITCH_MASK : R/W ;bitpos:[31:12] ;default: ~20'h0 ; */ +/*description: */ +#define RTC_CNTL_XPD_MEM_SWITCH_MASK 0x000FFFFF +#define RTC_CNTL_XPD_MEM_SWITCH_MASK_M ((RTC_CNTL_XPD_MEM_SWITCH_MASK_V)<<(RTC_CNTL_XPD_MEM_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_MEM_SWITCH_MASK_V 0xFFFFF +#define RTC_CNTL_XPD_MEM_SWITCH_MASK_S 12 +/* RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK : R/W ;bitpos:[11:7] ;default: ~5'h0 ; */ +/*description: */ +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_M ((RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V)<<(RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S 7 +/* RTC_CNTL_XPD_DG_PERI_SWITCH_MASK : R/W ;bitpos:[6:2] ;default: ~5'h0 ; */ +/*description: */ +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_M ((RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V)<<(RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S 2 + +#define RTC_CNTL_DIG_POWER_SWITCH1_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +/* RTC_CNTL_XPD_CPU_SWITCH_MASK : R/W ;bitpos:[31:27] ;default: ~5'h0 ; */ +/*description: */ +#define RTC_CNTL_XPD_CPU_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_CPU_SWITCH_MASK_M ((RTC_CNTL_XPD_CPU_SWITCH_MASK_V)<<(RTC_CNTL_XPD_CPU_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_CPU_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_CPU_SWITCH_MASK_S 27 +/* RTC_CNTL_XPD_WIFI_SWITCH_MASK : R/W ;bitpos:[26:22] ;default: ~5'h0 ; */ +/*description: */ +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK 0x0000001F +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_M ((RTC_CNTL_XPD_WIFI_SWITCH_MASK_V)<<(RTC_CNTL_XPD_WIFI_SWITCH_MASK_S)) +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_V 0x1F +#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_S 22 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x00AC) /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ /*description: */ #define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) @@ -1593,8 +1895,20 @@ extern "C" { #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 +/* RTC_CNTL_DG_MEM_FORCE_ISO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DG_MEM_FORCE_ISO (BIT(6)) +#define RTC_CNTL_DG_MEM_FORCE_ISO_M (BIT(6)) +#define RTC_CNTL_DG_MEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_ISO_S 6 +/* RTC_CNTL_DG_MEM_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_DG_MEM_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_DG_MEM_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_DG_MEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_MEM_FORCE_NOISO_S 5 -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x00B0) /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ #define RTC_CNTL_WDT_EN (BIT(31)) @@ -1682,7 +1996,7 @@ extern "C" { #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0094) +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x00B4) /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ /*description: */ #define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF @@ -1690,7 +2004,7 @@ extern "C" { #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG0_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x0098) +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x00B8) /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ /*description: */ #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF @@ -1698,7 +2012,7 @@ extern "C" { #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG1_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x009C) +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00BC) /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ /*description: */ #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF @@ -1706,7 +2020,7 @@ extern "C" { #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG2_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00C0) /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ /*description: */ #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF @@ -1714,7 +2028,7 @@ extern "C" { #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG3_HOLD_S 0 -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00C4) /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_WDT_FEED (BIT(31)) @@ -1722,15 +2036,29 @@ extern "C" { #define RTC_CNTL_WDT_FEED_V 0x1 #define RTC_CNTL_WDT_FEED_S 31 -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00A8) -/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_S 0 -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +#define RTC_CNTL_WDTRESET_CHIP_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +/* RTC_CNTL_RESET_CHIP_KEY : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: */ +#define RTC_CNTL_RESET_CHIP_KEY 0x000000FF +#define RTC_CNTL_RESET_CHIP_KEY_M ((RTC_CNTL_RESET_CHIP_KEY_V)<<(RTC_CNTL_RESET_CHIP_KEY_S)) +#define RTC_CNTL_RESET_CHIP_KEY_V 0xFF +#define RTC_CNTL_RESET_CHIP_KEY_S 24 +/* RTC_CNTL_RESET_CHIP_TARGET : R/W ;bitpos:[23:16] ;default: 8'ha5 ; */ +/*description: */ +#define RTC_CNTL_RESET_CHIP_TARGET 0x000000FF +#define RTC_CNTL_RESET_CHIP_TARGET_M ((RTC_CNTL_RESET_CHIP_TARGET_V)<<(RTC_CNTL_RESET_CHIP_TARGET_S)) +#define RTC_CNTL_RESET_CHIP_TARGET_V 0xFF +#define RTC_CNTL_RESET_CHIP_TARGET_S 16 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00D0) /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: automatically feed swd when int comes*/ #define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) @@ -1780,15 +2108,15 @@ extern "C" { #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 #define RTC_CNTL_SWD_RESET_FLAG_S 0 -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B0) -/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define RTC_CNTL_SWD_WKEY 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_S 0 -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00D8) /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ /*description: */ #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F @@ -1802,7 +2130,7 @@ extern "C" { #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00DC) /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH4 0xFFFFFFFF @@ -1810,7 +2138,7 @@ extern "C" { #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH4_S 0 -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00E0) /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH5 0xFFFFFFFF @@ -1818,7 +2146,7 @@ extern "C" { #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH5_S 0 -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00E4) /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH6 0xFFFFFFFF @@ -1826,7 +2154,7 @@ extern "C" { #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH6_S 0 -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00E8) /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH7 0xFFFFFFFF @@ -1834,7 +2162,7 @@ extern "C" { #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_S 0 -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00EC) /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ /*description: rtc main state machine status*/ #define RTC_CNTL_MAIN_STATE 0x0000000F @@ -2004,7 +2332,7 @@ extern "C" { #define RTC_CNTL_XPD_ROM0_V 0x1 #define RTC_CNTL_XPD_ROM0_S 0 -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00F0) /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF @@ -2012,7 +2340,7 @@ extern "C" { #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF #define RTC_CNTL_LOW_POWER_DIAG1_S 0 -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00F4) /* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) @@ -2050,7 +2378,7 @@ extern "C" { #define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 #define RTC_CNTL_GPIO_PIN0_HOLD_S 0 -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00F8) /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF @@ -2058,7 +2386,15 @@ extern "C" { #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF #define RTC_CNTL_DIG_PAD_HOLD_S 0 -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +#define RTC_CNTL_DIG_PAD_HOLD1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +/* RTC_CNTL_DIG_PAD_HOLD1 : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_PAD_HOLD1 0x000001FF +#define RTC_CNTL_DIG_PAD_HOLD1_M ((RTC_CNTL_DIG_PAD_HOLD1_V)<<(RTC_CNTL_DIG_PAD_HOLD1_S)) +#define RTC_CNTL_DIG_PAD_HOLD1_V 0x1FF +#define RTC_CNTL_DIG_PAD_HOLD1_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x0100) /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) @@ -2120,7 +2456,7 @@ extern "C" { #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x0104) /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: RTC timer low 32 bits*/ #define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF @@ -2128,7 +2464,7 @@ extern "C" { #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x0108) /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: RTC timer high 16 bits*/ #define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF @@ -2136,7 +2472,7 @@ extern "C" { #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x010C) /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: xtal 32k watch dog backup clock factor*/ #define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF @@ -2144,7 +2480,7 @@ extern "C" { #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0110) /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ /*description: if restarted xtal32k period is smaller than this*/ #define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F @@ -2170,7 +2506,7 @@ extern "C" { #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0114) /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) @@ -2178,15 +2514,15 @@ extern "C" { #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F0) -/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0118) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[18:0] ;default: 19'd0 ; */ /*description: sleep reject cause*/ -#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE 0x0007FFFF #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) -#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_V 0x7FFFF #define RTC_CNTL_REJECT_CAUSE_S 0 -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x011C) /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) @@ -2194,15 +2530,15 @@ extern "C" { #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F8) -/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0120) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[18:0] ;default: 19'd0 ; */ /*description: sleep wakeup cause*/ -#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE 0x0007FFFF #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FFFF #define RTC_CNTL_WAKEUP_CAUSE_S 0 -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0124) /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ /*description: sleep cycles for ULP-coprocessor timer*/ #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF @@ -2210,7 +2546,19 @@ extern "C" { #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 -#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0100) +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0128) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_S 21 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) @@ -2266,7 +2614,19 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 -#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0104) +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x012C) +/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_M (BIT(22)) +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_S 22 +/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_M (BIT(21)) +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_S 21 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) @@ -2322,7 +2682,7 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0108) +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0130) /* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ /*description: wait cycles for rention operation*/ #define RTC_CNTL_RETENTION_WAIT 0x0000001F @@ -2353,8 +2713,22 @@ extern "C" { #define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) #define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 #define RTC_CNTL_RETENTION_CLK_SEL_S 18 +/* RTC_CNTL_CNTL_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CNTL_CLK_EN (BIT(17)) +#define RTC_CNTL_CNTL_CLK_EN_M (BIT(17)) +#define RTC_CNTL_CNTL_CLK_EN_V 0x1 +#define RTC_CNTL_CNTL_CLK_EN_S 17 -#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +#define RTC_CNTL_RETENTION_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0134) +/* RTC_CNTL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_LINK_ADDR 0x07FFFFFF +#define RTC_CNTL_RETENTION_LINK_ADDR_M ((RTC_CNTL_RETENTION_LINK_ADDR_V)<<(RTC_CNTL_RETENTION_LINK_ADDR_S)) +#define RTC_CNTL_RETENTION_LINK_ADDR_V 0x7FFFFFF +#define RTC_CNTL_RETENTION_LINK_ADDR_S 0 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0138) /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ /*description: select use analog fib signal*/ #define RTC_CNTL_FIB_SEL 0x00000007 @@ -2366,7 +2740,7 @@ extern "C" { #define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) -#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) +#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C) /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) @@ -2458,7 +2832,7 @@ extern "C" { #define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F #define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 -#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0114) +#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140) /* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ /*description: */ #define RTC_CNTL_DEBUG_SEL4 0x0000001F @@ -2501,8 +2875,14 @@ extern "C" { #define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) #define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 #define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 +/* RTC_CNTL_MTDI_ENAMUX : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_MTDI_ENAMUX (BIT(0)) +#define RTC_CNTL_MTDI_ENAMUX_M (BIT(0)) +#define RTC_CNTL_MTDI_ENAMUX_V 0x1 +#define RTC_CNTL_MTDI_ENAMUX_S 0 -#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0118) +#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0144) /* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ /*description: */ #define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F @@ -2575,22 +2955,14 @@ extern "C" { #define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) #define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 - -#define RTC_CNTL_SENSOR_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011C) -/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ +/* RTC_CNTL_VDD_DIG_TEST : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: */ -#define RTC_CNTL_FORCE_XPD_SAR 0x00000003 -#define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S)) -#define RTC_CNTL_FORCE_XPD_SAR_V 0x3 -#define RTC_CNTL_FORCE_XPD_SAR_S 30 -/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_SAR2_PWDET_CCT 0x00000007 -#define RTC_CNTL_SAR2_PWDET_CCT_M ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S)) -#define RTC_CNTL_SAR2_PWDET_CCT_V 0x7 -#define RTC_CNTL_SAR2_PWDET_CCT_S 27 +#define RTC_CNTL_VDD_DIG_TEST 0x00000003 +#define RTC_CNTL_VDD_DIG_TEST_M ((RTC_CNTL_VDD_DIG_TEST_V)<<(RTC_CNTL_VDD_DIG_TEST_S)) +#define RTC_CNTL_VDD_DIG_TEST_V 0x3 +#define RTC_CNTL_VDD_DIG_TEST_S 0 -#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0148) /* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ /*description: */ #define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F @@ -2598,7 +2970,7 @@ extern "C" { #define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F #define RTC_CNTL_SAR_DEBUG_SEL_S 27 -#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0124) +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x014C) /* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) @@ -2630,8 +3002,174 @@ extern "C" { #define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 #define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 +#define RTC_CNTL_DCDC_CTRL0_REG (DR_REG_RTCCNTL_BASE + 0x0150) +/* RTC_CNTL_POCPENB_DCDC : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_POCPENB_DCDC (BIT(31)) +#define RTC_CNTL_POCPENB_DCDC_M (BIT(31)) +#define RTC_CNTL_POCPENB_DCDC_V 0x1 +#define RTC_CNTL_POCPENB_DCDC_S 31 +/* RTC_CNTL_SSTIME_DCDC : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SSTIME_DCDC (BIT(30)) +#define RTC_CNTL_SSTIME_DCDC_M (BIT(30)) +#define RTC_CNTL_SSTIME_DCDC_V 0x1 +#define RTC_CNTL_SSTIME_DCDC_S 30 +/* RTC_CNTL_CCM_DCDC : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CCM_DCDC (BIT(29)) +#define RTC_CNTL_CCM_DCDC_M (BIT(29)) +#define RTC_CNTL_CCM_DCDC_V 0x1 +#define RTC_CNTL_CCM_DCDC_S 29 +/* RTC_CNTL_FSW_DCDC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: */ +#define RTC_CNTL_FSW_DCDC 0x00000007 +#define RTC_CNTL_FSW_DCDC_M ((RTC_CNTL_FSW_DCDC_V)<<(RTC_CNTL_FSW_DCDC_S)) +#define RTC_CNTL_FSW_DCDC_V 0x7 +#define RTC_CNTL_FSW_DCDC_S 26 +/* RTC_CNTL_DCMLEVEL_DCDC : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ +/*description: */ +#define RTC_CNTL_DCMLEVEL_DCDC 0x00000003 +#define RTC_CNTL_DCMLEVEL_DCDC_M ((RTC_CNTL_DCMLEVEL_DCDC_V)<<(RTC_CNTL_DCMLEVEL_DCDC_S)) +#define RTC_CNTL_DCMLEVEL_DCDC_V 0x3 +#define RTC_CNTL_DCMLEVEL_DCDC_S 24 +/* RTC_CNTL_DCM2ENB_DCDC : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DCM2ENB_DCDC (BIT(23)) +#define RTC_CNTL_DCM2ENB_DCDC_M (BIT(23)) +#define RTC_CNTL_DCM2ENB_DCDC_V 0x1 +#define RTC_CNTL_DCM2ENB_DCDC_S 23 +/* RTC_CNTL_RAMP_DCDC : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RAMP_DCDC (BIT(22)) +#define RTC_CNTL_RAMP_DCDC_M (BIT(22)) +#define RTC_CNTL_RAMP_DCDC_V 0x1 +#define RTC_CNTL_RAMP_DCDC_S 22 +/* RTC_CNTL_RAMPLEVEL_DCDC : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RAMPLEVEL_DCDC (BIT(21)) +#define RTC_CNTL_RAMPLEVEL_DCDC_M (BIT(21)) +#define RTC_CNTL_RAMPLEVEL_DCDC_V 0x1 +#define RTC_CNTL_RAMPLEVEL_DCDC_S 21 +/* RTC_CNTL_POWER_GOOD_DCDC : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_POWER_GOOD_DCDC (BIT(5)) +#define RTC_CNTL_POWER_GOOD_DCDC_M (BIT(5)) +#define RTC_CNTL_POWER_GOOD_DCDC_V 0x1 +#define RTC_CNTL_POWER_GOOD_DCDC_S 5 +/* RTC_CNTL_VSET_DCDC_VALUE : RO ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_VALUE 0x0000001F +#define RTC_CNTL_VSET_DCDC_VALUE_M ((RTC_CNTL_VSET_DCDC_VALUE_V)<<(RTC_CNTL_VSET_DCDC_VALUE_S)) +#define RTC_CNTL_VSET_DCDC_VALUE_V 0x1F +#define RTC_CNTL_VSET_DCDC_VALUE_S 0 + +#define RTC_CNTL_DCDC_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0154) +/* RTC_CNTL_DCDC_MODE_IDLE : R/W ;bitpos:[31:29] ;default: 3'b100 ; */ +/*description: */ +#define RTC_CNTL_DCDC_MODE_IDLE 0x00000007 +#define RTC_CNTL_DCDC_MODE_IDLE_M ((RTC_CNTL_DCDC_MODE_IDLE_V)<<(RTC_CNTL_DCDC_MODE_IDLE_S)) +#define RTC_CNTL_DCDC_MODE_IDLE_V 0x7 +#define RTC_CNTL_DCDC_MODE_IDLE_S 29 +/* RTC_CNTL_DCDC_MODE_MONITOR : R/W ;bitpos:[28:26] ;default: 3'b100 ; */ +/*description: */ +#define RTC_CNTL_DCDC_MODE_MONITOR 0x00000007 +#define RTC_CNTL_DCDC_MODE_MONITOR_M ((RTC_CNTL_DCDC_MODE_MONITOR_V)<<(RTC_CNTL_DCDC_MODE_MONITOR_S)) +#define RTC_CNTL_DCDC_MODE_MONITOR_V 0x7 +#define RTC_CNTL_DCDC_MODE_MONITOR_S 26 +/* RTC_CNTL_DCDC_MODE_SLP : R/W ;bitpos:[25:23] ;default: 3'b100 ; */ +/*description: */ +#define RTC_CNTL_DCDC_MODE_SLP 0x00000007 +#define RTC_CNTL_DCDC_MODE_SLP_M ((RTC_CNTL_DCDC_MODE_SLP_V)<<(RTC_CNTL_DCDC_MODE_SLP_S)) +#define RTC_CNTL_DCDC_MODE_SLP_V 0x7 +#define RTC_CNTL_DCDC_MODE_SLP_S 23 + +#define RTC_CNTL_DCDC_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0158) +/* RTC_CNTL_VSET_DCDC_SW_SEL : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_SW_SEL (BIT(28)) +#define RTC_CNTL_VSET_DCDC_SW_SEL_M (BIT(28)) +#define RTC_CNTL_VSET_DCDC_SW_SEL_V 0x1 +#define RTC_CNTL_VSET_DCDC_SW_SEL_S 28 +/* RTC_CNTL_VSET_DCDC_SEL_HW_SW : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW (BIT(27)) +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_M (BIT(27)) +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_V 0x1 +#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_S 27 +/* RTC_CNTL_VSET_DCDC_GAP : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_GAP 0x0000001F +#define RTC_CNTL_VSET_DCDC_GAP_M ((RTC_CNTL_VSET_DCDC_GAP_V)<<(RTC_CNTL_VSET_DCDC_GAP_S)) +#define RTC_CNTL_VSET_DCDC_GAP_V 0x1F +#define RTC_CNTL_VSET_DCDC_GAP_S 22 +/* RTC_CNTL_VSET_DCDC_STEP : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_STEP 0x0000001F +#define RTC_CNTL_VSET_DCDC_STEP_M ((RTC_CNTL_VSET_DCDC_STEP_V)<<(RTC_CNTL_VSET_DCDC_STEP_S)) +#define RTC_CNTL_VSET_DCDC_STEP_V 0x1F +#define RTC_CNTL_VSET_DCDC_STEP_S 17 +/* RTC_CNTL_VSET_DCDC_FIX : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_FIX (BIT(16)) +#define RTC_CNTL_VSET_DCDC_FIX_M (BIT(16)) +#define RTC_CNTL_VSET_DCDC_FIX_V 0x1 +#define RTC_CNTL_VSET_DCDC_FIX_S 16 +/* RTC_CNTL_VSET_DCDC_INIT : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_INIT (BIT(15)) +#define RTC_CNTL_VSET_DCDC_INIT_M (BIT(15)) +#define RTC_CNTL_VSET_DCDC_INIT_V 0x1 +#define RTC_CNTL_VSET_DCDC_INIT_S 15 +/* RTC_CNTL_VSET_DCDC_INIT_VALUE : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_INIT_VALUE 0x0000001F +#define RTC_CNTL_VSET_DCDC_INIT_VALUE_M ((RTC_CNTL_VSET_DCDC_INIT_VALUE_V)<<(RTC_CNTL_VSET_DCDC_INIT_VALUE_S)) +#define RTC_CNTL_VSET_DCDC_INIT_VALUE_V 0x1F +#define RTC_CNTL_VSET_DCDC_INIT_VALUE_S 10 +/* RTC_CNTL_VSET_DCDC_TARGET_VALUE0 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0 0x0000001F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_M ((RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V)<<(RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S)) +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V 0x1F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S 5 +/* RTC_CNTL_VSET_DCDC_TARGET_VALUE1 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1 0x0000001F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_M ((RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V)<<(RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S)) +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V 0x1F +#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S 0 + +#define RTC_CNTL_RC32K_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x015C) +/* RTC_CNTL_RC32K_XPD : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RC32K_XPD (BIT(31)) +#define RTC_CNTL_RC32K_XPD_M (BIT(31)) +#define RTC_CNTL_RC32K_XPD_V 0x1 +#define RTC_CNTL_RC32K_XPD_S 31 +/* RTC_CNTL_RC32K_DFREQ : R/W ;bitpos:[30:21] ;default: 10'h1ff ; */ +/*description: */ +#define RTC_CNTL_RC32K_DFREQ 0x000003FF +#define RTC_CNTL_RC32K_DFREQ_M ((RTC_CNTL_RC32K_DFREQ_V)<<(RTC_CNTL_RC32K_DFREQ_S)) +#define RTC_CNTL_RC32K_DFREQ_V 0x3FF +#define RTC_CNTL_RC32K_DFREQ_S 21 + +#define RTC_CNTL_PLL8M_REG (DR_REG_RTCCNTL_BASE + 0x0160) +/* RTC_CNTL_XPD_PLL8M : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XPD_PLL8M (BIT(31)) +#define RTC_CNTL_XPD_PLL8M_M (BIT(31)) +#define RTC_CNTL_XPD_PLL8M_V 0x1 +#define RTC_CNTL_XPD_PLL8M_S 31 +/* RTC_CNTL_CKREF_PLL8M_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_CKREF_PLL8M_SEL (BIT(30)) +#define RTC_CNTL_CKREF_PLL8M_SEL_M (BIT(30)) +#define RTC_CNTL_CKREF_PLL8M_SEL_V 0x1 +#define RTC_CNTL_CKREF_PLL8M_SEL_S 30 + #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) -/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */ +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103250 ; */ /*description: */ #define RTC_CNTL_CNTL_DATE 0x0FFFFFFF #define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) @@ -2645,3 +3183,5 @@ extern "C" { #endif /*_SOC_RTC_CNTL_REG_H_ */ + + diff --git a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h b/components/soc/esp32h2/include/soc/rtc_cntl_struct.h index 358ebaded7..68100c9cee 100644 --- a/components/soc/esp32h2/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32h2/include/soc/rtc_cntl_struct.h @@ -20,20 +20,21 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ - uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ - uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ - uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ - uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ - uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ - uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ - uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ - uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ - uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ - uint32_t xtl_force_pd: 1; /*crystall force power down*/ - uint32_t xtl_force_pu: 1; /*crystall force power up*/ - uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ - uint32_t reserved18: 2; + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ + uint32_t xpd_rfpll: 1; + uint32_t xpd_rfpll_force: 1; uint32_t ctr_sel: 3; uint32_t xtl_force_iso: 1; uint32_t pll_force_iso: 1; @@ -41,17 +42,17 @@ typedef volatile struct { uint32_t xtl_force_noiso: 1; uint32_t pll_force_noiso: 1; uint32_t analog_force_noiso: 1; - uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ - uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ - uint32_t sw_sys_rst: 1; /*SW system reset*/ + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ }; uint32_t val; } options0; - uint32_t slp_timer0; /**/ + uint32_t slp_timer0; /**/ union { struct { - uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ - uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ uint32_t reserved17: 15; }; uint32_t val; @@ -59,50 +60,50 @@ typedef volatile struct { union { struct { uint32_t reserved0: 27; - uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ - uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ - uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ + uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ uint32_t reserved30: 1; - uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ }; uint32_t val; } time_update; - uint32_t time_low0; /*RTC timer low 32 bits*/ + uint32_t time_low0; /*RTC timer low 32 bits*/ union { struct { - uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/ + uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/ uint32_t reserved16: 16; }; uint32_t val; } time_high0; union { struct { - uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ - uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ + uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ uint32_t reserved2: 20; - uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ uint32_t reserved23: 5; - uint32_t sdio_active_ind: 1; /*SDIO active indication*/ - uint32_t slp_wakeup: 1; /*leep wakeup bit*/ - uint32_t slp_reject: 1; /*leep reject bit*/ - uint32_t sleep_en: 1; /*sleep enable bit*/ + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*leep wakeup bit*/ + uint32_t slp_reject: 1; /*leep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ }; uint32_t val; } state0; union { struct { - uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ - uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ - uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ - uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ - uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ }; uint32_t val; } timer1; union { struct { uint32_t reserved0: 24; - uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ }; uint32_t val; } timer2; @@ -127,7 +128,7 @@ typedef volatile struct { union { struct { uint32_t reserved0: 8; - uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ uint32_t reserved16: 16; }; uint32_t val; @@ -142,36 +143,38 @@ typedef volatile struct { } timer6; union { struct { - uint32_t reserved0: 18; + uint32_t reserved0: 16; + uint32_t xpd_trx_force_pd: 1; + uint32_t xpd_trx_force_pu: 1; uint32_t i2c_reset_por_force_pd: 1; uint32_t i2c_reset_por_force_pu: 1; uint32_t glitch_rst_en: 1; - uint32_t reserved21: 1; /*PLLA force power down*/ - uint32_t sar_i2c_pu: 1; /*PLLA force power up*/ - uint32_t plla_force_pd: 1; /*PLLA force power down*/ - uint32_t plla_force_pu: 1; /*PLLA force power up*/ - uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ - uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ - uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ - uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ + uint32_t reserved21: 1; /*PLLA force power down*/ + uint32_t peri_i2c_pu: 1; /*PLLA force power up*/ + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ uint32_t reserved29: 1; - uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ uint32_t pll_i2c_pu: 1; }; uint32_t val; } ana_conf; union { struct { - uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ - uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ - uint32_t stat_vector_sel_appcpu: 1; /*APP CPU state vector sel*/ - uint32_t stat_vector_sel_procpu: 1; /*PRO CPU state vector sel*/ - uint32_t all_reset_flag_procpu: 1; /*PRO CPU reset_flag*/ - uint32_t all_reset_flag_appcpu: 1; /*APP CPU reset flag*/ - uint32_t all_reset_flag_clr_procpu: 1; /*clear PRO CPU reset_flag*/ - uint32_t all_reset_flag_clr_appcpu: 1; /*clear APP CPU reset flag*/ - uint32_t ocd_halt_on_reset_appcpu: 1; /*APPCPU OcdHaltOnReset*/ - uint32_t ocd_halt_on_reset_procpu: 1; /*PROCPU OcdHaltOnReset*/ + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t stat_vector_sel_appcpu: 1; /*APP CPU state vector sel*/ + uint32_t stat_vector_sel_procpu: 1; /*PRO CPU state vector sel*/ + uint32_t all_reset_flag_procpu: 1; /*PRO CPU reset_flag*/ + uint32_t all_reset_flag_appcpu: 1; /*APP CPU reset flag*/ + uint32_t all_reset_flag_clr_procpu: 1; /*clear PRO CPU reset_flag*/ + uint32_t all_reset_flag_clr_appcpu: 1; /*clear APP CPU reset flag*/ + uint32_t ocd_halt_on_reset_appcpu: 1; /*APPCPU OcdHaltOnReset*/ + uint32_t ocd_halt_on_reset_procpu: 1; /*PROCPU OcdHaltOnReset*/ uint32_t jtag_reset_flag_procpu: 1; uint32_t jtag_reset_flag_appcpu: 1; uint32_t jtag_reset_flag_clr_procpu: 1; @@ -184,108 +187,116 @@ typedef volatile struct { } reset_state; union { struct { - uint32_t reserved0: 15; - uint32_t rtc_wakeup_ena:17; /*wakeup enable bitmap*/ + uint32_t reserved0: 13; + uint32_t rtc_wakeup_ena:19; /*wakeup enable bitmap*/ }; uint32_t val; } wakeup_state; union { struct { - uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ - uint32_t reserved2: 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ - uint32_t reserved4: 5; - uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ - uint32_t reserved11: 4; /*enable saradc2 interrupt*/ - uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ - uint32_t reserved17: 2; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t reserved2: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4: 5; + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11: 4; /*enable saradc2 interrupt*/ + uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17: 2; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t rtc_ble_compare_wake: 1; + uint32_t vset_dcdc_done: 1; + uint32_t reserved23: 9; }; uint32_t val; } int_ena; union { struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ - uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ - uint32_t reserved2: 1; /*SDIO idle interrupt raw*/ - uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ - uint32_t reserved4: 5; /*touch inactive interrupt raw*/ - uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ - uint32_t reserved11: 4; /*saradc2 interrupt raw*/ - uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ - uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ - uint32_t reserved17: 2; /*touch timeout interrupt raw*/ - uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t reserved2: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t reserved4: 5; /*touch inactive interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t reserved11: 4; /*saradc2 interrupt raw*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ + uint32_t reserved17: 2; /*touch timeout interrupt raw*/ + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t rtc_ble_compare_wake: 1; + uint32_t vset_dcdc_done: 1; + uint32_t reserved23: 9; }; uint32_t val; } int_raw; union { struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*sleep reject interrupt state*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ - uint32_t reserved4: 5; - uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ - uint32_t reserved11: 4; - uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t reserved4: 5; + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t reserved11: 4; + uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t rtc_ble_compare_wake: 1; + uint32_t vset_dcdc_done: 1; + uint32_t reserved23: 9; }; uint32_t val; } int_st; union { struct { - uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ - uint32_t reserved4: 5; - uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ - uint32_t reserved11: 4; - uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t reserved4: 5; + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved11: 4; + uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ + uint32_t rtc_bbpll_cal: 1; + uint32_t rtc_ble_compare_wake: 1; + uint32_t vset_dcdc_done: 1; + uint32_t reserved23: 9; }; uint32_t val; } int_clr; - uint32_t store[4]; /**/ + uint32_t store[4]; /**/ union { struct { - uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ - uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ - uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ - uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ - uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ - uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ - uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ - uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ - uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ - uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ - uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ - uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ - uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ - uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ - uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ - uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ + uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ + uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ + uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ uint32_t reserved24: 6; - uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ + uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ uint32_t ctr_en: 1; }; uint32_t val; @@ -293,57 +304,57 @@ typedef volatile struct { union { struct { uint32_t reserved0: 31; - uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ }; uint32_t val; } ext_wakeup_conf; union { struct { - uint32_t reserved0: 12; - uint32_t rtc_sleep_reject_ena:18; /*sleep reject enable*/ - uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ - uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + uint32_t reserved0: 11; + uint32_t rtc_sleep_reject_ena:19; /*sleep reject enable*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ }; uint32_t val; } slp_reject_conf; union { struct { uint32_t reserved0: 29; - uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpusel_conf: 1; /*CPU sel option*/ uint32_t cpuperiod_sel: 2; }; uint32_t val; } cpu_period_conf; union { struct { - uint32_t reserved0: 1; + uint32_t rtc_ble_tmr_rst: 1; uint32_t efuse_clk_force_gating: 1; uint32_t efuse_clk_force_nogating: 1; - uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ - uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ - uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ - uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ - uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ - uint32_t reserved11: 1; - uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ - uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ - uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ - uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ - uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ - uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_rc32k_en: 1; /*enable RC32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t reserved7: 3; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 10; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ uint32_t xtal_global_force_gating: 1; uint32_t xtal_global_force_nogating: 1; - uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ uint32_t ana_clk_rtc_sel: 2; }; uint32_t val; } clk_conf; union { struct { - uint32_t reserved0: 22; - uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ + uint32_t reserved0: 19; + uint32_t rtc_ana_clk_pd_slp: 1; + uint32_t rtc_ana_clk_pd_monitor: 1; + uint32_t rtc_ana_clk_pd_idle: 1; + uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ uint32_t rtc_ana_clk_div: 8; uint32_t slow_clk_next_edge: 1; }; @@ -351,63 +362,129 @@ typedef volatile struct { } slow_clk_conf; union { struct { - uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ uint32_t reserved8: 1; - uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ - uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ - uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ - uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ - uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ - uint32_t sdio_modecurlim: 1; /*select current limit mode*/ - uint32_t sdio_encurlim: 1; /*enable current limit*/ - uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ - uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ - uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ - uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ - uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ + uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ + uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim: 1; /*select current limit mode*/ + uint32_t sdio_encurlim: 1; /*enable current limit*/ + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ uint32_t xpd_sdio: 1; }; uint32_t val; } sdio_conf; union { struct { - uint32_t dg_vdd_drv_b_slp: 8; - uint32_t dg_vdd_drv_b_slp_en: 1; - uint32_t reserved9: 1; + uint32_t reserved0: 10; uint32_t bias_buf_idle: 1; uint32_t bias_buf_wake: 1; uint32_t bias_buf_deep_slp: 1; uint32_t bias_buf_monitor: 1; - uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ - uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ - uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ - uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ - uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ - uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ - uint32_t reserved26: 6; + uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ + uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ + uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ + uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ + uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ + uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ + uint32_t xpd_dcdc_slp: 1; + uint32_t xpd_dcdc_monitor: 1; + uint32_t xpd_dcdc_idle: 1; + uint32_t reserved29: 3; }; uint32_t val; } bias_conf; union { struct { - uint32_t reserved0: 7; - uint32_t dig_cal_en: 1; - uint32_t reserved8: 6; - uint32_t sck_dcap: 8; /*SCK_DCAP*/ - uint32_t reserved22: 6; - uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ - uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ - uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ - uint32_t rtculator_force_pu: 1; + uint32_t dbias_switch_slp: 1; + uint32_t dbias_switch_monitor: 1; + uint32_t dbias_switch_idle: 1; + uint32_t dig_cal_en: 1; + uint32_t sck_dcap: 8; + uint32_t reserved12: 3; + uint32_t rtc_vdd_drv_b_active: 6; /*SCK_DCAP*/ + uint32_t rtc_vdd_drv_b_slp: 6; + uint32_t rtc_vdd_drv_b_slp_en: 1; + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtculator_force_pu: 1; }; uint32_t val; - } rtc; + } rtculator; + union { + struct { + uint32_t reserved0: 15; + uint32_t pvt_rtc_dbias: 5; /*get pvt dbias value*/ + uint32_t rtculator0_dbias_slp: 5; /*the rtc regulator0 dbias when chip in sleep state*/ + uint32_t rtculator0_dbias_active: 5; /*the rtc regulator0 dbias when chip in active state*/ + uint32_t reserved30: 1; + uint32_t rtculator0_dbias_sel: 1; /*1: select sw dbias_active 0: select pvt value*/ + }; + uint32_t val; + } rtculator0_dbias; + union { + struct { + uint32_t reserved0: 20; + uint32_t rtculator1_dbias_slp: 4; /*the rtc regulator1 dbias when chip in sleep state*/ + uint32_t reserved24: 1; + uint32_t rtculator1_dbias_active: 4; /*the rtc regulator1 dbias when chip in active state*/ + uint32_t reserved29: 3; + }; + uint32_t val; + } rtculator1_dbias; + union { + struct { + uint32_t reserved0: 3; + uint32_t dg_vdd_drv_b_slp: 24; + uint32_t dg_vdd_drv_b_slp_en: 1; + uint32_t dgulator_slp_force_pd: 1; + uint32_t dgulator_slp_force_pu: 1; + uint32_t dgulator_force_pd: 1; + uint32_t dgulator_force_pu: 1; + }; + uint32_t val; + } digulator; + union { + struct { + uint32_t dg_vdd_drv_b_active:24; + uint32_t reserved24: 8; + }; + uint32_t val; + } digulator_drvb; + union { + struct { + uint32_t reserved0: 15; + uint32_t pvt_dig_dbias: 5; /*get pvt dbias value*/ + uint32_t digulator0_dbias_slp: 5; /*the dig regulator0 dbias when chip in sleep state*/ + uint32_t digulator0_dbias_active: 5; /*the dig regulator0 dbias when chip in active state*/ + uint32_t digulator0_dbias_init: 1; /*initial pvt dbias value*/ + uint32_t digulator0_dbias_sel: 1; /*1: select sw dbias_active 0: select pvt value*/ + }; + uint32_t val; + } digulator0_dbias; + union { + struct { + uint32_t reserved0: 20; + uint32_t digulator1_dbias_slp: 4; /*the dig regulator1 dbias when chip in sleep state*/ + uint32_t reserved24: 1; + uint32_t digulator1_dbias_active: 4; /*the dig regulator1 dbias when chip in active state*/ + uint32_t reserved29: 3; + }; + uint32_t val; + } digulator1_dbias; union { struct { uint32_t reserved0: 21; - uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ + uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ uint32_t reserved22: 10; }; uint32_t val; @@ -416,78 +493,101 @@ typedef volatile struct { struct { uint32_t vdd_spi_pwr_drv: 2; uint32_t vdd_spi_pwr_force: 1; - uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ - uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ - uint32_t reserved5: 6; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t reserved5: 2; + uint32_t dg_mem_force_pd: 1; + uint32_t dg_mem_force_pu: 1; + uint32_t dg_wrap_force_pd: 1; + uint32_t dg_wrap_force_pu: 1; uint32_t bt_force_pd: 1; uint32_t bt_force_pu: 1; uint32_t dg_peri_force_pd: 1; uint32_t dg_peri_force_pu: 1; uint32_t fastmem_force_lpd: 1; uint32_t fastmem_force_lpu: 1; - uint32_t wifi_force_pd: 1; /*wifi force power down*/ - uint32_t wifi_force_pu: 1; /*wifi force power up*/ - uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ - uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t reserved19: 2; /*digital core force power down*/ uint32_t cpu_top_force_pd: 1; uint32_t cpu_top_force_pu: 1; - uint32_t reserved23: 4; + uint32_t reserved23: 3; + uint32_t dg_wrap_ret_pd_en: 1; uint32_t bt_pd_en: 1; uint32_t dg_peri_pd_en: 1; uint32_t cpu_top_pd_en: 1; - uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ uint32_t dg_wrap_pd_en: 1; }; uint32_t val; } dig_pwc; union { struct { - uint32_t reserved0: 7; + uint32_t reserved0: 2; + uint32_t xpd_dg_peri_switch_mask: 5; + uint32_t xpd_dg_wrap_switch_mask: 5; + uint32_t xpd_mem_switch_mask: 20; + }; + uint32_t val; + } dig_power_switch0; + union { + struct { + uint32_t reserved0: 22; + uint32_t xpd_wifi_switch_mask: 5; + uint32_t xpd_cpu_switch_mask: 5; + }; + uint32_t val; + } dig_power_switch1; + union { + struct { + uint32_t reserved0: 5; + uint32_t dg_mem_force_noiso: 1; + uint32_t dg_mem_force_iso: 1; uint32_t dig_iso_force_off: 1; uint32_t dig_iso_force_on: 1; - uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ - uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ - uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ - uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ - uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ - uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ - uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ uint32_t reserved16: 6; uint32_t bt_force_iso: 1; uint32_t bt_force_noiso: 1; uint32_t dg_peri_force_iso: 1; uint32_t dg_peri_force_noiso: 1; - uint32_t cpu_top_force_iso: 1; /*cpu force ISO*/ - uint32_t cpu_top_force_noiso: 1; /*cpu force no ISO*/ - uint32_t wifi_force_iso: 1; /*wifi force ISO*/ - uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ - uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t cpu_top_force_iso: 1; /*cpu force ISO*/ + uint32_t cpu_top_force_noiso: 1; /*cpu force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ uint32_t dg_wrap_force_noiso: 1; }; uint32_t val; } dig_iso; union { struct { - uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ - uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ - uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ - uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ - uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ - uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ - uint32_t sys_reset_length: 3; /*system reset counter length*/ - uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ - uint32_t stg3: 3; /*1: interrupt stage en*/ - uint32_t stg2: 3; /*1: interrupt stage en*/ - uint32_t stg1: 3; /*1: interrupt stage en*/ - uint32_t stg0: 3; /*1: interrupt stage en*/ + uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t stg3: 3; /*1: interrupt stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en*/ uint32_t en: 1; }; uint32_t val; } wdt_config0; - uint32_t wdt_config1; /**/ - uint32_t wdt_config2; /**/ - uint32_t wdt_config3; /**/ - uint32_t wdt_config4; /**/ + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ union { struct { uint32_t reserved0: 31; @@ -495,69 +595,77 @@ typedef volatile struct { }; uint32_t val; } wdt_feed; - uint32_t wdt_wprotect; /**/ + uint32_t wdt_wprotect; /**/ union { struct { - uint32_t swd_reset_flag: 1; /*swd reset flag*/ - uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ + uint32_t reserved0: 16; + uint32_t reset_chip_target: 8; + uint32_t reset_chip_key: 8; + }; + uint32_t val; + } wdtreset_chip; + union { + struct { + uint32_t swd_reset_flag: 1; /*swd reset flag*/ + uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ uint32_t reserved2: 15; uint32_t swd_bypass_rst: 1; - uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ - uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ - uint32_t swd_feed: 1; /*Sw feed swd*/ - uint32_t swd_disable: 1; /*disabel SWD*/ - uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ + uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ + uint32_t swd_feed: 1; /*Sw feed swd*/ + uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ }; uint32_t val; } swd_conf; - uint32_t swd_wprotect; /**/ + uint32_t swd_wprotect; /**/ union { struct { uint32_t reserved0: 20; - uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ uint32_t procpu_c1: 6; }; uint32_t val; } sw_cpu_stall; - uint32_t store4; /**/ - uint32_t store5; /**/ - uint32_t store6; /**/ - uint32_t store7; /**/ + uint32_t store4; /**/ + uint32_t store5; /**/ + uint32_t store6; /**/ + uint32_t store7; /**/ union { struct { - uint32_t xpd_rom0: 1; /*rom0 power down*/ + uint32_t xpd_rom0: 1; /*rom0 power down*/ uint32_t reserved1: 1; - uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ - uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ - uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ - uint32_t wifi_iso: 1; /*wifi iso*/ - uint32_t xpd_wifi: 1; /*wifi wrap power down*/ - uint32_t dig_iso: 1; /*digital wrap iso*/ - uint32_t xpd_dig: 1; /*digital wrap power down*/ - uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ - uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ - uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ - uint32_t rtc_touch_state_done: 1; /*touch is done*/ - uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ - uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ - uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ - uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ - uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ - uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ - uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ - uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ - uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ - uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ - uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ - uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ - uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ - uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ - uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ - uint32_t rtc_main_state: 4; /*rtc main state machine status*/ + uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ + uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ + uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ + uint32_t wifi_iso: 1; /*wifi iso*/ + uint32_t xpd_wifi: 1; /*wifi wrap power down*/ + uint32_t dig_iso: 1; /*digital wrap iso*/ + uint32_t xpd_dig: 1; /*digital wrap power down*/ + uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ + uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ + uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done: 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ + uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ + uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ + uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ + uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ + uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ + uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ + uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ + uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ + uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ + uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ + uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ + uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ + uint32_t rtc_main_state: 4; /*rtc main state machine status*/ }; uint32_t val; } low_power_st; - uint32_t diag0; /**/ + uint32_t diag0; /**/ union { struct { uint32_t rtc_gpio_pin0_hold: 1; @@ -570,38 +678,45 @@ typedef volatile struct { }; uint32_t val; } pad_hold; - uint32_t dig_pad_hold; /**/ + uint32_t dig_pad_hold; /**/ + union { + struct { + uint32_t dig_pad_hold1: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } dig_pad_hold1; union { struct { uint32_t reserved0: 4; - uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ - uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ - uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ - uint32_t rst_wait: 10; /*brown out reset wait cycles*/ - uint32_t rst_ena: 1; /*enable brown out reset*/ - uint32_t rst_sel: 1; /*1: 4-pos reset*/ + uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t rst_sel: 1; /*1: 4-pos reset*/ uint32_t ana_rst_en: 1; - uint32_t cnt_clr: 1; /*clear brown out counter*/ - uint32_t ena: 1; /*enable brown out*/ + uint32_t cnt_clr: 1; /*clear brown out counter*/ + uint32_t ena: 1; /*enable brown out*/ uint32_t det: 1; }; uint32_t val; } brown_out; - uint32_t time_low1; /*RTC timer low 32 bits*/ + uint32_t time_low1; /*RTC timer low 32 bits*/ union { struct { - uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/ + uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/ uint32_t reserved16: 16; }; uint32_t val; } time_high1; - uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ + uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ union { struct { - uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ - uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ - uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ - uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ + uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ }; uint32_t val; } xtal32k_conf; @@ -615,8 +730,8 @@ typedef volatile struct { } usb_conf; union { struct { - uint32_t reject_cause:18; /*sleep reject cause*/ - uint32_t reserved18: 14; + uint32_t reject_cause:19; /*sleep reject cause*/ + uint32_t reserved19: 13; }; uint32_t val; } slp_reject_cause; @@ -629,70 +744,82 @@ typedef volatile struct { } option1; union { struct { - uint32_t wakeup_cause:17; /*sleep wakeup cause*/ - uint32_t reserved17: 15; + uint32_t wakeup_cause:19; /*sleep wakeup cause*/ + uint32_t reserved19: 13; }; uint32_t val; } slp_wakeup_cause; union { struct { uint32_t reserved0: 8; - uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/ + uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/ }; uint32_t val; } ulp_cp_timer_1; union { struct { - uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ - uint32_t reserved4: 5; - uint32_t w1ts: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ - uint32_t reserved11: 4; - uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_bbpll_cal_w1ts: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4: 5; + uint32_t w1ts: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11: 4; + uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal_w1ts: 1; + uint32_t rtc_ble_compare_wake_w1ts: 1; + uint32_t vset_dcdc_done_w1ts: 1; + uint32_t reserved23: 9; }; uint32_t val; } int_ena_w1ts; union { struct { - uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ - uint32_t reserved4: 5; - uint32_t w1tc: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ - uint32_t reserved11: 4; - uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_bbpll_cal_w1tc: 1; - uint32_t reserved21: 11; + uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ + uint32_t reserved2: 1; + uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ + uint32_t reserved4: 5; + uint32_t w1tc: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved11: 4; + uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ + uint32_t reserved17: 2; + uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_bbpll_cal_w1tc: 1; + uint32_t rtc_ble_compare_wake_w1tc: 1; + uint32_t vset_dcdc_done_w1tc: 1; + uint32_t reserved23: 9; }; uint32_t val; } int_ena_w1tc; union { struct { - uint32_t reserved0: 18; + uint32_t reserved0: 17; + uint32_t clk_en: 1; uint32_t retention_clk_sel: 1; uint32_t retention_done_wait: 3; uint32_t retention_clkoff_wait: 4; uint32_t retention_en: 1; - uint32_t retention_wait: 5; /*wait cycles for rention operation*/ + uint32_t retention_wait: 5; /*wait cycles for rention operation*/ }; uint32_t val; } retention_ctrl; union { struct { - uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ + uint32_t retention_link_addr:27; + uint32_t reserved27: 5; + }; + uint32_t val; + } retention_ctrl1; + union { + struct { + uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ uint32_t reserved3: 29; }; uint32_t val; @@ -719,7 +846,7 @@ typedef volatile struct { } gpio_wakeup; union { struct { - uint32_t reserved0: 1; + uint32_t rtc_mtdi_enamux: 1; uint32_t rtc_debug_12m_no_gating: 1; uint32_t rtc_debug_bit_sel: 5; uint32_t rtc_debug_sel0: 5; @@ -732,7 +859,7 @@ typedef volatile struct { } dbg_sel; union { struct { - uint32_t reserved0: 2; + uint32_t vdd_dig_test: 2; uint32_t rtc_gpio_pin5_mux_sel: 1; uint32_t rtc_gpio_pin4_mux_sel: 1; uint32_t rtc_gpio_pin3_mux_sel: 1; @@ -748,14 +875,6 @@ typedef volatile struct { }; uint32_t val; } dbg_map; - union { - struct { - uint32_t reserved0: 27; - uint32_t sar2_pwdet_cct: 3; - uint32_t force_xpd_sar: 2; - }; - uint32_t val; - } sensor_ctrl; union { struct { uint32_t reserved0: 27; @@ -774,21 +893,62 @@ typedef volatile struct { }; uint32_t val; } pg_ctrl; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; + union { + struct { + uint32_t vset_dcdc_value: 5; + uint32_t power_good_dcdc: 1; + uint32_t reserved6: 15; + uint32_t ramplevel_dcdc: 1; + uint32_t ramp_dcdc: 1; + uint32_t dcm2enb_dcdc: 1; + uint32_t dcmlevel_dcdc: 2; + uint32_t fsw_dcdc: 3; + uint32_t ccm_dcdc: 1; + uint32_t sstime_dcdc: 1; + uint32_t pocpenb_dcdc: 1; + }; + uint32_t val; + } dcdc_ctrl0; + union { + struct { + uint32_t reserved0: 23; + uint32_t dcdc_mode_slp: 3; + uint32_t dcdc_mode_monitor: 3; + uint32_t dcdc_mode_idle: 3; + }; + uint32_t val; + } dcdc_ctrl1; + union { + struct { + uint32_t vset_dcdc_target_value1: 5; + uint32_t vset_dcdc_target_value0: 5; + uint32_t vset_dcdc_init_value: 5; + uint32_t vset_dcdc_init: 1; + uint32_t vset_dcdc_fix: 1; + uint32_t vset_dcdc_step: 5; + uint32_t vset_dcdc_gap: 5; + uint32_t vset_dcdc_sel_hw_sw: 1; + uint32_t vset_dcdc_sw_sel: 1; + uint32_t reserved29: 3; + }; + uint32_t val; + } dcdc_ctrl2; + union { + struct { + uint32_t reserved0: 21; + uint32_t rc32k_dfreq:10; + uint32_t rc32k_xpd: 1; + }; + uint32_t val; + } rc32k_ctrl; + union { + struct { + uint32_t reserved0: 30; + uint32_t ckref_pll8m_sel: 1; + uint32_t xpd_pll8m: 1; + }; + uint32_t val; + } pll8m; uint32_t reserved_164; uint32_t reserved_168; uint32_t reserved_16c; diff --git a/components/soc/esp32h2/include/soc/rtc_io_caps.h b/components/soc/esp32h2/include/soc/rtc_io_caps.h new file mode 100644 index 0000000000..5759afc43b --- /dev/null +++ b/components/soc/esp32h2/include/soc/rtc_io_caps.h @@ -0,0 +1,21 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/* No dedicated RTCIO subsystem on ESP32-H2. RTC functions are still supported + * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ +#define SOC_RTCIO_PIN_COUNT 0 + +#define RTCIO_LL_PIN_FUNC 0 diff --git a/components/soc/esp32h2/include/soc/sensitive_reg.h b/components/soc/esp32h2/include/soc/sensitive_reg.h index e1ce7d93ef..f1ee26ab8f 100644 --- a/components/soc/esp32h2/include/soc/sensitive_reg.h +++ b/components/soc/esp32h2/include/soc/sensitive_reg.h @@ -689,7 +689,181 @@ extern "C" { #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x080) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x080) +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x084) +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x088) +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x08C) +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x090) +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x094) +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x098) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) @@ -697,7 +871,7 @@ extern "C" { #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x084) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x09C) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ /*description: */ #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) @@ -711,7 +885,7 @@ extern "C" { #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x088) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0A0) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */ /*description: */ #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF @@ -731,7 +905,7 @@ extern "C" { #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x08C) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0A4) /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ /*description: */ #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F @@ -745,7 +919,7 @@ extern "C" { #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x090) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0A8) /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) @@ -753,7 +927,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x094) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0AC) /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000FF @@ -779,7 +953,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x098) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0B0) /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000FF @@ -805,7 +979,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x09C) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0B4) /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000FF @@ -831,7 +1005,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0A0) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0B8) /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000FF @@ -857,7 +1031,7 @@ extern "C" { #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0A4) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0BC) /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000FF @@ -883,7 +1057,7 @@ extern "C" { #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0A8) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0C0) /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) @@ -891,7 +1065,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0AC) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0C4) /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 @@ -929,7 +1103,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0B0) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0C8) /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 @@ -967,7 +1141,7 @@ extern "C" { #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0B4) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0CC) /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) @@ -975,7 +1149,7 @@ extern "C" { #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0B8) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0D0) /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) @@ -989,7 +1163,7 @@ extern "C" { #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0BC) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0D4) /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF @@ -1021,7 +1195,7 @@ extern "C" { #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0C0) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0D8) /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) @@ -1029,7 +1203,7 @@ extern "C" { #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0C4) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0DC) /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 @@ -1091,7 +1265,7 @@ extern "C" { #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0C8) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0E0) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) @@ -1099,7 +1273,7 @@ extern "C" { #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0CC) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0E4) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) @@ -1113,7 +1287,7 @@ extern "C" { #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0D0) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0E8) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF @@ -1139,7 +1313,7 @@ extern "C" { #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0D4) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0EC) /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F @@ -1153,7 +1327,7 @@ extern "C" { #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0D8) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0F0) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) @@ -1161,7 +1335,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0DC) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0F4) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 @@ -1198,24 +1372,12 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 @@ -1241,7 +1403,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0E0) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0F8) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 @@ -1260,12 +1422,12 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 @@ -1297,19 +1459,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0E4) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0FC) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 @@ -1341,67 +1491,55 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0E8) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x100) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 16 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S 16 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 @@ -1420,14 +1558,64 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0EC) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x104) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x108) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 @@ -1464,24 +1652,12 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 @@ -1507,7 +1683,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x0F0) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x10C) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 @@ -1526,12 +1702,12 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 @@ -1563,19 +1739,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x0F4) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x110) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 @@ -1607,67 +1771,55 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x0F8) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x114) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 16 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S 16 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S 12 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 @@ -1686,14 +1838,64 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x0FC) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x118) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x11C) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF @@ -1707,7 +1909,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x100) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x120) /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 @@ -1733,7 +1935,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x104) +#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124) /* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) @@ -1741,7 +1943,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V 0x1 #define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x108) +#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128) /* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 @@ -1785,7 +1987,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x3 #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x10C) +#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12C) /* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 @@ -1829,7 +2031,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x3 #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x110) +#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF @@ -1837,7 +2039,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x114) +#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFF @@ -1845,7 +2047,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x118) +#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF @@ -1853,7 +2055,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x11C) +#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13C) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFF @@ -1861,7 +2063,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x120) +#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF @@ -1869,7 +2071,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x124) +#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFF @@ -1877,7 +2079,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x128) +#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF @@ -1885,7 +2087,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S 0 -#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x12C) +#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14C) /* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ /*description: */ #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFF @@ -1893,7 +2095,7 @@ extern "C" { #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFF #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x130) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x150) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) @@ -1901,7 +2103,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x134) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x154) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) @@ -1915,7 +2117,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x138) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x158) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 @@ -1947,7 +2149,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x13C) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x15C) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF @@ -1955,7 +2157,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x140) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x160) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) @@ -1969,7 +2171,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x144) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x164) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 @@ -1989,7 +2191,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x148) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x168) /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF @@ -1997,7 +2199,7 @@ extern "C" { #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x14C) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x16C) /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) @@ -2005,7 +2207,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x1 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x150) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x170) /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003 @@ -2042,24 +2244,12 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S)) #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S 12 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S)) #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S 8 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003 @@ -2085,7 +2275,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x154) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x174) /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003 @@ -2104,12 +2294,12 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S)) #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ /*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S 22 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S 18 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003 @@ -2141,19 +2331,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x158) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S 28 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S 26 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x178) /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003 @@ -2185,19 +2363,55 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x15C) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x17C) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S 30 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S 28 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S 26 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S 22 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S 20 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S 18 +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S 16 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S)) #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 14 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S 12 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003 @@ -2216,14 +2430,16 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S)) #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x3 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S 2 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x160) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x180) +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V 0x3 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S 0 + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x184) /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) @@ -2231,7 +2447,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x1 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x164) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x188) /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) @@ -2245,7 +2461,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x1 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x168) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x18C) /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) @@ -2271,7 +2487,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x1 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x16C) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x190) /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xFFFFFFFF @@ -2279,7 +2495,7 @@ extern "C" { #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xFFFFFFFF #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 -#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x170) +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x194) /* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define SENSITIVE_CLK_EN (BIT(0)) @@ -2288,7 +2504,7 @@ extern "C" { #define SENSITIVE_CLK_EN_S 0 #define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) -/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010200 ; */ +/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101190 ; */ /*description: */ #define SENSITIVE_DATE 0x0FFFFFFF #define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) diff --git a/components/soc/esp32h2/include/soc/sensitive_struct.h b/components/soc/esp32h2/include/soc/sensitive_struct.h index a24ccf6402..cf27320a79 100644 --- a/components/soc/esp32h2/include/soc/sensitive_struct.h +++ b/components/soc/esp32h2/include/soc/sensitive_struct.h @@ -328,8 +328,77 @@ typedef volatile struct { } dma_apbperi_adc_dac_pms_constrain_1; union { struct { - uint32_t reg_dma_apbperi_pms_monitor_lock: 1; /*dma_apbperi_pms_monitor_lock*/ - uint32_t reserved1 : 31; + uint32_t dma_apbperi_ble_sec_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_ble_sec_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0: 2; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1: 2; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2: 2; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3: 2; + uint32_t reserved8: 4; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0: 2; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1: 2; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2: 2; + uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3: 2; + uint32_t reserved20: 4; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_ble_sec_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_white_list_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_white_list_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0: 2; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1: 2; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2: 2; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3: 2; + uint32_t reserved8: 4; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0: 2; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1: 2; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2: 2; + uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3: 2; + uint32_t reserved20: 4; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_white_list_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_sdio_host_pms_constrain_0; + union { + struct { + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0: 2; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1: 2; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2: 2; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3: 2; + uint32_t reserved8: 4; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0: 2; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1: 2; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2: 2; + uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3: 2; + uint32_t reserved20: 4; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_sdio_host_pms_constrain_1; + union { + struct { + uint32_t reg_dma_apbperi_pms_monitor_lock: 1; + uint32_t reserved1: 31; }; uint32_t val; } dma_apbperi_pms_monitor_0; @@ -514,7 +583,7 @@ typedef volatile struct { union { struct { uint32_t reg_core_0_dram0_pms_monitor_violate_clr: 1; /*core_0_dram0_pms_monitor_violate_clr*/ - uint32_t reg_core_0_dram0_pms_monitor_violate_en: 1; /*core_0_dram0_pms_monitor_violate_en*/ + uint32_t reg_core_0_dram0_pms_monitor_violate_en: 1; /*core_0_dram0_pms_monitor_violate_en*/ uint32_t reserved2 : 30; }; uint32_t val; @@ -550,9 +619,9 @@ typedef volatile struct { uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1: 2; /*core_0_pif_pms_constrain_world_0_g0spi_1*/ uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0: 2; /*core_0_pif_pms_constrain_world_0_g0spi_0*/ uint32_t reg_core_0_pif_pms_constrain_world_0_gpio: 2; /*core_0_pif_pms_constrain_world_0_gpio*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_fe2: 2; /*core_0_pif_pms_constrain_world_0_fe2*/ + uint32_t reserved8: 2; uint32_t reg_core_0_pif_pms_constrain_world_0_fe: 2; /*core_0_pif_pms_constrain_world_0_fe*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_timer: 2; /*core_0_pif_pms_constrain_world_0_timer*/ + uint32_t reserved12: 2; uint32_t reg_core_0_pif_pms_constrain_world_0_rtc: 2; /*core_0_pif_pms_constrain_world_0_rtc*/ uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux: 2; /*core_0_pif_pms_constrain_world_0_io_mux*/ uint32_t reg_core_0_pif_pms_constrain_world_0_wdg: 2; /*core_0_pif_pms_constrain_world_0_wdg*/ @@ -574,12 +643,13 @@ typedef volatile struct { uint32_t reg_core_0_pif_pms_constrain_world_0_rmt: 2; /*core_0_pif_pms_constrain_world_0_rmt*/ uint32_t reserved12 : 4; uint32_t reg_core_0_pif_pms_constrain_world_0_ledc: 2; /*core_0_pif_pms_constrain_world_0_ledc*/ - uint32_t reserved18 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_0_bb: 2; /*core_0_pif_pms_constrain_world_0_bb*/ - uint32_t reserved24 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup: 2; /*core_0_pif_pms_constrain_world_0_timergroup*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1: 2; /*core_0_pif_pms_constrain_world_0_timergroup1*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_systimer: 2; /*core_0_pif_pms_constrain_world_0_systimer*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_efuse: 2; + uint32_t reserved20: 2; + uint32_t reserved22: 2; + uint32_t reserved24: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_systimer: 2; }; uint32_t val; } core_0_pif_pms_constrain_2; @@ -595,8 +665,8 @@ typedef volatile struct { uint32_t reserved16 : 6; uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt: 2; /*core_0_pif_pms_constrain_world_0_rwbt*/ uint32_t reserved24 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_wifimac: 2; /*core_0_pif_pms_constrain_world_0_wifimac*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_pwr: 2; /*core_0_pif_pms_constrain_world_0_pwr*/ + uint32_t reserved26: 2; + uint32_t reserved28: 2; uint32_t reserved30 : 2; }; uint32_t val; @@ -604,124 +674,155 @@ typedef volatile struct { union { struct { uint32_t reserved0 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_usb_wrap: 2; /*core_0_pif_pms_constrain_world_0_usb_wrap*/ + uint32_t reserved2: 2; uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri: 2; /*core_0_pif_pms_constrain_world_0_crypto_peri*/ uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma: 2; /*core_0_pif_pms_constrain_world_0_crypto_dma*/ uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc: 2; /*core_0_pif_pms_constrain_world_0_apb_adc*/ uint32_t reserved10 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_bt_pwr: 2; /*core_0_pif_pms_constrain_world_0_bt_pwr*/ + uint32_t reserved12: 2; uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device: 2; /*core_0_pif_pms_constrain_world_0_usb_device*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_system: 2; /*core_0_pif_pms_constrain_world_0_system*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive: 2; /*core_0_pif_pms_constrain_world_0_sensitive*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt: 2; /*core_0_pif_pms_constrain_world_0_interrupt*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy: 2; /*core_0_pif_pms_constrain_world_0_dma_copy*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config: 2; /*core_0_pif_pms_constrain_world_0_cache_config*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_ad: 2; /*core_0_pif_pms_constrain_world_0_ad*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_dio: 2; /*core_0_pif_pms_constrain_world_0_dio*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller: 2; /*core_0_pif_pms_constrain_world_0_world_controller*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_etm: 2; /*core_0_pif_pms_constrain_world_0_system*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup3: 2; /*core_0_pif_pms_constrain_world_0_sensitive*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_ble_sec: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_ieee802154mac: 2; + uint32_t reserved24: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_coex: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_rtc_ble_tmr: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_clkrst: 2; }; uint32_t val; } core_0_pif_pms_constrain_4; union { struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_uart: 2; /*core_0_pif_pms_constrain_world_1_uart*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1: 2; /*core_0_pif_pms_constrain_world_1_g0spi_1*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0: 2; /*core_0_pif_pms_constrain_world_1_g0spi_0*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_gpio: 2; /*core_0_pif_pms_constrain_world_1_gpio*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_fe2: 2; /*core_0_pif_pms_constrain_world_1_fe2*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_fe: 2; /*core_0_pif_pms_constrain_world_1_fe*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_timer: 2; /*core_0_pif_pms_constrain_world_1_timer*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_rtc: 2; /*core_0_pif_pms_constrain_world_1_rtc*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux: 2; /*core_0_pif_pms_constrain_world_1_io_mux*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_wdg: 2; /*core_0_pif_pms_constrain_world_1_wdg*/ - uint32_t reserved20 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_misc: 2; /*core_0_pif_pms_constrain_world_1_misc*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_i2c: 2; /*core_0_pif_pms_constrain_world_1_i2c*/ - uint32_t reserved28 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_uart1: 2; /*core_0_pif_pms_constrain_world_1_uart1*/ + uint32_t reg_core_0_pif_pms_constrain_world_0_pvt: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_system: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_ad: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_dio: 2; + uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller: 2; + uint32_t reserved18: 14; }; uint32_t val; } core_0_pif_pms_constrain_5; union { struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_bt: 2; /*core_0_pif_pms_constrain_world_1_bt*/ - uint32_t reserved2 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0: 2; /*core_0_pif_pms_constrain_world_1_i2c_ext0*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0: 2; /*core_0_pif_pms_constrain_world_1_uhci0*/ - uint32_t reserved8 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_rmt: 2; /*core_0_pif_pms_constrain_world_1_rmt*/ - uint32_t reserved12 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_ledc: 2; /*core_0_pif_pms_constrain_world_1_ledc*/ - uint32_t reserved18 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_bb: 2; /*core_0_pif_pms_constrain_world_1_bb*/ - uint32_t reserved24 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup: 2; /*core_0_pif_pms_constrain_world_1_timergroup*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1: 2; /*core_0_pif_pms_constrain_world_1_timergroup1*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_systimer: 2; /*core_0_pif_pms_constrain_world_1_systimer*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_uart: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_gpio: 2; + uint32_t reserved8: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_fe: 2; + uint32_t reserved12: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_rtc: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_wdg: 2; + uint32_t reserved20: 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_misc: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_i2c: 2; + uint32_t reserved28: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_uart1: 2; }; uint32_t val; } core_0_pif_pms_constrain_6; union { struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2: 2; /*core_0_pif_pms_constrain_world_1_spi_2*/ - uint32_t reserved2 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2; /*core_0_pif_pms_constrain_world_1_apb_ctrl*/ - uint32_t reserved6 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2; /*core_0_pif_pms_constrain_world_1_can*/ - uint32_t reserved12 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; /*core_0_pif_pms_constrain_world_1_i2s1*/ - uint32_t reserved16 : 6; - uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; /*core_0_pif_pms_constrain_world_1_rwbt*/ - uint32_t reserved24 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_wifimac: 2; /*core_0_pif_pms_constrain_world_1_wifimac*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_pwr: 2; /*core_0_pif_pms_constrain_world_1_pwr*/ - uint32_t reserved30 : 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_bt: 2; + uint32_t reserved2: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0: 2; + uint32_t reserved8: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_rmt: 2; + uint32_t reserved12: 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_ledc: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_efuse: 2; + uint32_t reserved20: 2; + uint32_t reserved22: 2; + uint32_t reserved24: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_systimer: 2; }; uint32_t val; } core_0_pif_pms_constrain_7; union { struct { - uint32_t reserved0 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_usb_wrap: 2; /*core_0_pif_pms_constrain_world_1_usb_wrap*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri: 2; /*core_0_pif_pms_constrain_world_1_crypto_peri*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma: 2; /*core_0_pif_pms_constrain_world_1_crypto_dma*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc: 2; /*core_0_pif_pms_constrain_world_1_apb_adc*/ - uint32_t reserved10 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_bt_pwr: 2; /*core_0_pif_pms_constrain_world_1_bt_pwr*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device: 2; /*core_0_pif_pms_constrain_world_1_usb_device*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_system: 2; /*core_0_pif_pms_constrain_world_1_system*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive: 2; /*core_0_pif_pms_constrain_world_1_sensitive*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt: 2; /*core_0_pif_pms_constrain_world_1_interrupt*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy: 2; /*core_0_pif_pms_constrain_world_1_dma_copy*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config: 2; /*core_0_pif_pms_constrain_world_1_cache_config*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_ad: 2; /*core_0_pif_pms_constrain_world_1_ad*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_dio: 2; /*core_0_pif_pms_constrain_world_1_dio*/ - uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller: 2; /*core_0_pif_pms_constrain_world_1_world_controller*/ + uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2: 2; + uint32_t reserved2: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2; + uint32_t reserved6: 4; + uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2; + uint32_t reserved12: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; + uint32_t reserved16: 6; + uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; + uint32_t reserved24: 2; + uint32_t reserved26: 2; + uint32_t reserved28: 2; + uint32_t reserved30: 2; }; uint32_t val; } core_0_pif_pms_constrain_8; union { struct { - uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_0*/ - uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_1*/ - uint32_t reserved22 : 10; + uint32_t reserved0: 2; + uint32_t reserved2: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc: 2; + uint32_t reserved10: 2; + uint32_t reserved12: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_etm: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup3: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_ble_sec: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_ieee802154mac: 2; + uint32_t reserved24: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_coex: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_rtc_ble_tmr: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_clkrst: 2; }; uint32_t val; } core_0_pif_pms_constrain_9; union { struct { - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l: 3; /*core_0_pif_pms_constrain_rtcfast_world_0_l*/ - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h: 3; /*core_0_pif_pms_constrain_rtcfast_world_0_h*/ - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l: 3; /*core_0_pif_pms_constrain_rtcfast_world_1_l*/ - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h: 3; /*core_0_pif_pms_constrain_rtcfast_world_1_h*/ - uint32_t reserved12 : 20; + uint32_t reg_core_0_pif_pms_constrain_world_1_pvt: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_system: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_ad: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_dio: 2; + uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller: 2; + uint32_t reserved18: 14; }; uint32_t val; } core_0_pif_pms_constrain_10; union { struct { - uint32_t reg_region_pms_constrain_lock : 1; /*region_pms_constrain_lock*/ - uint32_t reserved1 : 31; + uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:11; + uint32_t reg_ore_0_pif_pms_constrain_rtcfast_spltaddr_world_1:11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_0_pif_pms_constrain_11; + union { + struct { + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l: 3; + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h: 3; + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l: 3; + uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_pif_pms_constrain_12; + union { + struct { + uint32_t region_pms_constrain_lock: 1; + uint32_t reserved1: 31; }; uint32_t val; } sensitiveion_pms_constrain_0; @@ -847,7 +948,7 @@ typedef volatile struct { uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr: 1; /*core_0_pif_pms_monitor_nonword_violate_intr*/ uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/ uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/ - uint32_t reserved5 : 27; + uint32_t reserved5: 27; }; uint32_t val; } core_0_pif_pms_monitor_5; @@ -865,9 +966,9 @@ typedef volatile struct { uint32_t reg_backup_bus_pms_constrain_g0spi_1: 2; /*backup_bus_pms_constrain_g0spi_1*/ uint32_t reg_backup_bus_pms_constrain_g0spi_0: 2; /*backup_bus_pms_constrain_g0spi_0*/ uint32_t reg_backup_bus_pms_constrain_gpio: 2; /*backup_bus_pms_constrain_gpio*/ - uint32_t reg_backup_bus_pms_constrain_fe2: 2; /*backup_bus_pms_constrain_fe2*/ + uint32_t reserved8: 2; uint32_t reg_backup_bus_pms_constrain_fe: 2; /*backup_bus_pms_constrain_fe*/ - uint32_t reg_backup_bus_pms_constrain_timer: 2; /*backup_bus_pms_constrain_timer*/ + uint32_t reserved12: 2; uint32_t reg_backup_bus_pms_constrain_rtc: 2; /*backup_bus_pms_constrain_rtc*/ uint32_t reg_backup_bus_pms_constrain_io_mux: 2; /*backup_bus_pms_constrain_io_mux*/ uint32_t reg_backup_bus_pms_constrain_wdg: 2; /*backup_bus_pms_constrain_wdg*/ @@ -889,8 +990,9 @@ typedef volatile struct { uint32_t reg_backup_bus_pms_constrain_rmt: 2; /*backup_bus_pms_constrain_rmt*/ uint32_t reserved12 : 4; uint32_t reg_backup_bus_pms_constrain_ledc: 2; /*backup_bus_pms_constrain_ledc*/ - uint32_t reserved18 : 4; - uint32_t reg_backup_bus_pms_constrain_bb: 2; /*backup_bus_pms_constrain_bb*/ + uint32_t reg_backup_bus_pms_constrain_efuse: 2; + uint32_t reserved20 : 2; + uint32_t reserved22 : 2; uint32_t reserved24 : 2; uint32_t reg_backup_bus_pms_constrain_timergroup: 2; /*backup_bus_pms_constrain_timergroup*/ uint32_t reg_backup_bus_pms_constrain_timergroup1: 2; /*backup_bus_pms_constrain_timergroup1*/ @@ -910,30 +1012,44 @@ typedef volatile struct { uint32_t reserved16 : 6; uint32_t reg_backup_bus_pms_constrain_rwbt: 2; /*backup_bus_pms_constrain_rwbt*/ uint32_t reserved24 : 2; - uint32_t reg_backup_bus_pms_constrain_wifimac: 2; /*backup_bus_pms_constrain_wifimac*/ - uint32_t reg_backup_bus_pms_constrain_pwr: 2; /*backup_bus_pms_constrain_pwr*/ + uint32_t reserved26 : 2; + uint32_t reserved28 : 2; uint32_t reserved30 : 2; }; uint32_t val; } backup_bus_pms_constrain_3; union { struct { - uint32_t reserved0 : 2; - uint32_t reg_backup_bus_pms_constrain_usb_wrap: 2; /*backup_bus_pms_constrain_usb_wrap*/ - uint32_t reg_backup_bus_pms_constrain_crypto_peri: 2; /*backup_bus_pms_constrain_crypto_peri*/ - uint32_t reg_backup_bus_pms_constrain_crypto_dma: 2; /*backup_bus_pms_constrain_crypto_dma*/ - uint32_t reg_backup_bus_pms_constrain_apb_adc: 2; /*backup_bus_pms_constrain_apb_adc*/ - uint32_t reserved10 : 2; - uint32_t reg_backup_bus_pms_constrain_bt_pwr: 2; /*backup_bus_pms_constrain_bt_pwr*/ - uint32_t reg_backup_bus_pms_constrain_usb_device: 2; /*backup_bus_pms_constrain_usb_device*/ - uint32_t reserved16 : 16; + uint32_t reserved0: 2; + uint32_t reserved2: 2; + uint32_t reg_backup_bus_pms_constrain_crypto_peri: 2; + uint32_t reg_backup_bus_pms_constrain_crypto_dma: 2; + uint32_t reg_backup_bus_pms_constrain_apb_adc: 2; + uint32_t reserved10: 2; + uint32_t reserved12: 2; + uint32_t reg_backup_bus_pms_constrain_usb_device: 2; + uint32_t reg_backup_bus_pms_constrain_etm: 2; + uint32_t reg_backup_bus_pms_constrain_timergroup3: 2; + uint32_t reg_backup_bus_pms_constrain_ble_sec: 2; + uint32_t backup_bus_pms_constrain_ieee802154mac: 2; + uint32_t reserved24: 2; + uint32_t reg_backup_bus_pms_constrain_coex: 2; + uint32_t reg_backup_bus_pms_constrain_rtc_ble_tmr: 2; + uint32_t reg_backup_bus_pms_constrain_clkrst: 2; }; uint32_t val; } backup_bus_pms_constrain_4; union { struct { - uint32_t reg_backup_bus_pms_monitor_lock: 1; /*backup_bus_pms_monitor_lock*/ - uint32_t reserved1 : 31; + uint32_t backup_bus_pms_constrain_pvt: 2; + uint32_t reserved2: 30; + }; + uint32_t val; + } backup_bus_pms_constrain_5; + union { + struct { + uint32_t backup_bus_pms_monitor_lock: 1; + uint32_t reserved1: 31; }; uint32_t val; } backup_bus_pms_monitor_0; @@ -958,9 +1074,8 @@ typedef volatile struct { uint32_t backup_bus_pms_monitor_3; union { struct { - uint32_t reg_clk_en : 1; /*clk_en*/ - uint32_t reserved1 : 31; - uint32_t reservedNone : None; /*SENSITIVE_CLOCK_GATE_REG_REG*/ + uint32_t reg_clk_en: 1; + uint32_t reserved1: 31; }; uint32_t val; } clock_gate; @@ -1907,6 +2022,4 @@ extern sensitive_dev_t SENSITIVE; } #endif - - #endif /*_SOC_SENSITIVE_STRUCT_H_ */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 8c1963c3f9..8215c4099b 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -29,52 +29,83 @@ #define DR_REG_INTERRUPT_BASE 0x600c2000 #define DR_REG_EXTMEM_BASE 0x600c4000 #define DR_REG_MMU_TABLE 0x600c5000 + +#define DR_REG_ITAG_TABLE 0x600c6000 +#define DR_REG_DTAG_TABLE 0x600c8000 +#define DR_REG_ECC_MULT_BASE 0x60039000 #define DR_REG_AES_BASE 0x6003a000 #define DR_REG_SHA_BASE 0x6003b000 #define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_HMAC_BASE 0x6003e000 #define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_HMAC_BASE 0x6003e000 #define DR_REG_GDMA_BASE 0x6003f000 + #define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 #define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 #define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_DPORT_END 0x600d3FFC +// #define DR_REG_DPORT_END 0x600d3FFC #define DR_REG_UART_BASE 0x60000000 #define DR_REG_SPI1_BASE 0x60002000 #define DR_REG_SPI0_BASE 0x60003000 #define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_GPIO_SD_BASE 0x60004f00 #define DR_REG_FE2_BASE 0x60005000 #define DR_REG_FE_BASE 0x60006000 +#define DR_REG_FRC_TIMER_BASE 0x60007000 #define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_RTCIO_BASE 0x60008400 +#define DR_REG_SENS_BASE 0x60008800 +#define DR_REG_RTC_I2C_BASE 0x60008C00 #define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_HINF_BASE 0x6002B000 +#define DR_REG_UHCI1_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000F000 #define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_BT_BASE 0x60011000 #define DR_REG_I2C_EXT_BASE 0x60013000 #define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_SLCHOST_BASE 0x60019000 #define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_PCNT_BASE 0x60017000 +#define DR_REG_SLC_BASE 0x6002D000 #define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_EFUSE_BASE 0x6001A000 #define DR_REG_NRX_BASE 0x6001CC00 #define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_PWM_BASE 0x6001E000 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 +#define DR_REG_SYS_TIMER_BASE 0x60023000 #define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SPI3_BASE 0x60025000 #define DR_REG_SYSCON_BASE 0x60026000 #define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_I2S0_BASE 0x6002D000 +#define DR_REG_I2C1_EXT_BASE 0x60027000 +#define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_CAN_BASE 0x6002B000 +#define DR_REG_PWM1_BASE 0x6002C000 +#define DR_REG_I2S1_BASE 0x6002D000 +#define DR_REG_UART2_BASE 0x6002E000 +#define DR_REG_PWM2_BASE 0x6002F000 +#define DR_REG_PWM3_BASE 0x60030000 +#define DR_REG_SPI4_BASE 0x60037000 +#define DR_REG_USB_WRAP_BASE 0x60039000 #define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_LCD_CAM_BASE 0x60041000 #define DR_REG_AES_XTS_BASE 0x600CC000 +#define DR_REG_USB_DEVICE_BASE 0x60043000 +#define DR_REG_CLKRST_BASE 0x6004B000 -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) @@ -190,19 +221,19 @@ //}} //Periheral Clock {{ -#define APB_CLK_FREQ_ROM ( 40*1000000 ) +#define APB_CLK_FREQ_ROM ( 32*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 40*1000000) +#define UART_CLK_FREQ_ROM ( 32*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #if CONFIG_IDF_ENV_FPGA -#define APB_CLK_FREQ ( 40*1000000 ) +#define APB_CLK_FREQ ( 32*1000000 ) #else #define APB_CLK_FREQ ( 80*1000000 ) #endif #define REF_CLK_FREQ ( 1000000 ) #define RTC_CLK_FREQ (20*1000000) -#define XTAL_CLK_FREQ (40*1000000) +#define XTAL_CLK_FREQ (32*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 @@ -224,7 +255,7 @@ #define SOC_IRAM_HIGH 0x403E0000 #define SOC_DRAM_LOW 0x3FC80000 #define SOC_DRAM_HIGH 0x3FCE0000 -#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C3 only has RTC slow memory +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H2 only has RTC slow memory #define SOC_RTC_IRAM_HIGH 0x50002000 #define SOC_RTC_DRAM_LOW 0x50000000 #define SOC_RTC_DRAM_HIGH 0x50002000 @@ -315,7 +346,7 @@ #define ETS_FRC1_INUM 22 #define ETS_T1_WDT_INUM 24 #define ETS_CACHEERR_INUM 25 -#ifdef CONFIG_IDF_TARGET_ESP32C3 +#ifdef CONFIG_IDF_TARGET_ESP32H2 #define ETS_MEMPROT_ERR_INUM 26 #endif #define ETS_DPORT_INUM 28 diff --git a/components/soc/esp32h2/include/soc/spi_caps.h b/components/soc/esp32h2/include/soc/spi_caps.h new file mode 100644 index 0000000000..fefb464f6f --- /dev/null +++ b/components/soc/esp32h2/include/soc/spi_caps.h @@ -0,0 +1,38 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_DMA_CHAN_NUM 3 +#define SOC_SPI_PERIPH_CS_NUM(i) 3 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 + +//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) + +// Peripheral supports output given level during its "dummy phase" +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 + +#define SOC_MEMSPI_IS_INDEPENDENT 1 + +#define SOC_SPI_MAX_PRE_DIVIDER 16 diff --git a/components/soc/esp32h2/include/soc/spi_reg.h b/components/soc/esp32h2/include/soc/spi_reg.h index a08cb24f3c..d50dadd641 100644 --- a/components/soc/esp32h2/include/soc/spi_reg.h +++ b/components/soc/esp32h2/include/soc/spi_reg.h @@ -51,21 +51,21 @@ clock domain, which is only used in SPI master mode..*/ #define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF #define SPI_USR_ADDR_VALUE_S 0 -#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) -/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con -figured in CONF state..*/ -#define SPI_WR_BIT_ORDER (BIT(26)) -#define SPI_WR_BIT_ORDER_M (BIT(26)) -#define SPI_WR_BIT_ORDER_V 0x1 -#define SPI_WR_BIT_ORDER_S 26 -/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s -tate..*/ -#define SPI_RD_BIT_ORDER (BIT(25)) -#define SPI_RD_BIT_ORDER_M (BIT(25)) -#define SPI_RD_BIT_ORDER_V 0x1 -#define SPI_RD_BIT_ORDER_S 25 +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB + first. Can be configured in CONF state.*/ +#define SPI_WR_BIT_ORDER 0x00000003 +#define SPI_WR_BIT_ORDER_M ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S)) +#define SPI_WR_BIT_ORDER_V 0x3 +#define SPI_WR_BIT_ORDER_S 25 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured + in CONF state.*/ +#define SPI_RD_BIT_ORDER 0x00000003 +#define SPI_RD_BIT_ORDER_M ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S)) +#define SPI_RD_BIT_ORDER_V 0x3 +#define SPI_RD_BIT_ORDER_S 23 /* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */ /*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. C an be configured in CONF state..*/ @@ -641,6 +641,20 @@ _vld is cleared by spi_trans_done..*/ #define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) #define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 #define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready + for receiving data. 0: DMA RX FIFO is ready for receiving data.*/ +#define SPI_DMA_INFIFO_FULL (BIT(1)) +#define SPI_DMA_INFIFO_FULL_M (BIT(1)) +#define SPI_DMA_INFIFO_FULL_V 0x1 +#define SPI_DMA_INFIFO_FULL_S 1 +/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready + for sending data. 0: DMA TX FIFO is ready for sending data.*/ +#define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_M (BIT(0)) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_S 0 #define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34) /* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ @@ -1178,257 +1192,384 @@ the receive data. 0: Others. .*/ #define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x1 #define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 -#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98) +#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x044) +/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_APP1_INT interrupt.*/ +#define SPI_APP1_INT_SET (BIT(20)) +#define SPI_APP1_INT_SET_M (BIT(20)) +#define SPI_APP1_INT_SET_V 0x1 +#define SPI_APP1_INT_SET_S 20 +/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_APP2_INT interrupt.*/ +#define SPI_APP2_INT_SET (BIT(19)) +#define SPI_APP2_INT_SET_M (BIT(19)) +#define SPI_APP2_INT_SET_V 0x1 +#define SPI_APP2_INT_SET_S 19 +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x1 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/ +#define SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_SET_V 0x1 +#define SPI_SLV_CMD_ERR_INT_SET_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ +#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_SET_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13 +/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_TRANS_DONE_INT interrupt.*/ +#define SPI_TRANS_DONE_INT_SET (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_M (BIT(12)) +#define SPI_TRANS_DONE_INT_SET_V 0x1 +#define SPI_TRANS_DONE_INT_SET_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8 +/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMDA interrupt.*/ +#define SPI_SLV_CMDA_INT_SET (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_M (BIT(7)) +#define SPI_SLV_CMDA_INT_SET_V 0x1 +#define SPI_SLV_CMDA_INT_SET_S 7 +/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMD9 interrupt.*/ +#define SPI_SLV_CMD9_INT_SET (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_M (BIT(6)) +#define SPI_SLV_CMD9_INT_SET_V 0x1 +#define SPI_SLV_CMD9_INT_SET_S 6 +/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMD8 interrupt.*/ +#define SPI_SLV_CMD8_INT_SET (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_M (BIT(5)) +#define SPI_SLV_CMD8_INT_SET_V 0x1 +#define SPI_SLV_CMD8_INT_SET_S 5 +/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave CMD7 interrupt.*/ +#define SPI_SLV_CMD7_INT_SET (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_M (BIT(4)) +#define SPI_SLV_CMD7_INT_SET_V 0x1 +#define SPI_SLV_CMD7_INT_SET_S 4 +/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave En_QPI interrupt.*/ +#define SPI_SLV_EN_QPI_INT_SET (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_SET_V 0x1 +#define SPI_SLV_EN_QPI_INT_SET_S 3 +/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The software set bit for SPI slave Ex_QPI interrupt.*/ +#define SPI_SLV_EX_QPI_INT_SET (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_SET_V 0x1 +#define SPI_SLV_EX_QPI_INT_SET_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x098) /* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF0 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF0 0xFFFFFFFF #define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) #define SPI_BUF0_V 0xFFFFFFFF #define SPI_BUF0_S 0 -#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9C) +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x09C) /* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF1 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF1 0xFFFFFFFF #define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) #define SPI_BUF1_V 0xFFFFFFFF #define SPI_BUF1_S 0 -#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xA0) +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0A0) /* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF2 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF2 0xFFFFFFFF #define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) #define SPI_BUF2_V 0xFFFFFFFF #define SPI_BUF2_S 0 -#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xA4) +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0A4) /* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF3 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF3 0xFFFFFFFF #define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) #define SPI_BUF3_V 0xFFFFFFFF #define SPI_BUF3_S 0 -#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xA8) +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0A8) /* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF4 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF4 0xFFFFFFFF #define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) #define SPI_BUF4_V 0xFFFFFFFF #define SPI_BUF4_S 0 -#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xAC) +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0AC) /* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF5 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF5 0xFFFFFFFF #define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) #define SPI_BUF5_V 0xFFFFFFFF #define SPI_BUF5_S 0 -#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xB0) +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0B0) /* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF6 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF6 0xFFFFFFFF #define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) #define SPI_BUF6_V 0xFFFFFFFF #define SPI_BUF6_S 0 -#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xB4) +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0B4) /* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF7 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF7 0xFFFFFFFF #define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) #define SPI_BUF7_V 0xFFFFFFFF #define SPI_BUF7_S 0 -#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xB8) +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0B8) /* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF8 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF8 0xFFFFFFFF #define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) #define SPI_BUF8_V 0xFFFFFFFF #define SPI_BUF8_S 0 -#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xBC) +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0BC) /* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF9 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF9 0xFFFFFFFF #define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) #define SPI_BUF9_V 0xFFFFFFFF #define SPI_BUF9_S 0 -#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xC0) +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0C0) /* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF10 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF10 0xFFFFFFFF #define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) #define SPI_BUF10_V 0xFFFFFFFF #define SPI_BUF10_S 0 -#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xC4) +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0C4) /* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF11 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF11 0xFFFFFFFF #define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) #define SPI_BUF11_V 0xFFFFFFFF #define SPI_BUF11_S 0 -#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xC8) +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0C8) /* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF12 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF12 0xFFFFFFFF #define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) #define SPI_BUF12_V 0xFFFFFFFF #define SPI_BUF12_S 0 -#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xCC) +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0CC) /* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF13 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF13 0xFFFFFFFF #define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) #define SPI_BUF13_V 0xFFFFFFFF #define SPI_BUF13_S 0 -#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xD0) +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0D0) /* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF14 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF14 0xFFFFFFFF #define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) #define SPI_BUF14_V 0xFFFFFFFF #define SPI_BUF14_S 0 -#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xD4) +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0D4) /* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: data buffer.*/ -#define SPI_BUF15 0xFFFFFFFF +/*description: data buffer*/ +#define SPI_BUF15 0xFFFFFFFF #define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) #define SPI_BUF15_V 0xFFFFFFFF #define SPI_BUF15_S 0 -#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xE0) +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x0E0) /* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra -ns will start. 0: This is not seg-trans mode..*/ -#define SPI_USR_CONF (BIT(28)) +/*description: 1: Enable the DMA CONF phase of current seg-trans operation + which means seg-trans will start. 0: This is not seg-trans mode.*/ +#define SPI_USR_CONF (BIT(28)) #define SPI_USR_CONF_M (BIT(28)) #define SPI_USR_CONF_V 0x1 #define SPI_USR_CONF_S 28 /* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c -onfigured in CONF state..*/ -#define SPI_SOFT_RESET (BIT(27)) +/*description: Software reset enable reset the spi clock line cs line and data + lines. Can be configured in CONF state.*/ +#define SPI_SOFT_RESET (BIT(27)) #define SPI_SOFT_RESET_M (BIT(27)) #define SPI_SOFT_RESET_V 0x1 #define SPI_SOFT_RESET_S 27 /* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set SPI work mode. 1: slave mode 0: master mode..*/ -#define SPI_SLAVE_MODE (BIT(26)) +/*description: Set SPI work mode. 1: slave mode 0: master mode.*/ +#define SPI_SLAVE_MODE (BIT(26)) #define SPI_SLAVE_MODE_M (BIT(26)) #define SPI_SLAVE_MODE_V 0x1 #define SPI_SLAVE_MODE_S 26 /* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */ -/*description: The magic value of BM table in master DMA seg-trans..*/ -#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F +/*description: The magic value of BM table in master DMA seg-trans.*/ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F #define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S)) #define SPI_DMA_SEG_MAGIC_VALUE_V 0xF #define SPI_DMA_SEG_MAGIC_VALUE_S 22 /* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng -th in CPU controlled mode(Wr_BUF). 0: others.*/ -#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in CPU controlled mode(Wr_BUF). 0: others*/ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) #define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11)) #define SPI_SLV_WRBUF_BITLEN_EN_V 0x1 #define SPI_SLV_WRBUF_BITLEN_EN_S 11 /* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i -n CPU controlled mode(Rd_BUF). 0: others.*/ -#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in CPU controlled mode(Rd_BUF). 0: others*/ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) #define SPI_SLV_RDBUF_BITLEN_EN_M (BIT(10)) #define SPI_SLV_RDBUF_BITLEN_EN_V 0x1 #define SPI_SLV_RDBUF_BITLEN_EN_S 10 /* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng -th in DMA controlled mode(Wr_DMA). 0: others.*/ -#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in DMA controlled mode(Wr_DMA). 0: others*/ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) #define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9)) #define SPI_SLV_WRDMA_BITLEN_EN_V 0x1 #define SPI_SLV_WRDMA_BITLEN_EN_S 9 /* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i -n DMA controlled mode(Rd_DMA). 0: others.*/ -#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in DMA controlled mode(Rd_DMA). 0: others*/ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) #define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8)) #define SPI_SLV_RDDMA_BITLEN_EN_V 0x1 #define SPI_SLV_RDDMA_BITLEN_EN_S 8 /* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose -dge 0: output data at tsck posedge .*/ -#define SPI_RSCK_DATA_OUT (BIT(3)) +/*description: It saves half a cycle when tsck is the same as rsck. 1: output + data at rsck posedge 0: output data at tsck posedge*/ +#define SPI_RSCK_DATA_OUT (BIT(3)) #define SPI_RSCK_DATA_OUT_M (BIT(3)) #define SPI_RSCK_DATA_OUT_V 0x1 #define SPI_RSCK_DATA_OUT_S 3 /* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. - 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/ -#define SPI_CLK_MODE_13 (BIT(2)) +/*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output + data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ +#define SPI_CLK_MODE_13 (BIT(2)) #define SPI_CLK_MODE_13_M (BIT(2)) #define SPI_CLK_MODE_13_V 0x1 #define SPI_CLK_MODE_13_S 2 /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye -d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/ -#define SPI_CLK_MODE 0x00000003 +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ +#define SPI_CLK_MODE 0x00000003 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) #define SPI_CLK_MODE_V 0x3 #define SPI_CLK_MODE_S 0 -#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xE4) +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x0E4) /* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */ -/*description: In the slave mode it is the value of address..*/ -#define SPI_SLV_LAST_ADDR 0x0000003F +/*description: In the slave mode it is the value of address.*/ +#define SPI_SLV_LAST_ADDR 0x0000003F #define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S)) #define SPI_SLV_LAST_ADDR_V 0x3F #define SPI_SLV_LAST_ADDR_S 26 /* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of command..*/ -#define SPI_SLV_LAST_COMMAND 0x000000FF +/*description: In the slave mode it is the value of command.*/ +#define SPI_SLV_LAST_COMMAND 0x000000FF #define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) #define SPI_SLV_LAST_COMMAND_V 0xFF #define SPI_SLV_LAST_COMMAND_S 18 /* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */ -/*description: The transferred data bit length in SPI slave FD and HD mode. .*/ -#define SPI_SLV_DATA_BITLEN 0x0003FFFF +/*description: The transferred data bit length in SPI slave FD and HD mode.*/ +#define SPI_SLV_DATA_BITLEN 0x0003FFFF #define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S)) #define SPI_SLV_DATA_BITLEN_V 0x3FFFF #define SPI_SLV_DATA_BITLEN_S 0 -#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xE8) +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0x0E8) /* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80 -M. 0: XTAL CLK..*/ -#define SPI_MST_CLK_SEL (BIT(2)) +/*description: This bit is used to select SPI module clock source in master + mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ +#define SPI_MST_CLK_SEL (BIT(2)) #define SPI_MST_CLK_SEL_M (BIT(2)) #define SPI_MST_CLK_SEL_V 0x1 #define SPI_MST_CLK_SEL_S 2 /* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to power on the SPI module clock..*/ -#define SPI_MST_CLK_ACTIVE (BIT(1)) +/*description: Set this bit to power on the SPI module clock.*/ +#define SPI_MST_CLK_ACTIVE (BIT(1)) #define SPI_MST_CLK_ACTIVE_M (BIT(1)) #define SPI_MST_CLK_ACTIVE_V 0x1 #define SPI_MST_CLK_ACTIVE_S 1 /* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable clk gate.*/ -#define SPI_CLK_EN (BIT(0)) +/*description: Set this bit to enable clk gate*/ +#define SPI_CLK_EN (BIT(0)) #define SPI_CLK_EN_M (BIT(0)) #define SPI_CLK_EN_V 0x1 #define SPI_CLK_EN_S 0 -#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xF0) -/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007220 ; */ -/*description: SPI register version..*/ -#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x0F0) +/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101040 ; */ +/*description: SPI register version.*/ +#define SPI_DATE 0x0FFFFFFF #define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) #define SPI_DATE_V 0xFFFFFFF #define SPI_DATE_S 0 diff --git a/components/soc/esp32h2/include/soc/spi_struct.h b/components/soc/esp32h2/include/soc/spi_struct.h index cc22595dd0..867510549d 100644 --- a/components/soc/esp32h2/include/soc/spi_struct.h +++ b/components/soc/esp32h2/include/soc/spi_struct.h @@ -18,6 +18,7 @@ #ifdef __cplusplus extern "C" { #endif +#include "soc.h" typedef volatile struct { union { @@ -30,30 +31,30 @@ typedef volatile struct { }; uint32_t val; } cmd; - uint32_t addr; + uint32_t addr; /*Address value register*/ union { struct { - uint32_t reserved0 : 3; /*reserved*/ - uint32_t dummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved7 : 1; /*reserved*/ - uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved10 : 4; /*reserved*/ - uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t reserved17 : 1; /*reserved*/ - uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22 : 3; /*reserved*/ - uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ - uint32_t reserved27 : 5; /*reserved*/ + uint32_t reserved0: 3; /*reserved*/ + uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ + uint32_t reserved4: 1; /*reserved*/ + uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved7: 1; /*reserved*/ + uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved10: 4; /*reserved*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved16: 1; /*reserved*/ + uint32_t reserved17: 1; /*reserved*/ + uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/ + uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/ + uint32_t hold_pol: 1; /*SPI_HOLD output value when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ + uint32_t wp_pol: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ + uint32_t reserved22: 1; /*reserved*/ + uint32_t rd_bit_order: 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ + uint32_t wr_bit_order: 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ + uint32_t reserved27: 5; /*reserved*/ }; uint32_t val; } ctrl; @@ -178,17 +179,19 @@ typedef volatile struct { } dout_mode; union { struct { - uint32_t reserved0 : 18; /*reserved*/ - uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ - uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ - uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ - uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ - uint32_t reserved22 : 5; /*reserved*/ - uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ - uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ - uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/ - uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ - uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/ + uint32_t outfifo_empty: 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/ + uint32_t infifo_full: 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/ + uint32_t reserved2: 16; /*reserved*/ + uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ + uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ + uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ + uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ + uint32_t reserved22: 5; /*reserved*/ + uint32_t dma_rx_ena: 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ + uint32_t dma_tx_ena: 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ + uint32_t rx_afifo_rst: 1; /*Set this bit to reset RX AFIFO which is used to receive data in SPI master and slave mode transfer.*/ + uint32_t buf_afifo_rst: 1; /*Set this bit to reset BUF TX AFIFO which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ + uint32_t dma_afifo_rst: 1; /*Set this bit to reset DMA TX AFIFO which is used to send data out in SPI slave DMA controlled mode transfer.*/ }; uint32_t val; } dma_conf; @@ -300,7 +303,33 @@ typedef volatile struct { }; uint32_t val; } dma_int_st; - uint32_t reserved_44; + union { + struct { + uint32_t infifo_full_err_int_set: 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err_int_set: 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi_int_set: 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi_int_set: 1; /*The software set bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7_int_set: 1; /*The software set bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8_int_set: 1; /*The software set bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9_int_set: 1; /*The software set bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda_int_set: 1; /*The software set bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done_int_set: 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done_int_set: 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done_int_set: 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done_int_set: 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done_int_set: 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done_int_set: 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err_int_set: 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err_int_set: 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err_int_set: 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ + uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ + uint32_t app2_int_set: 1; /*The software set bit for SPI_APP2_INT interrupt.*/ + uint32_t app1_int_set: 1; /*The software set bit for SPI_APP1_INT interrupt.*/ + uint32_t reserved21: 11; /*reserved*/ + }; + uint32_t val; + } dma_int_set; uint32_t reserved_48; uint32_t reserved_4c; uint32_t reserved_50; diff --git a/components/soc/esp32h2/include/soc/syscon_reg.h b/components/soc/esp32h2/include/soc/syscon_reg.h index cc5a3c68cb..eb36eb4078 100644 --- a/components/soc/esp32h2/include/soc/syscon_reg.h +++ b/components/soc/esp32h2/include/soc/syscon_reg.h @@ -19,120 +19,6 @@ extern "C" { #endif #include "soc.h" -#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) -/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_RST_TICK_CNT (BIT(12)) -#define SYSCON_RST_TICK_CNT_M (BIT(12)) -#define SYSCON_RST_TICK_CNT_V 0x1 -#define SYSCON_RST_TICK_CNT_S 12 -/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_CLK_EN (BIT(11)) -#define SYSCON_CLK_EN_M (BIT(11)) -#define SYSCON_CLK_EN_V 0x1 -#define SYSCON_CLK_EN_S 11 -/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_CLK_320M_EN (BIT(10)) -#define SYSCON_CLK_320M_EN_M (BIT(10)) -#define SYSCON_CLK_320M_EN_V 0x1 -#define SYSCON_CLK_320M_EN_S 10 -/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: */ -#define SYSCON_PRE_DIV_CNT 0x000003FF -#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) -#define SYSCON_PRE_DIV_CNT_V 0x3FF -#define SYSCON_PRE_DIV_CNT_S 0 - -#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) -/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: */ -#define SYSCON_TICK_ENABLE (BIT(16)) -#define SYSCON_TICK_ENABLE_M (BIT(16)) -#define SYSCON_TICK_ENABLE_V 0x1 -#define SYSCON_TICK_ENABLE_S 16 -/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ -/*description: */ -#define SYSCON_CK8M_TICK_NUM 0x000000FF -#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) -#define SYSCON_CK8M_TICK_NUM_V 0xFF -#define SYSCON_CK8M_TICK_NUM_S 8 -/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ -/*description: */ -#define SYSCON_XTAL_TICK_NUM 0x000000FF -#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) -#define SYSCON_XTAL_TICK_NUM_V 0xFF -#define SYSCON_XTAL_TICK_NUM_S 0 - -#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) -/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK_XTAL_OEN (BIT(10)) -#define SYSCON_CLK_XTAL_OEN_M (BIT(10)) -#define SYSCON_CLK_XTAL_OEN_V 0x1 -#define SYSCON_CLK_XTAL_OEN_S 10 -/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK40X_BB_OEN (BIT(9)) -#define SYSCON_CLK40X_BB_OEN_M (BIT(9)) -#define SYSCON_CLK40X_BB_OEN_V 0x1 -#define SYSCON_CLK40X_BB_OEN_S 9 -/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) -#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) -#define SYSCON_CLK_DAC_CPU_OEN_V 0x1 -#define SYSCON_CLK_DAC_CPU_OEN_S 8 -/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK_ADC_INF_OEN (BIT(7)) -#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) -#define SYSCON_CLK_ADC_INF_OEN_V 0x1 -#define SYSCON_CLK_ADC_INF_OEN_S 7 -/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK_320M_OEN (BIT(6)) -#define SYSCON_CLK_320M_OEN_M (BIT(6)) -#define SYSCON_CLK_320M_OEN_V 0x1 -#define SYSCON_CLK_320M_OEN_S 6 -/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK160_OEN (BIT(5)) -#define SYSCON_CLK160_OEN_M (BIT(5)) -#define SYSCON_CLK160_OEN_V 0x1 -#define SYSCON_CLK160_OEN_S 5 -/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK80_OEN (BIT(4)) -#define SYSCON_CLK80_OEN_M (BIT(4)) -#define SYSCON_CLK80_OEN_V 0x1 -#define SYSCON_CLK80_OEN_S 4 -/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK_BB_OEN (BIT(3)) -#define SYSCON_CLK_BB_OEN_M (BIT(3)) -#define SYSCON_CLK_BB_OEN_V 0x1 -#define SYSCON_CLK_BB_OEN_S 3 -/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK44_OEN (BIT(2)) -#define SYSCON_CLK44_OEN_M (BIT(2)) -#define SYSCON_CLK44_OEN_V 0x1 -#define SYSCON_CLK44_OEN_S 2 -/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK22_OEN (BIT(1)) -#define SYSCON_CLK22_OEN_M (BIT(1)) -#define SYSCON_CLK22_OEN_V 0x1 -#define SYSCON_CLK22_OEN_S 1 -/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_CLK20_OEN (BIT(0)) -#define SYSCON_CLK20_OEN_M (BIT(0)) -#define SYSCON_CLK20_OEN_V 0x1 -#define SYSCON_CLK20_OEN_S 0 - #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ @@ -149,74 +35,6 @@ extern "C" { #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF #define SYSCON_WIFI_BB_CFG_2_S 0 -#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) -/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ -/*description: */ -#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF -#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) -#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF -#define SYSCON_WIFI_CLK_EN_S 0 - -#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) -/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSCON_WIFI_RST 0xFFFFFFFF -#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) -#define SYSCON_WIFI_RST_V 0xFFFFFFFF -#define SYSCON_WIFI_RST_S 0 - -#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG -/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ -/*description: */ -#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF -#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S)) -#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF -#define SYSTEM_WIFI_CLK_EN_S 0 - -/* Mask for all Wifi clock bits, 6 */ -#define SYSTEM_WIFI_CLK_WIFI_EN 0x0 -#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) -#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 -#define SYSTEM_WIFI_CLK_WIFI_EN_S 0 -/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */ -#define SYSTEM_WIFI_CLK_BT_EN 0x0 -#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) -#define SYSTEM_WIFI_CLK_BT_EN_V 0x0 -#define SYSTEM_WIFI_CLK_BT_EN_S 0 -/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ -#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F - -/* Digital team to check */ -//bluetooth baseband bit11 -#define SYSTEM_BT_BASEBAND_EN BIT(11) -//bluetooth LC bit16 and bit17 -#define SYSTEM_BT_LC_EN (BIT(16)|BIT(17)) - -/* Remaining single bit clock masks */ -#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4) -#define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5) -#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) -#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) -#define SYSTEM_WIFI_CLK_RNG_EN BIT(15) - -#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG -#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG -/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSTEM_BB_RST BIT(0) -#define SYSTEM_FE_RST BIT(1) -#define SYSTEM_MAC_RST BIT(2) -#define SYSTEM_BT_RST BIT(3) -#define SYSTEM_BTMAC_RST BIT(4) -#define SYSTEM_SDIO_RST BIT(5) -#define SYSTEM_EMAC_RST BIT(7) -#define SYSTEM_MACPWR_RST BIT(8) -#define SYSTEM_RW_BTMAC_RST BIT(9) -#define SYSTEM_RW_BTLP_RST BIT(10) -#define BLE_REG_REST_BIT BIT(11) -#define BLE_PWR_REG_REST_BIT BIT(12) -#define BLE_BB_REG_REST_BIT BIT(13) - #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ @@ -438,12 +256,6 @@ extern "C" { #define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) #define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 #define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 -/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ -/*description: */ -#define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF -#define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S)) -#define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF -#define SYSCON_RETENTION_LINK_ADDR_S 0 #define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4) /* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ @@ -532,30 +344,68 @@ extern "C" { #define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S)) #define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F #define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 -/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ +/* SYSCON_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003 +#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE (BIT(3)) +#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3)) +#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V 0x1 +#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S 3 +/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000007 #define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S)) -#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3 -#define SYSCON_PERI_BACKUP_FLOW_ERR_S 1 +#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x7 +#define SYSCON_PERI_BACKUP_FLOW_ERR_S 0 #define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8) -/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/* SYSCON_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ /*description: */ -#define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF -#define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S)) -#define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF -#define SYSCON_BACKUP_APB_START_ADDR_S 0 +#define SYSCON_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_APB_START_ADDR_M ((SYSCON_PERI_BACKUP_APB_START_ADDR_V)<<(SYSCON_PERI_BACKUP_APB_START_ADDR_S)) +#define SYSCON_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_APB_START_ADDR_S 0 #define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC) -/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/* SYSCON_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ /*description: */ -#define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF -#define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S)) -#define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF -#define SYSCON_BACKUP_MEM_START_ADDR_S 0 +#define SYSCON_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MEM_START_ADDR_M ((SYSCON_PERI_BACKUP_MEM_START_ADDR_V)<<(SYSCON_PERI_BACKUP_MEM_START_ADDR_S)) +#define SYSCON_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MEM_START_ADDR_S 0 -#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0C0) +#define SYSCON_PERI_BACKUP_MAP0_REG (DR_REG_SYSCON_BASE + 0x0C0) +/* SYSCON_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_MAP0 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP0_M ((SYSCON_PERI_BACKUP_MAP0_V)<<(SYSCON_PERI_BACKUP_MAP0_S)) +#define SYSCON_PERI_BACKUP_MAP0_V 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP0_S 0 + +#define SYSCON_PERI_BACKUP_MAP1_REG (DR_REG_SYSCON_BASE + 0x0C4) +/* SYSCON_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_MAP1 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP1_M ((SYSCON_PERI_BACKUP_MAP1_V)<<(SYSCON_PERI_BACKUP_MAP1_S)) +#define SYSCON_PERI_BACKUP_MAP1_V 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP1_S 0 + +#define SYSCON_PERI_BACKUP_MAP2_REG (DR_REG_SYSCON_BASE + 0x0C8) +/* SYSCON_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_MAP2 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP2_M ((SYSCON_PERI_BACKUP_MAP2_V)<<(SYSCON_PERI_BACKUP_MAP2_S)) +#define SYSCON_PERI_BACKUP_MAP2_V 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP2_S 0 + +#define SYSCON_PERI_BACKUP_MAP3_REG (DR_REG_SYSCON_BASE + 0x0CC) +/* SYSCON_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define SYSCON_PERI_BACKUP_MAP3 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP3_M ((SYSCON_PERI_BACKUP_MAP3_V)<<(SYSCON_PERI_BACKUP_MAP3_S)) +#define SYSCON_PERI_BACKUP_MAP3_V 0xFFFFFFFF +#define SYSCON_PERI_BACKUP_MAP3_S 0 + +#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0D0) /* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) @@ -569,7 +419,7 @@ extern "C" { #define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 -#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0C4) +#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0D4) /* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) @@ -583,7 +433,7 @@ extern "C" { #define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1 #define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 -#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0C8) +#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0D8) /* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) @@ -597,7 +447,7 @@ extern "C" { #define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 -#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0D0) +#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0DC) /* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ /*description: */ #define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) @@ -611,8 +461,16 @@ extern "C" { #define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 +#define SYSCON_CLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0E0) +/* SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_EN (BIT(0)) +#define SYSCON_CLK_EN_M (BIT(0)) +#define SYSCON_CLK_EN_V 0x1 +#define SYSCON_CLK_EN_S 0 + #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) -/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */ +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */ /*description: Version control*/ #define SYSCON_DATE 0xFFFFFFFF #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) diff --git a/components/soc/esp32h2/include/soc/syscon_struct.h b/components/soc/esp32h2/include/soc/syscon_struct.h index 2a9485aa87..e25e44179f 100644 --- a/components/soc/esp32h2/include/soc/syscon_struct.h +++ b/components/soc/esp32h2/include/soc/syscon_struct.h @@ -18,46 +18,13 @@ extern "C" { #endif typedef volatile struct { - union { - struct { - uint32_t apb_ctrl_pre_div_cnt: 10; - uint32_t apb_ctrl_clk_320m_en: 1; - uint32_t clk_en: 1; - uint32_t apb_ctrl_rst_tick_cnt: 1; - uint32_t reserved13: 19; - }; - uint32_t val; - } apb_ctrl_sysclk_conf; - union { - struct { - uint32_t apb_ctrl_xtal_tick_num: 8; - uint32_t apb_ctrl_ck8m_tick_num: 8; - uint32_t apb_ctrl_tick_enable: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } apb_ctrl_tick_conf; - union { - struct { - uint32_t clk20_oen: 1; - uint32_t clk22_oen: 1; - uint32_t clk44_oen: 1; - uint32_t clk_bb_oen: 1; - uint32_t clk80_oen: 1; - uint32_t clk160_oen: 1; - uint32_t clk_320m_oen: 1; - uint32_t clk_adc_inf_oen: 1; - uint32_t clk_dac_cpu_oen: 1; - uint32_t clk40x_bb_oen: 1; - uint32_t clk_xtal_oen: 1; - uint32_t reserved11: 21; - }; - uint32_t val; - } apb_ctrl_clk_out_en; + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; uint32_t wifi_bb_cfg; /**/ uint32_t wifi_bb_cfg_2; /**/ - uint32_t wifi_clk_en; /**/ - uint32_t wifi_rst_en; /**/ + uint32_t reserved_14; + uint32_t reserved_18; union { struct { uint32_t peri_io_swap: 8; @@ -223,20 +190,23 @@ typedef volatile struct { uint32_t rnd_data; /**/ union { struct { - uint32_t reserved0: 1; - uint32_t peri_backup_flow_err: 2; - uint32_t reserved3: 1; - uint32_t peri_backup_burst_limit: 5; - uint32_t peri_backup_tout_thres: 10; - uint32_t peri_backup_size: 10; - uint32_t peri_backup_start: 1; - uint32_t peri_backup_to_mem: 1; - uint32_t peri_backup_ena: 1; + uint32_t peri_backup_flow_err: 3; + uint32_t peri_backup_addr_map_mode: 1; + uint32_t peri_backup_burst_limit: 5; + uint32_t peri_backup_tout_thres: 10; + uint32_t peri_backup_size: 10; + uint32_t peri_backup_start: 1; + uint32_t peri_backup_to_mem: 1; + uint32_t peri_backup_ena: 1; }; uint32_t val; } peri_backup_config; - uint32_t peri_backup_apb_addr; /**/ - uint32_t peri_backup_mem_addr; /**/ + uint32_t peri_backup_apb_addr; /**/ + uint32_t peri_backup_mem_addr; /**/ + uint32_t peri_backup_map0; /**/ + uint32_t peri_backup_map1; /**/ + uint32_t peri_backup_map2; /**/ + uint32_t peri_backup_map3; /**/ union { struct { uint32_t peri_backup_done: 1; @@ -261,7 +231,6 @@ typedef volatile struct { }; uint32_t val; } peri_backup_int_ena; - uint32_t reserved_cc; union { struct { uint32_t peri_backup_done: 1; @@ -270,10 +239,13 @@ typedef volatile struct { }; uint32_t val; } peri_backup_int_clr; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } apb_ctrlclk_conf; uint32_t reserved_e4; uint32_t reserved_e8; uint32_t reserved_ec; @@ -472,7 +444,7 @@ typedef volatile struct { uint32_t reserved_3f0; uint32_t reserved_3f4; uint32_t reserved_3f8; - uint32_t apb_ctrl_date; /*Version control*/ + uint32_t apb_ctrl_date; /*Version control*/ } syscon_dev_t; extern syscon_dev_t SYSCON; #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/soc/system_reg.h b/components/soc/esp32h2/include/soc/system_reg.h index 3a67cb4606..56239ad0d4 100644 --- a/components/soc/esp32h2/include/soc/system_reg.h +++ b/components/soc/esp32h2/include/soc/system_reg.h @@ -19,6 +19,7 @@ extern "C" { #endif #include "soc.h" +#include "clkrst_reg.h" #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) /* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ /*description: */ @@ -60,18 +61,6 @@ extern "C" { #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 -/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_PLL_FREQ_SEL (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_V 0x1 -#define SYSTEM_PLL_FREQ_SEL_S 2 -/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SYSTEM_CPUPERIOD_SEL 0x00000003 -#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) -#define SYSTEM_CPUPERIOD_SEL_V 0x3 -#define SYSTEM_CPUPERIOD_SEL_S 0 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C) /* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ @@ -81,571 +70,7 @@ extern "C" { #define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 #define SYSTEM_LSLP_MEM_PD_MASK_S 0 -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010) -/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ -/*description: */ -#define SYSTEM_SPI4_CLK_EN (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_V 0x1 -#define SYSTEM_SPI4_CLK_EN_S 31 -/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 -#define SYSTEM_ADC2_ARB_CLK_EN_S 30 -/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 -#define SYSTEM_SYSTIMER_CLK_EN_S 29 -/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 -#define SYSTEM_APB_SARADC_CLK_EN_S 28 -/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 -#define SYSTEM_SPI3_DMA_CLK_EN_S 27 -/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM3_CLK_EN (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_V 0x1 -#define SYSTEM_PWM3_CLK_EN_S 26 -/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM2_CLK_EN (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_V 0x1 -#define SYSTEM_PWM2_CLK_EN_S 25 -/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_V 0x1 -#define SYSTEM_UART_MEM_CLK_EN_S 24 -/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) -#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) -#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 -#define SYSTEM_USB_DEVICE_CLK_EN_S 23 -/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 -#define SYSTEM_SPI2_DMA_CLK_EN_S 22 -/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S1_CLK_EN (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_V 0x1 -#define SYSTEM_I2S1_CLK_EN_S 21 -/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM1_CLK_EN (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_V 0x1 -#define SYSTEM_PWM1_CLK_EN_S 20 -/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TWAI_CLK_EN (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_V 0x1 -#define SYSTEM_TWAI_CLK_EN_S 19 -/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT1_CLK_EN_S 18 -/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM0_CLK_EN (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_V 0x1 -#define SYSTEM_PWM0_CLK_EN_S 17 -/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI3_CLK_EN (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_V 0x1 -#define SYSTEM_SPI3_CLK_EN_S 16 -/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 -/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_EFUSE_CLK_EN (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_V 0x1 -#define SYSTEM_EFUSE_CLK_EN_S 14 -/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP_CLK_EN_S 13 -/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI1_CLK_EN (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_V 0x1 -#define SYSTEM_UHCI1_CLK_EN_S 12 -/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LEDC_CLK_EN (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_V 0x1 -#define SYSTEM_LEDC_CLK_EN_S 11 -/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PCNT_CLK_EN (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_V 0x1 -#define SYSTEM_PCNT_CLK_EN_S 10 -/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RMT_CLK_EN (BIT(9)) -#define SYSTEM_RMT_CLK_EN_M (BIT(9)) -#define SYSTEM_RMT_CLK_EN_V 0x1 -#define SYSTEM_RMT_CLK_EN_S 9 -/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI0_CLK_EN (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_V 0x1 -#define SYSTEM_UHCI0_CLK_EN_S 8 -/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT0_CLK_EN_S 7 -/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI2_CLK_EN (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_V 0x1 -#define SYSTEM_SPI2_CLK_EN_S 6 -/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART1_CLK_EN (BIT(5)) -#define SYSTEM_UART1_CLK_EN_M (BIT(5)) -#define SYSTEM_UART1_CLK_EN_V 0x1 -#define SYSTEM_UART1_CLK_EN_S 5 -/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S0_CLK_EN (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_V 0x1 -#define SYSTEM_I2S0_CLK_EN_S 4 -/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_WDG_CLK_EN (BIT(3)) -#define SYSTEM_WDG_CLK_EN_M (BIT(3)) -#define SYSTEM_WDG_CLK_EN_V 0x1 -#define SYSTEM_WDG_CLK_EN_S 3 -/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART_CLK_EN (BIT(2)) -#define SYSTEM_UART_CLK_EN_M (BIT(2)) -#define SYSTEM_UART_CLK_EN_V 0x1 -#define SYSTEM_UART_CLK_EN_S 2 -/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI01_CLK_EN (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_V 0x1 -#define SYSTEM_SPI01_CLK_EN_S 1 -/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERS_CLK_EN (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_V 0x1 -#define SYSTEM_TIMERS_CLK_EN_S 0 - -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014) -/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TSENS_CLK_EN (BIT(10)) -#define SYSTEM_TSENS_CLK_EN_M (BIT(10)) -#define SYSTEM_TSENS_CLK_EN_V 0x1 -#define SYSTEM_TSENS_CLK_EN_S 10 -/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART2_CLK_EN (BIT(9)) -#define SYSTEM_UART2_CLK_EN_M (BIT(9)) -#define SYSTEM_UART2_CLK_EN_V 0x1 -#define SYSTEM_UART2_CLK_EN_S 9 -/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) -#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) -#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 -#define SYSTEM_LCD_CAM_CLK_EN_S 8 -/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) -#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) -#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 -#define SYSTEM_SDIO_HOST_CLK_EN_S 7 -/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DMA_CLK_EN (BIT(6)) -#define SYSTEM_DMA_CLK_EN_M (BIT(6)) -#define SYSTEM_DMA_CLK_EN_V 0x1 -#define SYSTEM_DMA_CLK_EN_S 6 -/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 -/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 -/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 -/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 -/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 - -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018) -/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SYSTEM_SPI4_RST (BIT(31)) -#define SYSTEM_SPI4_RST_M (BIT(31)) -#define SYSTEM_SPI4_RST_V 0x1 -#define SYSTEM_SPI4_RST_S 31 -/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ADC2_ARB_RST (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_V 0x1 -#define SYSTEM_ADC2_ARB_RST_S 30 -/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SYSTIMER_RST (BIT(29)) -#define SYSTEM_SYSTIMER_RST_M (BIT(29)) -#define SYSTEM_SYSTIMER_RST_V 0x1 -#define SYSTEM_SYSTIMER_RST_S 29 -/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_APB_SARADC_RST (BIT(28)) -#define SYSTEM_APB_SARADC_RST_M (BIT(28)) -#define SYSTEM_APB_SARADC_RST_V 0x1 -#define SYSTEM_APB_SARADC_RST_S 28 -/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI3_DMA_RST (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_V 0x1 -#define SYSTEM_SPI3_DMA_RST_S 27 -/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM3_RST (BIT(26)) -#define SYSTEM_PWM3_RST_M (BIT(26)) -#define SYSTEM_PWM3_RST_V 0x1 -#define SYSTEM_PWM3_RST_S 26 -/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM2_RST (BIT(25)) -#define SYSTEM_PWM2_RST_M (BIT(25)) -#define SYSTEM_PWM2_RST_V 0x1 -#define SYSTEM_PWM2_RST_S 25 -/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART_MEM_RST (BIT(24)) -#define SYSTEM_UART_MEM_RST_M (BIT(24)) -#define SYSTEM_UART_MEM_RST_V 0x1 -#define SYSTEM_UART_MEM_RST_S 24 -/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_USB_DEVICE_RST (BIT(23)) -#define SYSTEM_USB_DEVICE_RST_M (BIT(23)) -#define SYSTEM_USB_DEVICE_RST_V 0x1 -#define SYSTEM_USB_DEVICE_RST_S 23 -/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI2_DMA_RST (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_V 0x1 -#define SYSTEM_SPI2_DMA_RST_S 22 -/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S1_RST (BIT(21)) -#define SYSTEM_I2S1_RST_M (BIT(21)) -#define SYSTEM_I2S1_RST_V 0x1 -#define SYSTEM_I2S1_RST_S 21 -/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM1_RST (BIT(20)) -#define SYSTEM_PWM1_RST_M (BIT(20)) -#define SYSTEM_PWM1_RST_V 0x1 -#define SYSTEM_PWM1_RST_S 20 -/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TWAI_RST (BIT(19)) -#define SYSTEM_TWAI_RST_M (BIT(19)) -#define SYSTEM_TWAI_RST_V 0x1 -#define SYSTEM_TWAI_RST_S 19 -/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT1_RST (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_V 0x1 -#define SYSTEM_I2C_EXT1_RST_S 18 -/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM0_RST (BIT(17)) -#define SYSTEM_PWM0_RST_M (BIT(17)) -#define SYSTEM_PWM0_RST_V 0x1 -#define SYSTEM_PWM0_RST_S 17 -/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI3_RST (BIT(16)) -#define SYSTEM_SPI3_RST_M (BIT(16)) -#define SYSTEM_SPI3_RST_V 0x1 -#define SYSTEM_SPI3_RST_S 16 -/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP1_RST (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_V 0x1 -#define SYSTEM_TIMERGROUP1_RST_S 15 -/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_EFUSE_RST (BIT(14)) -#define SYSTEM_EFUSE_RST_M (BIT(14)) -#define SYSTEM_EFUSE_RST_V 0x1 -#define SYSTEM_EFUSE_RST_S 14 -/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP_RST (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_V 0x1 -#define SYSTEM_TIMERGROUP_RST_S 13 -/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI1_RST (BIT(12)) -#define SYSTEM_UHCI1_RST_M (BIT(12)) -#define SYSTEM_UHCI1_RST_V 0x1 -#define SYSTEM_UHCI1_RST_S 12 -/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LEDC_RST (BIT(11)) -#define SYSTEM_LEDC_RST_M (BIT(11)) -#define SYSTEM_LEDC_RST_V 0x1 -#define SYSTEM_LEDC_RST_S 11 -/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PCNT_RST (BIT(10)) -#define SYSTEM_PCNT_RST_M (BIT(10)) -#define SYSTEM_PCNT_RST_V 0x1 -#define SYSTEM_PCNT_RST_S 10 -/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RMT_RST (BIT(9)) -#define SYSTEM_RMT_RST_M (BIT(9)) -#define SYSTEM_RMT_RST_V 0x1 -#define SYSTEM_RMT_RST_S 9 -/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI0_RST (BIT(8)) -#define SYSTEM_UHCI0_RST_M (BIT(8)) -#define SYSTEM_UHCI0_RST_V 0x1 -#define SYSTEM_UHCI0_RST_S 8 -/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT0_RST (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_V 0x1 -#define SYSTEM_I2C_EXT0_RST_S 7 -/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI2_RST (BIT(6)) -#define SYSTEM_SPI2_RST_M (BIT(6)) -#define SYSTEM_SPI2_RST_V 0x1 -#define SYSTEM_SPI2_RST_S 6 -/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART1_RST (BIT(5)) -#define SYSTEM_UART1_RST_M (BIT(5)) -#define SYSTEM_UART1_RST_V 0x1 -#define SYSTEM_UART1_RST_S 5 -/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S0_RST (BIT(4)) -#define SYSTEM_I2S0_RST_M (BIT(4)) -#define SYSTEM_I2S0_RST_V 0x1 -#define SYSTEM_I2S0_RST_S 4 -/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_WDG_RST (BIT(3)) -#define SYSTEM_WDG_RST_M (BIT(3)) -#define SYSTEM_WDG_RST_V 0x1 -#define SYSTEM_WDG_RST_S 3 -/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART_RST (BIT(2)) -#define SYSTEM_UART_RST_M (BIT(2)) -#define SYSTEM_UART_RST_V 0x1 -#define SYSTEM_UART_RST_S 2 -/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI01_RST (BIT(1)) -#define SYSTEM_SPI01_RST_M (BIT(1)) -#define SYSTEM_SPI01_RST_V 0x1 -#define SYSTEM_SPI01_RST_S 1 -/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERS_RST (BIT(0)) -#define SYSTEM_TIMERS_RST_M (BIT(0)) -#define SYSTEM_TIMERS_RST_V 0x1 -#define SYSTEM_TIMERS_RST_S 0 - -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01C) -/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TSENS_RST (BIT(10)) -#define SYSTEM_TSENS_RST_M (BIT(10)) -#define SYSTEM_TSENS_RST_V 0x1 -#define SYSTEM_TSENS_RST_S 10 -/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART2_RST (BIT(9)) -#define SYSTEM_UART2_RST_M (BIT(9)) -#define SYSTEM_UART2_RST_V 0x1 -#define SYSTEM_UART2_RST_S 9 -/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LCD_CAM_RST (BIT(8)) -#define SYSTEM_LCD_CAM_RST_M (BIT(8)) -#define SYSTEM_LCD_CAM_RST_V 0x1 -#define SYSTEM_LCD_CAM_RST_S 8 -/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SDIO_HOST_RST (BIT(7)) -#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) -#define SYSTEM_SDIO_HOST_RST_V 0x1 -#define SYSTEM_SDIO_HOST_RST_S 7 -/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_DMA_RST (BIT(6)) -#define SYSTEM_DMA_RST_M (BIT(6)) -#define SYSTEM_DMA_RST_V 0x1 -#define SYSTEM_DMA_RST_S 6 -/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 -#define SYSTEM_CRYPTO_HMAC_RST_S 5 -/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_DS_RST (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_V 0x1 -#define SYSTEM_CRYPTO_DS_RST_S 4 -/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_V 0x1 -#define SYSTEM_CRYPTO_RSA_RST_S 3 -/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_V 0x1 -#define SYSTEM_CRYPTO_SHA_RST_S 2 -/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_AES_RST (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_V 0x1 -#define SYSTEM_CRYPTO_AES_RST_S 1 - -#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020) -/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ -/*description: */ -#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) -#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_NUM_S 0 - -#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024) -/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_RTC_EN (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_V 0x1 -#define SYSTEM_LPCLK_RTC_EN_S 28 -/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 -#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 -/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 -#define SYSTEM_LPCLK_SEL_XTAL_S 26 -/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_8M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_V 0x1 -#define SYSTEM_LPCLK_SEL_8M_S 25 -/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 -#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 -/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ -/*description: */ -#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) -#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_A_S 12 -/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ -/*description: */ -#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF -#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) -#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF -#define SYSTEM_BT_LPCK_DIV_B_S 0 - -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x028) +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x010) /* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) @@ -653,7 +78,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x02C) +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x014) /* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) @@ -661,7 +86,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x030) +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x018) /* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) @@ -669,7 +94,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x034) +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x01C) /* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) @@ -677,7 +102,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038) +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x020) /* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) @@ -697,7 +122,7 @@ extern "C" { #define SYSTEM_RSA_MEM_PD_V 0x1 #define SYSTEM_RSA_MEM_PD_S 0 -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x03C) +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x024) /* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_EDMA_RESET (BIT(1)) @@ -711,7 +136,7 @@ extern "C" { #define SYSTEM_EDMA_CLK_ON_V 0x1 #define SYSTEM_EDMA_CLK_ON_S 0 -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x040) +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x028) /* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_DCACHE_RESET (BIT(3)) @@ -737,7 +162,7 @@ extern "C" { #define SYSTEM_ICACHE_CLK_ON_V 0x1 #define SYSTEM_ICACHE_CLK_ON_S 0 -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x044) +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x02C) /* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) @@ -763,7 +188,7 @@ extern "C" { #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x048) +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x030) /* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) @@ -789,7 +214,7 @@ extern "C" { #define SYSTEM_RTC_MEM_CRC_START_V 0x1 #define SYSTEM_RTC_MEM_CRC_START_S 8 -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x04C) +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x034) /* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF @@ -797,7 +222,7 @@ extern "C" { #define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF #define SYSTEM_RTC_MEM_CRC_RES_S 0 -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x050) +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038) /* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) @@ -811,7 +236,7 @@ extern "C" { #define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 #define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x054) +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x03C) /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define SYSTEM_CLK_EN (BIT(0)) @@ -819,33 +244,7 @@ extern "C" { #define SYSTEM_CLK_EN_V 0x1 #define SYSTEM_CLK_EN_S 0 -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x058) -/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: */ -#define SYSTEM_CLK_DIV_EN (BIT(19)) -#define SYSTEM_CLK_DIV_EN_M (BIT(19)) -#define SYSTEM_CLK_DIV_EN_V 0x1 -#define SYSTEM_CLK_DIV_EN_S 19 -/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ -/*description: */ -#define SYSTEM_CLK_XTAL_FREQ 0x0000007F -#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) -#define SYSTEM_CLK_XTAL_FREQ_V 0x7F -#define SYSTEM_CLK_XTAL_FREQ_S 12 -/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ -/*description: */ -#define SYSTEM_SOC_CLK_SEL 0x00000003 -#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) -#define SYSTEM_SOC_CLK_SEL_V 0x3 -#define SYSTEM_SOC_CLK_SEL_S 10 -/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ -/*description: */ -#define SYSTEM_PRE_DIV_CNT 0x000003FF -#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) -#define SYSTEM_PRE_DIV_CNT_V 0x3FF -#define SYSTEM_PRE_DIV_CNT_S 0 - -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x05C) +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x040) /* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ /*description: */ #define SYSTEM_MEM_VT_SEL 0x00000003 @@ -877,164 +276,8 @@ extern "C" { #define SYSTEM_MEM_PATH_LEN_V 0xF #define SYSTEM_MEM_PATH_LEN_S 0 -#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x060) -/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 -/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 -/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ -/*description: */ -#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F -#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) -#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F -#define SYSTEM_COMB_PATH_LEN_LVT_S 0 - -#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x064) -/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 -/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 -/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ -/*description: */ -#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F -#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) -#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F -#define SYSTEM_COMB_PATH_LEN_NVT_S 0 - -#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x068) -/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 -/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 -/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ -/*description: */ -#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F -#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) -#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F -#define SYSTEM_COMB_PATH_LEN_HVT_S 0 - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x06C) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x070) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x074) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x078) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x07C) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x080) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x084) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x088) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x08C) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x090) -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x094) -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x098) -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 - #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */ +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103240 ; */ /*description: */ #define SYSTEM_DATE 0x0FFFFFFF #define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) diff --git a/components/soc/esp32h2/include/soc/system_struct.h b/components/soc/esp32h2/include/soc/system_struct.h index f07fab0aff..58c1c6b99f 100644 --- a/components/soc/esp32h2/include/soc/system_struct.h +++ b/components/soc/esp32h2/include/soc/system_struct.h @@ -56,134 +56,6 @@ typedef volatile struct { }; uint32_t val; } mem_pd_mask; - union { - struct { - uint32_t reg_timers_clk_en : 1; /*reg_timers_clk_en*/ - uint32_t reg_spi01_clk_en : 1; /*reg_spi01_clk_en*/ - uint32_t reg_uart_clk_en : 1; /*reg_uart_clk_en*/ - uint32_t reg_wdg_clk_en : 1; /*reg_wdg_clk_en*/ - uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/ - uint32_t reg_uart1_clk_en : 1; /*reg_uart1_clk_en*/ - uint32_t reg_spi2_clk_en : 1; /*reg_spi2_clk_en*/ - uint32_t reg_i2c_ext0_clk_en : 1; /*reg_i2c_ext0_clk_en*/ - uint32_t reg_uhci0_clk_en : 1; /*reg_uhci0_clk_en*/ - uint32_t reg_rmt_clk_en : 1; /*reg_rmt_clk_en*/ - uint32_t reg_pcnt_clk_en : 1; /*reg_pcnt_clk_en*/ - uint32_t reg_ledc_clk_en : 1; /*reg_ledc_clk_en*/ - uint32_t reg_uhci1_clk_en : 1; /*reg_uhci1_clk_en*/ - uint32_t reg_timergroup_clk_en : 1; /*reg_timergroup_clk_en*/ - uint32_t reg_efuse_clk_en : 1; /*reg_efuse_clk_en*/ - uint32_t reg_timergroup1_clk_en : 1; /*reg_timergroup1_clk_en*/ - uint32_t reg_spi3_clk_en : 1; /*reg_spi3_clk_en*/ - uint32_t reg_pwm0_clk_en : 1; /*reg_pwm0_clk_en*/ - uint32_t reg_i2c_ext1_clk_en : 1; /*reg_i2c_ext1_clk_en*/ - uint32_t reg_can_clk_en : 1; /*reg_can_clk_en*/ - uint32_t reg_pwm1_clk_en : 1; /*reg_pwm1_clk_en*/ - uint32_t reg_i2s1_clk_en : 1; /*reg_i2s1_clk_en*/ - uint32_t reg_spi2_dma_clk_en : 1; /*reg_spi2_dma_clk_en*/ - uint32_t reg_usb_device_clk_en : 1; /*reg_usb_device_clk_en*/ - uint32_t reg_uart_mem_clk_en : 1; /*reg_uart_mem_clk_en*/ - uint32_t reg_pwm2_clk_en : 1; /*reg_pwm2_clk_en*/ - uint32_t reg_pwm3_clk_en : 1; /*reg_pwm3_clk_en*/ - uint32_t reg_spi3_dma_clk_en : 1; /*reg_spi3_dma_clk_en*/ - uint32_t reg_apb_saradc_clk_en : 1; /*reg_apb_saradc_clk_en*/ - uint32_t reg_systimer_clk_en : 1; /*reg_systimer_clk_en*/ - uint32_t reg_adc2_arb_clk_en : 1; /*reg_adc2_arb_clk_en*/ - uint32_t reg_spi4_clk_en : 1; /*reg_spi4_clk_en*/ - }; - uint32_t val; - } perip_clk_en0; - union { - struct { - uint32_t reserved0 : 1; /*peripheral reset register*/ - uint32_t reg_crypto_aes_clk_en : 1; /*reg_crypto_aes_clk_en*/ - uint32_t reg_crypto_sha_clk_en : 1; /*reg_crypto_sha_clk_en*/ - uint32_t reg_crypto_rsa_clk_en : 1; /*reg_crypto_rsa_clk_en*/ - uint32_t reg_crypto_ds_clk_en : 1; /*reg_crypto_ds_clk_en*/ - uint32_t reg_crypto_hmac_clk_en : 1; /*reg_crypto_hmac_clk_en*/ - uint32_t reg_dma_clk_en : 1; /*reg_dma_clk_en*/ - uint32_t reg_sdio_host_clk_en : 1; /*reg_sdio_host_clk_en*/ - uint32_t reg_lcd_cam_clk_en : 1; /*reg_lcd_cam_clk_en*/ - uint32_t reg_uart2_clk_en : 1; /*reg_uart2_clk_en*/ - uint32_t reg_tsens_clk_en : 1; /*reg_tsens_clk_en*/ - uint32_t reserved11 : 21; /*reserved*/ - }; - uint32_t val; - } perip_clk_en1; - union { - struct { - uint32_t reg_timers_rst : 1; /*reg_timers_rst*/ - uint32_t reg_spi01_rst : 1; /*reg_spi01_rst*/ - uint32_t reg_uart_rst : 1; /*reg_uart_rst*/ - uint32_t reg_wdg_rst : 1; /*reg_wdg_rst*/ - uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/ - uint32_t reg_uart1_rst : 1; /*reg_uart1_rst*/ - uint32_t reg_spi2_rst : 1; /*reg_spi2_rst*/ - uint32_t reg_i2c_ext0_rst : 1; /*reg_i2c_ext0_rst*/ - uint32_t reg_uhci0_rst : 1; /*reg_uhci0_rst*/ - uint32_t reg_rmt_rst : 1; /*reg_rmt_rst*/ - uint32_t reg_pcnt_rst : 1; /*reg_pcnt_rst*/ - uint32_t reg_ledc_rst : 1; /*reg_ledc_rst*/ - uint32_t reg_uhci1_rst : 1; /*reg_uhci1_rst*/ - uint32_t reg_timergroup_rst : 1; /*reg_timergroup_rst*/ - uint32_t reg_efuse_rst : 1; /*reg_efuse_rst*/ - uint32_t reg_timergroup1_rst : 1; /*reg_timergroup1_rst*/ - uint32_t reg_spi3_rst : 1; /*reg_spi3_rst*/ - uint32_t reg_pwm0_rst : 1; /*reg_pwm0_rst*/ - uint32_t reg_i2c_ext1_rst : 1; /*reg_i2c_ext1_rst*/ - uint32_t reg_can_rst : 1; /*reg_can_rst*/ - uint32_t reg_pwm1_rst : 1; /*reg_pwm1_rst*/ - uint32_t reg_i2s1_rst : 1; /*reg_i2s1_rst*/ - uint32_t reg_spi2_dma_rst : 1; /*reg_spi2_dma_rst*/ - uint32_t reg_usb_device_rst : 1; /*reg_usb_device_rst*/ - uint32_t reg_uart_mem_rst : 1; /*reg_uart_mem_rst*/ - uint32_t reg_pwm2_rst : 1; /*reg_pwm2_rst*/ - uint32_t reg_pwm3_rst : 1; /*reg_pwm3_rst*/ - uint32_t reg_spi3_dma_rst : 1; /*reg_spi3_dma_rst*/ - uint32_t reg_apb_saradc_rst : 1; /*reg_apb_saradc_rst*/ - uint32_t reg_systimer_rst : 1; /*reg_systimer_rst*/ - uint32_t reg_adc2_arb_rst : 1; /*reg_adc2_arb_rst*/ - uint32_t reg_spi4_rst : 1; /*reg_spi4_rst*/ - }; - uint32_t val; - } perip_rst_en0; - union { - struct { - uint32_t reserved0 : 1; /*reserved*/ - uint32_t reg_crypto_aes_rst : 1; /*reg_crypto_aes_rst*/ - uint32_t reg_crypto_sha_rst : 1; /*reg_crypto_sha_rst*/ - uint32_t reg_crypto_rsa_rst : 1; /*reg_crypto_rsa_rst*/ - uint32_t reg_crypto_ds_rst : 1; /*reg_crypto_ds_rst*/ - uint32_t reg_crypto_hmac_rst : 1; /*reg_crypto_hmac_rst*/ - uint32_t reg_dma_rst : 1; /*reg_dma_rst*/ - uint32_t reg_sdio_host_rst : 1; /*reg_sdio_host_rst*/ - uint32_t reg_lcd_cam_rst : 1; /*reg_lcd_cam_rst*/ - uint32_t reg_uart2_rst : 1; /*reg_uart2_rst*/ - uint32_t reg_tsens_rst : 1; /*reg_tsens_rst*/ - uint32_t reserved11 : 21; /*reserved*/ - }; - uint32_t val; - } perip_rst_en1; - union { - struct { - uint32_t reg_bt_lpck_div_num : 12; /*reg_bt_lpck_div_num*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } bt_lpck_div_int; - union { - struct { - uint32_t reg_bt_lpck_div_b : 12; /*reg_bt_lpck_div_b*/ - uint32_t reg_bt_lpck_div_a : 12; /*reg_bt_lpck_div_a*/ - uint32_t reg_lpclk_sel_rtc_slow : 1; /*reg_lpclk_sel_rtc_slow*/ - uint32_t reg_lpclk_sel_8m : 1; /*reg_lpclk_sel_8m*/ - uint32_t reg_lpclk_sel_xtal : 1; /*reg_lpclk_sel_xtal*/ - uint32_t reg_lpclk_sel_xtal32k : 1; /*reg_lpclk_sel_xtal32k*/ - uint32_t reg_lpclk_rtc_en : 1; /*reg_lpclk_rtc_en*/ - uint32_t reserved29 : 3; /*reserved*/ - }; - uint32_t val; - } bt_lpck_div_frac; union { struct { uint32_t reg_cpu_intr_from_cpu_0 : 1; /*reg_cpu_intr_from_cpu_0*/ @@ -275,16 +147,6 @@ typedef volatile struct { }; uint32_t val; } clock_gate; - union { - struct { - uint32_t reg_pre_div_cnt : 10; /*reg_pre_div_cnt*/ - uint32_t reg_soc_clk_sel : 2; /*reg_soc_clk_sel*/ - uint32_t reg_clk_xtal_freq : 7; /*reg_clk_xtal_freq*/ - uint32_t reg_clk_div_en : 1; /*reg_clk_div_en*/ - uint32_t reserved20 : 12; /*reserved*/ - }; - uint32_t val; - } sysclk_conf; union { struct { uint32_t reg_mem_path_len : 4; /*reg_mem_path_len*/ @@ -296,120 +158,28 @@ typedef volatile struct { }; uint32_t val; } mem_pvt; - union { - struct { - uint32_t reg_comb_path_len_lvt : 5; /*reg_comb_path_len_lvt*/ - uint32_t reg_comb_err_cnt_clr_lvt : 1; /*reg_comb_err_cnt_clr_lvt*/ - uint32_t reg_comb_pvt_monitor_en_lvt : 1; /*reg_comb_pvt_monitor_en_lvt*/ - uint32_t reserved7 : 18; /*reserved*/ - uint32_t reserved25 : 7; /*reserved*/ - }; - uint32_t val; - } comb_pvt_lvt_conf; - union { - struct { - uint32_t reg_comb_path_len_nvt : 5; /*reg_comb_path_len_nvt*/ - uint32_t reg_comb_err_cnt_clr_nvt : 1; /*reg_comb_err_cnt_clr_nvt*/ - uint32_t reg_comb_pvt_monitor_en_nvt : 1; /*reg_comb_pvt_monitor_en_nvt*/ - uint32_t reserved7 : 18; /*reserved*/ - uint32_t reserved25 : 7; /*reserved*/ - }; - uint32_t val; - } comb_pvt_nvt_conf; - union { - struct { - uint32_t reg_comb_path_len_hvt : 5; /*reg_comb_path_len_hvt*/ - uint32_t reg_comb_err_cnt_clr_hvt : 1; /*reg_comb_err_cnt_clr_hvt*/ - uint32_t reg_comb_pvt_monitor_en_hvt : 1; /*reg_comb_pvt_monitor_en_hvt*/ - uint32_t reserved7 : 18; /*reserved*/ - uint32_t reserved25 : 7; /*reserved*/ - }; - uint32_t val; - } comb_pvt_hvt_conf; - union { - struct { - uint32_t reg_comb_timing_err_cnt_lvt_site0: 16; /*reg_comb_timing_err_cnt_lvt_site0*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site0; - union { - struct { - uint32_t reg_comb_timing_err_cnt_nvt_site0: 16; /*reg_comb_timing_err_cnt_nvt_site0*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site0; - union { - struct { - uint32_t reg_comb_timing_err_cnt_hvt_site0: 16; /*reg_comb_timing_err_cnt_hvt_site0*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site0; - union { - struct { - uint32_t reg_comb_timing_err_cnt_lvt_site1: 16; /*reg_comb_timing_err_cnt_lvt_site1*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site1; - union { - struct { - uint32_t reg_comb_timing_err_cnt_nvt_site1: 16; /*reg_comb_timing_err_cnt_nvt_site1*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site1; - union { - struct { - uint32_t reg_comb_timing_err_cnt_hvt_site1: 16; /*reg_comb_timing_err_cnt_hvt_site1*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site1; - union { - struct { - uint32_t reg_comb_timing_err_cnt_lvt_site2: 16; /*reg_comb_timing_err_cnt_lvt_site2*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site2; - union { - struct { - uint32_t reg_comb_timing_err_cnt_nvt_site2: 16; /*reg_comb_timing_err_cnt_nvt_site2*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site2; - union { - struct { - uint32_t reg_comb_timing_err_cnt_hvt_site2: 16; /*reg_comb_timing_err_cnt_hvt_site2*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site2; - union { - struct { - uint32_t reg_comb_timing_err_cnt_lvt_site3: 16; /*reg_comb_timing_err_cnt_lvt_site3*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_lvt_site3; - union { - struct { - uint32_t reg_comb_timing_err_cnt_nvt_site3: 16; /*reg_comb_timing_err_cnt_nvt_site3*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_nvt_site3; - union { - struct { - uint32_t reg_comb_timing_err_cnt_hvt_site3: 16; /*reg_comb_timing_err_cnt_hvt_site3*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } comb_pvt_err_hvt_site3; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; uint32_t reserved_9c; uint32_t reserved_a0; uint32_t reserved_a4; diff --git a/components/soc/esp32h2/include/soc/systimer_reg.h b/components/soc/esp32h2/include/soc/systimer_reg.h index 4e9f64fffa..cb6ebe6a43 100644 --- a/components/soc/esp32h2/include/soc/systimer_reg.h +++ b/components/soc/esp32h2/include/soc/systimer_reg.h @@ -1,567 +1,424 @@ -/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#pragma once +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SYS_TIMER_REG_H_ +#define _SOC_SYS_TIMER_REG_H_ + -#include -#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif +#include "soc.h" +#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000) +/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: register file clk gating*/ +#define SYS_TIMER_CLK_EN (BIT(31)) +#define SYS_TIMER_CLK_EN_M (BIT(31)) +#define SYS_TIMER_CLK_EN_V 0x1 +#define SYS_TIMER_CLK_EN_S 31 +/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: timer unit0 work enable*/ +#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 +/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: timer unit1 work enable*/ +#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 +/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: If timer unit0 is stalled when core0 stalled*/ +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: If timer unit0 is stalled when core1 stalled*/ +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ +/*description: If timer unit1 is stalled when core0 stalled*/ +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: If timer unit1 is stalled when core1 stalled*/ +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: target0 work enable*/ +#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET0_WORK_EN_S 24 +/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: target1 work enable*/ +#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET1_WORK_EN_S 23 +/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: target2 work enable*/ +#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET2_WORK_EN_S 22 +/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: systimer clock force on*/ +#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 +#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 -/** SYSTIMER_CONF_REG register - * SYSTIMER_CONF. - */ -#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) -/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; - * systimer clock force on - */ -#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) -#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 -#define SYSTIMER_SYSTIMER_CLK_FO_S 0 -/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; - * target2 work enable - */ -#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) -#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) -#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 -#define SYSTIMER_TARGET2_WORK_EN_S 22 -/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; - * target1 work enable - */ -#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) -#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) -#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 -#define SYSTIMER_TARGET1_WORK_EN_S 23 -/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; - * target0 work enable - */ -#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) -#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) -#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 -#define SYSTIMER_TARGET0_WORK_EN_S 24 -/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; - * If timer unit1 is stalled when core1 stalled - */ -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 -/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; - * If timer unit1 is stalled when core0 stalled - */ -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 -/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; - * If timer unit0 is stalled when core1 stalled - */ -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 -/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; - * If timer unit0 is stalled when core0 stalled - */ -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 -/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; - * timer unit1 work enable - */ -#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) -#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 -/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; - * timer unit0 work enable - */ -#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) -#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 -/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; - * register file clk gating - */ -#define SYSTIMER_CLK_EN (BIT(31)) -#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) -#define SYSTIMER_CLK_EN_V 0x00000001 -#define SYSTIMER_CLK_EN_S 31 +#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004) +/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: update timer_unit0*/ +#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 +/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 -/** SYSTIMER_UNIT0_OP_REG register - * SYSTIMER_UNIT0_OP. - */ -#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) -/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; - * reg_timer_unit0_value_valid - */ -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 -/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; - * update timer_unit0 - */ -#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) -#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 +#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008) +/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ +/*description: update timer unit1*/ +#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 +/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ +/*description: timer value is sync and valid*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 -/** SYSTIMER_UNIT1_OP_REG register - * SYSTIMER_UNIT1_OP. - */ -#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) -/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; - * timer value is sync and valid - */ -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 -/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; - * update timer unit1 - */ -#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) -#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C) +/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer unit0 load high 32 bit*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 -/** SYSTIMER_UNIT0_LOAD_HI_REG register - * SYSTIMER_UNIT0_LOAD_HI. - */ -#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) -/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; - * timer unit0 load high 32 bit - */ -#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) -#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010) +/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer unit0 load low 32 bit*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 -/** SYSTIMER_UNIT0_LOAD_LO_REG register - * SYSTIMER_UNIT0_LOAD_LO. - */ -#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) -/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * timer unit0 load low 32 bit - */ -#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) -#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014) +/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer unit1 load high 32 bit*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 -/** SYSTIMER_UNIT1_LOAD_HI_REG register - * SYSTIMER_UNIT1_LOAD_HI. - */ -#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) -/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; - * timer unit1 load high 32 bit - */ -#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) -#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018) +/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer unit1 load low 32 bit*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 -/** SYSTIMER_UNIT1_LOAD_LO_REG register - * SYSTIMER_UNIT1_LOAD_LO. - */ -#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) -/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * timer unit1 load low 32 bit - */ -#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) -#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 +#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C) +/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer taget0 high 32 bit*/ +#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) +#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET0_HI_S 0 -/** SYSTIMER_TARGET0_HI_REG register - * SYSTIMER_TARGET0_HI. - */ -#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) -/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; - * timer taget0 high 32 bit - */ -#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF -#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) -#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_TARGET0_HI_S 0 +#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020) +/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer taget0 low 32 bit*/ +#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) +#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET0_LO_S 0 -/** SYSTIMER_TARGET0_LO_REG register - * SYSTIMER_TARGET0_LO. - */ -#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) -/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; - * timer taget0 low 32 bit - */ -#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) -#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_TARGET0_LO_S 0 +#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024) +/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer taget1 high 32 bit*/ +#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) +#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET1_HI_S 0 -/** SYSTIMER_TARGET1_HI_REG register - * SYSTIMER_TARGET1_HI. - */ -#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) -/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; - * timer taget1 high 32 bit - */ -#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF -#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) -#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_TARGET1_HI_S 0 +#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028) +/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer taget1 low 32 bit*/ +#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) +#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET1_LO_S 0 -/** SYSTIMER_TARGET1_LO_REG register - * SYSTIMER_TARGET1_LO. - */ -#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) -/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; - * timer taget1 low 32 bit - */ -#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) -#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_TARGET1_LO_S 0 +#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C) +/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer taget2 high 32 bit*/ +#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) +#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET2_HI_S 0 -/** SYSTIMER_TARGET2_HI_REG register - * SYSTIMER_TARGET2_HI. - */ -#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) -/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; - * timer taget2 high 32 bit - */ -#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF -#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) -#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_TARGET2_HI_S 0 +#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030) +/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer taget2 low 32 bit*/ +#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) +#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET2_LO_S 0 -/** SYSTIMER_TARGET2_LO_REG register - * SYSTIMER_TARGET2_LO. - */ -#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) -/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; - * timer taget2 low 32 bit - */ -#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) -#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_TARGET2_LO_S 0 +#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034) +/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: select which unit to compare*/ +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 +/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set target0 to period mode*/ +#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 +/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: target0 period*/ +#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) +#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET0_PERIOD_S 0 -/** SYSTIMER_TARGET0_CONF_REG register - * SYSTIMER_TARGET0_CONF. - */ -#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) -/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; - * target0 period - */ -#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) -#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF -#define SYSTIMER_TARGET0_PERIOD_S 0 -/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; - * Set target0 to period mode - */ -#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) -#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 -#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 -/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 +#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038) +/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: select which unit to compare*/ +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 +/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set target1 to period mode*/ +#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 +/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: target1 period*/ +#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) +#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET1_PERIOD_S 0 -/** SYSTIMER_TARGET1_CONF_REG register - * SYSTIMER_TARGET1_CONF. - */ -#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) -/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; - * target1 period - */ -#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) -#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF -#define SYSTIMER_TARGET1_PERIOD_S 0 -/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; - * Set target1 to period mode - */ -#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) -#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 -#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 -/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 +#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C) +/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: select which unit to compare*/ +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 +/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set target2 to period mode*/ +#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 +/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: target2 period*/ +#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) +#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET2_PERIOD_S 0 -/** SYSTIMER_TARGET2_CONF_REG register - * SYSTIMER_TARGET2_CONF. - */ -#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) -/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; - * target2 period - */ -#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) -#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF -#define SYSTIMER_TARGET2_PERIOD_S 0 -/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; - * Set target2 to period mode - */ -#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) -#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 -#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 -/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040) +/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer read value high 32bit*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 -/** SYSTIMER_UNIT0_VALUE_HI_REG register - * SYSTIMER_UNIT0_VALUE_HI. - */ -#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) -/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; - * timer read value high 32bit - */ -#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) -#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044) +/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer read value low 32bit*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 -/** SYSTIMER_UNIT0_VALUE_LO_REG register - * SYSTIMER_UNIT0_VALUE_LO. - */ -#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) -/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; - * timer read value low 32bit - */ -#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) -#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048) +/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer read value high 32bit*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 -/** SYSTIMER_UNIT1_VALUE_HI_REG register - * SYSTIMER_UNIT1_VALUE_HI. - */ -#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) -/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; - * timer read value high 32bit - */ -#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) -#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF -#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C) +/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer read value low 32bit*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 -/** SYSTIMER_UNIT1_VALUE_LO_REG register - * SYSTIMER_UNIT1_VALUE_LO. - */ -#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) -/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; - * timer read value low 32bit - */ -#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) -#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 +#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050) +/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp0 load value*/ +#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 -/** SYSTIMER_COMP0_LOAD_REG register - * SYSTIMER_COMP0_LOAD. - */ -#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) -/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; - * timer comp0 load value - */ -#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) -#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_COMP0_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054) +/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp1 load value*/ +#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 -/** SYSTIMER_COMP1_LOAD_REG register - * SYSTIMER_COMP1_LOAD. - */ -#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) -/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; - * timer comp1 load value - */ -#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) -#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_COMP1_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058) +/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp2 load value*/ +#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 -/** SYSTIMER_COMP2_LOAD_REG register - * SYSTIMER_COMP2_LOAD. - */ -#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) -/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; - * timer comp2 load value - */ -#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) -#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_COMP2_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C) +/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer unit0 load value*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 -/** SYSTIMER_UNIT0_LOAD_REG register - * SYSTIMER_UNIT0_LOAD. - */ -#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) -/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; - * timer unit0 load value - */ -#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) -#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060) +/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer unit1 load value*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 -/** SYSTIMER_UNIT1_LOAD_REG register - * SYSTIMER_UNIT1_LOAD. - */ -#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) -/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; - * timer unit1 load value - */ -#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) -#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 +#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064) +/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 enable*/ +#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET2_INT_ENA_S 2 +/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 enable*/ +#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET1_INT_ENA_S 1 +/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 enable*/ +#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 +#define SYS_TIMER_TARGET0_INT_ENA_S 0 -/** SYSTIMER_INT_ENA_REG register - * SYSTIMER_INT_ENA. - */ -#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) -/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; - * interupt0 enable - */ -#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) -#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) -#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 -#define SYSTIMER_TARGET0_INT_ENA_S 0 -/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; - * interupt1 enable - */ -#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) -#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) -#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 -#define SYSTIMER_TARGET1_INT_ENA_S 1 -/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; - * interupt2 enable - */ -#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) -#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) -#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 -#define SYSTIMER_TARGET2_INT_ENA_S 2 +#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068) +/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 raw*/ +#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) +#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET2_INT_RAW_S 2 +/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 raw*/ +#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) +#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET1_INT_RAW_S 1 +/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 raw*/ +#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) +#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 +#define SYS_TIMER_TARGET0_INT_RAW_S 0 -/** SYSTIMER_INT_RAW_REG register - * SYSTIMER_INT_RAW. - */ -#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) -/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * interupt0 raw - */ -#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) -#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) -#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 -#define SYSTIMER_TARGET0_INT_RAW_S 0 -/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * interupt1 raw - */ -#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) -#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) -#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 -#define SYSTIMER_TARGET1_INT_RAW_S 1 -/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * interupt2 raw - */ -#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) -#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) -#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 -#define SYSTIMER_TARGET2_INT_RAW_S 2 +#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c) +/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 clear*/ +#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) +#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET2_INT_CLR_S 2 +/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 clear*/ +#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) +#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET1_INT_CLR_S 1 +/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 clear*/ +#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) +#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 +#define SYS_TIMER_TARGET0_INT_CLR_S 0 -/** SYSTIMER_INT_CLR_REG register - * SYSTIMER_INT_CLR. - */ -#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) -/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; - * interupt0 clear - */ -#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) -#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) -#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 -#define SYSTIMER_TARGET0_INT_CLR_S 0 -/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; - * interupt1 clear - */ -#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) -#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) -#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 -#define SYSTIMER_TARGET1_INT_CLR_S 1 -/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; - * interupt2 clear - */ -#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) -#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) -#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 -#define SYSTIMER_TARGET2_INT_CLR_S 2 +#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070) +/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) +#define SYS_TIMER_TARGET2_INT_ST_V 0x1 +#define SYS_TIMER_TARGET2_INT_ST_S 2 +/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) +#define SYS_TIMER_TARGET1_INT_ST_V 0x1 +#define SYS_TIMER_TARGET1_INT_ST_S 1 +/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) +#define SYS_TIMER_TARGET0_INT_ST_V 0x1 +#define SYS_TIMER_TARGET0_INT_ST_S 0 -/** SYSTIMER_INT_ST_REG register - * SYSTIMER_INT_ST. - */ -#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) -/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; - * reg_target0_int_st - */ -#define SYSTIMER_TARGET0_INT_ST (BIT(0)) -#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) -#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 -#define SYSTIMER_TARGET0_INT_ST_S 0 -/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; - * reg_target1_int_st - */ -#define SYSTIMER_TARGET1_INT_ST (BIT(1)) -#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) -#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 -#define SYSTIMER_TARGET1_INT_ST_S 1 -/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; - * reg_target2_int_st - */ -#define SYSTIMER_TARGET2_INT_ST (BIT(2)) -#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) -#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 -#define SYSTIMER_TARGET2_INT_ST_S 2 - -/** SYSTIMER_DATE_REG register - * SYSTIMER_DATE. - */ -#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) -/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377; - * reg_date - */ -#define SYSTIMER_DATE 0xFFFFFFFF -#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) -#define SYSTIMER_DATE_V 0xFFFFFFFF -#define SYSTIMER_DATE_S 0 +#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc) +/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2006171 ; */ +/*description: */ +#define SYS_TIMER_DATE 0xFFFFFFFF +#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) +#define SYS_TIMER_DATE_V 0xFFFFFFFF +#define SYS_TIMER_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_SYS_TIMER_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/include/soc/timer_group_reg.h index 05ae6fb42e..ba8cba2bbe 100644 --- a/components/soc/esp32h2/include/soc/timer_group_reg.h +++ b/components/soc/esp32h2/include/soc/timer_group_reg.h @@ -37,6 +37,11 @@ extern "C" { #define TIMG_WDT_RESET_LENGTH_800_NS 5 #define TIMG_WDT_RESET_LENGTH_1600_NS 6 #define TIMG_WDT_RESET_LENGTH_3200_NS 7 +/* Possible values for TIMG_WDT_STGx */ +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) /* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ diff --git a/components/soc/esp32h2/include/soc/twai_struct.h b/components/soc/esp32h2/include/soc/twai_struct.h index 64cb80e5ed..a2c72e5afa 100644 --- a/components/soc/esp32h2/include/soc/twai_struct.h +++ b/components/soc/esp32h2/include/soc/twai_struct.h @@ -22,7 +22,7 @@ extern "C" { /* ---------------------------- Register Layout ------------------------------ */ -/* The TWAI peripheral's registers are 8bits, however the ESP32-C3 can only access +/* The TWAI peripheral's registers are 8bits, however the ESP32-H2 can only access * peripheral registers every 32bits. Therefore each TWAI register is mapped to * the least significant byte of every 32bits. */ diff --git a/components/soc/esp32h2/soc_memory_layout.c b/components/soc/esp32h2/soc_memory_layout.c index ba0ae819cb..d2f645e35f 100644 --- a/components/soc/esp32h2/soc_memory_layout.c +++ b/components/soc/esp32h2/soc_memory_layout.c @@ -91,7 +91,7 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_ #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP /* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW - region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. + region on H2, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. */ SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); #endif diff --git a/components/soc/include/soc/lldesc.h b/components/soc/include/soc/lldesc.h index ef74ce7aa4..966917da51 100644 --- a/components/soc/include/soc/lldesc.h +++ b/components/soc/include/soc/lldesc.h @@ -24,6 +24,8 @@ #include "esp32s3/rom/lldesc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/lldesc.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/lldesc.h" #endif //the size field has 12 bits, but 0 not for 4096. diff --git a/components/soc/memory_layout_utils.c b/components/soc/memory_layout_utils.c index 27e073b34c..3ef6d0e9e7 100644 --- a/components/soc/memory_layout_utils.c +++ b/components/soc/memory_layout_utils.c @@ -23,6 +23,9 @@ #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/rom_layout.h" #define ROM_HAS_LAYOUT_TABLE 1 +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/rom_layout.h" +#define ROM_HAS_LAYOUT_TABLE 1 #else #define ROM_HAS_LAYOUT_TABLE 0 #endif