From 21a4eda4d4554db1af780aa5c05accf3df89d666 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 1 Jul 2022 17:46:17 +0800 Subject: [PATCH] Use the entire sharedbuffer space as the heap of the D/IRAM attribute --- components/heap/port/esp32c2/memory_layout.c | 42 ++++++++------------ components/heap/port/esp32c3/memory_layout.c | 30 +++++++++----- components/heap/port/esp32h2/memory_layout.c | 30 +++++++++----- components/heap/port/esp32s3/memory_layout.c | 22 ++++++---- components/soc/esp32c2/include/soc/soc.h | 1 + components/soc/esp32c3/include/soc/soc.h | 3 +- components/soc/esp32h2/include/soc/soc.h | 1 + components/soc/esp32s3/include/soc/soc.h | 3 +- 8 files changed, 80 insertions(+), 52 deletions(-) diff --git a/components/heap/port/esp32c2/memory_layout.c b/components/heap/port/esp32c2/memory_layout.c index a563135c93..f4840e33ed 100644 --- a/components/heap/port/esp32c2/memory_layout.c +++ b/components/heap/port/esp32c2/memory_layout.c @@ -25,19 +25,18 @@ * - Most other malloc caps only fit in one region anyway. * */ -// IDF-4299 const soc_memory_type_desc_t soc_memory_types[] = { - // Type 0: DRAM - { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, - // Type 1: DRAM used for startup stacks - { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, - // Type 2: DRAM which has an alias on the I-port + // Type 0: DRAM used for startup stacks + { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + // Type 1: DRAM which has an alias on the I-port { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: IRAM - { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, }; -#define SOC_MEMORY_TYPE_DEFAULT 2 +/* Index of memory in `soc_memory_types[]` */ +#define SOC_MEMORY_TYPE_STACK_DRAM 0 +#define SOC_MEMORY_TYPE_DIRAM 1 + +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -49,26 +48,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * */ -#define RAM_BOTTOM_LEVEL_REUSE_SIZE 0x18000 -#define RAM_BOTTOM_LEVEL_RESERVE_SIZE 0x8000 -#define MIN_ADDR_OF_STARTUP_STACK_TOP 0x3FCD81D0 //TODO: IDF-4585 - -/*|------------------------------------ SRAM LEVEL 3 -------------------------------------|*/ -/*|0x3FCC0000 0x3FCDFFFF|*/ -/*|------------------------------------------------|--------------------------|-------------|*/ -/*| Shared Buffer | Startup Stack | Interface |*/ -/*|------------------------------------------------|--------------------------|-------------|*/ -/*| <---RAM_BOTTOM_LEVEL_REUSE_SIZE---> | <---------RAM_BOTTOM_LEVEL_RESERVE_SIZE---------> |*/ -/*|-----------------------------------------------------------------------------------------|*/ +/** + * Register the shared buffer area of the last memory block into the heap during heap initialization + */ +#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x6E0000) const soc_memory_region_t soc_memory_regions[] = { - { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 1, can be remapped to ROM, can be used as trace memory - { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //Block 2, can be remapped to ROM, can be used as trace memory - { 0x3FCC0000, RAM_BOTTOM_LEVEL_REUSE_SIZE, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 3, can be remapped to ROM, can be used as trace memory - { 0x3FCC0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE, RAM_BOTTOM_LEVEL_RESERVE_SIZE, 1, 0x403A0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE} //Block 4, can be used as trace memory + { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1 + { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //D/IRAM level2 + { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level3 + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area) }; -_Static_assert(0x3FCC0000 + RAM_BOTTOM_LEVEL_REUSE_SIZE <= MIN_ADDR_OF_STARTUP_STACK_TOP, "Heap reuse area overlaps startup stack"); const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); diff --git a/components/heap/port/esp32c3/memory_layout.c b/components/heap/port/esp32c3/memory_layout.c index 403a102836..f40c934db9 100644 --- a/components/heap/port/esp32c3/memory_layout.c +++ b/components/heap/port/esp32c3/memory_layout.c @@ -31,16 +31,20 @@ const soc_memory_type_desc_t soc_memory_types[] = { { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, // Type 2: DRAM which has an alias on the I-port { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: IRAM - { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, - // Type 4: RTCRAM + // Type 3: RTCRAM { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, }; +/* Index of memory in `soc_memory_types[]` */ +#define SOC_MEMORY_TYPE_DRAM 0 +#define SOC_MEMORY_TYPE_STACK_DRAM 1 +#define SOC_MEMORY_TYPE_DIRAM 2 +#define SOC_MEMORY_TYPE_RTCRAM 3 + #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE -#define SOC_MEMORY_TYPE_DEFAULT 0 +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM #else -#define SOC_MEMORY_TYPE_DEFAULT 2 +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM #endif const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -52,12 +56,20 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * this list should always be sorted from low to high by start address. * */ + +/** + * Register the shared buffer area of the last memory block into the heap during heap initialization + */ +#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000) + const soc_memory_region_t soc_memory_regions[] = { - { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory - { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory - { 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory + { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory + { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory + { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x2000, 4, 0}, //Fast RTC memory + { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif }; diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index 57fd94f840..6e9fbd0c0c 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -31,16 +31,20 @@ const soc_memory_type_desc_t soc_memory_types[] = { { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, // Type 2: DRAM which has an alias on the I-port { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: IRAM - { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, - // Type 4: RTCRAM + // Type 3: RTCRAM { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, }; +/* Index of memory in `soc_memory_types[]` */ +#define SOC_MEMORY_TYPE_DRAM 0 +#define SOC_MEMORY_TYPE_STACK_DRAM 1 +#define SOC_MEMORY_TYPE_DIRAM 2 +#define SOC_MEMORY_TYPE_RTCRAM 3 + #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE -#define SOC_MEMORY_TYPE_DEFAULT 0 +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM #else -#define SOC_MEMORY_TYPE_DEFAULT 2 +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM #endif const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -52,12 +56,20 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * this list should always be sorted from low to high by start address. * */ + +/** + * Register the shared buffer area of the last memory block into the heap during heap initialization + */ +#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x700000) + const soc_memory_region_t soc_memory_regions[] = { - { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Block 4, can be remapped to ROM, can be used as trace memory - { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Block 5, can be remapped to ROM, can be used as trace memory - { 0x3FCC0000, 0x20000, 1, 0x403C0000}, //Block 9, can be used as trace memory + { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory + { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory + { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x2000, 4, 0}, //Fast RTC memory + { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif }; diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 341df39330..fbbb941ac6 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -52,6 +52,13 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor * this list should always be sorted from low to high by start address. * */ + +/** + * Register the shared buffer area of the last memory block into the heap during heap initialization + */ +#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#define DRAM0_TO_IRAM0(dram_addr) (dram_addr + 0x6F0000) + const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available @@ -59,13 +66,14 @@ const soc_memory_region_t soc_memory_regions[] = { #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB { 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM #endif - { 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy - { 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy - { 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy - { 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy - { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy - { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy - { 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task + { 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy + { 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy + { 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy + { 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy + { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy + { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy + { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), 2, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy, + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, DRAM0_TO_IRAM0(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task #if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM #endif diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index 83afaa5fab..c0d7e84dab 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -202,6 +202,7 @@ // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3fcebf10 +#define SOC_ROM_STACK_SIZE 0x2000 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index a4131b79b8..a0733b0228 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -207,7 +207,8 @@ #define SOC_DEBUG_HIGH 0x28000000 // Start (highest address) of ROM boot stack, only relevant during early boot -#define SOC_ROM_STACK_START 0x3fcebf10 +#define SOC_ROM_STACK_START 0x3fcde710 +#define SOC_ROM_STACK_SIZE 0x2000 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index d83bca8e50..b452f371c1 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -208,6 +208,7 @@ // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3fcdf120 +#define SOC_ROM_STACK_SIZE 0x2000 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index ab0db41ae3..b1b256d4a8 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -218,7 +218,8 @@ #define SOC_MEM_INTERNAL_HIGH 0x403E2000 // Start (highest address) of ROM boot stack, only relevant during early boot -#define SOC_ROM_STACK_START 0x3fcebf10 +#define SOC_ROM_STACK_START 0x3fceb710 +#define SOC_ROM_STACK_SIZE 0x2000 //interrupt cpu using table, Please see the core-isa.h /*************************************************************************************************************