From 19d8a403e643078437b5bd8d7e6c8885b4f9fbf9 Mon Sep 17 00:00:00 2001 From: Renz Bagaporo Date: Mon, 11 Jan 2021 17:35:56 +0800 Subject: [PATCH] ulp: set riscv-ulp as done signal source properly Closes https://github.com/espressif/esp-idf/issues/6069 --- components/ulp/ulp_riscv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/components/ulp/ulp_riscv.c b/components/ulp/ulp_riscv.c index 31f3269c36..1cd3c0b3b7 100644 --- a/components/ulp/ulp_riscv.c +++ b/components/ulp/ulp_riscv.c @@ -44,8 +44,9 @@ esp_err_t ulp_riscv_run(void) esp_rom_delay_us(20); /* Select RISC-V as the ULP_TIMER trigger target. */ CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL); - /* Select ULP_TIMER sleep trigger source. 1: REG_COCPU_DONE; 0: ULP END.*/ - SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE); + + /* Select ULP-RISC-V to send the DONE signal. */ + SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE); /* start ULP_TIMER */ CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);