RISC-V: Fix vectors.S assembly file indentation and macro usage

The file is now more consistent as the macros have been fixed, more comments
have been added and the indentation is now using spaces only.

components/riscv/vectors.S

@@ -1,16 +1,9 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #include "soc/soc.h"
 #include "soc/interrupt_reg.h"
 #include "riscv/rvruntime-frames.h"
@@ -23,8 +16,12 @@
     .equ panic_from_exception, xt_unhandled_exception
     .equ panic_from_isr, panicHandler
 
-.macro save_regs
-	addi sp, sp, -CONTEXT_SIZE
+/* Macro which first allocates space on the stack to save general
+ * purpose registers, and then save them. GP register is excluded.
+ * The default size allocated on the stack is CONTEXT_SIZE, but it
+ * can be overridden. */
+.macro save_general_regs cxt_size=CONTEXT_SIZE
+    addi sp, sp, -\cxt_size
     sw   ra, RV_STK_RA(sp)
     sw   tp, RV_STK_TP(sp)
     sw   t0, RV_STK_T0(sp)
@@ -61,7 +58,10 @@
     sw   t0, RV_STK_MEPC(sp)
 .endm
 
-.macro restore_regs
+/* Restore the general purpose registers (excluding gp) from the context on
+ * the stack. The context is then deallocated. The default size is CONTEXT_SIZE
+ * but it can be overriden. */
+.macro restore_general_regs cxt_size=CONTEXT_SIZE
     lw   ra, RV_STK_RA(sp)
     lw   tp, RV_STK_TP(sp)
     lw   t0, RV_STK_T0(sp)
@@ -91,7 +91,7 @@
     lw   t4, RV_STK_T4(sp)
     lw   t5, RV_STK_T5(sp)
     lw   t6, RV_STK_T6(sp)
-	addi sp, sp, CONTEXT_SIZE
+    addi sp,sp, \cxt_size
 .endm
 
 .macro restore_mepc
@@ -131,7 +131,7 @@ _vector_table:
     .rept (ETS_MAX_INUM - ETS_MEMPROT_ERR_INUM)
     #else
     .rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
-	#endif
+    #endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
     j _interrupt_handler		/* 6 identical entries, all pointing to the interrupt handler */
     .endr
 
@@ -141,39 +141,16 @@ _vector_table:
     /* Exception handler.*/
     .type _panic_handler, @function
 _panic_handler:
-	addi sp, sp, -RV_STK_FRMSZ /* allocate space on stack to store necessary registers */
-	/* save general registers */
-	sw ra,  RV_STK_RA(sp)
+    /* Allocate space on the stack and store general purpose registers */
+    save_general_regs RV_STK_FRMSZ
+
+    /* As gp register is not saved by the macro, save it here */
     sw    gp, RV_STK_GP(sp)
-	sw tp,  RV_STK_TP(sp)
-	sw t0,  RV_STK_T0(sp)
-	sw t1,  RV_STK_T1(sp)
-	sw t2,  RV_STK_T2(sp)
-	sw s0,  RV_STK_S0(sp)
-	sw s1,  RV_STK_S1(sp)
-	sw a0,  RV_STK_A0(sp)
-	sw a1,  RV_STK_A1(sp)
-	sw a2,  RV_STK_A2(sp)
-	sw a3,  RV_STK_A3(sp)
-	sw a4,  RV_STK_A4(sp)
-	sw a5,  RV_STK_A5(sp)
-	sw a6,  RV_STK_A6(sp)
-	sw a7,  RV_STK_A7(sp)
-	sw s2,  RV_STK_S2(sp)
-	sw s3,  RV_STK_S3(sp)
-	sw s4,  RV_STK_S4(sp)
-	sw s5,  RV_STK_S5(sp)
-	sw s6,  RV_STK_S6(sp)
-	sw s7,  RV_STK_S7(sp)
-	sw s8,  RV_STK_S8(sp)
-	sw s9,  RV_STK_S9(sp)
-	sw s10, RV_STK_S10(sp)
-	sw s11, RV_STK_S11(sp)
-	sw t3,  RV_STK_T3(sp)
-	sw t4,  RV_STK_T4(sp)
-	sw t5,  RV_STK_T5(sp)
-	sw t6,  RV_STK_T6(sp)
+
+    /* Same goes for the SP value before trapping */
     addi  t0, sp, RV_STK_FRMSZ /* restore sp with the value when trap happened */
+
+    /* Save CSRs */
     sw    t0, RV_STK_SP(sp)
     csrr  t0, mepc
     sw    t0, RV_STK_MEPC(sp)
@@ -219,14 +196,16 @@ _call_panic_handler:
     .global _interrupt_handler
     .type _interrupt_handler, @function
 _interrupt_handler:
-	/* entry */
-	save_regs
+    /* Start by saving the general purpose registers and the PC value before
+     * the interrupt happened. */
+    save_general_regs
     save_mepc
 
     /* Before doing anythig preserve the stack pointer */
     /* It will be saved in current TCB, if needed */
     mv      a0, sp
     call    rtos_int_enter
+    /* If this is a non-nested interrupt, SP now points to the interrupt stack */
 
     /* Before dispatch c handler, restore interrupt to enable nested intr */
     csrr    s1, mcause
@@ -249,6 +228,7 @@ _interrupt_handler:
 
     li      t0, 0x8
     csrrs   t0, mstatus, t0
+    /* MIE set. Nested interrupts can now occur */
 
     #ifdef CONFIG_PM_TRACE
     li      a0, 0       /* = ESP_PM_TRACE_IDLE */
@@ -278,6 +258,7 @@ _interrupt_handler:
 
     li      t0, 0x8
     csrrc   t0, mstatus, t0
+    /* MIE cleared. Nested interrupts are disabled */
 
     /* restore the interrupt threshold level */
     la      t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
@@ -287,6 +268,7 @@ _interrupt_handler:
     /* Yield to the next task is needed: */
     mv      a0, sp
     call    rtos_int_exit
+    /* If this is a non-nested interrupt, context switch called, SP now points to back to task stack. */
 
     /* The next (or current) stack pointer is returned in a0 */
     mv      sp, a0
@@ -295,7 +277,7 @@ _interrupt_handler:
     csrw    mcause, s1
     csrw    mstatus, s2
     restore_mepc
-	restore_regs
+    restore_general_regs
 
     /* exit, this will also re-enable the interrupts */
     mret