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feat(esp_hw_support): do esp32p4 l1 cache invalidate by regdma

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This commit is contained in:
wuzhenghui
2024-12-11 21:26:54 +08:00
parent f3cc52d234
commit 228e74e06c
4 changed files with 10 additions and 26 deletions
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25
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S
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@ -149,31 +149,6 @@ _rv_core_critical_regs_restore: /* export a strong symbol to jump to here, used
nop nop
rv_core_critical_regs_restore: rv_core_critical_regs_restore:
/* Invalidate L1 Cache by Core 0*/
csrr t0, mhartid
bnez t0, start_restore
/* Core 0 is wakeup core, Invalidate L1 Cache here */
/* Invalidate L1 cache is required here!!! */
la t0, CACHE_SYNC_MAP_REG
li t1, CACHE_MAP_L1_CACHE_MASK /* map l1 i/dcache */
sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
la t2, CACHE_SYNC_ADDR_REG
sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */
la t0, CACHE_SYNC_SIZE_REG
sw zero, 0x0(t0) /* clear EXTMEM_CACHE_SYNC_SIZE_REG */
la t1, CACHE_SYNC_CTRL_REG
lw t2, 0x0(t1)
ori t2, t2, 0x1
sw t2, 0x0(t1)
li t0, 0x10 /* SYNC_DONE bit */
wait_cache_sync_done1:
lw t2, 0x0(t1)
and t2, t0, t2
beqz t2, wait_cache_sync_done1
start_restore:
la t0, rv_core_critical_regs_frame la t0, rv_core_critical_regs_frame
csrr t1, mhartid csrr t1, mhartid
slli t1, t1, 2 slli t1, t1, 2

1
components/esp_rom/esp32p4/include/esp32p4/rom/cache.h
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@ -231,6 +231,7 @@ typedef enum {
#define CACHE_MAP_L2_CACHE BIT(5) #define CACHE_MAP_L2_CACHE BIT(5)
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1) #define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
#define CACHE_MAP_L1_CACHE_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE)
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE) #define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
struct cache_internal_stub_table { struct cache_internal_stub_table {

2
components/soc/esp32p4/include/soc/system_periph_retention.h
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@ -32,7 +32,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO
* This is an internal function of the sleep retention driver, and is not * This is an internal function of the sleep retention driver, and is not
* useful for external use. * useful for external use.
*/ */
#define CACHE_RETENTION_LINK_LEN 2 #define CACHE_RETENTION_LINK_LEN 8
extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN]; extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN];
/** /**

8
components/soc/esp32p4/system_retention_periph.c
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@ -22,6 +22,7 @@
#include "soc/timer_group_reg.h" #include "soc/timer_group_reg.h"
#include "soc/timer_periph.h" #include "soc/timer_periph.h"
#include "soc/uart_reg.h" #include "soc/uart_reg.h"
#include "esp32p4/rom/cache.h"
/* Interrupt Matrix Registers Context */ /* Interrupt Matrix Registers Context */
#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1) #define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
@ -61,6 +62,13 @@ const regdma_entries_config_t cache_regs_retention[] = {
l2_cache_regs_map[2], l2_cache_regs_map[3]), \ l2_cache_regs_map[2], l2_cache_regs_map[3]), \
.owner = ENTRY(0) .owner = ENTRY(0)
}, },
// Invalidate L1 Cache
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x02), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x03), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) },
}; };
_Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions"); _Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");