From 8ab44b1df7cb9f46efc9125aaa40052b2180a153 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:12 +0800 Subject: [PATCH 1/8] change(ble): [AUTO_MR] Update lib_esp32h2 to 000475d3 (cherry picked from commit 141362fe48dda7dc605b3e0a6f78a3ad0dd13e21) Co-authored-by: zwl --- components/bt/controller/lib_esp32h2/esp32h2-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index 0a35e009b9..0783414092 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit 0a35e009b9a31993d998492a0c0d3a34a881514f +Subproject commit 07834140920ccf33cbca4b9c0655256efe389ed7 From 79b7fecb4bbeaa964995c7612e9d1c05660ccbf1 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:15 +0800 Subject: [PATCH 2/8] change(ble): [AUTO_MR] Update lib_esp32c6 to 000475d3 (cherry picked from commit 32a510900ce593be86498894ab7a3c7b623e62f7) Co-authored-by: zwl --- components/bt/controller/lib_esp32c6/esp32c6-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index 3c4701301c..9d2f7a02d1 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit 3c4701301cd4253b99e9b0e39f603852ded06b7b +Subproject commit 9d2f7a02d1073a2835cf71d9a9231759324f0338 From 683b2ebe75e88d7f54453448d3c35ac4db544482 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:17 +0800 Subject: [PATCH 3/8] change(ble): [AUTO_MR] Update lib_esp32c2 to e08d6058 (cherry picked from commit 0ec2a92d7930ee36e393d5aee990612565ae71ed) Co-authored-by: zwl --- components/bt/controller/lib_esp32c2/esp32c2-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index ff958fab2f..c5a5ba3f0a 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit ff958fab2f693e4b5974375cce525945fd238c4f +Subproject commit c5a5ba3f0ae2bb056384a140ad809ee5d4e78491 From 17f23d94238aefa9ad385178e728322cb8d01685 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:19 +0800 Subject: [PATCH 4/8] change(ble): [AUTO_MR] updated rom linker script for ESP32-C2 (cherry picked from commit 32c3556c7a950063e663fba4a8fd62af7a4cfc89) Co-authored-by: zwl --- .../esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld | 14 +++++++------- components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld index cb34663aa9..84a59d6b05 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld @@ -293,7 +293,7 @@ r_ble_ll_ctrl_rx_feature_req = 0x40000ee0; r_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4; r_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8; r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec; -r_ble_ll_ctrl_rx_pdu = 0x40000ef0; +//r_ble_ll_ctrl_rx_pdu = 0x40000ef0; r_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4; r_ble_ll_ctrl_rx_phy_req = 0x40000ef8; r_ble_ll_ctrl_rx_phy_rsp = 0x40000efc; @@ -726,15 +726,15 @@ r_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac; r_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0; r_ble_lll_dtm_init = 0x400015b4; r_ble_lll_dtm_reset = 0x400015b8; -r_ble_lll_dtm_rx_create_ctx = 0x400015bc; +//r_ble_lll_dtm_rx_create_ctx = 0x400015bc; r_ble_lll_dtm_rx_isr_end = 0x400015c0; r_ble_lll_dtm_rx_isr_start = 0x400015c4; -r_ble_lll_dtm_rx_pkt_in = 0x400015c8; +//r_ble_lll_dtm_rx_pkt_in = 0x400015c8; r_ble_lll_dtm_rx_sched_cb = 0x400015cc; r_ble_lll_dtm_rx_start = 0x400015d0; r_ble_lll_dtm_rx_test = 0x400015d4; r_ble_lll_dtm_set_next = 0x400015d8; -r_ble_lll_dtm_tx_create_ctx = 0x400015dc; +//r_ble_lll_dtm_tx_create_ctx = 0x400015dc; r_ble_lll_dtm_tx_done = 0x400015e0; r_ble_lll_dtm_tx_sched_cb = 0x400015e4; r_ble_lll_dtm_tx_test = 0x400015e8; @@ -761,7 +761,7 @@ r_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638; r_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c; r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640; r_ble_lll_reset = 0x40001644; -r_ble_lll_rfmgmt_controller_sleep_en = 0x40001648; +//r_ble_lll_rfmgmt_controller_sleep_en = 0x40001648; r_ble_lll_rfmgmt_deinit = 0x4000164c; //r_ble_lll_rfmgmt_disable = 0x40001650; //r_ble_lll_rfmgmt_enable = 0x40001654; @@ -770,7 +770,7 @@ r_ble_lll_rfmgmt_init = 0x4000165c; //r_ble_lll_rfmgmt_is_enabled = 0x40001660; r_ble_lll_rfmgmt_release = 0x40001664; r_ble_lll_rfmgmt_release_ev = 0x40001668; -r_ble_lll_rfmgmt_reset = 0x4000166c; +//r_ble_lll_rfmgmt_reset = 0x4000166c; r_ble_lll_rfmgmt_scan_changed = 0x40001670; r_ble_lll_rfmgmt_sched_changed = 0x40001674; r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678; @@ -1199,7 +1199,7 @@ r_ble_lll_rfmgmt_wake_up_ev = 0x40002fc4; r_ble_lll_sched_env_deinit = 0x40002fc8; r_ble_phy_env_deinit = 0x40002fcc; r_ble_hw_driver_env_deinit = 0x40002fd0; -r_ble_lll_dtm_env_init = 0x40002fd4; +//r_ble_lll_dtm_env_init = 0x40002fd4; r_ble_lll_dtm_env_deinit = 0x40002fd8; r_ble_lll_scan_callout_env_init = 0x40002fdc; r_ble_lll_scan_callout_env_deinit = 0x40002fe0; diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld index 1ba085564c..edde433afe 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld @@ -577,10 +577,10 @@ r_ble_lll_dtm_end_test = 0x400015a8; r_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac; r_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0; r_ble_lll_dtm_reset = 0x400015b8; -r_ble_lll_dtm_rx_create_ctx = 0x400015bc; +//r_ble_lll_dtm_rx_create_ctx = 0x400015bc; r_ble_lll_dtm_rx_isr_end = 0x400015c0; r_ble_lll_dtm_rx_isr_start = 0x400015c4; -r_ble_lll_dtm_rx_pkt_in = 0x400015c8; +//r_ble_lll_dtm_rx_pkt_in = 0x400015c8; r_ble_lll_dtm_rx_sched_cb = 0x400015cc; r_ble_lll_dtm_rx_start = 0x400015d0; r_ble_lll_dtm_rx_test = 0x400015d4; From c4271c77426e83ad52b4f473ed8650d0c353c068 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:21 +0800 Subject: [PATCH 5/8] fix(ble): update ext_version on ESP32-C6 (cherry picked from commit 3558f20a4ed15e4d819d3b05f7b2d0e2709ad3b9) Co-authored-by: zwl --- components/bt/controller/esp32c6/bt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c index 8c1b91173e..255bcbab5e 100644 --- a/components/bt/controller/esp32c6/bt.c +++ b/components/bt/controller/esp32c6/bt.c @@ -72,7 +72,7 @@ #define OSI_COEX_VERSION 0x00010006 #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD -#define EXT_FUNC_VERSION 0x20250415 +#define EXT_FUNC_VERSION 0x20250825 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 #define BT_ASSERT_PRINT ets_printf From 3e7a2685e10fd3864b767fc157f27176c39459bd Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:24 +0800 Subject: [PATCH 6/8] fix(ble): update ext_version on ESP32-H2 (cherry picked from commit b091ec843c3b6fd26b4d66421bf45b04bb64e272) Co-authored-by: zwl --- components/bt/controller/esp32h2/bt.c | 29 ++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index 27fbb7ca54..f22ce5cc8d 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -66,7 +66,7 @@ #define OSI_COEX_VERSION 0x00010006 #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD -#define EXT_FUNC_VERSION 0x20250415 +#define EXT_FUNC_VERSION 0x20250825 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 #define BT_ASSERT_PRINT ets_printf @@ -97,6 +97,7 @@ struct ext_funcs_t { int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv); int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y, const uint8_t *local_priv_key, uint8_t *dhkey); + void (* _esp_reset_modem)(uint8_t mdl_opts, uint8_t start); uint32_t magic; }; @@ -111,6 +112,11 @@ enum { /* External functions or variables ************************************************************************ */ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE +extern void coex_hw_timer_set(uint8_t idx,uint8_t src, uint8_t pti,uint32_t latency, uint32_t perioidc); +extern void coex_hw_timer_enable(uint8_t idx); +extern void coex_hw_timer_disable(uint8_t idx); +#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs); extern int r_ble_controller_init(esp_bt_controller_config_t *cfg); extern void esp_ble_controller_info_capture(uint32_t cycle_times); @@ -186,6 +192,7 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, static int esp_intr_free_wrapper(void **ret_handle); static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2); static uint32_t osi_random_wrapper(void); +static void esp_reset_modem(uint8_t mdl_opts,uint8_t start); static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv); static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, const uint8_t *our_priv_key, uint8_t *out_dhkey); @@ -462,9 +469,29 @@ struct ext_funcs_t ext_funcs_ro = { ._os_random = osi_random_wrapper, ._ecc_gen_key_pair = esp_ecc_gen_key_pair, ._ecc_gen_dh_key = esp_ecc_gen_dh_key, + ._esp_reset_modem = esp_reset_modem, .magic = EXT_FUNC_MAGIC_VALUE, }; +static void IRAM_ATTR esp_reset_modem(uint8_t mdl_opts,uint8_t start) +{ + if (mdl_opts == 0x05) { + if (start) { +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_hw_timer_set(0x04, 0x02, 15, 0, 5000); + coex_hw_timer_enable(0x04); +#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + MODEM_SYSCON.modem_rst_conf.val |= (BIT(16) | BIT(18)); + MODEM_SYSCON.modem_rst_conf.val &= ~(BIT(16) | BIT(18)); + } else { +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_hw_timer_disable(0x04); +#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + } + + } +} + static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2) { From 89f6c1b9b7fb3a392894136e046a639c8cd84374 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:26 +0800 Subject: [PATCH 7/8] feat(ble): add console command to get dtm rx rssi on ESP32-C6 (cherry picked from commit b40f7c773b92aebb153bb07b9d3899d7090ece26) Co-authored-by: zwl --- examples/phy/cert_test/main/cmd_ble_dtm.c | 31 +++++++++++++++++++ .../phy/cert_test/sdkconfig.defaults.esp32c6 | 1 + .../phy/cert_test/sdkconfig.defaults.esp32h2 | 3 +- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/examples/phy/cert_test/main/cmd_ble_dtm.c b/examples/phy/cert_test/main/cmd_ble_dtm.c index 90e9d8daf7..56def074c6 100644 --- a/examples/phy/cert_test/main/cmd_ble_dtm.c +++ b/examples/phy/cert_test/main/cmd_ble_dtm.c @@ -121,6 +121,36 @@ static int dtm_test_enable_command(int argc, char **argv) return 0; } +extern int8_t esp_ble_get_dtm_rx_rssi(void); +static int dtm_get_ble_rx_rssi_command(int argc, char **argv) +{ + int8_t rx_rssi = 0x7F; + if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_ENABLED) { + esp_rom_printf("\nPlease enable BLE DTM mode first by using the command enable_ble_dtm -e 1 before sending this command.\n"); + return 2; + } + + rx_rssi = esp_ble_get_dtm_rx_rssi(); + if (rx_rssi == 0x7f) { + esp_rom_printf("\nRx RSSI is not available!\n"); + } else { + esp_rom_printf("\nRx RSSI is %d dBm\n", rx_rssi); + } + + return 0; +} + +esp_err_t esp_console_register_get_ble_rx_rssi_command(void) +{ + esp_console_cmd_t command = { + .command = "get_ble_rx_rssi", + .help = "Get ble rx rssi during DTM", + .func = &dtm_get_ble_rx_rssi_command, + }; + + return esp_console_cmd_register(&command); +} + esp_err_t esp_console_register_set_ble_tx_power_command(void) { dtm_set_tx_power_cmd_args.cmd_params = arg_int1("i", "index", "","tx power level index"); @@ -185,5 +215,6 @@ esp_err_t dtm_configuration_command_register(void) esp_console_register_get_ble_tx_power_command(); esp_console_register_reconfig_dtm_pins_command(); esp_console_register_enable_ble_dtm_command(); + esp_console_register_get_ble_rx_rssi_command(); return ESP_OK; } diff --git a/examples/phy/cert_test/sdkconfig.defaults.esp32c6 b/examples/phy/cert_test/sdkconfig.defaults.esp32c6 index 8ae9f0ef3b..1dce7aaed0 100644 --- a/examples/phy/cert_test/sdkconfig.defaults.esp32c6 +++ b/examples/phy/cert_test/sdkconfig.defaults.esp32c6 @@ -4,6 +4,7 @@ CONFIG_COMMANDS_ENABLE_BLE_DTM_TEST=y CONFIG_BT_CONTROLLER_ONLY=y +CONFIG_BT_LE_DTM_ENABLED=y CONFIG_BT_LE_HCI_INTERFACE_USE_UART=y CONFIG_BT_LE_HCI_UART_TX_PIN=8 CONFIG_BT_LE_HCI_UART_RX_PIN=9 diff --git a/examples/phy/cert_test/sdkconfig.defaults.esp32h2 b/examples/phy/cert_test/sdkconfig.defaults.esp32h2 index 6cc9f6cd96..c4828b6211 100644 --- a/examples/phy/cert_test/sdkconfig.defaults.esp32h2 +++ b/examples/phy/cert_test/sdkconfig.defaults.esp32h2 @@ -1,8 +1,9 @@ # -# ESP32C6-specific +# ESP32H2-specific # CONFIG_COMMANDS_ENABLE_BLE_DTM_TEST=y CONFIG_BT_CONTROLLER_ONLY=y +CONFIG_BT_LE_DTM_ENABLED=y CONFIG_BT_LE_HCI_INTERFACE_USE_UART=y CONFIG_BT_LE_HCI_UART_TX_PIN=8 CONFIG_BT_LE_HCI_UART_RX_PIN=9 From a08f095131c5f5553eae04e5a11269f69629d197 Mon Sep 17 00:00:00 2001 From: Zhao Wei Liang Date: Wed, 17 Sep 2025 11:13:28 +0800 Subject: [PATCH 8/8] feat(ble): add console command to get dtm rx rssi in hci example (cherry picked from commit c58f07ed1e842f860693db934bc062848c9f7c28) Co-authored-by: zwl --- .../hci/main/dtm_configuration_command.c | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/examples/bluetooth/nimble/hci/main/dtm_configuration_command.c b/examples/bluetooth/nimble/hci/main/dtm_configuration_command.c index 80c2ab6105..e7ac664405 100644 --- a/examples/bluetooth/nimble/hci/main/dtm_configuration_command.c +++ b/examples/bluetooth/nimble/hci/main/dtm_configuration_command.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -67,6 +67,36 @@ static int dtm_reconfig_uart_pins_command(int argc, char **argv) return 0; } +extern int8_t esp_ble_get_dtm_rx_rssi(void); +static int dtm_get_ble_rx_rssi_command(int argc, char **argv) +{ + int8_t rx_rssi = 0x7F; + if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_ENABLED) { + esp_rom_printf("\nPlease enable BLE DTM mode first by using the command enable_ble_dtm -e 1 before sending this command.\n"); + return 2; + } + + rx_rssi = esp_ble_get_dtm_rx_rssi(); + if (rx_rssi == 0x7f) { + esp_rom_printf("\nRx RSSI is not available!\n"); + } else { + esp_rom_printf("\nRx RSSI is %d dBm\n", rx_rssi); + } + + return 0; +} + +esp_err_t esp_console_register_get_ble_rx_rssi_command(void) +{ + esp_console_cmd_t command = { + .command = "get_ble_rx_rssi", + .help = "Get ble rx rssi during DTM", + .func = &dtm_get_ble_rx_rssi_command, + }; + + return esp_console_cmd_register(&command); +} + esp_err_t esp_console_register_set_ble_tx_power_command(void) { dtm_set_tx_power_cmd_args.cmd_params = arg_int1("i", "index", "","tx power level index"); @@ -122,6 +152,7 @@ esp_err_t dtm_configuration_command_enable(void) esp_console_register_set_ble_tx_power_command(); esp_console_register_get_ble_tx_power_command(); esp_console_register_reconfig_dtm_pins_command(); + esp_console_register_get_ble_rx_rssi_command(); esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl)); ESP_ERROR_CHECK(esp_console_start_repl(repl));