diff --git a/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core1_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core1_reg.h new file mode 100644 index 0000000000..0cc0a6746b --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core1_reg.h @@ -0,0 +1,3592 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CORE1_LP_RTC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0) +/** CORE1_CORE1_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP_M (CORE1_CORE1_LP_RTC_INT_MAP_V << CORE1_CORE1_LP_RTC_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_MAP_S 0 +/** CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_RTC_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4) +/** CORE1_CORE1_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP_M (CORE1_CORE1_LP_WDT_INT_MAP_V << CORE1_CORE1_LP_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_MAP_S 0 +/** CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_WDT_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_TIMER_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8) +/** CORE1_CORE1_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_M (CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_MAP_S 0 +/** CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_TIMER_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc) +/** CORE1_CORE1_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_M (CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V << CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_MAP_S 0 +/** CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_MB_HP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10) +/** CORE1_CORE1_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP_M (CORE1_CORE1_MB_HP_INT_MAP_V << CORE1_CORE1_MB_HP_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_MAP_S 0 +/** CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_MB_HP_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_MB_LP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14) +/** CORE1_CORE1_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP_M (CORE1_CORE1_MB_LP_INT_MAP_V << CORE1_CORE1_MB_LP_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_MAP_S 0 +/** CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_MB_LP_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PMU_REG_0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18) +/** CORE1_CORE1_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP_M (CORE1_CORE1_PMU_REG_0_INT_MAP_V << CORE1_CORE1_PMU_REG_0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_MAP_S 0 +/** CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PMU_REG_1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c) +/** CORE1_CORE1_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP_M (CORE1_CORE1_PMU_REG_1_INT_MAP_V << CORE1_CORE1_PMU_REG_1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_MAP_S 0 +/** CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_ANAPERI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20) +/** CORE1_CORE1_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP_M (CORE1_CORE1_LP_ANAPERI_INT_MAP_V << CORE1_CORE1_LP_ANAPERI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_MAP_S 0 +/** CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24) +/** CORE1_CORE1_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP_M (CORE1_CORE1_LP_ADC_INT_MAP_V << CORE1_CORE1_LP_ADC_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_MAP_S 0 +/** CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_ADC_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_GPIO_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28) +/** CORE1_CORE1_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP_M (CORE1_CORE1_LP_GPIO_INT_MAP_V << CORE1_CORE1_LP_GPIO_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_MAP_S 0 +/** CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_GPIO_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_I2C_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c) +/** CORE1_CORE1_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP_M (CORE1_CORE1_LP_I2C_INT_MAP_V << CORE1_CORE1_LP_I2C_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_MAP_S 0 +/** CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_I2C_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_I2S_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30) +/** CORE1_CORE1_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP_M (CORE1_CORE1_LP_I2S_INT_MAP_V << CORE1_CORE1_LP_I2S_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_MAP_S 0 +/** CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_I2S_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_SPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34) +/** CORE1_CORE1_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP_M (CORE1_CORE1_LP_SPI_INT_MAP_V << CORE1_CORE1_LP_SPI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_MAP_S 0 +/** CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_SPI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_TOUCH_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38) +/** CORE1_CORE1_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP_M (CORE1_CORE1_LP_TOUCH_INT_MAP_V << CORE1_CORE1_LP_TOUCH_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_MAP_S 0 +/** CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_TSENS_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3c) +/** CORE1_CORE1_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP_M (CORE1_CORE1_LP_TSENS_INT_MAP_V << CORE1_CORE1_LP_TSENS_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_MAP_S 0 +/** CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_TSENS_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_UART_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40) +/** CORE1_CORE1_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP_M (CORE1_CORE1_LP_UART_INT_MAP_V << CORE1_CORE1_LP_UART_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_MAP_S 0 +/** CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_UART_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_EFUSE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44) +/** CORE1_CORE1_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP_M (CORE1_CORE1_LP_EFUSE_INT_MAP_V << CORE1_CORE1_LP_EFUSE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_MAP_S 0 +/** CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_SW_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48) +/** CORE1_CORE1_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP_M (CORE1_CORE1_LP_SW_INT_MAP_V << CORE1_CORE1_LP_SW_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_MAP_S 0 +/** CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_SW_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4c) +/** CORE1_CORE1_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP_M (CORE1_CORE1_LP_SYSREG_INT_MAP_V << CORE1_CORE1_LP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_MAP_S 0 +/** CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LP_HUK_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50) +/** CORE1_CORE1_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP_M (CORE1_CORE1_LP_HUK_INT_MAP_V << CORE1_CORE1_LP_HUK_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_MAP_S 0 +/** CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LP_HUK_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SYS_ICM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54) +/** CORE1_CORE1_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP_M (CORE1_CORE1_SYS_ICM_INT_MAP_V << CORE1_CORE1_SYS_ICM_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_MAP_S 0 +/** CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYS_ICM_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_USB_DEVICE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58) +/** CORE1_CORE1_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP_M (CORE1_CORE1_USB_DEVICE_INT_MAP_V << CORE1_CORE1_USB_DEVICE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_MAP_S 0 +/** CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SDIO_HOST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5c) +/** CORE1_CORE1_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP_M (CORE1_CORE1_SDIO_HOST_INT_MAP_V << CORE1_CORE1_SDIO_HOST_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_MAP_S 0 +/** CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GDMA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60) +/** CORE1_CORE1_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP_M (CORE1_CORE1_GDMA_INT_MAP_V << CORE1_CORE1_GDMA_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GDMA_INT_MAP_S 0 +/** CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GDMA_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SPI2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64) +/** CORE1_CORE1_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP_M (CORE1_CORE1_SPI2_INT_MAP_V << CORE1_CORE1_SPI2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SPI2_INT_MAP_S 0 +/** CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SPI2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SPI3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68) +/** CORE1_CORE1_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP_M (CORE1_CORE1_SPI3_INT_MAP_V << CORE1_CORE1_SPI3_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SPI3_INT_MAP_S 0 +/** CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SPI3_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I2S0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6c) +/** CORE1_CORE1_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP_M (CORE1_CORE1_I2S0_INT_MAP_V << CORE1_CORE1_I2S0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2S0_INT_MAP_S 0 +/** CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2S0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I2S1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70) +/** CORE1_CORE1_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP_M (CORE1_CORE1_I2S1_INT_MAP_V << CORE1_CORE1_I2S1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2S1_INT_MAP_S 0 +/** CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2S1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I2S2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74) +/** CORE1_CORE1_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP_M (CORE1_CORE1_I2S2_INT_MAP_V << CORE1_CORE1_I2S2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2S2_INT_MAP_S 0 +/** CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2S2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_UHCI0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78) +/** CORE1_CORE1_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP_M (CORE1_CORE1_UHCI0_INT_MAP_V << CORE1_CORE1_UHCI0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_MAP_S 0 +/** CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UHCI0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_UART0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7c) +/** CORE1_CORE1_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP_M (CORE1_CORE1_UART0_INT_MAP_V << CORE1_CORE1_UART0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART0_INT_MAP_S 0 +/** CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_UART1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80) +/** CORE1_CORE1_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP_M (CORE1_CORE1_UART1_INT_MAP_V << CORE1_CORE1_UART1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART1_INT_MAP_S 0 +/** CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_UART2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84) +/** CORE1_CORE1_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP_M (CORE1_CORE1_UART2_INT_MAP_V << CORE1_CORE1_UART2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART2_INT_MAP_S 0 +/** CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_UART3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88) +/** CORE1_CORE1_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP_M (CORE1_CORE1_UART3_INT_MAP_V << CORE1_CORE1_UART3_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART3_INT_MAP_S 0 +/** CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART3_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_UART4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8c) +/** CORE1_CORE1_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP_M (CORE1_CORE1_UART4_INT_MAP_V << CORE1_CORE1_UART4_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_UART4_INT_MAP_S 0 +/** CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_UART4_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LCD_CAM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90) +/** CORE1_CORE1_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP_M (CORE1_CORE1_LCD_CAM_INT_MAP_V << CORE1_CORE1_LCD_CAM_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_MAP_S 0 +/** CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LCD_CAM_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_ADC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94) +/** CORE1_CORE1_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP_M (CORE1_CORE1_ADC_INT_MAP_V << CORE1_CORE1_ADC_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ADC_INT_MAP_S 0 +/** CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ADC_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PWM0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98) +/** CORE1_CORE1_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP_M (CORE1_CORE1_PWM0_INT_MAP_V << CORE1_CORE1_PWM0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PWM0_INT_MAP_S 0 +/** CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PWM0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PWM1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9c) +/** CORE1_CORE1_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP_M (CORE1_CORE1_PWM1_INT_MAP_V << CORE1_CORE1_PWM1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PWM1_INT_MAP_S 0 +/** CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PWM1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CAN0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa0) +/** CORE1_CORE1_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP_M (CORE1_CORE1_CAN0_INT_MAP_V << CORE1_CORE1_CAN0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CAN0_INT_MAP_S 0 +/** CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CAN0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CAN1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa4) +/** CORE1_CORE1_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP_M (CORE1_CORE1_CAN1_INT_MAP_V << CORE1_CORE1_CAN1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CAN1_INT_MAP_S 0 +/** CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CAN1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CAN2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa8) +/** CORE1_CORE1_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP_M (CORE1_CORE1_CAN2_INT_MAP_V << CORE1_CORE1_CAN2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CAN2_INT_MAP_S 0 +/** CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CAN2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_RMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xac) +/** CORE1_CORE1_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP_M (CORE1_CORE1_RMT_INT_MAP_V << CORE1_CORE1_RMT_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_RMT_INT_MAP_S 0 +/** CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_RMT_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I2C0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb0) +/** CORE1_CORE1_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP_M (CORE1_CORE1_I2C0_INT_MAP_V << CORE1_CORE1_I2C0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2C0_INT_MAP_S 0 +/** CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2C0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I2C1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb4) +/** CORE1_CORE1_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP_M (CORE1_CORE1_I2C1_INT_MAP_V << CORE1_CORE1_I2C1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I2C1_INT_MAP_S 0 +/** CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I2C1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_TIMERGRP0_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb8) +/** CORE1_CORE1_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP_M (CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_MAP_S 0 +/** CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_TIMERGRP0_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xbc) +/** CORE1_CORE1_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP_M (CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_MAP_S 0 +/** CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_TIMERGRP0_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc0) +/** CORE1_CORE1_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_M (CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_MAP_S 0 +/** CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_TIMERGRP1_T0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc4) +/** CORE1_CORE1_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP_M (CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_MAP_S 0 +/** CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_TIMERGRP1_T1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc8) +/** CORE1_CORE1_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP_M (CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V << CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_MAP_S 0 +/** CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_TIMERGRP1_WDT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xcc) +/** CORE1_CORE1_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_M (CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V << CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_MAP_S 0 +/** CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LEDC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd0) +/** CORE1_CORE1_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP_M (CORE1_CORE1_LEDC_INT_MAP_V << CORE1_CORE1_LEDC_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LEDC_INT_MAP_S 0 +/** CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LEDC_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SYSTIMER_TARGET0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd4) +/** CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 +/** CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SYSTIMER_TARGET1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd8) +/** CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 +/** CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SYSTIMER_TARGET2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xdc) +/** CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_M (CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 +/** CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe0) +/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_MAP_S 0 +/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe4) +/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_MAP_S 0 +/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe8) +/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_M (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_MAP_S 0 +/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xec) +/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_S 0 +/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf0) +/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_S 0 +/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf4) +/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_M (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_S 0 +/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf8) +/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xfc) +/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100) +/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_M (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104) +/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108) +/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10c) +/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_M (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_RSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110) +/** CORE1_CORE1_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP_M (CORE1_CORE1_RSA_INT_MAP_V << CORE1_CORE1_RSA_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_RSA_INT_MAP_S 0 +/** CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_RSA_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AES_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114) +/** CORE1_CORE1_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AES_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AES_INT_MAP_M (CORE1_CORE1_AES_INT_MAP_V << CORE1_CORE1_AES_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AES_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AES_INT_MAP_S 0 +/** CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AES_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SHA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118) +/** CORE1_CORE1_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP_M (CORE1_CORE1_SHA_INT_MAP_V << CORE1_CORE1_SHA_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SHA_INT_MAP_S 0 +/** CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SHA_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_ECC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11c) +/** CORE1_CORE1_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP_M (CORE1_CORE1_ECC_INT_MAP_V << CORE1_CORE1_ECC_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ECC_INT_MAP_S 0 +/** CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ECC_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_ECDSA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120) +/** CORE1_CORE1_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP_M (CORE1_CORE1_ECDSA_INT_MAP_V << CORE1_CORE1_ECDSA_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_MAP_S 0 +/** CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ECDSA_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_KM_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124) +/** CORE1_CORE1_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_KM_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_KM_INT_MAP_M (CORE1_CORE1_KM_INT_MAP_V << CORE1_CORE1_KM_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_KM_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_KM_INT_MAP_S 0 +/** CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_KM_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GPIO_INT0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128) +/** CORE1_CORE1_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP_M (CORE1_CORE1_GPIO_INT0_MAP_V << CORE1_CORE1_GPIO_INT0_MAP_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_MAP_S 0 +/** CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_M (CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT0_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GPIO_INT1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12c) +/** CORE1_CORE1_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP_M (CORE1_CORE1_GPIO_INT1_MAP_V << CORE1_CORE1_GPIO_INT1_MAP_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_MAP_S 0 +/** CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_M (CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT1_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GPIO_INT2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130) +/** CORE1_CORE1_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP_M (CORE1_CORE1_GPIO_INT2_MAP_V << CORE1_CORE1_GPIO_INT2_MAP_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_MAP_S 0 +/** CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_M (CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT2_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GPIO_INT3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134) +/** CORE1_CORE1_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP_M (CORE1_CORE1_GPIO_INT3_MAP_V << CORE1_CORE1_GPIO_INT3_MAP_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_MAP_S 0 +/** CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_M (CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_INT3_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GPIO_PAD_COMP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138) +/** CORE1_CORE1_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_M (CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V << CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_MAP_S 0 +/** CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CPU_INT_FROM_CPU_0_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13c) +/** CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_MAP_S 0 +/** CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_M (CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CPU_INT_FROM_CPU_1_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140) +/** CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_MAP_S 0 +/** CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_M (CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CPU_INT_FROM_CPU_2_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144) +/** CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_MAP_S 0 +/** CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_M (CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CPU_INT_FROM_CPU_3_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148) +/** CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_M (CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_MAP_S 0 +/** CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_M (CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CACHE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14c) +/** CORE1_CORE1_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP_M (CORE1_CORE1_CACHE_INT_MAP_V << CORE1_CORE1_CACHE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CACHE_INT_MAP_S 0 +/** CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CACHE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_FLASH_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150) +/** CORE1_CORE1_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP_M (CORE1_CORE1_FLASH_MSPI_INT_MAP_V << CORE1_CORE1_FLASH_MSPI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_MAP_S 0 +/** CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154) +/** CORE1_CORE1_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP_M (CORE1_CORE1_CSI_BRIDGE_INT_MAP_V << CORE1_CORE1_CSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_MAP_S 0 +/** CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DSI_BRIDGE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158) +/** CORE1_CORE1_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP_M (CORE1_CORE1_DSI_BRIDGE_INT_MAP_V << CORE1_CORE1_DSI_BRIDGE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_MAP_S 0 +/** CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15c) +/** CORE1_CORE1_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP_M (CORE1_CORE1_CSI_INT_MAP_V << CORE1_CORE1_CSI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CSI_INT_MAP_S 0 +/** CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CSI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DSI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160) +/** CORE1_CORE1_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP_M (CORE1_CORE1_DSI_INT_MAP_V << CORE1_CORE1_DSI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DSI_INT_MAP_S 0 +/** CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DSI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_GMII_PHY_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164) +/** CORE1_CORE1_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP_M (CORE1_CORE1_GMII_PHY_INT_MAP_V << CORE1_CORE1_GMII_PHY_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_MAP_S 0 +/** CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_GMII_PHY_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_LPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168) +/** CORE1_CORE1_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP_M (CORE1_CORE1_LPI_INT_MAP_V << CORE1_CORE1_LPI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_LPI_INT_MAP_S 0 +/** CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_LPI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PMT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16c) +/** CORE1_CORE1_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP_M (CORE1_CORE1_PMT_INT_MAP_V << CORE1_CORE1_PMT_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PMT_INT_MAP_S 0 +/** CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PMT_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_SBD_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170) +/** CORE1_CORE1_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP_M (CORE1_CORE1_SBD_INT_MAP_V << CORE1_CORE1_SBD_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_SBD_INT_MAP_S 0 +/** CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_SBD_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_USB_OTG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174) +/** CORE1_CORE1_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP_M (CORE1_CORE1_USB_OTG_INT_MAP_V << CORE1_CORE1_USB_OTG_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_MAP_S 0 +/** CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_OTG_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178) +/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S 0 +/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; + * default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; + * default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_JPEG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17c) +/** CORE1_CORE1_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP_M (CORE1_CORE1_JPEG_INT_MAP_V << CORE1_CORE1_JPEG_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_JPEG_INT_MAP_S 0 +/** CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_JPEG_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PPA_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180) +/** CORE1_CORE1_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP_M (CORE1_CORE1_PPA_INT_MAP_V << CORE1_CORE1_PPA_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PPA_INT_MAP_S 0 +/** CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PPA_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CORE0_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184) +/** CORE1_CORE1_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP_M (CORE1_CORE1_CORE0_TRACE_INT_MAP_V << CORE1_CORE1_CORE0_TRACE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_MAP_S 0 +/** CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_CORE1_TRACE_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188) +/** CORE1_CORE1_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP_M (CORE1_CORE1_CORE1_TRACE_INT_MAP_V << CORE1_CORE1_CORE1_TRACE_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_MAP_S 0 +/** CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_HP_CORE_CTRL_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18c) +/** CORE1_CORE1_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP_M (CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V << CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_MAP_S 0 +/** CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_ISP_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190) +/** CORE1_CORE1_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP_M (CORE1_CORE1_ISP_INT_MAP_V << CORE1_CORE1_ISP_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ISP_INT_MAP_S 0 +/** CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ISP_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I3C_MST_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194) +/** CORE1_CORE1_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP_M (CORE1_CORE1_I3C_MST_INT_MAP_V << CORE1_CORE1_I3C_MST_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_MAP_S 0 +/** CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I3C_MST_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_I3C_SLV_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198) +/** CORE1_CORE1_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP_M (CORE1_CORE1_I3C_SLV_INT_MAP_V << CORE1_CORE1_I3C_SLV_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_MAP_S 0 +/** CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_I3C_SLV_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_USB_OTG11_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c) +/** CORE1_CORE1_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP_M (CORE1_CORE1_USB_OTG11_INT_MAP_V << CORE1_CORE1_USB_OTG11_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_MAP_S 0 +/** CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_USB_OTG11_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a0) +/** CORE1_CORE1_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a4) +/** CORE1_CORE1_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a8) +/** CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ac) +/** CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b0) +/** CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PSRAM_MSPI_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b4) +/** CORE1_CORE1_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP_M (CORE1_CORE1_PSRAM_MSPI_INT_MAP_V << CORE1_CORE1_PSRAM_MSPI_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_MAP_S 0 +/** CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_HP_SYSREG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b8) +/** CORE1_CORE1_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP_M (CORE1_CORE1_HP_SYSREG_INT_MAP_V << CORE1_CORE1_HP_SYSREG_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_MAP_S 0 +/** CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_PCNT_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1bc) +/** CORE1_CORE1_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP_M (CORE1_CORE1_PCNT_INT_MAP_V << CORE1_CORE1_PCNT_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_PCNT_INT_MAP_S 0 +/** CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_PCNT_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_HP_PAU_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c0) +/** CORE1_CORE1_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP_M (CORE1_CORE1_HP_PAU_INT_MAP_V << CORE1_CORE1_HP_PAU_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_MAP_S 0 +/** CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_PAU_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_HP_PARLIO_RX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c4) +/** CORE1_CORE1_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP_M (CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_MAP_S 0 +/** CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_HP_PARLIO_TX_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c8) +/** CORE1_CORE1_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP_M (CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V << CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_MAP_S 0 +/** CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1cc) +/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d0) +/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d4) +/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d8) +/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1dc) +/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_M (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e0) +/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e4) +/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e8) +/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ec) +/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f0) +/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f4) +/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_M (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_MAP_S 0 +/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_H264_REG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f8) +/** CORE1_CORE1_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP_M (CORE1_CORE1_H264_REG_INT_MAP_V << CORE1_CORE1_H264_REG_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_MAP_S 0 +/** CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_H264_REG_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_ASSIST_DEBUG_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1fc) +/** CORE1_CORE1_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP_M (CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V << CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_MAP_S 0 +/** CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_INTR_STATUS_REG_0_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200) +/** CORE1_CORE1_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0_M (CORE1_CORE1_INTR_STATUS_0_V << CORE1_CORE1_INTR_STATUS_0_S) +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_0_S 0 + +/** CORE1_INTR_STATUS_REG_1_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204) +/** CORE1_CORE1_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1_M (CORE1_CORE1_INTR_STATUS_1_V << CORE1_CORE1_INTR_STATUS_1_S) +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_1_S 0 + +/** CORE1_INTR_STATUS_REG_2_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208) +/** CORE1_CORE1_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2_M (CORE1_CORE1_INTR_STATUS_2_V << CORE1_CORE1_INTR_STATUS_2_S) +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_2_S 0 + +/** CORE1_INTR_STATUS_REG_3_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20c) +/** CORE1_CORE1_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3_M (CORE1_CORE1_INTR_STATUS_3_V << CORE1_CORE1_INTR_STATUS_3_S) +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_3_S 0 + +/** CORE1_CLOCK_GATE_REG register + * NA + */ +#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210) +/** CORE1_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ +#define INTERRUPT_CORE1_CORE1_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE1_CORE1_REG_CLK_EN_M (CORE1_CORE1_REG_CLK_EN_V << CORE1_CORE1_REG_CLK_EN_S) +#define INTERRUPT_CORE1_CORE1_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_REG_CLK_EN_S 0 + +/** CORE1_DMA2D_IN_CH2_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x214) +/** CORE1_CORE1_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_M (CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_V << CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_DMA2D_OUT_CH3_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x218) +/** CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_M (CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_V << CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_MAP_S 0 +/** CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_AXI_PERF_MON_INT_MAP_REG register + * NA + */ +#define INTERRUPT_CORE1_AXI_PERF_MON_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x21c) +/** CORE1_CORE1_AXI_PERF_MON_INT_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP_M (CORE1_CORE1_AXI_PERF_MON_INT_MAP_V << CORE1_CORE1_AXI_PERF_MON_INT_MAP_S) +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_MAP_S 0 +/** CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC (BIT(6)) +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_M (CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V << CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S 6 +/** CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG (BIT(7)) +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_M (CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V << CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S) +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V 0x00000001U +#define INTERRUPT_CORE1_CORE1_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S 7 + +/** CORE1_INTR_STATUS_REG_4_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x220) +/** CORE1_CORE1_INTR_STATUS_4 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4_M (CORE1_CORE1_INTR_STATUS_4_V << CORE1_CORE1_INTR_STATUS_4_S) +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_STATUS_4_S 0 + +/** CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x228) +/** CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC 0x0000003FU +#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_M (CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_V << CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_S) +#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_V 0x0000003FU +#define INTERRUPT_CORE1_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_S 0 + +/** CORE1_INTR_SEC_STATUS_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SEC_STATUS_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x22c) +/** CORE1_CORE1_INTR_SEC_STATUS : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS_M (CORE1_CORE1_INTR_SEC_STATUS_V << CORE1_CORE1_INTR_SEC_STATUS_S) +#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SEC_STATUS_S 0 + +/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x230) +/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_M (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_S) +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_0_S 0 + +/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x234) +/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_M (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_S) +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_1_S 0 + +/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x238) +/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_M (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_S) +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_2_S 0 + +/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x23c) +/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_M (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_S) +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_3_S 0 + +/** CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_REG register + * NA + */ +#define INTERRUPT_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x240) +/** CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4 : RO; bitpos: [31:0]; default: 0; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_M (CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_V << CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_S) +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_V 0xFFFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTR_SRC_PASS_IN_SEC_STATUS_4_S 0 + +/** CORE1_INTERRUPT_REG_DATE_REG register + * NA + */ +#define INTERRUPT_CORE1_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3fc) +/** CORE1_CORE1_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 38806144; + * NA + */ +#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE_M (CORE1_CORE1_INTERRUPT_REG_DATE_V << CORE1_CORE1_INTERRUPT_REG_DATE_S) +#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE1_CORE1_INTERRUPT_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core1_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core1_struct.h new file mode 100644 index 0000000000..67d86f98bb --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core1_struct.h @@ -0,0 +1,3528 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: CORE1 LP RTC INT MAP REG */ +/** Type of lp_rtc_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_rtc_int_map:6; + /** core1_lp_rtc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_rtc_int_src_pass_in_sec:1; + /** core1_lp_rtc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_rtc_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_rtc_int_map_reg_t; + + +/** Group: CORE1 LP WDT INT MAP REG */ +/** Type of lp_wdt_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_wdt_int_map:6; + /** core1_lp_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_wdt_int_src_pass_in_sec:1; + /** core1_lp_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_wdt_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_wdt_int_map_reg_t; + + +/** Group: CORE1 LP TIMER REG 0 INT MAP REG */ +/** Type of lp_timer_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_timer_reg_0_int_map:6; + /** core1_lp_timer_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_timer_reg_0_int_src_pass_in_sec:1; + /** core1_lp_timer_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_timer_reg_0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_timer_reg_0_int_map_reg_t; + + +/** Group: CORE1 LP TIMER REG 1 INT MAP REG */ +/** Type of lp_timer_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_timer_reg_1_int_map:6; + /** core1_lp_timer_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_timer_reg_1_int_src_pass_in_sec:1; + /** core1_lp_timer_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_timer_reg_1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_timer_reg_1_int_map_reg_t; + + +/** Group: CORE1 MB HP INT MAP REG */ +/** Type of mb_hp_int_map register + * NA + */ +typedef union { + struct { + /** core1_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_mb_hp_int_map:6; + /** core1_mb_hp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_mb_hp_int_src_pass_in_sec:1; + /** core1_mb_hp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_mb_hp_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_mb_hp_int_map_reg_t; + + +/** Group: CORE1 MB LP INT MAP REG */ +/** Type of mb_lp_int_map register + * NA + */ +typedef union { + struct { + /** core1_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_mb_lp_int_map:6; + /** core1_mb_lp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_mb_lp_int_src_pass_in_sec:1; + /** core1_mb_lp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_mb_lp_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_mb_lp_int_map_reg_t; + + +/** Group: CORE1 PMU REG 0 INT MAP REG */ +/** Type of pmu_reg_0_int_map register + * NA + */ +typedef union { + struct { + /** core1_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_pmu_reg_0_int_map:6; + /** core1_pmu_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_pmu_reg_0_int_src_pass_in_sec:1; + /** core1_pmu_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_pmu_reg_0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_pmu_reg_0_int_map_reg_t; + + +/** Group: CORE1 PMU REG 1 INT MAP REG */ +/** Type of pmu_reg_1_int_map register + * NA + */ +typedef union { + struct { + /** core1_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_pmu_reg_1_int_map:6; + /** core1_pmu_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_pmu_reg_1_int_src_pass_in_sec:1; + /** core1_pmu_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_pmu_reg_1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_pmu_reg_1_int_map_reg_t; + + +/** Group: CORE1 LP ANAPERI INT MAP REG */ +/** Type of lp_anaperi_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_anaperi_int_map:6; + /** core1_lp_anaperi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_anaperi_int_src_pass_in_sec:1; + /** core1_lp_anaperi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_anaperi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_anaperi_int_map_reg_t; + + +/** Group: CORE1 LP ADC INT MAP REG */ +/** Type of lp_adc_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_adc_int_map:6; + /** core1_lp_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_adc_int_src_pass_in_sec:1; + /** core1_lp_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_adc_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_adc_int_map_reg_t; + + +/** Group: CORE1 LP GPIO INT MAP REG */ +/** Type of lp_gpio_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_gpio_int_map:6; + /** core1_lp_gpio_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_gpio_int_src_pass_in_sec:1; + /** core1_lp_gpio_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_gpio_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_gpio_int_map_reg_t; + + +/** Group: CORE1 LP I2C INT MAP REG */ +/** Type of lp_i2c_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_i2c_int_map:6; + /** core1_lp_i2c_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_i2c_int_src_pass_in_sec:1; + /** core1_lp_i2c_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_i2c_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_i2c_int_map_reg_t; + + +/** Group: CORE1 LP I2S INT MAP REG */ +/** Type of lp_i2s_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_i2s_int_map:6; + /** core1_lp_i2s_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_i2s_int_src_pass_in_sec:1; + /** core1_lp_i2s_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_i2s_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_i2s_int_map_reg_t; + + +/** Group: CORE1 LP SPI INT MAP REG */ +/** Type of lp_spi_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_spi_int_map:6; + /** core1_lp_spi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_spi_int_src_pass_in_sec:1; + /** core1_lp_spi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_spi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_spi_int_map_reg_t; + + +/** Group: CORE1 LP TOUCH INT MAP REG */ +/** Type of lp_touch_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_touch_int_map:6; + /** core1_lp_touch_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_touch_int_src_pass_in_sec:1; + /** core1_lp_touch_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_touch_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_touch_int_map_reg_t; + + +/** Group: CORE1 LP TSENS INT MAP REG */ +/** Type of lp_tsens_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_tsens_int_map:6; + /** core1_lp_tsens_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_tsens_int_src_pass_in_sec:1; + /** core1_lp_tsens_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_tsens_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_tsens_int_map_reg_t; + + +/** Group: CORE1 LP UART INT MAP REG */ +/** Type of lp_uart_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_uart_int_map:6; + /** core1_lp_uart_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_uart_int_src_pass_in_sec:1; + /** core1_lp_uart_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_uart_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_uart_int_map_reg_t; + + +/** Group: CORE1 LP EFUSE INT MAP REG */ +/** Type of lp_efuse_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_efuse_int_map:6; + /** core1_lp_efuse_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_efuse_int_src_pass_in_sec:1; + /** core1_lp_efuse_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_efuse_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_efuse_int_map_reg_t; + + +/** Group: CORE1 LP SW INT MAP REG */ +/** Type of lp_sw_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_sw_int_map:6; + /** core1_lp_sw_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_sw_int_src_pass_in_sec:1; + /** core1_lp_sw_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_sw_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_sw_int_map_reg_t; + + +/** Group: CORE1 LP SYSREG INT MAP REG */ +/** Type of lp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_sysreg_int_map:6; + /** core1_lp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_sysreg_int_src_pass_in_sec:1; + /** core1_lp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_sysreg_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_sysreg_int_map_reg_t; + + +/** Group: CORE1 LP HUK INT MAP REG */ +/** Type of lp_huk_int_map register + * NA + */ +typedef union { + struct { + /** core1_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lp_huk_int_map:6; + /** core1_lp_huk_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lp_huk_int_src_pass_in_sec:1; + /** core1_lp_huk_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lp_huk_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lp_huk_int_map_reg_t; + + +/** Group: CORE1 SYS ICM INT MAP REG */ +/** Type of sys_icm_int_map register + * NA + */ +typedef union { + struct { + /** core1_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_sys_icm_int_map:6; + /** core1_sys_icm_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_sys_icm_int_src_pass_in_sec:1; + /** core1_sys_icm_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_sys_icm_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_sys_icm_int_map_reg_t; + + +/** Group: CORE1 USB DEVICE INT MAP REG */ +/** Type of usb_device_int_map register + * NA + */ +typedef union { + struct { + /** core1_usb_device_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_usb_device_int_map:6; + /** core1_usb_device_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_usb_device_int_src_pass_in_sec:1; + /** core1_usb_device_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_usb_device_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_usb_device_int_map_reg_t; + + +/** Group: CORE1 SDIO HOST INT MAP REG */ +/** Type of sdio_host_int_map register + * NA + */ +typedef union { + struct { + /** core1_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_sdio_host_int_map:6; + /** core1_sdio_host_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_sdio_host_int_src_pass_in_sec:1; + /** core1_sdio_host_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_sdio_host_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_sdio_host_int_map_reg_t; + + +/** Group: CORE1 GDMA INT MAP REG */ +/** Type of gdma_int_map register + * NA + */ +typedef union { + struct { + /** core1_gdma_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gdma_int_map:6; + /** core1_gdma_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gdma_int_src_pass_in_sec:1; + /** core1_gdma_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gdma_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gdma_int_map_reg_t; + + +/** Group: CORE1 SPI2 INT MAP REG */ +/** Type of spi2_int_map register + * NA + */ +typedef union { + struct { + /** core1_spi2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_spi2_int_map:6; + /** core1_spi2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_spi2_int_src_pass_in_sec:1; + /** core1_spi2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_spi2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_spi2_int_map_reg_t; + + +/** Group: CORE1 SPI3 INT MAP REG */ +/** Type of spi3_int_map register + * NA + */ +typedef union { + struct { + /** core1_spi3_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_spi3_int_map:6; + /** core1_spi3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_spi3_int_src_pass_in_sec:1; + /** core1_spi3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_spi3_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_spi3_int_map_reg_t; + + +/** Group: CORE1 I2S0 INT MAP REG */ +/** Type of i2s0_int_map register + * NA + */ +typedef union { + struct { + /** core1_i2s0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i2s0_int_map:6; + /** core1_i2s0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i2s0_int_src_pass_in_sec:1; + /** core1_i2s0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i2s0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i2s0_int_map_reg_t; + + +/** Group: CORE1 I2S1 INT MAP REG */ +/** Type of i2s1_int_map register + * NA + */ +typedef union { + struct { + /** core1_i2s1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i2s1_int_map:6; + /** core1_i2s1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i2s1_int_src_pass_in_sec:1; + /** core1_i2s1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i2s1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i2s1_int_map_reg_t; + + +/** Group: CORE1 I2S2 INT MAP REG */ +/** Type of i2s2_int_map register + * NA + */ +typedef union { + struct { + /** core1_i2s2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i2s2_int_map:6; + /** core1_i2s2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i2s2_int_src_pass_in_sec:1; + /** core1_i2s2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i2s2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i2s2_int_map_reg_t; + + +/** Group: CORE1 UHCI0 INT MAP REG */ +/** Type of uhci0_int_map register + * NA + */ +typedef union { + struct { + /** core1_uhci0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_uhci0_int_map:6; + /** core1_uhci0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_uhci0_int_src_pass_in_sec:1; + /** core1_uhci0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_uhci0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_uhci0_int_map_reg_t; + + +/** Group: CORE1 UART0 INT MAP REG */ +/** Type of uart0_int_map register + * NA + */ +typedef union { + struct { + /** core1_uart0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_uart0_int_map:6; + /** core1_uart0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_uart0_int_src_pass_in_sec:1; + /** core1_uart0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_uart0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_uart0_int_map_reg_t; + + +/** Group: CORE1 UART1 INT MAP REG */ +/** Type of uart1_int_map register + * NA + */ +typedef union { + struct { + /** core1_uart1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_uart1_int_map:6; + /** core1_uart1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_uart1_int_src_pass_in_sec:1; + /** core1_uart1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_uart1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_uart1_int_map_reg_t; + + +/** Group: CORE1 UART2 INT MAP REG */ +/** Type of uart2_int_map register + * NA + */ +typedef union { + struct { + /** core1_uart2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_uart2_int_map:6; + /** core1_uart2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_uart2_int_src_pass_in_sec:1; + /** core1_uart2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_uart2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_uart2_int_map_reg_t; + + +/** Group: CORE1 UART3 INT MAP REG */ +/** Type of uart3_int_map register + * NA + */ +typedef union { + struct { + /** core1_uart3_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_uart3_int_map:6; + /** core1_uart3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_uart3_int_src_pass_in_sec:1; + /** core1_uart3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_uart3_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_uart3_int_map_reg_t; + + +/** Group: CORE1 UART4 INT MAP REG */ +/** Type of uart4_int_map register + * NA + */ +typedef union { + struct { + /** core1_uart4_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_uart4_int_map:6; + /** core1_uart4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_uart4_int_src_pass_in_sec:1; + /** core1_uart4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_uart4_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_uart4_int_map_reg_t; + + +/** Group: CORE1 LCD CAM INT MAP REG */ +/** Type of lcd_cam_int_map register + * NA + */ +typedef union { + struct { + /** core1_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lcd_cam_int_map:6; + /** core1_lcd_cam_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lcd_cam_int_src_pass_in_sec:1; + /** core1_lcd_cam_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lcd_cam_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lcd_cam_int_map_reg_t; + + +/** Group: CORE1 ADC INT MAP REG */ +/** Type of adc_int_map register + * NA + */ +typedef union { + struct { + /** core1_adc_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_adc_int_map:6; + /** core1_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_adc_int_src_pass_in_sec:1; + /** core1_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_adc_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_adc_int_map_reg_t; + + +/** Group: CORE1 PWM0 INT MAP REG */ +/** Type of pwm0_int_map register + * NA + */ +typedef union { + struct { + /** core1_pwm0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_pwm0_int_map:6; + /** core1_pwm0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_pwm0_int_src_pass_in_sec:1; + /** core1_pwm0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_pwm0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_pwm0_int_map_reg_t; + + +/** Group: CORE1 PWM1 INT MAP REG */ +/** Type of pwm1_int_map register + * NA + */ +typedef union { + struct { + /** core1_pwm1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_pwm1_int_map:6; + /** core1_pwm1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_pwm1_int_src_pass_in_sec:1; + /** core1_pwm1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_pwm1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_pwm1_int_map_reg_t; + + +/** Group: CORE1 CAN0 INT MAP REG */ +/** Type of can0_int_map register + * NA + */ +typedef union { + struct { + /** core1_can0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_can0_int_map:6; + /** core1_can0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_can0_int_src_pass_in_sec:1; + /** core1_can0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_can0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_can0_int_map_reg_t; + + +/** Group: CORE1 CAN1 INT MAP REG */ +/** Type of can1_int_map register + * NA + */ +typedef union { + struct { + /** core1_can1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_can1_int_map:6; + /** core1_can1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_can1_int_src_pass_in_sec:1; + /** core1_can1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_can1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_can1_int_map_reg_t; + + +/** Group: CORE1 CAN2 INT MAP REG */ +/** Type of can2_int_map register + * NA + */ +typedef union { + struct { + /** core1_can2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_can2_int_map:6; + /** core1_can2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_can2_int_src_pass_in_sec:1; + /** core1_can2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_can2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_can2_int_map_reg_t; + + +/** Group: CORE1 RMT INT MAP REG */ +/** Type of rmt_int_map register + * NA + */ +typedef union { + struct { + /** core1_rmt_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_rmt_int_map:6; + /** core1_rmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_rmt_int_src_pass_in_sec:1; + /** core1_rmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_rmt_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_rmt_int_map_reg_t; + + +/** Group: CORE1 I2C0 INT MAP REG */ +/** Type of i2c0_int_map register + * NA + */ +typedef union { + struct { + /** core1_i2c0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i2c0_int_map:6; + /** core1_i2c0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i2c0_int_src_pass_in_sec:1; + /** core1_i2c0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i2c0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i2c0_int_map_reg_t; + + +/** Group: CORE1 I2C1 INT MAP REG */ +/** Type of i2c1_int_map register + * NA + */ +typedef union { + struct { + /** core1_i2c1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i2c1_int_map:6; + /** core1_i2c1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i2c1_int_src_pass_in_sec:1; + /** core1_i2c1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i2c1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i2c1_int_map_reg_t; + + +/** Group: CORE1 TIMERGRP0 T0 INT MAP REG */ +/** Type of timergrp0_t0_int_map register + * NA + */ +typedef union { + struct { + /** core1_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_timergrp0_t0_int_map:6; + /** core1_timergrp0_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_timergrp0_t0_int_src_pass_in_sec:1; + /** core1_timergrp0_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_timergrp0_t0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_timergrp0_t0_int_map_reg_t; + + +/** Group: CORE1 TIMERGRP0 T1 INT MAP REG */ +/** Type of timergrp0_t1_int_map register + * NA + */ +typedef union { + struct { + /** core1_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_timergrp0_t1_int_map:6; + /** core1_timergrp0_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_timergrp0_t1_int_src_pass_in_sec:1; + /** core1_timergrp0_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_timergrp0_t1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_timergrp0_t1_int_map_reg_t; + + +/** Group: CORE1 TIMERGRP0 WDT INT MAP REG */ +/** Type of timergrp0_wdt_int_map register + * NA + */ +typedef union { + struct { + /** core1_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_timergrp0_wdt_int_map:6; + /** core1_timergrp0_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_timergrp0_wdt_int_src_pass_in_sec:1; + /** core1_timergrp0_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_timergrp0_wdt_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_timergrp0_wdt_int_map_reg_t; + + +/** Group: CORE1 TIMERGRP1 T0 INT MAP REG */ +/** Type of timergrp1_t0_int_map register + * NA + */ +typedef union { + struct { + /** core1_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_timergrp1_t0_int_map:6; + /** core1_timergrp1_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_timergrp1_t0_int_src_pass_in_sec:1; + /** core1_timergrp1_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_timergrp1_t0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_timergrp1_t0_int_map_reg_t; + + +/** Group: CORE1 TIMERGRP1 T1 INT MAP REG */ +/** Type of timergrp1_t1_int_map register + * NA + */ +typedef union { + struct { + /** core1_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_timergrp1_t1_int_map:6; + /** core1_timergrp1_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_timergrp1_t1_int_src_pass_in_sec:1; + /** core1_timergrp1_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_timergrp1_t1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_timergrp1_t1_int_map_reg_t; + + +/** Group: CORE1 TIMERGRP1 WDT INT MAP REG */ +/** Type of timergrp1_wdt_int_map register + * NA + */ +typedef union { + struct { + /** core1_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_timergrp1_wdt_int_map:6; + /** core1_timergrp1_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_timergrp1_wdt_int_src_pass_in_sec:1; + /** core1_timergrp1_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_timergrp1_wdt_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_timergrp1_wdt_int_map_reg_t; + + +/** Group: CORE1 LEDC INT MAP REG */ +/** Type of ledc_int_map register + * NA + */ +typedef union { + struct { + /** core1_ledc_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ledc_int_map:6; + /** core1_ledc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ledc_int_src_pass_in_sec:1; + /** core1_ledc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ledc_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ledc_int_map_reg_t; + + +/** Group: CORE1 SYSTIMER TARGET0 INT MAP REG */ +/** Type of systimer_target0_int_map register + * NA + */ +typedef union { + struct { + /** core1_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_systimer_target0_int_map:6; + /** core1_systimer_target0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_systimer_target0_int_src_pass_in_sec:1; + /** core1_systimer_target0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_systimer_target0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_systimer_target0_int_map_reg_t; + + +/** Group: CORE1 SYSTIMER TARGET1 INT MAP REG */ +/** Type of systimer_target1_int_map register + * NA + */ +typedef union { + struct { + /** core1_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_systimer_target1_int_map:6; + /** core1_systimer_target1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_systimer_target1_int_src_pass_in_sec:1; + /** core1_systimer_target1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_systimer_target1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_systimer_target1_int_map_reg_t; + + +/** Group: CORE1 SYSTIMER TARGET2 INT MAP REG */ +/** Type of systimer_target2_int_map register + * NA + */ +typedef union { + struct { + /** core1_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_systimer_target2_int_map:6; + /** core1_systimer_target2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_systimer_target2_int_src_pass_in_sec:1; + /** core1_systimer_target2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_systimer_target2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_systimer_target2_int_map_reg_t; + + +/** Group: CORE1 AHB PDMA IN CH0 INT MAP REG */ +/** Type of ahb_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ahb_pdma_in_ch0_int_map:6; + /** core1_ahb_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_in_ch0_int_src_pass_in_sec:1; + /** core1_ahb_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_in_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ahb_pdma_in_ch0_int_map_reg_t; + + +/** Group: CORE1 AHB PDMA IN CH1 INT MAP REG */ +/** Type of ahb_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ahb_pdma_in_ch1_int_map:6; + /** core1_ahb_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_in_ch1_int_src_pass_in_sec:1; + /** core1_ahb_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_in_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ahb_pdma_in_ch1_int_map_reg_t; + + +/** Group: CORE1 AHB PDMA IN CH2 INT MAP REG */ +/** Type of ahb_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ahb_pdma_in_ch2_int_map:6; + /** core1_ahb_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_in_ch2_int_src_pass_in_sec:1; + /** core1_ahb_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_in_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ahb_pdma_in_ch2_int_map_reg_t; + + +/** Group: CORE1 AHB PDMA OUT CH0 INT MAP REG */ +/** Type of ahb_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ahb_pdma_out_ch0_int_map:6; + /** core1_ahb_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_out_ch0_int_src_pass_in_sec:1; + /** core1_ahb_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_out_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ahb_pdma_out_ch0_int_map_reg_t; + + +/** Group: CORE1 AHB PDMA OUT CH1 INT MAP REG */ +/** Type of ahb_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ahb_pdma_out_ch1_int_map:6; + /** core1_ahb_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_out_ch1_int_src_pass_in_sec:1; + /** core1_ahb_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_out_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ahb_pdma_out_ch1_int_map_reg_t; + + +/** Group: CORE1 AHB PDMA OUT CH2 INT MAP REG */ +/** Type of ahb_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ahb_pdma_out_ch2_int_map:6; + /** core1_ahb_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_out_ch2_int_src_pass_in_sec:1; + /** core1_ahb_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ahb_pdma_out_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ahb_pdma_out_ch2_int_map_reg_t; + + +/** Group: CORE1 AXI PDMA IN CH0 INT MAP REG */ +/** Type of axi_pdma_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_pdma_in_ch0_int_map:6; + /** core1_axi_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_in_ch0_int_src_pass_in_sec:1; + /** core1_axi_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_in_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_pdma_in_ch0_int_map_reg_t; + + +/** Group: CORE1 AXI PDMA IN CH1 INT MAP REG */ +/** Type of axi_pdma_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_pdma_in_ch1_int_map:6; + /** core1_axi_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_in_ch1_int_src_pass_in_sec:1; + /** core1_axi_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_in_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_pdma_in_ch1_int_map_reg_t; + + +/** Group: CORE1 AXI PDMA IN CH2 INT MAP REG */ +/** Type of axi_pdma_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_pdma_in_ch2_int_map:6; + /** core1_axi_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_in_ch2_int_src_pass_in_sec:1; + /** core1_axi_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_in_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_pdma_in_ch2_int_map_reg_t; + + +/** Group: CORE1 AXI PDMA OUT CH0 INT MAP REG */ +/** Type of axi_pdma_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_pdma_out_ch0_int_map:6; + /** core1_axi_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_out_ch0_int_src_pass_in_sec:1; + /** core1_axi_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_out_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_pdma_out_ch0_int_map_reg_t; + + +/** Group: CORE1 AXI PDMA OUT CH1 INT MAP REG */ +/** Type of axi_pdma_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_pdma_out_ch1_int_map:6; + /** core1_axi_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_out_ch1_int_src_pass_in_sec:1; + /** core1_axi_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_out_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_pdma_out_ch1_int_map_reg_t; + + +/** Group: CORE1 AXI PDMA OUT CH2 INT MAP REG */ +/** Type of axi_pdma_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_pdma_out_ch2_int_map:6; + /** core1_axi_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_out_ch2_int_src_pass_in_sec:1; + /** core1_axi_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_pdma_out_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_pdma_out_ch2_int_map_reg_t; + + +/** Group: CORE1 RSA INT MAP REG */ +/** Type of rsa_int_map register + * NA + */ +typedef union { + struct { + /** core1_rsa_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_rsa_int_map:6; + /** core1_rsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_rsa_int_src_pass_in_sec:1; + /** core1_rsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_rsa_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_rsa_int_map_reg_t; + + +/** Group: CORE1 AES INT MAP REG */ +/** Type of aes_int_map register + * NA + */ +typedef union { + struct { + /** core1_aes_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_aes_int_map:6; + /** core1_aes_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_aes_int_src_pass_in_sec:1; + /** core1_aes_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_aes_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_aes_int_map_reg_t; + + +/** Group: CORE1 SHA INT MAP REG */ +/** Type of sha_int_map register + * NA + */ +typedef union { + struct { + /** core1_sha_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_sha_int_map:6; + /** core1_sha_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_sha_int_src_pass_in_sec:1; + /** core1_sha_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_sha_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_sha_int_map_reg_t; + + +/** Group: CORE1 ECC INT MAP REG */ +/** Type of ecc_int_map register + * NA + */ +typedef union { + struct { + /** core1_ecc_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ecc_int_map:6; + /** core1_ecc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ecc_int_src_pass_in_sec:1; + /** core1_ecc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ecc_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ecc_int_map_reg_t; + + +/** Group: CORE1 ECDSA INT MAP REG */ +/** Type of ecdsa_int_map register + * NA + */ +typedef union { + struct { + /** core1_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ecdsa_int_map:6; + /** core1_ecdsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ecdsa_int_src_pass_in_sec:1; + /** core1_ecdsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ecdsa_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ecdsa_int_map_reg_t; + + +/** Group: CORE1 KM INT MAP REG */ +/** Type of km_int_map register + * NA + */ +typedef union { + struct { + /** core1_km_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_km_int_map:6; + /** core1_km_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_km_int_src_pass_in_sec:1; + /** core1_km_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_km_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_km_int_map_reg_t; + + +/** Group: CORE1 GPIO INT0 MAP REG */ +/** Type of gpio_int0_map register + * NA + */ +typedef union { + struct { + /** core1_gpio_int0_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gpio_int0_map:6; + /** core1_gpio_int0_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gpio_int0_src_pass_in_sec:1; + /** core1_gpio_int0_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gpio_int0_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gpio_int0_map_reg_t; + + +/** Group: CORE1 GPIO INT1 MAP REG */ +/** Type of gpio_int1_map register + * NA + */ +typedef union { + struct { + /** core1_gpio_int1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gpio_int1_map:6; + /** core1_gpio_int1_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gpio_int1_src_pass_in_sec:1; + /** core1_gpio_int1_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gpio_int1_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gpio_int1_map_reg_t; + + +/** Group: CORE1 GPIO INT2 MAP REG */ +/** Type of gpio_int2_map register + * NA + */ +typedef union { + struct { + /** core1_gpio_int2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gpio_int2_map:6; + /** core1_gpio_int2_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gpio_int2_src_pass_in_sec:1; + /** core1_gpio_int2_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gpio_int2_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gpio_int2_map_reg_t; + + +/** Group: CORE1 GPIO INT3 MAP REG */ +/** Type of gpio_int3_map register + * NA + */ +typedef union { + struct { + /** core1_gpio_int3_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gpio_int3_map:6; + /** core1_gpio_int3_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gpio_int3_src_pass_in_sec:1; + /** core1_gpio_int3_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gpio_int3_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gpio_int3_map_reg_t; + + +/** Group: CORE1 GPIO PAD COMP INT MAP REG */ +/** Type of gpio_pad_comp_int_map register + * NA + */ +typedef union { + struct { + /** core1_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gpio_pad_comp_int_map:6; + /** core1_gpio_pad_comp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gpio_pad_comp_int_src_pass_in_sec:1; + /** core1_gpio_pad_comp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gpio_pad_comp_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gpio_pad_comp_int_map_reg_t; + + +/** Group: CORE1 CPU INT FROM CPU 0 MAP REG */ +/** Type of cpu_int_from_cpu_0_map register + * NA + */ +typedef union { + struct { + /** core1_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_cpu_int_from_cpu_0_map:6; + /** core1_cpu_int_from_cpu_0_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_0_src_pass_in_sec:1; + /** core1_cpu_int_from_cpu_0_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_0_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_cpu_int_from_cpu_0_map_reg_t; + + +/** Group: CORE1 CPU INT FROM CPU 1 MAP REG */ +/** Type of cpu_int_from_cpu_1_map register + * NA + */ +typedef union { + struct { + /** core1_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_cpu_int_from_cpu_1_map:6; + /** core1_cpu_int_from_cpu_1_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_1_src_pass_in_sec:1; + /** core1_cpu_int_from_cpu_1_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_1_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_cpu_int_from_cpu_1_map_reg_t; + + +/** Group: CORE1 CPU INT FROM CPU 2 MAP REG */ +/** Type of cpu_int_from_cpu_2_map register + * NA + */ +typedef union { + struct { + /** core1_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_cpu_int_from_cpu_2_map:6; + /** core1_cpu_int_from_cpu_2_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_2_src_pass_in_sec:1; + /** core1_cpu_int_from_cpu_2_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_2_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_cpu_int_from_cpu_2_map_reg_t; + + +/** Group: CORE1 CPU INT FROM CPU 3 MAP REG */ +/** Type of cpu_int_from_cpu_3_map register + * NA + */ +typedef union { + struct { + /** core1_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_cpu_int_from_cpu_3_map:6; + /** core1_cpu_int_from_cpu_3_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_3_src_pass_in_sec:1; + /** core1_cpu_int_from_cpu_3_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_cpu_int_from_cpu_3_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_cpu_int_from_cpu_3_map_reg_t; + + +/** Group: CORE1 CACHE INT MAP REG */ +/** Type of cache_int_map register + * NA + */ +typedef union { + struct { + /** core1_cache_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_cache_int_map:6; + /** core1_cache_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_cache_int_src_pass_in_sec:1; + /** core1_cache_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_cache_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_cache_int_map_reg_t; + + +/** Group: CORE1 FLASH MSPI INT MAP REG */ +/** Type of flash_mspi_int_map register + * NA + */ +typedef union { + struct { + /** core1_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_flash_mspi_int_map:6; + /** core1_flash_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_flash_mspi_int_src_pass_in_sec:1; + /** core1_flash_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_flash_mspi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_flash_mspi_int_map_reg_t; + + +/** Group: CORE1 CSI BRIDGE INT MAP REG */ +/** Type of csi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** core1_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_csi_bridge_int_map:6; + /** core1_csi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_csi_bridge_int_src_pass_in_sec:1; + /** core1_csi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_csi_bridge_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_csi_bridge_int_map_reg_t; + + +/** Group: CORE1 DSI BRIDGE INT MAP REG */ +/** Type of dsi_bridge_int_map register + * NA + */ +typedef union { + struct { + /** core1_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dsi_bridge_int_map:6; + /** core1_dsi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dsi_bridge_int_src_pass_in_sec:1; + /** core1_dsi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dsi_bridge_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dsi_bridge_int_map_reg_t; + + +/** Group: CORE1 CSI INT MAP REG */ +/** Type of csi_int_map register + * NA + */ +typedef union { + struct { + /** core1_csi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_csi_int_map:6; + /** core1_csi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_csi_int_src_pass_in_sec:1; + /** core1_csi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_csi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_csi_int_map_reg_t; + + +/** Group: CORE1 DSI INT MAP REG */ +/** Type of dsi_int_map register + * NA + */ +typedef union { + struct { + /** core1_dsi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dsi_int_map:6; + /** core1_dsi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dsi_int_src_pass_in_sec:1; + /** core1_dsi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dsi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dsi_int_map_reg_t; + + +/** Group: CORE1 GMII PHY INT MAP REG */ +/** Type of gmii_phy_int_map register + * NA + */ +typedef union { + struct { + /** core1_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_gmii_phy_int_map:6; + /** core1_gmii_phy_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_gmii_phy_int_src_pass_in_sec:1; + /** core1_gmii_phy_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_gmii_phy_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_gmii_phy_int_map_reg_t; + + +/** Group: CORE1 LPI INT MAP REG */ +/** Type of lpi_int_map register + * NA + */ +typedef union { + struct { + /** core1_lpi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_lpi_int_map:6; + /** core1_lpi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_lpi_int_src_pass_in_sec:1; + /** core1_lpi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_lpi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_lpi_int_map_reg_t; + + +/** Group: CORE1 PMT INT MAP REG */ +/** Type of pmt_int_map register + * NA + */ +typedef union { + struct { + /** core1_pmt_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_pmt_int_map:6; + /** core1_pmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_pmt_int_src_pass_in_sec:1; + /** core1_pmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_pmt_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_pmt_int_map_reg_t; + + +/** Group: CORE1 SBD INT MAP REG */ +/** Type of sbd_int_map register + * NA + */ +typedef union { + struct { + /** core1_sbd_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_sbd_int_map:6; + /** core1_sbd_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_sbd_int_src_pass_in_sec:1; + /** core1_sbd_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_sbd_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_sbd_int_map_reg_t; + + +/** Group: CORE1 USB OTG INT MAP REG */ +/** Type of usb_otg_int_map register + * NA + */ +typedef union { + struct { + /** core1_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_usb_otg_int_map:6; + /** core1_usb_otg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_usb_otg_int_src_pass_in_sec:1; + /** core1_usb_otg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_usb_otg_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_usb_otg_int_map_reg_t; + + +/** Group: CORE1 USB OTG ENDP MULTI PROC INT MAP REG */ +/** Type of usb_otg_endp_multi_proc_int_map register + * NA + */ +typedef union { + struct { + /** core1_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_usb_otg_endp_multi_proc_int_map:6; + /** core1_usb_otg_endp_multi_proc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_usb_otg_endp_multi_proc_int_src_pass_in_sec:1; + /** core1_usb_otg_endp_multi_proc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_usb_otg_endp_multi_proc_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_usb_otg_endp_multi_proc_int_map_reg_t; + + +/** Group: CORE1 JPEG INT MAP REG */ +/** Type of jpeg_int_map register + * NA + */ +typedef union { + struct { + /** core1_jpeg_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_jpeg_int_map:6; + /** core1_jpeg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_jpeg_int_src_pass_in_sec:1; + /** core1_jpeg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_jpeg_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_jpeg_int_map_reg_t; + + +/** Group: CORE1 PPA INT MAP REG */ +/** Type of ppa_int_map register + * NA + */ +typedef union { + struct { + /** core1_ppa_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_ppa_int_map:6; + /** core1_ppa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_ppa_int_src_pass_in_sec:1; + /** core1_ppa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_ppa_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_ppa_int_map_reg_t; + + +/** Group: CORE1 CORE0 TRACE INT MAP REG */ +/** Type of core0_trace_int_map register + * NA + */ +typedef union { + struct { + /** core1_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_core0_trace_int_map:6; + /** core1_core0_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_core0_trace_int_src_pass_in_sec:1; + /** core1_core0_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_core0_trace_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_core0_trace_int_map_reg_t; + + +/** Group: CORE1 CORE1 TRACE INT MAP REG */ +/** Type of core1_trace_int_map register + * NA + */ +typedef union { + struct { + /** core1_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_core1_trace_int_map:6; + /** core1_core1_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_core1_trace_int_src_pass_in_sec:1; + /** core1_core1_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_core1_trace_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_core1_trace_int_map_reg_t; + + +/** Group: CORE1 HP CORE CTRL INT MAP REG */ +/** Type of hp_core_ctrl_int_map register + * NA + */ +typedef union { + struct { + /** core1_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_hp_core_ctrl_int_map:6; + /** core1_hp_core_ctrl_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_hp_core_ctrl_int_src_pass_in_sec:1; + /** core1_hp_core_ctrl_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_hp_core_ctrl_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_hp_core_ctrl_int_map_reg_t; + + +/** Group: CORE1 ISP INT MAP REG */ +/** Type of isp_int_map register + * NA + */ +typedef union { + struct { + /** core1_isp_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_isp_int_map:6; + /** core1_isp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_isp_int_src_pass_in_sec:1; + /** core1_isp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_isp_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_isp_int_map_reg_t; + + +/** Group: CORE1 I3C MST INT MAP REG */ +/** Type of i3c_mst_int_map register + * NA + */ +typedef union { + struct { + /** core1_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i3c_mst_int_map:6; + /** core1_i3c_mst_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i3c_mst_int_src_pass_in_sec:1; + /** core1_i3c_mst_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i3c_mst_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i3c_mst_int_map_reg_t; + + +/** Group: CORE1 I3C SLV INT MAP REG */ +/** Type of i3c_slv_int_map register + * NA + */ +typedef union { + struct { + /** core1_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_i3c_slv_int_map:6; + /** core1_i3c_slv_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_i3c_slv_int_src_pass_in_sec:1; + /** core1_i3c_slv_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_i3c_slv_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_i3c_slv_int_map_reg_t; + + +/** Group: CORE1 USB OTG11 INT MAP REG */ +/** Type of usb_otg11_int_map register + * NA + */ +typedef union { + struct { + /** core1_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_usb_otg11_int_map:6; + /** core1_usb_otg11_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_usb_otg11_int_src_pass_in_sec:1; + /** core1_usb_otg11_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_usb_otg11_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_usb_otg11_int_map_reg_t; + + +/** Group: CORE1 DMA2D IN CH0 INT MAP REG */ +/** Type of dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_in_ch0_int_map:6; + /** core1_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_in_ch0_int_src_pass_in_sec:1; + /** core1_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_in_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_in_ch0_int_map_reg_t; + + +/** Group: CORE1 DMA2D IN CH1 INT MAP REG */ +/** Type of dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_in_ch1_int_map:6; + /** core1_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_in_ch1_int_src_pass_in_sec:1; + /** core1_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_in_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_in_ch1_int_map_reg_t; + + +/** Group: CORE1 DMA2D OUT CH0 INT MAP REG */ +/** Type of dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_out_ch0_int_map:6; + /** core1_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch0_int_src_pass_in_sec:1; + /** core1_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_out_ch0_int_map_reg_t; + + +/** Group: CORE1 DMA2D OUT CH1 INT MAP REG */ +/** Type of dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_out_ch1_int_map:6; + /** core1_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch1_int_src_pass_in_sec:1; + /** core1_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_out_ch1_int_map_reg_t; + + +/** Group: CORE1 DMA2D OUT CH2 INT MAP REG */ +/** Type of dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_out_ch2_int_map:6; + /** core1_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch2_int_src_pass_in_sec:1; + /** core1_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_out_ch2_int_map_reg_t; + + +/** Group: CORE1 PSRAM MSPI INT MAP REG */ +/** Type of psram_mspi_int_map register + * NA + */ +typedef union { + struct { + /** core1_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_psram_mspi_int_map:6; + /** core1_psram_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_psram_mspi_int_src_pass_in_sec:1; + /** core1_psram_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_psram_mspi_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_psram_mspi_int_map_reg_t; + + +/** Group: CORE1 HP SYSREG INT MAP REG */ +/** Type of hp_sysreg_int_map register + * NA + */ +typedef union { + struct { + /** core1_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_hp_sysreg_int_map:6; + /** core1_hp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_hp_sysreg_int_src_pass_in_sec:1; + /** core1_hp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_hp_sysreg_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_hp_sysreg_int_map_reg_t; + + +/** Group: CORE1 PCNT INT MAP REG */ +/** Type of pcnt_int_map register + * NA + */ +typedef union { + struct { + /** core1_pcnt_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_pcnt_int_map:6; + /** core1_pcnt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_pcnt_int_src_pass_in_sec:1; + /** core1_pcnt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_pcnt_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_pcnt_int_map_reg_t; + + +/** Group: CORE1 HP PAU INT MAP REG */ +/** Type of hp_pau_int_map register + * NA + */ +typedef union { + struct { + /** core1_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_hp_pau_int_map:6; + /** core1_hp_pau_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_hp_pau_int_src_pass_in_sec:1; + /** core1_hp_pau_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_hp_pau_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_hp_pau_int_map_reg_t; + + +/** Group: CORE1 HP PARLIO RX INT MAP REG */ +/** Type of hp_parlio_rx_int_map register + * NA + */ +typedef union { + struct { + /** core1_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_hp_parlio_rx_int_map:6; + /** core1_hp_parlio_rx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_hp_parlio_rx_int_src_pass_in_sec:1; + /** core1_hp_parlio_rx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_hp_parlio_rx_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_hp_parlio_rx_int_map_reg_t; + + +/** Group: CORE1 HP PARLIO TX INT MAP REG */ +/** Type of hp_parlio_tx_int_map register + * NA + */ +typedef union { + struct { + /** core1_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_hp_parlio_tx_int_map:6; + /** core1_hp_parlio_tx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_hp_parlio_tx_int_src_pass_in_sec:1; + /** core1_hp_parlio_tx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_hp_parlio_tx_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_hp_parlio_tx_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D OUT CH0 INT MAP REG */ +/** Type of h264_dma2d_out_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_out_ch0_int_map:6; + /** core1_h264_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch0_int_src_pass_in_sec:1; + /** core1_h264_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_out_ch0_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D OUT CH1 INT MAP REG */ +/** Type of h264_dma2d_out_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_out_ch1_int_map:6; + /** core1_h264_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch1_int_src_pass_in_sec:1; + /** core1_h264_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_out_ch1_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D OUT CH2 INT MAP REG */ +/** Type of h264_dma2d_out_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_out_ch2_int_map:6; + /** core1_h264_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch2_int_src_pass_in_sec:1; + /** core1_h264_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_out_ch2_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D OUT CH3 INT MAP REG */ +/** Type of h264_dma2d_out_ch3_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_out_ch3_int_map:6; + /** core1_h264_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch3_int_src_pass_in_sec:1; + /** core1_h264_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch3_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_out_ch3_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D OUT CH4 INT MAP REG */ +/** Type of h264_dma2d_out_ch4_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_out_ch4_int_map:6; + /** core1_h264_dma2d_out_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch4_int_src_pass_in_sec:1; + /** core1_h264_dma2d_out_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_out_ch4_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_out_ch4_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D IN CH0 INT MAP REG */ +/** Type of h264_dma2d_in_ch0_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_in_ch0_int_map:6; + /** core1_h264_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch0_int_src_pass_in_sec:1; + /** core1_h264_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch0_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_in_ch0_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D IN CH1 INT MAP REG */ +/** Type of h264_dma2d_in_ch1_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_in_ch1_int_map:6; + /** core1_h264_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch1_int_src_pass_in_sec:1; + /** core1_h264_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch1_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_in_ch1_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D IN CH2 INT MAP REG */ +/** Type of h264_dma2d_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_in_ch2_int_map:6; + /** core1_h264_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch2_int_src_pass_in_sec:1; + /** core1_h264_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_in_ch2_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D IN CH3 INT MAP REG */ +/** Type of h264_dma2d_in_ch3_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_in_ch3_int_map:6; + /** core1_h264_dma2d_in_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch3_int_src_pass_in_sec:1; + /** core1_h264_dma2d_in_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch3_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_in_ch3_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D IN CH4 INT MAP REG */ +/** Type of h264_dma2d_in_ch4_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_in_ch4_int_map:6; + /** core1_h264_dma2d_in_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch4_int_src_pass_in_sec:1; + /** core1_h264_dma2d_in_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch4_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_in_ch4_int_map_reg_t; + + +/** Group: CORE1 H264 DMA2D IN CH5 INT MAP REG */ +/** Type of h264_dma2d_in_ch5_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_dma2d_in_ch5_int_map:6; + /** core1_h264_dma2d_in_ch5_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch5_int_src_pass_in_sec:1; + /** core1_h264_dma2d_in_ch5_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_dma2d_in_ch5_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_dma2d_in_ch5_int_map_reg_t; + + +/** Group: CORE1 H264 REG INT MAP REG */ +/** Type of h264_reg_int_map register + * NA + */ +typedef union { + struct { + /** core1_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_h264_reg_int_map:6; + /** core1_h264_reg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_h264_reg_int_src_pass_in_sec:1; + /** core1_h264_reg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_h264_reg_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_h264_reg_int_map_reg_t; + + +/** Group: CORE1 ASSIST DEBUG INT MAP REG */ +/** Type of assist_debug_int_map register + * NA + */ +typedef union { + struct { + /** core1_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_assist_debug_int_map:6; + /** core1_assist_debug_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_assist_debug_int_src_pass_in_sec:1; + /** core1_assist_debug_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_assist_debug_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_assist_debug_int_map_reg_t; + + +/** Group: CORE1 INTR STATUS REG 0 REG */ +/** Type of intr_status_reg_0 register + * NA + */ +typedef union { + struct { + /** core1_intr_status_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_status_0:32; + }; + uint32_t val; +} core1_intr_status_reg_0_reg_t; + + +/** Group: CORE1 INTR STATUS REG 1 REG */ +/** Type of intr_status_reg_1 register + * NA + */ +typedef union { + struct { + /** core1_intr_status_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_status_1:32; + }; + uint32_t val; +} core1_intr_status_reg_1_reg_t; + + +/** Group: CORE1 INTR STATUS REG 2 REG */ +/** Type of intr_status_reg_2 register + * NA + */ +typedef union { + struct { + /** core1_intr_status_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_status_2:32; + }; + uint32_t val; +} core1_intr_status_reg_2_reg_t; + + +/** Group: CORE1 INTR STATUS REG 3 REG */ +/** Type of intr_status_reg_3 register + * NA + */ +typedef union { + struct { + /** core1_intr_status_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_status_3:32; + }; + uint32_t val; +} core1_intr_status_reg_3_reg_t; + + +/** Group: CORE1 CLOCK GATE REG */ +/** Type of clock_gate register + * NA + */ +typedef union { + struct { + /** core1_reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t core1_reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} core1_clock_gate_reg_t; + + +/** Group: CORE1 DMA2D IN CH2 INT MAP REG */ +/** Type of dma2d_in_ch2_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_in_ch2_int_map:6; + /** core1_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_in_ch2_int_src_pass_in_sec:1; + /** core1_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_in_ch2_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_in_ch2_int_map_reg_t; + + +/** Group: CORE1 DMA2D OUT CH3 INT MAP REG */ +/** Type of dma2d_out_ch3_int_map register + * NA + */ +typedef union { + struct { + /** core1_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_dma2d_out_ch3_int_map:6; + /** core1_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch3_int_src_pass_in_sec:1; + /** core1_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_dma2d_out_ch3_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_dma2d_out_ch3_int_map_reg_t; + + +/** Group: CORE1 AXI PERF MON INT MAP REG */ +/** Type of axi_perf_mon_int_map register + * NA + */ +typedef union { + struct { + /** core1_axi_perf_mon_int_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_axi_perf_mon_int_map:6; + /** core1_axi_perf_mon_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0; + * NA + */ + uint32_t core1_axi_perf_mon_int_src_pass_in_sec:1; + /** core1_axi_perf_mon_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0; + * NA + */ + uint32_t core1_axi_perf_mon_int_src_in_sec_flag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} core1_axi_perf_mon_int_map_reg_t; + + +/** Group: CORE1 INTR STATUS REG 4 REG */ +/** Type of intr_status_reg_4 register + * NA + */ +typedef union { + struct { + /** core1_intr_status_4 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_status_4:32; + }; + uint32_t val; +} core1_intr_status_reg_4_reg_t; + + +/** Group: CORE1 INTR SIG IDX ASSERT IN SEC REG */ +/** Type of intr_sig_idx_assert_in_sec register + * NA + */ +typedef union { + struct { + /** core1_intr_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0; + * NA + */ + uint32_t core1_intr_sig_idx_assert_in_sec:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} core1_intr_sig_idx_assert_in_sec_reg_t; + + +/** Group: CORE1 INTR SEC STATUS REG */ +/** Type of intr_sec_status register + * NA + */ +typedef union { + struct { + /** core1_intr_sec_status : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_sec_status:32; + }; + uint32_t val; +} core1_intr_sec_status_reg_t; + + +/** Group: CORE1 INTR SRC PASS IN SEC STATUS 0 REG */ +/** Type of intr_src_pass_in_sec_status_0 register + * NA + */ +typedef union { + struct { + /** core1_intr_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_src_pass_in_sec_status_0:32; + }; + uint32_t val; +} core1_intr_src_pass_in_sec_status_0_reg_t; + + +/** Group: CORE1 INTR SRC PASS IN SEC STATUS 1 REG */ +/** Type of intr_src_pass_in_sec_status_1 register + * NA + */ +typedef union { + struct { + /** core1_intr_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_src_pass_in_sec_status_1:32; + }; + uint32_t val; +} core1_intr_src_pass_in_sec_status_1_reg_t; + + +/** Group: CORE1 INTR SRC PASS IN SEC STATUS 2 REG */ +/** Type of intr_src_pass_in_sec_status_2 register + * NA + */ +typedef union { + struct { + /** core1_intr_src_pass_in_sec_status_2 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_src_pass_in_sec_status_2:32; + }; + uint32_t val; +} core1_intr_src_pass_in_sec_status_2_reg_t; + + +/** Group: CORE1 INTR SRC PASS IN SEC STATUS 3 REG */ +/** Type of intr_src_pass_in_sec_status_3 register + * NA + */ +typedef union { + struct { + /** core1_intr_src_pass_in_sec_status_3 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_src_pass_in_sec_status_3:32; + }; + uint32_t val; +} core1_intr_src_pass_in_sec_status_3_reg_t; + + +/** Group: CORE1 INTR SRC PASS IN SEC STATUS 4 REG */ +/** Type of intr_src_pass_in_sec_status_4 register + * NA + */ +typedef union { + struct { + /** core1_intr_src_pass_in_sec_status_4 : RO; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t core1_intr_src_pass_in_sec_status_4:32; + }; + uint32_t val; +} core1_intr_src_pass_in_sec_status_4_reg_t; + + +/** Group: CORE1 INTERRUPT REG DATE REG */ +/** Type of interrupt_reg_date register + * NA + */ +typedef union { + struct { + /** core1_interrupt_reg_date : R/W; bitpos: [27:0]; default: 38806144; + * NA + */ + uint32_t core1_interrupt_reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} core1_interrupt_reg_date_reg_t; + + +typedef struct { + volatile core1_lp_rtc_int_map_reg_t lp_rtc_int_map; + volatile core1_lp_wdt_int_map_reg_t lp_wdt_int_map; + volatile core1_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map; + volatile core1_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map; + volatile core1_mb_hp_int_map_reg_t mb_hp_int_map; + volatile core1_mb_lp_int_map_reg_t mb_lp_int_map; + volatile core1_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map; + volatile core1_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map; + volatile core1_lp_anaperi_int_map_reg_t lp_anaperi_int_map; + volatile core1_lp_adc_int_map_reg_t lp_adc_int_map; + volatile core1_lp_gpio_int_map_reg_t lp_gpio_int_map; + volatile core1_lp_i2c_int_map_reg_t lp_i2c_int_map; + volatile core1_lp_i2s_int_map_reg_t lp_i2s_int_map; + volatile core1_lp_spi_int_map_reg_t lp_spi_int_map; + volatile core1_lp_touch_int_map_reg_t lp_touch_int_map; + volatile core1_lp_tsens_int_map_reg_t lp_tsens_int_map; + volatile core1_lp_uart_int_map_reg_t lp_uart_int_map; + volatile core1_lp_efuse_int_map_reg_t lp_efuse_int_map; + volatile core1_lp_sw_int_map_reg_t lp_sw_int_map; + volatile core1_lp_sysreg_int_map_reg_t lp_sysreg_int_map; + volatile core1_lp_huk_int_map_reg_t lp_huk_int_map; + volatile core1_sys_icm_int_map_reg_t sys_icm_int_map; + volatile core1_usb_device_int_map_reg_t usb_device_int_map; + volatile core1_sdio_host_int_map_reg_t sdio_host_int_map; + volatile core1_gdma_int_map_reg_t gdma_int_map; + volatile core1_spi2_int_map_reg_t spi2_int_map; + volatile core1_spi3_int_map_reg_t spi3_int_map; + volatile core1_i2s0_int_map_reg_t i2s0_int_map; + volatile core1_i2s1_int_map_reg_t i2s1_int_map; + volatile core1_i2s2_int_map_reg_t i2s2_int_map; + volatile core1_uhci0_int_map_reg_t uhci0_int_map; + volatile core1_uart0_int_map_reg_t uart0_int_map; + volatile core1_uart1_int_map_reg_t uart1_int_map; + volatile core1_uart2_int_map_reg_t uart2_int_map; + volatile core1_uart3_int_map_reg_t uart3_int_map; + volatile core1_uart4_int_map_reg_t uart4_int_map; + volatile core1_lcd_cam_int_map_reg_t lcd_cam_int_map; + volatile core1_adc_int_map_reg_t adc_int_map; + volatile core1_pwm0_int_map_reg_t pwm0_int_map; + volatile core1_pwm1_int_map_reg_t pwm1_int_map; + volatile core1_can0_int_map_reg_t can0_int_map; + volatile core1_can1_int_map_reg_t can1_int_map; + volatile core1_can2_int_map_reg_t can2_int_map; + volatile core1_rmt_int_map_reg_t rmt_int_map; + volatile core1_i2c0_int_map_reg_t i2c0_int_map; + volatile core1_i2c1_int_map_reg_t i2c1_int_map; + volatile core1_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map; + volatile core1_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map; + volatile core1_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map; + volatile core1_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map; + volatile core1_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map; + volatile core1_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map; + volatile core1_ledc_int_map_reg_t ledc_int_map; + volatile core1_systimer_target0_int_map_reg_t systimer_target0_int_map; + volatile core1_systimer_target1_int_map_reg_t systimer_target1_int_map; + volatile core1_systimer_target2_int_map_reg_t systimer_target2_int_map; + volatile core1_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map; + volatile core1_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map; + volatile core1_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map; + volatile core1_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map; + volatile core1_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map; + volatile core1_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map; + volatile core1_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map; + volatile core1_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map; + volatile core1_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map; + volatile core1_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map; + volatile core1_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map; + volatile core1_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map; + volatile core1_rsa_int_map_reg_t rsa_int_map; + volatile core1_aes_int_map_reg_t aes_int_map; + volatile core1_sha_int_map_reg_t sha_int_map; + volatile core1_ecc_int_map_reg_t ecc_int_map; + volatile core1_ecdsa_int_map_reg_t ecdsa_int_map; + volatile core1_km_int_map_reg_t km_int_map; + volatile core1_gpio_int0_map_reg_t gpio_int0_map; + volatile core1_gpio_int1_map_reg_t gpio_int1_map; + volatile core1_gpio_int2_map_reg_t gpio_int2_map; + volatile core1_gpio_int3_map_reg_t gpio_int3_map; + volatile core1_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map; + volatile core1_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map; + volatile core1_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map; + volatile core1_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map; + volatile core1_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map; + volatile core1_cache_int_map_reg_t cache_int_map; + volatile core1_flash_mspi_int_map_reg_t flash_mspi_int_map; + volatile core1_csi_bridge_int_map_reg_t csi_bridge_int_map; + volatile core1_dsi_bridge_int_map_reg_t dsi_bridge_int_map; + volatile core1_csi_int_map_reg_t csi_int_map; + volatile core1_dsi_int_map_reg_t dsi_int_map; + volatile core1_gmii_phy_int_map_reg_t gmii_phy_int_map; + volatile core1_lpi_int_map_reg_t lpi_int_map; + volatile core1_pmt_int_map_reg_t pmt_int_map; + volatile core1_sbd_int_map_reg_t sbd_int_map; + volatile core1_usb_otg_int_map_reg_t usb_otg_int_map; + volatile core1_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map; + volatile core1_jpeg_int_map_reg_t jpeg_int_map; + volatile core1_ppa_int_map_reg_t ppa_int_map; + volatile core1_core0_trace_int_map_reg_t core0_trace_int_map; + volatile core1_core1_trace_int_map_reg_t core1_trace_int_map; + volatile core1_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map; + volatile core1_isp_int_map_reg_t isp_int_map; + volatile core1_i3c_mst_int_map_reg_t i3c_mst_int_map; + volatile core1_i3c_slv_int_map_reg_t i3c_slv_int_map; + volatile core1_usb_otg11_int_map_reg_t usb_otg11_int_map; + volatile core1_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map; + volatile core1_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map; + volatile core1_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map; + volatile core1_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map; + volatile core1_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map; + volatile core1_psram_mspi_int_map_reg_t psram_mspi_int_map; + volatile core1_hp_sysreg_int_map_reg_t hp_sysreg_int_map; + volatile core1_pcnt_int_map_reg_t pcnt_int_map; + volatile core1_hp_pau_int_map_reg_t hp_pau_int_map; + volatile core1_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map; + volatile core1_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map; + volatile core1_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map; + volatile core1_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map; + volatile core1_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map; + volatile core1_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map; + volatile core1_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map; + volatile core1_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map; + volatile core1_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map; + volatile core1_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map; + volatile core1_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map; + volatile core1_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map; + volatile core1_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map; + volatile core1_h264_reg_int_map_reg_t h264_reg_int_map; + volatile core1_assist_debug_int_map_reg_t assist_debug_int_map; + volatile core1_intr_status_reg_0_reg_t intr_status_reg_0; + volatile core1_intr_status_reg_1_reg_t intr_status_reg_1; + volatile core1_intr_status_reg_2_reg_t intr_status_reg_2; + volatile core1_intr_status_reg_3_reg_t intr_status_reg_3; + volatile core1_clock_gate_reg_t clock_gate; + volatile core1_dma2d_in_ch2_int_map_reg_t dma2d_in_ch2_int_map; + volatile core1_dma2d_out_ch3_int_map_reg_t dma2d_out_ch3_int_map; + volatile core1_axi_perf_mon_int_map_reg_t axi_perf_mon_int_map; + volatile core1_intr_status_reg_4_reg_t intr_status_reg_4; + uint32_t reserved_224; + volatile core1_intr_sig_idx_assert_in_sec_reg_t intr_sig_idx_assert_in_sec; + volatile core1_intr_sec_status_reg_t intr_sec_status; + volatile core1_intr_src_pass_in_sec_status_0_reg_t intr_src_pass_in_sec_status_0; + volatile core1_intr_src_pass_in_sec_status_1_reg_t intr_src_pass_in_sec_status_1; + volatile core1_intr_src_pass_in_sec_status_2_reg_t intr_src_pass_in_sec_status_2; + volatile core1_intr_src_pass_in_sec_status_3_reg_t intr_src_pass_in_sec_status_3; + volatile core1_intr_src_pass_in_sec_status_4_reg_t intr_src_pass_in_sec_status_4; + uint32_t reserved_244[110]; + volatile core1_interrupt_reg_date_reg_t interrupt_reg_date; +} core1_dev_t; + +extern core1_dev_t INTR_CORE0; + +#ifndef __cplusplus +_Static_assert(sizeof(core1_dev_t) == 0x400, "Invalid size of core1_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/interrupts.h b/components/soc/esp32p4/register/hw_ver2/soc/interrupts.h new file mode 100644 index 0000000000..2b03a849a4 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/interrupts.h @@ -0,0 +1,157 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_LP_RTC_INT_SOURCE, + ETS_LP_WDT_INT_SOURCE, + ETS_LP_TIMER_REG_0_INT_SOURCE, + ETS_LP_TIMER_REG_1_INT_SOURCE, + ETS_MB_HP_INT_SOURCE, + ETS_MB_LP_INT_SOURCE, + ETS_PMU_REG_0_INT_SOURCE, + ETS_PMU_REG_1_INT_SOURCE, + ETS_LP_ANAPERI_INT_SOURCE, + ETS_LP_ADC_INT_SOURCE, + ETS_LP_GPIO_INT_SOURCE, + ETS_LP_I2C_INT_SOURCE, + ETS_LP_I2S_INT_SOURCE, + ETS_LP_SPI_INT_SOURCE, + ETS_LP_TOUCH_INT_SOURCE, + ETS_LP_TSENS_INT_SOURCE, + ETS_LP_UART_INT_SOURCE, + ETS_LP_EFUSE_INT_SOURCE, + ETS_LP_SW_INT_SOURCE, + ETS_LP_SYSREG_INT_SOURCE, + ETS_LP_HUK_INT_SOURCE, + ETS_SYS_ICM_INT_SOURCE, + ETS_USB_DEVICE_INT_SOURCE, + ETS_SDIO_HOST_INT_SOURCE, + ETS_GDMA_INT_SOURCE, + ETS_SPI2_INT_SOURCE, + ETS_SPI3_INT_SOURCE, + ETS_I2S0_INT_SOURCE, + ETS_I2S1_INT_SOURCE, + ETS_I2S2_INT_SOURCE, + ETS_UHCI0_INT_SOURCE, + ETS_UART0_INT_SOURCE, + ETS_UART1_INT_SOURCE, + ETS_UART2_INT_SOURCE, + ETS_UART3_INT_SOURCE, + ETS_UART4_INT_SOURCE, + ETS_LCD_CAM_INT_SOURCE, + ETS_ADC_INT_SOURCE, + ETS_PWM0_INT_SOURCE, + ETS_PWM1_INT_SOURCE, + ETS_TWAI0_INT_SOURCE, + ETS_TWAI1_INT_SOURCE, + ETS_TWAI2_INT_SOURCE, + ETS_RMT_INT_SOURCE, + ETS_I2C0_INT_SOURCE, + ETS_I2C1_INT_SOURCE, + ETS_TIMERGRP0_T0_INT_SOURCE, + ETS_TIMERGRP0_T1_INT_SOURCE, + ETS_TIMERGRP0_WDT_INT_SOURCE, + ETS_TIMERGRP1_T0_INT_SOURCE, + ETS_TIMERGRP1_T1_INT_SOURCE, + ETS_TIMERGRP1_WDT_INT_SOURCE, + ETS_LEDC_INT_SOURCE, + ETS_SYSTIMER_TARGET0_INT_SOURCE, + ETS_SYSTIMER_TARGET1_INT_SOURCE, + ETS_SYSTIMER_TARGET2_INT_SOURCE, + ETS_AHB_PDMA_IN_CH0_INT_SOURCE, + ETS_AHB_PDMA_IN_CH1_INT_SOURCE, + ETS_AHB_PDMA_IN_CH2_INT_SOURCE, + ETS_AHB_PDMA_OUT_CH0_INT_SOURCE, + ETS_AHB_PDMA_OUT_CH1_INT_SOURCE, + ETS_AHB_PDMA_OUT_CH2_INT_SOURCE, + ETS_AXI_PDMA_IN_CH0_INT_SOURCE, + ETS_AXI_PDMA_IN_CH1_INT_SOURCE, + ETS_AXI_PDMA_IN_CH2_INT_SOURCE, + ETS_AXI_PDMA_OUT_CH0_INT_SOURCE, + ETS_AXI_PDMA_OUT_CH1_INT_SOURCE, + ETS_AXI_PDMA_OUT_CH2_INT_SOURCE, + ETS_RSA_INT_SOURCE, + ETS_AES_INT_SOURCE, + ETS_SHA_INT_SOURCE, + ETS_ECC_INT_SOURCE, + ETS_ECDSA_INT_SOURCE, + ETS_KM_INT_SOURCE, + ETS_GPIO_INT0_SOURCE, + ETS_GPIO_INT1_SOURCE, + ETS_GPIO_INT2_SOURCE, + ETS_GPIO_INT3_SOURCE, + ETS_GPIO_PAD_COMP_INT_SOURCE, + ETS_CPU_INT_FROM_CPU_0_SOURCE, + ETS_CPU_INT_FROM_CPU_1_SOURCE, + ETS_CPU_INT_FROM_CPU_2_SOURCE, + ETS_CPU_INT_FROM_CPU_3_SOURCE, + ETS_CACHE_INT_SOURCE, + ETS_FLASH_MSPI_INT_SOURCE, + ETS_CSI_BRIDGE_INT_SOURCE, + ETS_DSI_BRIDGE_INT_SOURCE, + ETS_CSI_INT_SOURCE, + ETS_DSI_INT_SOURCE, + ETS_GMII_PHY_INT_SOURCE, + ETS_LPI_INT_SOURCE, + ETS_PMT_INT_SOURCE, + ETS_SBD_INT_SOURCE, + ETS_USB_OTG_INT_SOURCE, + ETS_USB_OTG_ENDP_MULTI_PROC_INT_SOURCE, + ETS_JPEG_INT_SOURCE, + ETS_PPA_INT_SOURCE, + ETS_CORE0_TRACE_INT_SOURCE, + ETS_CORE1_TRACE_INT_SOURCE, + ETS_HP_CORE_CTRL_INT_SOURCE, + ETS_ISP_INT_SOURCE, + ETS_I3C_MST_INT_SOURCE, + ETS_I3C_SLV_INT_SOURCE, + ETS_USB_OTG11_INT_SOURCE, + ETS_DMA2D_IN_CH0_INT_SOURCE, + ETS_DMA2D_IN_CH1_INT_SOURCE, + ETS_DMA2D_OUT_CH0_INT_SOURCE, + ETS_DMA2D_OUT_CH1_INT_SOURCE, + ETS_DMA2D_OUT_CH2_INT_SOURCE, + ETS_PSRAM_MSPI_INT_SOURCE, + ETS_HP_SYSREG_INT_SOURCE, + ETS_PCNT_INT_SOURCE, + ETS_HP_PAU_INT_SOURCE, + ETS_HP_PARLIO_RX_INT_SOURCE, + ETS_HP_PARLIO_TX_INT_SOURCE, + ETS_H264_DMA2D_OUT_CH0_INT_SOURCE, + ETS_H264_DMA2D_OUT_CH1_INT_SOURCE, + ETS_H264_DMA2D_OUT_CH2_INT_SOURCE, + ETS_H264_DMA2D_OUT_CH3_INT_SOURCE, + ETS_H264_DMA2D_OUT_CH4_INT_SOURCE, + ETS_H264_DMA2D_IN_CH0_INT_SOURCE, + ETS_H264_DMA2D_IN_CH1_INT_SOURCE, + ETS_H264_DMA2D_IN_CH2_INT_SOURCE, + ETS_H264_DMA2D_IN_CH3_INT_SOURCE, + ETS_H264_DMA2D_IN_CH4_INT_SOURCE, + ETS_H264_DMA2D_IN_CH5_INT_SOURCE, + ETS_H264_REG_INT_SOURCE, + ETS_ASSIST_DEBUG_INT_SOURCE, + ETS_DMA2D_IN_CH2_INT_SOURCE, + ETS_DMA2D_OUT_CH3_INT_SOURCE, + ETS_AXI_PERF_MON_INT_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrupt_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/io_mux_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_eco5_reg.h new file mode 100644 index 0000000000..c651fb6e56 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_eco5_reg.h @@ -0,0 +1,5466 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO0_GPIO0_0 0 +#define FUNC_GPIO0_GPIO0 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO1_GPIO1_0 0 +#define FUNC_GPIO1_GPIO1 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO2_MTCK 0 +#define FUNC_GPIO2_GPIO2 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO3_MTDI 0 +#define FUNC_GPIO3_GPIO3 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO4_MTMS 0 +#define FUNC_GPIO4_GPIO4 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO5_MTDO 0 +#define FUNC_GPIO5_GPIO5 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO6_GPIO6_0 0 +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_SPI2_HOLD_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO7_GPIO7_0 0 +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_SPI2_CS_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO8_GPIO8_0 0 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_UART0_RTS_PAD 2 +#define FUNC_GPIO8_SPI2_D_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO9_GPIO9_0 0 +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_UART0_CTS_PAD 2 +#define FUNC_GPIO9_SPI2_CK_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO10_GPIO10_0 0 +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_UART1_TXD_PAD 2 +#define FUNC_GPIO10_SPI2_Q_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO11 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO11_GPIO11_0 0 +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_UART1_RXD_PAD 2 +#define FUNC_GPIO11_SPI2_WP_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO12_GPIO12_0 0 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_UART1_RTS_PAD 2 + +#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO13_GPIO13_0 0 +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_UART1_CTS_PAD 2 + +#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO14_GPIO14_0 0 +#define FUNC_GPIO14_GPIO14 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO15_GPIO15_0 0 +#define FUNC_GPIO15_GPIO15 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO16_GPIO16_0 0 +#define FUNC_GPIO16_GPIO16 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO17_GPIO17_0 0 +#define FUNC_GPIO17_GPIO17 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO18_GPIO18_0 0 +#define FUNC_GPIO18_GPIO18 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO19_GPIO19_0 0 +#define FUNC_GPIO19_GPIO19 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO20_GPIO20_0 0 +#define FUNC_GPIO20_GPIO20 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO21_GPIO21_0 0 +#define FUNC_GPIO21_GPIO21 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO22_GPIO22_0 0 +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_DBG_PSRAM_CK_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO23_GPIO23_0 0 +#define FUNC_GPIO23_GPIO23 1 +#define FUNC_GPIO23_REF_50M_CLK_PAD 3 +#define FUNC_GPIO23_DBG_PSRAM_CS_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO24_GPIO24_0 0 +#define FUNC_GPIO24_GPIO24 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO25_GPIO25_0 0 +#define FUNC_GPIO25_GPIO25 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO26_GPIO26_0 0 +#define FUNC_GPIO26_GPIO26 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO27_GPIO27_0 0 +#define FUNC_GPIO27_GPIO27 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO28_GPIO28_0 0 +#define FUNC_GPIO28_GPIO28 1 +#define FUNC_GPIO28_SPI2_CS_PAD 2 +#define FUNC_GPIO28_GMAC_PHY_RXDV_PAD 3 +#define FUNC_GPIO28_DBG_PSRAM_D_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO29 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO29_GPIO29_0 0 +#define FUNC_GPIO29_GPIO29 1 +#define FUNC_GPIO29_SPI2_D_PAD 2 +#define FUNC_GPIO29_GMAC_PHY_RXD0_PAD 3 +#define FUNC_GPIO29_DBG_PSRAM_Q_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO30 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO30_GPIO30_0 0 +#define FUNC_GPIO30_GPIO30 1 +#define FUNC_GPIO30_SPI2_CK_PAD 2 +#define FUNC_GPIO30_GMAC_PHY_RXD1_PAD 3 +#define FUNC_GPIO30_DBG_PSRAM_WP_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO31 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO31_GPIO31_0 0 +#define FUNC_GPIO31_GPIO31 1 +#define FUNC_GPIO31_SPI2_Q_PAD 2 +#define FUNC_GPIO31_GMAC_PHY_RXER_PAD 3 +#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD 4 + +// Strapping: Diag Group Sel1 +#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO32_GPIO32_0 0 +#define FUNC_GPIO32_GPIO32 1 +#define FUNC_GPIO32_SPI2_HOLD_PAD 2 +#define FUNC_GPIO32_GMAC_RMII_CLK_PAD 3 +#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4 + +// Strapping: Diag Group Sel0 +#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO33_GPIO33_0 0 +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_SPI2_WP_PAD 2 +#define FUNC_GPIO33_GMAC_PHY_TXEN_PAD 3 +#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4 + +// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag +#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO34_GPIO34_0 0 +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_SPI2_IO4_PAD 2 +#define FUNC_GPIO34_GMAC_PHY_TXD0_PAD 3 +#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4 + +// Strapping: Boot Mode select 3 +#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO35_GPIO35_0 0 +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_SPI2_IO5_PAD 2 +#define FUNC_GPIO35_GMAC_PHY_TXD1_PAD 3 +#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4 + +// Strapping: Boot Mode select 2 +#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO36_GPIO36_0 0 +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_SPI2_IO6_PAD 2 +#define FUNC_GPIO36_GMAC_PHY_TXER_PAD 3 +#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4 + +// Strapping: Boot Mode select 1 +#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO37_UART0_TXD_PAD 0 +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_SPI2_IO7_PAD 2 + +// Strapping: Boot Mode select 0 +#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO38_UART0_RXD_PAD 0 +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_SPI2_DQS_PAD 2 + +#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO39_SD1_CDATA0_PAD 0 +#define FUNC_GPIO39_GPIO39 1 +#define FUNC_GPIO39_BIST_PAD 2 +#define FUNC_GPIO39_REF_50M_CLK_PAD 3 +#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO40 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO40_SD1_CDATA1_PAD 0 +#define FUNC_GPIO40_GPIO40 1 +#define FUNC_GPIO40_BIST_PAD 2 +#define FUNC_GPIO40_GMAC_PHY_TXEN_PAD 3 +#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO41 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO41_SD1_CDATA2_PAD 0 +#define FUNC_GPIO41_GPIO41 1 +#define FUNC_GPIO41_BIST_PAD 2 +#define FUNC_GPIO41_GMAC_PHY_TXD0_PAD 3 +#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO42 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO42_SD1_CDATA3_PAD 0 +#define FUNC_GPIO42_GPIO42 1 +#define FUNC_GPIO42_BIST_PAD 2 +#define FUNC_GPIO42_GMAC_PHY_TXD1_PAD 3 +#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO43 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO43_SD1_CCLK_PAD 0 +#define FUNC_GPIO43_GPIO43 1 +#define FUNC_GPIO43_BIST_PAD 2 +#define FUNC_GPIO43_GMAC_PHY_TXER_PAD 3 +#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO44 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO44_SD1_CCMD_PAD 0 +#define FUNC_GPIO44_GPIO44 1 +#define FUNC_GPIO44_BIST_PAD 2 +#define FUNC_GPIO44_GMAC_RMII_CLK_PAD 3 +#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO45 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO45_SD1_CDATA4_PAD 0 +#define FUNC_GPIO45_GPIO45 1 +#define FUNC_GPIO45_BIST_PAD 2 +#define FUNC_GPIO45_GMAC_PHY_RXDV_PAD 3 +#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO46 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO46_SD1_CDATA5_PAD 0 +#define FUNC_GPIO46_GPIO46 1 +#define FUNC_GPIO46_BIST_PAD 2 +#define FUNC_GPIO46_GMAC_PHY_RXD0_PAD 3 +#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO47 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO47_SD1_CDATA6_PAD 0 +#define FUNC_GPIO47_GPIO47 1 +#define FUNC_GPIO47_BIST_PAD 2 +#define FUNC_GPIO47_GMAC_PHY_RXD1_PAD 3 +#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO48 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO48_SD1_CDATA7_PAD 0 +#define FUNC_GPIO48_GPIO48 1 +#define FUNC_GPIO48_BIST_PAD 2 +#define FUNC_GPIO48_GMAC_PHY_RXER_PAD 3 + +#define PERIPHS_IO_MUX_U_PAD_GPIO49 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO49_GPIO49_0 0 +#define FUNC_GPIO49_GPIO49 1 +#define FUNC_GPIO49_GMAC_PHY_TXEN_PAD 3 +#define FUNC_GPIO49_DBG_FLASH_CS_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO50 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO50_GPIO50_0 0 +#define FUNC_GPIO50_GPIO50 1 +#define FUNC_GPIO50_GMAC_RMII_CLK_PAD 3 +#define FUNC_GPIO50_DBG_FLASH_Q_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO51 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO51_GPIO51_0 0 +#define FUNC_GPIO51_GPIO51 1 +#define FUNC_GPIO51_GMAC_PHY_RXDV_PAD 3 +#define FUNC_GPIO51_DBG_FLASH_WP_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO52 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO52_GPIO52_0 0 +#define FUNC_GPIO52_GPIO52 1 +#define FUNC_GPIO52_GMAC_PHY_RXD0_PAD 3 +#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO53 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO53_GPIO53_0 0 +#define FUNC_GPIO53_GPIO53 1 +#define FUNC_GPIO53_GMAC_PHY_RXD1_PAD 3 +#define FUNC_GPIO53_DBG_FLASH_CK_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO54 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO54_GPIO54_0 0 +#define FUNC_GPIO54_GPIO54 1 +#define FUNC_GPIO54_GMAC_PHY_RXER_PAD 3 +#define FUNC_GPIO54_DBG_FLASH_D_PAD 4 + +#define PERIPHS_IO_MUX_U_PAD_GPIO55 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO55_GPIO55_0 0 +#define FUNC_GPIO55_GPIO55 1 + +#define PERIPHS_IO_MUX_U_PAD_GPIO56 (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO56_GPIO56_0 0 +#define FUNC_GPIO56_GPIO56 1 + + +/** IO_MUX_gpio0_REG register + * iomux control register for gpio0 + */ +#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4) +/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO0_MCU_OE (BIT(0)) +#define IO_MUX_GPIO0_MCU_OE_M (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S) +#define IO_MUX_GPIO0_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO0_MCU_OE_S 0 +/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO0_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO0_SLP_SEL_M (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S) +#define IO_MUX_GPIO0_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO0_SLP_SEL_S 1 +/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO0_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO0_MCU_WPD_M (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S) +#define IO_MUX_GPIO0_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO0_MCU_WPD_S 2 +/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO0_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO0_MCU_WPU_M (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S) +#define IO_MUX_GPIO0_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO0_MCU_WPU_S 3 +/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO0_MCU_IE (BIT(4)) +#define IO_MUX_GPIO0_MCU_IE_M (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S) +#define IO_MUX_GPIO0_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO0_MCU_IE_S 4 +/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO0_MCU_DRV 0x00000003U +#define IO_MUX_GPIO0_MCU_DRV_M (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S) +#define IO_MUX_GPIO0_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO0_MCU_DRV_S 5 +/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO0_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO0_FUN_WPD_M (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S) +#define IO_MUX_GPIO0_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO0_FUN_WPD_S 7 +/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO0_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO0_FUN_WPU_M (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S) +#define IO_MUX_GPIO0_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO0_FUN_WPU_S 8 +/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO0_FUN_IE (BIT(9)) +#define IO_MUX_GPIO0_FUN_IE_M (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S) +#define IO_MUX_GPIO0_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO0_FUN_IE_S 9 +/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO0_FUN_DRV 0x00000003U +#define IO_MUX_GPIO0_FUN_DRV_M (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S) +#define IO_MUX_GPIO0_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO0_FUN_DRV_S 10 +/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO0_MCU_SEL 0x00000007U +#define IO_MUX_GPIO0_MCU_SEL_M (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S) +#define IO_MUX_GPIO0_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO0_MCU_SEL_S 12 +/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO0_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO0_FILTER_EN_M (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S) +#define IO_MUX_GPIO0_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO0_FILTER_EN_S 15 + +/** IO_MUX_gpio1_REG register + * iomux control register for gpio1 + */ +#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8) +/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO1_MCU_OE (BIT(0)) +#define IO_MUX_GPIO1_MCU_OE_M (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S) +#define IO_MUX_GPIO1_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO1_MCU_OE_S 0 +/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO1_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO1_SLP_SEL_M (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S) +#define IO_MUX_GPIO1_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO1_SLP_SEL_S 1 +/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO1_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO1_MCU_WPD_M (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S) +#define IO_MUX_GPIO1_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO1_MCU_WPD_S 2 +/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO1_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO1_MCU_WPU_M (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S) +#define IO_MUX_GPIO1_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO1_MCU_WPU_S 3 +/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO1_MCU_IE (BIT(4)) +#define IO_MUX_GPIO1_MCU_IE_M (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S) +#define IO_MUX_GPIO1_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO1_MCU_IE_S 4 +/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO1_MCU_DRV 0x00000003U +#define IO_MUX_GPIO1_MCU_DRV_M (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S) +#define IO_MUX_GPIO1_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO1_MCU_DRV_S 5 +/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO1_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO1_FUN_WPD_M (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S) +#define IO_MUX_GPIO1_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO1_FUN_WPD_S 7 +/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO1_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO1_FUN_WPU_M (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S) +#define IO_MUX_GPIO1_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO1_FUN_WPU_S 8 +/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO1_FUN_IE (BIT(9)) +#define IO_MUX_GPIO1_FUN_IE_M (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S) +#define IO_MUX_GPIO1_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO1_FUN_IE_S 9 +/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO1_FUN_DRV 0x00000003U +#define IO_MUX_GPIO1_FUN_DRV_M (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S) +#define IO_MUX_GPIO1_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO1_FUN_DRV_S 10 +/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO1_MCU_SEL 0x00000007U +#define IO_MUX_GPIO1_MCU_SEL_M (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S) +#define IO_MUX_GPIO1_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO1_MCU_SEL_S 12 +/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO1_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO1_FILTER_EN_M (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S) +#define IO_MUX_GPIO1_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO1_FILTER_EN_S 15 + +/** IO_MUX_gpio2_REG register + * iomux control register for gpio2 + */ +#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc) +/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO2_MCU_OE (BIT(0)) +#define IO_MUX_GPIO2_MCU_OE_M (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S) +#define IO_MUX_GPIO2_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO2_MCU_OE_S 0 +/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO2_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO2_SLP_SEL_M (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S) +#define IO_MUX_GPIO2_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO2_SLP_SEL_S 1 +/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO2_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO2_MCU_WPD_M (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S) +#define IO_MUX_GPIO2_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO2_MCU_WPD_S 2 +/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO2_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO2_MCU_WPU_M (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S) +#define IO_MUX_GPIO2_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO2_MCU_WPU_S 3 +/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO2_MCU_IE (BIT(4)) +#define IO_MUX_GPIO2_MCU_IE_M (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S) +#define IO_MUX_GPIO2_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO2_MCU_IE_S 4 +/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO2_MCU_DRV 0x00000003U +#define IO_MUX_GPIO2_MCU_DRV_M (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S) +#define IO_MUX_GPIO2_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO2_MCU_DRV_S 5 +/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO2_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO2_FUN_WPD_M (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S) +#define IO_MUX_GPIO2_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO2_FUN_WPD_S 7 +/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO2_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO2_FUN_WPU_M (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S) +#define IO_MUX_GPIO2_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO2_FUN_WPU_S 8 +/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO2_FUN_IE (BIT(9)) +#define IO_MUX_GPIO2_FUN_IE_M (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S) +#define IO_MUX_GPIO2_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO2_FUN_IE_S 9 +/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO2_FUN_DRV 0x00000003U +#define IO_MUX_GPIO2_FUN_DRV_M (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S) +#define IO_MUX_GPIO2_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO2_FUN_DRV_S 10 +/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO2_MCU_SEL 0x00000007U +#define IO_MUX_GPIO2_MCU_SEL_M (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S) +#define IO_MUX_GPIO2_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO2_MCU_SEL_S 12 +/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO2_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO2_FILTER_EN_M (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S) +#define IO_MUX_GPIO2_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO2_FILTER_EN_S 15 + +/** IO_MUX_gpio3_REG register + * iomux control register for gpio3 + */ +#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10) +/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO3_MCU_OE (BIT(0)) +#define IO_MUX_GPIO3_MCU_OE_M (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S) +#define IO_MUX_GPIO3_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO3_MCU_OE_S 0 +/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO3_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO3_SLP_SEL_M (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S) +#define IO_MUX_GPIO3_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO3_SLP_SEL_S 1 +/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO3_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO3_MCU_WPD_M (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S) +#define IO_MUX_GPIO3_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO3_MCU_WPD_S 2 +/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO3_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO3_MCU_WPU_M (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S) +#define IO_MUX_GPIO3_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO3_MCU_WPU_S 3 +/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO3_MCU_IE (BIT(4)) +#define IO_MUX_GPIO3_MCU_IE_M (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S) +#define IO_MUX_GPIO3_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO3_MCU_IE_S 4 +/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO3_MCU_DRV 0x00000003U +#define IO_MUX_GPIO3_MCU_DRV_M (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S) +#define IO_MUX_GPIO3_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO3_MCU_DRV_S 5 +/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO3_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO3_FUN_WPD_M (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S) +#define IO_MUX_GPIO3_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO3_FUN_WPD_S 7 +/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO3_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO3_FUN_WPU_M (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S) +#define IO_MUX_GPIO3_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO3_FUN_WPU_S 8 +/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO3_FUN_IE (BIT(9)) +#define IO_MUX_GPIO3_FUN_IE_M (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S) +#define IO_MUX_GPIO3_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO3_FUN_IE_S 9 +/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO3_FUN_DRV 0x00000003U +#define IO_MUX_GPIO3_FUN_DRV_M (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S) +#define IO_MUX_GPIO3_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO3_FUN_DRV_S 10 +/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO3_MCU_SEL 0x00000007U +#define IO_MUX_GPIO3_MCU_SEL_M (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S) +#define IO_MUX_GPIO3_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO3_MCU_SEL_S 12 +/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO3_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO3_FILTER_EN_M (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S) +#define IO_MUX_GPIO3_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO3_FILTER_EN_S 15 + +/** IO_MUX_gpio4_REG register + * iomux control register for gpio4 + */ +#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14) +/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO4_MCU_OE (BIT(0)) +#define IO_MUX_GPIO4_MCU_OE_M (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S) +#define IO_MUX_GPIO4_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO4_MCU_OE_S 0 +/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO4_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO4_SLP_SEL_M (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S) +#define IO_MUX_GPIO4_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO4_SLP_SEL_S 1 +/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO4_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO4_MCU_WPD_M (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S) +#define IO_MUX_GPIO4_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO4_MCU_WPD_S 2 +/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO4_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO4_MCU_WPU_M (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S) +#define IO_MUX_GPIO4_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO4_MCU_WPU_S 3 +/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO4_MCU_IE (BIT(4)) +#define IO_MUX_GPIO4_MCU_IE_M (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S) +#define IO_MUX_GPIO4_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO4_MCU_IE_S 4 +/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO4_MCU_DRV 0x00000003U +#define IO_MUX_GPIO4_MCU_DRV_M (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S) +#define IO_MUX_GPIO4_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO4_MCU_DRV_S 5 +/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO4_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO4_FUN_WPD_M (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S) +#define IO_MUX_GPIO4_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO4_FUN_WPD_S 7 +/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO4_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO4_FUN_WPU_M (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S) +#define IO_MUX_GPIO4_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO4_FUN_WPU_S 8 +/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO4_FUN_IE (BIT(9)) +#define IO_MUX_GPIO4_FUN_IE_M (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S) +#define IO_MUX_GPIO4_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO4_FUN_IE_S 9 +/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO4_FUN_DRV 0x00000003U +#define IO_MUX_GPIO4_FUN_DRV_M (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S) +#define IO_MUX_GPIO4_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO4_FUN_DRV_S 10 +/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO4_MCU_SEL 0x00000007U +#define IO_MUX_GPIO4_MCU_SEL_M (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S) +#define IO_MUX_GPIO4_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO4_MCU_SEL_S 12 +/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO4_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO4_FILTER_EN_M (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S) +#define IO_MUX_GPIO4_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO4_FILTER_EN_S 15 + +/** IO_MUX_gpio5_REG register + * iomux control register for gpio5 + */ +#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18) +/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO5_MCU_OE (BIT(0)) +#define IO_MUX_GPIO5_MCU_OE_M (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S) +#define IO_MUX_GPIO5_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO5_MCU_OE_S 0 +/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO5_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO5_SLP_SEL_M (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S) +#define IO_MUX_GPIO5_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO5_SLP_SEL_S 1 +/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO5_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO5_MCU_WPD_M (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S) +#define IO_MUX_GPIO5_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO5_MCU_WPD_S 2 +/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO5_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO5_MCU_WPU_M (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S) +#define IO_MUX_GPIO5_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO5_MCU_WPU_S 3 +/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO5_MCU_IE (BIT(4)) +#define IO_MUX_GPIO5_MCU_IE_M (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S) +#define IO_MUX_GPIO5_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO5_MCU_IE_S 4 +/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO5_MCU_DRV 0x00000003U +#define IO_MUX_GPIO5_MCU_DRV_M (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S) +#define IO_MUX_GPIO5_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO5_MCU_DRV_S 5 +/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO5_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO5_FUN_WPD_M (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S) +#define IO_MUX_GPIO5_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO5_FUN_WPD_S 7 +/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO5_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO5_FUN_WPU_M (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S) +#define IO_MUX_GPIO5_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO5_FUN_WPU_S 8 +/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO5_FUN_IE (BIT(9)) +#define IO_MUX_GPIO5_FUN_IE_M (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S) +#define IO_MUX_GPIO5_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO5_FUN_IE_S 9 +/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO5_FUN_DRV 0x00000003U +#define IO_MUX_GPIO5_FUN_DRV_M (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S) +#define IO_MUX_GPIO5_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO5_FUN_DRV_S 10 +/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO5_MCU_SEL 0x00000007U +#define IO_MUX_GPIO5_MCU_SEL_M (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S) +#define IO_MUX_GPIO5_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO5_MCU_SEL_S 12 +/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO5_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO5_FILTER_EN_M (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S) +#define IO_MUX_GPIO5_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO5_FILTER_EN_S 15 + +/** IO_MUX_gpio6_REG register + * iomux control register for gpio6 + */ +#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c) +/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO6_MCU_OE (BIT(0)) +#define IO_MUX_GPIO6_MCU_OE_M (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S) +#define IO_MUX_GPIO6_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO6_MCU_OE_S 0 +/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO6_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO6_SLP_SEL_M (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S) +#define IO_MUX_GPIO6_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO6_SLP_SEL_S 1 +/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO6_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO6_MCU_WPD_M (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S) +#define IO_MUX_GPIO6_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO6_MCU_WPD_S 2 +/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO6_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO6_MCU_WPU_M (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S) +#define IO_MUX_GPIO6_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO6_MCU_WPU_S 3 +/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO6_MCU_IE (BIT(4)) +#define IO_MUX_GPIO6_MCU_IE_M (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S) +#define IO_MUX_GPIO6_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO6_MCU_IE_S 4 +/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO6_MCU_DRV 0x00000003U +#define IO_MUX_GPIO6_MCU_DRV_M (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S) +#define IO_MUX_GPIO6_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO6_MCU_DRV_S 5 +/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO6_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO6_FUN_WPD_M (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S) +#define IO_MUX_GPIO6_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO6_FUN_WPD_S 7 +/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO6_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO6_FUN_WPU_M (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S) +#define IO_MUX_GPIO6_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO6_FUN_WPU_S 8 +/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO6_FUN_IE (BIT(9)) +#define IO_MUX_GPIO6_FUN_IE_M (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S) +#define IO_MUX_GPIO6_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO6_FUN_IE_S 9 +/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO6_FUN_DRV 0x00000003U +#define IO_MUX_GPIO6_FUN_DRV_M (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S) +#define IO_MUX_GPIO6_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO6_FUN_DRV_S 10 +/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO6_MCU_SEL 0x00000007U +#define IO_MUX_GPIO6_MCU_SEL_M (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S) +#define IO_MUX_GPIO6_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO6_MCU_SEL_S 12 +/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO6_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO6_FILTER_EN_M (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S) +#define IO_MUX_GPIO6_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO6_FILTER_EN_S 15 + +/** IO_MUX_gpio7_REG register + * iomux control register for gpio7 + */ +#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20) +/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO7_MCU_OE (BIT(0)) +#define IO_MUX_GPIO7_MCU_OE_M (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S) +#define IO_MUX_GPIO7_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO7_MCU_OE_S 0 +/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO7_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO7_SLP_SEL_M (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S) +#define IO_MUX_GPIO7_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO7_SLP_SEL_S 1 +/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO7_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO7_MCU_WPD_M (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S) +#define IO_MUX_GPIO7_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO7_MCU_WPD_S 2 +/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO7_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO7_MCU_WPU_M (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S) +#define IO_MUX_GPIO7_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO7_MCU_WPU_S 3 +/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO7_MCU_IE (BIT(4)) +#define IO_MUX_GPIO7_MCU_IE_M (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S) +#define IO_MUX_GPIO7_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO7_MCU_IE_S 4 +/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO7_MCU_DRV 0x00000003U +#define IO_MUX_GPIO7_MCU_DRV_M (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S) +#define IO_MUX_GPIO7_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO7_MCU_DRV_S 5 +/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO7_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO7_FUN_WPD_M (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S) +#define IO_MUX_GPIO7_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO7_FUN_WPD_S 7 +/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO7_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO7_FUN_WPU_M (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S) +#define IO_MUX_GPIO7_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO7_FUN_WPU_S 8 +/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO7_FUN_IE (BIT(9)) +#define IO_MUX_GPIO7_FUN_IE_M (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S) +#define IO_MUX_GPIO7_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO7_FUN_IE_S 9 +/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO7_FUN_DRV 0x00000003U +#define IO_MUX_GPIO7_FUN_DRV_M (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S) +#define IO_MUX_GPIO7_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO7_FUN_DRV_S 10 +/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO7_MCU_SEL 0x00000007U +#define IO_MUX_GPIO7_MCU_SEL_M (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S) +#define IO_MUX_GPIO7_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO7_MCU_SEL_S 12 +/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO7_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO7_FILTER_EN_M (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S) +#define IO_MUX_GPIO7_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO7_FILTER_EN_S 15 + +/** IO_MUX_gpio8_REG register + * iomux control register for gpio8 + */ +#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24) +/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO8_MCU_OE (BIT(0)) +#define IO_MUX_GPIO8_MCU_OE_M (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S) +#define IO_MUX_GPIO8_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO8_MCU_OE_S 0 +/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO8_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO8_SLP_SEL_M (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S) +#define IO_MUX_GPIO8_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO8_SLP_SEL_S 1 +/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO8_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO8_MCU_WPD_M (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S) +#define IO_MUX_GPIO8_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO8_MCU_WPD_S 2 +/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO8_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO8_MCU_WPU_M (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S) +#define IO_MUX_GPIO8_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO8_MCU_WPU_S 3 +/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO8_MCU_IE (BIT(4)) +#define IO_MUX_GPIO8_MCU_IE_M (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S) +#define IO_MUX_GPIO8_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO8_MCU_IE_S 4 +/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO8_MCU_DRV 0x00000003U +#define IO_MUX_GPIO8_MCU_DRV_M (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S) +#define IO_MUX_GPIO8_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO8_MCU_DRV_S 5 +/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO8_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO8_FUN_WPD_M (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S) +#define IO_MUX_GPIO8_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO8_FUN_WPD_S 7 +/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO8_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO8_FUN_WPU_M (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S) +#define IO_MUX_GPIO8_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO8_FUN_WPU_S 8 +/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO8_FUN_IE (BIT(9)) +#define IO_MUX_GPIO8_FUN_IE_M (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S) +#define IO_MUX_GPIO8_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO8_FUN_IE_S 9 +/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO8_FUN_DRV 0x00000003U +#define IO_MUX_GPIO8_FUN_DRV_M (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S) +#define IO_MUX_GPIO8_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO8_FUN_DRV_S 10 +/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO8_MCU_SEL 0x00000007U +#define IO_MUX_GPIO8_MCU_SEL_M (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S) +#define IO_MUX_GPIO8_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO8_MCU_SEL_S 12 +/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO8_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO8_FILTER_EN_M (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S) +#define IO_MUX_GPIO8_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO8_FILTER_EN_S 15 + +/** IO_MUX_gpio9_REG register + * iomux control register for gpio9 + */ +#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28) +/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO9_MCU_OE (BIT(0)) +#define IO_MUX_GPIO9_MCU_OE_M (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S) +#define IO_MUX_GPIO9_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO9_MCU_OE_S 0 +/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO9_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO9_SLP_SEL_M (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S) +#define IO_MUX_GPIO9_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO9_SLP_SEL_S 1 +/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO9_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO9_MCU_WPD_M (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S) +#define IO_MUX_GPIO9_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO9_MCU_WPD_S 2 +/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO9_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO9_MCU_WPU_M (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S) +#define IO_MUX_GPIO9_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO9_MCU_WPU_S 3 +/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO9_MCU_IE (BIT(4)) +#define IO_MUX_GPIO9_MCU_IE_M (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S) +#define IO_MUX_GPIO9_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO9_MCU_IE_S 4 +/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO9_MCU_DRV 0x00000003U +#define IO_MUX_GPIO9_MCU_DRV_M (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S) +#define IO_MUX_GPIO9_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO9_MCU_DRV_S 5 +/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO9_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO9_FUN_WPD_M (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S) +#define IO_MUX_GPIO9_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO9_FUN_WPD_S 7 +/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO9_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO9_FUN_WPU_M (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S) +#define IO_MUX_GPIO9_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO9_FUN_WPU_S 8 +/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO9_FUN_IE (BIT(9)) +#define IO_MUX_GPIO9_FUN_IE_M (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S) +#define IO_MUX_GPIO9_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO9_FUN_IE_S 9 +/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO9_FUN_DRV 0x00000003U +#define IO_MUX_GPIO9_FUN_DRV_M (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S) +#define IO_MUX_GPIO9_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO9_FUN_DRV_S 10 +/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO9_MCU_SEL 0x00000007U +#define IO_MUX_GPIO9_MCU_SEL_M (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S) +#define IO_MUX_GPIO9_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO9_MCU_SEL_S 12 +/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO9_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO9_FILTER_EN_M (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S) +#define IO_MUX_GPIO9_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO9_FILTER_EN_S 15 + +/** IO_MUX_gpio10_REG register + * iomux control register for gpio10 + */ +#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c) +/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO10_MCU_OE (BIT(0)) +#define IO_MUX_GPIO10_MCU_OE_M (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S) +#define IO_MUX_GPIO10_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO10_MCU_OE_S 0 +/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO10_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO10_SLP_SEL_M (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S) +#define IO_MUX_GPIO10_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO10_SLP_SEL_S 1 +/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO10_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO10_MCU_WPD_M (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S) +#define IO_MUX_GPIO10_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO10_MCU_WPD_S 2 +/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO10_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO10_MCU_WPU_M (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S) +#define IO_MUX_GPIO10_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO10_MCU_WPU_S 3 +/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO10_MCU_IE (BIT(4)) +#define IO_MUX_GPIO10_MCU_IE_M (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S) +#define IO_MUX_GPIO10_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO10_MCU_IE_S 4 +/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO10_MCU_DRV 0x00000003U +#define IO_MUX_GPIO10_MCU_DRV_M (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S) +#define IO_MUX_GPIO10_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO10_MCU_DRV_S 5 +/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO10_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO10_FUN_WPD_M (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S) +#define IO_MUX_GPIO10_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO10_FUN_WPD_S 7 +/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO10_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO10_FUN_WPU_M (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S) +#define IO_MUX_GPIO10_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO10_FUN_WPU_S 8 +/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO10_FUN_IE (BIT(9)) +#define IO_MUX_GPIO10_FUN_IE_M (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S) +#define IO_MUX_GPIO10_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO10_FUN_IE_S 9 +/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO10_FUN_DRV 0x00000003U +#define IO_MUX_GPIO10_FUN_DRV_M (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S) +#define IO_MUX_GPIO10_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO10_FUN_DRV_S 10 +/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO10_MCU_SEL 0x00000007U +#define IO_MUX_GPIO10_MCU_SEL_M (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S) +#define IO_MUX_GPIO10_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO10_MCU_SEL_S 12 +/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO10_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO10_FILTER_EN_M (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S) +#define IO_MUX_GPIO10_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO10_FILTER_EN_S 15 + +/** IO_MUX_gpio11_REG register + * iomux control register for gpio11 + */ +#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30) +/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO11_MCU_OE (BIT(0)) +#define IO_MUX_GPIO11_MCU_OE_M (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S) +#define IO_MUX_GPIO11_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO11_MCU_OE_S 0 +/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO11_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO11_SLP_SEL_M (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S) +#define IO_MUX_GPIO11_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO11_SLP_SEL_S 1 +/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO11_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO11_MCU_WPD_M (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S) +#define IO_MUX_GPIO11_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO11_MCU_WPD_S 2 +/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO11_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO11_MCU_WPU_M (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S) +#define IO_MUX_GPIO11_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO11_MCU_WPU_S 3 +/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO11_MCU_IE (BIT(4)) +#define IO_MUX_GPIO11_MCU_IE_M (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S) +#define IO_MUX_GPIO11_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO11_MCU_IE_S 4 +/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO11_MCU_DRV 0x00000003U +#define IO_MUX_GPIO11_MCU_DRV_M (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S) +#define IO_MUX_GPIO11_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO11_MCU_DRV_S 5 +/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO11_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO11_FUN_WPD_M (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S) +#define IO_MUX_GPIO11_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO11_FUN_WPD_S 7 +/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO11_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO11_FUN_WPU_M (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S) +#define IO_MUX_GPIO11_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO11_FUN_WPU_S 8 +/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO11_FUN_IE (BIT(9)) +#define IO_MUX_GPIO11_FUN_IE_M (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S) +#define IO_MUX_GPIO11_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO11_FUN_IE_S 9 +/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO11_FUN_DRV 0x00000003U +#define IO_MUX_GPIO11_FUN_DRV_M (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S) +#define IO_MUX_GPIO11_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO11_FUN_DRV_S 10 +/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO11_MCU_SEL 0x00000007U +#define IO_MUX_GPIO11_MCU_SEL_M (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S) +#define IO_MUX_GPIO11_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO11_MCU_SEL_S 12 +/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO11_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO11_FILTER_EN_M (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S) +#define IO_MUX_GPIO11_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO11_FILTER_EN_S 15 + +/** IO_MUX_gpio12_REG register + * iomux control register for gpio12 + */ +#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34) +/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO12_MCU_OE (BIT(0)) +#define IO_MUX_GPIO12_MCU_OE_M (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S) +#define IO_MUX_GPIO12_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO12_MCU_OE_S 0 +/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO12_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO12_SLP_SEL_M (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S) +#define IO_MUX_GPIO12_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO12_SLP_SEL_S 1 +/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO12_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO12_MCU_WPD_M (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S) +#define IO_MUX_GPIO12_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO12_MCU_WPD_S 2 +/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO12_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO12_MCU_WPU_M (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S) +#define IO_MUX_GPIO12_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO12_MCU_WPU_S 3 +/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO12_MCU_IE (BIT(4)) +#define IO_MUX_GPIO12_MCU_IE_M (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S) +#define IO_MUX_GPIO12_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO12_MCU_IE_S 4 +/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO12_MCU_DRV 0x00000003U +#define IO_MUX_GPIO12_MCU_DRV_M (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S) +#define IO_MUX_GPIO12_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO12_MCU_DRV_S 5 +/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO12_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO12_FUN_WPD_M (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S) +#define IO_MUX_GPIO12_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO12_FUN_WPD_S 7 +/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO12_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO12_FUN_WPU_M (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S) +#define IO_MUX_GPIO12_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO12_FUN_WPU_S 8 +/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO12_FUN_IE (BIT(9)) +#define IO_MUX_GPIO12_FUN_IE_M (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S) +#define IO_MUX_GPIO12_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO12_FUN_IE_S 9 +/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO12_FUN_DRV 0x00000003U +#define IO_MUX_GPIO12_FUN_DRV_M (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S) +#define IO_MUX_GPIO12_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO12_FUN_DRV_S 10 +/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO12_MCU_SEL 0x00000007U +#define IO_MUX_GPIO12_MCU_SEL_M (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S) +#define IO_MUX_GPIO12_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO12_MCU_SEL_S 12 +/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO12_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO12_FILTER_EN_M (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S) +#define IO_MUX_GPIO12_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO12_FILTER_EN_S 15 + +/** IO_MUX_gpio13_REG register + * iomux control register for gpio13 + */ +#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38) +/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO13_MCU_OE (BIT(0)) +#define IO_MUX_GPIO13_MCU_OE_M (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S) +#define IO_MUX_GPIO13_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO13_MCU_OE_S 0 +/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO13_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO13_SLP_SEL_M (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S) +#define IO_MUX_GPIO13_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO13_SLP_SEL_S 1 +/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO13_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO13_MCU_WPD_M (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S) +#define IO_MUX_GPIO13_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO13_MCU_WPD_S 2 +/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO13_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO13_MCU_WPU_M (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S) +#define IO_MUX_GPIO13_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO13_MCU_WPU_S 3 +/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO13_MCU_IE (BIT(4)) +#define IO_MUX_GPIO13_MCU_IE_M (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S) +#define IO_MUX_GPIO13_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO13_MCU_IE_S 4 +/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO13_MCU_DRV 0x00000003U +#define IO_MUX_GPIO13_MCU_DRV_M (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S) +#define IO_MUX_GPIO13_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO13_MCU_DRV_S 5 +/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO13_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO13_FUN_WPD_M (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S) +#define IO_MUX_GPIO13_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO13_FUN_WPD_S 7 +/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO13_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO13_FUN_WPU_M (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S) +#define IO_MUX_GPIO13_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO13_FUN_WPU_S 8 +/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO13_FUN_IE (BIT(9)) +#define IO_MUX_GPIO13_FUN_IE_M (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S) +#define IO_MUX_GPIO13_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO13_FUN_IE_S 9 +/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO13_FUN_DRV 0x00000003U +#define IO_MUX_GPIO13_FUN_DRV_M (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S) +#define IO_MUX_GPIO13_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO13_FUN_DRV_S 10 +/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO13_MCU_SEL 0x00000007U +#define IO_MUX_GPIO13_MCU_SEL_M (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S) +#define IO_MUX_GPIO13_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO13_MCU_SEL_S 12 +/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO13_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO13_FILTER_EN_M (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S) +#define IO_MUX_GPIO13_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO13_FILTER_EN_S 15 + +/** IO_MUX_gpio14_REG register + * iomux control register for gpio14 + */ +#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c) +/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO14_MCU_OE (BIT(0)) +#define IO_MUX_GPIO14_MCU_OE_M (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S) +#define IO_MUX_GPIO14_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO14_MCU_OE_S 0 +/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO14_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO14_SLP_SEL_M (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S) +#define IO_MUX_GPIO14_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO14_SLP_SEL_S 1 +/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO14_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO14_MCU_WPD_M (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S) +#define IO_MUX_GPIO14_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO14_MCU_WPD_S 2 +/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO14_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO14_MCU_WPU_M (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S) +#define IO_MUX_GPIO14_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO14_MCU_WPU_S 3 +/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO14_MCU_IE (BIT(4)) +#define IO_MUX_GPIO14_MCU_IE_M (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S) +#define IO_MUX_GPIO14_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO14_MCU_IE_S 4 +/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO14_MCU_DRV 0x00000003U +#define IO_MUX_GPIO14_MCU_DRV_M (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S) +#define IO_MUX_GPIO14_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO14_MCU_DRV_S 5 +/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO14_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO14_FUN_WPD_M (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S) +#define IO_MUX_GPIO14_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO14_FUN_WPD_S 7 +/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO14_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO14_FUN_WPU_M (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S) +#define IO_MUX_GPIO14_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO14_FUN_WPU_S 8 +/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO14_FUN_IE (BIT(9)) +#define IO_MUX_GPIO14_FUN_IE_M (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S) +#define IO_MUX_GPIO14_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO14_FUN_IE_S 9 +/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO14_FUN_DRV 0x00000003U +#define IO_MUX_GPIO14_FUN_DRV_M (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S) +#define IO_MUX_GPIO14_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO14_FUN_DRV_S 10 +/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO14_MCU_SEL 0x00000007U +#define IO_MUX_GPIO14_MCU_SEL_M (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S) +#define IO_MUX_GPIO14_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO14_MCU_SEL_S 12 +/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO14_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO14_FILTER_EN_M (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S) +#define IO_MUX_GPIO14_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO14_FILTER_EN_S 15 + +/** IO_MUX_gpio15_REG register + * iomux control register for gpio15 + */ +#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40) +/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO15_MCU_OE (BIT(0)) +#define IO_MUX_GPIO15_MCU_OE_M (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S) +#define IO_MUX_GPIO15_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO15_MCU_OE_S 0 +/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO15_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO15_SLP_SEL_M (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S) +#define IO_MUX_GPIO15_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO15_SLP_SEL_S 1 +/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO15_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO15_MCU_WPD_M (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S) +#define IO_MUX_GPIO15_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO15_MCU_WPD_S 2 +/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO15_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO15_MCU_WPU_M (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S) +#define IO_MUX_GPIO15_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO15_MCU_WPU_S 3 +/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO15_MCU_IE (BIT(4)) +#define IO_MUX_GPIO15_MCU_IE_M (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S) +#define IO_MUX_GPIO15_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO15_MCU_IE_S 4 +/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO15_MCU_DRV 0x00000003U +#define IO_MUX_GPIO15_MCU_DRV_M (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S) +#define IO_MUX_GPIO15_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO15_MCU_DRV_S 5 +/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO15_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO15_FUN_WPD_M (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S) +#define IO_MUX_GPIO15_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO15_FUN_WPD_S 7 +/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO15_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO15_FUN_WPU_M (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S) +#define IO_MUX_GPIO15_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO15_FUN_WPU_S 8 +/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO15_FUN_IE (BIT(9)) +#define IO_MUX_GPIO15_FUN_IE_M (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S) +#define IO_MUX_GPIO15_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO15_FUN_IE_S 9 +/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO15_FUN_DRV 0x00000003U +#define IO_MUX_GPIO15_FUN_DRV_M (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S) +#define IO_MUX_GPIO15_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO15_FUN_DRV_S 10 +/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO15_MCU_SEL 0x00000007U +#define IO_MUX_GPIO15_MCU_SEL_M (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S) +#define IO_MUX_GPIO15_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO15_MCU_SEL_S 12 +/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO15_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO15_FILTER_EN_M (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S) +#define IO_MUX_GPIO15_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO15_FILTER_EN_S 15 + +/** IO_MUX_gpio16_REG register + * iomux control register for gpio16 + */ +#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44) +/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO16_MCU_OE (BIT(0)) +#define IO_MUX_GPIO16_MCU_OE_M (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S) +#define IO_MUX_GPIO16_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO16_MCU_OE_S 0 +/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO16_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO16_SLP_SEL_M (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S) +#define IO_MUX_GPIO16_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO16_SLP_SEL_S 1 +/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO16_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO16_MCU_WPD_M (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S) +#define IO_MUX_GPIO16_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO16_MCU_WPD_S 2 +/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO16_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO16_MCU_WPU_M (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S) +#define IO_MUX_GPIO16_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO16_MCU_WPU_S 3 +/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO16_MCU_IE (BIT(4)) +#define IO_MUX_GPIO16_MCU_IE_M (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S) +#define IO_MUX_GPIO16_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO16_MCU_IE_S 4 +/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO16_MCU_DRV 0x00000003U +#define IO_MUX_GPIO16_MCU_DRV_M (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S) +#define IO_MUX_GPIO16_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO16_MCU_DRV_S 5 +/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO16_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO16_FUN_WPD_M (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S) +#define IO_MUX_GPIO16_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO16_FUN_WPD_S 7 +/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO16_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO16_FUN_WPU_M (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S) +#define IO_MUX_GPIO16_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO16_FUN_WPU_S 8 +/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO16_FUN_IE (BIT(9)) +#define IO_MUX_GPIO16_FUN_IE_M (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S) +#define IO_MUX_GPIO16_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO16_FUN_IE_S 9 +/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO16_FUN_DRV 0x00000003U +#define IO_MUX_GPIO16_FUN_DRV_M (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S) +#define IO_MUX_GPIO16_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO16_FUN_DRV_S 10 +/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO16_MCU_SEL 0x00000007U +#define IO_MUX_GPIO16_MCU_SEL_M (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S) +#define IO_MUX_GPIO16_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO16_MCU_SEL_S 12 +/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO16_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO16_FILTER_EN_M (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S) +#define IO_MUX_GPIO16_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO16_FILTER_EN_S 15 + +/** IO_MUX_gpio17_REG register + * iomux control register for gpio17 + */ +#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48) +/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO17_MCU_OE (BIT(0)) +#define IO_MUX_GPIO17_MCU_OE_M (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S) +#define IO_MUX_GPIO17_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO17_MCU_OE_S 0 +/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO17_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO17_SLP_SEL_M (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S) +#define IO_MUX_GPIO17_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO17_SLP_SEL_S 1 +/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO17_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO17_MCU_WPD_M (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S) +#define IO_MUX_GPIO17_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO17_MCU_WPD_S 2 +/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO17_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO17_MCU_WPU_M (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S) +#define IO_MUX_GPIO17_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO17_MCU_WPU_S 3 +/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO17_MCU_IE (BIT(4)) +#define IO_MUX_GPIO17_MCU_IE_M (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S) +#define IO_MUX_GPIO17_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO17_MCU_IE_S 4 +/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO17_MCU_DRV 0x00000003U +#define IO_MUX_GPIO17_MCU_DRV_M (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S) +#define IO_MUX_GPIO17_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO17_MCU_DRV_S 5 +/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO17_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO17_FUN_WPD_M (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S) +#define IO_MUX_GPIO17_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO17_FUN_WPD_S 7 +/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO17_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO17_FUN_WPU_M (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S) +#define IO_MUX_GPIO17_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO17_FUN_WPU_S 8 +/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO17_FUN_IE (BIT(9)) +#define IO_MUX_GPIO17_FUN_IE_M (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S) +#define IO_MUX_GPIO17_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO17_FUN_IE_S 9 +/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO17_FUN_DRV 0x00000003U +#define IO_MUX_GPIO17_FUN_DRV_M (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S) +#define IO_MUX_GPIO17_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO17_FUN_DRV_S 10 +/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO17_MCU_SEL 0x00000007U +#define IO_MUX_GPIO17_MCU_SEL_M (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S) +#define IO_MUX_GPIO17_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO17_MCU_SEL_S 12 +/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO17_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO17_FILTER_EN_M (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S) +#define IO_MUX_GPIO17_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO17_FILTER_EN_S 15 + +/** IO_MUX_gpio18_REG register + * iomux control register for gpio18 + */ +#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c) +/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO18_MCU_OE (BIT(0)) +#define IO_MUX_GPIO18_MCU_OE_M (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S) +#define IO_MUX_GPIO18_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO18_MCU_OE_S 0 +/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO18_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO18_SLP_SEL_M (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S) +#define IO_MUX_GPIO18_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO18_SLP_SEL_S 1 +/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO18_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO18_MCU_WPD_M (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S) +#define IO_MUX_GPIO18_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO18_MCU_WPD_S 2 +/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO18_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO18_MCU_WPU_M (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S) +#define IO_MUX_GPIO18_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO18_MCU_WPU_S 3 +/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO18_MCU_IE (BIT(4)) +#define IO_MUX_GPIO18_MCU_IE_M (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S) +#define IO_MUX_GPIO18_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO18_MCU_IE_S 4 +/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO18_MCU_DRV 0x00000003U +#define IO_MUX_GPIO18_MCU_DRV_M (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S) +#define IO_MUX_GPIO18_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO18_MCU_DRV_S 5 +/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO18_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO18_FUN_WPD_M (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S) +#define IO_MUX_GPIO18_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO18_FUN_WPD_S 7 +/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO18_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO18_FUN_WPU_M (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S) +#define IO_MUX_GPIO18_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO18_FUN_WPU_S 8 +/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO18_FUN_IE (BIT(9)) +#define IO_MUX_GPIO18_FUN_IE_M (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S) +#define IO_MUX_GPIO18_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO18_FUN_IE_S 9 +/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO18_FUN_DRV 0x00000003U +#define IO_MUX_GPIO18_FUN_DRV_M (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S) +#define IO_MUX_GPIO18_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO18_FUN_DRV_S 10 +/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO18_MCU_SEL 0x00000007U +#define IO_MUX_GPIO18_MCU_SEL_M (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S) +#define IO_MUX_GPIO18_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO18_MCU_SEL_S 12 +/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO18_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO18_FILTER_EN_M (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S) +#define IO_MUX_GPIO18_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO18_FILTER_EN_S 15 + +/** IO_MUX_gpio19_REG register + * iomux control register for gpio19 + */ +#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50) +/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO19_MCU_OE (BIT(0)) +#define IO_MUX_GPIO19_MCU_OE_M (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S) +#define IO_MUX_GPIO19_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO19_MCU_OE_S 0 +/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO19_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO19_SLP_SEL_M (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S) +#define IO_MUX_GPIO19_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO19_SLP_SEL_S 1 +/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO19_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO19_MCU_WPD_M (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S) +#define IO_MUX_GPIO19_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO19_MCU_WPD_S 2 +/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO19_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO19_MCU_WPU_M (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S) +#define IO_MUX_GPIO19_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO19_MCU_WPU_S 3 +/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO19_MCU_IE (BIT(4)) +#define IO_MUX_GPIO19_MCU_IE_M (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S) +#define IO_MUX_GPIO19_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO19_MCU_IE_S 4 +/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO19_MCU_DRV 0x00000003U +#define IO_MUX_GPIO19_MCU_DRV_M (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S) +#define IO_MUX_GPIO19_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO19_MCU_DRV_S 5 +/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO19_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO19_FUN_WPD_M (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S) +#define IO_MUX_GPIO19_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO19_FUN_WPD_S 7 +/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO19_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO19_FUN_WPU_M (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S) +#define IO_MUX_GPIO19_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO19_FUN_WPU_S 8 +/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO19_FUN_IE (BIT(9)) +#define IO_MUX_GPIO19_FUN_IE_M (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S) +#define IO_MUX_GPIO19_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO19_FUN_IE_S 9 +/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO19_FUN_DRV 0x00000003U +#define IO_MUX_GPIO19_FUN_DRV_M (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S) +#define IO_MUX_GPIO19_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO19_FUN_DRV_S 10 +/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO19_MCU_SEL 0x00000007U +#define IO_MUX_GPIO19_MCU_SEL_M (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S) +#define IO_MUX_GPIO19_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO19_MCU_SEL_S 12 +/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO19_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO19_FILTER_EN_M (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S) +#define IO_MUX_GPIO19_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO19_FILTER_EN_S 15 + +/** IO_MUX_gpio20_REG register + * iomux control register for gpio20 + */ +#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54) +/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO20_MCU_OE (BIT(0)) +#define IO_MUX_GPIO20_MCU_OE_M (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S) +#define IO_MUX_GPIO20_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO20_MCU_OE_S 0 +/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO20_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO20_SLP_SEL_M (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S) +#define IO_MUX_GPIO20_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO20_SLP_SEL_S 1 +/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO20_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO20_MCU_WPD_M (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S) +#define IO_MUX_GPIO20_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO20_MCU_WPD_S 2 +/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO20_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO20_MCU_WPU_M (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S) +#define IO_MUX_GPIO20_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO20_MCU_WPU_S 3 +/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO20_MCU_IE (BIT(4)) +#define IO_MUX_GPIO20_MCU_IE_M (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S) +#define IO_MUX_GPIO20_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO20_MCU_IE_S 4 +/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO20_MCU_DRV 0x00000003U +#define IO_MUX_GPIO20_MCU_DRV_M (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S) +#define IO_MUX_GPIO20_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO20_MCU_DRV_S 5 +/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO20_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO20_FUN_WPD_M (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S) +#define IO_MUX_GPIO20_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO20_FUN_WPD_S 7 +/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO20_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO20_FUN_WPU_M (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S) +#define IO_MUX_GPIO20_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO20_FUN_WPU_S 8 +/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO20_FUN_IE (BIT(9)) +#define IO_MUX_GPIO20_FUN_IE_M (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S) +#define IO_MUX_GPIO20_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO20_FUN_IE_S 9 +/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO20_FUN_DRV 0x00000003U +#define IO_MUX_GPIO20_FUN_DRV_M (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S) +#define IO_MUX_GPIO20_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO20_FUN_DRV_S 10 +/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO20_MCU_SEL 0x00000007U +#define IO_MUX_GPIO20_MCU_SEL_M (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S) +#define IO_MUX_GPIO20_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO20_MCU_SEL_S 12 +/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO20_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO20_FILTER_EN_M (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S) +#define IO_MUX_GPIO20_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO20_FILTER_EN_S 15 + +/** IO_MUX_gpio21_REG register + * iomux control register for gpio21 + */ +#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58) +/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO21_MCU_OE (BIT(0)) +#define IO_MUX_GPIO21_MCU_OE_M (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S) +#define IO_MUX_GPIO21_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO21_MCU_OE_S 0 +/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO21_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO21_SLP_SEL_M (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S) +#define IO_MUX_GPIO21_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO21_SLP_SEL_S 1 +/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO21_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO21_MCU_WPD_M (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S) +#define IO_MUX_GPIO21_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO21_MCU_WPD_S 2 +/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO21_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO21_MCU_WPU_M (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S) +#define IO_MUX_GPIO21_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO21_MCU_WPU_S 3 +/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO21_MCU_IE (BIT(4)) +#define IO_MUX_GPIO21_MCU_IE_M (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S) +#define IO_MUX_GPIO21_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO21_MCU_IE_S 4 +/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO21_MCU_DRV 0x00000003U +#define IO_MUX_GPIO21_MCU_DRV_M (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S) +#define IO_MUX_GPIO21_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO21_MCU_DRV_S 5 +/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO21_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO21_FUN_WPD_M (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S) +#define IO_MUX_GPIO21_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO21_FUN_WPD_S 7 +/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO21_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO21_FUN_WPU_M (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S) +#define IO_MUX_GPIO21_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO21_FUN_WPU_S 8 +/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO21_FUN_IE (BIT(9)) +#define IO_MUX_GPIO21_FUN_IE_M (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S) +#define IO_MUX_GPIO21_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO21_FUN_IE_S 9 +/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO21_FUN_DRV 0x00000003U +#define IO_MUX_GPIO21_FUN_DRV_M (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S) +#define IO_MUX_GPIO21_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO21_FUN_DRV_S 10 +/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO21_MCU_SEL 0x00000007U +#define IO_MUX_GPIO21_MCU_SEL_M (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S) +#define IO_MUX_GPIO21_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO21_MCU_SEL_S 12 +/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO21_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO21_FILTER_EN_M (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S) +#define IO_MUX_GPIO21_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO21_FILTER_EN_S 15 + +/** IO_MUX_gpio22_REG register + * iomux control register for gpio22 + */ +#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c) +/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO22_MCU_OE (BIT(0)) +#define IO_MUX_GPIO22_MCU_OE_M (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S) +#define IO_MUX_GPIO22_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO22_MCU_OE_S 0 +/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO22_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO22_SLP_SEL_M (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S) +#define IO_MUX_GPIO22_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO22_SLP_SEL_S 1 +/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO22_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO22_MCU_WPD_M (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S) +#define IO_MUX_GPIO22_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO22_MCU_WPD_S 2 +/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO22_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO22_MCU_WPU_M (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S) +#define IO_MUX_GPIO22_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO22_MCU_WPU_S 3 +/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO22_MCU_IE (BIT(4)) +#define IO_MUX_GPIO22_MCU_IE_M (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S) +#define IO_MUX_GPIO22_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO22_MCU_IE_S 4 +/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO22_MCU_DRV 0x00000003U +#define IO_MUX_GPIO22_MCU_DRV_M (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S) +#define IO_MUX_GPIO22_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO22_MCU_DRV_S 5 +/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO22_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO22_FUN_WPD_M (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S) +#define IO_MUX_GPIO22_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO22_FUN_WPD_S 7 +/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO22_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO22_FUN_WPU_M (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S) +#define IO_MUX_GPIO22_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO22_FUN_WPU_S 8 +/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO22_FUN_IE (BIT(9)) +#define IO_MUX_GPIO22_FUN_IE_M (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S) +#define IO_MUX_GPIO22_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO22_FUN_IE_S 9 +/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO22_FUN_DRV 0x00000003U +#define IO_MUX_GPIO22_FUN_DRV_M (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S) +#define IO_MUX_GPIO22_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO22_FUN_DRV_S 10 +/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO22_MCU_SEL 0x00000007U +#define IO_MUX_GPIO22_MCU_SEL_M (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S) +#define IO_MUX_GPIO22_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO22_MCU_SEL_S 12 +/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO22_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO22_FILTER_EN_M (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S) +#define IO_MUX_GPIO22_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO22_FILTER_EN_S 15 + +/** IO_MUX_gpio23_REG register + * iomux control register for gpio23 + */ +#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60) +/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO23_MCU_OE (BIT(0)) +#define IO_MUX_GPIO23_MCU_OE_M (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S) +#define IO_MUX_GPIO23_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO23_MCU_OE_S 0 +/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO23_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO23_SLP_SEL_M (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S) +#define IO_MUX_GPIO23_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO23_SLP_SEL_S 1 +/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO23_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO23_MCU_WPD_M (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S) +#define IO_MUX_GPIO23_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO23_MCU_WPD_S 2 +/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO23_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO23_MCU_WPU_M (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S) +#define IO_MUX_GPIO23_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO23_MCU_WPU_S 3 +/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO23_MCU_IE (BIT(4)) +#define IO_MUX_GPIO23_MCU_IE_M (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S) +#define IO_MUX_GPIO23_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO23_MCU_IE_S 4 +/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO23_MCU_DRV 0x00000003U +#define IO_MUX_GPIO23_MCU_DRV_M (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S) +#define IO_MUX_GPIO23_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO23_MCU_DRV_S 5 +/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO23_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO23_FUN_WPD_M (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S) +#define IO_MUX_GPIO23_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO23_FUN_WPD_S 7 +/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO23_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO23_FUN_WPU_M (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S) +#define IO_MUX_GPIO23_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO23_FUN_WPU_S 8 +/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO23_FUN_IE (BIT(9)) +#define IO_MUX_GPIO23_FUN_IE_M (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S) +#define IO_MUX_GPIO23_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO23_FUN_IE_S 9 +/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO23_FUN_DRV 0x00000003U +#define IO_MUX_GPIO23_FUN_DRV_M (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S) +#define IO_MUX_GPIO23_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO23_FUN_DRV_S 10 +/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO23_MCU_SEL 0x00000007U +#define IO_MUX_GPIO23_MCU_SEL_M (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S) +#define IO_MUX_GPIO23_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO23_MCU_SEL_S 12 +/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO23_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO23_FILTER_EN_M (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S) +#define IO_MUX_GPIO23_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO23_FILTER_EN_S 15 + +/** IO_MUX_gpio24_REG register + * iomux control register for gpio24 + */ +#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64) +/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO24_MCU_OE (BIT(0)) +#define IO_MUX_GPIO24_MCU_OE_M (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S) +#define IO_MUX_GPIO24_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO24_MCU_OE_S 0 +/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO24_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO24_SLP_SEL_M (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S) +#define IO_MUX_GPIO24_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO24_SLP_SEL_S 1 +/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO24_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO24_MCU_WPD_M (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S) +#define IO_MUX_GPIO24_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO24_MCU_WPD_S 2 +/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO24_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO24_MCU_WPU_M (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S) +#define IO_MUX_GPIO24_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO24_MCU_WPU_S 3 +/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO24_MCU_IE (BIT(4)) +#define IO_MUX_GPIO24_MCU_IE_M (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S) +#define IO_MUX_GPIO24_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO24_MCU_IE_S 4 +/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO24_MCU_DRV 0x00000003U +#define IO_MUX_GPIO24_MCU_DRV_M (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S) +#define IO_MUX_GPIO24_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO24_MCU_DRV_S 5 +/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO24_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO24_FUN_WPD_M (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S) +#define IO_MUX_GPIO24_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO24_FUN_WPD_S 7 +/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO24_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO24_FUN_WPU_M (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S) +#define IO_MUX_GPIO24_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO24_FUN_WPU_S 8 +/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO24_FUN_IE (BIT(9)) +#define IO_MUX_GPIO24_FUN_IE_M (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S) +#define IO_MUX_GPIO24_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO24_FUN_IE_S 9 +/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 3; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO24_FUN_DRV 0x00000003U +#define IO_MUX_GPIO24_FUN_DRV_M (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S) +#define IO_MUX_GPIO24_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO24_FUN_DRV_S 10 +/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO24_MCU_SEL 0x00000007U +#define IO_MUX_GPIO24_MCU_SEL_M (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S) +#define IO_MUX_GPIO24_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO24_MCU_SEL_S 12 +/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO24_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO24_FILTER_EN_M (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S) +#define IO_MUX_GPIO24_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO24_FILTER_EN_S 15 + +/** IO_MUX_gpio25_REG register + * iomux control register for gpio25 + */ +#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68) +/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO25_MCU_OE (BIT(0)) +#define IO_MUX_GPIO25_MCU_OE_M (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S) +#define IO_MUX_GPIO25_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO25_MCU_OE_S 0 +/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO25_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO25_SLP_SEL_M (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S) +#define IO_MUX_GPIO25_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO25_SLP_SEL_S 1 +/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO25_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO25_MCU_WPD_M (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S) +#define IO_MUX_GPIO25_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO25_MCU_WPD_S 2 +/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO25_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO25_MCU_WPU_M (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S) +#define IO_MUX_GPIO25_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO25_MCU_WPU_S 3 +/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO25_MCU_IE (BIT(4)) +#define IO_MUX_GPIO25_MCU_IE_M (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S) +#define IO_MUX_GPIO25_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO25_MCU_IE_S 4 +/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO25_MCU_DRV 0x00000003U +#define IO_MUX_GPIO25_MCU_DRV_M (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S) +#define IO_MUX_GPIO25_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO25_MCU_DRV_S 5 +/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO25_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO25_FUN_WPD_M (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S) +#define IO_MUX_GPIO25_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO25_FUN_WPD_S 7 +/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO25_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO25_FUN_WPU_M (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S) +#define IO_MUX_GPIO25_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO25_FUN_WPU_S 8 +/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO25_FUN_IE (BIT(9)) +#define IO_MUX_GPIO25_FUN_IE_M (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S) +#define IO_MUX_GPIO25_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO25_FUN_IE_S 9 +/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 3; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO25_FUN_DRV 0x00000003U +#define IO_MUX_GPIO25_FUN_DRV_M (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S) +#define IO_MUX_GPIO25_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO25_FUN_DRV_S 10 +/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO25_MCU_SEL 0x00000007U +#define IO_MUX_GPIO25_MCU_SEL_M (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S) +#define IO_MUX_GPIO25_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO25_MCU_SEL_S 12 +/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO25_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO25_FILTER_EN_M (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S) +#define IO_MUX_GPIO25_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO25_FILTER_EN_S 15 + +/** IO_MUX_gpio26_REG register + * iomux control register for gpio26 + */ +#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c) +/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO26_MCU_OE (BIT(0)) +#define IO_MUX_GPIO26_MCU_OE_M (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S) +#define IO_MUX_GPIO26_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO26_MCU_OE_S 0 +/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO26_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO26_SLP_SEL_M (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S) +#define IO_MUX_GPIO26_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO26_SLP_SEL_S 1 +/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO26_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO26_MCU_WPD_M (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S) +#define IO_MUX_GPIO26_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO26_MCU_WPD_S 2 +/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO26_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO26_MCU_WPU_M (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S) +#define IO_MUX_GPIO26_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO26_MCU_WPU_S 3 +/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO26_MCU_IE (BIT(4)) +#define IO_MUX_GPIO26_MCU_IE_M (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S) +#define IO_MUX_GPIO26_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO26_MCU_IE_S 4 +/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO26_MCU_DRV 0x00000003U +#define IO_MUX_GPIO26_MCU_DRV_M (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S) +#define IO_MUX_GPIO26_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO26_MCU_DRV_S 5 +/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO26_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO26_FUN_WPD_M (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S) +#define IO_MUX_GPIO26_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO26_FUN_WPD_S 7 +/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO26_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO26_FUN_WPU_M (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S) +#define IO_MUX_GPIO26_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO26_FUN_WPU_S 8 +/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO26_FUN_IE (BIT(9)) +#define IO_MUX_GPIO26_FUN_IE_M (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S) +#define IO_MUX_GPIO26_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO26_FUN_IE_S 9 +/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO26_FUN_DRV 0x00000003U +#define IO_MUX_GPIO26_FUN_DRV_M (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S) +#define IO_MUX_GPIO26_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO26_FUN_DRV_S 10 +/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO26_MCU_SEL 0x00000007U +#define IO_MUX_GPIO26_MCU_SEL_M (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S) +#define IO_MUX_GPIO26_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO26_MCU_SEL_S 12 +/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO26_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO26_FILTER_EN_M (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S) +#define IO_MUX_GPIO26_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO26_FILTER_EN_S 15 + +/** IO_MUX_gpio27_REG register + * iomux control register for gpio27 + */ +#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70) +/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO27_MCU_OE (BIT(0)) +#define IO_MUX_GPIO27_MCU_OE_M (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S) +#define IO_MUX_GPIO27_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO27_MCU_OE_S 0 +/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO27_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO27_SLP_SEL_M (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S) +#define IO_MUX_GPIO27_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO27_SLP_SEL_S 1 +/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO27_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO27_MCU_WPD_M (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S) +#define IO_MUX_GPIO27_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO27_MCU_WPD_S 2 +/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO27_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO27_MCU_WPU_M (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S) +#define IO_MUX_GPIO27_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO27_MCU_WPU_S 3 +/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO27_MCU_IE (BIT(4)) +#define IO_MUX_GPIO27_MCU_IE_M (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S) +#define IO_MUX_GPIO27_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO27_MCU_IE_S 4 +/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO27_MCU_DRV 0x00000003U +#define IO_MUX_GPIO27_MCU_DRV_M (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S) +#define IO_MUX_GPIO27_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO27_MCU_DRV_S 5 +/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO27_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO27_FUN_WPD_M (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S) +#define IO_MUX_GPIO27_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO27_FUN_WPD_S 7 +/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO27_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO27_FUN_WPU_M (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S) +#define IO_MUX_GPIO27_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO27_FUN_WPU_S 8 +/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO27_FUN_IE (BIT(9)) +#define IO_MUX_GPIO27_FUN_IE_M (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S) +#define IO_MUX_GPIO27_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO27_FUN_IE_S 9 +/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO27_FUN_DRV 0x00000003U +#define IO_MUX_GPIO27_FUN_DRV_M (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S) +#define IO_MUX_GPIO27_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO27_FUN_DRV_S 10 +/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO27_MCU_SEL 0x00000007U +#define IO_MUX_GPIO27_MCU_SEL_M (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S) +#define IO_MUX_GPIO27_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO27_MCU_SEL_S 12 +/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO27_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO27_FILTER_EN_M (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S) +#define IO_MUX_GPIO27_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO27_FILTER_EN_S 15 + +/** IO_MUX_gpio28_REG register + * iomux control register for gpio28 + */ +#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74) +/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO28_MCU_OE (BIT(0)) +#define IO_MUX_GPIO28_MCU_OE_M (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S) +#define IO_MUX_GPIO28_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO28_MCU_OE_S 0 +/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO28_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO28_SLP_SEL_M (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S) +#define IO_MUX_GPIO28_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO28_SLP_SEL_S 1 +/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO28_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO28_MCU_WPD_M (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S) +#define IO_MUX_GPIO28_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO28_MCU_WPD_S 2 +/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO28_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO28_MCU_WPU_M (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S) +#define IO_MUX_GPIO28_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO28_MCU_WPU_S 3 +/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO28_MCU_IE (BIT(4)) +#define IO_MUX_GPIO28_MCU_IE_M (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S) +#define IO_MUX_GPIO28_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO28_MCU_IE_S 4 +/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO28_MCU_DRV 0x00000003U +#define IO_MUX_GPIO28_MCU_DRV_M (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S) +#define IO_MUX_GPIO28_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO28_MCU_DRV_S 5 +/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO28_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO28_FUN_WPD_M (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S) +#define IO_MUX_GPIO28_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO28_FUN_WPD_S 7 +/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO28_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO28_FUN_WPU_M (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S) +#define IO_MUX_GPIO28_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO28_FUN_WPU_S 8 +/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO28_FUN_IE (BIT(9)) +#define IO_MUX_GPIO28_FUN_IE_M (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S) +#define IO_MUX_GPIO28_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO28_FUN_IE_S 9 +/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO28_FUN_DRV 0x00000003U +#define IO_MUX_GPIO28_FUN_DRV_M (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S) +#define IO_MUX_GPIO28_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO28_FUN_DRV_S 10 +/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO28_MCU_SEL 0x00000007U +#define IO_MUX_GPIO28_MCU_SEL_M (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S) +#define IO_MUX_GPIO28_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO28_MCU_SEL_S 12 +/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO28_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO28_FILTER_EN_M (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S) +#define IO_MUX_GPIO28_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO28_FILTER_EN_S 15 + +/** IO_MUX_gpio29_REG register + * iomux control register for gpio29 + */ +#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78) +/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO29_MCU_OE (BIT(0)) +#define IO_MUX_GPIO29_MCU_OE_M (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S) +#define IO_MUX_GPIO29_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO29_MCU_OE_S 0 +/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO29_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO29_SLP_SEL_M (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S) +#define IO_MUX_GPIO29_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO29_SLP_SEL_S 1 +/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO29_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO29_MCU_WPD_M (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S) +#define IO_MUX_GPIO29_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO29_MCU_WPD_S 2 +/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO29_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO29_MCU_WPU_M (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S) +#define IO_MUX_GPIO29_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO29_MCU_WPU_S 3 +/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO29_MCU_IE (BIT(4)) +#define IO_MUX_GPIO29_MCU_IE_M (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S) +#define IO_MUX_GPIO29_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO29_MCU_IE_S 4 +/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO29_MCU_DRV 0x00000003U +#define IO_MUX_GPIO29_MCU_DRV_M (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S) +#define IO_MUX_GPIO29_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO29_MCU_DRV_S 5 +/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO29_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO29_FUN_WPD_M (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S) +#define IO_MUX_GPIO29_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO29_FUN_WPD_S 7 +/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO29_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO29_FUN_WPU_M (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S) +#define IO_MUX_GPIO29_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO29_FUN_WPU_S 8 +/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO29_FUN_IE (BIT(9)) +#define IO_MUX_GPIO29_FUN_IE_M (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S) +#define IO_MUX_GPIO29_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO29_FUN_IE_S 9 +/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO29_FUN_DRV 0x00000003U +#define IO_MUX_GPIO29_FUN_DRV_M (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S) +#define IO_MUX_GPIO29_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO29_FUN_DRV_S 10 +/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO29_MCU_SEL 0x00000007U +#define IO_MUX_GPIO29_MCU_SEL_M (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S) +#define IO_MUX_GPIO29_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO29_MCU_SEL_S 12 +/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO29_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO29_FILTER_EN_M (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S) +#define IO_MUX_GPIO29_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO29_FILTER_EN_S 15 + +/** IO_MUX_gpio30_REG register + * iomux control register for gpio30 + */ +#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c) +/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO30_MCU_OE (BIT(0)) +#define IO_MUX_GPIO30_MCU_OE_M (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S) +#define IO_MUX_GPIO30_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO30_MCU_OE_S 0 +/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO30_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO30_SLP_SEL_M (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S) +#define IO_MUX_GPIO30_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO30_SLP_SEL_S 1 +/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO30_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO30_MCU_WPD_M (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S) +#define IO_MUX_GPIO30_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO30_MCU_WPD_S 2 +/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO30_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO30_MCU_WPU_M (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S) +#define IO_MUX_GPIO30_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO30_MCU_WPU_S 3 +/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO30_MCU_IE (BIT(4)) +#define IO_MUX_GPIO30_MCU_IE_M (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S) +#define IO_MUX_GPIO30_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO30_MCU_IE_S 4 +/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO30_MCU_DRV 0x00000003U +#define IO_MUX_GPIO30_MCU_DRV_M (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S) +#define IO_MUX_GPIO30_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO30_MCU_DRV_S 5 +/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO30_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO30_FUN_WPD_M (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S) +#define IO_MUX_GPIO30_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO30_FUN_WPD_S 7 +/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO30_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO30_FUN_WPU_M (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S) +#define IO_MUX_GPIO30_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO30_FUN_WPU_S 8 +/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO30_FUN_IE (BIT(9)) +#define IO_MUX_GPIO30_FUN_IE_M (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S) +#define IO_MUX_GPIO30_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO30_FUN_IE_S 9 +/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO30_FUN_DRV 0x00000003U +#define IO_MUX_GPIO30_FUN_DRV_M (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S) +#define IO_MUX_GPIO30_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO30_FUN_DRV_S 10 +/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO30_MCU_SEL 0x00000007U +#define IO_MUX_GPIO30_MCU_SEL_M (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S) +#define IO_MUX_GPIO30_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO30_MCU_SEL_S 12 +/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO30_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO30_FILTER_EN_M (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S) +#define IO_MUX_GPIO30_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO30_FILTER_EN_S 15 + +/** IO_MUX_gpio31_REG register + * iomux control register for gpio31 + */ +#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80) +/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO31_MCU_OE (BIT(0)) +#define IO_MUX_GPIO31_MCU_OE_M (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S) +#define IO_MUX_GPIO31_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO31_MCU_OE_S 0 +/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO31_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO31_SLP_SEL_M (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S) +#define IO_MUX_GPIO31_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO31_SLP_SEL_S 1 +/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO31_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO31_MCU_WPD_M (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S) +#define IO_MUX_GPIO31_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO31_MCU_WPD_S 2 +/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO31_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO31_MCU_WPU_M (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S) +#define IO_MUX_GPIO31_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO31_MCU_WPU_S 3 +/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO31_MCU_IE (BIT(4)) +#define IO_MUX_GPIO31_MCU_IE_M (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S) +#define IO_MUX_GPIO31_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO31_MCU_IE_S 4 +/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO31_MCU_DRV 0x00000003U +#define IO_MUX_GPIO31_MCU_DRV_M (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S) +#define IO_MUX_GPIO31_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO31_MCU_DRV_S 5 +/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO31_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO31_FUN_WPD_M (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S) +#define IO_MUX_GPIO31_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO31_FUN_WPD_S 7 +/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO31_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO31_FUN_WPU_M (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S) +#define IO_MUX_GPIO31_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO31_FUN_WPU_S 8 +/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO31_FUN_IE (BIT(9)) +#define IO_MUX_GPIO31_FUN_IE_M (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S) +#define IO_MUX_GPIO31_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO31_FUN_IE_S 9 +/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO31_FUN_DRV 0x00000003U +#define IO_MUX_GPIO31_FUN_DRV_M (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S) +#define IO_MUX_GPIO31_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO31_FUN_DRV_S 10 +/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO31_MCU_SEL 0x00000007U +#define IO_MUX_GPIO31_MCU_SEL_M (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S) +#define IO_MUX_GPIO31_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO31_MCU_SEL_S 12 +/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO31_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO31_FILTER_EN_M (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S) +#define IO_MUX_GPIO31_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO31_FILTER_EN_S 15 + +/** IO_MUX_gpio32_REG register + * iomux control register for gpio32 + */ +#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84) +/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO32_MCU_OE (BIT(0)) +#define IO_MUX_GPIO32_MCU_OE_M (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S) +#define IO_MUX_GPIO32_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO32_MCU_OE_S 0 +/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO32_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO32_SLP_SEL_M (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S) +#define IO_MUX_GPIO32_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO32_SLP_SEL_S 1 +/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO32_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO32_MCU_WPD_M (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S) +#define IO_MUX_GPIO32_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO32_MCU_WPD_S 2 +/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO32_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO32_MCU_WPU_M (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S) +#define IO_MUX_GPIO32_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO32_MCU_WPU_S 3 +/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO32_MCU_IE (BIT(4)) +#define IO_MUX_GPIO32_MCU_IE_M (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S) +#define IO_MUX_GPIO32_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO32_MCU_IE_S 4 +/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO32_MCU_DRV 0x00000003U +#define IO_MUX_GPIO32_MCU_DRV_M (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S) +#define IO_MUX_GPIO32_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO32_MCU_DRV_S 5 +/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO32_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO32_FUN_WPD_M (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S) +#define IO_MUX_GPIO32_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO32_FUN_WPD_S 7 +/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO32_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO32_FUN_WPU_M (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S) +#define IO_MUX_GPIO32_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO32_FUN_WPU_S 8 +/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO32_FUN_IE (BIT(9)) +#define IO_MUX_GPIO32_FUN_IE_M (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S) +#define IO_MUX_GPIO32_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO32_FUN_IE_S 9 +/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO32_FUN_DRV 0x00000003U +#define IO_MUX_GPIO32_FUN_DRV_M (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S) +#define IO_MUX_GPIO32_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO32_FUN_DRV_S 10 +/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO32_MCU_SEL 0x00000007U +#define IO_MUX_GPIO32_MCU_SEL_M (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S) +#define IO_MUX_GPIO32_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO32_MCU_SEL_S 12 +/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO32_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO32_FILTER_EN_M (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S) +#define IO_MUX_GPIO32_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO32_FILTER_EN_S 15 +/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0; + * NA + */ +#define IO_MUX_GPIO32_RUE_I3C (BIT(16)) +#define IO_MUX_GPIO32_RUE_I3C_M (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S) +#define IO_MUX_GPIO32_RUE_I3C_V 0x00000001U +#define IO_MUX_GPIO32_RUE_I3C_S 16 +/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0; + * NA + */ +#define IO_MUX_GPIO32_RU_I3C 0x00000003U +#define IO_MUX_GPIO32_RU_I3C_M (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S) +#define IO_MUX_GPIO32_RU_I3C_V 0x00000003U +#define IO_MUX_GPIO32_RU_I3C_S 17 +/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; + * NA + */ +#define IO_MUX_GPIO32_RUE_SEL_I3C (BIT(19)) +#define IO_MUX_GPIO32_RUE_SEL_I3C_M (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S) +#define IO_MUX_GPIO32_RUE_SEL_I3C_V 0x00000001U +#define IO_MUX_GPIO32_RUE_SEL_I3C_S 19 + +/** IO_MUX_gpio33_REG register + * iomux control register for gpio33 + */ +#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88) +/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO33_MCU_OE (BIT(0)) +#define IO_MUX_GPIO33_MCU_OE_M (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S) +#define IO_MUX_GPIO33_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO33_MCU_OE_S 0 +/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO33_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO33_SLP_SEL_M (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S) +#define IO_MUX_GPIO33_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO33_SLP_SEL_S 1 +/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO33_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO33_MCU_WPD_M (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S) +#define IO_MUX_GPIO33_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO33_MCU_WPD_S 2 +/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO33_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO33_MCU_WPU_M (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S) +#define IO_MUX_GPIO33_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO33_MCU_WPU_S 3 +/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO33_MCU_IE (BIT(4)) +#define IO_MUX_GPIO33_MCU_IE_M (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S) +#define IO_MUX_GPIO33_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO33_MCU_IE_S 4 +/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO33_MCU_DRV 0x00000003U +#define IO_MUX_GPIO33_MCU_DRV_M (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S) +#define IO_MUX_GPIO33_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO33_MCU_DRV_S 5 +/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO33_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO33_FUN_WPD_M (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S) +#define IO_MUX_GPIO33_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO33_FUN_WPD_S 7 +/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO33_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO33_FUN_WPU_M (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S) +#define IO_MUX_GPIO33_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO33_FUN_WPU_S 8 +/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO33_FUN_IE (BIT(9)) +#define IO_MUX_GPIO33_FUN_IE_M (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S) +#define IO_MUX_GPIO33_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO33_FUN_IE_S 9 +/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO33_FUN_DRV 0x00000003U +#define IO_MUX_GPIO33_FUN_DRV_M (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S) +#define IO_MUX_GPIO33_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO33_FUN_DRV_S 10 +/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO33_MCU_SEL 0x00000007U +#define IO_MUX_GPIO33_MCU_SEL_M (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S) +#define IO_MUX_GPIO33_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO33_MCU_SEL_S 12 +/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO33_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO33_FILTER_EN_M (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S) +#define IO_MUX_GPIO33_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO33_FILTER_EN_S 15 +/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0; + * NA + */ +#define IO_MUX_GPIO33_RUE_I3C (BIT(16)) +#define IO_MUX_GPIO33_RUE_I3C_M (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S) +#define IO_MUX_GPIO33_RUE_I3C_V 0x00000001U +#define IO_MUX_GPIO33_RUE_I3C_S 16 +/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0; + * NA + */ +#define IO_MUX_GPIO33_RU_I3C 0x00000003U +#define IO_MUX_GPIO33_RU_I3C_M (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S) +#define IO_MUX_GPIO33_RU_I3C_V 0x00000003U +#define IO_MUX_GPIO33_RU_I3C_S 17 +/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; + * NA + */ +#define IO_MUX_GPIO33_RUE_SEL_I3C (BIT(19)) +#define IO_MUX_GPIO33_RUE_SEL_I3C_M (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S) +#define IO_MUX_GPIO33_RUE_SEL_I3C_V 0x00000001U +#define IO_MUX_GPIO33_RUE_SEL_I3C_S 19 + +/** IO_MUX_gpio34_REG register + * iomux control register for gpio34 + */ +#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c) +/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO34_MCU_OE (BIT(0)) +#define IO_MUX_GPIO34_MCU_OE_M (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S) +#define IO_MUX_GPIO34_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO34_MCU_OE_S 0 +/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO34_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO34_SLP_SEL_M (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S) +#define IO_MUX_GPIO34_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO34_SLP_SEL_S 1 +/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO34_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO34_MCU_WPD_M (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S) +#define IO_MUX_GPIO34_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO34_MCU_WPD_S 2 +/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO34_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO34_MCU_WPU_M (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S) +#define IO_MUX_GPIO34_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO34_MCU_WPU_S 3 +/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO34_MCU_IE (BIT(4)) +#define IO_MUX_GPIO34_MCU_IE_M (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S) +#define IO_MUX_GPIO34_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO34_MCU_IE_S 4 +/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO34_MCU_DRV 0x00000003U +#define IO_MUX_GPIO34_MCU_DRV_M (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S) +#define IO_MUX_GPIO34_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO34_MCU_DRV_S 5 +/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO34_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO34_FUN_WPD_M (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S) +#define IO_MUX_GPIO34_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO34_FUN_WPD_S 7 +/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO34_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO34_FUN_WPU_M (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S) +#define IO_MUX_GPIO34_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO34_FUN_WPU_S 8 +/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO34_FUN_IE (BIT(9)) +#define IO_MUX_GPIO34_FUN_IE_M (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S) +#define IO_MUX_GPIO34_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO34_FUN_IE_S 9 +/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO34_FUN_DRV 0x00000003U +#define IO_MUX_GPIO34_FUN_DRV_M (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S) +#define IO_MUX_GPIO34_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO34_FUN_DRV_S 10 +/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO34_MCU_SEL 0x00000007U +#define IO_MUX_GPIO34_MCU_SEL_M (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S) +#define IO_MUX_GPIO34_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO34_MCU_SEL_S 12 +/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO34_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO34_FILTER_EN_M (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S) +#define IO_MUX_GPIO34_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO34_FILTER_EN_S 15 + +/** IO_MUX_gpio35_REG register + * iomux control register for gpio35 + */ +#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90) +/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO35_MCU_OE (BIT(0)) +#define IO_MUX_GPIO35_MCU_OE_M (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S) +#define IO_MUX_GPIO35_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO35_MCU_OE_S 0 +/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO35_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO35_SLP_SEL_M (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S) +#define IO_MUX_GPIO35_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO35_SLP_SEL_S 1 +/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO35_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO35_MCU_WPD_M (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S) +#define IO_MUX_GPIO35_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO35_MCU_WPD_S 2 +/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO35_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO35_MCU_WPU_M (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S) +#define IO_MUX_GPIO35_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO35_MCU_WPU_S 3 +/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO35_MCU_IE (BIT(4)) +#define IO_MUX_GPIO35_MCU_IE_M (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S) +#define IO_MUX_GPIO35_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO35_MCU_IE_S 4 +/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO35_MCU_DRV 0x00000003U +#define IO_MUX_GPIO35_MCU_DRV_M (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S) +#define IO_MUX_GPIO35_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO35_MCU_DRV_S 5 +/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO35_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO35_FUN_WPD_M (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S) +#define IO_MUX_GPIO35_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO35_FUN_WPD_S 7 +/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO35_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO35_FUN_WPU_M (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S) +#define IO_MUX_GPIO35_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO35_FUN_WPU_S 8 +/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO35_FUN_IE (BIT(9)) +#define IO_MUX_GPIO35_FUN_IE_M (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S) +#define IO_MUX_GPIO35_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO35_FUN_IE_S 9 +/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO35_FUN_DRV 0x00000003U +#define IO_MUX_GPIO35_FUN_DRV_M (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S) +#define IO_MUX_GPIO35_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO35_FUN_DRV_S 10 +/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO35_MCU_SEL 0x00000007U +#define IO_MUX_GPIO35_MCU_SEL_M (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S) +#define IO_MUX_GPIO35_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO35_MCU_SEL_S 12 +/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO35_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO35_FILTER_EN_M (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S) +#define IO_MUX_GPIO35_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO35_FILTER_EN_S 15 + +/** IO_MUX_gpio36_REG register + * iomux control register for gpio36 + */ +#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94) +/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO36_MCU_OE (BIT(0)) +#define IO_MUX_GPIO36_MCU_OE_M (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S) +#define IO_MUX_GPIO36_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO36_MCU_OE_S 0 +/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO36_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO36_SLP_SEL_M (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S) +#define IO_MUX_GPIO36_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO36_SLP_SEL_S 1 +/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO36_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO36_MCU_WPD_M (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S) +#define IO_MUX_GPIO36_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO36_MCU_WPD_S 2 +/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO36_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO36_MCU_WPU_M (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S) +#define IO_MUX_GPIO36_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO36_MCU_WPU_S 3 +/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO36_MCU_IE (BIT(4)) +#define IO_MUX_GPIO36_MCU_IE_M (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S) +#define IO_MUX_GPIO36_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO36_MCU_IE_S 4 +/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO36_MCU_DRV 0x00000003U +#define IO_MUX_GPIO36_MCU_DRV_M (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S) +#define IO_MUX_GPIO36_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO36_MCU_DRV_S 5 +/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO36_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO36_FUN_WPD_M (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S) +#define IO_MUX_GPIO36_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO36_FUN_WPD_S 7 +/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO36_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO36_FUN_WPU_M (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S) +#define IO_MUX_GPIO36_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO36_FUN_WPU_S 8 +/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO36_FUN_IE (BIT(9)) +#define IO_MUX_GPIO36_FUN_IE_M (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S) +#define IO_MUX_GPIO36_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO36_FUN_IE_S 9 +/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO36_FUN_DRV 0x00000003U +#define IO_MUX_GPIO36_FUN_DRV_M (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S) +#define IO_MUX_GPIO36_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO36_FUN_DRV_S 10 +/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO36_MCU_SEL 0x00000007U +#define IO_MUX_GPIO36_MCU_SEL_M (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S) +#define IO_MUX_GPIO36_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO36_MCU_SEL_S 12 +/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO36_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO36_FILTER_EN_M (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S) +#define IO_MUX_GPIO36_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO36_FILTER_EN_S 15 + +/** IO_MUX_gpio37_REG register + * iomux control register for gpio37 + */ +#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98) +/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO37_MCU_OE (BIT(0)) +#define IO_MUX_GPIO37_MCU_OE_M (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S) +#define IO_MUX_GPIO37_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO37_MCU_OE_S 0 +/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO37_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO37_SLP_SEL_M (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S) +#define IO_MUX_GPIO37_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO37_SLP_SEL_S 1 +/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO37_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO37_MCU_WPD_M (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S) +#define IO_MUX_GPIO37_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO37_MCU_WPD_S 2 +/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO37_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO37_MCU_WPU_M (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S) +#define IO_MUX_GPIO37_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO37_MCU_WPU_S 3 +/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO37_MCU_IE (BIT(4)) +#define IO_MUX_GPIO37_MCU_IE_M (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S) +#define IO_MUX_GPIO37_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO37_MCU_IE_S 4 +/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO37_MCU_DRV 0x00000003U +#define IO_MUX_GPIO37_MCU_DRV_M (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S) +#define IO_MUX_GPIO37_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO37_MCU_DRV_S 5 +/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO37_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO37_FUN_WPD_M (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S) +#define IO_MUX_GPIO37_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO37_FUN_WPD_S 7 +/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO37_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO37_FUN_WPU_M (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S) +#define IO_MUX_GPIO37_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO37_FUN_WPU_S 8 +/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO37_FUN_IE (BIT(9)) +#define IO_MUX_GPIO37_FUN_IE_M (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S) +#define IO_MUX_GPIO37_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO37_FUN_IE_S 9 +/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO37_FUN_DRV 0x00000003U +#define IO_MUX_GPIO37_FUN_DRV_M (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S) +#define IO_MUX_GPIO37_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO37_FUN_DRV_S 10 +/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO37_MCU_SEL 0x00000007U +#define IO_MUX_GPIO37_MCU_SEL_M (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S) +#define IO_MUX_GPIO37_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO37_MCU_SEL_S 12 +/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO37_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO37_FILTER_EN_M (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S) +#define IO_MUX_GPIO37_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO37_FILTER_EN_S 15 + +/** IO_MUX_gpio38_REG register + * iomux control register for gpio38 + */ +#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c) +/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO38_MCU_OE (BIT(0)) +#define IO_MUX_GPIO38_MCU_OE_M (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S) +#define IO_MUX_GPIO38_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO38_MCU_OE_S 0 +/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO38_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO38_SLP_SEL_M (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S) +#define IO_MUX_GPIO38_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO38_SLP_SEL_S 1 +/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO38_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO38_MCU_WPD_M (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S) +#define IO_MUX_GPIO38_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO38_MCU_WPD_S 2 +/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO38_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO38_MCU_WPU_M (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S) +#define IO_MUX_GPIO38_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO38_MCU_WPU_S 3 +/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO38_MCU_IE (BIT(4)) +#define IO_MUX_GPIO38_MCU_IE_M (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S) +#define IO_MUX_GPIO38_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO38_MCU_IE_S 4 +/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO38_MCU_DRV 0x00000003U +#define IO_MUX_GPIO38_MCU_DRV_M (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S) +#define IO_MUX_GPIO38_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO38_MCU_DRV_S 5 +/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO38_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO38_FUN_WPD_M (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S) +#define IO_MUX_GPIO38_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO38_FUN_WPD_S 7 +/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO38_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO38_FUN_WPU_M (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S) +#define IO_MUX_GPIO38_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO38_FUN_WPU_S 8 +/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO38_FUN_IE (BIT(9)) +#define IO_MUX_GPIO38_FUN_IE_M (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S) +#define IO_MUX_GPIO38_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO38_FUN_IE_S 9 +/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO38_FUN_DRV 0x00000003U +#define IO_MUX_GPIO38_FUN_DRV_M (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S) +#define IO_MUX_GPIO38_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO38_FUN_DRV_S 10 +/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO38_MCU_SEL 0x00000007U +#define IO_MUX_GPIO38_MCU_SEL_M (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S) +#define IO_MUX_GPIO38_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO38_MCU_SEL_S 12 +/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO38_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO38_FILTER_EN_M (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S) +#define IO_MUX_GPIO38_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO38_FILTER_EN_S 15 + +/** IO_MUX_gpio39_REG register + * iomux control register for gpio39 + */ +#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0) +/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO39_MCU_OE (BIT(0)) +#define IO_MUX_GPIO39_MCU_OE_M (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S) +#define IO_MUX_GPIO39_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO39_MCU_OE_S 0 +/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO39_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO39_SLP_SEL_M (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S) +#define IO_MUX_GPIO39_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO39_SLP_SEL_S 1 +/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO39_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO39_MCU_WPD_M (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S) +#define IO_MUX_GPIO39_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO39_MCU_WPD_S 2 +/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO39_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO39_MCU_WPU_M (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S) +#define IO_MUX_GPIO39_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO39_MCU_WPU_S 3 +/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO39_MCU_IE (BIT(4)) +#define IO_MUX_GPIO39_MCU_IE_M (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S) +#define IO_MUX_GPIO39_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO39_MCU_IE_S 4 +/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO39_MCU_DRV 0x00000003U +#define IO_MUX_GPIO39_MCU_DRV_M (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S) +#define IO_MUX_GPIO39_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO39_MCU_DRV_S 5 +/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO39_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO39_FUN_WPD_M (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S) +#define IO_MUX_GPIO39_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO39_FUN_WPD_S 7 +/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO39_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO39_FUN_WPU_M (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S) +#define IO_MUX_GPIO39_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO39_FUN_WPU_S 8 +/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO39_FUN_IE (BIT(9)) +#define IO_MUX_GPIO39_FUN_IE_M (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S) +#define IO_MUX_GPIO39_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO39_FUN_IE_S 9 +/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO39_FUN_DRV 0x00000003U +#define IO_MUX_GPIO39_FUN_DRV_M (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S) +#define IO_MUX_GPIO39_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO39_FUN_DRV_S 10 +/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO39_MCU_SEL 0x00000007U +#define IO_MUX_GPIO39_MCU_SEL_M (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S) +#define IO_MUX_GPIO39_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO39_MCU_SEL_S 12 +/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO39_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO39_FILTER_EN_M (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S) +#define IO_MUX_GPIO39_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO39_FILTER_EN_S 15 + +/** IO_MUX_gpio40_REG register + * iomux control register for gpio40 + */ +#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4) +/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO40_MCU_OE (BIT(0)) +#define IO_MUX_GPIO40_MCU_OE_M (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S) +#define IO_MUX_GPIO40_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO40_MCU_OE_S 0 +/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO40_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO40_SLP_SEL_M (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S) +#define IO_MUX_GPIO40_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO40_SLP_SEL_S 1 +/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO40_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO40_MCU_WPD_M (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S) +#define IO_MUX_GPIO40_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO40_MCU_WPD_S 2 +/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO40_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO40_MCU_WPU_M (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S) +#define IO_MUX_GPIO40_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO40_MCU_WPU_S 3 +/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO40_MCU_IE (BIT(4)) +#define IO_MUX_GPIO40_MCU_IE_M (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S) +#define IO_MUX_GPIO40_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO40_MCU_IE_S 4 +/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO40_MCU_DRV 0x00000003U +#define IO_MUX_GPIO40_MCU_DRV_M (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S) +#define IO_MUX_GPIO40_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO40_MCU_DRV_S 5 +/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO40_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO40_FUN_WPD_M (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S) +#define IO_MUX_GPIO40_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO40_FUN_WPD_S 7 +/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO40_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO40_FUN_WPU_M (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S) +#define IO_MUX_GPIO40_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO40_FUN_WPU_S 8 +/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO40_FUN_IE (BIT(9)) +#define IO_MUX_GPIO40_FUN_IE_M (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S) +#define IO_MUX_GPIO40_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO40_FUN_IE_S 9 +/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO40_FUN_DRV 0x00000003U +#define IO_MUX_GPIO40_FUN_DRV_M (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S) +#define IO_MUX_GPIO40_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO40_FUN_DRV_S 10 +/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO40_MCU_SEL 0x00000007U +#define IO_MUX_GPIO40_MCU_SEL_M (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S) +#define IO_MUX_GPIO40_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO40_MCU_SEL_S 12 +/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO40_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO40_FILTER_EN_M (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S) +#define IO_MUX_GPIO40_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO40_FILTER_EN_S 15 + +/** IO_MUX_gpio41_REG register + * iomux control register for gpio41 + */ +#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8) +/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO41_MCU_OE (BIT(0)) +#define IO_MUX_GPIO41_MCU_OE_M (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S) +#define IO_MUX_GPIO41_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO41_MCU_OE_S 0 +/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO41_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO41_SLP_SEL_M (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S) +#define IO_MUX_GPIO41_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO41_SLP_SEL_S 1 +/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO41_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO41_MCU_WPD_M (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S) +#define IO_MUX_GPIO41_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO41_MCU_WPD_S 2 +/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO41_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO41_MCU_WPU_M (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S) +#define IO_MUX_GPIO41_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO41_MCU_WPU_S 3 +/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO41_MCU_IE (BIT(4)) +#define IO_MUX_GPIO41_MCU_IE_M (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S) +#define IO_MUX_GPIO41_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO41_MCU_IE_S 4 +/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO41_MCU_DRV 0x00000003U +#define IO_MUX_GPIO41_MCU_DRV_M (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S) +#define IO_MUX_GPIO41_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO41_MCU_DRV_S 5 +/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO41_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO41_FUN_WPD_M (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S) +#define IO_MUX_GPIO41_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO41_FUN_WPD_S 7 +/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO41_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO41_FUN_WPU_M (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S) +#define IO_MUX_GPIO41_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO41_FUN_WPU_S 8 +/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO41_FUN_IE (BIT(9)) +#define IO_MUX_GPIO41_FUN_IE_M (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S) +#define IO_MUX_GPIO41_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO41_FUN_IE_S 9 +/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO41_FUN_DRV 0x00000003U +#define IO_MUX_GPIO41_FUN_DRV_M (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S) +#define IO_MUX_GPIO41_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO41_FUN_DRV_S 10 +/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO41_MCU_SEL 0x00000007U +#define IO_MUX_GPIO41_MCU_SEL_M (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S) +#define IO_MUX_GPIO41_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO41_MCU_SEL_S 12 +/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO41_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO41_FILTER_EN_M (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S) +#define IO_MUX_GPIO41_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO41_FILTER_EN_S 15 + +/** IO_MUX_gpio42_REG register + * iomux control register for gpio42 + */ +#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac) +/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO42_MCU_OE (BIT(0)) +#define IO_MUX_GPIO42_MCU_OE_M (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S) +#define IO_MUX_GPIO42_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO42_MCU_OE_S 0 +/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO42_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO42_SLP_SEL_M (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S) +#define IO_MUX_GPIO42_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO42_SLP_SEL_S 1 +/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO42_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO42_MCU_WPD_M (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S) +#define IO_MUX_GPIO42_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO42_MCU_WPD_S 2 +/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO42_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO42_MCU_WPU_M (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S) +#define IO_MUX_GPIO42_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO42_MCU_WPU_S 3 +/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO42_MCU_IE (BIT(4)) +#define IO_MUX_GPIO42_MCU_IE_M (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S) +#define IO_MUX_GPIO42_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO42_MCU_IE_S 4 +/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO42_MCU_DRV 0x00000003U +#define IO_MUX_GPIO42_MCU_DRV_M (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S) +#define IO_MUX_GPIO42_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO42_MCU_DRV_S 5 +/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO42_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO42_FUN_WPD_M (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S) +#define IO_MUX_GPIO42_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO42_FUN_WPD_S 7 +/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO42_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO42_FUN_WPU_M (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S) +#define IO_MUX_GPIO42_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO42_FUN_WPU_S 8 +/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO42_FUN_IE (BIT(9)) +#define IO_MUX_GPIO42_FUN_IE_M (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S) +#define IO_MUX_GPIO42_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO42_FUN_IE_S 9 +/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO42_FUN_DRV 0x00000003U +#define IO_MUX_GPIO42_FUN_DRV_M (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S) +#define IO_MUX_GPIO42_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO42_FUN_DRV_S 10 +/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO42_MCU_SEL 0x00000007U +#define IO_MUX_GPIO42_MCU_SEL_M (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S) +#define IO_MUX_GPIO42_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO42_MCU_SEL_S 12 +/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO42_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO42_FILTER_EN_M (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S) +#define IO_MUX_GPIO42_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO42_FILTER_EN_S 15 + +/** IO_MUX_gpio43_REG register + * iomux control register for gpio43 + */ +#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0) +/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO43_MCU_OE (BIT(0)) +#define IO_MUX_GPIO43_MCU_OE_M (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S) +#define IO_MUX_GPIO43_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO43_MCU_OE_S 0 +/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO43_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO43_SLP_SEL_M (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S) +#define IO_MUX_GPIO43_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO43_SLP_SEL_S 1 +/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO43_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO43_MCU_WPD_M (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S) +#define IO_MUX_GPIO43_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO43_MCU_WPD_S 2 +/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO43_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO43_MCU_WPU_M (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S) +#define IO_MUX_GPIO43_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO43_MCU_WPU_S 3 +/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO43_MCU_IE (BIT(4)) +#define IO_MUX_GPIO43_MCU_IE_M (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S) +#define IO_MUX_GPIO43_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO43_MCU_IE_S 4 +/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO43_MCU_DRV 0x00000003U +#define IO_MUX_GPIO43_MCU_DRV_M (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S) +#define IO_MUX_GPIO43_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO43_MCU_DRV_S 5 +/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO43_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO43_FUN_WPD_M (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S) +#define IO_MUX_GPIO43_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO43_FUN_WPD_S 7 +/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO43_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO43_FUN_WPU_M (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S) +#define IO_MUX_GPIO43_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO43_FUN_WPU_S 8 +/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO43_FUN_IE (BIT(9)) +#define IO_MUX_GPIO43_FUN_IE_M (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S) +#define IO_MUX_GPIO43_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO43_FUN_IE_S 9 +/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO43_FUN_DRV 0x00000003U +#define IO_MUX_GPIO43_FUN_DRV_M (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S) +#define IO_MUX_GPIO43_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO43_FUN_DRV_S 10 +/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO43_MCU_SEL 0x00000007U +#define IO_MUX_GPIO43_MCU_SEL_M (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S) +#define IO_MUX_GPIO43_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO43_MCU_SEL_S 12 +/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO43_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO43_FILTER_EN_M (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S) +#define IO_MUX_GPIO43_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO43_FILTER_EN_S 15 + +/** IO_MUX_gpio44_REG register + * iomux control register for gpio44 + */ +#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4) +/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO44_MCU_OE (BIT(0)) +#define IO_MUX_GPIO44_MCU_OE_M (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S) +#define IO_MUX_GPIO44_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO44_MCU_OE_S 0 +/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO44_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO44_SLP_SEL_M (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S) +#define IO_MUX_GPIO44_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO44_SLP_SEL_S 1 +/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO44_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO44_MCU_WPD_M (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S) +#define IO_MUX_GPIO44_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO44_MCU_WPD_S 2 +/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO44_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO44_MCU_WPU_M (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S) +#define IO_MUX_GPIO44_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO44_MCU_WPU_S 3 +/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO44_MCU_IE (BIT(4)) +#define IO_MUX_GPIO44_MCU_IE_M (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S) +#define IO_MUX_GPIO44_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO44_MCU_IE_S 4 +/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO44_MCU_DRV 0x00000003U +#define IO_MUX_GPIO44_MCU_DRV_M (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S) +#define IO_MUX_GPIO44_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO44_MCU_DRV_S 5 +/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO44_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO44_FUN_WPD_M (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S) +#define IO_MUX_GPIO44_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO44_FUN_WPD_S 7 +/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO44_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO44_FUN_WPU_M (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S) +#define IO_MUX_GPIO44_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO44_FUN_WPU_S 8 +/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO44_FUN_IE (BIT(9)) +#define IO_MUX_GPIO44_FUN_IE_M (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S) +#define IO_MUX_GPIO44_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO44_FUN_IE_S 9 +/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO44_FUN_DRV 0x00000003U +#define IO_MUX_GPIO44_FUN_DRV_M (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S) +#define IO_MUX_GPIO44_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO44_FUN_DRV_S 10 +/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO44_MCU_SEL 0x00000007U +#define IO_MUX_GPIO44_MCU_SEL_M (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S) +#define IO_MUX_GPIO44_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO44_MCU_SEL_S 12 +/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO44_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO44_FILTER_EN_M (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S) +#define IO_MUX_GPIO44_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO44_FILTER_EN_S 15 + +/** IO_MUX_gpio45_REG register + * iomux control register for gpio45 + */ +#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8) +/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO45_MCU_OE (BIT(0)) +#define IO_MUX_GPIO45_MCU_OE_M (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S) +#define IO_MUX_GPIO45_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO45_MCU_OE_S 0 +/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO45_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO45_SLP_SEL_M (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S) +#define IO_MUX_GPIO45_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO45_SLP_SEL_S 1 +/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO45_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO45_MCU_WPD_M (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S) +#define IO_MUX_GPIO45_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO45_MCU_WPD_S 2 +/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO45_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO45_MCU_WPU_M (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S) +#define IO_MUX_GPIO45_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO45_MCU_WPU_S 3 +/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO45_MCU_IE (BIT(4)) +#define IO_MUX_GPIO45_MCU_IE_M (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S) +#define IO_MUX_GPIO45_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO45_MCU_IE_S 4 +/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO45_MCU_DRV 0x00000003U +#define IO_MUX_GPIO45_MCU_DRV_M (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S) +#define IO_MUX_GPIO45_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO45_MCU_DRV_S 5 +/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO45_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO45_FUN_WPD_M (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S) +#define IO_MUX_GPIO45_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO45_FUN_WPD_S 7 +/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO45_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO45_FUN_WPU_M (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S) +#define IO_MUX_GPIO45_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO45_FUN_WPU_S 8 +/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO45_FUN_IE (BIT(9)) +#define IO_MUX_GPIO45_FUN_IE_M (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S) +#define IO_MUX_GPIO45_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO45_FUN_IE_S 9 +/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO45_FUN_DRV 0x00000003U +#define IO_MUX_GPIO45_FUN_DRV_M (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S) +#define IO_MUX_GPIO45_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO45_FUN_DRV_S 10 +/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO45_MCU_SEL 0x00000007U +#define IO_MUX_GPIO45_MCU_SEL_M (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S) +#define IO_MUX_GPIO45_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO45_MCU_SEL_S 12 +/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO45_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO45_FILTER_EN_M (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S) +#define IO_MUX_GPIO45_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO45_FILTER_EN_S 15 + +/** IO_MUX_gpio46_REG register + * iomux control register for gpio46 + */ +#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc) +/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO46_MCU_OE (BIT(0)) +#define IO_MUX_GPIO46_MCU_OE_M (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S) +#define IO_MUX_GPIO46_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO46_MCU_OE_S 0 +/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO46_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO46_SLP_SEL_M (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S) +#define IO_MUX_GPIO46_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO46_SLP_SEL_S 1 +/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO46_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO46_MCU_WPD_M (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S) +#define IO_MUX_GPIO46_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO46_MCU_WPD_S 2 +/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO46_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO46_MCU_WPU_M (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S) +#define IO_MUX_GPIO46_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO46_MCU_WPU_S 3 +/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO46_MCU_IE (BIT(4)) +#define IO_MUX_GPIO46_MCU_IE_M (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S) +#define IO_MUX_GPIO46_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO46_MCU_IE_S 4 +/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO46_MCU_DRV 0x00000003U +#define IO_MUX_GPIO46_MCU_DRV_M (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S) +#define IO_MUX_GPIO46_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO46_MCU_DRV_S 5 +/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO46_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO46_FUN_WPD_M (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S) +#define IO_MUX_GPIO46_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO46_FUN_WPD_S 7 +/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO46_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO46_FUN_WPU_M (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S) +#define IO_MUX_GPIO46_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO46_FUN_WPU_S 8 +/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO46_FUN_IE (BIT(9)) +#define IO_MUX_GPIO46_FUN_IE_M (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S) +#define IO_MUX_GPIO46_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO46_FUN_IE_S 9 +/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO46_FUN_DRV 0x00000003U +#define IO_MUX_GPIO46_FUN_DRV_M (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S) +#define IO_MUX_GPIO46_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO46_FUN_DRV_S 10 +/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO46_MCU_SEL 0x00000007U +#define IO_MUX_GPIO46_MCU_SEL_M (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S) +#define IO_MUX_GPIO46_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO46_MCU_SEL_S 12 +/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO46_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO46_FILTER_EN_M (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S) +#define IO_MUX_GPIO46_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO46_FILTER_EN_S 15 + +/** IO_MUX_gpio47_REG register + * iomux control register for gpio47 + */ +#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0) +/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO47_MCU_OE (BIT(0)) +#define IO_MUX_GPIO47_MCU_OE_M (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S) +#define IO_MUX_GPIO47_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO47_MCU_OE_S 0 +/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO47_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO47_SLP_SEL_M (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S) +#define IO_MUX_GPIO47_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO47_SLP_SEL_S 1 +/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO47_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO47_MCU_WPD_M (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S) +#define IO_MUX_GPIO47_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO47_MCU_WPD_S 2 +/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO47_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO47_MCU_WPU_M (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S) +#define IO_MUX_GPIO47_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO47_MCU_WPU_S 3 +/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO47_MCU_IE (BIT(4)) +#define IO_MUX_GPIO47_MCU_IE_M (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S) +#define IO_MUX_GPIO47_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO47_MCU_IE_S 4 +/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO47_MCU_DRV 0x00000003U +#define IO_MUX_GPIO47_MCU_DRV_M (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S) +#define IO_MUX_GPIO47_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO47_MCU_DRV_S 5 +/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO47_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO47_FUN_WPD_M (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S) +#define IO_MUX_GPIO47_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO47_FUN_WPD_S 7 +/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO47_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO47_FUN_WPU_M (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S) +#define IO_MUX_GPIO47_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO47_FUN_WPU_S 8 +/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO47_FUN_IE (BIT(9)) +#define IO_MUX_GPIO47_FUN_IE_M (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S) +#define IO_MUX_GPIO47_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO47_FUN_IE_S 9 +/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO47_FUN_DRV 0x00000003U +#define IO_MUX_GPIO47_FUN_DRV_M (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S) +#define IO_MUX_GPIO47_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO47_FUN_DRV_S 10 +/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO47_MCU_SEL 0x00000007U +#define IO_MUX_GPIO47_MCU_SEL_M (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S) +#define IO_MUX_GPIO47_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO47_MCU_SEL_S 12 +/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO47_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO47_FILTER_EN_M (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S) +#define IO_MUX_GPIO47_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO47_FILTER_EN_S 15 + +/** IO_MUX_gpio48_REG register + * iomux control register for gpio48 + */ +#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4) +/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO48_MCU_OE (BIT(0)) +#define IO_MUX_GPIO48_MCU_OE_M (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S) +#define IO_MUX_GPIO48_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO48_MCU_OE_S 0 +/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO48_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO48_SLP_SEL_M (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S) +#define IO_MUX_GPIO48_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO48_SLP_SEL_S 1 +/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO48_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO48_MCU_WPD_M (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S) +#define IO_MUX_GPIO48_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO48_MCU_WPD_S 2 +/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO48_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO48_MCU_WPU_M (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S) +#define IO_MUX_GPIO48_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO48_MCU_WPU_S 3 +/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO48_MCU_IE (BIT(4)) +#define IO_MUX_GPIO48_MCU_IE_M (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S) +#define IO_MUX_GPIO48_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO48_MCU_IE_S 4 +/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO48_MCU_DRV 0x00000003U +#define IO_MUX_GPIO48_MCU_DRV_M (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S) +#define IO_MUX_GPIO48_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO48_MCU_DRV_S 5 +/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO48_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO48_FUN_WPD_M (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S) +#define IO_MUX_GPIO48_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO48_FUN_WPD_S 7 +/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO48_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO48_FUN_WPU_M (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S) +#define IO_MUX_GPIO48_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO48_FUN_WPU_S 8 +/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO48_FUN_IE (BIT(9)) +#define IO_MUX_GPIO48_FUN_IE_M (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S) +#define IO_MUX_GPIO48_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO48_FUN_IE_S 9 +/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO48_FUN_DRV 0x00000003U +#define IO_MUX_GPIO48_FUN_DRV_M (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S) +#define IO_MUX_GPIO48_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO48_FUN_DRV_S 10 +/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO48_MCU_SEL 0x00000007U +#define IO_MUX_GPIO48_MCU_SEL_M (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S) +#define IO_MUX_GPIO48_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO48_MCU_SEL_S 12 +/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO48_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO48_FILTER_EN_M (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S) +#define IO_MUX_GPIO48_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO48_FILTER_EN_S 15 + +/** IO_MUX_gpio49_REG register + * iomux control register for gpio49 + */ +#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8) +/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO49_MCU_OE (BIT(0)) +#define IO_MUX_GPIO49_MCU_OE_M (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S) +#define IO_MUX_GPIO49_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO49_MCU_OE_S 0 +/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO49_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO49_SLP_SEL_M (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S) +#define IO_MUX_GPIO49_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO49_SLP_SEL_S 1 +/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO49_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO49_MCU_WPD_M (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S) +#define IO_MUX_GPIO49_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO49_MCU_WPD_S 2 +/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO49_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO49_MCU_WPU_M (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S) +#define IO_MUX_GPIO49_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO49_MCU_WPU_S 3 +/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO49_MCU_IE (BIT(4)) +#define IO_MUX_GPIO49_MCU_IE_M (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S) +#define IO_MUX_GPIO49_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO49_MCU_IE_S 4 +/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO49_MCU_DRV 0x00000003U +#define IO_MUX_GPIO49_MCU_DRV_M (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S) +#define IO_MUX_GPIO49_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO49_MCU_DRV_S 5 +/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO49_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO49_FUN_WPD_M (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S) +#define IO_MUX_GPIO49_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO49_FUN_WPD_S 7 +/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO49_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO49_FUN_WPU_M (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S) +#define IO_MUX_GPIO49_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO49_FUN_WPU_S 8 +/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO49_FUN_IE (BIT(9)) +#define IO_MUX_GPIO49_FUN_IE_M (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S) +#define IO_MUX_GPIO49_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO49_FUN_IE_S 9 +/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO49_FUN_DRV 0x00000003U +#define IO_MUX_GPIO49_FUN_DRV_M (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S) +#define IO_MUX_GPIO49_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO49_FUN_DRV_S 10 +/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO49_MCU_SEL 0x00000007U +#define IO_MUX_GPIO49_MCU_SEL_M (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S) +#define IO_MUX_GPIO49_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO49_MCU_SEL_S 12 +/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO49_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO49_FILTER_EN_M (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S) +#define IO_MUX_GPIO49_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO49_FILTER_EN_S 15 + +/** IO_MUX_gpio50_REG register + * iomux control register for gpio50 + */ +#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc) +/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO50_MCU_OE (BIT(0)) +#define IO_MUX_GPIO50_MCU_OE_M (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S) +#define IO_MUX_GPIO50_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO50_MCU_OE_S 0 +/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO50_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO50_SLP_SEL_M (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S) +#define IO_MUX_GPIO50_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO50_SLP_SEL_S 1 +/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO50_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO50_MCU_WPD_M (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S) +#define IO_MUX_GPIO50_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO50_MCU_WPD_S 2 +/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO50_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO50_MCU_WPU_M (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S) +#define IO_MUX_GPIO50_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO50_MCU_WPU_S 3 +/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO50_MCU_IE (BIT(4)) +#define IO_MUX_GPIO50_MCU_IE_M (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S) +#define IO_MUX_GPIO50_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO50_MCU_IE_S 4 +/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO50_MCU_DRV 0x00000003U +#define IO_MUX_GPIO50_MCU_DRV_M (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S) +#define IO_MUX_GPIO50_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO50_MCU_DRV_S 5 +/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO50_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO50_FUN_WPD_M (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S) +#define IO_MUX_GPIO50_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO50_FUN_WPD_S 7 +/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO50_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO50_FUN_WPU_M (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S) +#define IO_MUX_GPIO50_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO50_FUN_WPU_S 8 +/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO50_FUN_IE (BIT(9)) +#define IO_MUX_GPIO50_FUN_IE_M (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S) +#define IO_MUX_GPIO50_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO50_FUN_IE_S 9 +/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO50_FUN_DRV 0x00000003U +#define IO_MUX_GPIO50_FUN_DRV_M (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S) +#define IO_MUX_GPIO50_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO50_FUN_DRV_S 10 +/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO50_MCU_SEL 0x00000007U +#define IO_MUX_GPIO50_MCU_SEL_M (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S) +#define IO_MUX_GPIO50_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO50_MCU_SEL_S 12 +/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO50_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO50_FILTER_EN_M (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S) +#define IO_MUX_GPIO50_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO50_FILTER_EN_S 15 + +/** IO_MUX_gpio51_REG register + * iomux control register for gpio51 + */ +#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0) +/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO51_MCU_OE (BIT(0)) +#define IO_MUX_GPIO51_MCU_OE_M (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S) +#define IO_MUX_GPIO51_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO51_MCU_OE_S 0 +/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO51_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO51_SLP_SEL_M (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S) +#define IO_MUX_GPIO51_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO51_SLP_SEL_S 1 +/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO51_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO51_MCU_WPD_M (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S) +#define IO_MUX_GPIO51_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO51_MCU_WPD_S 2 +/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO51_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO51_MCU_WPU_M (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S) +#define IO_MUX_GPIO51_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO51_MCU_WPU_S 3 +/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO51_MCU_IE (BIT(4)) +#define IO_MUX_GPIO51_MCU_IE_M (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S) +#define IO_MUX_GPIO51_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO51_MCU_IE_S 4 +/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO51_MCU_DRV 0x00000003U +#define IO_MUX_GPIO51_MCU_DRV_M (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S) +#define IO_MUX_GPIO51_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO51_MCU_DRV_S 5 +/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO51_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO51_FUN_WPD_M (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S) +#define IO_MUX_GPIO51_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO51_FUN_WPD_S 7 +/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO51_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO51_FUN_WPU_M (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S) +#define IO_MUX_GPIO51_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO51_FUN_WPU_S 8 +/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO51_FUN_IE (BIT(9)) +#define IO_MUX_GPIO51_FUN_IE_M (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S) +#define IO_MUX_GPIO51_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO51_FUN_IE_S 9 +/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO51_FUN_DRV 0x00000003U +#define IO_MUX_GPIO51_FUN_DRV_M (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S) +#define IO_MUX_GPIO51_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO51_FUN_DRV_S 10 +/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO51_MCU_SEL 0x00000007U +#define IO_MUX_GPIO51_MCU_SEL_M (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S) +#define IO_MUX_GPIO51_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO51_MCU_SEL_S 12 +/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO51_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO51_FILTER_EN_M (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S) +#define IO_MUX_GPIO51_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO51_FILTER_EN_S 15 + +/** IO_MUX_gpio52_REG register + * iomux control register for gpio52 + */ +#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4) +/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO52_MCU_OE (BIT(0)) +#define IO_MUX_GPIO52_MCU_OE_M (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S) +#define IO_MUX_GPIO52_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO52_MCU_OE_S 0 +/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO52_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO52_SLP_SEL_M (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S) +#define IO_MUX_GPIO52_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO52_SLP_SEL_S 1 +/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO52_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO52_MCU_WPD_M (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S) +#define IO_MUX_GPIO52_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO52_MCU_WPD_S 2 +/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO52_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO52_MCU_WPU_M (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S) +#define IO_MUX_GPIO52_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO52_MCU_WPU_S 3 +/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO52_MCU_IE (BIT(4)) +#define IO_MUX_GPIO52_MCU_IE_M (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S) +#define IO_MUX_GPIO52_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO52_MCU_IE_S 4 +/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO52_MCU_DRV 0x00000003U +#define IO_MUX_GPIO52_MCU_DRV_M (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S) +#define IO_MUX_GPIO52_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO52_MCU_DRV_S 5 +/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO52_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO52_FUN_WPD_M (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S) +#define IO_MUX_GPIO52_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO52_FUN_WPD_S 7 +/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO52_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO52_FUN_WPU_M (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S) +#define IO_MUX_GPIO52_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO52_FUN_WPU_S 8 +/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO52_FUN_IE (BIT(9)) +#define IO_MUX_GPIO52_FUN_IE_M (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S) +#define IO_MUX_GPIO52_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO52_FUN_IE_S 9 +/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO52_FUN_DRV 0x00000003U +#define IO_MUX_GPIO52_FUN_DRV_M (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S) +#define IO_MUX_GPIO52_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO52_FUN_DRV_S 10 +/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO52_MCU_SEL 0x00000007U +#define IO_MUX_GPIO52_MCU_SEL_M (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S) +#define IO_MUX_GPIO52_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO52_MCU_SEL_S 12 +/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO52_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO52_FILTER_EN_M (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S) +#define IO_MUX_GPIO52_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO52_FILTER_EN_S 15 + +/** IO_MUX_gpio53_REG register + * iomux control register for gpio53 + */ +#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8) +/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO53_MCU_OE (BIT(0)) +#define IO_MUX_GPIO53_MCU_OE_M (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S) +#define IO_MUX_GPIO53_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO53_MCU_OE_S 0 +/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO53_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO53_SLP_SEL_M (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S) +#define IO_MUX_GPIO53_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO53_SLP_SEL_S 1 +/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO53_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO53_MCU_WPD_M (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S) +#define IO_MUX_GPIO53_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO53_MCU_WPD_S 2 +/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO53_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO53_MCU_WPU_M (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S) +#define IO_MUX_GPIO53_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO53_MCU_WPU_S 3 +/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO53_MCU_IE (BIT(4)) +#define IO_MUX_GPIO53_MCU_IE_M (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S) +#define IO_MUX_GPIO53_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO53_MCU_IE_S 4 +/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO53_MCU_DRV 0x00000003U +#define IO_MUX_GPIO53_MCU_DRV_M (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S) +#define IO_MUX_GPIO53_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO53_MCU_DRV_S 5 +/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO53_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO53_FUN_WPD_M (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S) +#define IO_MUX_GPIO53_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO53_FUN_WPD_S 7 +/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO53_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO53_FUN_WPU_M (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S) +#define IO_MUX_GPIO53_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO53_FUN_WPU_S 8 +/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO53_FUN_IE (BIT(9)) +#define IO_MUX_GPIO53_FUN_IE_M (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S) +#define IO_MUX_GPIO53_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO53_FUN_IE_S 9 +/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO53_FUN_DRV 0x00000003U +#define IO_MUX_GPIO53_FUN_DRV_M (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S) +#define IO_MUX_GPIO53_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO53_FUN_DRV_S 10 +/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO53_MCU_SEL 0x00000007U +#define IO_MUX_GPIO53_MCU_SEL_M (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S) +#define IO_MUX_GPIO53_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO53_MCU_SEL_S 12 +/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO53_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO53_FILTER_EN_M (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S) +#define IO_MUX_GPIO53_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO53_FILTER_EN_S 15 + +/** IO_MUX_gpio54_REG register + * iomux control register for gpio54 + */ +#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc) +/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO54_MCU_OE (BIT(0)) +#define IO_MUX_GPIO54_MCU_OE_M (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S) +#define IO_MUX_GPIO54_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO54_MCU_OE_S 0 +/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO54_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO54_SLP_SEL_M (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S) +#define IO_MUX_GPIO54_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO54_SLP_SEL_S 1 +/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO54_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO54_MCU_WPD_M (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S) +#define IO_MUX_GPIO54_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO54_MCU_WPD_S 2 +/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO54_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO54_MCU_WPU_M (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S) +#define IO_MUX_GPIO54_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO54_MCU_WPU_S 3 +/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO54_MCU_IE (BIT(4)) +#define IO_MUX_GPIO54_MCU_IE_M (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S) +#define IO_MUX_GPIO54_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO54_MCU_IE_S 4 +/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO54_MCU_DRV 0x00000003U +#define IO_MUX_GPIO54_MCU_DRV_M (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S) +#define IO_MUX_GPIO54_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO54_MCU_DRV_S 5 +/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO54_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO54_FUN_WPD_M (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S) +#define IO_MUX_GPIO54_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO54_FUN_WPD_S 7 +/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO54_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO54_FUN_WPU_M (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S) +#define IO_MUX_GPIO54_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO54_FUN_WPU_S 8 +/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO54_FUN_IE (BIT(9)) +#define IO_MUX_GPIO54_FUN_IE_M (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S) +#define IO_MUX_GPIO54_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO54_FUN_IE_S 9 +/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO54_FUN_DRV 0x00000003U +#define IO_MUX_GPIO54_FUN_DRV_M (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S) +#define IO_MUX_GPIO54_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO54_FUN_DRV_S 10 +/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO54_MCU_SEL 0x00000007U +#define IO_MUX_GPIO54_MCU_SEL_M (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S) +#define IO_MUX_GPIO54_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO54_MCU_SEL_S 12 +/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO54_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO54_FILTER_EN_M (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S) +#define IO_MUX_GPIO54_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO54_FILTER_EN_S 15 + +/** IO_MUX_gpio55_REG register + * iomux control register for gpio55 + */ +#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0) +/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO55_MCU_OE (BIT(0)) +#define IO_MUX_GPIO55_MCU_OE_M (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S) +#define IO_MUX_GPIO55_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO55_MCU_OE_S 0 +/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO55_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO55_SLP_SEL_M (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S) +#define IO_MUX_GPIO55_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO55_SLP_SEL_S 1 +/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO55_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO55_MCU_WPD_M (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S) +#define IO_MUX_GPIO55_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO55_MCU_WPD_S 2 +/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO55_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO55_MCU_WPU_M (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S) +#define IO_MUX_GPIO55_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO55_MCU_WPU_S 3 +/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO55_MCU_IE (BIT(4)) +#define IO_MUX_GPIO55_MCU_IE_M (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S) +#define IO_MUX_GPIO55_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO55_MCU_IE_S 4 +/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO55_MCU_DRV 0x00000003U +#define IO_MUX_GPIO55_MCU_DRV_M (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S) +#define IO_MUX_GPIO55_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO55_MCU_DRV_S 5 +/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO55_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO55_FUN_WPD_M (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S) +#define IO_MUX_GPIO55_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO55_FUN_WPD_S 7 +/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO55_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO55_FUN_WPU_M (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S) +#define IO_MUX_GPIO55_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO55_FUN_WPU_S 8 +/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO55_FUN_IE (BIT(9)) +#define IO_MUX_GPIO55_FUN_IE_M (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S) +#define IO_MUX_GPIO55_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO55_FUN_IE_S 9 +/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO55_FUN_DRV 0x00000003U +#define IO_MUX_GPIO55_FUN_DRV_M (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S) +#define IO_MUX_GPIO55_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO55_FUN_DRV_S 10 +/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO55_MCU_SEL 0x00000007U +#define IO_MUX_GPIO55_MCU_SEL_M (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S) +#define IO_MUX_GPIO55_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO55_MCU_SEL_S 12 +/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO55_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO55_FILTER_EN_M (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S) +#define IO_MUX_GPIO55_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO55_FILTER_EN_S 15 + +/** IO_MUX_gpio56_REG register + * iomux control register for gpio56 + */ +#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4) +/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ +#define IO_MUX_GPIO56_MCU_OE (BIT(0)) +#define IO_MUX_GPIO56_MCU_OE_M (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S) +#define IO_MUX_GPIO56_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO56_MCU_OE_S 0 +/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ +#define IO_MUX_GPIO56_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO56_SLP_SEL_M (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S) +#define IO_MUX_GPIO56_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO56_SLP_SEL_S 1 +/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ +#define IO_MUX_GPIO56_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO56_MCU_WPD_M (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S) +#define IO_MUX_GPIO56_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO56_MCU_WPD_S 2 +/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ +#define IO_MUX_GPIO56_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO56_MCU_WPU_M (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S) +#define IO_MUX_GPIO56_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO56_MCU_WPU_S 3 +/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ +#define IO_MUX_GPIO56_MCU_IE (BIT(4)) +#define IO_MUX_GPIO56_MCU_IE_M (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S) +#define IO_MUX_GPIO56_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO56_MCU_IE_S 4 +/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ +#define IO_MUX_GPIO56_MCU_DRV 0x00000003U +#define IO_MUX_GPIO56_MCU_DRV_M (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S) +#define IO_MUX_GPIO56_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO56_MCU_DRV_S 5 +/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ +#define IO_MUX_GPIO56_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO56_FUN_WPD_M (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S) +#define IO_MUX_GPIO56_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO56_FUN_WPD_S 7 +/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ +#define IO_MUX_GPIO56_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO56_FUN_WPU_M (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S) +#define IO_MUX_GPIO56_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO56_FUN_WPU_S 8 +/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0; + * input enable + */ +#define IO_MUX_GPIO56_FUN_IE (BIT(9)) +#define IO_MUX_GPIO56_FUN_IE_M (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S) +#define IO_MUX_GPIO56_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO56_FUN_IE_S 9 +/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ +#define IO_MUX_GPIO56_FUN_DRV 0x00000003U +#define IO_MUX_GPIO56_FUN_DRV_M (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S) +#define IO_MUX_GPIO56_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO56_FUN_DRV_S 10 +/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ +#define IO_MUX_GPIO56_MCU_SEL 0x00000007U +#define IO_MUX_GPIO56_MCU_SEL_M (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S) +#define IO_MUX_GPIO56_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO56_MCU_SEL_S 12 +/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0; + * input filter enable + */ +#define IO_MUX_GPIO56_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO56_FILTER_EN_M (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S) +#define IO_MUX_GPIO56_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO56_FILTER_EN_S 15 + +/** IO_MUX_DATE_REG register + * iomux version + */ +#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104) +/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794; + * csv date + */ +#define IO_MUX_DATE 0x0FFFFFFFU +#define IO_MUX_DATE_M (IO_MUX_DATE_V << IO_MUX_DATE_S) +#define IO_MUX_DATE_V 0x0FFFFFFFU +#define IO_MUX_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/io_mux_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_eco5_struct.h new file mode 100644 index 0000000000..0ebee78c34 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_eco5_struct.h @@ -0,0 +1,3430 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: IOMUX Register */ +/** Type of gpio0 register + * iomux control register for gpio0 + */ +typedef union { + struct { + /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio0_mcu_oe:1; + /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio0_slp_sel:1; + /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio0_mcu_wpd:1; + /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio0_mcu_wpu:1; + /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio0_mcu_ie:1; + /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio0_mcu_drv:2; + /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio0_fun_wpd:1; + /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio0_fun_wpu:1; + /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio0_fun_ie:1; + /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio0_fun_drv:2; + /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio0_mcu_sel:3; + /** gpio0_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio0_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio0_reg_t; + +/** Type of gpio1 register + * iomux control register for gpio1 + */ +typedef union { + struct { + /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio1_mcu_oe:1; + /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio1_slp_sel:1; + /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio1_mcu_wpd:1; + /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio1_mcu_wpu:1; + /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio1_mcu_ie:1; + /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio1_mcu_drv:2; + /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio1_fun_wpd:1; + /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio1_fun_wpu:1; + /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio1_fun_ie:1; + /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio1_fun_drv:2; + /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio1_mcu_sel:3; + /** gpio1_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio1_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio1_reg_t; + +/** Type of gpio2 register + * iomux control register for gpio2 + */ +typedef union { + struct { + /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio2_mcu_oe:1; + /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio2_slp_sel:1; + /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio2_mcu_wpd:1; + /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio2_mcu_wpu:1; + /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio2_mcu_ie:1; + /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio2_mcu_drv:2; + /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio2_fun_wpd:1; + /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio2_fun_wpu:1; + /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio2_fun_ie:1; + /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio2_fun_drv:2; + /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio2_mcu_sel:3; + /** gpio2_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio2_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio2_reg_t; + +/** Type of gpio3 register + * iomux control register for gpio3 + */ +typedef union { + struct { + /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio3_mcu_oe:1; + /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio3_slp_sel:1; + /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio3_mcu_wpd:1; + /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio3_mcu_wpu:1; + /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio3_mcu_ie:1; + /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio3_mcu_drv:2; + /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio3_fun_wpd:1; + /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio3_fun_wpu:1; + /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio3_fun_ie:1; + /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio3_fun_drv:2; + /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio3_mcu_sel:3; + /** gpio3_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio3_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio3_reg_t; + +/** Type of gpio4 register + * iomux control register for gpio4 + */ +typedef union { + struct { + /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio4_mcu_oe:1; + /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio4_slp_sel:1; + /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio4_mcu_wpd:1; + /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio4_mcu_wpu:1; + /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio4_mcu_ie:1; + /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio4_mcu_drv:2; + /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio4_fun_wpd:1; + /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio4_fun_wpu:1; + /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio4_fun_ie:1; + /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio4_fun_drv:2; + /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio4_mcu_sel:3; + /** gpio4_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio4_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio4_reg_t; + +/** Type of gpio5 register + * iomux control register for gpio5 + */ +typedef union { + struct { + /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio5_mcu_oe:1; + /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio5_slp_sel:1; + /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio5_mcu_wpd:1; + /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio5_mcu_wpu:1; + /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio5_mcu_ie:1; + /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio5_mcu_drv:2; + /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio5_fun_wpd:1; + /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio5_fun_wpu:1; + /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio5_fun_ie:1; + /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio5_fun_drv:2; + /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio5_mcu_sel:3; + /** gpio5_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio5_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio5_reg_t; + +/** Type of gpio6 register + * iomux control register for gpio6 + */ +typedef union { + struct { + /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio6_mcu_oe:1; + /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio6_slp_sel:1; + /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio6_mcu_wpd:1; + /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio6_mcu_wpu:1; + /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio6_mcu_ie:1; + /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio6_mcu_drv:2; + /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio6_fun_wpd:1; + /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio6_fun_wpu:1; + /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio6_fun_ie:1; + /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio6_fun_drv:2; + /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio6_mcu_sel:3; + /** gpio6_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio6_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio6_reg_t; + +/** Type of gpio7 register + * iomux control register for gpio7 + */ +typedef union { + struct { + /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio7_mcu_oe:1; + /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio7_slp_sel:1; + /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio7_mcu_wpd:1; + /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio7_mcu_wpu:1; + /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio7_mcu_ie:1; + /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio7_mcu_drv:2; + /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio7_fun_wpd:1; + /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio7_fun_wpu:1; + /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio7_fun_ie:1; + /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio7_fun_drv:2; + /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio7_mcu_sel:3; + /** gpio7_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio7_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio7_reg_t; + +/** Type of gpio8 register + * iomux control register for gpio8 + */ +typedef union { + struct { + /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio8_mcu_oe:1; + /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio8_slp_sel:1; + /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio8_mcu_wpd:1; + /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio8_mcu_wpu:1; + /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio8_mcu_ie:1; + /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio8_mcu_drv:2; + /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio8_fun_wpd:1; + /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio8_fun_wpu:1; + /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio8_fun_ie:1; + /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio8_fun_drv:2; + /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio8_mcu_sel:3; + /** gpio8_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio8_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio8_reg_t; + +/** Type of gpio9 register + * iomux control register for gpio9 + */ +typedef union { + struct { + /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio9_mcu_oe:1; + /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio9_slp_sel:1; + /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio9_mcu_wpd:1; + /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio9_mcu_wpu:1; + /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio9_mcu_ie:1; + /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio9_mcu_drv:2; + /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio9_fun_wpd:1; + /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio9_fun_wpu:1; + /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio9_fun_ie:1; + /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio9_fun_drv:2; + /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio9_mcu_sel:3; + /** gpio9_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio9_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio9_reg_t; + +/** Type of gpio10 register + * iomux control register for gpio10 + */ +typedef union { + struct { + /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio10_mcu_oe:1; + /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio10_slp_sel:1; + /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio10_mcu_wpd:1; + /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio10_mcu_wpu:1; + /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio10_mcu_ie:1; + /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio10_mcu_drv:2; + /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio10_fun_wpd:1; + /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio10_fun_wpu:1; + /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio10_fun_ie:1; + /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio10_fun_drv:2; + /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio10_mcu_sel:3; + /** gpio10_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio10_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio10_reg_t; + +/** Type of gpio11 register + * iomux control register for gpio11 + */ +typedef union { + struct { + /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio11_mcu_oe:1; + /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio11_slp_sel:1; + /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio11_mcu_wpd:1; + /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio11_mcu_wpu:1; + /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio11_mcu_ie:1; + /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio11_mcu_drv:2; + /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio11_fun_wpd:1; + /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio11_fun_wpu:1; + /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio11_fun_ie:1; + /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio11_fun_drv:2; + /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio11_mcu_sel:3; + /** gpio11_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio11_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio11_reg_t; + +/** Type of gpio12 register + * iomux control register for gpio12 + */ +typedef union { + struct { + /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio12_mcu_oe:1; + /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio12_slp_sel:1; + /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio12_mcu_wpd:1; + /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio12_mcu_wpu:1; + /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio12_mcu_ie:1; + /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio12_mcu_drv:2; + /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio12_fun_wpd:1; + /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio12_fun_wpu:1; + /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio12_fun_ie:1; + /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio12_fun_drv:2; + /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio12_mcu_sel:3; + /** gpio12_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio12_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio12_reg_t; + +/** Type of gpio13 register + * iomux control register for gpio13 + */ +typedef union { + struct { + /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio13_mcu_oe:1; + /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio13_slp_sel:1; + /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio13_mcu_wpd:1; + /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio13_mcu_wpu:1; + /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio13_mcu_ie:1; + /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio13_mcu_drv:2; + /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio13_fun_wpd:1; + /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio13_fun_wpu:1; + /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio13_fun_ie:1; + /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio13_fun_drv:2; + /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio13_mcu_sel:3; + /** gpio13_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio13_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio13_reg_t; + +/** Type of gpio14 register + * iomux control register for gpio14 + */ +typedef union { + struct { + /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio14_mcu_oe:1; + /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio14_slp_sel:1; + /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio14_mcu_wpd:1; + /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio14_mcu_wpu:1; + /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio14_mcu_ie:1; + /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio14_mcu_drv:2; + /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio14_fun_wpd:1; + /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio14_fun_wpu:1; + /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio14_fun_ie:1; + /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio14_fun_drv:2; + /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio14_mcu_sel:3; + /** gpio14_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio14_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio14_reg_t; + +/** Type of gpio15 register + * iomux control register for gpio15 + */ +typedef union { + struct { + /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio15_mcu_oe:1; + /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio15_slp_sel:1; + /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio15_mcu_wpd:1; + /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio15_mcu_wpu:1; + /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio15_mcu_ie:1; + /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio15_mcu_drv:2; + /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio15_fun_wpd:1; + /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio15_fun_wpu:1; + /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio15_fun_ie:1; + /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio15_fun_drv:2; + /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio15_mcu_sel:3; + /** gpio15_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio15_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio15_reg_t; + +/** Type of gpio16 register + * iomux control register for gpio16 + */ +typedef union { + struct { + /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio16_mcu_oe:1; + /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio16_slp_sel:1; + /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio16_mcu_wpd:1; + /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio16_mcu_wpu:1; + /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio16_mcu_ie:1; + /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio16_mcu_drv:2; + /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio16_fun_wpd:1; + /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio16_fun_wpu:1; + /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio16_fun_ie:1; + /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio16_fun_drv:2; + /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio16_mcu_sel:3; + /** gpio16_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio16_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio16_reg_t; + +/** Type of gpio17 register + * iomux control register for gpio17 + */ +typedef union { + struct { + /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio17_mcu_oe:1; + /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio17_slp_sel:1; + /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio17_mcu_wpd:1; + /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio17_mcu_wpu:1; + /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio17_mcu_ie:1; + /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio17_mcu_drv:2; + /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio17_fun_wpd:1; + /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio17_fun_wpu:1; + /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio17_fun_ie:1; + /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio17_fun_drv:2; + /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio17_mcu_sel:3; + /** gpio17_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio17_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio17_reg_t; + +/** Type of gpio18 register + * iomux control register for gpio18 + */ +typedef union { + struct { + /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio18_mcu_oe:1; + /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio18_slp_sel:1; + /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio18_mcu_wpd:1; + /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio18_mcu_wpu:1; + /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio18_mcu_ie:1; + /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio18_mcu_drv:2; + /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio18_fun_wpd:1; + /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio18_fun_wpu:1; + /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio18_fun_ie:1; + /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio18_fun_drv:2; + /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio18_mcu_sel:3; + /** gpio18_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio18_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio18_reg_t; + +/** Type of gpio19 register + * iomux control register for gpio19 + */ +typedef union { + struct { + /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio19_mcu_oe:1; + /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio19_slp_sel:1; + /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio19_mcu_wpd:1; + /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio19_mcu_wpu:1; + /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio19_mcu_ie:1; + /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio19_mcu_drv:2; + /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio19_fun_wpd:1; + /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio19_fun_wpu:1; + /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio19_fun_ie:1; + /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio19_fun_drv:2; + /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio19_mcu_sel:3; + /** gpio19_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio19_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio19_reg_t; + +/** Type of gpio20 register + * iomux control register for gpio20 + */ +typedef union { + struct { + /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio20_mcu_oe:1; + /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio20_slp_sel:1; + /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio20_mcu_wpd:1; + /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio20_mcu_wpu:1; + /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio20_mcu_ie:1; + /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio20_mcu_drv:2; + /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio20_fun_wpd:1; + /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio20_fun_wpu:1; + /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio20_fun_ie:1; + /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio20_fun_drv:2; + /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio20_mcu_sel:3; + /** gpio20_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio20_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio20_reg_t; + +/** Type of gpio21 register + * iomux control register for gpio21 + */ +typedef union { + struct { + /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio21_mcu_oe:1; + /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio21_slp_sel:1; + /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio21_mcu_wpd:1; + /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio21_mcu_wpu:1; + /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio21_mcu_ie:1; + /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio21_mcu_drv:2; + /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio21_fun_wpd:1; + /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio21_fun_wpu:1; + /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio21_fun_ie:1; + /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio21_fun_drv:2; + /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio21_mcu_sel:3; + /** gpio21_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio21_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio21_reg_t; + +/** Type of gpio22 register + * iomux control register for gpio22 + */ +typedef union { + struct { + /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio22_mcu_oe:1; + /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio22_slp_sel:1; + /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio22_mcu_wpd:1; + /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio22_mcu_wpu:1; + /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio22_mcu_ie:1; + /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio22_mcu_drv:2; + /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio22_fun_wpd:1; + /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio22_fun_wpu:1; + /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio22_fun_ie:1; + /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio22_fun_drv:2; + /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio22_mcu_sel:3; + /** gpio22_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio22_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio22_reg_t; + +/** Type of gpio23 register + * iomux control register for gpio23 + */ +typedef union { + struct { + /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio23_mcu_oe:1; + /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio23_slp_sel:1; + /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio23_mcu_wpd:1; + /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio23_mcu_wpu:1; + /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio23_mcu_ie:1; + /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio23_mcu_drv:2; + /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio23_fun_wpd:1; + /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio23_fun_wpu:1; + /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio23_fun_ie:1; + /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio23_fun_drv:2; + /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio23_mcu_sel:3; + /** gpio23_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio23_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio23_reg_t; + +/** Type of gpio24 register + * iomux control register for gpio24 + */ +typedef union { + struct { + /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio24_mcu_oe:1; + /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio24_slp_sel:1; + /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio24_mcu_wpd:1; + /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio24_mcu_wpu:1; + /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio24_mcu_ie:1; + /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio24_mcu_drv:2; + /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio24_fun_wpd:1; + /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio24_fun_wpu:1; + /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio24_fun_ie:1; + /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 3; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio24_fun_drv:2; + /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio24_mcu_sel:3; + /** gpio24_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio24_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio24_reg_t; + +/** Type of gpio25 register + * iomux control register for gpio25 + */ +typedef union { + struct { + /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio25_mcu_oe:1; + /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio25_slp_sel:1; + /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio25_mcu_wpd:1; + /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio25_mcu_wpu:1; + /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio25_mcu_ie:1; + /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio25_mcu_drv:2; + /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio25_fun_wpd:1; + /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio25_fun_wpu:1; + /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio25_fun_ie:1; + /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 3; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio25_fun_drv:2; + /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio25_mcu_sel:3; + /** gpio25_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio25_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio25_reg_t; + +/** Type of gpio26 register + * iomux control register for gpio26 + */ +typedef union { + struct { + /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio26_mcu_oe:1; + /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio26_slp_sel:1; + /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio26_mcu_wpd:1; + /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio26_mcu_wpu:1; + /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio26_mcu_ie:1; + /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio26_mcu_drv:2; + /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio26_fun_wpd:1; + /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio26_fun_wpu:1; + /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio26_fun_ie:1; + /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio26_fun_drv:2; + /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio26_mcu_sel:3; + /** gpio26_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio26_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio26_reg_t; + +/** Type of gpio27 register + * iomux control register for gpio27 + */ +typedef union { + struct { + /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio27_mcu_oe:1; + /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio27_slp_sel:1; + /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio27_mcu_wpd:1; + /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio27_mcu_wpu:1; + /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio27_mcu_ie:1; + /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio27_mcu_drv:2; + /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio27_fun_wpd:1; + /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio27_fun_wpu:1; + /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio27_fun_ie:1; + /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio27_fun_drv:2; + /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio27_mcu_sel:3; + /** gpio27_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio27_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio27_reg_t; + +/** Type of gpio28 register + * iomux control register for gpio28 + */ +typedef union { + struct { + /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio28_mcu_oe:1; + /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio28_slp_sel:1; + /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio28_mcu_wpd:1; + /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio28_mcu_wpu:1; + /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio28_mcu_ie:1; + /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio28_mcu_drv:2; + /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio28_fun_wpd:1; + /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio28_fun_wpu:1; + /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio28_fun_ie:1; + /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio28_fun_drv:2; + /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio28_mcu_sel:3; + /** gpio28_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio28_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio28_reg_t; + +/** Type of gpio29 register + * iomux control register for gpio29 + */ +typedef union { + struct { + /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio29_mcu_oe:1; + /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio29_slp_sel:1; + /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio29_mcu_wpd:1; + /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio29_mcu_wpu:1; + /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio29_mcu_ie:1; + /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio29_mcu_drv:2; + /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio29_fun_wpd:1; + /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio29_fun_wpu:1; + /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio29_fun_ie:1; + /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio29_fun_drv:2; + /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio29_mcu_sel:3; + /** gpio29_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio29_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio29_reg_t; + +/** Type of gpio30 register + * iomux control register for gpio30 + */ +typedef union { + struct { + /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio30_mcu_oe:1; + /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio30_slp_sel:1; + /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio30_mcu_wpd:1; + /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio30_mcu_wpu:1; + /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio30_mcu_ie:1; + /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio30_mcu_drv:2; + /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio30_fun_wpd:1; + /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio30_fun_wpu:1; + /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio30_fun_ie:1; + /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio30_fun_drv:2; + /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio30_mcu_sel:3; + /** gpio30_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio30_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio30_reg_t; + +/** Type of gpio31 register + * iomux control register for gpio31 + */ +typedef union { + struct { + /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio31_mcu_oe:1; + /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio31_slp_sel:1; + /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio31_mcu_wpd:1; + /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio31_mcu_wpu:1; + /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio31_mcu_ie:1; + /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio31_mcu_drv:2; + /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio31_fun_wpd:1; + /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio31_fun_wpu:1; + /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio31_fun_ie:1; + /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio31_fun_drv:2; + /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio31_mcu_sel:3; + /** gpio31_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio31_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio31_reg_t; + +/** Type of gpio32 register + * iomux control register for gpio32 + */ +typedef union { + struct { + /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio32_mcu_oe:1; + /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio32_slp_sel:1; + /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio32_mcu_wpd:1; + /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio32_mcu_wpu:1; + /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio32_mcu_ie:1; + /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio32_mcu_drv:2; + /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio32_fun_wpd:1; + /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio32_fun_wpu:1; + /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio32_fun_ie:1; + /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio32_fun_drv:2; + /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio32_mcu_sel:3; + /** gpio32_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio32_filter_en:1; + /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t gpio32_rue_i3c:1; + /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0; + * NA + */ + uint32_t gpio32_ru_i3c:2; + /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t gpio32_rue_sel_i3c:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} io_mux_gpio32_reg_t; + +/** Type of gpio33 register + * iomux control register for gpio33 + */ +typedef union { + struct { + /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio33_mcu_oe:1; + /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio33_slp_sel:1; + /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio33_mcu_wpd:1; + /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio33_mcu_wpu:1; + /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio33_mcu_ie:1; + /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio33_mcu_drv:2; + /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio33_fun_wpd:1; + /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio33_fun_wpu:1; + /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio33_fun_ie:1; + /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio33_fun_drv:2; + /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio33_mcu_sel:3; + /** gpio33_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio33_filter_en:1; + /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t gpio33_rue_i3c:1; + /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0; + * NA + */ + uint32_t gpio33_ru_i3c:2; + /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t gpio33_rue_sel_i3c:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} io_mux_gpio33_reg_t; + +/** Type of gpio34 register + * iomux control register for gpio34 + */ +typedef union { + struct { + /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio34_mcu_oe:1; + /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio34_slp_sel:1; + /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio34_mcu_wpd:1; + /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio34_mcu_wpu:1; + /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio34_mcu_ie:1; + /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio34_mcu_drv:2; + /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio34_fun_wpd:1; + /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio34_fun_wpu:1; + /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio34_fun_ie:1; + /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio34_fun_drv:2; + /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio34_mcu_sel:3; + /** gpio34_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio34_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio34_reg_t; + +/** Type of gpio35 register + * iomux control register for gpio35 + */ +typedef union { + struct { + /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio35_mcu_oe:1; + /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio35_slp_sel:1; + /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio35_mcu_wpd:1; + /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio35_mcu_wpu:1; + /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio35_mcu_ie:1; + /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio35_mcu_drv:2; + /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio35_fun_wpd:1; + /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio35_fun_wpu:1; + /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio35_fun_ie:1; + /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio35_fun_drv:2; + /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio35_mcu_sel:3; + /** gpio35_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio35_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio35_reg_t; + +/** Type of gpio36 register + * iomux control register for gpio36 + */ +typedef union { + struct { + /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio36_mcu_oe:1; + /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio36_slp_sel:1; + /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio36_mcu_wpd:1; + /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio36_mcu_wpu:1; + /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio36_mcu_ie:1; + /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio36_mcu_drv:2; + /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio36_fun_wpd:1; + /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio36_fun_wpu:1; + /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio36_fun_ie:1; + /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio36_fun_drv:2; + /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio36_mcu_sel:3; + /** gpio36_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio36_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio36_reg_t; + +/** Type of gpio37 register + * iomux control register for gpio37 + */ +typedef union { + struct { + /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio37_mcu_oe:1; + /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio37_slp_sel:1; + /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio37_mcu_wpd:1; + /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio37_mcu_wpu:1; + /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio37_mcu_ie:1; + /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio37_mcu_drv:2; + /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio37_fun_wpd:1; + /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio37_fun_wpu:1; + /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio37_fun_ie:1; + /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio37_fun_drv:2; + /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio37_mcu_sel:3; + /** gpio37_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio37_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio37_reg_t; + +/** Type of gpio38 register + * iomux control register for gpio38 + */ +typedef union { + struct { + /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio38_mcu_oe:1; + /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio38_slp_sel:1; + /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio38_mcu_wpd:1; + /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio38_mcu_wpu:1; + /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio38_mcu_ie:1; + /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio38_mcu_drv:2; + /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio38_fun_wpd:1; + /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio38_fun_wpu:1; + /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio38_fun_ie:1; + /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio38_fun_drv:2; + /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio38_mcu_sel:3; + /** gpio38_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio38_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio38_reg_t; + +/** Type of gpio39 register + * iomux control register for gpio39 + */ +typedef union { + struct { + /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio39_mcu_oe:1; + /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio39_slp_sel:1; + /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio39_mcu_wpd:1; + /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio39_mcu_wpu:1; + /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio39_mcu_ie:1; + /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio39_mcu_drv:2; + /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio39_fun_wpd:1; + /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio39_fun_wpu:1; + /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio39_fun_ie:1; + /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio39_fun_drv:2; + /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio39_mcu_sel:3; + /** gpio39_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio39_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio39_reg_t; + +/** Type of gpio40 register + * iomux control register for gpio40 + */ +typedef union { + struct { + /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio40_mcu_oe:1; + /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio40_slp_sel:1; + /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio40_mcu_wpd:1; + /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio40_mcu_wpu:1; + /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio40_mcu_ie:1; + /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio40_mcu_drv:2; + /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio40_fun_wpd:1; + /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio40_fun_wpu:1; + /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio40_fun_ie:1; + /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio40_fun_drv:2; + /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio40_mcu_sel:3; + /** gpio40_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio40_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio40_reg_t; + +/** Type of gpio41 register + * iomux control register for gpio41 + */ +typedef union { + struct { + /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio41_mcu_oe:1; + /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio41_slp_sel:1; + /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio41_mcu_wpd:1; + /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio41_mcu_wpu:1; + /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio41_mcu_ie:1; + /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio41_mcu_drv:2; + /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio41_fun_wpd:1; + /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio41_fun_wpu:1; + /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio41_fun_ie:1; + /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio41_fun_drv:2; + /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio41_mcu_sel:3; + /** gpio41_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio41_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio41_reg_t; + +/** Type of gpio42 register + * iomux control register for gpio42 + */ +typedef union { + struct { + /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio42_mcu_oe:1; + /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio42_slp_sel:1; + /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio42_mcu_wpd:1; + /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio42_mcu_wpu:1; + /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio42_mcu_ie:1; + /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio42_mcu_drv:2; + /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio42_fun_wpd:1; + /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio42_fun_wpu:1; + /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio42_fun_ie:1; + /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio42_fun_drv:2; + /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio42_mcu_sel:3; + /** gpio42_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio42_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio42_reg_t; + +/** Type of gpio43 register + * iomux control register for gpio43 + */ +typedef union { + struct { + /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio43_mcu_oe:1; + /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio43_slp_sel:1; + /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio43_mcu_wpd:1; + /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio43_mcu_wpu:1; + /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio43_mcu_ie:1; + /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio43_mcu_drv:2; + /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio43_fun_wpd:1; + /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio43_fun_wpu:1; + /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio43_fun_ie:1; + /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio43_fun_drv:2; + /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio43_mcu_sel:3; + /** gpio43_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio43_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio43_reg_t; + +/** Type of gpio44 register + * iomux control register for gpio44 + */ +typedef union { + struct { + /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio44_mcu_oe:1; + /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio44_slp_sel:1; + /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio44_mcu_wpd:1; + /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio44_mcu_wpu:1; + /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio44_mcu_ie:1; + /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio44_mcu_drv:2; + /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio44_fun_wpd:1; + /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio44_fun_wpu:1; + /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio44_fun_ie:1; + /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio44_fun_drv:2; + /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio44_mcu_sel:3; + /** gpio44_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio44_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio44_reg_t; + +/** Type of gpio45 register + * iomux control register for gpio45 + */ +typedef union { + struct { + /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio45_mcu_oe:1; + /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio45_slp_sel:1; + /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio45_mcu_wpd:1; + /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio45_mcu_wpu:1; + /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio45_mcu_ie:1; + /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio45_mcu_drv:2; + /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio45_fun_wpd:1; + /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio45_fun_wpu:1; + /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio45_fun_ie:1; + /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio45_fun_drv:2; + /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio45_mcu_sel:3; + /** gpio45_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio45_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio45_reg_t; + +/** Type of gpio46 register + * iomux control register for gpio46 + */ +typedef union { + struct { + /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio46_mcu_oe:1; + /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio46_slp_sel:1; + /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio46_mcu_wpd:1; + /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio46_mcu_wpu:1; + /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio46_mcu_ie:1; + /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio46_mcu_drv:2; + /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio46_fun_wpd:1; + /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio46_fun_wpu:1; + /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio46_fun_ie:1; + /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio46_fun_drv:2; + /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio46_mcu_sel:3; + /** gpio46_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio46_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio46_reg_t; + +/** Type of gpio47 register + * iomux control register for gpio47 + */ +typedef union { + struct { + /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio47_mcu_oe:1; + /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio47_slp_sel:1; + /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio47_mcu_wpd:1; + /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio47_mcu_wpu:1; + /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio47_mcu_ie:1; + /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio47_mcu_drv:2; + /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio47_fun_wpd:1; + /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio47_fun_wpu:1; + /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio47_fun_ie:1; + /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio47_fun_drv:2; + /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio47_mcu_sel:3; + /** gpio47_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio47_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio47_reg_t; + +/** Type of gpio48 register + * iomux control register for gpio48 + */ +typedef union { + struct { + /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio48_mcu_oe:1; + /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio48_slp_sel:1; + /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio48_mcu_wpd:1; + /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio48_mcu_wpu:1; + /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio48_mcu_ie:1; + /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio48_mcu_drv:2; + /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio48_fun_wpd:1; + /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio48_fun_wpu:1; + /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio48_fun_ie:1; + /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio48_fun_drv:2; + /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 1; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio48_mcu_sel:3; + /** gpio48_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio48_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio48_reg_t; + +/** Type of gpio49 register + * iomux control register for gpio49 + */ +typedef union { + struct { + /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio49_mcu_oe:1; + /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio49_slp_sel:1; + /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio49_mcu_wpd:1; + /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio49_mcu_wpu:1; + /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio49_mcu_ie:1; + /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio49_mcu_drv:2; + /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio49_fun_wpd:1; + /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio49_fun_wpu:1; + /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio49_fun_ie:1; + /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio49_fun_drv:2; + /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio49_mcu_sel:3; + /** gpio49_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio49_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio49_reg_t; + +/** Type of gpio50 register + * iomux control register for gpio50 + */ +typedef union { + struct { + /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio50_mcu_oe:1; + /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio50_slp_sel:1; + /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio50_mcu_wpd:1; + /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio50_mcu_wpu:1; + /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio50_mcu_ie:1; + /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio50_mcu_drv:2; + /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio50_fun_wpd:1; + /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio50_fun_wpu:1; + /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio50_fun_ie:1; + /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio50_fun_drv:2; + /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio50_mcu_sel:3; + /** gpio50_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio50_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio50_reg_t; + +/** Type of gpio51 register + * iomux control register for gpio51 + */ +typedef union { + struct { + /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio51_mcu_oe:1; + /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio51_slp_sel:1; + /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio51_mcu_wpd:1; + /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio51_mcu_wpu:1; + /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio51_mcu_ie:1; + /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio51_mcu_drv:2; + /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio51_fun_wpd:1; + /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio51_fun_wpu:1; + /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio51_fun_ie:1; + /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio51_fun_drv:2; + /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio51_mcu_sel:3; + /** gpio51_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio51_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio51_reg_t; + +/** Type of gpio52 register + * iomux control register for gpio52 + */ +typedef union { + struct { + /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio52_mcu_oe:1; + /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio52_slp_sel:1; + /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio52_mcu_wpd:1; + /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio52_mcu_wpu:1; + /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio52_mcu_ie:1; + /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio52_mcu_drv:2; + /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio52_fun_wpd:1; + /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio52_fun_wpu:1; + /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio52_fun_ie:1; + /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio52_fun_drv:2; + /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio52_mcu_sel:3; + /** gpio52_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio52_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio52_reg_t; + +/** Type of gpio53 register + * iomux control register for gpio53 + */ +typedef union { + struct { + /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio53_mcu_oe:1; + /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio53_slp_sel:1; + /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio53_mcu_wpd:1; + /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio53_mcu_wpu:1; + /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio53_mcu_ie:1; + /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio53_mcu_drv:2; + /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio53_fun_wpd:1; + /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio53_fun_wpu:1; + /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio53_fun_ie:1; + /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio53_fun_drv:2; + /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio53_mcu_sel:3; + /** gpio53_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio53_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio53_reg_t; + +/** Type of gpio54 register + * iomux control register for gpio54 + */ +typedef union { + struct { + /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio54_mcu_oe:1; + /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio54_slp_sel:1; + /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio54_mcu_wpd:1; + /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio54_mcu_wpu:1; + /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio54_mcu_ie:1; + /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio54_mcu_drv:2; + /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio54_fun_wpd:1; + /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio54_fun_wpu:1; + /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio54_fun_ie:1; + /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio54_fun_drv:2; + /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio54_mcu_sel:3; + /** gpio54_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio54_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio54_reg_t; + +/** Type of gpio55 register + * iomux control register for gpio55 + */ +typedef union { + struct { + /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio55_mcu_oe:1; + /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio55_slp_sel:1; + /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio55_mcu_wpd:1; + /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio55_mcu_wpu:1; + /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio55_mcu_ie:1; + /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio55_mcu_drv:2; + /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio55_fun_wpd:1; + /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio55_fun_wpu:1; + /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio55_fun_ie:1; + /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio55_fun_drv:2; + /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio55_mcu_sel:3; + /** gpio55_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio55_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio55_reg_t; + +/** Type of gpio56 register + * iomux control register for gpio56 + */ +typedef union { + struct { + /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t gpio56_mcu_oe:1; + /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t gpio56_slp_sel:1; + /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t gpio56_mcu_wpd:1; + /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t gpio56_mcu_wpu:1; + /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t gpio56_mcu_ie:1; + /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * select drive strength on sleep mode + */ + uint32_t gpio56_mcu_drv:2; + /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t gpio56_fun_wpd:1; + /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t gpio56_fun_wpu:1; + /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t gpio56_fun_ie:1; + /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t gpio56_fun_drv:2; + /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t gpio56_mcu_sel:3; + /** gpio56_filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t gpio56_filter_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} io_mux_gpio56_reg_t; + +/** Type of date register + * iomux version + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 2101794; + * csv date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} io_mux_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile io_mux_gpio0_reg_t gpio0; + volatile io_mux_gpio1_reg_t gpio1; + volatile io_mux_gpio2_reg_t gpio2; + volatile io_mux_gpio3_reg_t gpio3; + volatile io_mux_gpio4_reg_t gpio4; + volatile io_mux_gpio5_reg_t gpio5; + volatile io_mux_gpio6_reg_t gpio6; + volatile io_mux_gpio7_reg_t gpio7; + volatile io_mux_gpio8_reg_t gpio8; + volatile io_mux_gpio9_reg_t gpio9; + volatile io_mux_gpio10_reg_t gpio10; + volatile io_mux_gpio11_reg_t gpio11; + volatile io_mux_gpio12_reg_t gpio12; + volatile io_mux_gpio13_reg_t gpio13; + volatile io_mux_gpio14_reg_t gpio14; + volatile io_mux_gpio15_reg_t gpio15; + volatile io_mux_gpio16_reg_t gpio16; + volatile io_mux_gpio17_reg_t gpio17; + volatile io_mux_gpio18_reg_t gpio18; + volatile io_mux_gpio19_reg_t gpio19; + volatile io_mux_gpio20_reg_t gpio20; + volatile io_mux_gpio21_reg_t gpio21; + volatile io_mux_gpio22_reg_t gpio22; + volatile io_mux_gpio23_reg_t gpio23; + volatile io_mux_gpio24_reg_t gpio24; + volatile io_mux_gpio25_reg_t gpio25; + volatile io_mux_gpio26_reg_t gpio26; + volatile io_mux_gpio27_reg_t gpio27; + volatile io_mux_gpio28_reg_t gpio28; + volatile io_mux_gpio29_reg_t gpio29; + volatile io_mux_gpio30_reg_t gpio30; + volatile io_mux_gpio31_reg_t gpio31; + volatile io_mux_gpio32_reg_t gpio32; + volatile io_mux_gpio33_reg_t gpio33; + volatile io_mux_gpio34_reg_t gpio34; + volatile io_mux_gpio35_reg_t gpio35; + volatile io_mux_gpio36_reg_t gpio36; + volatile io_mux_gpio37_reg_t gpio37; + volatile io_mux_gpio38_reg_t gpio38; + volatile io_mux_gpio39_reg_t gpio39; + volatile io_mux_gpio40_reg_t gpio40; + volatile io_mux_gpio41_reg_t gpio41; + volatile io_mux_gpio42_reg_t gpio42; + volatile io_mux_gpio43_reg_t gpio43; + volatile io_mux_gpio44_reg_t gpio44; + volatile io_mux_gpio45_reg_t gpio45; + volatile io_mux_gpio46_reg_t gpio46; + volatile io_mux_gpio47_reg_t gpio47; + volatile io_mux_gpio48_reg_t gpio48; + volatile io_mux_gpio49_reg_t gpio49; + volatile io_mux_gpio50_reg_t gpio50; + volatile io_mux_gpio51_reg_t gpio51; + volatile io_mux_gpio52_reg_t gpio52; + volatile io_mux_gpio53_reg_t gpio53; + volatile io_mux_gpio54_reg_t gpio54; + volatile io_mux_gpio55_reg_t gpio55; + volatile io_mux_gpio56_reg_t gpio56; + uint32_t reserved_0e8[7]; + volatile io_mux_date_reg_t date; +} io_mux_dev_t; + +extern io_mux_dev_t IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/io_mux_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_reg.h new file mode 100644 index 0000000000..b8eac91be1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_reg.h @@ -0,0 +1,524 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include "soc/soc.h" + +//TODO: IDF-13419 + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_GPIO0 +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_GPIO1 +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2 +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_GPIO3 +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_GPIO4 +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_GPIO5 +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_GPIO6 +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7 +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8 +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9 +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_GPIO10 +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_GPIO11 +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12 +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14 +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_GPIO15 +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_GPIO16 +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17 +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18 +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_GPIO19 +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_GPIO20 +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_GPIO21 +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22 +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23 +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24 +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_GPIO25 +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_U_PAD_GPIO26 +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_U_PAD_GPIO27 +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_U_PAD_GPIO28 +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_U_PAD_GPIO29 +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_U_PAD_GPIO30 +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_U_PAD_GPIO31 +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_U_PAD_GPIO32 +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_U_PAD_GPIO33 +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_U_PAD_GPIO34 +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_U_PAD_GPIO35 +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_U_PAD_GPIO36 +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_U_PAD_GPIO37 +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_U_PAD_GPIO38 +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_U_PAD_GPIO39 +#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_U_PAD_GPIO40 +#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_U_PAD_GPIO41 +#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_U_PAD_GPIO42 +#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U_PAD_GPIO43 +#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U_PAD_GPIO44 +#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_U_PAD_GPIO45 +#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_U_PAD_GPIO46 +#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_U_PAD_GPIO47 +#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_U_PAD_GPIO48 +#define IO_MUX_GPIO49_REG PERIPHS_IO_MUX_U_PAD_GPIO49 +#define IO_MUX_GPIO50_REG PERIPHS_IO_MUX_U_PAD_GPIO50 +#define IO_MUX_GPIO51_REG PERIPHS_IO_MUX_U_PAD_GPIO51 +#define IO_MUX_GPIO52_REG PERIPHS_IO_MUX_U_PAD_GPIO52 +#define IO_MUX_GPIO53_REG PERIPHS_IO_MUX_U_PAD_GPIO53 +#define IO_MUX_GPIO54_REG PERIPHS_IO_MUX_U_PAD_GPIO54 + +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +// TODO: IDF-7499, IDF-7495 +// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore. +// Please check iomux_mspi_pin_struct/reg.h +#include "soc/gpio_num.h" +#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX +#define SPI_HD_GPIO_NUM GPIO_NUM_MAX +#define SPI_WP_GPIO_NUM GPIO_NUM_MAX +#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX +#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX +#define SPI_Q_GPIO_NUM GPIO_NUM_MAX +#define SPI_D_GPIO_NUM GPIO_NUM_MAX +#define SPI_D4_GPIO_NUM GPIO_NUM_MAX +#define SPI_D5_GPIO_NUM GPIO_NUM_MAX +#define SPI_D6_GPIO_NUM GPIO_NUM_MAX +#define SPI_D7_GPIO_NUM GPIO_NUM_MAX +#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX + +#define SD_CLK_GPIO_NUM 43 +#define SD_CMD_GPIO_NUM 44 +#define SD_DATA0_GPIO_NUM 39 +#define SD_DATA1_GPIO_NUM 40 +#define SD_DATA2_GPIO_NUM 41 +#define SD_DATA3_GPIO_NUM 42 +#define SD_DATA4_GPIO_NUM 45 +#define SD_DATA5_GPIO_NUM 46 +#define SD_DATA6_GPIO_NUM 47 +#define SD_DATA7_GPIO_NUM 48 + +#define USB_INT_PHY0_DM_GPIO_NUM 24 +#define USB_INT_PHY0_DP_GPIO_NUM 25 +#define USB_INT_PHY1_DM_GPIO_NUM 26 +#define USB_INT_PHY1_DP_GPIO_NUM 27 + +// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG +#define USB_USJ_INT_PHY_DM_GPIO_NUM USB_INT_PHY0_DM_GPIO_NUM +#define USB_USJ_INT_PHY_DP_GPIO_NUM USB_INT_PHY0_DP_GPIO_NUM +#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM +#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM + +#define MAX_RTC_GPIO_NUM 15 +#define MAX_PAD_GPIO_NUM 54 +#define MAX_GPIO_NUM 56 + + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x4) +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x8) +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0xC) +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_MTCK 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_MTDI 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x14) +#define FUNC_GPIO4_GPIO4 1 +#define FUNC_GPIO4_MTMS 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x18) +#define FUNC_GPIO5_GPIO5 1 +#define FUNC_GPIO5_MTDO 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x1C) +#define FUNC_GPIO6_SPI2_HOLD_PAD 3 +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO7_SPI2_CS_PAD 3 +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO8_SPI2_D_PAD 3 +#define FUNC_GPIO8_UART0_RTS_PAD 2 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x28) +#define FUNC_GPIO9_SPI2_CK_PAD 3 +#define FUNC_GPIO9_UART0_CTS_PAD 2 +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x2C) +#define FUNC_GPIO10_SPI2_Q_PAD 3 +#define FUNC_GPIO10_UART1_TXD_PAD 2 +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO11 (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO11_SPI2_WP_PAD 3 +#define FUNC_GPIO11_UART1_RXD_PAD 2 +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO12_UART1_RTS_PAD 2 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x38) +#define FUNC_GPIO13_UART1_CTS_PAD 2 +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x3C) +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x40) +#define FUNC_GPIO15_GPIO15 1 +#define FUNC_GPIO15_GPIO15_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x44) +#define FUNC_GPIO16_GPIO16 1 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x48) +#define FUNC_GPIO17_GPIO17 1 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x4C) +#define FUNC_GPIO18_GPIO18 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x50) +#define FUNC_GPIO19_GPIO19 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x54) +#define FUNC_GPIO20_GPIO20 1 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x58) +#define FUNC_GPIO21_GPIO21 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x5C) +#define FUNC_GPIO22_DBG_PSRAM_CK_PAD 4 +#define FUNC_GPIO22_GPIO22 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x60) +#define FUNC_GPIO23_DBG_PSRAM_CS_PAD 4 +#define FUNC_GPIO23_REF_50M_CLK_PAD 3 +#define FUNC_GPIO23_GPIO23 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x64) +#define FUNC_GPIO24_GPIO24 1 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x68) +#define FUNC_GPIO25_GPIO25 1 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x6C) +#define FUNC_GPIO26_GPIO26 1 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x70) +#define FUNC_GPIO27_GPIO27 1 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x74) +#define FUNC_GPIO28_DBG_PSRAM_D_PAD 4 +#define FUNC_GPIO28_EMAC_PHY_RXDV_PAD 3 +#define FUNC_GPIO28_SPI2_CS_PAD 2 +#define FUNC_GPIO28_GPIO28 1 +#define FUNC_GPIO28_GPIO28_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO29 (REG_IO_MUX_BASE + 0x78) +#define FUNC_GPIO29_DBG_PSRAM_Q_PAD 4 +#define FUNC_GPIO29_EMAC_PHY_RXD0_PAD 3 +#define FUNC_GPIO29_SPI2_D_PAD 2 +#define FUNC_GPIO29_GPIO29 1 +#define FUNC_GPIO29_GPIO29_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO30 (REG_IO_MUX_BASE + 0x7C) +#define FUNC_GPIO30_DBG_PSRAM_WP_PAD 4 +#define FUNC_GPIO30_EMAC_PHY_RXD1_PAD 3 +#define FUNC_GPIO30_SPI2_CK_PAD 2 +#define FUNC_GPIO30_GPIO30 1 +#define FUNC_GPIO30_GPIO30_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO31 (REG_IO_MUX_BASE + 0x80) +#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD 4 +#define FUNC_GPIO31_EMAC_PHY_RXER_PAD 3 +#define FUNC_GPIO31_SPI2_Q_PAD 2 +#define FUNC_GPIO31_GPIO31 1 +#define FUNC_GPIO31_GPIO31_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x84) +#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4 +#define FUNC_GPIO32_EMAC_RMII_CLK_PAD 3 +#define FUNC_GPIO32_SPI2_HOLD_PAD 2 +#define FUNC_GPIO32_GPIO32 1 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x88) +#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4 +#define FUNC_GPIO33_EMAC_PHY_TXEN_PAD 3 +#define FUNC_GPIO33_SPI2_WP_PAD 2 +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x8C) +#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4 +#define FUNC_GPIO34_EMAC_PHY_TXD0_PAD 3 +#define FUNC_GPIO34_SPI2_IO4_PAD 2 +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x90) +#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4 +#define FUNC_GPIO35_EMAC_PHY_TXD1_PAD 3 +#define FUNC_GPIO35_SPI2_IO5_PAD 2 +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x94) +#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4 +#define FUNC_GPIO36_EMAC_PHY_TXER_PAD 3 +#define FUNC_GPIO36_SPI2_IO6_PAD 2 +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x98) +#define FUNC_GPIO37_SPI2_IO7_PAD 2 +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_UART0_TXD_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x9C) +#define FUNC_GPIO38_SPI2_DQS_PAD 2 +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_UART0_RXD_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0xA0) +#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD 4 +#define FUNC_GPIO39_REF_50M_CLK_PAD 3 +#define FUNC_GPIO39_BIST_PAD 2 +#define FUNC_GPIO39_GPIO39 1 +#define FUNC_GPIO39_SD1_CDATA0_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO40 (REG_IO_MUX_BASE + 0xA4) +#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD 4 +#define FUNC_GPIO40_EMAC_PHY_TXEN_PAD 3 +#define FUNC_GPIO40_BIST_PAD 2 +#define FUNC_GPIO40_GPIO40 1 +#define FUNC_GPIO40_SD1_CDATA1_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO41 (REG_IO_MUX_BASE + 0xA8) +#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD 4 +#define FUNC_GPIO41_EMAC_PHY_TXD0_PAD 3 +#define FUNC_GPIO41_BIST_PAD 2 +#define FUNC_GPIO41_GPIO41 1 +#define FUNC_GPIO41_SD1_CDATA2_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO42 (REG_IO_MUX_BASE + 0xAC) +#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD 4 +#define FUNC_GPIO42_EMAC_PHY_TXD1_PAD 3 +#define FUNC_GPIO42_BIST_PAD 2 +#define FUNC_GPIO42_GPIO42 1 +#define FUNC_GPIO42_SD1_CDATA3_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO43 (REG_IO_MUX_BASE + 0xB0) +#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD 4 +#define FUNC_GPIO43_EMAC_PHY_TXER_PAD 3 +#define FUNC_GPIO43_BIST_PAD 2 +#define FUNC_GPIO43_GPIO43 1 +#define FUNC_GPIO43_SD1_CCLK_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO44 (REG_IO_MUX_BASE + 0xB4) +#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD 4 +#define FUNC_GPIO44_EMAC_RMII_CLK_PAD 3 +#define FUNC_GPIO44_BIST_PAD 2 +#define FUNC_GPIO44_GPIO44 1 +#define FUNC_GPIO44_SD1_CCMD_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO45 (REG_IO_MUX_BASE + 0xB8) +#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD 4 +#define FUNC_GPIO45_EMAC_PHY_RXDV_PAD 3 +#define FUNC_GPIO45_BIST_PAD 2 +#define FUNC_GPIO45_GPIO45 1 +#define FUNC_GPIO45_SD1_CDATA4_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO46 (REG_IO_MUX_BASE + 0xBC) +#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD 4 +#define FUNC_GPIO46_EMAC_PHY_RXD0_PAD 3 +#define FUNC_GPIO46_BIST_PAD 2 +#define FUNC_GPIO46_GPIO46 1 +#define FUNC_GPIO46_SD1_CDATA5_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO47 (REG_IO_MUX_BASE + 0xC0) +#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD 4 +#define FUNC_GPIO47_EMAC_PHY_RXD1_PAD 3 +#define FUNC_GPIO47_BIST_PAD 2 +#define FUNC_GPIO47_GPIO47 1 +#define FUNC_GPIO47_SD1_CDATA6_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO48 (REG_IO_MUX_BASE + 0xC4) +#define FUNC_GPIO48_EMAC_PHY_RXER_PAD 3 +#define FUNC_GPIO48_BIST_PAD 2 +#define FUNC_GPIO48_GPIO48 1 +#define FUNC_GPIO48_SD1_CDATA7_PAD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO49 (REG_IO_MUX_BASE + 0xC8) +#define FUNC_GPIO49_DBG_FLASH_CS_PAD 4 +#define FUNC_GPIO49_EMAC_PHY_TXEN_PAD 3 +#define FUNC_GPIO49_GPIO49 1 +#define FUNC_GPIO49_GPIO49_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO50 (REG_IO_MUX_BASE + 0xCC) +#define FUNC_GPIO50_DBG_FLASH_Q_PAD 4 +#define FUNC_GPIO50_EMAC_RMII_CLK_PAD 3 +#define FUNC_GPIO50_GPIO50 1 +#define FUNC_GPIO50_GPIO50_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO51 (REG_IO_MUX_BASE + 0xD0) +#define FUNC_GPIO51_DBG_FLASH_WP_PAD 4 +#define FUNC_GPIO51_EMAC_PHY_RXDV_PAD 3 +#define FUNC_GPIO51_GPIO51 1 +#define FUNC_GPIO51_GPIO51_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO52 (REG_IO_MUX_BASE + 0xD4) +#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD 4 +#define FUNC_GPIO52_EMAC_PHY_RXD0_PAD 3 +#define FUNC_GPIO52_GPIO52 1 +#define FUNC_GPIO52_GPIO52_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO53 (REG_IO_MUX_BASE + 0xD8) +#define FUNC_GPIO53_DBG_FLASH_CK_PAD 4 +#define FUNC_GPIO53_EMAC_PHY_RXD1_PAD 3 +#define FUNC_GPIO53_GPIO53 1 +#define FUNC_GPIO53_GPIO53_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO54 (REG_IO_MUX_BASE + 0xDC) +#define FUNC_GPIO54_DBG_FLASH_D_PAD 4 +#define FUNC_GPIO54_EMAC_PHY_RXER_PAD 3 +#define FUNC_GPIO54_GPIO54 1 +#define FUNC_GPIO54_GPIO54_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO55 (REG_IO_MUX_BASE + 0xE0) +#define FUNC_GPIO55_GPIO55 1 +#define FUNC_GPIO55_GPIO55_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO56 (REG_IO_MUX_BASE + 0xE4) +#define FUNC_GPIO56_GPIO56 1 +#define FUNC_GPIO56_GPIO56_0 0 + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x104) +/* IO_MUX_DATE : R/W ;bitpos:[27:0] ;default: 27'h0201222 ; */ +/*description: csv date.*/ +#define IO_MUX_DATE 0x0FFFFFFF +#define IO_MUX_DATE_M ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S)) +#define IO_MUX_DATE_V 0xFFFFFFF +#define IO_MUX_DATE_S 0 diff --git a/components/soc/esp32p4/register/hw_ver2/soc/io_mux_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_struct.h new file mode 100644 index 0000000000..b2b0e66306 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/io_mux_struct.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: IDF-13419 +/** Type of GPIO register + * IO MUX gpio configuration register + */ +typedef union { + struct { + /** mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t mcu_oe:1; + /** slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t slp_sel:1; + /** mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t mcu_wpd:1; + /** mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t mcu_wpu:1; + /** mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t mcu_ie:1; + /** mcu_drv : R/W; bitpos: [5:6]; default: 0; + * select drive strength on sleep mode + */ + uint32_t mcu_drv:2; + /** fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t fun_wpd:1; + /** fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t fun_wpu:1; + /** fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t fun_ie:1; + /** fun_drv : R/W; bitpos: [10:11]; default: 2; + * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t fun_drv:2; + /** mcu_sel : R/W; bitpos: [12:14]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t mcu_sel:3; + /** filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t filter_en:1; + uint32_t reserved16 :16; + }; + uint32_t val; +} io_mux_gpio_reg_t; + +/** Type of date register + * IO_MUX version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 2101794; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} io_mux_date_reg_t; + + +typedef struct io_mux_dev_t { + uint32_t reserved_0; + volatile io_mux_gpio_reg_t gpio[57]; + uint32_t reserved_e8[7]; + volatile io_mux_date_reg_t date; +} io_mux_dev_t; + +extern io_mux_dev_t IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_reg.h new file mode 100644 index 0000000000..db2188d109 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_reg.h @@ -0,0 +1,1391 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** IOMUX_MSPI_PIN_CLK_EN0_REG register + * apb registers auto clock gating reg + */ +#define IOMUX_MSPI_PIN_CLK_EN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x0) +/** IOMUX_MSPI_PIN_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * 1: auto clock gating on + * 0: auto clock gating off + */ +#define IOMUX_MSPI_PIN_REG_CLK_EN (BIT(0)) +#define IOMUX_MSPI_PIN_REG_CLK_EN_M (IOMUX_MSPI_PIN_REG_CLK_EN_V << IOMUX_MSPI_PIN_REG_CLK_EN_S) +#define IOMUX_MSPI_PIN_REG_CLK_EN_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_CLK_EN_S 0 + +/** IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG register + * IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG + */ +#define IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x4) +/** IOMUX_MSPI_PIN_REG_FLASH_CS_HYS : R/W; bitpos: [0]; default: 0; + * flash cs hys + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS (BIT(0)) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_M (IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CS_HYS_S 0 +/** IOMUX_MSPI_PIN_REG_FLASH_CS_IE : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE (BIT(1)) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE_M (IOMUX_MSPI_PIN_REG_FLASH_CS_IE_V << IOMUX_MSPI_PIN_REG_FLASH_CS_IE_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CS_IE_S 1 +/** IOMUX_MSPI_PIN_REG_FLASH_CS_WPU : R/W; bitpos: [2]; default: 0; + * flash cs wpu + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU (BIT(2)) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_M (IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPU_S 2 +/** IOMUX_MSPI_PIN_REG_FLASH_CS_WPD : R/W; bitpos: [3]; default: 0; + * flash cs wpd + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD (BIT(3)) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_M (IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CS_WPD_S 3 +/** IOMUX_MSPI_PIN_REG_FLASH_CS_DRV : R/W; bitpos: [5:4]; default: 0; + * flash cs drv + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_M (IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_CS_DRV_S 4 + +/** IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG register + * IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG + */ +#define IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x8) +/** IOMUX_MSPI_PIN_REG_FLASH_Q_HYS : R/W; bitpos: [0]; default: 0; + * flash q hys + */ +#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS (BIT(0)) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_M (IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_S) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_Q_HYS_S 0 +/** IOMUX_MSPI_PIN_REG_FLASH_Q_IE : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE (BIT(1)) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE_M (IOMUX_MSPI_PIN_REG_FLASH_Q_IE_V << IOMUX_MSPI_PIN_REG_FLASH_Q_IE_S) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_Q_IE_S 1 +/** IOMUX_MSPI_PIN_REG_FLASH_Q_WPU : R/W; bitpos: [2]; default: 0; + * flash q wpu + */ +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU (BIT(2)) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_M (IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_S) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPU_S 2 +/** IOMUX_MSPI_PIN_REG_FLASH_Q_WPD : R/W; bitpos: [3]; default: 0; + * flash q wpd + */ +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD (BIT(3)) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_M (IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_S) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_Q_WPD_S 3 +/** IOMUX_MSPI_PIN_REG_FLASH_Q_DRV : R/W; bitpos: [5:4]; default: 0; + * flash q drv + */ +#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_M (IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_S) +#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_Q_DRV_S 4 + +/** IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG register + * IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG + */ +#define IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0xc) +/** IOMUX_MSPI_PIN_REG_FLASH_WP_HYS : R/W; bitpos: [0]; default: 0; + * flash wp hys + */ +#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS (BIT(0)) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_M (IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_S) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_WP_HYS_S 0 +/** IOMUX_MSPI_PIN_REG_FLASH_WP_IE : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE (BIT(1)) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE_M (IOMUX_MSPI_PIN_REG_FLASH_WP_IE_V << IOMUX_MSPI_PIN_REG_FLASH_WP_IE_S) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_WP_IE_S 1 +/** IOMUX_MSPI_PIN_REG_FLASH_WP_WPU : R/W; bitpos: [2]; default: 0; + * flash wp wpu + */ +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU (BIT(2)) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_M (IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_S) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPU_S 2 +/** IOMUX_MSPI_PIN_REG_FLASH_WP_WPD : R/W; bitpos: [3]; default: 0; + * flash wp wpd + */ +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD (BIT(3)) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_M (IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_S) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_WP_WPD_S 3 +/** IOMUX_MSPI_PIN_REG_FLASH_WP_DRV : R/W; bitpos: [5:4]; default: 0; + * flash wp drv + */ +#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_M (IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_S) +#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_WP_DRV_S 4 + +/** IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG register + * IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG + */ +#define IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x10) +/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS : R/W; bitpos: [0]; default: 0; + * flash hold hys + */ +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS (BIT(0)) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_M (IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_S) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_HYS_S 0 +/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE (BIT(1)) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_M (IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_S) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_IE_S 1 +/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU : R/W; bitpos: [2]; default: 0; + * flash hold wpu + */ +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU (BIT(2)) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_M (IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_S) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPU_S 2 +/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD : R/W; bitpos: [3]; default: 0; + * flash hold wpd + */ +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD (BIT(3)) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_M (IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_S) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_WPD_S 3 +/** IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV : R/W; bitpos: [5:4]; default: 0; + * flash hold drv + */ +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_M (IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_S) +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_HOLD_DRV_S 4 + +/** IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG register + * IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG + */ +#define IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x14) +/** IOMUX_MSPI_PIN_REG_FLASH_CK_HYS : R/W; bitpos: [0]; default: 0; + * flash ck hys + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS (BIT(0)) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_M (IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CK_HYS_S 0 +/** IOMUX_MSPI_PIN_REG_FLASH_CK_IE : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE (BIT(1)) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE_M (IOMUX_MSPI_PIN_REG_FLASH_CK_IE_V << IOMUX_MSPI_PIN_REG_FLASH_CK_IE_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CK_IE_S 1 +/** IOMUX_MSPI_PIN_REG_FLASH_CK_WPU : R/W; bitpos: [2]; default: 0; + * flash ck wpu + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU (BIT(2)) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_M (IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPU_S 2 +/** IOMUX_MSPI_PIN_REG_FLASH_CK_WPD : R/W; bitpos: [3]; default: 0; + * flash ck wpd + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD (BIT(3)) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_M (IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_CK_WPD_S 3 +/** IOMUX_MSPI_PIN_REG_FLASH_CK_DRV : R/W; bitpos: [5:4]; default: 0; + * flash ck drv + */ +#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_M (IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_S) +#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_CK_DRV_S 4 + +/** IOMUX_MSPI_PIN_FLASH_D_PIN0_REG register + * IOMUX_MSPI_PIN_FLASH_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_FLASH_D_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x18) +/** IOMUX_MSPI_PIN_REG_FLASH_D_HYS : R/W; bitpos: [0]; default: 0; + * flash d hys + */ +#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS (BIT(0)) +#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS_M (IOMUX_MSPI_PIN_REG_FLASH_D_HYS_V << IOMUX_MSPI_PIN_REG_FLASH_D_HYS_S) +#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_D_HYS_S 0 +/** IOMUX_MSPI_PIN_REG_FLASH_D_IE : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_FLASH_D_IE (BIT(1)) +#define IOMUX_MSPI_PIN_REG_FLASH_D_IE_M (IOMUX_MSPI_PIN_REG_FLASH_D_IE_V << IOMUX_MSPI_PIN_REG_FLASH_D_IE_S) +#define IOMUX_MSPI_PIN_REG_FLASH_D_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_D_IE_S 1 +/** IOMUX_MSPI_PIN_REG_FLASH_D_WPU : R/W; bitpos: [2]; default: 0; + * flash d wpu + */ +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU (BIT(2)) +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU_M (IOMUX_MSPI_PIN_REG_FLASH_D_WPU_V << IOMUX_MSPI_PIN_REG_FLASH_D_WPU_S) +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPU_S 2 +/** IOMUX_MSPI_PIN_REG_FLASH_D_WPD : R/W; bitpos: [3]; default: 0; + * flash d wpd + */ +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD (BIT(3)) +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD_M (IOMUX_MSPI_PIN_REG_FLASH_D_WPD_V << IOMUX_MSPI_PIN_REG_FLASH_D_WPD_S) +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_FLASH_D_WPD_S 3 +/** IOMUX_MSPI_PIN_REG_FLASH_D_DRV : R/W; bitpos: [5:4]; default: 0; + * flash d drv + */ +#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV_M (IOMUX_MSPI_PIN_REG_FLASH_D_DRV_V << IOMUX_MSPI_PIN_REG_FLASH_D_DRV_S) +#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_FLASH_D_DRV_S 4 + +/** IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x1c) +/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLI : R/W; bitpos: [3:0]; default: 0; + * psram d dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLC : R/W; bitpos: [7:4]; default: 0; + * psram d dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_D_HYS : R/W; bitpos: [8]; default: 0; + * psram d hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_D_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPU : R/W; bitpos: [10]; default: 0; + * psram d wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPD : R/W; bitpos: [11]; default: 0; + * psram d wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_D_DRV : R/W; bitpos: [13:12]; default: 0; + * psram d drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x20) +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI : R/W; bitpos: [3:0]; default: 0; + * psram q dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC : R/W; bitpos: [7:4]; default: 0; + * psram q dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS : R/W; bitpos: [8]; default: 0; + * psram q hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU : R/W; bitpos: [10]; default: 0; + * psram q wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD : R/W; bitpos: [11]; default: 0; + * psram q wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV : R/W; bitpos: [13:12]; default: 0; + * psram q drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x24) +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI : R/W; bitpos: [3:0]; default: 0; + * psram wp dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC : R/W; bitpos: [7:4]; default: 0; + * psram wp dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS : R/W; bitpos: [8]; default: 0; + * psram wp hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU : R/W; bitpos: [10]; default: 0; + * psram wp wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD : R/W; bitpos: [11]; default: 0; + * psram wp wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV : R/W; bitpos: [13:12]; default: 0; + * psram wp drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x28) +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI : R/W; bitpos: [3:0]; default: 0; + * psram hold dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC : R/W; bitpos: [7:4]; default: 0; + * psram hold dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS : R/W; bitpos: [8]; default: 0; + * psram hold hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU : R/W; bitpos: [10]; default: 0; + * psram hold wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD : R/W; bitpos: [11]; default: 0; + * psram hold wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV : R/W; bitpos: [13:12]; default: 0; + * psram hold drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x2c) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq4 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq4 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS : R/W; bitpos: [8]; default: 0; + * psram dq4 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU : R/W; bitpos: [10]; default: 0; + * psram dq4 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD : R/W; bitpos: [11]; default: 0; + * psram dq4 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq4 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x30) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq5 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq5 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS : R/W; bitpos: [8]; default: 0; + * psram dq5 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU : R/W; bitpos: [10]; default: 0; + * psram dq5 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD : R/W; bitpos: [11]; default: 0; + * psram dq5 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq5 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x34) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq6 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq6 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS : R/W; bitpos: [8]; default: 0; + * psram dq6 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU : R/W; bitpos: [10]; default: 0; + * psram dq6 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD : R/W; bitpos: [11]; default: 0; + * psram dq6 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq6 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x38) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq7 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq7 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS : R/W; bitpos: [8]; default: 0; + * psram dq7 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU : R/W; bitpos: [10]; default: 0; + * psram dq7 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD : R/W; bitpos: [11]; default: 0; + * psram dq7 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq7 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x3c) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD : R/W; bitpos: [0]; default: 0; + * psram xpd dqs0 + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD (BIT(0)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE : R/W; bitpos: [2:1]; default: 0; + * psram dqs0 phase + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S 1 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI : R/W; bitpos: [6:3]; default: 0; + * psram dqs0 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S 3 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90 : R/W; bitpos: [10:7]; default: 0; + * psram dqs0 delay 90 + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S 7 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS : R/W; bitpos: [11]; default: 0; + * psram dqs0 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE : R/W; bitpos: [12]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE (BIT(12)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S 12 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU : R/W; bitpos: [13]; default: 0; + * psram dqs0 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU (BIT(13)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S 13 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD : R/W; bitpos: [14]; default: 0; + * psram dqs0 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD (BIT(14)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S 14 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV : R/W; bitpos: [16:15]; default: 0; + * psram dqs0 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S 15 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270 : R/W; bitpos: [20:17]; default: 0; + * psram dqs0 delay 270 + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S 17 + +/** IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x40) +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI : R/W; bitpos: [3:0]; default: 0; + * psram ck dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC : R/W; bitpos: [7:4]; default: 0; + * psram ck dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS : R/W; bitpos: [8]; default: 0; + * psram ck hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU : R/W; bitpos: [10]; default: 0; + * psram ck wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD : R/W; bitpos: [11]; default: 0; + * psram ck wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV : R/W; bitpos: [13:12]; default: 0; + * psram ck drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x44) +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI : R/W; bitpos: [3:0]; default: 0; + * psram cs dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC : R/W; bitpos: [7:4]; default: 0; + * psram cs dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS : R/W; bitpos: [8]; default: 0; + * psram cs hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU : R/W; bitpos: [10]; default: 0; + * psram cs wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD : R/W; bitpos: [11]; default: 0; + * psram cs wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV : R/W; bitpos: [13:12]; default: 0; + * psram cs drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ8_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ8_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x48) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq8 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq8 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS : R/W; bitpos: [8]; default: 0; + * psram dq8 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU : R/W; bitpos: [10]; default: 0; + * psram dq8 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD : R/W; bitpos: [11]; default: 0; + * psram dq8 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq8 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ8_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ9_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ9_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x4c) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq9 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq9 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS : R/W; bitpos: [8]; default: 0; + * psram dq9 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU : R/W; bitpos: [10]; default: 0; + * psram dq9 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD : R/W; bitpos: [11]; default: 0; + * psram dq9 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq9 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ9_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ10_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ10_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x50) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq10 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq10 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS : R/W; bitpos: [8]; default: 0; + * psram dq10 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU : R/W; bitpos: [10]; default: 0; + * psram dq10 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD : R/W; bitpos: [11]; default: 0; + * psram dq10 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq10 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ10_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ11_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ11_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x54) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq11 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq11 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS : R/W; bitpos: [8]; default: 0; + * psram dq11 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU : R/W; bitpos: [10]; default: 0; + * psram dq11 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD : R/W; bitpos: [11]; default: 0; + * psram dq11 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq11 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ11_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ12_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ12_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x58) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq12 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq12 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS : R/W; bitpos: [8]; default: 0; + * psram dq12 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU : R/W; bitpos: [10]; default: 0; + * psram dq12 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD : R/W; bitpos: [11]; default: 0; + * psram dq12 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq12 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ12_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ13_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ13_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x5c) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq13 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq13 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS : R/W; bitpos: [8]; default: 0; + * psram dq13 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU : R/W; bitpos: [10]; default: 0; + * psram dq13 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD : R/W; bitpos: [11]; default: 0; + * psram dq13 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq13 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ13_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ14_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ14_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x60) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq14 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq14 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS : R/W; bitpos: [8]; default: 0; + * psram dq14 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU : R/W; bitpos: [10]; default: 0; + * psram dq14 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD : R/W; bitpos: [11]; default: 0; + * psram dq14 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq14 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ14_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQ15_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQ15_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x64) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI : R/W; bitpos: [3:0]; default: 0; + * psram dq15 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLI_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC : R/W; bitpos: [7:4]; default: 0; + * psram dq15 dlc + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DLC_S 4 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS : R/W; bitpos: [8]; default: 0; + * psram dq15 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS (BIT(8)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_HYS_S 8 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE : R/W; bitpos: [9]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE (BIT(9)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_IE_S 9 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU : R/W; bitpos: [10]; default: 0; + * psram dq15 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU (BIT(10)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPU_S 10 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD : R/W; bitpos: [11]; default: 0; + * psram dq15 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_WPD_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV : R/W; bitpos: [13:12]; default: 0; + * psram dq15 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQ15_DRV_S 12 + +/** IOMUX_MSPI_PIN_PSRAM_DQS_1_PIN0_REG register + * IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG + */ +#define IOMUX_MSPI_PIN_PSRAM_DQS_1_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x68) +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD : R/W; bitpos: [0]; default: 0; + * psram xpd dqs1 + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD (BIT(0)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_XPD_S 0 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE : R/W; bitpos: [2:1]; default: 0; + * psram dqs1 phase + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_PHASE_S 1 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI : R/W; bitpos: [6:3]; default: 0; + * psram dqs1 dli + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DLI_S 3 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90 : R/W; bitpos: [10:7]; default: 0; + * psram dqs1 delay 90 + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_90_S 7 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS : R/W; bitpos: [11]; default: 0; + * psram dqs1 hys + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS (BIT(11)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_HYS_S 11 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE : R/W; bitpos: [12]; default: 0; + * Reserved + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE (BIT(12)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_IE_S 12 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU : R/W; bitpos: [13]; default: 0; + * psram dqs1 wpu + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU (BIT(13)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPU_S 13 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD : R/W; bitpos: [14]; default: 0; + * psram dqs1 wpd + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD (BIT(14)) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_V 0x00000001U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_WPD_S 14 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV : R/W; bitpos: [16:15]; default: 0; + * psram dqs1 drv + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_V 0x00000003U +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DRV_S 15 +/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270 : R/W; bitpos: [20:17]; default: 0; + * psram dqs1 delay 270 + */ +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_M (IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_S) +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_V 0x0000000FU +#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_1_DELAY_270_S 17 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_struct.h new file mode 100644 index 0000000000..f5ab610d58 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/iomux_mspi_pin_struct.h @@ -0,0 +1,333 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: clk_en */ +/** Type of clk_en0 register + * apb registers auto clock gating reg + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * 1: auto clock gating on + * 0: auto clock gating off + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} iomux_mspi_pin_clk_en0_reg_t; + + +/** Group: flash_cs_pin */ +/** Type of flash_cs_pin0 register + * IOMUX_MSPI_PIN_FLASH_CS_PIN0_REG + */ +typedef union { + struct { + /** reg_flash_cs_hys : R/W; bitpos: [0]; default: 0; + * flash cs hys + */ + uint32_t reg_flash_cs_hys:1; + /** reg_flash_cs_ie : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t reg_flash_cs_ie:1; + /** reg_flash_cs_wpu : R/W; bitpos: [2]; default: 0; + * flash cs wpu + */ + uint32_t reg_flash_cs_wpu:1; + /** reg_flash_cs_wpd : R/W; bitpos: [3]; default: 0; + * flash cs wpd + */ + uint32_t reg_flash_cs_wpd:1; + /** reg_flash_cs_drv : R/W; bitpos: [5:4]; default: 0; + * flash cs drv + */ + uint32_t reg_flash_cs_drv:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} iomux_mspi_pin_flash_cs_pin0_reg_t; + + +/** Group: flash_q_pin */ +/** Type of flash_q_pin0 register + * IOMUX_MSPI_PIN_FLASH_Q_PIN0_REG + */ +typedef union { + struct { + /** reg_flash_q_hys : R/W; bitpos: [0]; default: 0; + * flash q hys + */ + uint32_t reg_flash_q_hys:1; + /** reg_flash_q_ie : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t reg_flash_q_ie:1; + /** reg_flash_q_wpu : R/W; bitpos: [2]; default: 0; + * flash q wpu + */ + uint32_t reg_flash_q_wpu:1; + /** reg_flash_q_wpd : R/W; bitpos: [3]; default: 0; + * flash q wpd + */ + uint32_t reg_flash_q_wpd:1; + /** reg_flash_q_drv : R/W; bitpos: [5:4]; default: 0; + * flash q drv + */ + uint32_t reg_flash_q_drv:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} iomux_mspi_pin_flash_q_pin0_reg_t; + + +/** Group: flash_wp_pin */ +/** Type of flash_wp_pin0 register + * IOMUX_MSPI_PIN_FLASH_WP_PIN0_REG + */ +typedef union { + struct { + /** reg_flash_wp_hys : R/W; bitpos: [0]; default: 0; + * flash wp hys + */ + uint32_t reg_flash_wp_hys:1; + /** reg_flash_wp_ie : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t reg_flash_wp_ie:1; + /** reg_flash_wp_wpu : R/W; bitpos: [2]; default: 0; + * flash wp wpu + */ + uint32_t reg_flash_wp_wpu:1; + /** reg_flash_wp_wpd : R/W; bitpos: [3]; default: 0; + * flash wp wpd + */ + uint32_t reg_flash_wp_wpd:1; + /** reg_flash_wp_drv : R/W; bitpos: [5:4]; default: 0; + * flash wp drv + */ + uint32_t reg_flash_wp_drv:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} iomux_mspi_pin_flash_wp_pin0_reg_t; + + +/** Group: flash_hold_pin */ +/** Type of flash_hold_pin0 register + * IOMUX_MSPI_PIN_FLASH_HOLD_PIN0_REG + */ +typedef union { + struct { + /** reg_flash_hold_hys : R/W; bitpos: [0]; default: 0; + * flash hold hys + */ + uint32_t reg_flash_hold_hys:1; + /** reg_flash_hold_ie : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t reg_flash_hold_ie:1; + /** reg_flash_hold_wpu : R/W; bitpos: [2]; default: 0; + * flash hold wpu + */ + uint32_t reg_flash_hold_wpu:1; + /** reg_flash_hold_wpd : R/W; bitpos: [3]; default: 0; + * flash hold wpd + */ + uint32_t reg_flash_hold_wpd:1; + /** reg_flash_hold_drv : R/W; bitpos: [5:4]; default: 0; + * flash hold drv + */ + uint32_t reg_flash_hold_drv:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} iomux_mspi_pin_flash_hold_pin0_reg_t; + + +/** Group: flash_ck_pin */ +/** Type of flash_ck_pin0 register + * IOMUX_MSPI_PIN_FLASH_CK_PIN0_REG + */ +typedef union { + struct { + /** reg_flash_ck_hys : R/W; bitpos: [0]; default: 0; + * flash ck hys + */ + uint32_t reg_flash_ck_hys:1; + /** reg_flash_ck_ie : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t reg_flash_ck_ie:1; + /** reg_flash_ck_wpu : R/W; bitpos: [2]; default: 0; + * flash ck wpu + */ + uint32_t reg_flash_ck_wpu:1; + /** reg_flash_ck_wpd : R/W; bitpos: [3]; default: 0; + * flash ck wpd + */ + uint32_t reg_flash_ck_wpd:1; + /** reg_flash_ck_drv : R/W; bitpos: [5:4]; default: 0; + * flash ck drv + */ + uint32_t reg_flash_ck_drv:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} iomux_mspi_pin_flash_ck_pin0_reg_t; + + +/** Group: flash_d_pin */ +/** Type of flash_d_pin0 register + * IOMUX_MSPI_PIN_FLASH_D_PIN0_REG + */ +typedef union { + struct { + /** reg_flash_d_hys : R/W; bitpos: [0]; default: 0; + * flash d hys + */ + uint32_t reg_flash_d_hys:1; + /** reg_flash_d_ie : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t reg_flash_d_ie:1; + /** reg_flash_d_wpu : R/W; bitpos: [2]; default: 0; + * flash d wpu + */ + uint32_t reg_flash_d_wpu:1; + /** reg_flash_d_wpd : R/W; bitpos: [3]; default: 0; + * flash d wpd + */ + uint32_t reg_flash_d_wpd:1; + /** reg_flash_d_drv : R/W; bitpos: [5:4]; default: 0; + * flash d drv + */ + uint32_t reg_flash_d_drv:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} iomux_mspi_pin_flash_d_pin0_reg_t; + + +/** psram_pin */ +typedef union { + struct { + /** reg_psram_pin_dli : R/W; bitpos: [3:0]; default: 0; + * psram pin dli + */ + uint32_t reg_psram_pin_dli:4; + /** reg_psram_pin_dlc : R/W; bitpos: [7:4]; default: 0; + * psram pin dlc + */ + uint32_t reg_psram_pin_dlc:4; + /** reg_psram_pin_hys : R/W; bitpos: [8]; default: 0; + * psram pin hys + */ + uint32_t reg_psram_pin_hys:1; + /** reg_psram_pin_ie : R/W; bitpos: [9]; default: 0; + * Reserved + */ + uint32_t reg_psram_pin_ie:1; + /** reg_psram_pin_wpu : R/W; bitpos: [10]; default: 0; + * psram pin wpu + */ + uint32_t reg_psram_pin_wpu:1; + /** reg_psram_pin_wpd : R/W; bitpos: [11]; default: 0; + * psram pin wpd + */ + uint32_t reg_psram_pin_wpd:1; + /** reg_psram_d_drv : R/W; bitpos: [13:12]; default: 0; + * psram pin drv + */ + uint32_t reg_psram_d_drv:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} iomux_mspi_pin_psram_pin_reg_t; + +/** psram_dqs_pin */ +typedef union { + struct { + /** reg_psram_dqs_xpd : R/W; bitpos: [0]; default: 0; + * psram xpd dqs + */ + uint32_t reg_psram_dqs_xpd:1; + /** reg_psram_dqs_phase : R/W; bitpos: [2:1]; default: 0; + * psram dqs phase + */ + uint32_t reg_psram_dqs_phase:2; + /** reg_psram_dqs_dli : R/W; bitpos: [6:3]; default: 0; + * psram dqs dli + */ + uint32_t reg_psram_dqs_dli:4; + /** reg_psram_dqs_delay_90 : R/W; bitpos: [10:7]; default: 0; + * psram dqs delay 90 + */ + uint32_t reg_psram_dqs_delay_90:4; + /** reg_psram_dqs_hys : R/W; bitpos: [11]; default: 0; + * psram dqs hys + */ + uint32_t reg_psram_dqs_hys:1; + /** reg_psram_dqs_ie : R/W; bitpos: [12]; default: 0; + * Reserved + */ + uint32_t reg_psram_dqs_ie:1; + /** reg_psram_dqs_wpu : R/W; bitpos: [13]; default: 0; + * psram dqs wpu + */ + uint32_t reg_psram_dqs_wpu:1; + /** reg_psram_dqs_wpd : R/W; bitpos: [14]; default: 0; + * psram dqs wpd + */ + uint32_t reg_psram_dqs_wpd:1; + /** reg_psram_dqs_drv : R/W; bitpos: [16:15]; default: 0; + * psram dqs drv + */ + uint32_t reg_psram_dqs_drv:2; + /** reg_psram_dqs_delay_270 : R/W; bitpos: [20:17]; default: 0; + * psram dqs delay 270 + */ + uint32_t reg_psram_dqs_delay_270:4; + uint32_t reserved_21:11; + }; + uint32_t val; +} iomux_mspi_pin_psram_dqs_pin_reg_t; + +/** psram_pin group */ +typedef struct { + volatile iomux_mspi_pin_psram_pin_reg_t pin_group0[8]; //for d, q, wp, hold, dq4, dq5, dq6, dq7 + volatile iomux_mspi_pin_psram_dqs_pin_reg_t dqs0; + volatile iomux_mspi_pin_psram_pin_reg_t pin_group1[10]; //for ck, cs, dq8, dq9, dq10, dq11, dq12, dq13, dq14, dq15 + volatile iomux_mspi_pin_psram_dqs_pin_reg_t dqs1; +} iomux_mspi_pin_psram_pin_grp_reg_t; + +typedef struct { + volatile iomux_mspi_pin_clk_en0_reg_t clk_en0; + volatile iomux_mspi_pin_flash_cs_pin0_reg_t flash_cs_pin0; + volatile iomux_mspi_pin_flash_q_pin0_reg_t flash_q_pin0; + volatile iomux_mspi_pin_flash_wp_pin0_reg_t flash_wp_pin0; + volatile iomux_mspi_pin_flash_hold_pin0_reg_t flash_hold_pin0; + volatile iomux_mspi_pin_flash_ck_pin0_reg_t flash_ck_pin0; + volatile iomux_mspi_pin_flash_d_pin0_reg_t flash_d_pin0; + volatile iomux_mspi_pin_psram_pin_grp_reg_t psram_pin_group; +} iomux_mspi_pin_dev_t; + +extern iomux_mspi_pin_dev_t MSPI_IOMUX; + +#ifndef __cplusplus +_Static_assert(sizeof(iomux_mspi_pin_dev_t) == 0x6c, "Invalid size of iomux_mspi_pin_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/isp_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/isp_eco5_struct.h new file mode 100644 index 0000000000..ce7d9518aa --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/isp_eco5_struct.h @@ -0,0 +1,4182 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Version Register */ +/** Type of ver_date register + * version control register + */ +typedef union { + struct { + /** ver_data : R/W; bitpos: [31:0]; default: 539035144; + * csv version + */ + uint32_t ver_data:32; + }; + uint32_t val; +} isp_ver_date_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clk_en register + * isp clk control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * this bit configures the clk force on of isp reg. 0: disable, 1: enable + */ + uint32_t clk_en:1; + /** clk_blc_force_on : R/W; bitpos: [1]; default: 0; + * this bit configures the clk force on of blc. 0: disable, 1: enable + */ + uint32_t clk_blc_force_on:1; + /** clk_dpc_force_on : R/W; bitpos: [2]; default: 0; + * this bit configures the clk force on of dpc. 0: disable, 1: enable + */ + uint32_t clk_dpc_force_on:1; + /** clk_bf_force_on : R/W; bitpos: [3]; default: 0; + * this bit configures the clk force on of bf. 0: disable, 1: enable + */ + uint32_t clk_bf_force_on:1; + /** clk_lsc_force_on : R/W; bitpos: [4]; default: 0; + * this bit configures the clk force on of lsc. 0: disable, 1: enable + */ + uint32_t clk_lsc_force_on:1; + /** clk_demosaic_force_on : R/W; bitpos: [5]; default: 0; + * this bit configures the clk force on of demosaic. 0: disable, 1: enable + */ + uint32_t clk_demosaic_force_on:1; + /** clk_median_force_on : R/W; bitpos: [6]; default: 0; + * this bit configures the clk force on of median. 0: disable, 1: enable + */ + uint32_t clk_median_force_on:1; + /** clk_ccm_force_on : R/W; bitpos: [7]; default: 0; + * this bit configures the clk force on of ccm. 0: disable, 1: enable + */ + uint32_t clk_ccm_force_on:1; + /** clk_gamma_force_on : R/W; bitpos: [8]; default: 0; + * this bit configures the clk force on of gamma. 0: disable, 1: enable + */ + uint32_t clk_gamma_force_on:1; + /** clk_rgb2yuv_force_on : R/W; bitpos: [9]; default: 0; + * this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable + */ + uint32_t clk_rgb2yuv_force_on:1; + /** clk_sharp_force_on : R/W; bitpos: [10]; default: 0; + * this bit configures the clk force on of sharp. 0: disable, 1: enable + */ + uint32_t clk_sharp_force_on:1; + /** clk_color_force_on : R/W; bitpos: [11]; default: 0; + * this bit configures the clk force on of color. 0: disable, 1: enable + */ + uint32_t clk_color_force_on:1; + /** clk_yuv2rgb_force_on : R/W; bitpos: [12]; default: 0; + * this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable + */ + uint32_t clk_yuv2rgb_force_on:1; + /** clk_ae_force_on : R/W; bitpos: [13]; default: 0; + * this bit configures the clk force on of ae. 0: disable, 1: enable + */ + uint32_t clk_ae_force_on:1; + /** clk_af_force_on : R/W; bitpos: [14]; default: 0; + * this bit configures the clk force on of af. 0: disable, 1: enable + */ + uint32_t clk_af_force_on:1; + /** clk_awb_force_on : R/W; bitpos: [15]; default: 0; + * this bit configures the clk force on of awb. 0: disable, 1: enable + */ + uint32_t clk_awb_force_on:1; + /** clk_hist_force_on : R/W; bitpos: [16]; default: 0; + * this bit configures the clk force on of hist. 0: disable, 1: enable + */ + uint32_t clk_hist_force_on:1; + /** clk_mipi_idi_force_on : R/W; bitpos: [17]; default: 0; + * this bit configures the clk force on of mipi idi input. 0: disable, 1: enable + */ + uint32_t clk_mipi_idi_force_on:1; + /** isp_mem_clk_force_on : R/W; bitpos: [18]; default: 0; + * this bit configures the clk force on of all isp memory. 0: disable, 1: enable + */ + uint32_t isp_mem_clk_force_on:1; + /** clk_crop_force_on : R/W; bitpos: [19]; default: 0; + * this bit configures the clk force on of crop. 0: disable, 1: enable + */ + uint32_t clk_crop_force_on:1; + /** clk_wbg_force_on : R/W; bitpos: [20]; default: 0; + * this bit configures the clk force on of wbg. 0: disable, 1: enable + */ + uint32_t clk_wbg_force_on:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} isp_clk_en_reg_t; + +/** Type of cntl register + * isp module enable control register + */ +typedef union { + struct { + /** mipi_data_en : R/W; bitpos: [0]; default: 0; + * this bit configures mipi input data enable. 0: disable, 1: enable + */ + uint32_t mipi_data_en:1; + /** isp_en : R/W; bitpos: [1]; default: 1; + * this bit configures isp global enable. 0: disable, 1: enable + */ + uint32_t isp_en:1; + /** blc_en : R/W; bitpos: [2]; default: 0; + * this bit configures blc enable. 0: disable, 1: enable + */ + uint32_t blc_en:1; + /** dpc_en : R/W; bitpos: [3]; default: 0; + * this bit configures dpc enable. 0: disable, 1: enable + */ + uint32_t dpc_en:1; + /** bf_en : R/W; bitpos: [4]; default: 0; + * this bit configures bf enable. 0: disable, 1: enable + */ + uint32_t bf_en:1; + /** lsc_en : R/W; bitpos: [5]; default: 0; + * this bit configures lsc enable. 0: disable, 1: enable + */ + uint32_t lsc_en:1; + /** demosaic_en : R/W; bitpos: [6]; default: 1; + * this bit configures demosaic enable. 0: disable, 1: enable + */ + uint32_t demosaic_en:1; + /** median_en : R/W; bitpos: [7]; default: 0; + * this bit configures median enable. 0: disable, 1: enable + */ + uint32_t median_en:1; + /** ccm_en : R/W; bitpos: [8]; default: 0; + * this bit configures ccm enable. 0: disable, 1: enable + */ + uint32_t ccm_en:1; + /** gamma_en : R/W; bitpos: [9]; default: 0; + * this bit configures gamma enable. 0: disable, 1: enable + */ + uint32_t gamma_en:1; + /** rgb2yuv_en : R/W; bitpos: [10]; default: 1; + * this bit configures rgb2yuv enable. 0: disable, 1: enable + */ + uint32_t rgb2yuv_en:1; + /** sharp_en : R/W; bitpos: [11]; default: 0; + * this bit configures sharp enable. 0: disable, 1: enable + */ + uint32_t sharp_en:1; + /** color_en : R/W; bitpos: [12]; default: 0; + * this bit configures color enable. 0: disable, 1: enable + */ + uint32_t color_en:1; + /** yuv2rgb_en : R/W; bitpos: [13]; default: 1; + * this bit configures yuv2rgb enable. 0: disable, 1: enable + */ + uint32_t yuv2rgb_en:1; + /** ae_en : R/W; bitpos: [14]; default: 0; + * this bit configures ae enable. 0: disable, 1: enable + */ + uint32_t ae_en:1; + /** af_en : R/W; bitpos: [15]; default: 0; + * this bit configures af enable. 0: disable, 1: enable + */ + uint32_t af_en:1; + /** awb_en : R/W; bitpos: [16]; default: 0; + * this bit configures awb enable. 0: disable, 1: enable + */ + uint32_t awb_en:1; + /** hist_en : R/W; bitpos: [17]; default: 0; + * this bit configures hist enable. 0: disable, 1: enable + */ + uint32_t hist_en:1; + /** crop_en : R/W; bitpos: [18]; default: 0; + * this bit configures crop enable. 0: disable, 1: enable + */ + uint32_t crop_en:1; + /** wbg_en : R/W; bitpos: [19]; default: 0; + * this bit configures wbg enable. 0: disable, 1: enable + */ + uint32_t wbg_en:1; + uint32_t reserved_20:4; + /** byte_endian_order : R/W; bitpos: [24]; default: 0; + * select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: + * {[7:0], [15:8], [23:16], [31:24]} + */ + uint32_t byte_endian_order:1; + /** isp_data_type : R/W; bitpos: [26:25]; default: 0; + * this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 + */ + uint32_t isp_data_type:2; + /** isp_in_src : R/W; bitpos: [28:27]; default: 0; + * this field configures input data source, 0:CSI HOST 1:CAM 2:DMA + */ + uint32_t isp_in_src:2; + /** isp_out_type : R/W; bitpos: [31:29]; default: 2; + * this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: + * RGB565 + */ + uint32_t isp_out_type:3; + }; + uint32_t val; +} isp_cntl_reg_t; + +/** Type of hsync_cnt register + * header hsync interval control register + */ +typedef union { + struct { + /** hsync_cnt : R/W; bitpos: [7:0]; default: 7; + * this field configures the number of clock before hsync and after vsync and line_end + * when decodes pix data from idi to isp + */ + uint32_t hsync_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} isp_hsync_cnt_reg_t; + +/** Type of frame_cfg register + * frame control parameter register + */ +typedef union { + struct { + /** vadr_num : R/W; bitpos: [11:0]; default: 480; + * this field configures input image size in y-direction, image row number - 1 + */ + uint32_t vadr_num:12; + /** hadr_num : R/W; bitpos: [23:12]; default: 480; + * this field configures input image size in x-direction, image line number - 1 + */ + uint32_t hadr_num:12; + uint32_t reserved_24:3; + /** bayer_mode : R/W; bitpos: [28:27]; default: 0; + * this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 + * : GR/BG 11 : RG/GB + */ + uint32_t bayer_mode:2; + /** hsync_start_exist : R/W; bitpos: [29]; default: 1; + * this bit configures the line end packet exist or not. 0: not exist, 1: exist + */ + uint32_t hsync_start_exist:1; + /** hsync_end_exist : R/W; bitpos: [30]; default: 1; + * this bit configures the line start packet exist or not. 0: not exist, 1: exist + */ + uint32_t hsync_end_exist:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} isp_frame_cfg_reg_t; + +/** Type of ccm_coef0 register + * ccm coef register 0 + */ +typedef union { + struct { + /** ccm_rr : R/W; bitpos: [12:0]; default: 256; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_rr:13; + /** ccm_rg : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_rg:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef0_reg_t; + +/** Type of ccm_coef1 register + * ccm coef register 1 + */ +typedef union { + struct { + /** ccm_rb : R/W; bitpos: [12:0]; default: 0; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_rb:13; + /** ccm_gr : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_gr:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef1_reg_t; + +/** Type of ccm_coef3 register + * ccm coef register 3 + */ +typedef union { + struct { + /** ccm_gg : R/W; bitpos: [12:0]; default: 256; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_gg:13; + /** ccm_gb : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_gb:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef3_reg_t; + +/** Type of ccm_coef4 register + * ccm coef register 4 + */ +typedef union { + struct { + /** ccm_br : R/W; bitpos: [12:0]; default: 0; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_br:13; + /** ccm_bg : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_bg:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef4_reg_t; + +/** Type of ccm_coef5 register + * ccm coef register 5 + */ +typedef union { + struct { + /** ccm_bb : R/W; bitpos: [12:0]; default: 256; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_bb:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} isp_ccm_coef5_reg_t; + +/** Type of bf_matrix_ctrl register + * bf pix2matrix ctrl + */ +typedef union { + struct { + /** bf_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 + * and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse + * function + */ + uint32_t bf_tail_pixen_pulse_tl:8; + /** bf_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and + * reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse + * function + */ + uint32_t bf_tail_pixen_pulse_th:8; + /** bf_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures bf matrix padding data + */ + uint32_t bf_padding_data:8; + /** bf_padding_mode : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of bf matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ + uint32_t bf_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_bf_matrix_ctrl_reg_t; + +/** Type of bf_sigma register + * bf denoising level control register + */ +typedef union { + struct { + /** sigma : R/W; bitpos: [5:0]; default: 2; + * this field configures the bayer denoising level, valid data from 2 to 20 + */ + uint32_t sigma:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_bf_sigma_reg_t; + +/** Type of bf_gau0 register + * bf gau template register 0 + */ +typedef union { + struct { + /** gau_template21 : R/W; bitpos: [3:0]; default: 15; + * this field configures index 21 of gaussian template + */ + uint32_t gau_template21:4; + /** gau_template20 : R/W; bitpos: [7:4]; default: 15; + * this field configures index 20 of gaussian template + */ + uint32_t gau_template20:4; + /** gau_template12 : R/W; bitpos: [11:8]; default: 15; + * this field configures index 12 of gaussian template + */ + uint32_t gau_template12:4; + /** gau_template11 : R/W; bitpos: [15:12]; default: 15; + * this field configures index 11 of gaussian template + */ + uint32_t gau_template11:4; + /** gau_template10 : R/W; bitpos: [19:16]; default: 15; + * this field configures index 10 of gaussian template + */ + uint32_t gau_template10:4; + /** gau_template02 : R/W; bitpos: [23:20]; default: 15; + * this field configures index 02 of gaussian template + */ + uint32_t gau_template02:4; + /** gau_template01 : R/W; bitpos: [27:24]; default: 15; + * this field configures index 01 of gaussian template + */ + uint32_t gau_template01:4; + /** gau_template00 : R/W; bitpos: [31:28]; default: 15; + * this field configures index 00 of gaussian template + */ + uint32_t gau_template00:4; + }; + uint32_t val; +} isp_bf_gau0_reg_t; + +/** Type of bf_gau1 register + * bf gau template register 1 + */ +typedef union { + struct { + /** gau_template22 : R/W; bitpos: [3:0]; default: 15; + * this field configures index 22 of gaussian template + */ + uint32_t gau_template22:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_bf_gau1_reg_t; + +/** Type of dpc_ctrl register + * DPC mode control register + */ +typedef union { + struct { + /** dpc_check_en : R/W; bitpos: [0]; default: 0; + * this bit configures the check mode enable. 0: disable, 1: enable + */ + uint32_t dpc_check_en:1; + /** sta_en : R/W; bitpos: [1]; default: 0; + * this bit configures the sta dpc enable. 0: disable, 1: enable + */ + uint32_t sta_en:1; + /** dyn_en : R/W; bitpos: [2]; default: 1; + * this bit configures the dyn dpc enable. 0: disable, 1: enable + */ + uint32_t dyn_en:1; + /** dpc_black_en : R/W; bitpos: [3]; default: 0; + * this bit configures input image type select when in check mode, 0: white img, 1: + * black img + */ + uint32_t dpc_black_en:1; + /** dpc_method_sel : R/W; bitpos: [4]; default: 0; + * this bit configures dyn dpc method select. 0: simple method, 1: hard method + */ + uint32_t dpc_method_sel:1; + /** dpc_check_od_en : R/W; bitpos: [5]; default: 0; + * this bit configures output pixel data when in check mode or not. 0: no data output, + * 1: data output + */ + uint32_t dpc_check_od_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_dpc_ctrl_reg_t; + +/** Type of dpc_conf register + * DPC parameter config register + */ +typedef union { + struct { + /** dpc_threshold_l : R/W; bitpos: [7:0]; default: 48; + * this bit configures the threshold to detect black img in check mode, or the low + * threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit + * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + */ + uint32_t dpc_threshold_l:8; + /** dpc_threshold_h : R/W; bitpos: [15:8]; default: 48; + * this bit configures the threshold to detect white img in check mode, or the high + * threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit + * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + */ + uint32_t dpc_threshold_h:8; + /** dpc_factor_dark : R/W; bitpos: [21:16]; default: 16; + * this field configures the dynamic correction method 1 dark factor + */ + uint32_t dpc_factor_dark:6; + /** dpc_factor_brig : R/W; bitpos: [27:22]; default: 16; + * this field configures the dynamic correction method 1 bright factor + */ + uint32_t dpc_factor_brig:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_dpc_conf_reg_t; + +/** Type of dpc_matrix_ctrl register + * dpc pix2matrix ctrl + */ +typedef union { + struct { + /** dpc_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 + * and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail + * pulse function + */ + uint32_t dpc_tail_pixen_pulse_tl:8; + /** dpc_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and + * reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse + * function + */ + uint32_t dpc_tail_pixen_pulse_th:8; + /** dpc_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures dpc matrix padding data + */ + uint32_t dpc_padding_data:8; + /** dpc_padding_mode : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of dpc matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ + uint32_t dpc_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_dpc_matrix_ctrl_reg_t; + +/** Type of lut_cmd register + * LUT command register + */ +typedef union { + struct { + /** lut_addr : WT; bitpos: [11:0]; default: 0; + * this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b + * lut, 01 sel r_gr lut + */ + uint32_t lut_addr:12; + /** lut_num : WT; bitpos: [15:12]; default: 0; + * this field configures the lut selection. 0000:LSC LUT. 0001:DPC LUT. 0010:AWB LUT + */ + uint32_t lut_num:4; + /** lut_cmd : WT; bitpos: [16]; default: 0; + * this bit configures the access event of lut. 0:rd 1: wr + */ + uint32_t lut_cmd:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_lut_cmd_reg_t; + +/** Type of lut_wdata register + * LUT write data register + */ +typedef union { + struct { + /** lut_wdata : R/W; bitpos: [31:0]; default: 0; + * this field configures the write data of lut. please initial ISP_LUT_WDATA before + * write ISP_LUT_CMD register + */ + uint32_t lut_wdata:32; + }; + uint32_t val; +} isp_lut_wdata_reg_t; + +/** Type of lsc_tablesize register + * LSC point in x-direction + */ +typedef union { + struct { + /** lsc_xtablesize : R/W; bitpos: [4:0]; default: 31; + * this field configures lsc table size in x-direction + */ + uint32_t lsc_xtablesize:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} isp_lsc_tablesize_reg_t; + +/** Type of demosaic_matrix_ctrl register + * demosaic pix2matrix ctrl + */ +typedef union { + struct { + /** demosaic_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and + * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < + * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + */ + uint32_t demosaic_tail_pixen_pulse_tl:8; + /** demosaic_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and + * reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable + * tail pulse function + */ + uint32_t demosaic_tail_pixen_pulse_th:8; + /** demosaic_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures demosaic matrix padding data + */ + uint32_t demosaic_padding_data:8; + /** demosaic_padding_mode : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of demosaic matrix. 0: use pixel in image to + * do padding 1: use reg_padding_data to do padding + */ + uint32_t demosaic_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_demosaic_matrix_ctrl_reg_t; + +/** Type of demosaic_grad_ratio register + * demosaic gradient select ratio + */ +typedef union { + struct { + /** demosaic_grad_ratio : R/W; bitpos: [5:0]; default: 16; + * this field configures demosaic gradient select ratio + */ + uint32_t demosaic_grad_ratio:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_demosaic_grad_ratio_reg_t; + +/** Type of median_matrix_ctrl register + * median pix2matrix ctrl + */ +typedef union { + struct { + /** median_padding_data : R/W; bitpos: [7:0]; default: 0; + * this field configures median matrix padding data + */ + uint32_t median_padding_data:8; + /** median_padding_mode : R/W; bitpos: [8]; default: 0; + * this bit configures the padding mode of median matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ + uint32_t median_padding_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} isp_median_matrix_ctrl_reg_t; + +/** Type of gamma_ctrl register + * gamma control register + */ +typedef union { + struct { + /** gamma_update : R/W; bitpos: [0]; default: 0; + * Indicates that gamma register configuration is complete + */ + uint32_t gamma_update:1; + /** gamma_b_last_correct : R/W; bitpos: [1]; default: 1; + * this bit configures enable of last b segment correcction. 0: disable, 1: enable + */ + uint32_t gamma_b_last_correct:1; + /** gamma_g_last_correct : R/W; bitpos: [2]; default: 1; + * this bit configures enable of last g segment correcction. 0: disable, 1: enable + */ + uint32_t gamma_g_last_correct:1; + /** gamma_r_last_correct : R/W; bitpos: [3]; default: 1; + * this bit configures enable of last r segment correcction. 0: disable, 1: enable + */ + uint32_t gamma_r_last_correct:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_gamma_ctrl_reg_t; + +/** Type of gamma_ry1 register + * point of Y-axis of r channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_r_y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y03:8; + /** gamma_r_y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y02:8; + /** gamma_r_y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y01:8; + /** gamma_r_y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y00:8; + }; + uint32_t val; +} isp_gamma_ry1_reg_t; + +/** Type of gamma_ry2 register + * point of Y-axis of r channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_r_y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y07:8; + /** gamma_r_y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y06:8; + /** gamma_r_y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y05:8; + /** gamma_r_y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y04:8; + }; + uint32_t val; +} isp_gamma_ry2_reg_t; + +/** Type of gamma_ry3 register + * point of Y-axis of r channel gamma curve register 3 + */ +typedef union { + struct { + /** gamma_r_y0b : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y0b:8; + /** gamma_r_y0a : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y0a:8; + /** gamma_r_y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y09:8; + /** gamma_r_y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y08:8; + }; + uint32_t val; +} isp_gamma_ry3_reg_t; + +/** Type of gamma_ry4 register + * point of Y-axis of r channel gamma curve register 4 + */ +typedef union { + struct { + /** gamma_r_y0f : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y0f:8; + /** gamma_r_y0e : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y0e:8; + /** gamma_r_y0d : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y0d:8; + /** gamma_r_y0c : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of r channel gamma curve + */ + uint32_t gamma_r_y0c:8; + }; + uint32_t val; +} isp_gamma_ry4_reg_t; + +/** Type of gamma_gy1 register + * point of Y-axis of g channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_g_y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y03:8; + /** gamma_g_y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y02:8; + /** gamma_g_y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y01:8; + /** gamma_g_y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y00:8; + }; + uint32_t val; +} isp_gamma_gy1_reg_t; + +/** Type of gamma_gy2 register + * point of Y-axis of g channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_g_y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y07:8; + /** gamma_g_y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y06:8; + /** gamma_g_y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y05:8; + /** gamma_g_y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y04:8; + }; + uint32_t val; +} isp_gamma_gy2_reg_t; + +/** Type of gamma_gy3 register + * point of Y-axis of g channel gamma curve register 3 + */ +typedef union { + struct { + /** gamma_g_y0b : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y0b:8; + /** gamma_g_y0a : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y0a:8; + /** gamma_g_y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y09:8; + /** gamma_g_y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y08:8; + }; + uint32_t val; +} isp_gamma_gy3_reg_t; + +/** Type of gamma_gy4 register + * point of Y-axis of g channel gamma curve register 4 + */ +typedef union { + struct { + /** gamma_g_y0f : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y0f:8; + /** gamma_g_y0e : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y0e:8; + /** gamma_g_y0d : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y0d:8; + /** gamma_g_y0c : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of g channel gamma curve + */ + uint32_t gamma_g_y0c:8; + }; + uint32_t val; +} isp_gamma_gy4_reg_t; + +/** Type of gamma_by1 register + * point of Y-axis of b channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_b_y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y03:8; + /** gamma_b_y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y02:8; + /** gamma_b_y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y01:8; + /** gamma_b_y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y00:8; + }; + uint32_t val; +} isp_gamma_by1_reg_t; + +/** Type of gamma_by2 register + * point of Y-axis of b channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_b_y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y07:8; + /** gamma_b_y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y06:8; + /** gamma_b_y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y05:8; + /** gamma_b_y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y04:8; + }; + uint32_t val; +} isp_gamma_by2_reg_t; + +/** Type of gamma_by3 register + * point of Y-axis of b channel gamma curve register 3 + */ +typedef union { + struct { + /** gamma_b_y0b : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y0b:8; + /** gamma_b_y0a : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y0a:8; + /** gamma_b_y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y09:8; + /** gamma_b_y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y08:8; + }; + uint32_t val; +} isp_gamma_by3_reg_t; + +/** Type of gamma_by4 register + * point of Y-axis of b channel gamma curve register 4 + */ +typedef union { + struct { + /** gamma_b_y0f : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y0f:8; + /** gamma_b_y0e : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y0e:8; + /** gamma_b_y0d : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y0d:8; + /** gamma_b_y0c : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of b channel gamma curve + */ + uint32_t gamma_b_y0c:8; + }; + uint32_t val; +} isp_gamma_by4_reg_t; + +/** Type of gamma_rx1 register + * point of X-axis of r channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_r_x07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x07:3; + /** gamma_r_x06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x06:3; + /** gamma_r_x05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x05:3; + /** gamma_r_x04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x04:3; + /** gamma_r_x03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x03:3; + /** gamma_r_x02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x02:3; + /** gamma_r_x01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x01:3; + /** gamma_r_x00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x00:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_rx1_reg_t; + +/** Type of gamma_rx2 register + * point of X-axis of r channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_r_x0f : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_r_x0f:3; + /** gamma_r_x0e : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_r_x0e:3; + /** gamma_r_x0d : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_r_x0d:3; + /** gamma_r_x0c : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_r_x0c:3; + /** gamma_r_x0b : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_r_x0b:3; + /** gamma_r_x0a : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_r_x0a:3; + /** gamma_r_x09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x09:3; + /** gamma_r_x08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_r_x08:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_rx2_reg_t; + +/** Type of gamma_gx1 register + * point of X-axis of g channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_g_x07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x07:3; + /** gamma_g_x06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x06:3; + /** gamma_g_x05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x05:3; + /** gamma_g_x04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x04:3; + /** gamma_g_x03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x03:3; + /** gamma_g_x02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x02:3; + /** gamma_g_x01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x01:3; + /** gamma_g_x00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x00:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_gx1_reg_t; + +/** Type of gamma_gx2 register + * point of X-axis of g channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_g_x0f : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_g_x0f:3; + /** gamma_g_x0e : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_g_x0e:3; + /** gamma_g_x0d : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_g_x0d:3; + /** gamma_g_x0c : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_g_x0c:3; + /** gamma_g_x0b : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_g_x0b:3; + /** gamma_g_x0a : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_g_x0a:3; + /** gamma_g_x09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x09:3; + /** gamma_g_x08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_g_x08:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_gx2_reg_t; + +/** Type of gamma_bx1 register + * point of X-axis of b channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_b_x07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x07:3; + /** gamma_b_x06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x06:3; + /** gamma_b_x05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x05:3; + /** gamma_b_x04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x04:3; + /** gamma_b_x03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x03:3; + /** gamma_b_x02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x02:3; + /** gamma_b_x01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x01:3; + /** gamma_b_x00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x00:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_bx1_reg_t; + +/** Type of gamma_bx2 register + * point of X-axis of b channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_b_x0f : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_b_x0f:3; + /** gamma_b_x0e : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_b_x0e:3; + /** gamma_b_x0d : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_b_x0d:3; + /** gamma_b_x0c : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_b_x0c:3; + /** gamma_b_x0b : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_b_x0b:3; + /** gamma_b_x0a : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_b_x0a:3; + /** gamma_b_x09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x09:3; + /** gamma_b_x08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_b_x08:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_bx2_reg_t; + +/** Type of ae_ctrl register + * ae control register + */ +typedef union { + struct { + /** ae_update : WT; bitpos: [0]; default: 0; + * write 1 to this bit triggers one statistic event + */ + uint32_t ae_update:1; + /** ae_select : R/W; bitpos: [1]; default: 0; + * this field configures ae input data source, 0: data from median, 1: data from gama + */ + uint32_t ae_select:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_ae_ctrl_reg_t; + +/** Type of ae_monitor register + * ae monitor control register + */ +typedef union { + struct { + /** ae_monitor_tl : R/W; bitpos: [7:0]; default: 0; + * this field configures the lower lum threshold of ae monitor + */ + uint32_t ae_monitor_tl:8; + /** ae_monitor_th : R/W; bitpos: [15:8]; default: 0; + * this field configures the higher lum threshold of ae monitor + */ + uint32_t ae_monitor_th:8; + /** ae_monitor_period : R/W; bitpos: [21:16]; default: 0; + * this field configures ae monitor frame period + */ + uint32_t ae_monitor_period:6; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_ae_monitor_reg_t; + +/** Type of ae_bx register + * ae window register in x-direction + */ +typedef union { + struct { + /** ae_x_bsize : R/W; bitpos: [10:0]; default: 384; + * this field configures every block x size + */ + uint32_t ae_x_bsize:11; + /** ae_x_start : R/W; bitpos: [21:11]; default: 0; + * this field configures first block start x address + */ + uint32_t ae_x_start:11; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_ae_bx_reg_t; + +/** Type of ae_by register + * ae window register in y-direction + */ +typedef union { + struct { + /** ae_y_bsize : R/W; bitpos: [10:0]; default: 216; + * this field configures every block y size + */ + uint32_t ae_y_bsize:11; + /** ae_y_start : R/W; bitpos: [21:11]; default: 0; + * this field configures first block start y address + */ + uint32_t ae_y_start:11; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_ae_by_reg_t; + +/** Type of ae_winpixnum register + * ae sub-window pix num register + */ +typedef union { + struct { + /** ae_subwin_pixnum : R/W; bitpos: [16:0]; default: 82944; + * this field configures the pixel number of each sub win + */ + uint32_t ae_subwin_pixnum:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_ae_winpixnum_reg_t; + +/** Type of ae_win_reciprocal register + * reciprocal of ae sub-window pixel number + */ +typedef union { + struct { + /** ae_subwin_recip : R/W; bitpos: [19:0]; default: 0; + * this field configures the reciprocal of each subwin_pixnum, 20bit fraction + */ + uint32_t ae_subwin_recip:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} isp_ae_win_reciprocal_reg_t; + +/** Type of sharp_ctrl0 register + * sharp control register 0 + */ +typedef union { + struct { + /** sharp_threshold_low : R/W; bitpos: [7:0]; default: 0; + * this field configures sharpen threshold for detail + */ + uint32_t sharp_threshold_low:8; + /** sharp_threshold_high : R/W; bitpos: [15:8]; default: 0; + * this field configures sharpen threshold for edge + */ + uint32_t sharp_threshold_high:8; + /** sharp_amount_low : R/W; bitpos: [23:16]; default: 0; + * this field configures sharpen amount for detail + */ + uint32_t sharp_amount_low:8; + /** sharp_amount_high : R/W; bitpos: [31:24]; default: 0; + * this field configures sharpen amount for edge + */ + uint32_t sharp_amount_high:8; + }; + uint32_t val; +} isp_sharp_ctrl0_reg_t; + +/** Type of sharp_filter0 register + * sharp usm config register 0 + */ +typedef union { + struct { + /** sharp_filter_coe00 : R/W; bitpos: [4:0]; default: 1; + * this field configures unsharp masking(usm) filter coefficient + */ + uint32_t sharp_filter_coe00:5; + /** sharp_filter_coe01 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe01:5; + /** sharp_filter_coe02 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe02:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter0_reg_t; + +/** Type of sharp_filter1 register + * sharp usm config register 1 + */ +typedef union { + struct { + /** sharp_filter_coe10 : R/W; bitpos: [4:0]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe10:5; + /** sharp_filter_coe11 : R/W; bitpos: [9:5]; default: 4; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe11:5; + /** sharp_filter_coe12 : R/W; bitpos: [14:10]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe12:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter1_reg_t; + +/** Type of sharp_filter2 register + * sharp usm config register 2 + */ +typedef union { + struct { + /** sharp_filter_coe20 : R/W; bitpos: [4:0]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe20:5; + /** sharp_filter_coe21 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe21:5; + /** sharp_filter_coe22 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe22:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter2_reg_t; + +/** Type of sharp_matrix_ctrl register + * sharp pix2matrix ctrl + */ +typedef union { + struct { + /** sharp_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and + * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < + * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + */ + uint32_t sharp_tail_pixen_pulse_tl:8; + /** sharp_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and + * reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail + * pulse function + */ + uint32_t sharp_tail_pixen_pulse_th:8; + /** sharp_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures sharp padding data + */ + uint32_t sharp_padding_data:8; + /** sharp_padding_mode : R/W; bitpos: [24]; default: 0; + * this field configures sharp padding mode + */ + uint32_t sharp_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_sharp_matrix_ctrl_reg_t; + +/** Type of sharp_ctrl1 register + * sharp control register 1 + */ +typedef union { + struct { + /** sharp_gradient_max : RO; bitpos: [7:0]; default: 0; + * this field configures sharp max gradient, refresh at the end of each frame end + */ + uint32_t sharp_gradient_max:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} isp_sharp_ctrl1_reg_t; + +/** Type of dma_cntl register + * isp dma source trans control register + */ +typedef union { + struct { + /** dma_en : WT; bitpos: [0]; default: 0; + * write 1 to trigger dma to get 1 frame + */ + uint32_t dma_en:1; + /** dma_update_reg : R/W; bitpos: [1]; default: 0; + * write 1 to update reg_dma_burst_len & reg_dma_data_type + */ + uint32_t dma_update_reg:1; + /** dma_data_type : R/W; bitpos: [7:2]; default: 42; + * this field configures the idi data type for image data + */ + uint32_t dma_data_type:6; + /** dma_burst_len : R/W; bitpos: [19:8]; default: 128; + * this field configures dma burst len when data source is dma. set according to + * dma_msize, it is the number of 64bits in a dma transfer + */ + uint32_t dma_burst_len:12; + /** dma_interval : R/W; bitpos: [31:20]; default: 1; + * this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... + */ + uint32_t dma_interval:12; + }; + uint32_t val; +} isp_dma_cntl_reg_t; + +/** Type of dma_raw_data register + * isp dma source total raw number set register + */ +typedef union { + struct { + /** dma_raw_num_total : R/W; bitpos: [21:0]; default: 0; + * this field configures the the number of 64bits in a frame + */ + uint32_t dma_raw_num_total:22; + uint32_t reserved_22:9; + /** dma_raw_num_total_set : WT; bitpos: [31]; default: 0; + * write 1 to update reg_dma_raw_num_total + */ + uint32_t dma_raw_num_total_set:1; + }; + uint32_t val; +} isp_dma_raw_data_reg_t; + +/** Type of cam_cntl register + * isp cam source control register + */ +typedef union { + struct { + /** cam_en : R/W; bitpos: [0]; default: 0; + * write 1 to start receive camera data, write 0 to disable + */ + uint32_t cam_en:1; + /** cam_update_reg : R/W; bitpos: [1]; default: 0; + * write 1 to update ISP_CAM_CONF + */ + uint32_t cam_update_reg:1; + /** cam_reset : R/W; bitpos: [2]; default: 1; + * this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset + */ + uint32_t cam_reset:1; + /** cam_clk_inv : R/W; bitpos: [3]; default: 0; + * this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1: + * invert cam clk + */ + uint32_t cam_clk_inv:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_cam_cntl_reg_t; + +/** Type of cam_conf register + * isp cam source config register + */ +typedef union { + struct { + /** cam_data_order : R/W; bitpos: [0]; default: 0; + * this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], + * cam_data_in[15:8]} + */ + uint32_t cam_data_order:1; + /** cam_2byte_mode : R/W; bitpos: [1]; default: 0; + * this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: + * disable, 1: enable + */ + uint32_t cam_2byte_mode:1; + /** cam_data_type : R/W; bitpos: [7:2]; default: 42; + * this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: + * RAW12 + */ + uint32_t cam_data_type:6; + /** cam_de_inv : R/W; bitpos: [8]; default: 0; + * this bit configures cam data enable invert. 0: not invert, 1: invert + */ + uint32_t cam_de_inv:1; + /** cam_hsync_inv : R/W; bitpos: [9]; default: 0; + * this bit configures cam hsync invert. 0: not invert, 1: invert + */ + uint32_t cam_hsync_inv:1; + /** cam_vsync_inv : R/W; bitpos: [10]; default: 0; + * this bit configures cam vsync invert. 0: not invert, 1: invert + */ + uint32_t cam_vsync_inv:1; + /** cam_vsync_filter_thres : R/W; bitpos: [13:11]; default: 0; + * this bit configures the number of clock of vsync filter length + */ + uint32_t cam_vsync_filter_thres:3; + /** cam_vsync_filter_en : R/W; bitpos: [14]; default: 0; + * this bit configures vsync filter en + */ + uint32_t cam_vsync_filter_en:1; + /** cam_de_only : R/W; bitpos: [15]; default: 0; + * configures whether cam inf only has de, no hsync data. 0: has hsync, 1: no hsync + */ + uint32_t cam_de_only:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} isp_cam_conf_reg_t; + +/** Type of af_ctrl0 register + * af control register 0 + */ +typedef union { + struct { + /** af_auto_update : R/W; bitpos: [0]; default: 0; + * this bit configures auto_update enable. when set to 1, will update sum and lum each + * frame + */ + uint32_t af_auto_update:1; + uint32_t reserved_1:3; + /** af_manual_update : WT; bitpos: [4]; default: 0; + * write 1 to this bit will update the sum and lum once + */ + uint32_t af_manual_update:1; + uint32_t reserved_5:3; + /** af_env_threshold : R/W; bitpos: [11:8]; default: 0; + * this field configures env threshold. when both sum and lum changes larger than this + * value, consider environment changes and need to trigger a new autofocus. 4Bit + * fractional + */ + uint32_t af_env_threshold:4; + uint32_t reserved_12:4; + /** af_env_period : R/W; bitpos: [23:16]; default: 0; + * this field configures environment changes detection period (frame). When set to 0, + * disable this function + */ + uint32_t af_env_period:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_af_ctrl0_reg_t; + +/** Type of af_ctrl1 register + * af control register 1 + */ +typedef union { + struct { + /** af_thpixnum : R/W; bitpos: [21:0]; default: 0; + * this field configures pixnum used when calculating the autofocus threshold. Set to + * 0 to disable threshold calculation + */ + uint32_t af_thpixnum:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_af_ctrl1_reg_t; + +/** Type of af_gen_th_ctrl register + * af gen threshold control register + */ +typedef union { + struct { + /** af_gen_threshold_min : R/W; bitpos: [15:0]; default: 128; + * this field configures min threshold when use auto_threshold + */ + uint32_t af_gen_threshold_min:16; + /** af_gen_threshold_max : R/W; bitpos: [31:16]; default: 1088; + * this field configures max threshold when use auto_threshold + */ + uint32_t af_gen_threshold_max:16; + }; + uint32_t val; +} isp_af_gen_th_ctrl_reg_t; + +/** Type of af_env_user_th_sum register + * af monitor user sum threshold register + */ +typedef union { + struct { + /** af_env_user_threshold_sum : R/W; bitpos: [31:0]; default: 0; + * this field configures user setup env detect sum threshold + */ + uint32_t af_env_user_threshold_sum:32; + }; + uint32_t val; +} isp_af_env_user_th_sum_reg_t; + +/** Type of af_env_user_th_lum register + * af monitor user lum threshold register + */ +typedef union { + struct { + /** af_env_user_threshold_lum : R/W; bitpos: [29:0]; default: 0; + * this field configures user setup env detect lum threshold + */ + uint32_t af_env_user_threshold_lum:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_env_user_th_lum_reg_t; + +/** Type of af_threshold register + * af threshold register + */ +typedef union { + struct { + /** af_threshold : R/W; bitpos: [15:0]; default: 256; + * this field configures user threshold. When set to non-zero, autofocus will use this + * threshold + */ + uint32_t af_threshold:16; + /** af_gen_threshold : RO; bitpos: [31:16]; default: 0; + * this field represents the last calculated threshold + */ + uint32_t af_gen_threshold:16; + }; + uint32_t val; +} isp_af_threshold_reg_t; + +/** Type of af_hscale_a register + * h-scale of af window a register + */ +typedef union { + struct { + /** af_rpoint_a : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window a, must >= 2 + */ + uint32_t af_rpoint_a:12; + uint32_t reserved_12:4; + /** af_lpoint_a : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window a, must >= 2 + */ + uint32_t af_lpoint_a:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_hscale_a_reg_t; + +/** Type of af_vscale_a register + * v-scale of af window a register + */ +typedef union { + struct { + /** af_bpoint_a : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window a, must <= hnum-2 + */ + uint32_t af_bpoint_a:12; + uint32_t reserved_12:4; + /** af_tpoint_a : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window a, must <= hnum-2 + */ + uint32_t af_tpoint_a:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_vscale_a_reg_t; + +/** Type of af_hscale_b register + * h-scale of af window b register + */ +typedef union { + struct { + /** af_rpoint_b : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window b, must >= 2 + */ + uint32_t af_rpoint_b:12; + uint32_t reserved_12:4; + /** af_lpoint_b : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window b, must >= 2 + */ + uint32_t af_lpoint_b:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_hscale_b_reg_t; + +/** Type of af_vscale_b register + * v-scale of af window b register + */ +typedef union { + struct { + /** af_bpoint_b : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window b, must <= hnum-2 + */ + uint32_t af_bpoint_b:12; + uint32_t reserved_12:4; + /** af_tpoint_b : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window b, must <= hnum-2 + */ + uint32_t af_tpoint_b:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_vscale_b_reg_t; + +/** Type of af_hscale_c register + * v-scale of af window c register + */ +typedef union { + struct { + /** af_rpoint_c : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window c, must >= 2 + */ + uint32_t af_rpoint_c:12; + uint32_t reserved_12:4; + /** af_lpoint_c : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window c, must >= 2 + */ + uint32_t af_lpoint_c:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_hscale_c_reg_t; + +/** Type of af_vscale_c register + * v-scale of af window c register + */ +typedef union { + struct { + /** af_bpoint_c : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window c, must <= hnum-2 + */ + uint32_t af_bpoint_c:12; + uint32_t reserved_12:4; + /** af_tpoint_c : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window c, must <= hnum-2 + */ + uint32_t af_tpoint_c:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_vscale_c_reg_t; + +/** Type of awb_mode register + * awb mode control register + */ +typedef union { + struct { + /** awb_mode : R/W; bitpos: [1:0]; default: 3; + * this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel + * algo1. 11: sel both algo0 and algo1 + */ + uint32_t awb_mode:2; + uint32_t reserved_2:2; + /** awb_sample : R/W; bitpos: [4]; default: 0; + * this bit configures awb sample location, 0:before ccm, 1:after ccm + */ + uint32_t awb_sample:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} isp_awb_mode_reg_t; + +/** Type of awb_hscale register + * h-scale of awb window + */ +typedef union { + struct { + /** awb_rpoint : R/W; bitpos: [11:0]; default: 1919; + * this field configures awb window right coordinate + */ + uint32_t awb_rpoint:12; + uint32_t reserved_12:4; + /** awb_lpoint : R/W; bitpos: [27:16]; default: 0; + * this field configures awb window left coordinate + */ + uint32_t awb_lpoint:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_awb_hscale_reg_t; + +/** Type of awb_vscale register + * v-scale of awb window + */ +typedef union { + struct { + /** awb_bpoint : R/W; bitpos: [11:0]; default: 1079; + * this field configures awb window bottom coordinate + */ + uint32_t awb_bpoint:12; + uint32_t reserved_12:4; + /** awb_tpoint : R/W; bitpos: [27:16]; default: 0; + * this field configures awb window top coordinate + */ + uint32_t awb_tpoint:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_awb_vscale_reg_t; + +/** Type of awb_th_lum register + * awb lum threshold register + */ +typedef union { + struct { + /** awb_min_lum : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of r+g+b + */ + uint32_t awb_min_lum:10; + uint32_t reserved_10:6; + /** awb_max_lum : R/W; bitpos: [25:16]; default: 765; + * this field configures upper threshold of r+g+b + */ + uint32_t awb_max_lum:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_awb_th_lum_reg_t; + +/** Type of awb_th_rg register + * awb r/g threshold register + */ +typedef union { + struct { + /** awb_min_rg : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of r/g, 2bit integer and 8bit fraction + */ + uint32_t awb_min_rg:10; + uint32_t reserved_10:6; + /** awb_max_rg : R/W; bitpos: [25:16]; default: 1023; + * this field configures upper threshold of r/g, 2bit integer and 8bit fraction + */ + uint32_t awb_max_rg:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_awb_th_rg_reg_t; + +/** Type of awb_th_bg register + * awb b/g threshold register + */ +typedef union { + struct { + /** awb_min_bg : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of b/g, 2bit integer and 8bit fraction + */ + uint32_t awb_min_bg:10; + uint32_t reserved_10:6; + /** awb_max_bg : R/W; bitpos: [25:16]; default: 1023; + * this field configures upper threshold of b/g, 2bit integer and 8bit fraction + */ + uint32_t awb_max_bg:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_awb_th_bg_reg_t; + +/** Type of color_ctrl register + * color control register + */ +typedef union { + struct { + /** color_saturation : R/W; bitpos: [7:0]; default: 128; + * this field configures the color saturation value + */ + uint32_t color_saturation:8; + /** color_hue : R/W; bitpos: [15:8]; default: 0; + * this field configures the color hue angle + */ + uint32_t color_hue:8; + /** color_contrast : R/W; bitpos: [23:16]; default: 128; + * this field configures the color contrast value + */ + uint32_t color_contrast:8; + /** color_brightness : R/W; bitpos: [31:24]; default: 0; + * this field configures the color brightness value, signed 2's complement + */ + uint32_t color_brightness:8; + }; + uint32_t val; +} isp_color_ctrl_reg_t; + +/** Type of blc_value register + * blc black level register + */ +typedef union { + struct { + /** blc_r3_value : R/W; bitpos: [7:0]; default: 0; + * this field configures the black level of bottom right channel of bayer img + */ + uint32_t blc_r3_value:8; + /** blc_r2_value : R/W; bitpos: [15:8]; default: 0; + * this field configures the black level of bottom left channel of bayer img + */ + uint32_t blc_r2_value:8; + /** blc_r1_value : R/W; bitpos: [23:16]; default: 0; + * this field configures the black level of top right channel of bayer img + */ + uint32_t blc_r1_value:8; + /** blc_r0_value : R/W; bitpos: [31:24]; default: 0; + * this field configures the black level of top left channel of bayer img + */ + uint32_t blc_r0_value:8; + }; + uint32_t val; +} isp_blc_value_reg_t; + +/** Type of blc_ctrl0 register + * blc stretch control register + */ +typedef union { + struct { + /** blc_r3_stretch : R/W; bitpos: [0]; default: 0; + * this bit configures the stretch feature of bottom right channel. 0: stretch + * disable, 1: stretch enable + */ + uint32_t blc_r3_stretch:1; + /** blc_r2_stretch : R/W; bitpos: [1]; default: 0; + * this bit configures the stretch feature of bottom left channel. 0: stretch disable, + * 1: stretch enable + */ + uint32_t blc_r2_stretch:1; + /** blc_r1_stretch : R/W; bitpos: [2]; default: 0; + * this bit configures the stretch feature of top right channel. 0: stretch disable, + * 1: stretch enable + */ + uint32_t blc_r1_stretch:1; + /** blc_r0_stretch : R/W; bitpos: [3]; default: 0; + * this bit configures the stretch feature of top left channel. 0: stretch disable, 1: + * stretch enable + */ + uint32_t blc_r0_stretch:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_blc_ctrl0_reg_t; + +/** Type of blc_ctrl1 register + * blc window control register + */ +typedef union { + struct { + /** blc_window_top : R/W; bitpos: [10:0]; default: 0; + * this field configures blc average calculation window top + */ + uint32_t blc_window_top:11; + /** blc_window_left : R/W; bitpos: [21:11]; default: 0; + * this field configures blc average calculation window left + */ + uint32_t blc_window_left:11; + /** blc_window_vnum : R/W; bitpos: [25:22]; default: 0; + * this field configures blc average calculation window vnum + */ + uint32_t blc_window_vnum:4; + /** blc_window_hnum : R/W; bitpos: [29:26]; default: 0; + * this field configures blc average calculation window hnum + */ + uint32_t blc_window_hnum:4; + /** blc_filter_en : R/W; bitpos: [30]; default: 0; + * this bit configures enable blc average input filter. 0: disable, 1: enable + */ + uint32_t blc_filter_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} isp_blc_ctrl1_reg_t; + +/** Type of blc_ctrl2 register + * blc black threshold control register + */ +typedef union { + struct { + /** blc_r3_th : R/W; bitpos: [7:0]; default: 0; + * this field configures black threshold when get blc average of bottom right channel + */ + uint32_t blc_r3_th:8; + /** blc_r2_th : R/W; bitpos: [15:8]; default: 0; + * this field configures black threshold when get blc average of bottom left channel + */ + uint32_t blc_r2_th:8; + /** blc_r1_th : R/W; bitpos: [23:16]; default: 0; + * this field configures black threshold when get blc average of top right channel + */ + uint32_t blc_r1_th:8; + /** blc_r0_th : R/W; bitpos: [31:24]; default: 0; + * this field configures black threshold when get blc average of top left channel + */ + uint32_t blc_r0_th:8; + }; + uint32_t val; +} isp_blc_ctrl2_reg_t; + +/** Type of hist_mode register + * histogram mode control register + */ +typedef union { + struct { + /** hist_mode : R/W; bitpos: [2:0]; default: 4; + * this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: + * RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V + */ + uint32_t hist_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} isp_hist_mode_reg_t; + +/** Type of hist_coeff register + * histogram rgb to gray coefficients register + */ +typedef union { + struct { + /** hist_coeff_b : R/W; bitpos: [7:0]; default: 85; + * this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ + uint32_t hist_coeff_b:8; + /** hist_coeff_g : R/W; bitpos: [15:8]; default: 85; + * this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ + uint32_t hist_coeff_g:8; + /** hist_coeff_r : R/W; bitpos: [23:16]; default: 85; + * this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ + uint32_t hist_coeff_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_hist_coeff_reg_t; + +/** Type of hist_offs register + * histogram window offsets register + */ +typedef union { + struct { + /** hist_y_offs : R/W; bitpos: [11:0]; default: 0; + * this field configures y coordinate of first window + */ + uint32_t hist_y_offs:12; + uint32_t reserved_12:4; + /** hist_x_offs : R/W; bitpos: [27:16]; default: 0; + * this field configures x coordinate of first window + */ + uint32_t hist_x_offs:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_hist_offs_reg_t; + +/** Type of hist_size register + * histogram sub-window size register + */ +typedef union { + struct { + /** hist_y_size : R/W; bitpos: [8:0]; default: 32; + * this field configures y direction size of subwindow + */ + uint32_t hist_y_size:9; + uint32_t reserved_9:7; + /** hist_x_size : R/W; bitpos: [24:16]; default: 18; + * this field configures x direction size of subwindow + */ + uint32_t hist_x_size:9; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_hist_size_reg_t; + +/** Type of hist_seg0 register + * histogram bin control register 0 + */ +typedef union { + struct { + /** hist_seg_3_4 : R/W; bitpos: [7:0]; default: 64; + * this field configures threshold of histogram bin 3 and bin 4 + */ + uint32_t hist_seg_3_4:8; + /** hist_seg_2_3 : R/W; bitpos: [15:8]; default: 48; + * this field configures threshold of histogram bin 2 and bin 3 + */ + uint32_t hist_seg_2_3:8; + /** hist_seg_1_2 : R/W; bitpos: [23:16]; default: 32; + * this field configures threshold of histogram bin 1 and bin 2 + */ + uint32_t hist_seg_1_2:8; + /** hist_seg_0_1 : R/W; bitpos: [31:24]; default: 16; + * this field configures threshold of histogram bin 0 and bin 1 + */ + uint32_t hist_seg_0_1:8; + }; + uint32_t val; +} isp_hist_seg0_reg_t; + +/** Type of hist_seg1 register + * histogram bin control register 1 + */ +typedef union { + struct { + /** hist_seg_7_8 : R/W; bitpos: [7:0]; default: 128; + * this field configures threshold of histogram bin 7 and bin 8 + */ + uint32_t hist_seg_7_8:8; + /** hist_seg_6_7 : R/W; bitpos: [15:8]; default: 112; + * this field configures threshold of histogram bin 6 and bin 7 + */ + uint32_t hist_seg_6_7:8; + /** hist_seg_5_6 : R/W; bitpos: [23:16]; default: 96; + * this field configures threshold of histogram bin 5 and bin 6 + */ + uint32_t hist_seg_5_6:8; + /** hist_seg_4_5 : R/W; bitpos: [31:24]; default: 80; + * this field configures threshold of histogram bin 4 and bin 5 + */ + uint32_t hist_seg_4_5:8; + }; + uint32_t val; +} isp_hist_seg1_reg_t; + +/** Type of hist_seg2 register + * histogram bin control register 2 + */ +typedef union { + struct { + /** hist_seg_11_12 : R/W; bitpos: [7:0]; default: 192; + * this field configures threshold of histogram bin 11 and bin 12 + */ + uint32_t hist_seg_11_12:8; + /** hist_seg_10_11 : R/W; bitpos: [15:8]; default: 176; + * this field configures threshold of histogram bin 10 and bin 11 + */ + uint32_t hist_seg_10_11:8; + /** hist_seg_9_10 : R/W; bitpos: [23:16]; default: 160; + * this field configures threshold of histogram bin 9 and bin 10 + */ + uint32_t hist_seg_9_10:8; + /** hist_seg_8_9 : R/W; bitpos: [31:24]; default: 144; + * this field configures threshold of histogram bin 8 and bin 9 + */ + uint32_t hist_seg_8_9:8; + }; + uint32_t val; +} isp_hist_seg2_reg_t; + +/** Type of hist_seg3 register + * histogram bin control register 3 + */ +typedef union { + struct { + /** hist_seg_14_15 : R/W; bitpos: [7:0]; default: 240; + * this field configures threshold of histogram bin 14 and bin 15 + */ + uint32_t hist_seg_14_15:8; + /** hist_seg_13_14 : R/W; bitpos: [15:8]; default: 224; + * this field configures threshold of histogram bin 13 and bin 14 + */ + uint32_t hist_seg_13_14:8; + /** hist_seg_12_13 : R/W; bitpos: [23:16]; default: 208; + * this field configures threshold of histogram bin 12 and bin 13 + */ + uint32_t hist_seg_12_13:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_hist_seg3_reg_t; + +/** Type of hist_weight0 register + * histogram sub-window weight register 0 + */ +typedef union { + struct { + /** hist_weight_03 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 03 + */ + uint32_t hist_weight_03:8; + /** hist_weight_02 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 02 + */ + uint32_t hist_weight_02:8; + /** hist_weight_01 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 01 + */ + uint32_t hist_weight_01:8; + /** hist_weight_00 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 00 and sum of all weight should be 256 + */ + uint32_t hist_weight_00:8; + }; + uint32_t val; +} isp_hist_weight0_reg_t; + +/** Type of hist_weight1 register + * histogram sub-window weight register 1 + */ +typedef union { + struct { + /** hist_weight_12 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 12 + */ + uint32_t hist_weight_12:8; + /** hist_weight_11 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 11 + */ + uint32_t hist_weight_11:8; + /** hist_weight_10 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 10 + */ + uint32_t hist_weight_10:8; + /** hist_weight_04 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 04 + */ + uint32_t hist_weight_04:8; + }; + uint32_t val; +} isp_hist_weight1_reg_t; + +/** Type of hist_weight2 register + * histogram sub-window weight register 2 + */ +typedef union { + struct { + /** hist_weight_21 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 21 + */ + uint32_t hist_weight_21:8; + /** hist_weight_20 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 20 + */ + uint32_t hist_weight_20:8; + /** hist_weight_14 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 04 + */ + uint32_t hist_weight_14:8; + /** hist_weight_13 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 13 + */ + uint32_t hist_weight_13:8; + }; + uint32_t val; +} isp_hist_weight2_reg_t; + +/** Type of hist_weight3 register + * histogram sub-window weight register 3 + */ +typedef union { + struct { + /** hist_weight_30 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 30 + */ + uint32_t hist_weight_30:8; + /** hist_weight_24 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 24 + */ + uint32_t hist_weight_24:8; + /** hist_weight_23 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 23 + */ + uint32_t hist_weight_23:8; + /** hist_weight_22 : R/W; bitpos: [31:24]; default: 232; + * this field configures weight of subwindow 22 + */ + uint32_t hist_weight_22:8; + }; + uint32_t val; +} isp_hist_weight3_reg_t; + +/** Type of hist_weight4 register + * histogram sub-window weight register 4 + */ +typedef union { + struct { + /** hist_weight_34 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 34 + */ + uint32_t hist_weight_34:8; + /** hist_weight_33 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 33 + */ + uint32_t hist_weight_33:8; + /** hist_weight_32 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 32 + */ + uint32_t hist_weight_32:8; + /** hist_weight_31 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 31 + */ + uint32_t hist_weight_31:8; + }; + uint32_t val; +} isp_hist_weight4_reg_t; + +/** Type of hist_weight5 register + * histogram sub-window weight register 5 + */ +typedef union { + struct { + /** hist_weight_43 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 43 + */ + uint32_t hist_weight_43:8; + /** hist_weight_42 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 42 + */ + uint32_t hist_weight_42:8; + /** hist_weight_41 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 41 + */ + uint32_t hist_weight_41:8; + /** hist_weight_40 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 40 + */ + uint32_t hist_weight_40:8; + }; + uint32_t val; +} isp_hist_weight5_reg_t; + +/** Type of hist_weight6 register + * histogram sub-window weight register 6 + */ +typedef union { + struct { + /** hist_weight_44 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 44 + */ + uint32_t hist_weight_44:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} isp_hist_weight6_reg_t; + +/** Type of mem_aux_ctrl_0 register + * mem aux control register 0 + */ +typedef union { + struct { + /** header_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of isp input buffer memory + */ + uint32_t header_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** dpc_lut_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field represents this field configures the mem_aux of dpc lut memory + */ + uint32_t dpc_lut_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_0_reg_t; + +/** Type of mem_aux_ctrl_1 register + * mem aux control register 1 + */ +typedef union { + struct { + /** lsc_lut_r_gr_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of lsc r gr lut memory + */ + uint32_t lsc_lut_r_gr_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** lsc_lut_gb_b_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of lsc gb b lut memory + */ + uint32_t lsc_lut_gb_b_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_1_reg_t; + +/** Type of mem_aux_ctrl_2 register + * mem aux control register 2 + */ +typedef union { + struct { + /** bf_matrix_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of bf line buffer memory + */ + uint32_t bf_matrix_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** dpc_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of dpc line buffer memory + */ + uint32_t dpc_matrix_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_2_reg_t; + +/** Type of mem_aux_ctrl_3 register + * mem aux control register 3 + */ +typedef union { + struct { + /** sharp_matrix_y_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of sharp y line buffer memory + */ + uint32_t sharp_matrix_y_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** demosaic_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of demosaic line buffer memory + */ + uint32_t demosaic_matrix_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_3_reg_t; + +/** Type of mem_aux_ctrl_4 register + * mem aux control register 4 + */ +typedef union { + struct { + /** sharp_matrix_uv_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of sharp uv line buffer memory + */ + uint32_t sharp_matrix_uv_mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} isp_mem_aux_ctrl_4_reg_t; + +/** Type of yuv_format register + * yuv format control register + */ +typedef union { + struct { + /** yuv_mode : R/W; bitpos: [0]; default: 0; + * this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 + */ + uint32_t yuv_mode:1; + /** yuv_range : R/W; bitpos: [1]; default: 0; + * this bit configures the yuv range. 0: full range, 1: limit range + */ + uint32_t yuv_range:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_yuv_format_reg_t; + +/** Type of rdn_eco_low register + * rdn eco all low register + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * rdn_eco_low + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} isp_rdn_eco_low_reg_t; + +/** Type of rdn_eco_high register + * rdn eco all high register + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * rdn_eco_high + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} isp_rdn_eco_high_reg_t; + +/** Type of crop_ctrl register + * isp_crop ctrl register + */ +typedef union { + struct { + /** crop_sft_rst : WT; bitpos: [0]; default: 0; + * Write 1 to clear err st + */ + uint32_t crop_sft_rst:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} isp_crop_ctrl_reg_t; + +/** Type of crop_y_capture register + * isp_crop row capture range register + */ +typedef union { + struct { + /** crop_y_start : R/W; bitpos: [11:0]; default: 0; + * isp_crop capture row start index + */ + uint32_t crop_y_start:12; + /** crop_y_end : R/W; bitpos: [23:12]; default: 0; + * isp_crop capture row end index + */ + uint32_t crop_y_end:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_crop_y_capture_reg_t; + +/** Type of crop_x_capture register + * isp_crop col capture range register + */ +typedef union { + struct { + /** crop_x_start : R/W; bitpos: [11:0]; default: 0; + * isp_crop capture col start index + */ + uint32_t crop_x_start:12; + /** crop_x_end : R/W; bitpos: [23:12]; default: 0; + * isp_crop capture col end index + */ + uint32_t crop_x_end:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_crop_x_capture_reg_t; + +/** Type of crop_err_st register + * crop error state register + */ +typedef union { + struct { + /** crop_y_mismatch : RO; bitpos: [0]; default: 0; + * Represents isp_corp row end index over image size + */ + uint32_t crop_y_mismatch:1; + /** crop_x_mismatch : RO; bitpos: [1]; default: 0; + * Represents isp_corp col end index over image size + */ + uint32_t crop_x_mismatch:1; + /** crop_y_end_even : RO; bitpos: [2]; default: 0; + * Represents isp_corp row end index is an even number + */ + uint32_t crop_y_end_even:1; + /** crop_x_end_even : RO; bitpos: [3]; default: 0; + * Represents isp_corp col end index is an even number + */ + uint32_t crop_x_end_even:1; + /** crop_y_start_odd : RO; bitpos: [4]; default: 0; + * Represents isp_corp row start index is an odd number + */ + uint32_t crop_y_start_odd:1; + /** crop_x_start_odd : RO; bitpos: [5]; default: 0; + * Represents isp_corp col start index is an odd number + */ + uint32_t crop_x_start_odd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_crop_err_st_reg_t; + +/** Type of wbg_coef_r register + * white balance red gain register 0 + */ +typedef union { + struct { + /** wbg_r : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance red gain + */ + uint32_t wbg_r:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} isp_wbg_coef_r_reg_t; + +/** Type of wbg_coef_g register + * white balance green gain register 0 + */ +typedef union { + struct { + /** wbg_g : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance green gain + */ + uint32_t wbg_g:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} isp_wbg_coef_g_reg_t; + +/** Type of wbg_coef_b register + * white balance blue gain register 0 + */ +typedef union { + struct { + /** wbg_b : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance blue gain + */ + uint32_t wbg_b:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} isp_wbg_coef_b_reg_t; + +/** Type of color_hue_ctrl register + * color control register + */ +typedef union { + struct { + /** color_hue_h : R/W; bitpos: [0]; default: 0; + * Configures the color hue angle most bit + */ + uint32_t color_hue_h:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} isp_color_hue_ctrl_reg_t; + +/** Type of awb_bx register + * awb window register in x-direction + */ +typedef union { + struct { + /** awb_x_bsize : R/W; bitpos: [11:0]; default: 0; + * Configures every block x size, min number is 4 + */ + uint32_t awb_x_bsize:12; + /** awb_x_start : R/W; bitpos: [23:12]; default: 0; + * Configures first block start x address + */ + uint32_t awb_x_start:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_awb_bx_reg_t; + +/** Type of awb_by register + * awb window register in y-direction + */ +typedef union { + struct { + /** awb_y_bsize : R/W; bitpos: [11:0]; default: 0; + * Configures every block y size + */ + uint32_t awb_y_bsize:12; + /** awb_y_start : R/W; bitpos: [23:12]; default: 0; + * Configures first block start y address + */ + uint32_t awb_y_start:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_awb_by_reg_t; + +/** Type of state register + * awb window register in y-direction + */ +typedef union { + struct { + /** tail_busy : RO; bitpos: [0]; default: 0; + * Represents isp_tail state + */ + uint32_t tail_busy:1; + /** header_busy : RO; bitpos: [1]; default: 0; + * Represents isp_header state + */ + uint32_t header_busy:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_state_reg_t; + +/** Type of shadow_reg_ctrl register + * shadow register ctrl register + */ +typedef union { + struct { + /** blc_update : R/W; bitpos: [0]; default: 0; + * Write 1 to update blc configuration register + */ + uint32_t blc_update:1; + /** dpc_update : R/W; bitpos: [1]; default: 0; + * Write 1 to update dpc configuration register + */ + uint32_t dpc_update:1; + /** bf_update : R/W; bitpos: [2]; default: 0; + * Write 1 to update bf configuration register + */ + uint32_t bf_update:1; + /** wbg_update : R/W; bitpos: [3]; default: 0; + * Write 1 to update wbg configuration register + */ + uint32_t wbg_update:1; + /** ccm_update : R/W; bitpos: [4]; default: 0; + * Write 1 to update ccm configuration register + */ + uint32_t ccm_update:1; + uint32_t reserved_5:1; + /** sharp_update : R/W; bitpos: [6]; default: 0; + * Write 1 to update sharp configuration register + */ + uint32_t sharp_update:1; + /** color_update : R/W; bitpos: [7]; default: 0; + * Write 1 to update color configuration register + */ + uint32_t color_update:1; + uint32_t reserved_8:22; + /** shadow_update_sel : R/W; bitpos: [31:30]; default: 1; + * Configures shadow register update type. 0: no shadow register. 1: update every + * vsyn. 2: update only the next vsync after write reg_xxx_update + */ + uint32_t shadow_update_sel:2; + }; + uint32_t val; +} isp_shadow_reg_ctrl_reg_t; + + +/** Group: Status Registers */ +/** Type of dpc_deadpix_cnt register + * DPC dead-pix number register + */ +typedef union { + struct { + /** dpc_deadpix_cnt : RO; bitpos: [9:0]; default: 0; + * this field represents the dead pixel count + */ + uint32_t dpc_deadpix_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} isp_dpc_deadpix_cnt_reg_t; + +/** Type of lut_rdata register + * LUT read data register + */ +typedef union { + struct { + /** lut_rdata : RO; bitpos: [31:0]; default: 0; + * this field represents the read data of lut. read ISP_LUT_RDATA after write + * ISP_LUT_CMD register + */ + uint32_t lut_rdata:32; + }; + uint32_t val; +} isp_lut_rdata_reg_t; + +/** Type of ae_block_mean_0 register + * ae statistic result register 0 + */ +typedef union { + struct { + /** ae_b03_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block03 Y mean data + */ + uint32_t ae_b03_mean:8; + /** ae_b02_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block02 Y mean data + */ + uint32_t ae_b02_mean:8; + /** ae_b01_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block01 Y mean data + */ + uint32_t ae_b01_mean:8; + /** ae_b00_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block00 Y mean data + */ + uint32_t ae_b00_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_0_reg_t; + +/** Type of ae_block_mean_1 register + * ae statistic result register 1 + */ +typedef union { + struct { + /** ae_b12_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block12 Y mean data + */ + uint32_t ae_b12_mean:8; + /** ae_b11_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block11 Y mean data + */ + uint32_t ae_b11_mean:8; + /** ae_b10_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block10 Y mean data + */ + uint32_t ae_b10_mean:8; + /** ae_b04_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block04 Y mean data + */ + uint32_t ae_b04_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_1_reg_t; + +/** Type of ae_block_mean_2 register + * ae statistic result register 2 + */ +typedef union { + struct { + /** ae_b21_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block21 Y mean data + */ + uint32_t ae_b21_mean:8; + /** ae_b20_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block20 Y mean data + */ + uint32_t ae_b20_mean:8; + /** ae_b14_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block14 Y mean data + */ + uint32_t ae_b14_mean:8; + /** ae_b13_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block13 Y mean data + */ + uint32_t ae_b13_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_2_reg_t; + +/** Type of ae_block_mean_3 register + * ae statistic result register 3 + */ +typedef union { + struct { + /** ae_b30_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block30 Y mean data + */ + uint32_t ae_b30_mean:8; + /** ae_b24_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block24 Y mean data + */ + uint32_t ae_b24_mean:8; + /** ae_b23_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block23 Y mean data + */ + uint32_t ae_b23_mean:8; + /** ae_b22_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block22 Y mean data + */ + uint32_t ae_b22_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_3_reg_t; + +/** Type of ae_block_mean_4 register + * ae statistic result register 4 + */ +typedef union { + struct { + /** ae_b34_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block34 Y mean data + */ + uint32_t ae_b34_mean:8; + /** ae_b33_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block33 Y mean data + */ + uint32_t ae_b33_mean:8; + /** ae_b32_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block32 Y mean data + */ + uint32_t ae_b32_mean:8; + /** ae_b31_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block31 Y mean data + */ + uint32_t ae_b31_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_4_reg_t; + +/** Type of ae_block_mean_5 register + * ae statistic result register 5 + */ +typedef union { + struct { + /** ae_b43_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block43 Y mean data + */ + uint32_t ae_b43_mean:8; + /** ae_b42_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block42 Y mean data + */ + uint32_t ae_b42_mean:8; + /** ae_b41_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block41 Y mean data + */ + uint32_t ae_b41_mean:8; + /** ae_b40_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block40 Y mean data + */ + uint32_t ae_b40_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_5_reg_t; + +/** Type of ae_block_mean_6 register + * ae statistic result register 6 + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** ae_b44_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block44 Y mean data + */ + uint32_t ae_b44_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_6_reg_t; + +/** Type of af_sum_a register + * result of sum of af window a + */ +typedef union { + struct { + /** af_suma : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window a + */ + uint32_t af_suma:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_sum_a_reg_t; + +/** Type of af_sum_b register + * result of sum of af window b + */ +typedef union { + struct { + /** af_sumb : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window b + */ + uint32_t af_sumb:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_sum_b_reg_t; + +/** Type of af_sum_c register + * result of sum of af window c + */ +typedef union { + struct { + /** af_sumc : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window c + */ + uint32_t af_sumc:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_sum_c_reg_t; + +/** Type of af_lum_a register + * result of lum of af window a + */ +typedef union { + struct { + /** af_luma : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window a + */ + uint32_t af_luma:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_lum_a_reg_t; + +/** Type of af_lum_b register + * result of lum of af window b + */ +typedef union { + struct { + /** af_lumb : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window b + */ + uint32_t af_lumb:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_lum_b_reg_t; + +/** Type of af_lum_c register + * result of lum of af window c + */ +typedef union { + struct { + /** af_lumc : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window c + */ + uint32_t af_lumc:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_lum_c_reg_t; + +/** Type of awb0_white_cnt register + * result of awb white point number + */ +typedef union { + struct { + /** awb0_white_cnt : RO; bitpos: [23:0]; default: 0; + * this field configures number of white point detected of algo0 + */ + uint32_t awb0_white_cnt:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_awb0_white_cnt_reg_t; + +/** Type of awb0_acc_r register + * result of accumulate of r channel of all white points + */ +typedef union { + struct { + /** awb0_acc_r : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel r of all white point of algo0 + */ + uint32_t awb0_acc_r:32; + }; + uint32_t val; +} isp_awb0_acc_r_reg_t; + +/** Type of awb0_acc_g register + * result of accumulate of g channel of all white points + */ +typedef union { + struct { + /** awb0_acc_g : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel g of all white point of algo0 + */ + uint32_t awb0_acc_g:32; + }; + uint32_t val; +} isp_awb0_acc_g_reg_t; + +/** Type of awb0_acc_b register + * result of accumulate of b channel of all white points + */ +typedef union { + struct { + /** awb0_acc_b : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel b of all white point of algo0 + */ + uint32_t awb0_acc_b:32; + }; + uint32_t val; +} isp_awb0_acc_b_reg_t; + +/** Type of blc_mean register + * results of the average of black window + */ +typedef union { + struct { + /** blc_r3_mean : RO; bitpos: [7:0]; default: 0; + * this field represents the average black value of bottom right channel + */ + uint32_t blc_r3_mean:8; + /** blc_r2_mean : RO; bitpos: [15:8]; default: 0; + * this field represents the average black value of bottom left channel + */ + uint32_t blc_r2_mean:8; + /** blc_r1_mean : RO; bitpos: [23:16]; default: 0; + * this field represents the average black value of top right channel + */ + uint32_t blc_r1_mean:8; + /** blc_r0_mean : RO; bitpos: [31:24]; default: 0; + * this field represents the average black value of top left channel + */ + uint32_t blc_r0_mean:8; + }; + uint32_t val; +} isp_blc_mean_reg_t; + +/** Type of hist_bin0 register + * result of histogram bin 0 + */ +typedef union { + struct { + /** hist_bin_0 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 0 + */ + uint32_t hist_bin_0:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin0_reg_t; + +/** Type of hist_bin1 register + * result of histogram bin 1 + */ +typedef union { + struct { + /** hist_bin_1 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 1 + */ + uint32_t hist_bin_1:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin1_reg_t; + +/** Type of hist_bin2 register + * result of histogram bin 2 + */ +typedef union { + struct { + /** hist_bin_2 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 2 + */ + uint32_t hist_bin_2:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin2_reg_t; + +/** Type of hist_bin3 register + * result of histogram bin 3 + */ +typedef union { + struct { + /** hist_bin_3 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 3 + */ + uint32_t hist_bin_3:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin3_reg_t; + +/** Type of hist_bin4 register + * result of histogram bin 4 + */ +typedef union { + struct { + /** hist_bin_4 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 4 + */ + uint32_t hist_bin_4:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin4_reg_t; + +/** Type of hist_bin5 register + * result of histogram bin 5 + */ +typedef union { + struct { + /** hist_bin_5 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 5 + */ + uint32_t hist_bin_5:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin5_reg_t; + +/** Type of hist_bin6 register + * result of histogram bin 6 + */ +typedef union { + struct { + /** hist_bin_6 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 6 + */ + uint32_t hist_bin_6:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin6_reg_t; + +/** Type of hist_bin7 register + * result of histogram bin 7 + */ +typedef union { + struct { + /** hist_bin_7 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 7 + */ + uint32_t hist_bin_7:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin7_reg_t; + +/** Type of hist_bin8 register + * result of histogram bin 8 + */ +typedef union { + struct { + /** hist_bin_8 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 8 + */ + uint32_t hist_bin_8:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin8_reg_t; + +/** Type of hist_bin9 register + * result of histogram bin 9 + */ +typedef union { + struct { + /** hist_bin_9 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 9 + */ + uint32_t hist_bin_9:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin9_reg_t; + +/** Type of hist_bin10 register + * result of histogram bin 10 + */ +typedef union { + struct { + /** hist_bin_10 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 10 + */ + uint32_t hist_bin_10:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin10_reg_t; + +/** Type of hist_bin11 register + * result of histogram bin 11 + */ +typedef union { + struct { + /** hist_bin_11 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 11 + */ + uint32_t hist_bin_11:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin11_reg_t; + +/** Type of hist_bin12 register + * result of histogram bin 12 + */ +typedef union { + struct { + /** hist_bin_12 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 12 + */ + uint32_t hist_bin_12:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin12_reg_t; + +/** Type of hist_bin13 register + * result of histogram bin 13 + */ +typedef union { + struct { + /** hist_bin_13 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 13 + */ + uint32_t hist_bin_13:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin13_reg_t; + +/** Type of hist_bin14 register + * result of histogram bin 14 + */ +typedef union { + struct { + /** hist_bin_14 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 14 + */ + uint32_t hist_bin_14:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin14_reg_t; + +/** Type of hist_bin15 register + * result of histogram bin 15 + */ +typedef union { + struct { + /** hist_bin_15 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 15 + */ + uint32_t hist_bin_15:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_bin15_reg_t; + +/** Type of rdn_eco_cs register + * rdn eco cs register + */ +typedef union { + struct { + /** rdn_eco_en : R/W; bitpos: [0]; default: 0; + * rdn_eco_en + */ + uint32_t rdn_eco_en:1; + /** rdn_eco_result : RO; bitpos: [1]; default: 0; + * rdn_eco_result + */ + uint32_t rdn_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_rdn_eco_cs_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * raw interrupt register + */ +typedef union { + struct { + /** isp_data_type_err_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * the raw interrupt status of input data type error. isp only support RGB bayer data + * type, other type will report type_err_int + */ + uint32_t isp_data_type_err_int_raw:1; + /** isp_async_fifo_ovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * the raw interrupt status of isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_raw:1; + /** isp_buf_full_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * the raw interrupt status of isp input buffer full + */ + uint32_t isp_buf_full_int_raw:1; + /** isp_hvnum_setting_err_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * the raw interrupt status of hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_raw:1; + /** isp_data_type_setting_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * the raw interrupt status of setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_raw:1; + /** isp_mipi_hnum_unmatch_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * the raw interrupt status of hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_raw:1; + /** dpc_check_done_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * the raw interrupt status of dpc check done + */ + uint32_t dpc_check_done_int_raw:1; + /** gamma_xcoord_err_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * the raw interrupt status of gamma setting error. it report the sum of the lengths + * represented by reg_gamma_x00~x0F isn't equal to 256 + */ + uint32_t gamma_xcoord_err_int_raw:1; + /** ae_monitor_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * the raw interrupt status of ae monitor + */ + uint32_t ae_monitor_int_raw:1; + /** ae_frame_done_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * the raw interrupt status of ae. + */ + uint32_t ae_frame_done_int_raw:1; + /** af_fdone_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * the raw interrupt status of af statistic. when auto_update enable, each frame done + * will send one int pulse when manual_update, each time when write 1 to + * reg_manual_update will send a int pulse when next frame done + */ + uint32_t af_fdone_int_raw:1; + /** af_env_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * the raw interrupt status of af monitor. send a int pulse when env_det function + * enabled and environment changes detected + */ + uint32_t af_env_int_raw:1; + /** awb_fdone_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * the raw interrupt status of awb. send a int pulse when statistic of one awb frame + * done + */ + uint32_t awb_fdone_int_raw:1; + /** hist_fdone_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * the raw interrupt status of histogram. send a int pulse when statistic of one frame + * histogram done + */ + uint32_t hist_fdone_int_raw:1; + /** frame_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * the raw interrupt status of isp frame end + */ + uint32_t frame_int_raw:1; + /** blc_frame_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * the raw interrupt status of blc frame done + */ + uint32_t blc_frame_int_raw:1; + /** lsc_frame_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * the raw interrupt status of lsc frame done + */ + uint32_t lsc_frame_int_raw:1; + /** dpc_frame_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * the raw interrupt status of dpc frame done + */ + uint32_t dpc_frame_int_raw:1; + /** bf_frame_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * the raw interrupt status of bf frame done + */ + uint32_t bf_frame_int_raw:1; + /** demosaic_frame_int_raw : R/SS/WTC; bitpos: [19]; default: 0; + * the raw interrupt status of demosaic frame done + */ + uint32_t demosaic_frame_int_raw:1; + /** median_frame_int_raw : R/SS/WTC; bitpos: [20]; default: 0; + * the raw interrupt status of median frame done + */ + uint32_t median_frame_int_raw:1; + /** ccm_frame_int_raw : R/SS/WTC; bitpos: [21]; default: 0; + * the raw interrupt status of ccm frame done + */ + uint32_t ccm_frame_int_raw:1; + /** gamma_frame_int_raw : R/SS/WTC; bitpos: [22]; default: 0; + * the raw interrupt status of gamma frame done + */ + uint32_t gamma_frame_int_raw:1; + /** rgb2yuv_frame_int_raw : R/SS/WTC; bitpos: [23]; default: 0; + * the raw interrupt status of rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_raw:1; + /** sharp_frame_int_raw : R/SS/WTC; bitpos: [24]; default: 0; + * the raw interrupt status of sharp frame done + */ + uint32_t sharp_frame_int_raw:1; + /** color_frame_int_raw : R/SS/WTC; bitpos: [25]; default: 0; + * the raw interrupt status of color frame done + */ + uint32_t color_frame_int_raw:1; + /** yuv2rgb_frame_int_raw : R/SS/WTC; bitpos: [26]; default: 0; + * the raw interrupt status of yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_raw:1; + /** tail_idi_frame_int_raw : R/SS/WTC; bitpos: [27]; default: 0; + * the raw interrupt status of isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_raw:1; + /** header_idi_frame_int_raw : R/SS/WTC; bitpos: [28]; default: 0; + * the raw interrupt status of real input frame end of isp_input + */ + uint32_t header_idi_frame_int_raw:1; + /** crop_frame_int_raw : R/SS/WTC; bitpos: [29]; default: 0; + * the raw interrupt status of crop frame done + */ + uint32_t crop_frame_int_raw:1; + /** wbg_frame_int_raw : R/SS/WTC; bitpos: [30]; default: 0; + * the raw interrupt status of wbg frame done + */ + uint32_t wbg_frame_int_raw:1; + /** crop_err_int_raw : R/SS/WTC; bitpos: [31]; default: 0; + * the raw interrupt status of crop error + */ + uint32_t crop_err_int_raw:1; + }; + uint32_t val; +} isp_int_raw_reg_t; + +/** Type of int_st register + * masked interrupt register + */ +typedef union { + struct { + /** isp_data_type_err_int_st : RO; bitpos: [0]; default: 0; + * the masked interrupt status of input data type error + */ + uint32_t isp_data_type_err_int_st:1; + /** isp_async_fifo_ovf_int_st : RO; bitpos: [1]; default: 0; + * the masked interrupt status of isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_st:1; + /** isp_buf_full_int_st : RO; bitpos: [2]; default: 0; + * the masked interrupt status of isp input buffer full + */ + uint32_t isp_buf_full_int_st:1; + /** isp_hvnum_setting_err_int_st : RO; bitpos: [3]; default: 0; + * the masked interrupt status of hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_st:1; + /** isp_data_type_setting_err_int_st : RO; bitpos: [4]; default: 0; + * the masked interrupt status of setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_st:1; + /** isp_mipi_hnum_unmatch_int_st : RO; bitpos: [5]; default: 0; + * the masked interrupt status of hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_st:1; + /** dpc_check_done_int_st : RO; bitpos: [6]; default: 0; + * the masked interrupt status of dpc check done + */ + uint32_t dpc_check_done_int_st:1; + /** gamma_xcoord_err_int_st : RO; bitpos: [7]; default: 0; + * the masked interrupt status of gamma setting error + */ + uint32_t gamma_xcoord_err_int_st:1; + /** ae_monitor_int_st : RO; bitpos: [8]; default: 0; + * the masked interrupt status of ae monitor + */ + uint32_t ae_monitor_int_st:1; + /** ae_frame_done_int_st : RO; bitpos: [9]; default: 0; + * the masked interrupt status of ae + */ + uint32_t ae_frame_done_int_st:1; + /** af_fdone_int_st : RO; bitpos: [10]; default: 0; + * the masked interrupt status of af statistic + */ + uint32_t af_fdone_int_st:1; + /** af_env_int_st : RO; bitpos: [11]; default: 0; + * the masked interrupt status of af monitor + */ + uint32_t af_env_int_st:1; + /** awb_fdone_int_st : RO; bitpos: [12]; default: 0; + * the masked interrupt status of awb + */ + uint32_t awb_fdone_int_st:1; + /** hist_fdone_int_st : RO; bitpos: [13]; default: 0; + * the masked interrupt status of histogram + */ + uint32_t hist_fdone_int_st:1; + /** frame_int_st : RO; bitpos: [14]; default: 0; + * the masked interrupt status of isp frame end + */ + uint32_t frame_int_st:1; + /** blc_frame_int_st : RO; bitpos: [15]; default: 0; + * the masked interrupt status of blc frame done + */ + uint32_t blc_frame_int_st:1; + /** lsc_frame_int_st : RO; bitpos: [16]; default: 0; + * the masked interrupt status of lsc frame done + */ + uint32_t lsc_frame_int_st:1; + /** dpc_frame_int_st : RO; bitpos: [17]; default: 0; + * the masked interrupt status of dpc frame done + */ + uint32_t dpc_frame_int_st:1; + /** bf_frame_int_st : RO; bitpos: [18]; default: 0; + * the masked interrupt status of bf frame done + */ + uint32_t bf_frame_int_st:1; + /** demosaic_frame_int_st : RO; bitpos: [19]; default: 0; + * the masked interrupt status of demosaic frame done + */ + uint32_t demosaic_frame_int_st:1; + /** median_frame_int_st : RO; bitpos: [20]; default: 0; + * the masked interrupt status of median frame done + */ + uint32_t median_frame_int_st:1; + /** ccm_frame_int_st : RO; bitpos: [21]; default: 0; + * the masked interrupt status of ccm frame done + */ + uint32_t ccm_frame_int_st:1; + /** gamma_frame_int_st : RO; bitpos: [22]; default: 0; + * the masked interrupt status of gamma frame done + */ + uint32_t gamma_frame_int_st:1; + /** rgb2yuv_frame_int_st : RO; bitpos: [23]; default: 0; + * the masked interrupt status of rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_st:1; + /** sharp_frame_int_st : RO; bitpos: [24]; default: 0; + * the masked interrupt status of sharp frame done + */ + uint32_t sharp_frame_int_st:1; + /** color_frame_int_st : RO; bitpos: [25]; default: 0; + * the masked interrupt status of color frame done + */ + uint32_t color_frame_int_st:1; + /** yuv2rgb_frame_int_st : RO; bitpos: [26]; default: 0; + * the masked interrupt status of yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_st:1; + /** tail_idi_frame_int_st : RO; bitpos: [27]; default: 0; + * the masked interrupt status of isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_st:1; + /** header_idi_frame_int_st : RO; bitpos: [28]; default: 0; + * the masked interrupt status of real input frame end of isp_input + */ + uint32_t header_idi_frame_int_st:1; + /** crop_frame_int_st : RO; bitpos: [29]; default: 0; + * the masked interrupt status of crop frame done + */ + uint32_t crop_frame_int_st:1; + /** wbg_frame_int_st : RO; bitpos: [30]; default: 0; + * the masked interrupt status of wbg frame done + */ + uint32_t wbg_frame_int_st:1; + /** crop_err_int_st : RO; bitpos: [31]; default: 0; + * the masked interrupt status of crop error + */ + uint32_t crop_err_int_st:1; + }; + uint32_t val; +} isp_int_st_reg_t; + +/** Type of int_ena register + * interrupt enable register + */ +typedef union { + struct { + /** isp_data_type_err_int_ena : R/W; bitpos: [0]; default: 1; + * write 1 to enable input data type error + */ + uint32_t isp_data_type_err_int_ena:1; + /** isp_async_fifo_ovf_int_ena : R/W; bitpos: [1]; default: 1; + * write 1 to enable isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_ena:1; + /** isp_buf_full_int_ena : R/W; bitpos: [2]; default: 0; + * write 1 to enable isp input buffer full + */ + uint32_t isp_buf_full_int_ena:1; + /** isp_hvnum_setting_err_int_ena : R/W; bitpos: [3]; default: 0; + * write 1 to enable hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_ena:1; + /** isp_data_type_setting_err_int_ena : R/W; bitpos: [4]; default: 0; + * write 1 to enable setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_ena:1; + /** isp_mipi_hnum_unmatch_int_ena : R/W; bitpos: [5]; default: 0; + * write 1 to enable hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_ena:1; + /** dpc_check_done_int_ena : R/W; bitpos: [6]; default: 1; + * write 1 to enable dpc check done + */ + uint32_t dpc_check_done_int_ena:1; + /** gamma_xcoord_err_int_ena : R/W; bitpos: [7]; default: 1; + * write 1 to enable gamma setting error + */ + uint32_t gamma_xcoord_err_int_ena:1; + /** ae_monitor_int_ena : R/W; bitpos: [8]; default: 0; + * write 1 to enable ae monitor + */ + uint32_t ae_monitor_int_ena:1; + /** ae_frame_done_int_ena : R/W; bitpos: [9]; default: 0; + * write 1 to enable ae + */ + uint32_t ae_frame_done_int_ena:1; + /** af_fdone_int_ena : R/W; bitpos: [10]; default: 0; + * write 1 to enable af statistic + */ + uint32_t af_fdone_int_ena:1; + /** af_env_int_ena : R/W; bitpos: [11]; default: 0; + * write 1 to enable af monitor + */ + uint32_t af_env_int_ena:1; + /** awb_fdone_int_ena : R/W; bitpos: [12]; default: 0; + * write 1 to enable awb + */ + uint32_t awb_fdone_int_ena:1; + /** hist_fdone_int_ena : R/W; bitpos: [13]; default: 0; + * write 1 to enable histogram + */ + uint32_t hist_fdone_int_ena:1; + /** frame_int_ena : R/W; bitpos: [14]; default: 0; + * write 1 to enable isp frame end + */ + uint32_t frame_int_ena:1; + /** blc_frame_int_ena : R/W; bitpos: [15]; default: 0; + * write 1 to enable blc frame done + */ + uint32_t blc_frame_int_ena:1; + /** lsc_frame_int_ena : R/W; bitpos: [16]; default: 0; + * write 1 to enable lsc frame done + */ + uint32_t lsc_frame_int_ena:1; + /** dpc_frame_int_ena : R/W; bitpos: [17]; default: 0; + * write 1 to enable dpc frame done + */ + uint32_t dpc_frame_int_ena:1; + /** bf_frame_int_ena : R/W; bitpos: [18]; default: 0; + * write 1 to enable bf frame done + */ + uint32_t bf_frame_int_ena:1; + /** demosaic_frame_int_ena : R/W; bitpos: [19]; default: 0; + * write 1 to enable demosaic frame done + */ + uint32_t demosaic_frame_int_ena:1; + /** median_frame_int_ena : R/W; bitpos: [20]; default: 0; + * write 1 to enable median frame done + */ + uint32_t median_frame_int_ena:1; + /** ccm_frame_int_ena : R/W; bitpos: [21]; default: 0; + * write 1 to enable ccm frame done + */ + uint32_t ccm_frame_int_ena:1; + /** gamma_frame_int_ena : R/W; bitpos: [22]; default: 0; + * write 1 to enable gamma frame done + */ + uint32_t gamma_frame_int_ena:1; + /** rgb2yuv_frame_int_ena : R/W; bitpos: [23]; default: 0; + * write 1 to enable rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_ena:1; + /** sharp_frame_int_ena : R/W; bitpos: [24]; default: 0; + * write 1 to enable sharp frame done + */ + uint32_t sharp_frame_int_ena:1; + /** color_frame_int_ena : R/W; bitpos: [25]; default: 0; + * write 1 to enable color frame done + */ + uint32_t color_frame_int_ena:1; + /** yuv2rgb_frame_int_ena : R/W; bitpos: [26]; default: 0; + * write 1 to enable yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_ena:1; + /** tail_idi_frame_int_ena : R/W; bitpos: [27]; default: 0; + * write 1 to enable isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_ena:1; + /** header_idi_frame_int_ena : R/W; bitpos: [28]; default: 0; + * write 1 to enable real input frame end of isp_input + */ + uint32_t header_idi_frame_int_ena:1; + /** crop_frame_int_ena : R/W; bitpos: [29]; default: 0; + * write 1 to enable crop frame done + */ + uint32_t crop_frame_int_ena:1; + /** wbg_frame_int_ena : R/W; bitpos: [30]; default: 0; + * write 1 to enable wbg frame done + */ + uint32_t wbg_frame_int_ena:1; + /** crop_err_int_ena : R/W; bitpos: [31]; default: 0; + * write 1 to enable crop error + */ + uint32_t crop_err_int_ena:1; + }; + uint32_t val; +} isp_int_ena_reg_t; + +/** Type of int_clr register + * interrupt clear register + */ +typedef union { + struct { + /** isp_data_type_err_int_clr : WT; bitpos: [0]; default: 0; + * write 1 to clear input data type error + */ + uint32_t isp_data_type_err_int_clr:1; + /** isp_async_fifo_ovf_int_clr : WT; bitpos: [1]; default: 0; + * write 1 to clear isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_clr:1; + /** isp_buf_full_int_clr : WT; bitpos: [2]; default: 0; + * write 1 to clear isp input buffer full + */ + uint32_t isp_buf_full_int_clr:1; + /** isp_hvnum_setting_err_int_clr : WT; bitpos: [3]; default: 0; + * write 1 to clear hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_clr:1; + /** isp_data_type_setting_err_int_clr : WT; bitpos: [4]; default: 0; + * write 1 to clear setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_clr:1; + /** isp_mipi_hnum_unmatch_int_clr : WT; bitpos: [5]; default: 0; + * write 1 to clear hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_clr:1; + /** dpc_check_done_int_clr : WT; bitpos: [6]; default: 0; + * write 1 to clear dpc check done + */ + uint32_t dpc_check_done_int_clr:1; + /** gamma_xcoord_err_int_clr : WT; bitpos: [7]; default: 0; + * write 1 to clear gamma setting error + */ + uint32_t gamma_xcoord_err_int_clr:1; + /** ae_monitor_int_clr : WT; bitpos: [8]; default: 0; + * write 1 to clear ae monitor + */ + uint32_t ae_monitor_int_clr:1; + /** ae_frame_done_int_clr : WT; bitpos: [9]; default: 0; + * write 1 to clear ae + */ + uint32_t ae_frame_done_int_clr:1; + /** af_fdone_int_clr : WT; bitpos: [10]; default: 0; + * write 1 to clear af statistic + */ + uint32_t af_fdone_int_clr:1; + /** af_env_int_clr : WT; bitpos: [11]; default: 0; + * write 1 to clear af monitor + */ + uint32_t af_env_int_clr:1; + /** awb_fdone_int_clr : WT; bitpos: [12]; default: 0; + * write 1 to clear awb + */ + uint32_t awb_fdone_int_clr:1; + /** hist_fdone_int_clr : WT; bitpos: [13]; default: 0; + * write 1 to clear histogram + */ + uint32_t hist_fdone_int_clr:1; + /** frame_int_clr : WT; bitpos: [14]; default: 0; + * write 1 to clear isp frame end + */ + uint32_t frame_int_clr:1; + /** blc_frame_int_clr : WT; bitpos: [15]; default: 0; + * write 1 to clear blc frame done + */ + uint32_t blc_frame_int_clr:1; + /** lsc_frame_int_clr : WT; bitpos: [16]; default: 0; + * write 1 to clear lsc frame done + */ + uint32_t lsc_frame_int_clr:1; + /** dpc_frame_int_clr : WT; bitpos: [17]; default: 0; + * write 1 to clear dpc frame done + */ + uint32_t dpc_frame_int_clr:1; + /** bf_frame_int_clr : WT; bitpos: [18]; default: 0; + * write 1 to clear bf frame done + */ + uint32_t bf_frame_int_clr:1; + /** demosaic_frame_int_clr : WT; bitpos: [19]; default: 0; + * write 1 to clear demosaic frame done + */ + uint32_t demosaic_frame_int_clr:1; + /** median_frame_int_clr : WT; bitpos: [20]; default: 0; + * write 1 to clear median frame done + */ + uint32_t median_frame_int_clr:1; + /** ccm_frame_int_clr : WT; bitpos: [21]; default: 0; + * write 1 to clear ccm frame done + */ + uint32_t ccm_frame_int_clr:1; + /** gamma_frame_int_clr : WT; bitpos: [22]; default: 0; + * write 1 to clear gamma frame done + */ + uint32_t gamma_frame_int_clr:1; + /** rgb2yuv_frame_int_clr : WT; bitpos: [23]; default: 0; + * write 1 to clear rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_clr:1; + /** sharp_frame_int_clr : WT; bitpos: [24]; default: 0; + * write 1 to clear sharp frame done + */ + uint32_t sharp_frame_int_clr:1; + /** color_frame_int_clr : WT; bitpos: [25]; default: 0; + * write 1 to clear color frame done + */ + uint32_t color_frame_int_clr:1; + /** yuv2rgb_frame_int_clr : WT; bitpos: [26]; default: 0; + * write 1 to clear yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_clr:1; + /** tail_idi_frame_int_clr : WT; bitpos: [27]; default: 0; + * write 1 to clear isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_clr:1; + /** header_idi_frame_int_clr : WT; bitpos: [28]; default: 0; + * write 1 to clear real input frame end of isp_input + */ + uint32_t header_idi_frame_int_clr:1; + /** crop_frame_int_clr : WT; bitpos: [29]; default: 0; + * write 1 to clear crop frame done + */ + uint32_t crop_frame_int_clr:1; + /** wbg_frame_int_clr : WT; bitpos: [30]; default: 0; + * write 1 to clear wbg frame done + */ + uint32_t wbg_frame_int_clr:1; + /** crop_err_int_clr : WT; bitpos: [31]; default: 0; + * write 1 to clear crop error + */ + uint32_t crop_err_int_clr:1; + }; + uint32_t val; +} isp_int_clr_reg_t; + + +typedef struct { + volatile isp_ver_date_reg_t ver_date; + volatile isp_clk_en_reg_t clk_en; + volatile isp_cntl_reg_t cntl; + volatile isp_hsync_cnt_reg_t hsync_cnt; + volatile isp_frame_cfg_reg_t frame_cfg; + volatile isp_ccm_coef0_reg_t ccm_coef0; + volatile isp_ccm_coef1_reg_t ccm_coef1; + volatile isp_ccm_coef3_reg_t ccm_coef3; + volatile isp_ccm_coef4_reg_t ccm_coef4; + volatile isp_ccm_coef5_reg_t ccm_coef5; + volatile isp_bf_matrix_ctrl_reg_t bf_matrix_ctrl; + volatile isp_bf_sigma_reg_t bf_sigma; + volatile isp_bf_gau0_reg_t bf_gau0; + volatile isp_bf_gau1_reg_t bf_gau1; + volatile isp_dpc_ctrl_reg_t dpc_ctrl; + volatile isp_dpc_conf_reg_t dpc_conf; + volatile isp_dpc_matrix_ctrl_reg_t dpc_matrix_ctrl; + volatile isp_dpc_deadpix_cnt_reg_t dpc_deadpix_cnt; + volatile isp_lut_cmd_reg_t lut_cmd; + volatile isp_lut_wdata_reg_t lut_wdata; + volatile isp_lut_rdata_reg_t lut_rdata; + volatile isp_lsc_tablesize_reg_t lsc_tablesize; + volatile isp_demosaic_matrix_ctrl_reg_t demosaic_matrix_ctrl; + volatile isp_demosaic_grad_ratio_reg_t demosaic_grad_ratio; + volatile isp_median_matrix_ctrl_reg_t median_matrix_ctrl; + volatile isp_int_raw_reg_t int_raw; + volatile isp_int_st_reg_t int_st; + volatile isp_int_ena_reg_t int_ena; + volatile isp_int_clr_reg_t int_clr; + volatile isp_gamma_ctrl_reg_t gamma_ctrl; + volatile isp_gamma_ry1_reg_t gamma_ry1; + volatile isp_gamma_ry2_reg_t gamma_ry2; + volatile isp_gamma_ry3_reg_t gamma_ry3; + volatile isp_gamma_ry4_reg_t gamma_ry4; + volatile isp_gamma_gy1_reg_t gamma_gy1; + volatile isp_gamma_gy2_reg_t gamma_gy2; + volatile isp_gamma_gy3_reg_t gamma_gy3; + volatile isp_gamma_gy4_reg_t gamma_gy4; + volatile isp_gamma_by1_reg_t gamma_by1; + volatile isp_gamma_by2_reg_t gamma_by2; + volatile isp_gamma_by3_reg_t gamma_by3; + volatile isp_gamma_by4_reg_t gamma_by4; + volatile isp_gamma_rx1_reg_t gamma_rx1; + volatile isp_gamma_rx2_reg_t gamma_rx2; + volatile isp_gamma_gx1_reg_t gamma_gx1; + volatile isp_gamma_gx2_reg_t gamma_gx2; + volatile isp_gamma_bx1_reg_t gamma_bx1; + volatile isp_gamma_bx2_reg_t gamma_bx2; + volatile isp_ae_ctrl_reg_t ae_ctrl; + volatile isp_ae_monitor_reg_t ae_monitor; + volatile isp_ae_bx_reg_t ae_bx; + volatile isp_ae_by_reg_t ae_by; + volatile isp_ae_winpixnum_reg_t ae_winpixnum; + volatile isp_ae_win_reciprocal_reg_t ae_win_reciprocal; + volatile isp_ae_block_mean_0_reg_t ae_block_mean_0; + volatile isp_ae_block_mean_1_reg_t ae_block_mean_1; + volatile isp_ae_block_mean_2_reg_t ae_block_mean_2; + volatile isp_ae_block_mean_3_reg_t ae_block_mean_3; + volatile isp_ae_block_mean_4_reg_t ae_block_mean_4; + volatile isp_ae_block_mean_5_reg_t ae_block_mean_5; + volatile isp_ae_block_mean_6_reg_t ae_block_mean_6; + volatile isp_sharp_ctrl0_reg_t sharp_ctrl0; + volatile isp_sharp_filter0_reg_t sharp_filter0; + volatile isp_sharp_filter1_reg_t sharp_filter1; + volatile isp_sharp_filter2_reg_t sharp_filter2; + volatile isp_sharp_matrix_ctrl_reg_t sharp_matrix_ctrl; + volatile isp_sharp_ctrl1_reg_t sharp_ctrl1; + volatile isp_dma_cntl_reg_t dma_cntl; + volatile isp_dma_raw_data_reg_t dma_raw_data; + volatile isp_cam_cntl_reg_t cam_cntl; + volatile isp_cam_conf_reg_t cam_conf; + volatile isp_af_ctrl0_reg_t af_ctrl0; + volatile isp_af_ctrl1_reg_t af_ctrl1; + volatile isp_af_gen_th_ctrl_reg_t af_gen_th_ctrl; + volatile isp_af_env_user_th_sum_reg_t af_env_user_th_sum; + volatile isp_af_env_user_th_lum_reg_t af_env_user_th_lum; + volatile isp_af_threshold_reg_t af_threshold; + volatile isp_af_hscale_a_reg_t af_hscale_a; + volatile isp_af_vscale_a_reg_t af_vscale_a; + volatile isp_af_hscale_b_reg_t af_hscale_b; + volatile isp_af_vscale_b_reg_t af_vscale_b; + volatile isp_af_hscale_c_reg_t af_hscale_c; + volatile isp_af_vscale_c_reg_t af_vscale_c; + volatile isp_af_sum_a_reg_t af_sum_a; + volatile isp_af_sum_b_reg_t af_sum_b; + volatile isp_af_sum_c_reg_t af_sum_c; + volatile isp_af_lum_a_reg_t af_lum_a; + volatile isp_af_lum_b_reg_t af_lum_b; + volatile isp_af_lum_c_reg_t af_lum_c; + volatile isp_awb_mode_reg_t awb_mode; + volatile isp_awb_hscale_reg_t awb_hscale; + volatile isp_awb_vscale_reg_t awb_vscale; + volatile isp_awb_th_lum_reg_t awb_th_lum; + volatile isp_awb_th_rg_reg_t awb_th_rg; + volatile isp_awb_th_bg_reg_t awb_th_bg; + volatile isp_awb0_white_cnt_reg_t awb0_white_cnt; + volatile isp_awb0_acc_r_reg_t awb0_acc_r; + volatile isp_awb0_acc_g_reg_t awb0_acc_g; + volatile isp_awb0_acc_b_reg_t awb0_acc_b; + volatile isp_color_ctrl_reg_t color_ctrl; + volatile isp_blc_value_reg_t blc_value; + volatile isp_blc_ctrl0_reg_t blc_ctrl0; + volatile isp_blc_ctrl1_reg_t blc_ctrl1; + volatile isp_blc_ctrl2_reg_t blc_ctrl2; + volatile isp_blc_mean_reg_t blc_mean; + volatile isp_hist_mode_reg_t hist_mode; + volatile isp_hist_coeff_reg_t hist_coeff; + volatile isp_hist_offs_reg_t hist_offs; + volatile isp_hist_size_reg_t hist_size; + volatile isp_hist_seg0_reg_t hist_seg0; + volatile isp_hist_seg1_reg_t hist_seg1; + volatile isp_hist_seg2_reg_t hist_seg2; + volatile isp_hist_seg3_reg_t hist_seg3; + volatile isp_hist_weight0_reg_t hist_weight0; + volatile isp_hist_weight1_reg_t hist_weight1; + volatile isp_hist_weight2_reg_t hist_weight2; + volatile isp_hist_weight3_reg_t hist_weight3; + volatile isp_hist_weight4_reg_t hist_weight4; + volatile isp_hist_weight5_reg_t hist_weight5; + volatile isp_hist_weight6_reg_t hist_weight6; + volatile isp_hist_bin0_reg_t hist_bin0; + volatile isp_hist_bin1_reg_t hist_bin1; + volatile isp_hist_bin2_reg_t hist_bin2; + volatile isp_hist_bin3_reg_t hist_bin3; + volatile isp_hist_bin4_reg_t hist_bin4; + volatile isp_hist_bin5_reg_t hist_bin5; + volatile isp_hist_bin6_reg_t hist_bin6; + volatile isp_hist_bin7_reg_t hist_bin7; + volatile isp_hist_bin8_reg_t hist_bin8; + volatile isp_hist_bin9_reg_t hist_bin9; + volatile isp_hist_bin10_reg_t hist_bin10; + volatile isp_hist_bin11_reg_t hist_bin11; + volatile isp_hist_bin12_reg_t hist_bin12; + volatile isp_hist_bin13_reg_t hist_bin13; + volatile isp_hist_bin14_reg_t hist_bin14; + volatile isp_hist_bin15_reg_t hist_bin15; + volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; + volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; + volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2; + volatile isp_mem_aux_ctrl_3_reg_t mem_aux_ctrl_3; + volatile isp_mem_aux_ctrl_4_reg_t mem_aux_ctrl_4; + volatile isp_yuv_format_reg_t yuv_format; + volatile isp_rdn_eco_cs_reg_t rdn_eco_cs; + volatile isp_rdn_eco_low_reg_t rdn_eco_low; + volatile isp_rdn_eco_high_reg_t rdn_eco_high; + volatile isp_crop_ctrl_reg_t crop_ctrl; + volatile isp_crop_y_capture_reg_t crop_y_capture; + volatile isp_crop_x_capture_reg_t crop_x_capture; + volatile isp_crop_err_st_reg_t crop_err_st; + volatile isp_wbg_coef_r_reg_t wbg_coef_r; + volatile isp_wbg_coef_g_reg_t wbg_coef_g; + volatile isp_wbg_coef_b_reg_t wbg_coef_b; + volatile isp_color_hue_ctrl_reg_t color_hue_ctrl; + volatile isp_awb_bx_reg_t awb_bx; + volatile isp_awb_by_reg_t awb_by; + volatile isp_state_reg_t state; + volatile isp_shadow_reg_ctrl_reg_t shadow_reg_ctrl; +} isp_dev_t; + +extern isp_dev_t ISP; + +#ifndef __cplusplus +_Static_assert(sizeof(isp_dev_t) == 0x274, "Invalid size of isp_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/isp_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/isp_reg.h new file mode 100644 index 0000000000..f4d25d40e4 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/isp_reg.h @@ -0,0 +1,4999 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ISP_VER_DATE_REG register + * version control register + */ +#define ISP_VER_DATE_REG (DR_REG_ISP_BASE + 0x0) +/** ISP_VER_DATA : R/W; bitpos: [31:0]; default: 539035144; + * csv version + */ +#define ISP_VER_DATA 0xFFFFFFFFU +#define ISP_VER_DATA_M (ISP_VER_DATA_V << ISP_VER_DATA_S) +#define ISP_VER_DATA_V 0xFFFFFFFFU +#define ISP_VER_DATA_S 0 + +/** ISP_CLK_EN_REG register + * isp clk control register + */ +#define ISP_CLK_EN_REG (DR_REG_ISP_BASE + 0x4) +/** ISP_CLK_EN : R/W; bitpos: [0]; default: 0; + * this bit configures the clk force on of isp reg. 0: disable, 1: enable + */ +#define ISP_CLK_EN (BIT(0)) +#define ISP_CLK_EN_M (ISP_CLK_EN_V << ISP_CLK_EN_S) +#define ISP_CLK_EN_V 0x00000001U +#define ISP_CLK_EN_S 0 +/** ISP_CLK_BLC_FORCE_ON : R/W; bitpos: [1]; default: 0; + * this bit configures the clk force on of blc. 0: disable, 1: enable + */ +#define ISP_CLK_BLC_FORCE_ON (BIT(1)) +#define ISP_CLK_BLC_FORCE_ON_M (ISP_CLK_BLC_FORCE_ON_V << ISP_CLK_BLC_FORCE_ON_S) +#define ISP_CLK_BLC_FORCE_ON_V 0x00000001U +#define ISP_CLK_BLC_FORCE_ON_S 1 +/** ISP_CLK_DPC_FORCE_ON : R/W; bitpos: [2]; default: 0; + * this bit configures the clk force on of dpc. 0: disable, 1: enable + */ +#define ISP_CLK_DPC_FORCE_ON (BIT(2)) +#define ISP_CLK_DPC_FORCE_ON_M (ISP_CLK_DPC_FORCE_ON_V << ISP_CLK_DPC_FORCE_ON_S) +#define ISP_CLK_DPC_FORCE_ON_V 0x00000001U +#define ISP_CLK_DPC_FORCE_ON_S 2 +/** ISP_CLK_BF_FORCE_ON : R/W; bitpos: [3]; default: 0; + * this bit configures the clk force on of bf. 0: disable, 1: enable + */ +#define ISP_CLK_BF_FORCE_ON (BIT(3)) +#define ISP_CLK_BF_FORCE_ON_M (ISP_CLK_BF_FORCE_ON_V << ISP_CLK_BF_FORCE_ON_S) +#define ISP_CLK_BF_FORCE_ON_V 0x00000001U +#define ISP_CLK_BF_FORCE_ON_S 3 +/** ISP_CLK_LSC_FORCE_ON : R/W; bitpos: [4]; default: 0; + * this bit configures the clk force on of lsc. 0: disable, 1: enable + */ +#define ISP_CLK_LSC_FORCE_ON (BIT(4)) +#define ISP_CLK_LSC_FORCE_ON_M (ISP_CLK_LSC_FORCE_ON_V << ISP_CLK_LSC_FORCE_ON_S) +#define ISP_CLK_LSC_FORCE_ON_V 0x00000001U +#define ISP_CLK_LSC_FORCE_ON_S 4 +/** ISP_CLK_DEMOSAIC_FORCE_ON : R/W; bitpos: [5]; default: 0; + * this bit configures the clk force on of demosaic. 0: disable, 1: enable + */ +#define ISP_CLK_DEMOSAIC_FORCE_ON (BIT(5)) +#define ISP_CLK_DEMOSAIC_FORCE_ON_M (ISP_CLK_DEMOSAIC_FORCE_ON_V << ISP_CLK_DEMOSAIC_FORCE_ON_S) +#define ISP_CLK_DEMOSAIC_FORCE_ON_V 0x00000001U +#define ISP_CLK_DEMOSAIC_FORCE_ON_S 5 +/** ISP_CLK_MEDIAN_FORCE_ON : R/W; bitpos: [6]; default: 0; + * this bit configures the clk force on of median. 0: disable, 1: enable + */ +#define ISP_CLK_MEDIAN_FORCE_ON (BIT(6)) +#define ISP_CLK_MEDIAN_FORCE_ON_M (ISP_CLK_MEDIAN_FORCE_ON_V << ISP_CLK_MEDIAN_FORCE_ON_S) +#define ISP_CLK_MEDIAN_FORCE_ON_V 0x00000001U +#define ISP_CLK_MEDIAN_FORCE_ON_S 6 +/** ISP_CLK_CCM_FORCE_ON : R/W; bitpos: [7]; default: 0; + * this bit configures the clk force on of ccm. 0: disable, 1: enable + */ +#define ISP_CLK_CCM_FORCE_ON (BIT(7)) +#define ISP_CLK_CCM_FORCE_ON_M (ISP_CLK_CCM_FORCE_ON_V << ISP_CLK_CCM_FORCE_ON_S) +#define ISP_CLK_CCM_FORCE_ON_V 0x00000001U +#define ISP_CLK_CCM_FORCE_ON_S 7 +/** ISP_CLK_GAMMA_FORCE_ON : R/W; bitpos: [8]; default: 0; + * this bit configures the clk force on of gamma. 0: disable, 1: enable + */ +#define ISP_CLK_GAMMA_FORCE_ON (BIT(8)) +#define ISP_CLK_GAMMA_FORCE_ON_M (ISP_CLK_GAMMA_FORCE_ON_V << ISP_CLK_GAMMA_FORCE_ON_S) +#define ISP_CLK_GAMMA_FORCE_ON_V 0x00000001U +#define ISP_CLK_GAMMA_FORCE_ON_S 8 +/** ISP_CLK_RGB2YUV_FORCE_ON : R/W; bitpos: [9]; default: 0; + * this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable + */ +#define ISP_CLK_RGB2YUV_FORCE_ON (BIT(9)) +#define ISP_CLK_RGB2YUV_FORCE_ON_M (ISP_CLK_RGB2YUV_FORCE_ON_V << ISP_CLK_RGB2YUV_FORCE_ON_S) +#define ISP_CLK_RGB2YUV_FORCE_ON_V 0x00000001U +#define ISP_CLK_RGB2YUV_FORCE_ON_S 9 +/** ISP_CLK_SHARP_FORCE_ON : R/W; bitpos: [10]; default: 0; + * this bit configures the clk force on of sharp. 0: disable, 1: enable + */ +#define ISP_CLK_SHARP_FORCE_ON (BIT(10)) +#define ISP_CLK_SHARP_FORCE_ON_M (ISP_CLK_SHARP_FORCE_ON_V << ISP_CLK_SHARP_FORCE_ON_S) +#define ISP_CLK_SHARP_FORCE_ON_V 0x00000001U +#define ISP_CLK_SHARP_FORCE_ON_S 10 +/** ISP_CLK_COLOR_FORCE_ON : R/W; bitpos: [11]; default: 0; + * this bit configures the clk force on of color. 0: disable, 1: enable + */ +#define ISP_CLK_COLOR_FORCE_ON (BIT(11)) +#define ISP_CLK_COLOR_FORCE_ON_M (ISP_CLK_COLOR_FORCE_ON_V << ISP_CLK_COLOR_FORCE_ON_S) +#define ISP_CLK_COLOR_FORCE_ON_V 0x00000001U +#define ISP_CLK_COLOR_FORCE_ON_S 11 +/** ISP_CLK_YUV2RGB_FORCE_ON : R/W; bitpos: [12]; default: 0; + * this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable + */ +#define ISP_CLK_YUV2RGB_FORCE_ON (BIT(12)) +#define ISP_CLK_YUV2RGB_FORCE_ON_M (ISP_CLK_YUV2RGB_FORCE_ON_V << ISP_CLK_YUV2RGB_FORCE_ON_S) +#define ISP_CLK_YUV2RGB_FORCE_ON_V 0x00000001U +#define ISP_CLK_YUV2RGB_FORCE_ON_S 12 +/** ISP_CLK_AE_FORCE_ON : R/W; bitpos: [13]; default: 0; + * this bit configures the clk force on of ae. 0: disable, 1: enable + */ +#define ISP_CLK_AE_FORCE_ON (BIT(13)) +#define ISP_CLK_AE_FORCE_ON_M (ISP_CLK_AE_FORCE_ON_V << ISP_CLK_AE_FORCE_ON_S) +#define ISP_CLK_AE_FORCE_ON_V 0x00000001U +#define ISP_CLK_AE_FORCE_ON_S 13 +/** ISP_CLK_AF_FORCE_ON : R/W; bitpos: [14]; default: 0; + * this bit configures the clk force on of af. 0: disable, 1: enable + */ +#define ISP_CLK_AF_FORCE_ON (BIT(14)) +#define ISP_CLK_AF_FORCE_ON_M (ISP_CLK_AF_FORCE_ON_V << ISP_CLK_AF_FORCE_ON_S) +#define ISP_CLK_AF_FORCE_ON_V 0x00000001U +#define ISP_CLK_AF_FORCE_ON_S 14 +/** ISP_CLK_AWB_FORCE_ON : R/W; bitpos: [15]; default: 0; + * this bit configures the clk force on of awb. 0: disable, 1: enable + */ +#define ISP_CLK_AWB_FORCE_ON (BIT(15)) +#define ISP_CLK_AWB_FORCE_ON_M (ISP_CLK_AWB_FORCE_ON_V << ISP_CLK_AWB_FORCE_ON_S) +#define ISP_CLK_AWB_FORCE_ON_V 0x00000001U +#define ISP_CLK_AWB_FORCE_ON_S 15 +/** ISP_CLK_HIST_FORCE_ON : R/W; bitpos: [16]; default: 0; + * this bit configures the clk force on of hist. 0: disable, 1: enable + */ +#define ISP_CLK_HIST_FORCE_ON (BIT(16)) +#define ISP_CLK_HIST_FORCE_ON_M (ISP_CLK_HIST_FORCE_ON_V << ISP_CLK_HIST_FORCE_ON_S) +#define ISP_CLK_HIST_FORCE_ON_V 0x00000001U +#define ISP_CLK_HIST_FORCE_ON_S 16 +/** ISP_CLK_MIPI_IDI_FORCE_ON : R/W; bitpos: [17]; default: 0; + * this bit configures the clk force on of mipi idi input. 0: disable, 1: enable + */ +#define ISP_CLK_MIPI_IDI_FORCE_ON (BIT(17)) +#define ISP_CLK_MIPI_IDI_FORCE_ON_M (ISP_CLK_MIPI_IDI_FORCE_ON_V << ISP_CLK_MIPI_IDI_FORCE_ON_S) +#define ISP_CLK_MIPI_IDI_FORCE_ON_V 0x00000001U +#define ISP_CLK_MIPI_IDI_FORCE_ON_S 17 +/** ISP_ISP_MEM_CLK_FORCE_ON : R/W; bitpos: [18]; default: 0; + * this bit configures the clk force on of all isp memory. 0: disable, 1: enable + */ +#define ISP_ISP_MEM_CLK_FORCE_ON (BIT(18)) +#define ISP_ISP_MEM_CLK_FORCE_ON_M (ISP_ISP_MEM_CLK_FORCE_ON_V << ISP_ISP_MEM_CLK_FORCE_ON_S) +#define ISP_ISP_MEM_CLK_FORCE_ON_V 0x00000001U +#define ISP_ISP_MEM_CLK_FORCE_ON_S 18 +/** ISP_CLK_CROP_FORCE_ON : R/W; bitpos: [19]; default: 0; + * this bit configures the clk force on of crop. 0: disable, 1: enable + */ +#define ISP_CLK_CROP_FORCE_ON (BIT(19)) +#define ISP_CLK_CROP_FORCE_ON_M (ISP_CLK_CROP_FORCE_ON_V << ISP_CLK_CROP_FORCE_ON_S) +#define ISP_CLK_CROP_FORCE_ON_V 0x00000001U +#define ISP_CLK_CROP_FORCE_ON_S 19 +/** ISP_CLK_WBG_FORCE_ON : R/W; bitpos: [20]; default: 0; + * this bit configures the clk force on of wbg. 0: disable, 1: enable + */ +#define ISP_CLK_WBG_FORCE_ON (BIT(20)) +#define ISP_CLK_WBG_FORCE_ON_M (ISP_CLK_WBG_FORCE_ON_V << ISP_CLK_WBG_FORCE_ON_S) +#define ISP_CLK_WBG_FORCE_ON_V 0x00000001U +#define ISP_CLK_WBG_FORCE_ON_S 20 + +/** ISP_CNTL_REG register + * isp module enable control register + */ +#define ISP_CNTL_REG (DR_REG_ISP_BASE + 0x8) +/** ISP_MIPI_DATA_EN : R/W; bitpos: [0]; default: 0; + * this bit configures mipi input data enable. 0: disable, 1: enable + */ +#define ISP_MIPI_DATA_EN (BIT(0)) +#define ISP_MIPI_DATA_EN_M (ISP_MIPI_DATA_EN_V << ISP_MIPI_DATA_EN_S) +#define ISP_MIPI_DATA_EN_V 0x00000001U +#define ISP_MIPI_DATA_EN_S 0 +/** ISP_ISP_EN : R/W; bitpos: [1]; default: 1; + * this bit configures isp global enable. 0: disable, 1: enable + */ +#define ISP_ISP_EN (BIT(1)) +#define ISP_ISP_EN_M (ISP_ISP_EN_V << ISP_ISP_EN_S) +#define ISP_ISP_EN_V 0x00000001U +#define ISP_ISP_EN_S 1 +/** ISP_BLC_EN : R/W; bitpos: [2]; default: 0; + * this bit configures blc enable. 0: disable, 1: enable + */ +#define ISP_BLC_EN (BIT(2)) +#define ISP_BLC_EN_M (ISP_BLC_EN_V << ISP_BLC_EN_S) +#define ISP_BLC_EN_V 0x00000001U +#define ISP_BLC_EN_S 2 +/** ISP_DPC_EN : R/W; bitpos: [3]; default: 0; + * this bit configures dpc enable. 0: disable, 1: enable + */ +#define ISP_DPC_EN (BIT(3)) +#define ISP_DPC_EN_M (ISP_DPC_EN_V << ISP_DPC_EN_S) +#define ISP_DPC_EN_V 0x00000001U +#define ISP_DPC_EN_S 3 +/** ISP_BF_EN : R/W; bitpos: [4]; default: 0; + * this bit configures bf enable. 0: disable, 1: enable + */ +#define ISP_BF_EN (BIT(4)) +#define ISP_BF_EN_M (ISP_BF_EN_V << ISP_BF_EN_S) +#define ISP_BF_EN_V 0x00000001U +#define ISP_BF_EN_S 4 +/** ISP_LSC_EN : R/W; bitpos: [5]; default: 0; + * this bit configures lsc enable. 0: disable, 1: enable + */ +#define ISP_LSC_EN (BIT(5)) +#define ISP_LSC_EN_M (ISP_LSC_EN_V << ISP_LSC_EN_S) +#define ISP_LSC_EN_V 0x00000001U +#define ISP_LSC_EN_S 5 +/** ISP_DEMOSAIC_EN : R/W; bitpos: [6]; default: 1; + * this bit configures demosaic enable. 0: disable, 1: enable + */ +#define ISP_DEMOSAIC_EN (BIT(6)) +#define ISP_DEMOSAIC_EN_M (ISP_DEMOSAIC_EN_V << ISP_DEMOSAIC_EN_S) +#define ISP_DEMOSAIC_EN_V 0x00000001U +#define ISP_DEMOSAIC_EN_S 6 +/** ISP_MEDIAN_EN : R/W; bitpos: [7]; default: 0; + * this bit configures median enable. 0: disable, 1: enable + */ +#define ISP_MEDIAN_EN (BIT(7)) +#define ISP_MEDIAN_EN_M (ISP_MEDIAN_EN_V << ISP_MEDIAN_EN_S) +#define ISP_MEDIAN_EN_V 0x00000001U +#define ISP_MEDIAN_EN_S 7 +/** ISP_CCM_EN : R/W; bitpos: [8]; default: 0; + * this bit configures ccm enable. 0: disable, 1: enable + */ +#define ISP_CCM_EN (BIT(8)) +#define ISP_CCM_EN_M (ISP_CCM_EN_V << ISP_CCM_EN_S) +#define ISP_CCM_EN_V 0x00000001U +#define ISP_CCM_EN_S 8 +/** ISP_GAMMA_EN : R/W; bitpos: [9]; default: 0; + * this bit configures gamma enable. 0: disable, 1: enable + */ +#define ISP_GAMMA_EN (BIT(9)) +#define ISP_GAMMA_EN_M (ISP_GAMMA_EN_V << ISP_GAMMA_EN_S) +#define ISP_GAMMA_EN_V 0x00000001U +#define ISP_GAMMA_EN_S 9 +/** ISP_RGB2YUV_EN : R/W; bitpos: [10]; default: 1; + * this bit configures rgb2yuv enable. 0: disable, 1: enable + */ +#define ISP_RGB2YUV_EN (BIT(10)) +#define ISP_RGB2YUV_EN_M (ISP_RGB2YUV_EN_V << ISP_RGB2YUV_EN_S) +#define ISP_RGB2YUV_EN_V 0x00000001U +#define ISP_RGB2YUV_EN_S 10 +/** ISP_SHARP_EN : R/W; bitpos: [11]; default: 0; + * this bit configures sharp enable. 0: disable, 1: enable + */ +#define ISP_SHARP_EN (BIT(11)) +#define ISP_SHARP_EN_M (ISP_SHARP_EN_V << ISP_SHARP_EN_S) +#define ISP_SHARP_EN_V 0x00000001U +#define ISP_SHARP_EN_S 11 +/** ISP_COLOR_EN : R/W; bitpos: [12]; default: 0; + * this bit configures color enable. 0: disable, 1: enable + */ +#define ISP_COLOR_EN (BIT(12)) +#define ISP_COLOR_EN_M (ISP_COLOR_EN_V << ISP_COLOR_EN_S) +#define ISP_COLOR_EN_V 0x00000001U +#define ISP_COLOR_EN_S 12 +/** ISP_YUV2RGB_EN : R/W; bitpos: [13]; default: 1; + * this bit configures yuv2rgb enable. 0: disable, 1: enable + */ +#define ISP_YUV2RGB_EN (BIT(13)) +#define ISP_YUV2RGB_EN_M (ISP_YUV2RGB_EN_V << ISP_YUV2RGB_EN_S) +#define ISP_YUV2RGB_EN_V 0x00000001U +#define ISP_YUV2RGB_EN_S 13 +/** ISP_AE_EN : R/W; bitpos: [14]; default: 0; + * this bit configures ae enable. 0: disable, 1: enable + */ +#define ISP_AE_EN (BIT(14)) +#define ISP_AE_EN_M (ISP_AE_EN_V << ISP_AE_EN_S) +#define ISP_AE_EN_V 0x00000001U +#define ISP_AE_EN_S 14 +/** ISP_AF_EN : R/W; bitpos: [15]; default: 0; + * this bit configures af enable. 0: disable, 1: enable + */ +#define ISP_AF_EN (BIT(15)) +#define ISP_AF_EN_M (ISP_AF_EN_V << ISP_AF_EN_S) +#define ISP_AF_EN_V 0x00000001U +#define ISP_AF_EN_S 15 +/** ISP_AWB_EN : R/W; bitpos: [16]; default: 0; + * this bit configures awb enable. 0: disable, 1: enable + */ +#define ISP_AWB_EN (BIT(16)) +#define ISP_AWB_EN_M (ISP_AWB_EN_V << ISP_AWB_EN_S) +#define ISP_AWB_EN_V 0x00000001U +#define ISP_AWB_EN_S 16 +/** ISP_HIST_EN : R/W; bitpos: [17]; default: 0; + * this bit configures hist enable. 0: disable, 1: enable + */ +#define ISP_HIST_EN (BIT(17)) +#define ISP_HIST_EN_M (ISP_HIST_EN_V << ISP_HIST_EN_S) +#define ISP_HIST_EN_V 0x00000001U +#define ISP_HIST_EN_S 17 +/** ISP_CROP_EN : R/W; bitpos: [18]; default: 0; + * this bit configures crop enable. 0: disable, 1: enable + */ +#define ISP_CROP_EN (BIT(18)) +#define ISP_CROP_EN_M (ISP_CROP_EN_V << ISP_CROP_EN_S) +#define ISP_CROP_EN_V 0x00000001U +#define ISP_CROP_EN_S 18 +/** ISP_WBG_EN : R/W; bitpos: [19]; default: 0; + * this bit configures wbg enable. 0: disable, 1: enable + */ +#define ISP_WBG_EN (BIT(19)) +#define ISP_WBG_EN_M (ISP_WBG_EN_V << ISP_WBG_EN_S) +#define ISP_WBG_EN_V 0x00000001U +#define ISP_WBG_EN_S 19 +/** ISP_BYTE_ENDIAN_ORDER : R/W; bitpos: [24]; default: 0; + * select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: + * {[7:0], [15:8], [23:16], [31:24]} + */ +#define ISP_BYTE_ENDIAN_ORDER (BIT(24)) +#define ISP_BYTE_ENDIAN_ORDER_M (ISP_BYTE_ENDIAN_ORDER_V << ISP_BYTE_ENDIAN_ORDER_S) +#define ISP_BYTE_ENDIAN_ORDER_V 0x00000001U +#define ISP_BYTE_ENDIAN_ORDER_S 24 +/** ISP_ISP_DATA_TYPE : R/W; bitpos: [26:25]; default: 0; + * this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 + */ +#define ISP_ISP_DATA_TYPE 0x00000003U +#define ISP_ISP_DATA_TYPE_M (ISP_ISP_DATA_TYPE_V << ISP_ISP_DATA_TYPE_S) +#define ISP_ISP_DATA_TYPE_V 0x00000003U +#define ISP_ISP_DATA_TYPE_S 25 +/** ISP_ISP_IN_SRC : R/W; bitpos: [28:27]; default: 0; + * this field configures input data source, 0:CSI HOST 1:CAM 2:DMA + */ +#define ISP_ISP_IN_SRC 0x00000003U +#define ISP_ISP_IN_SRC_M (ISP_ISP_IN_SRC_V << ISP_ISP_IN_SRC_S) +#define ISP_ISP_IN_SRC_V 0x00000003U +#define ISP_ISP_IN_SRC_S 27 +/** ISP_ISP_OUT_TYPE : R/W; bitpos: [31:29]; default: 2; + * this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: + * RGB565 + */ +#define ISP_ISP_OUT_TYPE 0x00000007U +#define ISP_ISP_OUT_TYPE_M (ISP_ISP_OUT_TYPE_V << ISP_ISP_OUT_TYPE_S) +#define ISP_ISP_OUT_TYPE_V 0x00000007U +#define ISP_ISP_OUT_TYPE_S 29 + +/** ISP_HSYNC_CNT_REG register + * header hsync interval control register + */ +#define ISP_HSYNC_CNT_REG (DR_REG_ISP_BASE + 0xc) +/** ISP_HSYNC_CNT : R/W; bitpos: [7:0]; default: 7; + * this field configures the number of clock before hsync and after vsync and line_end + * when decodes pix data from idi to isp + */ +#define ISP_HSYNC_CNT 0x000000FFU +#define ISP_HSYNC_CNT_M (ISP_HSYNC_CNT_V << ISP_HSYNC_CNT_S) +#define ISP_HSYNC_CNT_V 0x000000FFU +#define ISP_HSYNC_CNT_S 0 + +/** ISP_FRAME_CFG_REG register + * frame control parameter register + */ +#define ISP_FRAME_CFG_REG (DR_REG_ISP_BASE + 0x10) +/** ISP_VADR_NUM : R/W; bitpos: [11:0]; default: 480; + * this field configures input image size in y-direction, image row number - 1 + */ +#define ISP_VADR_NUM 0x00000FFFU +#define ISP_VADR_NUM_M (ISP_VADR_NUM_V << ISP_VADR_NUM_S) +#define ISP_VADR_NUM_V 0x00000FFFU +#define ISP_VADR_NUM_S 0 +/** ISP_HADR_NUM : R/W; bitpos: [23:12]; default: 480; + * this field configures input image size in x-direction, image line number - 1 + */ +#define ISP_HADR_NUM 0x00000FFFU +#define ISP_HADR_NUM_M (ISP_HADR_NUM_V << ISP_HADR_NUM_S) +#define ISP_HADR_NUM_V 0x00000FFFU +#define ISP_HADR_NUM_S 12 +/** ISP_BAYER_MODE : R/W; bitpos: [28:27]; default: 0; + * this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 + * : GR/BG 11 : RG/GB + */ +#define ISP_BAYER_MODE 0x00000003U +#define ISP_BAYER_MODE_M (ISP_BAYER_MODE_V << ISP_BAYER_MODE_S) +#define ISP_BAYER_MODE_V 0x00000003U +#define ISP_BAYER_MODE_S 27 +/** ISP_HSYNC_START_EXIST : R/W; bitpos: [29]; default: 1; + * this bit configures the line end packet exist or not. 0: not exist, 1: exist + */ +#define ISP_HSYNC_START_EXIST (BIT(29)) +#define ISP_HSYNC_START_EXIST_M (ISP_HSYNC_START_EXIST_V << ISP_HSYNC_START_EXIST_S) +#define ISP_HSYNC_START_EXIST_V 0x00000001U +#define ISP_HSYNC_START_EXIST_S 29 +/** ISP_HSYNC_END_EXIST : R/W; bitpos: [30]; default: 1; + * this bit configures the line start packet exist or not. 0: not exist, 1: exist + */ +#define ISP_HSYNC_END_EXIST (BIT(30)) +#define ISP_HSYNC_END_EXIST_M (ISP_HSYNC_END_EXIST_V << ISP_HSYNC_END_EXIST_S) +#define ISP_HSYNC_END_EXIST_V 0x00000001U +#define ISP_HSYNC_END_EXIST_S 30 + +/** ISP_CCM_COEF0_REG register + * ccm coef register 0 + */ +#define ISP_CCM_COEF0_REG (DR_REG_ISP_BASE + 0x14) +/** ISP_CCM_RR : R/W; bitpos: [12:0]; default: 256; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_RR 0x00001FFFU +#define ISP_CCM_RR_M (ISP_CCM_RR_V << ISP_CCM_RR_S) +#define ISP_CCM_RR_V 0x00001FFFU +#define ISP_CCM_RR_S 0 +/** ISP_CCM_RG : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_RG 0x00001FFFU +#define ISP_CCM_RG_M (ISP_CCM_RG_V << ISP_CCM_RG_S) +#define ISP_CCM_RG_V 0x00001FFFU +#define ISP_CCM_RG_S 13 + +/** ISP_CCM_COEF1_REG register + * ccm coef register 1 + */ +#define ISP_CCM_COEF1_REG (DR_REG_ISP_BASE + 0x18) +/** ISP_CCM_RB : R/W; bitpos: [12:0]; default: 0; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_RB 0x00001FFFU +#define ISP_CCM_RB_M (ISP_CCM_RB_V << ISP_CCM_RB_S) +#define ISP_CCM_RB_V 0x00001FFFU +#define ISP_CCM_RB_S 0 +/** ISP_CCM_GR : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_GR 0x00001FFFU +#define ISP_CCM_GR_M (ISP_CCM_GR_V << ISP_CCM_GR_S) +#define ISP_CCM_GR_V 0x00001FFFU +#define ISP_CCM_GR_S 13 + +/** ISP_CCM_COEF3_REG register + * ccm coef register 3 + */ +#define ISP_CCM_COEF3_REG (DR_REG_ISP_BASE + 0x1c) +/** ISP_CCM_GG : R/W; bitpos: [12:0]; default: 256; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_GG 0x00001FFFU +#define ISP_CCM_GG_M (ISP_CCM_GG_V << ISP_CCM_GG_S) +#define ISP_CCM_GG_V 0x00001FFFU +#define ISP_CCM_GG_S 0 +/** ISP_CCM_GB : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_GB 0x00001FFFU +#define ISP_CCM_GB_M (ISP_CCM_GB_V << ISP_CCM_GB_S) +#define ISP_CCM_GB_V 0x00001FFFU +#define ISP_CCM_GB_S 13 + +/** ISP_CCM_COEF4_REG register + * ccm coef register 4 + */ +#define ISP_CCM_COEF4_REG (DR_REG_ISP_BASE + 0x20) +/** ISP_CCM_BR : R/W; bitpos: [12:0]; default: 0; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_BR 0x00001FFFU +#define ISP_CCM_BR_M (ISP_CCM_BR_V << ISP_CCM_BR_S) +#define ISP_CCM_BR_V 0x00001FFFU +#define ISP_CCM_BR_S 0 +/** ISP_CCM_BG : R/W; bitpos: [25:13]; default: 0; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_BG 0x00001FFFU +#define ISP_CCM_BG_M (ISP_CCM_BG_V << ISP_CCM_BG_S) +#define ISP_CCM_BG_V 0x00001FFFU +#define ISP_CCM_BG_S 13 + +/** ISP_CCM_COEF5_REG register + * ccm coef register 5 + */ +#define ISP_CCM_COEF5_REG (DR_REG_ISP_BASE + 0x24) +/** ISP_CCM_BB : R/W; bitpos: [12:0]; default: 256; + * this field configures the color correction matrix coefficient + */ +#define ISP_CCM_BB 0x00001FFFU +#define ISP_CCM_BB_M (ISP_CCM_BB_V << ISP_CCM_BB_S) +#define ISP_CCM_BB_V 0x00001FFFU +#define ISP_CCM_BB_S 0 + +/** ISP_BF_MATRIX_CTRL_REG register + * bf pix2matrix ctrl + */ +#define ISP_BF_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x28) +/** ISP_BF_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 + * and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse + * function + */ +#define ISP_BF_TAIL_PIXEN_PULSE_TL 0x000000FFU +#define ISP_BF_TAIL_PIXEN_PULSE_TL_M (ISP_BF_TAIL_PIXEN_PULSE_TL_V << ISP_BF_TAIL_PIXEN_PULSE_TL_S) +#define ISP_BF_TAIL_PIXEN_PULSE_TL_V 0x000000FFU +#define ISP_BF_TAIL_PIXEN_PULSE_TL_S 0 +/** ISP_BF_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and + * reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse + * function + */ +#define ISP_BF_TAIL_PIXEN_PULSE_TH 0x000000FFU +#define ISP_BF_TAIL_PIXEN_PULSE_TH_M (ISP_BF_TAIL_PIXEN_PULSE_TH_V << ISP_BF_TAIL_PIXEN_PULSE_TH_S) +#define ISP_BF_TAIL_PIXEN_PULSE_TH_V 0x000000FFU +#define ISP_BF_TAIL_PIXEN_PULSE_TH_S 8 +/** ISP_BF_PADDING_DATA : R/W; bitpos: [23:16]; default: 0; + * this field configures bf matrix padding data + */ +#define ISP_BF_PADDING_DATA 0x000000FFU +#define ISP_BF_PADDING_DATA_M (ISP_BF_PADDING_DATA_V << ISP_BF_PADDING_DATA_S) +#define ISP_BF_PADDING_DATA_V 0x000000FFU +#define ISP_BF_PADDING_DATA_S 16 +/** ISP_BF_PADDING_MODE : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of bf matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ +#define ISP_BF_PADDING_MODE (BIT(24)) +#define ISP_BF_PADDING_MODE_M (ISP_BF_PADDING_MODE_V << ISP_BF_PADDING_MODE_S) +#define ISP_BF_PADDING_MODE_V 0x00000001U +#define ISP_BF_PADDING_MODE_S 24 + +/** ISP_BF_SIGMA_REG register + * bf denoising level control register + */ +#define ISP_BF_SIGMA_REG (DR_REG_ISP_BASE + 0x2c) +/** ISP_SIGMA : R/W; bitpos: [5:0]; default: 2; + * this field configures the bayer denoising level, valid data from 2 to 20 + */ +#define ISP_SIGMA 0x0000003FU +#define ISP_SIGMA_M (ISP_SIGMA_V << ISP_SIGMA_S) +#define ISP_SIGMA_V 0x0000003FU +#define ISP_SIGMA_S 0 + +/** ISP_BF_GAU0_REG register + * bf gau template register 0 + */ +#define ISP_BF_GAU0_REG (DR_REG_ISP_BASE + 0x30) +/** ISP_GAU_TEMPLATE21 : R/W; bitpos: [3:0]; default: 15; + * this field configures index 21 of gaussian template + */ +#define ISP_GAU_TEMPLATE21 0x0000000FU +#define ISP_GAU_TEMPLATE21_M (ISP_GAU_TEMPLATE21_V << ISP_GAU_TEMPLATE21_S) +#define ISP_GAU_TEMPLATE21_V 0x0000000FU +#define ISP_GAU_TEMPLATE21_S 0 +/** ISP_GAU_TEMPLATE20 : R/W; bitpos: [7:4]; default: 15; + * this field configures index 20 of gaussian template + */ +#define ISP_GAU_TEMPLATE20 0x0000000FU +#define ISP_GAU_TEMPLATE20_M (ISP_GAU_TEMPLATE20_V << ISP_GAU_TEMPLATE20_S) +#define ISP_GAU_TEMPLATE20_V 0x0000000FU +#define ISP_GAU_TEMPLATE20_S 4 +/** ISP_GAU_TEMPLATE12 : R/W; bitpos: [11:8]; default: 15; + * this field configures index 12 of gaussian template + */ +#define ISP_GAU_TEMPLATE12 0x0000000FU +#define ISP_GAU_TEMPLATE12_M (ISP_GAU_TEMPLATE12_V << ISP_GAU_TEMPLATE12_S) +#define ISP_GAU_TEMPLATE12_V 0x0000000FU +#define ISP_GAU_TEMPLATE12_S 8 +/** ISP_GAU_TEMPLATE11 : R/W; bitpos: [15:12]; default: 15; + * this field configures index 11 of gaussian template + */ +#define ISP_GAU_TEMPLATE11 0x0000000FU +#define ISP_GAU_TEMPLATE11_M (ISP_GAU_TEMPLATE11_V << ISP_GAU_TEMPLATE11_S) +#define ISP_GAU_TEMPLATE11_V 0x0000000FU +#define ISP_GAU_TEMPLATE11_S 12 +/** ISP_GAU_TEMPLATE10 : R/W; bitpos: [19:16]; default: 15; + * this field configures index 10 of gaussian template + */ +#define ISP_GAU_TEMPLATE10 0x0000000FU +#define ISP_GAU_TEMPLATE10_M (ISP_GAU_TEMPLATE10_V << ISP_GAU_TEMPLATE10_S) +#define ISP_GAU_TEMPLATE10_V 0x0000000FU +#define ISP_GAU_TEMPLATE10_S 16 +/** ISP_GAU_TEMPLATE02 : R/W; bitpos: [23:20]; default: 15; + * this field configures index 02 of gaussian template + */ +#define ISP_GAU_TEMPLATE02 0x0000000FU +#define ISP_GAU_TEMPLATE02_M (ISP_GAU_TEMPLATE02_V << ISP_GAU_TEMPLATE02_S) +#define ISP_GAU_TEMPLATE02_V 0x0000000FU +#define ISP_GAU_TEMPLATE02_S 20 +/** ISP_GAU_TEMPLATE01 : R/W; bitpos: [27:24]; default: 15; + * this field configures index 01 of gaussian template + */ +#define ISP_GAU_TEMPLATE01 0x0000000FU +#define ISP_GAU_TEMPLATE01_M (ISP_GAU_TEMPLATE01_V << ISP_GAU_TEMPLATE01_S) +#define ISP_GAU_TEMPLATE01_V 0x0000000FU +#define ISP_GAU_TEMPLATE01_S 24 +/** ISP_GAU_TEMPLATE00 : R/W; bitpos: [31:28]; default: 15; + * this field configures index 00 of gaussian template + */ +#define ISP_GAU_TEMPLATE00 0x0000000FU +#define ISP_GAU_TEMPLATE00_M (ISP_GAU_TEMPLATE00_V << ISP_GAU_TEMPLATE00_S) +#define ISP_GAU_TEMPLATE00_V 0x0000000FU +#define ISP_GAU_TEMPLATE00_S 28 + +/** ISP_BF_GAU1_REG register + * bf gau template register 1 + */ +#define ISP_BF_GAU1_REG (DR_REG_ISP_BASE + 0x34) +/** ISP_GAU_TEMPLATE22 : R/W; bitpos: [3:0]; default: 15; + * this field configures index 22 of gaussian template + */ +#define ISP_GAU_TEMPLATE22 0x0000000FU +#define ISP_GAU_TEMPLATE22_M (ISP_GAU_TEMPLATE22_V << ISP_GAU_TEMPLATE22_S) +#define ISP_GAU_TEMPLATE22_V 0x0000000FU +#define ISP_GAU_TEMPLATE22_S 0 + +/** ISP_DPC_CTRL_REG register + * DPC mode control register + */ +#define ISP_DPC_CTRL_REG (DR_REG_ISP_BASE + 0x38) +/** ISP_DPC_CHECK_EN : R/W; bitpos: [0]; default: 0; + * this bit configures the check mode enable. 0: disable, 1: enable + */ +#define ISP_DPC_CHECK_EN (BIT(0)) +#define ISP_DPC_CHECK_EN_M (ISP_DPC_CHECK_EN_V << ISP_DPC_CHECK_EN_S) +#define ISP_DPC_CHECK_EN_V 0x00000001U +#define ISP_DPC_CHECK_EN_S 0 +/** ISP_STA_EN : R/W; bitpos: [1]; default: 0; + * this bit configures the sta dpc enable. 0: disable, 1: enable + */ +#define ISP_STA_EN (BIT(1)) +#define ISP_STA_EN_M (ISP_STA_EN_V << ISP_STA_EN_S) +#define ISP_STA_EN_V 0x00000001U +#define ISP_STA_EN_S 1 +/** ISP_DYN_EN : R/W; bitpos: [2]; default: 1; + * this bit configures the dyn dpc enable. 0: disable, 1: enable + */ +#define ISP_DYN_EN (BIT(2)) +#define ISP_DYN_EN_M (ISP_DYN_EN_V << ISP_DYN_EN_S) +#define ISP_DYN_EN_V 0x00000001U +#define ISP_DYN_EN_S 2 +/** ISP_DPC_BLACK_EN : R/W; bitpos: [3]; default: 0; + * this bit configures input image type select when in check mode, 0: white img, 1: + * black img + */ +#define ISP_DPC_BLACK_EN (BIT(3)) +#define ISP_DPC_BLACK_EN_M (ISP_DPC_BLACK_EN_V << ISP_DPC_BLACK_EN_S) +#define ISP_DPC_BLACK_EN_V 0x00000001U +#define ISP_DPC_BLACK_EN_S 3 +/** ISP_DPC_METHOD_SEL : R/W; bitpos: [4]; default: 0; + * this bit configures dyn dpc method select. 0: simple method, 1: hard method + */ +#define ISP_DPC_METHOD_SEL (BIT(4)) +#define ISP_DPC_METHOD_SEL_M (ISP_DPC_METHOD_SEL_V << ISP_DPC_METHOD_SEL_S) +#define ISP_DPC_METHOD_SEL_V 0x00000001U +#define ISP_DPC_METHOD_SEL_S 4 +/** ISP_DPC_CHECK_OD_EN : R/W; bitpos: [5]; default: 0; + * this bit configures output pixel data when in check mode or not. 0: no data output, + * 1: data output + */ +#define ISP_DPC_CHECK_OD_EN (BIT(5)) +#define ISP_DPC_CHECK_OD_EN_M (ISP_DPC_CHECK_OD_EN_V << ISP_DPC_CHECK_OD_EN_S) +#define ISP_DPC_CHECK_OD_EN_V 0x00000001U +#define ISP_DPC_CHECK_OD_EN_S 5 + +/** ISP_DPC_CONF_REG register + * DPC parameter config register + */ +#define ISP_DPC_CONF_REG (DR_REG_ISP_BASE + 0x3c) +/** ISP_DPC_THRESHOLD_L : R/W; bitpos: [7:0]; default: 48; + * this bit configures the threshold to detect black img in check mode, or the low + * threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit + * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + */ +#define ISP_DPC_THRESHOLD_L 0x000000FFU +#define ISP_DPC_THRESHOLD_L_M (ISP_DPC_THRESHOLD_L_V << ISP_DPC_THRESHOLD_L_S) +#define ISP_DPC_THRESHOLD_L_V 0x000000FFU +#define ISP_DPC_THRESHOLD_L_S 0 +/** ISP_DPC_THRESHOLD_H : R/W; bitpos: [15:8]; default: 48; + * this bit configures the threshold to detect white img in check mode, or the high + * threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit + * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + */ +#define ISP_DPC_THRESHOLD_H 0x000000FFU +#define ISP_DPC_THRESHOLD_H_M (ISP_DPC_THRESHOLD_H_V << ISP_DPC_THRESHOLD_H_S) +#define ISP_DPC_THRESHOLD_H_V 0x000000FFU +#define ISP_DPC_THRESHOLD_H_S 8 +/** ISP_DPC_FACTOR_DARK : R/W; bitpos: [21:16]; default: 16; + * this field configures the dynamic correction method 1 dark factor + */ +#define ISP_DPC_FACTOR_DARK 0x0000003FU +#define ISP_DPC_FACTOR_DARK_M (ISP_DPC_FACTOR_DARK_V << ISP_DPC_FACTOR_DARK_S) +#define ISP_DPC_FACTOR_DARK_V 0x0000003FU +#define ISP_DPC_FACTOR_DARK_S 16 +/** ISP_DPC_FACTOR_BRIG : R/W; bitpos: [27:22]; default: 16; + * this field configures the dynamic correction method 1 bright factor + */ +#define ISP_DPC_FACTOR_BRIG 0x0000003FU +#define ISP_DPC_FACTOR_BRIG_M (ISP_DPC_FACTOR_BRIG_V << ISP_DPC_FACTOR_BRIG_S) +#define ISP_DPC_FACTOR_BRIG_V 0x0000003FU +#define ISP_DPC_FACTOR_BRIG_S 22 + +/** ISP_DPC_MATRIX_CTRL_REG register + * dpc pix2matrix ctrl + */ +#define ISP_DPC_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x40) +/** ISP_DPC_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 + * and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail + * pulse function + */ +#define ISP_DPC_TAIL_PIXEN_PULSE_TL 0x000000FFU +#define ISP_DPC_TAIL_PIXEN_PULSE_TL_M (ISP_DPC_TAIL_PIXEN_PULSE_TL_V << ISP_DPC_TAIL_PIXEN_PULSE_TL_S) +#define ISP_DPC_TAIL_PIXEN_PULSE_TL_V 0x000000FFU +#define ISP_DPC_TAIL_PIXEN_PULSE_TL_S 0 +/** ISP_DPC_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and + * reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse + * function + */ +#define ISP_DPC_TAIL_PIXEN_PULSE_TH 0x000000FFU +#define ISP_DPC_TAIL_PIXEN_PULSE_TH_M (ISP_DPC_TAIL_PIXEN_PULSE_TH_V << ISP_DPC_TAIL_PIXEN_PULSE_TH_S) +#define ISP_DPC_TAIL_PIXEN_PULSE_TH_V 0x000000FFU +#define ISP_DPC_TAIL_PIXEN_PULSE_TH_S 8 +/** ISP_DPC_PADDING_DATA : R/W; bitpos: [23:16]; default: 0; + * this field configures dpc matrix padding data + */ +#define ISP_DPC_PADDING_DATA 0x000000FFU +#define ISP_DPC_PADDING_DATA_M (ISP_DPC_PADDING_DATA_V << ISP_DPC_PADDING_DATA_S) +#define ISP_DPC_PADDING_DATA_V 0x000000FFU +#define ISP_DPC_PADDING_DATA_S 16 +/** ISP_DPC_PADDING_MODE : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of dpc matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ +#define ISP_DPC_PADDING_MODE (BIT(24)) +#define ISP_DPC_PADDING_MODE_M (ISP_DPC_PADDING_MODE_V << ISP_DPC_PADDING_MODE_S) +#define ISP_DPC_PADDING_MODE_V 0x00000001U +#define ISP_DPC_PADDING_MODE_S 24 + +/** ISP_DPC_DEADPIX_CNT_REG register + * DPC dead-pix number register + */ +#define ISP_DPC_DEADPIX_CNT_REG (DR_REG_ISP_BASE + 0x44) +/** ISP_DPC_DEADPIX_CNT : RO; bitpos: [9:0]; default: 0; + * this field represents the dead pixel count + */ +#define ISP_DPC_DEADPIX_CNT 0x000003FFU +#define ISP_DPC_DEADPIX_CNT_M (ISP_DPC_DEADPIX_CNT_V << ISP_DPC_DEADPIX_CNT_S) +#define ISP_DPC_DEADPIX_CNT_V 0x000003FFU +#define ISP_DPC_DEADPIX_CNT_S 0 + +/** ISP_LUT_CMD_REG register + * LUT command register + */ +#define ISP_LUT_CMD_REG (DR_REG_ISP_BASE + 0x48) +/** ISP_LUT_ADDR : WT; bitpos: [11:0]; default: 0; + * this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b + * lut, 01 sel r_gr lut + */ +#define ISP_LUT_ADDR 0x00000FFFU +#define ISP_LUT_ADDR_M (ISP_LUT_ADDR_V << ISP_LUT_ADDR_S) +#define ISP_LUT_ADDR_V 0x00000FFFU +#define ISP_LUT_ADDR_S 0 +/** ISP_LUT_NUM : WT; bitpos: [15:12]; default: 0; + * this field configures the lut selection. 0000:LSC LUT. 0001:DPC LUT. 0010:AWB LUT + */ +#define ISP_LUT_NUM 0x0000000FU +#define ISP_LUT_NUM_M (ISP_LUT_NUM_V << ISP_LUT_NUM_S) +#define ISP_LUT_NUM_V 0x0000000FU +#define ISP_LUT_NUM_S 12 +/** ISP_LUT_CMD : WT; bitpos: [16]; default: 0; + * this bit configures the access event of lut. 0:rd 1: wr + */ +#define ISP_LUT_CMD (BIT(16)) +#define ISP_LUT_CMD_M (ISP_LUT_CMD_V << ISP_LUT_CMD_S) +#define ISP_LUT_CMD_V 0x00000001U +#define ISP_LUT_CMD_S 16 + +/** ISP_LUT_WDATA_REG register + * LUT write data register + */ +#define ISP_LUT_WDATA_REG (DR_REG_ISP_BASE + 0x4c) +/** ISP_LUT_WDATA : R/W; bitpos: [31:0]; default: 0; + * this field configures the write data of lut. please initial ISP_LUT_WDATA before + * write ISP_LUT_CMD register + */ +#define ISP_LUT_WDATA 0xFFFFFFFFU +#define ISP_LUT_WDATA_M (ISP_LUT_WDATA_V << ISP_LUT_WDATA_S) +#define ISP_LUT_WDATA_V 0xFFFFFFFFU +#define ISP_LUT_WDATA_S 0 + +/** ISP_LUT_RDATA_REG register + * LUT read data register + */ +#define ISP_LUT_RDATA_REG (DR_REG_ISP_BASE + 0x50) +/** ISP_LUT_RDATA : RO; bitpos: [31:0]; default: 0; + * this field represents the read data of lut. read ISP_LUT_RDATA after write + * ISP_LUT_CMD register + */ +#define ISP_LUT_RDATA 0xFFFFFFFFU +#define ISP_LUT_RDATA_M (ISP_LUT_RDATA_V << ISP_LUT_RDATA_S) +#define ISP_LUT_RDATA_V 0xFFFFFFFFU +#define ISP_LUT_RDATA_S 0 + +/** ISP_LSC_TABLESIZE_REG register + * LSC point in x-direction + */ +#define ISP_LSC_TABLESIZE_REG (DR_REG_ISP_BASE + 0x54) +/** ISP_LSC_XTABLESIZE : R/W; bitpos: [4:0]; default: 31; + * this field configures lsc table size in x-direction + */ +#define ISP_LSC_XTABLESIZE 0x0000001FU +#define ISP_LSC_XTABLESIZE_M (ISP_LSC_XTABLESIZE_V << ISP_LSC_XTABLESIZE_S) +#define ISP_LSC_XTABLESIZE_V 0x0000001FU +#define ISP_LSC_XTABLESIZE_S 0 + +/** ISP_DEMOSAIC_MATRIX_CTRL_REG register + * demosaic pix2matrix ctrl + */ +#define ISP_DEMOSAIC_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x58) +/** ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and + * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < + * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + */ +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL 0x000000FFU +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_M (ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_V << ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_S) +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_V 0x000000FFU +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TL_S 0 +/** ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and + * reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable + * tail pulse function + */ +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH 0x000000FFU +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_M (ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_V << ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_S) +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_V 0x000000FFU +#define ISP_DEMOSAIC_TAIL_PIXEN_PULSE_TH_S 8 +/** ISP_DEMOSAIC_PADDING_DATA : R/W; bitpos: [23:16]; default: 0; + * this field configures demosaic matrix padding data + */ +#define ISP_DEMOSAIC_PADDING_DATA 0x000000FFU +#define ISP_DEMOSAIC_PADDING_DATA_M (ISP_DEMOSAIC_PADDING_DATA_V << ISP_DEMOSAIC_PADDING_DATA_S) +#define ISP_DEMOSAIC_PADDING_DATA_V 0x000000FFU +#define ISP_DEMOSAIC_PADDING_DATA_S 16 +/** ISP_DEMOSAIC_PADDING_MODE : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of demosaic matrix. 0: use pixel in image to + * do padding 1: use reg_padding_data to do padding + */ +#define ISP_DEMOSAIC_PADDING_MODE (BIT(24)) +#define ISP_DEMOSAIC_PADDING_MODE_M (ISP_DEMOSAIC_PADDING_MODE_V << ISP_DEMOSAIC_PADDING_MODE_S) +#define ISP_DEMOSAIC_PADDING_MODE_V 0x00000001U +#define ISP_DEMOSAIC_PADDING_MODE_S 24 + +/** ISP_DEMOSAIC_GRAD_RATIO_REG register + * demosaic gradient select ratio + */ +#define ISP_DEMOSAIC_GRAD_RATIO_REG (DR_REG_ISP_BASE + 0x5c) +/** ISP_DEMOSAIC_GRAD_RATIO : R/W; bitpos: [5:0]; default: 16; + * this field configures demosaic gradient select ratio + */ +#define ISP_DEMOSAIC_GRAD_RATIO 0x0000003FU +#define ISP_DEMOSAIC_GRAD_RATIO_M (ISP_DEMOSAIC_GRAD_RATIO_V << ISP_DEMOSAIC_GRAD_RATIO_S) +#define ISP_DEMOSAIC_GRAD_RATIO_V 0x0000003FU +#define ISP_DEMOSAIC_GRAD_RATIO_S 0 + +/** ISP_MEDIAN_MATRIX_CTRL_REG register + * median pix2matrix ctrl + */ +#define ISP_MEDIAN_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x60) +/** ISP_MEDIAN_PADDING_DATA : R/W; bitpos: [7:0]; default: 0; + * this field configures median matrix padding data + */ +#define ISP_MEDIAN_PADDING_DATA 0x000000FFU +#define ISP_MEDIAN_PADDING_DATA_M (ISP_MEDIAN_PADDING_DATA_V << ISP_MEDIAN_PADDING_DATA_S) +#define ISP_MEDIAN_PADDING_DATA_V 0x000000FFU +#define ISP_MEDIAN_PADDING_DATA_S 0 +/** ISP_MEDIAN_PADDING_MODE : R/W; bitpos: [8]; default: 0; + * this bit configures the padding mode of median matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ +#define ISP_MEDIAN_PADDING_MODE (BIT(8)) +#define ISP_MEDIAN_PADDING_MODE_M (ISP_MEDIAN_PADDING_MODE_V << ISP_MEDIAN_PADDING_MODE_S) +#define ISP_MEDIAN_PADDING_MODE_V 0x00000001U +#define ISP_MEDIAN_PADDING_MODE_S 8 + +/** ISP_INT_RAW_REG register + * raw interrupt register + */ +#define ISP_INT_RAW_REG (DR_REG_ISP_BASE + 0x64) +/** ISP_ISP_DATA_TYPE_ERR_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * the raw interrupt status of input data type error. isp only support RGB bayer data + * type, other type will report type_err_int + */ +#define ISP_ISP_DATA_TYPE_ERR_INT_RAW (BIT(0)) +#define ISP_ISP_DATA_TYPE_ERR_INT_RAW_M (ISP_ISP_DATA_TYPE_ERR_INT_RAW_V << ISP_ISP_DATA_TYPE_ERR_INT_RAW_S) +#define ISP_ISP_DATA_TYPE_ERR_INT_RAW_V 0x00000001U +#define ISP_ISP_DATA_TYPE_ERR_INT_RAW_S 0 +/** ISP_ISP_ASYNC_FIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * the raw interrupt status of isp input fifo overflow + */ +#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW (BIT(1)) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_M (ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_V << ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_S) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_V 0x00000001U +#define ISP_ISP_ASYNC_FIFO_OVF_INT_RAW_S 1 +/** ISP_ISP_BUF_FULL_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * the raw interrupt status of isp input buffer full + */ +#define ISP_ISP_BUF_FULL_INT_RAW (BIT(2)) +#define ISP_ISP_BUF_FULL_INT_RAW_M (ISP_ISP_BUF_FULL_INT_RAW_V << ISP_ISP_BUF_FULL_INT_RAW_S) +#define ISP_ISP_BUF_FULL_INT_RAW_V 0x00000001U +#define ISP_ISP_BUF_FULL_INT_RAW_S 2 +/** ISP_ISP_HVNUM_SETTING_ERR_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * the raw interrupt status of hnum and vnum setting format error + */ +#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW (BIT(3)) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_M (ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_V << ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_S) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_V 0x00000001U +#define ISP_ISP_HVNUM_SETTING_ERR_INT_RAW_S 3 +/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * the raw interrupt status of setting invalid reg_data_type + */ +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW (BIT(4)) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_M (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_S) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_V 0x00000001U +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_S 4 +/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * the raw interrupt status of hnum setting unmatch with mipi input + */ +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW (BIT(5)) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_M (ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_S) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_V 0x00000001U +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_RAW_S 5 +/** ISP_DPC_CHECK_DONE_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * the raw interrupt status of dpc check done + */ +#define ISP_DPC_CHECK_DONE_INT_RAW (BIT(6)) +#define ISP_DPC_CHECK_DONE_INT_RAW_M (ISP_DPC_CHECK_DONE_INT_RAW_V << ISP_DPC_CHECK_DONE_INT_RAW_S) +#define ISP_DPC_CHECK_DONE_INT_RAW_V 0x00000001U +#define ISP_DPC_CHECK_DONE_INT_RAW_S 6 +/** ISP_GAMMA_XCOORD_ERR_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * the raw interrupt status of gamma setting error. it report the sum of the lengths + * represented by reg_gamma_x00~x0F isn't equal to 256 + */ +#define ISP_GAMMA_XCOORD_ERR_INT_RAW (BIT(7)) +#define ISP_GAMMA_XCOORD_ERR_INT_RAW_M (ISP_GAMMA_XCOORD_ERR_INT_RAW_V << ISP_GAMMA_XCOORD_ERR_INT_RAW_S) +#define ISP_GAMMA_XCOORD_ERR_INT_RAW_V 0x00000001U +#define ISP_GAMMA_XCOORD_ERR_INT_RAW_S 7 +/** ISP_AE_MONITOR_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * the raw interrupt status of ae monitor + */ +#define ISP_AE_MONITOR_INT_RAW (BIT(8)) +#define ISP_AE_MONITOR_INT_RAW_M (ISP_AE_MONITOR_INT_RAW_V << ISP_AE_MONITOR_INT_RAW_S) +#define ISP_AE_MONITOR_INT_RAW_V 0x00000001U +#define ISP_AE_MONITOR_INT_RAW_S 8 +/** ISP_AE_FRAME_DONE_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * the raw interrupt status of ae. + */ +#define ISP_AE_FRAME_DONE_INT_RAW (BIT(9)) +#define ISP_AE_FRAME_DONE_INT_RAW_M (ISP_AE_FRAME_DONE_INT_RAW_V << ISP_AE_FRAME_DONE_INT_RAW_S) +#define ISP_AE_FRAME_DONE_INT_RAW_V 0x00000001U +#define ISP_AE_FRAME_DONE_INT_RAW_S 9 +/** ISP_AF_FDONE_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * the raw interrupt status of af statistic. when auto_update enable, each frame done + * will send one int pulse when manual_update, each time when write 1 to + * reg_manual_update will send a int pulse when next frame done + */ +#define ISP_AF_FDONE_INT_RAW (BIT(10)) +#define ISP_AF_FDONE_INT_RAW_M (ISP_AF_FDONE_INT_RAW_V << ISP_AF_FDONE_INT_RAW_S) +#define ISP_AF_FDONE_INT_RAW_V 0x00000001U +#define ISP_AF_FDONE_INT_RAW_S 10 +/** ISP_AF_ENV_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * the raw interrupt status of af monitor. send a int pulse when env_det function + * enabled and environment changes detected + */ +#define ISP_AF_ENV_INT_RAW (BIT(11)) +#define ISP_AF_ENV_INT_RAW_M (ISP_AF_ENV_INT_RAW_V << ISP_AF_ENV_INT_RAW_S) +#define ISP_AF_ENV_INT_RAW_V 0x00000001U +#define ISP_AF_ENV_INT_RAW_S 11 +/** ISP_AWB_FDONE_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * the raw interrupt status of awb. send a int pulse when statistic of one awb frame + * done + */ +#define ISP_AWB_FDONE_INT_RAW (BIT(12)) +#define ISP_AWB_FDONE_INT_RAW_M (ISP_AWB_FDONE_INT_RAW_V << ISP_AWB_FDONE_INT_RAW_S) +#define ISP_AWB_FDONE_INT_RAW_V 0x00000001U +#define ISP_AWB_FDONE_INT_RAW_S 12 +/** ISP_HIST_FDONE_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * the raw interrupt status of histogram. send a int pulse when statistic of one frame + * histogram done + */ +#define ISP_HIST_FDONE_INT_RAW (BIT(13)) +#define ISP_HIST_FDONE_INT_RAW_M (ISP_HIST_FDONE_INT_RAW_V << ISP_HIST_FDONE_INT_RAW_S) +#define ISP_HIST_FDONE_INT_RAW_V 0x00000001U +#define ISP_HIST_FDONE_INT_RAW_S 13 +/** ISP_FRAME_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * the raw interrupt status of isp frame end + */ +#define ISP_FRAME_INT_RAW (BIT(14)) +#define ISP_FRAME_INT_RAW_M (ISP_FRAME_INT_RAW_V << ISP_FRAME_INT_RAW_S) +#define ISP_FRAME_INT_RAW_V 0x00000001U +#define ISP_FRAME_INT_RAW_S 14 +/** ISP_BLC_FRAME_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * the raw interrupt status of blc frame done + */ +#define ISP_BLC_FRAME_INT_RAW (BIT(15)) +#define ISP_BLC_FRAME_INT_RAW_M (ISP_BLC_FRAME_INT_RAW_V << ISP_BLC_FRAME_INT_RAW_S) +#define ISP_BLC_FRAME_INT_RAW_V 0x00000001U +#define ISP_BLC_FRAME_INT_RAW_S 15 +/** ISP_LSC_FRAME_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * the raw interrupt status of lsc frame done + */ +#define ISP_LSC_FRAME_INT_RAW (BIT(16)) +#define ISP_LSC_FRAME_INT_RAW_M (ISP_LSC_FRAME_INT_RAW_V << ISP_LSC_FRAME_INT_RAW_S) +#define ISP_LSC_FRAME_INT_RAW_V 0x00000001U +#define ISP_LSC_FRAME_INT_RAW_S 16 +/** ISP_DPC_FRAME_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * the raw interrupt status of dpc frame done + */ +#define ISP_DPC_FRAME_INT_RAW (BIT(17)) +#define ISP_DPC_FRAME_INT_RAW_M (ISP_DPC_FRAME_INT_RAW_V << ISP_DPC_FRAME_INT_RAW_S) +#define ISP_DPC_FRAME_INT_RAW_V 0x00000001U +#define ISP_DPC_FRAME_INT_RAW_S 17 +/** ISP_BF_FRAME_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; + * the raw interrupt status of bf frame done + */ +#define ISP_BF_FRAME_INT_RAW (BIT(18)) +#define ISP_BF_FRAME_INT_RAW_M (ISP_BF_FRAME_INT_RAW_V << ISP_BF_FRAME_INT_RAW_S) +#define ISP_BF_FRAME_INT_RAW_V 0x00000001U +#define ISP_BF_FRAME_INT_RAW_S 18 +/** ISP_DEMOSAIC_FRAME_INT_RAW : R/SS/WTC; bitpos: [19]; default: 0; + * the raw interrupt status of demosaic frame done + */ +#define ISP_DEMOSAIC_FRAME_INT_RAW (BIT(19)) +#define ISP_DEMOSAIC_FRAME_INT_RAW_M (ISP_DEMOSAIC_FRAME_INT_RAW_V << ISP_DEMOSAIC_FRAME_INT_RAW_S) +#define ISP_DEMOSAIC_FRAME_INT_RAW_V 0x00000001U +#define ISP_DEMOSAIC_FRAME_INT_RAW_S 19 +/** ISP_MEDIAN_FRAME_INT_RAW : R/SS/WTC; bitpos: [20]; default: 0; + * the raw interrupt status of median frame done + */ +#define ISP_MEDIAN_FRAME_INT_RAW (BIT(20)) +#define ISP_MEDIAN_FRAME_INT_RAW_M (ISP_MEDIAN_FRAME_INT_RAW_V << ISP_MEDIAN_FRAME_INT_RAW_S) +#define ISP_MEDIAN_FRAME_INT_RAW_V 0x00000001U +#define ISP_MEDIAN_FRAME_INT_RAW_S 20 +/** ISP_CCM_FRAME_INT_RAW : R/SS/WTC; bitpos: [21]; default: 0; + * the raw interrupt status of ccm frame done + */ +#define ISP_CCM_FRAME_INT_RAW (BIT(21)) +#define ISP_CCM_FRAME_INT_RAW_M (ISP_CCM_FRAME_INT_RAW_V << ISP_CCM_FRAME_INT_RAW_S) +#define ISP_CCM_FRAME_INT_RAW_V 0x00000001U +#define ISP_CCM_FRAME_INT_RAW_S 21 +/** ISP_GAMMA_FRAME_INT_RAW : R/SS/WTC; bitpos: [22]; default: 0; + * the raw interrupt status of gamma frame done + */ +#define ISP_GAMMA_FRAME_INT_RAW (BIT(22)) +#define ISP_GAMMA_FRAME_INT_RAW_M (ISP_GAMMA_FRAME_INT_RAW_V << ISP_GAMMA_FRAME_INT_RAW_S) +#define ISP_GAMMA_FRAME_INT_RAW_V 0x00000001U +#define ISP_GAMMA_FRAME_INT_RAW_S 22 +/** ISP_RGB2YUV_FRAME_INT_RAW : R/SS/WTC; bitpos: [23]; default: 0; + * the raw interrupt status of rgb2yuv frame done + */ +#define ISP_RGB2YUV_FRAME_INT_RAW (BIT(23)) +#define ISP_RGB2YUV_FRAME_INT_RAW_M (ISP_RGB2YUV_FRAME_INT_RAW_V << ISP_RGB2YUV_FRAME_INT_RAW_S) +#define ISP_RGB2YUV_FRAME_INT_RAW_V 0x00000001U +#define ISP_RGB2YUV_FRAME_INT_RAW_S 23 +/** ISP_SHARP_FRAME_INT_RAW : R/SS/WTC; bitpos: [24]; default: 0; + * the raw interrupt status of sharp frame done + */ +#define ISP_SHARP_FRAME_INT_RAW (BIT(24)) +#define ISP_SHARP_FRAME_INT_RAW_M (ISP_SHARP_FRAME_INT_RAW_V << ISP_SHARP_FRAME_INT_RAW_S) +#define ISP_SHARP_FRAME_INT_RAW_V 0x00000001U +#define ISP_SHARP_FRAME_INT_RAW_S 24 +/** ISP_COLOR_FRAME_INT_RAW : R/SS/WTC; bitpos: [25]; default: 0; + * the raw interrupt status of color frame done + */ +#define ISP_COLOR_FRAME_INT_RAW (BIT(25)) +#define ISP_COLOR_FRAME_INT_RAW_M (ISP_COLOR_FRAME_INT_RAW_V << ISP_COLOR_FRAME_INT_RAW_S) +#define ISP_COLOR_FRAME_INT_RAW_V 0x00000001U +#define ISP_COLOR_FRAME_INT_RAW_S 25 +/** ISP_YUV2RGB_FRAME_INT_RAW : R/SS/WTC; bitpos: [26]; default: 0; + * the raw interrupt status of yuv2rgb frame done + */ +#define ISP_YUV2RGB_FRAME_INT_RAW (BIT(26)) +#define ISP_YUV2RGB_FRAME_INT_RAW_M (ISP_YUV2RGB_FRAME_INT_RAW_V << ISP_YUV2RGB_FRAME_INT_RAW_S) +#define ISP_YUV2RGB_FRAME_INT_RAW_V 0x00000001U +#define ISP_YUV2RGB_FRAME_INT_RAW_S 26 +/** ISP_TAIL_IDI_FRAME_INT_RAW : R/SS/WTC; bitpos: [27]; default: 0; + * the raw interrupt status of isp_tail idi frame_end + */ +#define ISP_TAIL_IDI_FRAME_INT_RAW (BIT(27)) +#define ISP_TAIL_IDI_FRAME_INT_RAW_M (ISP_TAIL_IDI_FRAME_INT_RAW_V << ISP_TAIL_IDI_FRAME_INT_RAW_S) +#define ISP_TAIL_IDI_FRAME_INT_RAW_V 0x00000001U +#define ISP_TAIL_IDI_FRAME_INT_RAW_S 27 +/** ISP_HEADER_IDI_FRAME_INT_RAW : R/SS/WTC; bitpos: [28]; default: 0; + * the raw interrupt status of real input frame end of isp_input + */ +#define ISP_HEADER_IDI_FRAME_INT_RAW (BIT(28)) +#define ISP_HEADER_IDI_FRAME_INT_RAW_M (ISP_HEADER_IDI_FRAME_INT_RAW_V << ISP_HEADER_IDI_FRAME_INT_RAW_S) +#define ISP_HEADER_IDI_FRAME_INT_RAW_V 0x00000001U +#define ISP_HEADER_IDI_FRAME_INT_RAW_S 28 +/** ISP_CROP_FRAME_INT_RAW : R/SS/WTC; bitpos: [29]; default: 0; + * the raw interrupt status of crop frame done + */ +#define ISP_CROP_FRAME_INT_RAW (BIT(29)) +#define ISP_CROP_FRAME_INT_RAW_M (ISP_CROP_FRAME_INT_RAW_V << ISP_CROP_FRAME_INT_RAW_S) +#define ISP_CROP_FRAME_INT_RAW_V 0x00000001U +#define ISP_CROP_FRAME_INT_RAW_S 29 +/** ISP_WBG_FRAME_INT_RAW : R/SS/WTC; bitpos: [30]; default: 0; + * the raw interrupt status of wbg frame done + */ +#define ISP_WBG_FRAME_INT_RAW (BIT(30)) +#define ISP_WBG_FRAME_INT_RAW_M (ISP_WBG_FRAME_INT_RAW_V << ISP_WBG_FRAME_INT_RAW_S) +#define ISP_WBG_FRAME_INT_RAW_V 0x00000001U +#define ISP_WBG_FRAME_INT_RAW_S 30 +/** ISP_CROP_ERR_INT_RAW : R/SS/WTC; bitpos: [31]; default: 0; + * the raw interrupt status of crop error + */ +#define ISP_CROP_ERR_INT_RAW (BIT(31)) +#define ISP_CROP_ERR_INT_RAW_M (ISP_CROP_ERR_INT_RAW_V << ISP_CROP_ERR_INT_RAW_S) +#define ISP_CROP_ERR_INT_RAW_V 0x00000001U +#define ISP_CROP_ERR_INT_RAW_S 31 + +/** ISP_INT_ST_REG register + * masked interrupt register + */ +#define ISP_INT_ST_REG (DR_REG_ISP_BASE + 0x68) +/** ISP_ISP_DATA_TYPE_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * the masked interrupt status of input data type error + */ +#define ISP_ISP_DATA_TYPE_ERR_INT_ST (BIT(0)) +#define ISP_ISP_DATA_TYPE_ERR_INT_ST_M (ISP_ISP_DATA_TYPE_ERR_INT_ST_V << ISP_ISP_DATA_TYPE_ERR_INT_ST_S) +#define ISP_ISP_DATA_TYPE_ERR_INT_ST_V 0x00000001U +#define ISP_ISP_DATA_TYPE_ERR_INT_ST_S 0 +/** ISP_ISP_ASYNC_FIFO_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * the masked interrupt status of isp input fifo overflow + */ +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST (BIT(1)) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST_M (ISP_ISP_ASYNC_FIFO_OVF_INT_ST_V << ISP_ISP_ASYNC_FIFO_OVF_INT_ST_S) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST_V 0x00000001U +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ST_S 1 +/** ISP_ISP_BUF_FULL_INT_ST : RO; bitpos: [2]; default: 0; + * the masked interrupt status of isp input buffer full + */ +#define ISP_ISP_BUF_FULL_INT_ST (BIT(2)) +#define ISP_ISP_BUF_FULL_INT_ST_M (ISP_ISP_BUF_FULL_INT_ST_V << ISP_ISP_BUF_FULL_INT_ST_S) +#define ISP_ISP_BUF_FULL_INT_ST_V 0x00000001U +#define ISP_ISP_BUF_FULL_INT_ST_S 2 +/** ISP_ISP_HVNUM_SETTING_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * the masked interrupt status of hnum and vnum setting format error + */ +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST (BIT(3)) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST_M (ISP_ISP_HVNUM_SETTING_ERR_INT_ST_V << ISP_ISP_HVNUM_SETTING_ERR_INT_ST_S) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST_V 0x00000001U +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ST_S 3 +/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * the masked interrupt status of setting invalid reg_data_type + */ +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST (BIT(4)) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_M (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_S) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_V 0x00000001U +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ST_S 4 +/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST : RO; bitpos: [5]; default: 0; + * the masked interrupt status of hnum setting unmatch with mipi input + */ +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST (BIT(5)) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_M (ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_S) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_V 0x00000001U +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ST_S 5 +/** ISP_DPC_CHECK_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * the masked interrupt status of dpc check done + */ +#define ISP_DPC_CHECK_DONE_INT_ST (BIT(6)) +#define ISP_DPC_CHECK_DONE_INT_ST_M (ISP_DPC_CHECK_DONE_INT_ST_V << ISP_DPC_CHECK_DONE_INT_ST_S) +#define ISP_DPC_CHECK_DONE_INT_ST_V 0x00000001U +#define ISP_DPC_CHECK_DONE_INT_ST_S 6 +/** ISP_GAMMA_XCOORD_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * the masked interrupt status of gamma setting error + */ +#define ISP_GAMMA_XCOORD_ERR_INT_ST (BIT(7)) +#define ISP_GAMMA_XCOORD_ERR_INT_ST_M (ISP_GAMMA_XCOORD_ERR_INT_ST_V << ISP_GAMMA_XCOORD_ERR_INT_ST_S) +#define ISP_GAMMA_XCOORD_ERR_INT_ST_V 0x00000001U +#define ISP_GAMMA_XCOORD_ERR_INT_ST_S 7 +/** ISP_AE_MONITOR_INT_ST : RO; bitpos: [8]; default: 0; + * the masked interrupt status of ae monitor + */ +#define ISP_AE_MONITOR_INT_ST (BIT(8)) +#define ISP_AE_MONITOR_INT_ST_M (ISP_AE_MONITOR_INT_ST_V << ISP_AE_MONITOR_INT_ST_S) +#define ISP_AE_MONITOR_INT_ST_V 0x00000001U +#define ISP_AE_MONITOR_INT_ST_S 8 +/** ISP_AE_FRAME_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * the masked interrupt status of ae + */ +#define ISP_AE_FRAME_DONE_INT_ST (BIT(9)) +#define ISP_AE_FRAME_DONE_INT_ST_M (ISP_AE_FRAME_DONE_INT_ST_V << ISP_AE_FRAME_DONE_INT_ST_S) +#define ISP_AE_FRAME_DONE_INT_ST_V 0x00000001U +#define ISP_AE_FRAME_DONE_INT_ST_S 9 +/** ISP_AF_FDONE_INT_ST : RO; bitpos: [10]; default: 0; + * the masked interrupt status of af statistic + */ +#define ISP_AF_FDONE_INT_ST (BIT(10)) +#define ISP_AF_FDONE_INT_ST_M (ISP_AF_FDONE_INT_ST_V << ISP_AF_FDONE_INT_ST_S) +#define ISP_AF_FDONE_INT_ST_V 0x00000001U +#define ISP_AF_FDONE_INT_ST_S 10 +/** ISP_AF_ENV_INT_ST : RO; bitpos: [11]; default: 0; + * the masked interrupt status of af monitor + */ +#define ISP_AF_ENV_INT_ST (BIT(11)) +#define ISP_AF_ENV_INT_ST_M (ISP_AF_ENV_INT_ST_V << ISP_AF_ENV_INT_ST_S) +#define ISP_AF_ENV_INT_ST_V 0x00000001U +#define ISP_AF_ENV_INT_ST_S 11 +/** ISP_AWB_FDONE_INT_ST : RO; bitpos: [12]; default: 0; + * the masked interrupt status of awb + */ +#define ISP_AWB_FDONE_INT_ST (BIT(12)) +#define ISP_AWB_FDONE_INT_ST_M (ISP_AWB_FDONE_INT_ST_V << ISP_AWB_FDONE_INT_ST_S) +#define ISP_AWB_FDONE_INT_ST_V 0x00000001U +#define ISP_AWB_FDONE_INT_ST_S 12 +/** ISP_HIST_FDONE_INT_ST : RO; bitpos: [13]; default: 0; + * the masked interrupt status of histogram + */ +#define ISP_HIST_FDONE_INT_ST (BIT(13)) +#define ISP_HIST_FDONE_INT_ST_M (ISP_HIST_FDONE_INT_ST_V << ISP_HIST_FDONE_INT_ST_S) +#define ISP_HIST_FDONE_INT_ST_V 0x00000001U +#define ISP_HIST_FDONE_INT_ST_S 13 +/** ISP_FRAME_INT_ST : RO; bitpos: [14]; default: 0; + * the masked interrupt status of isp frame end + */ +#define ISP_FRAME_INT_ST (BIT(14)) +#define ISP_FRAME_INT_ST_M (ISP_FRAME_INT_ST_V << ISP_FRAME_INT_ST_S) +#define ISP_FRAME_INT_ST_V 0x00000001U +#define ISP_FRAME_INT_ST_S 14 +/** ISP_BLC_FRAME_INT_ST : RO; bitpos: [15]; default: 0; + * the masked interrupt status of blc frame done + */ +#define ISP_BLC_FRAME_INT_ST (BIT(15)) +#define ISP_BLC_FRAME_INT_ST_M (ISP_BLC_FRAME_INT_ST_V << ISP_BLC_FRAME_INT_ST_S) +#define ISP_BLC_FRAME_INT_ST_V 0x00000001U +#define ISP_BLC_FRAME_INT_ST_S 15 +/** ISP_LSC_FRAME_INT_ST : RO; bitpos: [16]; default: 0; + * the masked interrupt status of lsc frame done + */ +#define ISP_LSC_FRAME_INT_ST (BIT(16)) +#define ISP_LSC_FRAME_INT_ST_M (ISP_LSC_FRAME_INT_ST_V << ISP_LSC_FRAME_INT_ST_S) +#define ISP_LSC_FRAME_INT_ST_V 0x00000001U +#define ISP_LSC_FRAME_INT_ST_S 16 +/** ISP_DPC_FRAME_INT_ST : RO; bitpos: [17]; default: 0; + * the masked interrupt status of dpc frame done + */ +#define ISP_DPC_FRAME_INT_ST (BIT(17)) +#define ISP_DPC_FRAME_INT_ST_M (ISP_DPC_FRAME_INT_ST_V << ISP_DPC_FRAME_INT_ST_S) +#define ISP_DPC_FRAME_INT_ST_V 0x00000001U +#define ISP_DPC_FRAME_INT_ST_S 17 +/** ISP_BF_FRAME_INT_ST : RO; bitpos: [18]; default: 0; + * the masked interrupt status of bf frame done + */ +#define ISP_BF_FRAME_INT_ST (BIT(18)) +#define ISP_BF_FRAME_INT_ST_M (ISP_BF_FRAME_INT_ST_V << ISP_BF_FRAME_INT_ST_S) +#define ISP_BF_FRAME_INT_ST_V 0x00000001U +#define ISP_BF_FRAME_INT_ST_S 18 +/** ISP_DEMOSAIC_FRAME_INT_ST : RO; bitpos: [19]; default: 0; + * the masked interrupt status of demosaic frame done + */ +#define ISP_DEMOSAIC_FRAME_INT_ST (BIT(19)) +#define ISP_DEMOSAIC_FRAME_INT_ST_M (ISP_DEMOSAIC_FRAME_INT_ST_V << ISP_DEMOSAIC_FRAME_INT_ST_S) +#define ISP_DEMOSAIC_FRAME_INT_ST_V 0x00000001U +#define ISP_DEMOSAIC_FRAME_INT_ST_S 19 +/** ISP_MEDIAN_FRAME_INT_ST : RO; bitpos: [20]; default: 0; + * the masked interrupt status of median frame done + */ +#define ISP_MEDIAN_FRAME_INT_ST (BIT(20)) +#define ISP_MEDIAN_FRAME_INT_ST_M (ISP_MEDIAN_FRAME_INT_ST_V << ISP_MEDIAN_FRAME_INT_ST_S) +#define ISP_MEDIAN_FRAME_INT_ST_V 0x00000001U +#define ISP_MEDIAN_FRAME_INT_ST_S 20 +/** ISP_CCM_FRAME_INT_ST : RO; bitpos: [21]; default: 0; + * the masked interrupt status of ccm frame done + */ +#define ISP_CCM_FRAME_INT_ST (BIT(21)) +#define ISP_CCM_FRAME_INT_ST_M (ISP_CCM_FRAME_INT_ST_V << ISP_CCM_FRAME_INT_ST_S) +#define ISP_CCM_FRAME_INT_ST_V 0x00000001U +#define ISP_CCM_FRAME_INT_ST_S 21 +/** ISP_GAMMA_FRAME_INT_ST : RO; bitpos: [22]; default: 0; + * the masked interrupt status of gamma frame done + */ +#define ISP_GAMMA_FRAME_INT_ST (BIT(22)) +#define ISP_GAMMA_FRAME_INT_ST_M (ISP_GAMMA_FRAME_INT_ST_V << ISP_GAMMA_FRAME_INT_ST_S) +#define ISP_GAMMA_FRAME_INT_ST_V 0x00000001U +#define ISP_GAMMA_FRAME_INT_ST_S 22 +/** ISP_RGB2YUV_FRAME_INT_ST : RO; bitpos: [23]; default: 0; + * the masked interrupt status of rgb2yuv frame done + */ +#define ISP_RGB2YUV_FRAME_INT_ST (BIT(23)) +#define ISP_RGB2YUV_FRAME_INT_ST_M (ISP_RGB2YUV_FRAME_INT_ST_V << ISP_RGB2YUV_FRAME_INT_ST_S) +#define ISP_RGB2YUV_FRAME_INT_ST_V 0x00000001U +#define ISP_RGB2YUV_FRAME_INT_ST_S 23 +/** ISP_SHARP_FRAME_INT_ST : RO; bitpos: [24]; default: 0; + * the masked interrupt status of sharp frame done + */ +#define ISP_SHARP_FRAME_INT_ST (BIT(24)) +#define ISP_SHARP_FRAME_INT_ST_M (ISP_SHARP_FRAME_INT_ST_V << ISP_SHARP_FRAME_INT_ST_S) +#define ISP_SHARP_FRAME_INT_ST_V 0x00000001U +#define ISP_SHARP_FRAME_INT_ST_S 24 +/** ISP_COLOR_FRAME_INT_ST : RO; bitpos: [25]; default: 0; + * the masked interrupt status of color frame done + */ +#define ISP_COLOR_FRAME_INT_ST (BIT(25)) +#define ISP_COLOR_FRAME_INT_ST_M (ISP_COLOR_FRAME_INT_ST_V << ISP_COLOR_FRAME_INT_ST_S) +#define ISP_COLOR_FRAME_INT_ST_V 0x00000001U +#define ISP_COLOR_FRAME_INT_ST_S 25 +/** ISP_YUV2RGB_FRAME_INT_ST : RO; bitpos: [26]; default: 0; + * the masked interrupt status of yuv2rgb frame done + */ +#define ISP_YUV2RGB_FRAME_INT_ST (BIT(26)) +#define ISP_YUV2RGB_FRAME_INT_ST_M (ISP_YUV2RGB_FRAME_INT_ST_V << ISP_YUV2RGB_FRAME_INT_ST_S) +#define ISP_YUV2RGB_FRAME_INT_ST_V 0x00000001U +#define ISP_YUV2RGB_FRAME_INT_ST_S 26 +/** ISP_TAIL_IDI_FRAME_INT_ST : RO; bitpos: [27]; default: 0; + * the masked interrupt status of isp_tail idi frame_end + */ +#define ISP_TAIL_IDI_FRAME_INT_ST (BIT(27)) +#define ISP_TAIL_IDI_FRAME_INT_ST_M (ISP_TAIL_IDI_FRAME_INT_ST_V << ISP_TAIL_IDI_FRAME_INT_ST_S) +#define ISP_TAIL_IDI_FRAME_INT_ST_V 0x00000001U +#define ISP_TAIL_IDI_FRAME_INT_ST_S 27 +/** ISP_HEADER_IDI_FRAME_INT_ST : RO; bitpos: [28]; default: 0; + * the masked interrupt status of real input frame end of isp_input + */ +#define ISP_HEADER_IDI_FRAME_INT_ST (BIT(28)) +#define ISP_HEADER_IDI_FRAME_INT_ST_M (ISP_HEADER_IDI_FRAME_INT_ST_V << ISP_HEADER_IDI_FRAME_INT_ST_S) +#define ISP_HEADER_IDI_FRAME_INT_ST_V 0x00000001U +#define ISP_HEADER_IDI_FRAME_INT_ST_S 28 +/** ISP_CROP_FRAME_INT_ST : RO; bitpos: [29]; default: 0; + * the masked interrupt status of crop frame done + */ +#define ISP_CROP_FRAME_INT_ST (BIT(29)) +#define ISP_CROP_FRAME_INT_ST_M (ISP_CROP_FRAME_INT_ST_V << ISP_CROP_FRAME_INT_ST_S) +#define ISP_CROP_FRAME_INT_ST_V 0x00000001U +#define ISP_CROP_FRAME_INT_ST_S 29 +/** ISP_WBG_FRAME_INT_ST : RO; bitpos: [30]; default: 0; + * the masked interrupt status of wbg frame done + */ +#define ISP_WBG_FRAME_INT_ST (BIT(30)) +#define ISP_WBG_FRAME_INT_ST_M (ISP_WBG_FRAME_INT_ST_V << ISP_WBG_FRAME_INT_ST_S) +#define ISP_WBG_FRAME_INT_ST_V 0x00000001U +#define ISP_WBG_FRAME_INT_ST_S 30 +/** ISP_CROP_ERR_INT_ST : RO; bitpos: [31]; default: 0; + * the masked interrupt status of crop error + */ +#define ISP_CROP_ERR_INT_ST (BIT(31)) +#define ISP_CROP_ERR_INT_ST_M (ISP_CROP_ERR_INT_ST_V << ISP_CROP_ERR_INT_ST_S) +#define ISP_CROP_ERR_INT_ST_V 0x00000001U +#define ISP_CROP_ERR_INT_ST_S 31 + +/** ISP_INT_ENA_REG register + * interrupt enable register + */ +#define ISP_INT_ENA_REG (DR_REG_ISP_BASE + 0x6c) +/** ISP_ISP_DATA_TYPE_ERR_INT_ENA : R/W; bitpos: [0]; default: 1; + * write 1 to enable input data type error + */ +#define ISP_ISP_DATA_TYPE_ERR_INT_ENA (BIT(0)) +#define ISP_ISP_DATA_TYPE_ERR_INT_ENA_M (ISP_ISP_DATA_TYPE_ERR_INT_ENA_V << ISP_ISP_DATA_TYPE_ERR_INT_ENA_S) +#define ISP_ISP_DATA_TYPE_ERR_INT_ENA_V 0x00000001U +#define ISP_ISP_DATA_TYPE_ERR_INT_ENA_S 0 +/** ISP_ISP_ASYNC_FIFO_OVF_INT_ENA : R/W; bitpos: [1]; default: 1; + * write 1 to enable isp input fifo overflow + */ +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA (BIT(1)) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_M (ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_V << ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_S) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_V 0x00000001U +#define ISP_ISP_ASYNC_FIFO_OVF_INT_ENA_S 1 +/** ISP_ISP_BUF_FULL_INT_ENA : R/W; bitpos: [2]; default: 0; + * write 1 to enable isp input buffer full + */ +#define ISP_ISP_BUF_FULL_INT_ENA (BIT(2)) +#define ISP_ISP_BUF_FULL_INT_ENA_M (ISP_ISP_BUF_FULL_INT_ENA_V << ISP_ISP_BUF_FULL_INT_ENA_S) +#define ISP_ISP_BUF_FULL_INT_ENA_V 0x00000001U +#define ISP_ISP_BUF_FULL_INT_ENA_S 2 +/** ISP_ISP_HVNUM_SETTING_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * write 1 to enable hnum and vnum setting format error + */ +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA (BIT(3)) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_M (ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_V << ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_S) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_V 0x00000001U +#define ISP_ISP_HVNUM_SETTING_ERR_INT_ENA_S 3 +/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * write 1 to enable setting invalid reg_data_type + */ +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA (BIT(4)) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_M (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_S) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_V 0x00000001U +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_S 4 +/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA : R/W; bitpos: [5]; default: 0; + * write 1 to enable hnum setting unmatch with mipi input + */ +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA (BIT(5)) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_M (ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_S) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_V 0x00000001U +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_ENA_S 5 +/** ISP_DPC_CHECK_DONE_INT_ENA : R/W; bitpos: [6]; default: 1; + * write 1 to enable dpc check done + */ +#define ISP_DPC_CHECK_DONE_INT_ENA (BIT(6)) +#define ISP_DPC_CHECK_DONE_INT_ENA_M (ISP_DPC_CHECK_DONE_INT_ENA_V << ISP_DPC_CHECK_DONE_INT_ENA_S) +#define ISP_DPC_CHECK_DONE_INT_ENA_V 0x00000001U +#define ISP_DPC_CHECK_DONE_INT_ENA_S 6 +/** ISP_GAMMA_XCOORD_ERR_INT_ENA : R/W; bitpos: [7]; default: 1; + * write 1 to enable gamma setting error + */ +#define ISP_GAMMA_XCOORD_ERR_INT_ENA (BIT(7)) +#define ISP_GAMMA_XCOORD_ERR_INT_ENA_M (ISP_GAMMA_XCOORD_ERR_INT_ENA_V << ISP_GAMMA_XCOORD_ERR_INT_ENA_S) +#define ISP_GAMMA_XCOORD_ERR_INT_ENA_V 0x00000001U +#define ISP_GAMMA_XCOORD_ERR_INT_ENA_S 7 +/** ISP_AE_MONITOR_INT_ENA : R/W; bitpos: [8]; default: 0; + * write 1 to enable ae monitor + */ +#define ISP_AE_MONITOR_INT_ENA (BIT(8)) +#define ISP_AE_MONITOR_INT_ENA_M (ISP_AE_MONITOR_INT_ENA_V << ISP_AE_MONITOR_INT_ENA_S) +#define ISP_AE_MONITOR_INT_ENA_V 0x00000001U +#define ISP_AE_MONITOR_INT_ENA_S 8 +/** ISP_AE_FRAME_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * write 1 to enable ae + */ +#define ISP_AE_FRAME_DONE_INT_ENA (BIT(9)) +#define ISP_AE_FRAME_DONE_INT_ENA_M (ISP_AE_FRAME_DONE_INT_ENA_V << ISP_AE_FRAME_DONE_INT_ENA_S) +#define ISP_AE_FRAME_DONE_INT_ENA_V 0x00000001U +#define ISP_AE_FRAME_DONE_INT_ENA_S 9 +/** ISP_AF_FDONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * write 1 to enable af statistic + */ +#define ISP_AF_FDONE_INT_ENA (BIT(10)) +#define ISP_AF_FDONE_INT_ENA_M (ISP_AF_FDONE_INT_ENA_V << ISP_AF_FDONE_INT_ENA_S) +#define ISP_AF_FDONE_INT_ENA_V 0x00000001U +#define ISP_AF_FDONE_INT_ENA_S 10 +/** ISP_AF_ENV_INT_ENA : R/W; bitpos: [11]; default: 0; + * write 1 to enable af monitor + */ +#define ISP_AF_ENV_INT_ENA (BIT(11)) +#define ISP_AF_ENV_INT_ENA_M (ISP_AF_ENV_INT_ENA_V << ISP_AF_ENV_INT_ENA_S) +#define ISP_AF_ENV_INT_ENA_V 0x00000001U +#define ISP_AF_ENV_INT_ENA_S 11 +/** ISP_AWB_FDONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * write 1 to enable awb + */ +#define ISP_AWB_FDONE_INT_ENA (BIT(12)) +#define ISP_AWB_FDONE_INT_ENA_M (ISP_AWB_FDONE_INT_ENA_V << ISP_AWB_FDONE_INT_ENA_S) +#define ISP_AWB_FDONE_INT_ENA_V 0x00000001U +#define ISP_AWB_FDONE_INT_ENA_S 12 +/** ISP_HIST_FDONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * write 1 to enable histogram + */ +#define ISP_HIST_FDONE_INT_ENA (BIT(13)) +#define ISP_HIST_FDONE_INT_ENA_M (ISP_HIST_FDONE_INT_ENA_V << ISP_HIST_FDONE_INT_ENA_S) +#define ISP_HIST_FDONE_INT_ENA_V 0x00000001U +#define ISP_HIST_FDONE_INT_ENA_S 13 +/** ISP_FRAME_INT_ENA : R/W; bitpos: [14]; default: 0; + * write 1 to enable isp frame end + */ +#define ISP_FRAME_INT_ENA (BIT(14)) +#define ISP_FRAME_INT_ENA_M (ISP_FRAME_INT_ENA_V << ISP_FRAME_INT_ENA_S) +#define ISP_FRAME_INT_ENA_V 0x00000001U +#define ISP_FRAME_INT_ENA_S 14 +/** ISP_BLC_FRAME_INT_ENA : R/W; bitpos: [15]; default: 0; + * write 1 to enable blc frame done + */ +#define ISP_BLC_FRAME_INT_ENA (BIT(15)) +#define ISP_BLC_FRAME_INT_ENA_M (ISP_BLC_FRAME_INT_ENA_V << ISP_BLC_FRAME_INT_ENA_S) +#define ISP_BLC_FRAME_INT_ENA_V 0x00000001U +#define ISP_BLC_FRAME_INT_ENA_S 15 +/** ISP_LSC_FRAME_INT_ENA : R/W; bitpos: [16]; default: 0; + * write 1 to enable lsc frame done + */ +#define ISP_LSC_FRAME_INT_ENA (BIT(16)) +#define ISP_LSC_FRAME_INT_ENA_M (ISP_LSC_FRAME_INT_ENA_V << ISP_LSC_FRAME_INT_ENA_S) +#define ISP_LSC_FRAME_INT_ENA_V 0x00000001U +#define ISP_LSC_FRAME_INT_ENA_S 16 +/** ISP_DPC_FRAME_INT_ENA : R/W; bitpos: [17]; default: 0; + * write 1 to enable dpc frame done + */ +#define ISP_DPC_FRAME_INT_ENA (BIT(17)) +#define ISP_DPC_FRAME_INT_ENA_M (ISP_DPC_FRAME_INT_ENA_V << ISP_DPC_FRAME_INT_ENA_S) +#define ISP_DPC_FRAME_INT_ENA_V 0x00000001U +#define ISP_DPC_FRAME_INT_ENA_S 17 +/** ISP_BF_FRAME_INT_ENA : R/W; bitpos: [18]; default: 0; + * write 1 to enable bf frame done + */ +#define ISP_BF_FRAME_INT_ENA (BIT(18)) +#define ISP_BF_FRAME_INT_ENA_M (ISP_BF_FRAME_INT_ENA_V << ISP_BF_FRAME_INT_ENA_S) +#define ISP_BF_FRAME_INT_ENA_V 0x00000001U +#define ISP_BF_FRAME_INT_ENA_S 18 +/** ISP_DEMOSAIC_FRAME_INT_ENA : R/W; bitpos: [19]; default: 0; + * write 1 to enable demosaic frame done + */ +#define ISP_DEMOSAIC_FRAME_INT_ENA (BIT(19)) +#define ISP_DEMOSAIC_FRAME_INT_ENA_M (ISP_DEMOSAIC_FRAME_INT_ENA_V << ISP_DEMOSAIC_FRAME_INT_ENA_S) +#define ISP_DEMOSAIC_FRAME_INT_ENA_V 0x00000001U +#define ISP_DEMOSAIC_FRAME_INT_ENA_S 19 +/** ISP_MEDIAN_FRAME_INT_ENA : R/W; bitpos: [20]; default: 0; + * write 1 to enable median frame done + */ +#define ISP_MEDIAN_FRAME_INT_ENA (BIT(20)) +#define ISP_MEDIAN_FRAME_INT_ENA_M (ISP_MEDIAN_FRAME_INT_ENA_V << ISP_MEDIAN_FRAME_INT_ENA_S) +#define ISP_MEDIAN_FRAME_INT_ENA_V 0x00000001U +#define ISP_MEDIAN_FRAME_INT_ENA_S 20 +/** ISP_CCM_FRAME_INT_ENA : R/W; bitpos: [21]; default: 0; + * write 1 to enable ccm frame done + */ +#define ISP_CCM_FRAME_INT_ENA (BIT(21)) +#define ISP_CCM_FRAME_INT_ENA_M (ISP_CCM_FRAME_INT_ENA_V << ISP_CCM_FRAME_INT_ENA_S) +#define ISP_CCM_FRAME_INT_ENA_V 0x00000001U +#define ISP_CCM_FRAME_INT_ENA_S 21 +/** ISP_GAMMA_FRAME_INT_ENA : R/W; bitpos: [22]; default: 0; + * write 1 to enable gamma frame done + */ +#define ISP_GAMMA_FRAME_INT_ENA (BIT(22)) +#define ISP_GAMMA_FRAME_INT_ENA_M (ISP_GAMMA_FRAME_INT_ENA_V << ISP_GAMMA_FRAME_INT_ENA_S) +#define ISP_GAMMA_FRAME_INT_ENA_V 0x00000001U +#define ISP_GAMMA_FRAME_INT_ENA_S 22 +/** ISP_RGB2YUV_FRAME_INT_ENA : R/W; bitpos: [23]; default: 0; + * write 1 to enable rgb2yuv frame done + */ +#define ISP_RGB2YUV_FRAME_INT_ENA (BIT(23)) +#define ISP_RGB2YUV_FRAME_INT_ENA_M (ISP_RGB2YUV_FRAME_INT_ENA_V << ISP_RGB2YUV_FRAME_INT_ENA_S) +#define ISP_RGB2YUV_FRAME_INT_ENA_V 0x00000001U +#define ISP_RGB2YUV_FRAME_INT_ENA_S 23 +/** ISP_SHARP_FRAME_INT_ENA : R/W; bitpos: [24]; default: 0; + * write 1 to enable sharp frame done + */ +#define ISP_SHARP_FRAME_INT_ENA (BIT(24)) +#define ISP_SHARP_FRAME_INT_ENA_M (ISP_SHARP_FRAME_INT_ENA_V << ISP_SHARP_FRAME_INT_ENA_S) +#define ISP_SHARP_FRAME_INT_ENA_V 0x00000001U +#define ISP_SHARP_FRAME_INT_ENA_S 24 +/** ISP_COLOR_FRAME_INT_ENA : R/W; bitpos: [25]; default: 0; + * write 1 to enable color frame done + */ +#define ISP_COLOR_FRAME_INT_ENA (BIT(25)) +#define ISP_COLOR_FRAME_INT_ENA_M (ISP_COLOR_FRAME_INT_ENA_V << ISP_COLOR_FRAME_INT_ENA_S) +#define ISP_COLOR_FRAME_INT_ENA_V 0x00000001U +#define ISP_COLOR_FRAME_INT_ENA_S 25 +/** ISP_YUV2RGB_FRAME_INT_ENA : R/W; bitpos: [26]; default: 0; + * write 1 to enable yuv2rgb frame done + */ +#define ISP_YUV2RGB_FRAME_INT_ENA (BIT(26)) +#define ISP_YUV2RGB_FRAME_INT_ENA_M (ISP_YUV2RGB_FRAME_INT_ENA_V << ISP_YUV2RGB_FRAME_INT_ENA_S) +#define ISP_YUV2RGB_FRAME_INT_ENA_V 0x00000001U +#define ISP_YUV2RGB_FRAME_INT_ENA_S 26 +/** ISP_TAIL_IDI_FRAME_INT_ENA : R/W; bitpos: [27]; default: 0; + * write 1 to enable isp_tail idi frame_end + */ +#define ISP_TAIL_IDI_FRAME_INT_ENA (BIT(27)) +#define ISP_TAIL_IDI_FRAME_INT_ENA_M (ISP_TAIL_IDI_FRAME_INT_ENA_V << ISP_TAIL_IDI_FRAME_INT_ENA_S) +#define ISP_TAIL_IDI_FRAME_INT_ENA_V 0x00000001U +#define ISP_TAIL_IDI_FRAME_INT_ENA_S 27 +/** ISP_HEADER_IDI_FRAME_INT_ENA : R/W; bitpos: [28]; default: 0; + * write 1 to enable real input frame end of isp_input + */ +#define ISP_HEADER_IDI_FRAME_INT_ENA (BIT(28)) +#define ISP_HEADER_IDI_FRAME_INT_ENA_M (ISP_HEADER_IDI_FRAME_INT_ENA_V << ISP_HEADER_IDI_FRAME_INT_ENA_S) +#define ISP_HEADER_IDI_FRAME_INT_ENA_V 0x00000001U +#define ISP_HEADER_IDI_FRAME_INT_ENA_S 28 +/** ISP_CROP_FRAME_INT_ENA : R/W; bitpos: [29]; default: 0; + * write 1 to enable crop frame done + */ +#define ISP_CROP_FRAME_INT_ENA (BIT(29)) +#define ISP_CROP_FRAME_INT_ENA_M (ISP_CROP_FRAME_INT_ENA_V << ISP_CROP_FRAME_INT_ENA_S) +#define ISP_CROP_FRAME_INT_ENA_V 0x00000001U +#define ISP_CROP_FRAME_INT_ENA_S 29 +/** ISP_WBG_FRAME_INT_ENA : R/W; bitpos: [30]; default: 0; + * write 1 to enable wbg frame done + */ +#define ISP_WBG_FRAME_INT_ENA (BIT(30)) +#define ISP_WBG_FRAME_INT_ENA_M (ISP_WBG_FRAME_INT_ENA_V << ISP_WBG_FRAME_INT_ENA_S) +#define ISP_WBG_FRAME_INT_ENA_V 0x00000001U +#define ISP_WBG_FRAME_INT_ENA_S 30 +/** ISP_CROP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0; + * write 1 to enable crop error + */ +#define ISP_CROP_ERR_INT_ENA (BIT(31)) +#define ISP_CROP_ERR_INT_ENA_M (ISP_CROP_ERR_INT_ENA_V << ISP_CROP_ERR_INT_ENA_S) +#define ISP_CROP_ERR_INT_ENA_V 0x00000001U +#define ISP_CROP_ERR_INT_ENA_S 31 + +/** ISP_INT_CLR_REG register + * interrupt clear register + */ +#define ISP_INT_CLR_REG (DR_REG_ISP_BASE + 0x70) +/** ISP_ISP_DATA_TYPE_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * write 1 to clear input data type error + */ +#define ISP_ISP_DATA_TYPE_ERR_INT_CLR (BIT(0)) +#define ISP_ISP_DATA_TYPE_ERR_INT_CLR_M (ISP_ISP_DATA_TYPE_ERR_INT_CLR_V << ISP_ISP_DATA_TYPE_ERR_INT_CLR_S) +#define ISP_ISP_DATA_TYPE_ERR_INT_CLR_V 0x00000001U +#define ISP_ISP_DATA_TYPE_ERR_INT_CLR_S 0 +/** ISP_ISP_ASYNC_FIFO_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * write 1 to clear isp input fifo overflow + */ +#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR (BIT(1)) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_M (ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_V << ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_S) +#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_V 0x00000001U +#define ISP_ISP_ASYNC_FIFO_OVF_INT_CLR_S 1 +/** ISP_ISP_BUF_FULL_INT_CLR : WT; bitpos: [2]; default: 0; + * write 1 to clear isp input buffer full + */ +#define ISP_ISP_BUF_FULL_INT_CLR (BIT(2)) +#define ISP_ISP_BUF_FULL_INT_CLR_M (ISP_ISP_BUF_FULL_INT_CLR_V << ISP_ISP_BUF_FULL_INT_CLR_S) +#define ISP_ISP_BUF_FULL_INT_CLR_V 0x00000001U +#define ISP_ISP_BUF_FULL_INT_CLR_S 2 +/** ISP_ISP_HVNUM_SETTING_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * write 1 to clear hnum and vnum setting format error + */ +#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR (BIT(3)) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_M (ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_V << ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_S) +#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_V 0x00000001U +#define ISP_ISP_HVNUM_SETTING_ERR_INT_CLR_S 3 +/** ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * write 1 to clear setting invalid reg_data_type + */ +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR (BIT(4)) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_M (ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_V << ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_S) +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_V 0x00000001U +#define ISP_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_S 4 +/** ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR : WT; bitpos: [5]; default: 0; + * write 1 to clear hnum setting unmatch with mipi input + */ +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR (BIT(5)) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_M (ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_V << ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_S) +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_V 0x00000001U +#define ISP_ISP_MIPI_HNUM_UNMATCH_INT_CLR_S 5 +/** ISP_DPC_CHECK_DONE_INT_CLR : WT; bitpos: [6]; default: 0; + * write 1 to clear dpc check done + */ +#define ISP_DPC_CHECK_DONE_INT_CLR (BIT(6)) +#define ISP_DPC_CHECK_DONE_INT_CLR_M (ISP_DPC_CHECK_DONE_INT_CLR_V << ISP_DPC_CHECK_DONE_INT_CLR_S) +#define ISP_DPC_CHECK_DONE_INT_CLR_V 0x00000001U +#define ISP_DPC_CHECK_DONE_INT_CLR_S 6 +/** ISP_GAMMA_XCOORD_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * write 1 to clear gamma setting error + */ +#define ISP_GAMMA_XCOORD_ERR_INT_CLR (BIT(7)) +#define ISP_GAMMA_XCOORD_ERR_INT_CLR_M (ISP_GAMMA_XCOORD_ERR_INT_CLR_V << ISP_GAMMA_XCOORD_ERR_INT_CLR_S) +#define ISP_GAMMA_XCOORD_ERR_INT_CLR_V 0x00000001U +#define ISP_GAMMA_XCOORD_ERR_INT_CLR_S 7 +/** ISP_AE_MONITOR_INT_CLR : WT; bitpos: [8]; default: 0; + * write 1 to clear ae monitor + */ +#define ISP_AE_MONITOR_INT_CLR (BIT(8)) +#define ISP_AE_MONITOR_INT_CLR_M (ISP_AE_MONITOR_INT_CLR_V << ISP_AE_MONITOR_INT_CLR_S) +#define ISP_AE_MONITOR_INT_CLR_V 0x00000001U +#define ISP_AE_MONITOR_INT_CLR_S 8 +/** ISP_AE_FRAME_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * write 1 to clear ae + */ +#define ISP_AE_FRAME_DONE_INT_CLR (BIT(9)) +#define ISP_AE_FRAME_DONE_INT_CLR_M (ISP_AE_FRAME_DONE_INT_CLR_V << ISP_AE_FRAME_DONE_INT_CLR_S) +#define ISP_AE_FRAME_DONE_INT_CLR_V 0x00000001U +#define ISP_AE_FRAME_DONE_INT_CLR_S 9 +/** ISP_AF_FDONE_INT_CLR : WT; bitpos: [10]; default: 0; + * write 1 to clear af statistic + */ +#define ISP_AF_FDONE_INT_CLR (BIT(10)) +#define ISP_AF_FDONE_INT_CLR_M (ISP_AF_FDONE_INT_CLR_V << ISP_AF_FDONE_INT_CLR_S) +#define ISP_AF_FDONE_INT_CLR_V 0x00000001U +#define ISP_AF_FDONE_INT_CLR_S 10 +/** ISP_AF_ENV_INT_CLR : WT; bitpos: [11]; default: 0; + * write 1 to clear af monitor + */ +#define ISP_AF_ENV_INT_CLR (BIT(11)) +#define ISP_AF_ENV_INT_CLR_M (ISP_AF_ENV_INT_CLR_V << ISP_AF_ENV_INT_CLR_S) +#define ISP_AF_ENV_INT_CLR_V 0x00000001U +#define ISP_AF_ENV_INT_CLR_S 11 +/** ISP_AWB_FDONE_INT_CLR : WT; bitpos: [12]; default: 0; + * write 1 to clear awb + */ +#define ISP_AWB_FDONE_INT_CLR (BIT(12)) +#define ISP_AWB_FDONE_INT_CLR_M (ISP_AWB_FDONE_INT_CLR_V << ISP_AWB_FDONE_INT_CLR_S) +#define ISP_AWB_FDONE_INT_CLR_V 0x00000001U +#define ISP_AWB_FDONE_INT_CLR_S 12 +/** ISP_HIST_FDONE_INT_CLR : WT; bitpos: [13]; default: 0; + * write 1 to clear histogram + */ +#define ISP_HIST_FDONE_INT_CLR (BIT(13)) +#define ISP_HIST_FDONE_INT_CLR_M (ISP_HIST_FDONE_INT_CLR_V << ISP_HIST_FDONE_INT_CLR_S) +#define ISP_HIST_FDONE_INT_CLR_V 0x00000001U +#define ISP_HIST_FDONE_INT_CLR_S 13 +/** ISP_FRAME_INT_CLR : WT; bitpos: [14]; default: 0; + * write 1 to clear isp frame end + */ +#define ISP_FRAME_INT_CLR (BIT(14)) +#define ISP_FRAME_INT_CLR_M (ISP_FRAME_INT_CLR_V << ISP_FRAME_INT_CLR_S) +#define ISP_FRAME_INT_CLR_V 0x00000001U +#define ISP_FRAME_INT_CLR_S 14 +/** ISP_BLC_FRAME_INT_CLR : WT; bitpos: [15]; default: 0; + * write 1 to clear blc frame done + */ +#define ISP_BLC_FRAME_INT_CLR (BIT(15)) +#define ISP_BLC_FRAME_INT_CLR_M (ISP_BLC_FRAME_INT_CLR_V << ISP_BLC_FRAME_INT_CLR_S) +#define ISP_BLC_FRAME_INT_CLR_V 0x00000001U +#define ISP_BLC_FRAME_INT_CLR_S 15 +/** ISP_LSC_FRAME_INT_CLR : WT; bitpos: [16]; default: 0; + * write 1 to clear lsc frame done + */ +#define ISP_LSC_FRAME_INT_CLR (BIT(16)) +#define ISP_LSC_FRAME_INT_CLR_M (ISP_LSC_FRAME_INT_CLR_V << ISP_LSC_FRAME_INT_CLR_S) +#define ISP_LSC_FRAME_INT_CLR_V 0x00000001U +#define ISP_LSC_FRAME_INT_CLR_S 16 +/** ISP_DPC_FRAME_INT_CLR : WT; bitpos: [17]; default: 0; + * write 1 to clear dpc frame done + */ +#define ISP_DPC_FRAME_INT_CLR (BIT(17)) +#define ISP_DPC_FRAME_INT_CLR_M (ISP_DPC_FRAME_INT_CLR_V << ISP_DPC_FRAME_INT_CLR_S) +#define ISP_DPC_FRAME_INT_CLR_V 0x00000001U +#define ISP_DPC_FRAME_INT_CLR_S 17 +/** ISP_BF_FRAME_INT_CLR : WT; bitpos: [18]; default: 0; + * write 1 to clear bf frame done + */ +#define ISP_BF_FRAME_INT_CLR (BIT(18)) +#define ISP_BF_FRAME_INT_CLR_M (ISP_BF_FRAME_INT_CLR_V << ISP_BF_FRAME_INT_CLR_S) +#define ISP_BF_FRAME_INT_CLR_V 0x00000001U +#define ISP_BF_FRAME_INT_CLR_S 18 +/** ISP_DEMOSAIC_FRAME_INT_CLR : WT; bitpos: [19]; default: 0; + * write 1 to clear demosaic frame done + */ +#define ISP_DEMOSAIC_FRAME_INT_CLR (BIT(19)) +#define ISP_DEMOSAIC_FRAME_INT_CLR_M (ISP_DEMOSAIC_FRAME_INT_CLR_V << ISP_DEMOSAIC_FRAME_INT_CLR_S) +#define ISP_DEMOSAIC_FRAME_INT_CLR_V 0x00000001U +#define ISP_DEMOSAIC_FRAME_INT_CLR_S 19 +/** ISP_MEDIAN_FRAME_INT_CLR : WT; bitpos: [20]; default: 0; + * write 1 to clear median frame done + */ +#define ISP_MEDIAN_FRAME_INT_CLR (BIT(20)) +#define ISP_MEDIAN_FRAME_INT_CLR_M (ISP_MEDIAN_FRAME_INT_CLR_V << ISP_MEDIAN_FRAME_INT_CLR_S) +#define ISP_MEDIAN_FRAME_INT_CLR_V 0x00000001U +#define ISP_MEDIAN_FRAME_INT_CLR_S 20 +/** ISP_CCM_FRAME_INT_CLR : WT; bitpos: [21]; default: 0; + * write 1 to clear ccm frame done + */ +#define ISP_CCM_FRAME_INT_CLR (BIT(21)) +#define ISP_CCM_FRAME_INT_CLR_M (ISP_CCM_FRAME_INT_CLR_V << ISP_CCM_FRAME_INT_CLR_S) +#define ISP_CCM_FRAME_INT_CLR_V 0x00000001U +#define ISP_CCM_FRAME_INT_CLR_S 21 +/** ISP_GAMMA_FRAME_INT_CLR : WT; bitpos: [22]; default: 0; + * write 1 to clear gamma frame done + */ +#define ISP_GAMMA_FRAME_INT_CLR (BIT(22)) +#define ISP_GAMMA_FRAME_INT_CLR_M (ISP_GAMMA_FRAME_INT_CLR_V << ISP_GAMMA_FRAME_INT_CLR_S) +#define ISP_GAMMA_FRAME_INT_CLR_V 0x00000001U +#define ISP_GAMMA_FRAME_INT_CLR_S 22 +/** ISP_RGB2YUV_FRAME_INT_CLR : WT; bitpos: [23]; default: 0; + * write 1 to clear rgb2yuv frame done + */ +#define ISP_RGB2YUV_FRAME_INT_CLR (BIT(23)) +#define ISP_RGB2YUV_FRAME_INT_CLR_M (ISP_RGB2YUV_FRAME_INT_CLR_V << ISP_RGB2YUV_FRAME_INT_CLR_S) +#define ISP_RGB2YUV_FRAME_INT_CLR_V 0x00000001U +#define ISP_RGB2YUV_FRAME_INT_CLR_S 23 +/** ISP_SHARP_FRAME_INT_CLR : WT; bitpos: [24]; default: 0; + * write 1 to clear sharp frame done + */ +#define ISP_SHARP_FRAME_INT_CLR (BIT(24)) +#define ISP_SHARP_FRAME_INT_CLR_M (ISP_SHARP_FRAME_INT_CLR_V << ISP_SHARP_FRAME_INT_CLR_S) +#define ISP_SHARP_FRAME_INT_CLR_V 0x00000001U +#define ISP_SHARP_FRAME_INT_CLR_S 24 +/** ISP_COLOR_FRAME_INT_CLR : WT; bitpos: [25]; default: 0; + * write 1 to clear color frame done + */ +#define ISP_COLOR_FRAME_INT_CLR (BIT(25)) +#define ISP_COLOR_FRAME_INT_CLR_M (ISP_COLOR_FRAME_INT_CLR_V << ISP_COLOR_FRAME_INT_CLR_S) +#define ISP_COLOR_FRAME_INT_CLR_V 0x00000001U +#define ISP_COLOR_FRAME_INT_CLR_S 25 +/** ISP_YUV2RGB_FRAME_INT_CLR : WT; bitpos: [26]; default: 0; + * write 1 to clear yuv2rgb frame done + */ +#define ISP_YUV2RGB_FRAME_INT_CLR (BIT(26)) +#define ISP_YUV2RGB_FRAME_INT_CLR_M (ISP_YUV2RGB_FRAME_INT_CLR_V << ISP_YUV2RGB_FRAME_INT_CLR_S) +#define ISP_YUV2RGB_FRAME_INT_CLR_V 0x00000001U +#define ISP_YUV2RGB_FRAME_INT_CLR_S 26 +/** ISP_TAIL_IDI_FRAME_INT_CLR : WT; bitpos: [27]; default: 0; + * write 1 to clear isp_tail idi frame_end + */ +#define ISP_TAIL_IDI_FRAME_INT_CLR (BIT(27)) +#define ISP_TAIL_IDI_FRAME_INT_CLR_M (ISP_TAIL_IDI_FRAME_INT_CLR_V << ISP_TAIL_IDI_FRAME_INT_CLR_S) +#define ISP_TAIL_IDI_FRAME_INT_CLR_V 0x00000001U +#define ISP_TAIL_IDI_FRAME_INT_CLR_S 27 +/** ISP_HEADER_IDI_FRAME_INT_CLR : WT; bitpos: [28]; default: 0; + * write 1 to clear real input frame end of isp_input + */ +#define ISP_HEADER_IDI_FRAME_INT_CLR (BIT(28)) +#define ISP_HEADER_IDI_FRAME_INT_CLR_M (ISP_HEADER_IDI_FRAME_INT_CLR_V << ISP_HEADER_IDI_FRAME_INT_CLR_S) +#define ISP_HEADER_IDI_FRAME_INT_CLR_V 0x00000001U +#define ISP_HEADER_IDI_FRAME_INT_CLR_S 28 +/** ISP_CROP_FRAME_INT_CLR : WT; bitpos: [29]; default: 0; + * write 1 to clear crop frame done + */ +#define ISP_CROP_FRAME_INT_CLR (BIT(29)) +#define ISP_CROP_FRAME_INT_CLR_M (ISP_CROP_FRAME_INT_CLR_V << ISP_CROP_FRAME_INT_CLR_S) +#define ISP_CROP_FRAME_INT_CLR_V 0x00000001U +#define ISP_CROP_FRAME_INT_CLR_S 29 +/** ISP_WBG_FRAME_INT_CLR : WT; bitpos: [30]; default: 0; + * write 1 to clear wbg frame done + */ +#define ISP_WBG_FRAME_INT_CLR (BIT(30)) +#define ISP_WBG_FRAME_INT_CLR_M (ISP_WBG_FRAME_INT_CLR_V << ISP_WBG_FRAME_INT_CLR_S) +#define ISP_WBG_FRAME_INT_CLR_V 0x00000001U +#define ISP_WBG_FRAME_INT_CLR_S 30 +/** ISP_CROP_ERR_INT_CLR : WT; bitpos: [31]; default: 0; + * write 1 to clear crop error + */ +#define ISP_CROP_ERR_INT_CLR (BIT(31)) +#define ISP_CROP_ERR_INT_CLR_M (ISP_CROP_ERR_INT_CLR_V << ISP_CROP_ERR_INT_CLR_S) +#define ISP_CROP_ERR_INT_CLR_V 0x00000001U +#define ISP_CROP_ERR_INT_CLR_S 31 + +/** ISP_GAMMA_CTRL_REG register + * gamma control register + */ +#define ISP_GAMMA_CTRL_REG (DR_REG_ISP_BASE + 0x74) +/** ISP_GAMMA_UPDATE : R/W; bitpos: [0]; default: 0; + * Indicates that gamma register configuration is complete + */ +#define ISP_GAMMA_UPDATE (BIT(0)) +#define ISP_GAMMA_UPDATE_M (ISP_GAMMA_UPDATE_V << ISP_GAMMA_UPDATE_S) +#define ISP_GAMMA_UPDATE_V 0x00000001U +#define ISP_GAMMA_UPDATE_S 0 +/** ISP_GAMMA_B_LAST_CORRECT : R/W; bitpos: [1]; default: 1; + * this bit configures enable of last b segment correcction. 0: disable, 1: enable + */ +#define ISP_GAMMA_B_LAST_CORRECT (BIT(1)) +#define ISP_GAMMA_B_LAST_CORRECT_M (ISP_GAMMA_B_LAST_CORRECT_V << ISP_GAMMA_B_LAST_CORRECT_S) +#define ISP_GAMMA_B_LAST_CORRECT_V 0x00000001U +#define ISP_GAMMA_B_LAST_CORRECT_S 1 +/** ISP_GAMMA_G_LAST_CORRECT : R/W; bitpos: [2]; default: 1; + * this bit configures enable of last g segment correcction. 0: disable, 1: enable + */ +#define ISP_GAMMA_G_LAST_CORRECT (BIT(2)) +#define ISP_GAMMA_G_LAST_CORRECT_M (ISP_GAMMA_G_LAST_CORRECT_V << ISP_GAMMA_G_LAST_CORRECT_S) +#define ISP_GAMMA_G_LAST_CORRECT_V 0x00000001U +#define ISP_GAMMA_G_LAST_CORRECT_S 2 +/** ISP_GAMMA_R_LAST_CORRECT : R/W; bitpos: [3]; default: 1; + * this bit configures enable of last r segment correcction. 0: disable, 1: enable + */ +#define ISP_GAMMA_R_LAST_CORRECT (BIT(3)) +#define ISP_GAMMA_R_LAST_CORRECT_M (ISP_GAMMA_R_LAST_CORRECT_V << ISP_GAMMA_R_LAST_CORRECT_S) +#define ISP_GAMMA_R_LAST_CORRECT_V 0x00000001U +#define ISP_GAMMA_R_LAST_CORRECT_S 3 + +/** ISP_GAMMA_RY1_REG register + * point of Y-axis of r channel gamma curve register 1 + */ +#define ISP_GAMMA_RY1_REG (DR_REG_ISP_BASE + 0x78) +/** ISP_GAMMA_R_Y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y03 0x000000FFU +#define ISP_GAMMA_R_Y03_M (ISP_GAMMA_R_Y03_V << ISP_GAMMA_R_Y03_S) +#define ISP_GAMMA_R_Y03_V 0x000000FFU +#define ISP_GAMMA_R_Y03_S 0 +/** ISP_GAMMA_R_Y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y02 0x000000FFU +#define ISP_GAMMA_R_Y02_M (ISP_GAMMA_R_Y02_V << ISP_GAMMA_R_Y02_S) +#define ISP_GAMMA_R_Y02_V 0x000000FFU +#define ISP_GAMMA_R_Y02_S 8 +/** ISP_GAMMA_R_Y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y01 0x000000FFU +#define ISP_GAMMA_R_Y01_M (ISP_GAMMA_R_Y01_V << ISP_GAMMA_R_Y01_S) +#define ISP_GAMMA_R_Y01_V 0x000000FFU +#define ISP_GAMMA_R_Y01_S 16 +/** ISP_GAMMA_R_Y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y00 0x000000FFU +#define ISP_GAMMA_R_Y00_M (ISP_GAMMA_R_Y00_V << ISP_GAMMA_R_Y00_S) +#define ISP_GAMMA_R_Y00_V 0x000000FFU +#define ISP_GAMMA_R_Y00_S 24 + +/** ISP_GAMMA_RY2_REG register + * point of Y-axis of r channel gamma curve register 2 + */ +#define ISP_GAMMA_RY2_REG (DR_REG_ISP_BASE + 0x7c) +/** ISP_GAMMA_R_Y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y07 0x000000FFU +#define ISP_GAMMA_R_Y07_M (ISP_GAMMA_R_Y07_V << ISP_GAMMA_R_Y07_S) +#define ISP_GAMMA_R_Y07_V 0x000000FFU +#define ISP_GAMMA_R_Y07_S 0 +/** ISP_GAMMA_R_Y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y06 0x000000FFU +#define ISP_GAMMA_R_Y06_M (ISP_GAMMA_R_Y06_V << ISP_GAMMA_R_Y06_S) +#define ISP_GAMMA_R_Y06_V 0x000000FFU +#define ISP_GAMMA_R_Y06_S 8 +/** ISP_GAMMA_R_Y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y05 0x000000FFU +#define ISP_GAMMA_R_Y05_M (ISP_GAMMA_R_Y05_V << ISP_GAMMA_R_Y05_S) +#define ISP_GAMMA_R_Y05_V 0x000000FFU +#define ISP_GAMMA_R_Y05_S 16 +/** ISP_GAMMA_R_Y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y04 0x000000FFU +#define ISP_GAMMA_R_Y04_M (ISP_GAMMA_R_Y04_V << ISP_GAMMA_R_Y04_S) +#define ISP_GAMMA_R_Y04_V 0x000000FFU +#define ISP_GAMMA_R_Y04_S 24 + +/** ISP_GAMMA_RY3_REG register + * point of Y-axis of r channel gamma curve register 3 + */ +#define ISP_GAMMA_RY3_REG (DR_REG_ISP_BASE + 0x80) +/** ISP_GAMMA_R_Y0B : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y0B 0x000000FFU +#define ISP_GAMMA_R_Y0B_M (ISP_GAMMA_R_Y0B_V << ISP_GAMMA_R_Y0B_S) +#define ISP_GAMMA_R_Y0B_V 0x000000FFU +#define ISP_GAMMA_R_Y0B_S 0 +/** ISP_GAMMA_R_Y0A : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y0A 0x000000FFU +#define ISP_GAMMA_R_Y0A_M (ISP_GAMMA_R_Y0A_V << ISP_GAMMA_R_Y0A_S) +#define ISP_GAMMA_R_Y0A_V 0x000000FFU +#define ISP_GAMMA_R_Y0A_S 8 +/** ISP_GAMMA_R_Y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y09 0x000000FFU +#define ISP_GAMMA_R_Y09_M (ISP_GAMMA_R_Y09_V << ISP_GAMMA_R_Y09_S) +#define ISP_GAMMA_R_Y09_V 0x000000FFU +#define ISP_GAMMA_R_Y09_S 16 +/** ISP_GAMMA_R_Y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y08 0x000000FFU +#define ISP_GAMMA_R_Y08_M (ISP_GAMMA_R_Y08_V << ISP_GAMMA_R_Y08_S) +#define ISP_GAMMA_R_Y08_V 0x000000FFU +#define ISP_GAMMA_R_Y08_S 24 + +/** ISP_GAMMA_RY4_REG register + * point of Y-axis of r channel gamma curve register 4 + */ +#define ISP_GAMMA_RY4_REG (DR_REG_ISP_BASE + 0x84) +/** ISP_GAMMA_R_Y0F : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y0F 0x000000FFU +#define ISP_GAMMA_R_Y0F_M (ISP_GAMMA_R_Y0F_V << ISP_GAMMA_R_Y0F_S) +#define ISP_GAMMA_R_Y0F_V 0x000000FFU +#define ISP_GAMMA_R_Y0F_S 0 +/** ISP_GAMMA_R_Y0E : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y0E 0x000000FFU +#define ISP_GAMMA_R_Y0E_M (ISP_GAMMA_R_Y0E_V << ISP_GAMMA_R_Y0E_S) +#define ISP_GAMMA_R_Y0E_V 0x000000FFU +#define ISP_GAMMA_R_Y0E_S 8 +/** ISP_GAMMA_R_Y0D : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y0D 0x000000FFU +#define ISP_GAMMA_R_Y0D_M (ISP_GAMMA_R_Y0D_V << ISP_GAMMA_R_Y0D_S) +#define ISP_GAMMA_R_Y0D_V 0x000000FFU +#define ISP_GAMMA_R_Y0D_S 16 +/** ISP_GAMMA_R_Y0C : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of r channel gamma curve + */ +#define ISP_GAMMA_R_Y0C 0x000000FFU +#define ISP_GAMMA_R_Y0C_M (ISP_GAMMA_R_Y0C_V << ISP_GAMMA_R_Y0C_S) +#define ISP_GAMMA_R_Y0C_V 0x000000FFU +#define ISP_GAMMA_R_Y0C_S 24 + +/** ISP_GAMMA_GY1_REG register + * point of Y-axis of g channel gamma curve register 1 + */ +#define ISP_GAMMA_GY1_REG (DR_REG_ISP_BASE + 0x88) +/** ISP_GAMMA_G_Y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y03 0x000000FFU +#define ISP_GAMMA_G_Y03_M (ISP_GAMMA_G_Y03_V << ISP_GAMMA_G_Y03_S) +#define ISP_GAMMA_G_Y03_V 0x000000FFU +#define ISP_GAMMA_G_Y03_S 0 +/** ISP_GAMMA_G_Y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y02 0x000000FFU +#define ISP_GAMMA_G_Y02_M (ISP_GAMMA_G_Y02_V << ISP_GAMMA_G_Y02_S) +#define ISP_GAMMA_G_Y02_V 0x000000FFU +#define ISP_GAMMA_G_Y02_S 8 +/** ISP_GAMMA_G_Y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y01 0x000000FFU +#define ISP_GAMMA_G_Y01_M (ISP_GAMMA_G_Y01_V << ISP_GAMMA_G_Y01_S) +#define ISP_GAMMA_G_Y01_V 0x000000FFU +#define ISP_GAMMA_G_Y01_S 16 +/** ISP_GAMMA_G_Y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y00 0x000000FFU +#define ISP_GAMMA_G_Y00_M (ISP_GAMMA_G_Y00_V << ISP_GAMMA_G_Y00_S) +#define ISP_GAMMA_G_Y00_V 0x000000FFU +#define ISP_GAMMA_G_Y00_S 24 + +/** ISP_GAMMA_GY2_REG register + * point of Y-axis of g channel gamma curve register 2 + */ +#define ISP_GAMMA_GY2_REG (DR_REG_ISP_BASE + 0x8c) +/** ISP_GAMMA_G_Y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y07 0x000000FFU +#define ISP_GAMMA_G_Y07_M (ISP_GAMMA_G_Y07_V << ISP_GAMMA_G_Y07_S) +#define ISP_GAMMA_G_Y07_V 0x000000FFU +#define ISP_GAMMA_G_Y07_S 0 +/** ISP_GAMMA_G_Y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y06 0x000000FFU +#define ISP_GAMMA_G_Y06_M (ISP_GAMMA_G_Y06_V << ISP_GAMMA_G_Y06_S) +#define ISP_GAMMA_G_Y06_V 0x000000FFU +#define ISP_GAMMA_G_Y06_S 8 +/** ISP_GAMMA_G_Y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y05 0x000000FFU +#define ISP_GAMMA_G_Y05_M (ISP_GAMMA_G_Y05_V << ISP_GAMMA_G_Y05_S) +#define ISP_GAMMA_G_Y05_V 0x000000FFU +#define ISP_GAMMA_G_Y05_S 16 +/** ISP_GAMMA_G_Y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y04 0x000000FFU +#define ISP_GAMMA_G_Y04_M (ISP_GAMMA_G_Y04_V << ISP_GAMMA_G_Y04_S) +#define ISP_GAMMA_G_Y04_V 0x000000FFU +#define ISP_GAMMA_G_Y04_S 24 + +/** ISP_GAMMA_GY3_REG register + * point of Y-axis of g channel gamma curve register 3 + */ +#define ISP_GAMMA_GY3_REG (DR_REG_ISP_BASE + 0x90) +/** ISP_GAMMA_G_Y0B : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y0B 0x000000FFU +#define ISP_GAMMA_G_Y0B_M (ISP_GAMMA_G_Y0B_V << ISP_GAMMA_G_Y0B_S) +#define ISP_GAMMA_G_Y0B_V 0x000000FFU +#define ISP_GAMMA_G_Y0B_S 0 +/** ISP_GAMMA_G_Y0A : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y0A 0x000000FFU +#define ISP_GAMMA_G_Y0A_M (ISP_GAMMA_G_Y0A_V << ISP_GAMMA_G_Y0A_S) +#define ISP_GAMMA_G_Y0A_V 0x000000FFU +#define ISP_GAMMA_G_Y0A_S 8 +/** ISP_GAMMA_G_Y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y09 0x000000FFU +#define ISP_GAMMA_G_Y09_M (ISP_GAMMA_G_Y09_V << ISP_GAMMA_G_Y09_S) +#define ISP_GAMMA_G_Y09_V 0x000000FFU +#define ISP_GAMMA_G_Y09_S 16 +/** ISP_GAMMA_G_Y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y08 0x000000FFU +#define ISP_GAMMA_G_Y08_M (ISP_GAMMA_G_Y08_V << ISP_GAMMA_G_Y08_S) +#define ISP_GAMMA_G_Y08_V 0x000000FFU +#define ISP_GAMMA_G_Y08_S 24 + +/** ISP_GAMMA_GY4_REG register + * point of Y-axis of g channel gamma curve register 4 + */ +#define ISP_GAMMA_GY4_REG (DR_REG_ISP_BASE + 0x94) +/** ISP_GAMMA_G_Y0F : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y0F 0x000000FFU +#define ISP_GAMMA_G_Y0F_M (ISP_GAMMA_G_Y0F_V << ISP_GAMMA_G_Y0F_S) +#define ISP_GAMMA_G_Y0F_V 0x000000FFU +#define ISP_GAMMA_G_Y0F_S 0 +/** ISP_GAMMA_G_Y0E : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y0E 0x000000FFU +#define ISP_GAMMA_G_Y0E_M (ISP_GAMMA_G_Y0E_V << ISP_GAMMA_G_Y0E_S) +#define ISP_GAMMA_G_Y0E_V 0x000000FFU +#define ISP_GAMMA_G_Y0E_S 8 +/** ISP_GAMMA_G_Y0D : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y0D 0x000000FFU +#define ISP_GAMMA_G_Y0D_M (ISP_GAMMA_G_Y0D_V << ISP_GAMMA_G_Y0D_S) +#define ISP_GAMMA_G_Y0D_V 0x000000FFU +#define ISP_GAMMA_G_Y0D_S 16 +/** ISP_GAMMA_G_Y0C : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of g channel gamma curve + */ +#define ISP_GAMMA_G_Y0C 0x000000FFU +#define ISP_GAMMA_G_Y0C_M (ISP_GAMMA_G_Y0C_V << ISP_GAMMA_G_Y0C_S) +#define ISP_GAMMA_G_Y0C_V 0x000000FFU +#define ISP_GAMMA_G_Y0C_S 24 + +/** ISP_GAMMA_BY1_REG register + * point of Y-axis of b channel gamma curve register 1 + */ +#define ISP_GAMMA_BY1_REG (DR_REG_ISP_BASE + 0x98) +/** ISP_GAMMA_B_Y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y03 0x000000FFU +#define ISP_GAMMA_B_Y03_M (ISP_GAMMA_B_Y03_V << ISP_GAMMA_B_Y03_S) +#define ISP_GAMMA_B_Y03_V 0x000000FFU +#define ISP_GAMMA_B_Y03_S 0 +/** ISP_GAMMA_B_Y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y02 0x000000FFU +#define ISP_GAMMA_B_Y02_M (ISP_GAMMA_B_Y02_V << ISP_GAMMA_B_Y02_S) +#define ISP_GAMMA_B_Y02_V 0x000000FFU +#define ISP_GAMMA_B_Y02_S 8 +/** ISP_GAMMA_B_Y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y01 0x000000FFU +#define ISP_GAMMA_B_Y01_M (ISP_GAMMA_B_Y01_V << ISP_GAMMA_B_Y01_S) +#define ISP_GAMMA_B_Y01_V 0x000000FFU +#define ISP_GAMMA_B_Y01_S 16 +/** ISP_GAMMA_B_Y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y00 0x000000FFU +#define ISP_GAMMA_B_Y00_M (ISP_GAMMA_B_Y00_V << ISP_GAMMA_B_Y00_S) +#define ISP_GAMMA_B_Y00_V 0x000000FFU +#define ISP_GAMMA_B_Y00_S 24 + +/** ISP_GAMMA_BY2_REG register + * point of Y-axis of b channel gamma curve register 2 + */ +#define ISP_GAMMA_BY2_REG (DR_REG_ISP_BASE + 0x9c) +/** ISP_GAMMA_B_Y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y07 0x000000FFU +#define ISP_GAMMA_B_Y07_M (ISP_GAMMA_B_Y07_V << ISP_GAMMA_B_Y07_S) +#define ISP_GAMMA_B_Y07_V 0x000000FFU +#define ISP_GAMMA_B_Y07_S 0 +/** ISP_GAMMA_B_Y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y06 0x000000FFU +#define ISP_GAMMA_B_Y06_M (ISP_GAMMA_B_Y06_V << ISP_GAMMA_B_Y06_S) +#define ISP_GAMMA_B_Y06_V 0x000000FFU +#define ISP_GAMMA_B_Y06_S 8 +/** ISP_GAMMA_B_Y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y05 0x000000FFU +#define ISP_GAMMA_B_Y05_M (ISP_GAMMA_B_Y05_V << ISP_GAMMA_B_Y05_S) +#define ISP_GAMMA_B_Y05_V 0x000000FFU +#define ISP_GAMMA_B_Y05_S 16 +/** ISP_GAMMA_B_Y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y04 0x000000FFU +#define ISP_GAMMA_B_Y04_M (ISP_GAMMA_B_Y04_V << ISP_GAMMA_B_Y04_S) +#define ISP_GAMMA_B_Y04_V 0x000000FFU +#define ISP_GAMMA_B_Y04_S 24 + +/** ISP_GAMMA_BY3_REG register + * point of Y-axis of b channel gamma curve register 3 + */ +#define ISP_GAMMA_BY3_REG (DR_REG_ISP_BASE + 0xa0) +/** ISP_GAMMA_B_Y0B : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y0B 0x000000FFU +#define ISP_GAMMA_B_Y0B_M (ISP_GAMMA_B_Y0B_V << ISP_GAMMA_B_Y0B_S) +#define ISP_GAMMA_B_Y0B_V 0x000000FFU +#define ISP_GAMMA_B_Y0B_S 0 +/** ISP_GAMMA_B_Y0A : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y0A 0x000000FFU +#define ISP_GAMMA_B_Y0A_M (ISP_GAMMA_B_Y0A_V << ISP_GAMMA_B_Y0A_S) +#define ISP_GAMMA_B_Y0A_V 0x000000FFU +#define ISP_GAMMA_B_Y0A_S 8 +/** ISP_GAMMA_B_Y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y09 0x000000FFU +#define ISP_GAMMA_B_Y09_M (ISP_GAMMA_B_Y09_V << ISP_GAMMA_B_Y09_S) +#define ISP_GAMMA_B_Y09_V 0x000000FFU +#define ISP_GAMMA_B_Y09_S 16 +/** ISP_GAMMA_B_Y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y08 0x000000FFU +#define ISP_GAMMA_B_Y08_M (ISP_GAMMA_B_Y08_V << ISP_GAMMA_B_Y08_S) +#define ISP_GAMMA_B_Y08_V 0x000000FFU +#define ISP_GAMMA_B_Y08_S 24 + +/** ISP_GAMMA_BY4_REG register + * point of Y-axis of b channel gamma curve register 4 + */ +#define ISP_GAMMA_BY4_REG (DR_REG_ISP_BASE + 0xa4) +/** ISP_GAMMA_B_Y0F : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y0F 0x000000FFU +#define ISP_GAMMA_B_Y0F_M (ISP_GAMMA_B_Y0F_V << ISP_GAMMA_B_Y0F_S) +#define ISP_GAMMA_B_Y0F_V 0x000000FFU +#define ISP_GAMMA_B_Y0F_S 0 +/** ISP_GAMMA_B_Y0E : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y0E 0x000000FFU +#define ISP_GAMMA_B_Y0E_M (ISP_GAMMA_B_Y0E_V << ISP_GAMMA_B_Y0E_S) +#define ISP_GAMMA_B_Y0E_V 0x000000FFU +#define ISP_GAMMA_B_Y0E_S 8 +/** ISP_GAMMA_B_Y0D : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y0D 0x000000FFU +#define ISP_GAMMA_B_Y0D_M (ISP_GAMMA_B_Y0D_V << ISP_GAMMA_B_Y0D_S) +#define ISP_GAMMA_B_Y0D_V 0x000000FFU +#define ISP_GAMMA_B_Y0D_S 16 +/** ISP_GAMMA_B_Y0C : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of b channel gamma curve + */ +#define ISP_GAMMA_B_Y0C 0x000000FFU +#define ISP_GAMMA_B_Y0C_M (ISP_GAMMA_B_Y0C_V << ISP_GAMMA_B_Y0C_S) +#define ISP_GAMMA_B_Y0C_V 0x000000FFU +#define ISP_GAMMA_B_Y0C_S 24 + +/** ISP_GAMMA_RX1_REG register + * point of X-axis of r channel gamma curve register 1 + */ +#define ISP_GAMMA_RX1_REG (DR_REG_ISP_BASE + 0xa8) +/** ISP_GAMMA_R_X07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X07 0x00000007U +#define ISP_GAMMA_R_X07_M (ISP_GAMMA_R_X07_V << ISP_GAMMA_R_X07_S) +#define ISP_GAMMA_R_X07_V 0x00000007U +#define ISP_GAMMA_R_X07_S 0 +/** ISP_GAMMA_R_X06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X06 0x00000007U +#define ISP_GAMMA_R_X06_M (ISP_GAMMA_R_X06_V << ISP_GAMMA_R_X06_S) +#define ISP_GAMMA_R_X06_V 0x00000007U +#define ISP_GAMMA_R_X06_S 3 +/** ISP_GAMMA_R_X05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X05 0x00000007U +#define ISP_GAMMA_R_X05_M (ISP_GAMMA_R_X05_V << ISP_GAMMA_R_X05_S) +#define ISP_GAMMA_R_X05_V 0x00000007U +#define ISP_GAMMA_R_X05_S 6 +/** ISP_GAMMA_R_X04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X04 0x00000007U +#define ISP_GAMMA_R_X04_M (ISP_GAMMA_R_X04_V << ISP_GAMMA_R_X04_S) +#define ISP_GAMMA_R_X04_V 0x00000007U +#define ISP_GAMMA_R_X04_S 9 +/** ISP_GAMMA_R_X03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X03 0x00000007U +#define ISP_GAMMA_R_X03_M (ISP_GAMMA_R_X03_V << ISP_GAMMA_R_X03_S) +#define ISP_GAMMA_R_X03_V 0x00000007U +#define ISP_GAMMA_R_X03_S 12 +/** ISP_GAMMA_R_X02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X02 0x00000007U +#define ISP_GAMMA_R_X02_M (ISP_GAMMA_R_X02_V << ISP_GAMMA_R_X02_S) +#define ISP_GAMMA_R_X02_V 0x00000007U +#define ISP_GAMMA_R_X02_S 15 +/** ISP_GAMMA_R_X01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X01 0x00000007U +#define ISP_GAMMA_R_X01_M (ISP_GAMMA_R_X01_V << ISP_GAMMA_R_X01_S) +#define ISP_GAMMA_R_X01_V 0x00000007U +#define ISP_GAMMA_R_X01_S 18 +/** ISP_GAMMA_R_X00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X00 0x00000007U +#define ISP_GAMMA_R_X00_M (ISP_GAMMA_R_X00_V << ISP_GAMMA_R_X00_S) +#define ISP_GAMMA_R_X00_V 0x00000007U +#define ISP_GAMMA_R_X00_S 21 + +/** ISP_GAMMA_RX2_REG register + * point of X-axis of r channel gamma curve register 2 + */ +#define ISP_GAMMA_RX2_REG (DR_REG_ISP_BASE + 0xac) +/** ISP_GAMMA_R_X0F : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X0F 0x00000007U +#define ISP_GAMMA_R_X0F_M (ISP_GAMMA_R_X0F_V << ISP_GAMMA_R_X0F_S) +#define ISP_GAMMA_R_X0F_V 0x00000007U +#define ISP_GAMMA_R_X0F_S 0 +/** ISP_GAMMA_R_X0E : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X0E 0x00000007U +#define ISP_GAMMA_R_X0E_M (ISP_GAMMA_R_X0E_V << ISP_GAMMA_R_X0E_S) +#define ISP_GAMMA_R_X0E_V 0x00000007U +#define ISP_GAMMA_R_X0E_S 3 +/** ISP_GAMMA_R_X0D : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X0D 0x00000007U +#define ISP_GAMMA_R_X0D_M (ISP_GAMMA_R_X0D_V << ISP_GAMMA_R_X0D_S) +#define ISP_GAMMA_R_X0D_V 0x00000007U +#define ISP_GAMMA_R_X0D_S 6 +/** ISP_GAMMA_R_X0C : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X0C 0x00000007U +#define ISP_GAMMA_R_X0C_M (ISP_GAMMA_R_X0C_V << ISP_GAMMA_R_X0C_S) +#define ISP_GAMMA_R_X0C_V 0x00000007U +#define ISP_GAMMA_R_X0C_S 9 +/** ISP_GAMMA_R_X0B : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X0B 0x00000007U +#define ISP_GAMMA_R_X0B_M (ISP_GAMMA_R_X0B_V << ISP_GAMMA_R_X0B_S) +#define ISP_GAMMA_R_X0B_V 0x00000007U +#define ISP_GAMMA_R_X0B_S 12 +/** ISP_GAMMA_R_X0A : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of r channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X0A 0x00000007U +#define ISP_GAMMA_R_X0A_M (ISP_GAMMA_R_X0A_V << ISP_GAMMA_R_X0A_S) +#define ISP_GAMMA_R_X0A_V 0x00000007U +#define ISP_GAMMA_R_X0A_S 15 +/** ISP_GAMMA_R_X09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X09 0x00000007U +#define ISP_GAMMA_R_X09_M (ISP_GAMMA_R_X09_V << ISP_GAMMA_R_X09_S) +#define ISP_GAMMA_R_X09_V 0x00000007U +#define ISP_GAMMA_R_X09_S 18 +/** ISP_GAMMA_R_X08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of r channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_R_X08 0x00000007U +#define ISP_GAMMA_R_X08_M (ISP_GAMMA_R_X08_V << ISP_GAMMA_R_X08_S) +#define ISP_GAMMA_R_X08_V 0x00000007U +#define ISP_GAMMA_R_X08_S 21 + +/** ISP_GAMMA_GX1_REG register + * point of X-axis of g channel gamma curve register 1 + */ +#define ISP_GAMMA_GX1_REG (DR_REG_ISP_BASE + 0xb0) +/** ISP_GAMMA_G_X07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X07 0x00000007U +#define ISP_GAMMA_G_X07_M (ISP_GAMMA_G_X07_V << ISP_GAMMA_G_X07_S) +#define ISP_GAMMA_G_X07_V 0x00000007U +#define ISP_GAMMA_G_X07_S 0 +/** ISP_GAMMA_G_X06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X06 0x00000007U +#define ISP_GAMMA_G_X06_M (ISP_GAMMA_G_X06_V << ISP_GAMMA_G_X06_S) +#define ISP_GAMMA_G_X06_V 0x00000007U +#define ISP_GAMMA_G_X06_S 3 +/** ISP_GAMMA_G_X05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X05 0x00000007U +#define ISP_GAMMA_G_X05_M (ISP_GAMMA_G_X05_V << ISP_GAMMA_G_X05_S) +#define ISP_GAMMA_G_X05_V 0x00000007U +#define ISP_GAMMA_G_X05_S 6 +/** ISP_GAMMA_G_X04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X04 0x00000007U +#define ISP_GAMMA_G_X04_M (ISP_GAMMA_G_X04_V << ISP_GAMMA_G_X04_S) +#define ISP_GAMMA_G_X04_V 0x00000007U +#define ISP_GAMMA_G_X04_S 9 +/** ISP_GAMMA_G_X03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X03 0x00000007U +#define ISP_GAMMA_G_X03_M (ISP_GAMMA_G_X03_V << ISP_GAMMA_G_X03_S) +#define ISP_GAMMA_G_X03_V 0x00000007U +#define ISP_GAMMA_G_X03_S 12 +/** ISP_GAMMA_G_X02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X02 0x00000007U +#define ISP_GAMMA_G_X02_M (ISP_GAMMA_G_X02_V << ISP_GAMMA_G_X02_S) +#define ISP_GAMMA_G_X02_V 0x00000007U +#define ISP_GAMMA_G_X02_S 15 +/** ISP_GAMMA_G_X01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X01 0x00000007U +#define ISP_GAMMA_G_X01_M (ISP_GAMMA_G_X01_V << ISP_GAMMA_G_X01_S) +#define ISP_GAMMA_G_X01_V 0x00000007U +#define ISP_GAMMA_G_X01_S 18 +/** ISP_GAMMA_G_X00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X00 0x00000007U +#define ISP_GAMMA_G_X00_M (ISP_GAMMA_G_X00_V << ISP_GAMMA_G_X00_S) +#define ISP_GAMMA_G_X00_V 0x00000007U +#define ISP_GAMMA_G_X00_S 21 + +/** ISP_GAMMA_GX2_REG register + * point of X-axis of g channel gamma curve register 2 + */ +#define ISP_GAMMA_GX2_REG (DR_REG_ISP_BASE + 0xb4) +/** ISP_GAMMA_G_X0F : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X0F 0x00000007U +#define ISP_GAMMA_G_X0F_M (ISP_GAMMA_G_X0F_V << ISP_GAMMA_G_X0F_S) +#define ISP_GAMMA_G_X0F_V 0x00000007U +#define ISP_GAMMA_G_X0F_S 0 +/** ISP_GAMMA_G_X0E : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X0E 0x00000007U +#define ISP_GAMMA_G_X0E_M (ISP_GAMMA_G_X0E_V << ISP_GAMMA_G_X0E_S) +#define ISP_GAMMA_G_X0E_V 0x00000007U +#define ISP_GAMMA_G_X0E_S 3 +/** ISP_GAMMA_G_X0D : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X0D 0x00000007U +#define ISP_GAMMA_G_X0D_M (ISP_GAMMA_G_X0D_V << ISP_GAMMA_G_X0D_S) +#define ISP_GAMMA_G_X0D_V 0x00000007U +#define ISP_GAMMA_G_X0D_S 6 +/** ISP_GAMMA_G_X0C : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X0C 0x00000007U +#define ISP_GAMMA_G_X0C_M (ISP_GAMMA_G_X0C_V << ISP_GAMMA_G_X0C_S) +#define ISP_GAMMA_G_X0C_V 0x00000007U +#define ISP_GAMMA_G_X0C_S 9 +/** ISP_GAMMA_G_X0B : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X0B 0x00000007U +#define ISP_GAMMA_G_X0B_M (ISP_GAMMA_G_X0B_V << ISP_GAMMA_G_X0B_S) +#define ISP_GAMMA_G_X0B_V 0x00000007U +#define ISP_GAMMA_G_X0B_S 12 +/** ISP_GAMMA_G_X0A : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of g channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X0A 0x00000007U +#define ISP_GAMMA_G_X0A_M (ISP_GAMMA_G_X0A_V << ISP_GAMMA_G_X0A_S) +#define ISP_GAMMA_G_X0A_V 0x00000007U +#define ISP_GAMMA_G_X0A_S 15 +/** ISP_GAMMA_G_X09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X09 0x00000007U +#define ISP_GAMMA_G_X09_M (ISP_GAMMA_G_X09_V << ISP_GAMMA_G_X09_S) +#define ISP_GAMMA_G_X09_V 0x00000007U +#define ISP_GAMMA_G_X09_S 18 +/** ISP_GAMMA_G_X08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of g channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_G_X08 0x00000007U +#define ISP_GAMMA_G_X08_M (ISP_GAMMA_G_X08_V << ISP_GAMMA_G_X08_S) +#define ISP_GAMMA_G_X08_V 0x00000007U +#define ISP_GAMMA_G_X08_S 21 + +/** ISP_GAMMA_BX1_REG register + * point of X-axis of b channel gamma curve register 1 + */ +#define ISP_GAMMA_BX1_REG (DR_REG_ISP_BASE + 0xb8) +/** ISP_GAMMA_B_X07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X07 0x00000007U +#define ISP_GAMMA_B_X07_M (ISP_GAMMA_B_X07_V << ISP_GAMMA_B_X07_S) +#define ISP_GAMMA_B_X07_V 0x00000007U +#define ISP_GAMMA_B_X07_S 0 +/** ISP_GAMMA_B_X06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X06 0x00000007U +#define ISP_GAMMA_B_X06_M (ISP_GAMMA_B_X06_V << ISP_GAMMA_B_X06_S) +#define ISP_GAMMA_B_X06_V 0x00000007U +#define ISP_GAMMA_B_X06_S 3 +/** ISP_GAMMA_B_X05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X05 0x00000007U +#define ISP_GAMMA_B_X05_M (ISP_GAMMA_B_X05_V << ISP_GAMMA_B_X05_S) +#define ISP_GAMMA_B_X05_V 0x00000007U +#define ISP_GAMMA_B_X05_S 6 +/** ISP_GAMMA_B_X04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X04 0x00000007U +#define ISP_GAMMA_B_X04_M (ISP_GAMMA_B_X04_V << ISP_GAMMA_B_X04_S) +#define ISP_GAMMA_B_X04_V 0x00000007U +#define ISP_GAMMA_B_X04_S 9 +/** ISP_GAMMA_B_X03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X03 0x00000007U +#define ISP_GAMMA_B_X03_M (ISP_GAMMA_B_X03_V << ISP_GAMMA_B_X03_S) +#define ISP_GAMMA_B_X03_V 0x00000007U +#define ISP_GAMMA_B_X03_S 12 +/** ISP_GAMMA_B_X02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X02 0x00000007U +#define ISP_GAMMA_B_X02_M (ISP_GAMMA_B_X02_V << ISP_GAMMA_B_X02_S) +#define ISP_GAMMA_B_X02_V 0x00000007U +#define ISP_GAMMA_B_X02_S 15 +/** ISP_GAMMA_B_X01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X01 0x00000007U +#define ISP_GAMMA_B_X01_M (ISP_GAMMA_B_X01_V << ISP_GAMMA_B_X01_S) +#define ISP_GAMMA_B_X01_V 0x00000007U +#define ISP_GAMMA_B_X01_S 18 +/** ISP_GAMMA_B_X00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X00 0x00000007U +#define ISP_GAMMA_B_X00_M (ISP_GAMMA_B_X00_V << ISP_GAMMA_B_X00_S) +#define ISP_GAMMA_B_X00_V 0x00000007U +#define ISP_GAMMA_B_X00_S 21 + +/** ISP_GAMMA_BX2_REG register + * point of X-axis of b channel gamma curve register 2 + */ +#define ISP_GAMMA_BX2_REG (DR_REG_ISP_BASE + 0xbc) +/** ISP_GAMMA_B_X0F : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X0F 0x00000007U +#define ISP_GAMMA_B_X0F_M (ISP_GAMMA_B_X0F_V << ISP_GAMMA_B_X0F_S) +#define ISP_GAMMA_B_X0F_V 0x00000007U +#define ISP_GAMMA_B_X0F_S 0 +/** ISP_GAMMA_B_X0E : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X0E 0x00000007U +#define ISP_GAMMA_B_X0E_M (ISP_GAMMA_B_X0E_V << ISP_GAMMA_B_X0E_S) +#define ISP_GAMMA_B_X0E_V 0x00000007U +#define ISP_GAMMA_B_X0E_S 3 +/** ISP_GAMMA_B_X0D : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X0D 0x00000007U +#define ISP_GAMMA_B_X0D_M (ISP_GAMMA_B_X0D_V << ISP_GAMMA_B_X0D_S) +#define ISP_GAMMA_B_X0D_V 0x00000007U +#define ISP_GAMMA_B_X0D_S 6 +/** ISP_GAMMA_B_X0C : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X0C 0x00000007U +#define ISP_GAMMA_B_X0C_M (ISP_GAMMA_B_X0C_V << ISP_GAMMA_B_X0C_S) +#define ISP_GAMMA_B_X0C_V 0x00000007U +#define ISP_GAMMA_B_X0C_S 9 +/** ISP_GAMMA_B_X0B : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X0B 0x00000007U +#define ISP_GAMMA_B_X0B_M (ISP_GAMMA_B_X0B_V << ISP_GAMMA_B_X0B_S) +#define ISP_GAMMA_B_X0B_V 0x00000007U +#define ISP_GAMMA_B_X0B_S 12 +/** ISP_GAMMA_B_X0A : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of b channel gamma curve, it + * represents the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X0A 0x00000007U +#define ISP_GAMMA_B_X0A_M (ISP_GAMMA_B_X0A_V << ISP_GAMMA_B_X0A_S) +#define ISP_GAMMA_B_X0A_V 0x00000007U +#define ISP_GAMMA_B_X0A_S 15 +/** ISP_GAMMA_B_X09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X09 0x00000007U +#define ISP_GAMMA_B_X09_M (ISP_GAMMA_B_X09_V << ISP_GAMMA_B_X09_S) +#define ISP_GAMMA_B_X09_V 0x00000007U +#define ISP_GAMMA_B_X09_S 18 +/** ISP_GAMMA_B_X08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of b channel gamma curve, it represents + * the power of the distance from the previous point + */ +#define ISP_GAMMA_B_X08 0x00000007U +#define ISP_GAMMA_B_X08_M (ISP_GAMMA_B_X08_V << ISP_GAMMA_B_X08_S) +#define ISP_GAMMA_B_X08_V 0x00000007U +#define ISP_GAMMA_B_X08_S 21 + +/** ISP_AE_CTRL_REG register + * ae control register + */ +#define ISP_AE_CTRL_REG (DR_REG_ISP_BASE + 0xc0) +/** ISP_AE_UPDATE : WT; bitpos: [0]; default: 0; + * write 1 to this bit triggers one statistic event + */ +#define ISP_AE_UPDATE (BIT(0)) +#define ISP_AE_UPDATE_M (ISP_AE_UPDATE_V << ISP_AE_UPDATE_S) +#define ISP_AE_UPDATE_V 0x00000001U +#define ISP_AE_UPDATE_S 0 +/** ISP_AE_SELECT : R/W; bitpos: [1]; default: 0; + * this field configures ae input data source, 0: data from median, 1: data from gama + */ +#define ISP_AE_SELECT (BIT(1)) +#define ISP_AE_SELECT_M (ISP_AE_SELECT_V << ISP_AE_SELECT_S) +#define ISP_AE_SELECT_V 0x00000001U +#define ISP_AE_SELECT_S 1 + +/** ISP_AE_MONITOR_REG register + * ae monitor control register + */ +#define ISP_AE_MONITOR_REG (DR_REG_ISP_BASE + 0xc4) +/** ISP_AE_MONITOR_TL : R/W; bitpos: [7:0]; default: 0; + * this field configures the lower lum threshold of ae monitor + */ +#define ISP_AE_MONITOR_TL 0x000000FFU +#define ISP_AE_MONITOR_TL_M (ISP_AE_MONITOR_TL_V << ISP_AE_MONITOR_TL_S) +#define ISP_AE_MONITOR_TL_V 0x000000FFU +#define ISP_AE_MONITOR_TL_S 0 +/** ISP_AE_MONITOR_TH : R/W; bitpos: [15:8]; default: 0; + * this field configures the higher lum threshold of ae monitor + */ +#define ISP_AE_MONITOR_TH 0x000000FFU +#define ISP_AE_MONITOR_TH_M (ISP_AE_MONITOR_TH_V << ISP_AE_MONITOR_TH_S) +#define ISP_AE_MONITOR_TH_V 0x000000FFU +#define ISP_AE_MONITOR_TH_S 8 +/** ISP_AE_MONITOR_PERIOD : R/W; bitpos: [21:16]; default: 0; + * this field configures ae monitor frame period + */ +#define ISP_AE_MONITOR_PERIOD 0x0000003FU +#define ISP_AE_MONITOR_PERIOD_M (ISP_AE_MONITOR_PERIOD_V << ISP_AE_MONITOR_PERIOD_S) +#define ISP_AE_MONITOR_PERIOD_V 0x0000003FU +#define ISP_AE_MONITOR_PERIOD_S 16 + +/** ISP_AE_BX_REG register + * ae window register in x-direction + */ +#define ISP_AE_BX_REG (DR_REG_ISP_BASE + 0xc8) +/** ISP_AE_X_BSIZE : R/W; bitpos: [10:0]; default: 384; + * this field configures every block x size + */ +#define ISP_AE_X_BSIZE 0x000007FFU +#define ISP_AE_X_BSIZE_M (ISP_AE_X_BSIZE_V << ISP_AE_X_BSIZE_S) +#define ISP_AE_X_BSIZE_V 0x000007FFU +#define ISP_AE_X_BSIZE_S 0 +/** ISP_AE_X_START : R/W; bitpos: [21:11]; default: 0; + * this field configures first block start x address + */ +#define ISP_AE_X_START 0x000007FFU +#define ISP_AE_X_START_M (ISP_AE_X_START_V << ISP_AE_X_START_S) +#define ISP_AE_X_START_V 0x000007FFU +#define ISP_AE_X_START_S 11 + +/** ISP_AE_BY_REG register + * ae window register in y-direction + */ +#define ISP_AE_BY_REG (DR_REG_ISP_BASE + 0xcc) +/** ISP_AE_Y_BSIZE : R/W; bitpos: [10:0]; default: 216; + * this field configures every block y size + */ +#define ISP_AE_Y_BSIZE 0x000007FFU +#define ISP_AE_Y_BSIZE_M (ISP_AE_Y_BSIZE_V << ISP_AE_Y_BSIZE_S) +#define ISP_AE_Y_BSIZE_V 0x000007FFU +#define ISP_AE_Y_BSIZE_S 0 +/** ISP_AE_Y_START : R/W; bitpos: [21:11]; default: 0; + * this field configures first block start y address + */ +#define ISP_AE_Y_START 0x000007FFU +#define ISP_AE_Y_START_M (ISP_AE_Y_START_V << ISP_AE_Y_START_S) +#define ISP_AE_Y_START_V 0x000007FFU +#define ISP_AE_Y_START_S 11 + +/** ISP_AE_WINPIXNUM_REG register + * ae sub-window pix num register + */ +#define ISP_AE_WINPIXNUM_REG (DR_REG_ISP_BASE + 0xd0) +/** ISP_AE_SUBWIN_PIXNUM : R/W; bitpos: [16:0]; default: 82944; + * this field configures the pixel number of each sub win + */ +#define ISP_AE_SUBWIN_PIXNUM 0x0001FFFFU +#define ISP_AE_SUBWIN_PIXNUM_M (ISP_AE_SUBWIN_PIXNUM_V << ISP_AE_SUBWIN_PIXNUM_S) +#define ISP_AE_SUBWIN_PIXNUM_V 0x0001FFFFU +#define ISP_AE_SUBWIN_PIXNUM_S 0 + +/** ISP_AE_WIN_RECIPROCAL_REG register + * reciprocal of ae sub-window pixel number + */ +#define ISP_AE_WIN_RECIPROCAL_REG (DR_REG_ISP_BASE + 0xd4) +/** ISP_AE_SUBWIN_RECIP : R/W; bitpos: [19:0]; default: 0; + * this field configures the reciprocal of each subwin_pixnum, 20bit fraction + */ +#define ISP_AE_SUBWIN_RECIP 0x000FFFFFU +#define ISP_AE_SUBWIN_RECIP_M (ISP_AE_SUBWIN_RECIP_V << ISP_AE_SUBWIN_RECIP_S) +#define ISP_AE_SUBWIN_RECIP_V 0x000FFFFFU +#define ISP_AE_SUBWIN_RECIP_S 0 + +/** ISP_AE_BLOCK_MEAN_0_REG register + * ae statistic result register 0 + */ +#define ISP_AE_BLOCK_MEAN_0_REG (DR_REG_ISP_BASE + 0xd8) +/** ISP_AE_B03_MEAN : RO; bitpos: [7:0]; default: 0; + * this field configures block03 Y mean data + */ +#define ISP_AE_B03_MEAN 0x000000FFU +#define ISP_AE_B03_MEAN_M (ISP_AE_B03_MEAN_V << ISP_AE_B03_MEAN_S) +#define ISP_AE_B03_MEAN_V 0x000000FFU +#define ISP_AE_B03_MEAN_S 0 +/** ISP_AE_B02_MEAN : RO; bitpos: [15:8]; default: 0; + * this field configures block02 Y mean data + */ +#define ISP_AE_B02_MEAN 0x000000FFU +#define ISP_AE_B02_MEAN_M (ISP_AE_B02_MEAN_V << ISP_AE_B02_MEAN_S) +#define ISP_AE_B02_MEAN_V 0x000000FFU +#define ISP_AE_B02_MEAN_S 8 +/** ISP_AE_B01_MEAN : RO; bitpos: [23:16]; default: 0; + * this field configures block01 Y mean data + */ +#define ISP_AE_B01_MEAN 0x000000FFU +#define ISP_AE_B01_MEAN_M (ISP_AE_B01_MEAN_V << ISP_AE_B01_MEAN_S) +#define ISP_AE_B01_MEAN_V 0x000000FFU +#define ISP_AE_B01_MEAN_S 16 +/** ISP_AE_B00_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block00 Y mean data + */ +#define ISP_AE_B00_MEAN 0x000000FFU +#define ISP_AE_B00_MEAN_M (ISP_AE_B00_MEAN_V << ISP_AE_B00_MEAN_S) +#define ISP_AE_B00_MEAN_V 0x000000FFU +#define ISP_AE_B00_MEAN_S 24 + +/** ISP_AE_BLOCK_MEAN_1_REG register + * ae statistic result register 1 + */ +#define ISP_AE_BLOCK_MEAN_1_REG (DR_REG_ISP_BASE + 0xdc) +/** ISP_AE_B12_MEAN : RO; bitpos: [7:0]; default: 0; + * this field configures block12 Y mean data + */ +#define ISP_AE_B12_MEAN 0x000000FFU +#define ISP_AE_B12_MEAN_M (ISP_AE_B12_MEAN_V << ISP_AE_B12_MEAN_S) +#define ISP_AE_B12_MEAN_V 0x000000FFU +#define ISP_AE_B12_MEAN_S 0 +/** ISP_AE_B11_MEAN : RO; bitpos: [15:8]; default: 0; + * this field configures block11 Y mean data + */ +#define ISP_AE_B11_MEAN 0x000000FFU +#define ISP_AE_B11_MEAN_M (ISP_AE_B11_MEAN_V << ISP_AE_B11_MEAN_S) +#define ISP_AE_B11_MEAN_V 0x000000FFU +#define ISP_AE_B11_MEAN_S 8 +/** ISP_AE_B10_MEAN : RO; bitpos: [23:16]; default: 0; + * this field configures block10 Y mean data + */ +#define ISP_AE_B10_MEAN 0x000000FFU +#define ISP_AE_B10_MEAN_M (ISP_AE_B10_MEAN_V << ISP_AE_B10_MEAN_S) +#define ISP_AE_B10_MEAN_V 0x000000FFU +#define ISP_AE_B10_MEAN_S 16 +/** ISP_AE_B04_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block04 Y mean data + */ +#define ISP_AE_B04_MEAN 0x000000FFU +#define ISP_AE_B04_MEAN_M (ISP_AE_B04_MEAN_V << ISP_AE_B04_MEAN_S) +#define ISP_AE_B04_MEAN_V 0x000000FFU +#define ISP_AE_B04_MEAN_S 24 + +/** ISP_AE_BLOCK_MEAN_2_REG register + * ae statistic result register 2 + */ +#define ISP_AE_BLOCK_MEAN_2_REG (DR_REG_ISP_BASE + 0xe0) +/** ISP_AE_B21_MEAN : RO; bitpos: [7:0]; default: 0; + * this field configures block21 Y mean data + */ +#define ISP_AE_B21_MEAN 0x000000FFU +#define ISP_AE_B21_MEAN_M (ISP_AE_B21_MEAN_V << ISP_AE_B21_MEAN_S) +#define ISP_AE_B21_MEAN_V 0x000000FFU +#define ISP_AE_B21_MEAN_S 0 +/** ISP_AE_B20_MEAN : RO; bitpos: [15:8]; default: 0; + * this field configures block20 Y mean data + */ +#define ISP_AE_B20_MEAN 0x000000FFU +#define ISP_AE_B20_MEAN_M (ISP_AE_B20_MEAN_V << ISP_AE_B20_MEAN_S) +#define ISP_AE_B20_MEAN_V 0x000000FFU +#define ISP_AE_B20_MEAN_S 8 +/** ISP_AE_B14_MEAN : RO; bitpos: [23:16]; default: 0; + * this field configures block14 Y mean data + */ +#define ISP_AE_B14_MEAN 0x000000FFU +#define ISP_AE_B14_MEAN_M (ISP_AE_B14_MEAN_V << ISP_AE_B14_MEAN_S) +#define ISP_AE_B14_MEAN_V 0x000000FFU +#define ISP_AE_B14_MEAN_S 16 +/** ISP_AE_B13_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block13 Y mean data + */ +#define ISP_AE_B13_MEAN 0x000000FFU +#define ISP_AE_B13_MEAN_M (ISP_AE_B13_MEAN_V << ISP_AE_B13_MEAN_S) +#define ISP_AE_B13_MEAN_V 0x000000FFU +#define ISP_AE_B13_MEAN_S 24 + +/** ISP_AE_BLOCK_MEAN_3_REG register + * ae statistic result register 3 + */ +#define ISP_AE_BLOCK_MEAN_3_REG (DR_REG_ISP_BASE + 0xe4) +/** ISP_AE_B30_MEAN : RO; bitpos: [7:0]; default: 0; + * this field configures block30 Y mean data + */ +#define ISP_AE_B30_MEAN 0x000000FFU +#define ISP_AE_B30_MEAN_M (ISP_AE_B30_MEAN_V << ISP_AE_B30_MEAN_S) +#define ISP_AE_B30_MEAN_V 0x000000FFU +#define ISP_AE_B30_MEAN_S 0 +/** ISP_AE_B24_MEAN : RO; bitpos: [15:8]; default: 0; + * this field configures block24 Y mean data + */ +#define ISP_AE_B24_MEAN 0x000000FFU +#define ISP_AE_B24_MEAN_M (ISP_AE_B24_MEAN_V << ISP_AE_B24_MEAN_S) +#define ISP_AE_B24_MEAN_V 0x000000FFU +#define ISP_AE_B24_MEAN_S 8 +/** ISP_AE_B23_MEAN : RO; bitpos: [23:16]; default: 0; + * this field configures block23 Y mean data + */ +#define ISP_AE_B23_MEAN 0x000000FFU +#define ISP_AE_B23_MEAN_M (ISP_AE_B23_MEAN_V << ISP_AE_B23_MEAN_S) +#define ISP_AE_B23_MEAN_V 0x000000FFU +#define ISP_AE_B23_MEAN_S 16 +/** ISP_AE_B22_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block22 Y mean data + */ +#define ISP_AE_B22_MEAN 0x000000FFU +#define ISP_AE_B22_MEAN_M (ISP_AE_B22_MEAN_V << ISP_AE_B22_MEAN_S) +#define ISP_AE_B22_MEAN_V 0x000000FFU +#define ISP_AE_B22_MEAN_S 24 + +/** ISP_AE_BLOCK_MEAN_4_REG register + * ae statistic result register 4 + */ +#define ISP_AE_BLOCK_MEAN_4_REG (DR_REG_ISP_BASE + 0xe8) +/** ISP_AE_B34_MEAN : RO; bitpos: [7:0]; default: 0; + * this field configures block34 Y mean data + */ +#define ISP_AE_B34_MEAN 0x000000FFU +#define ISP_AE_B34_MEAN_M (ISP_AE_B34_MEAN_V << ISP_AE_B34_MEAN_S) +#define ISP_AE_B34_MEAN_V 0x000000FFU +#define ISP_AE_B34_MEAN_S 0 +/** ISP_AE_B33_MEAN : RO; bitpos: [15:8]; default: 0; + * this field configures block33 Y mean data + */ +#define ISP_AE_B33_MEAN 0x000000FFU +#define ISP_AE_B33_MEAN_M (ISP_AE_B33_MEAN_V << ISP_AE_B33_MEAN_S) +#define ISP_AE_B33_MEAN_V 0x000000FFU +#define ISP_AE_B33_MEAN_S 8 +/** ISP_AE_B32_MEAN : RO; bitpos: [23:16]; default: 0; + * this field configures block32 Y mean data + */ +#define ISP_AE_B32_MEAN 0x000000FFU +#define ISP_AE_B32_MEAN_M (ISP_AE_B32_MEAN_V << ISP_AE_B32_MEAN_S) +#define ISP_AE_B32_MEAN_V 0x000000FFU +#define ISP_AE_B32_MEAN_S 16 +/** ISP_AE_B31_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block31 Y mean data + */ +#define ISP_AE_B31_MEAN 0x000000FFU +#define ISP_AE_B31_MEAN_M (ISP_AE_B31_MEAN_V << ISP_AE_B31_MEAN_S) +#define ISP_AE_B31_MEAN_V 0x000000FFU +#define ISP_AE_B31_MEAN_S 24 + +/** ISP_AE_BLOCK_MEAN_5_REG register + * ae statistic result register 5 + */ +#define ISP_AE_BLOCK_MEAN_5_REG (DR_REG_ISP_BASE + 0xec) +/** ISP_AE_B43_MEAN : RO; bitpos: [7:0]; default: 0; + * this field configures block43 Y mean data + */ +#define ISP_AE_B43_MEAN 0x000000FFU +#define ISP_AE_B43_MEAN_M (ISP_AE_B43_MEAN_V << ISP_AE_B43_MEAN_S) +#define ISP_AE_B43_MEAN_V 0x000000FFU +#define ISP_AE_B43_MEAN_S 0 +/** ISP_AE_B42_MEAN : RO; bitpos: [15:8]; default: 0; + * this field configures block42 Y mean data + */ +#define ISP_AE_B42_MEAN 0x000000FFU +#define ISP_AE_B42_MEAN_M (ISP_AE_B42_MEAN_V << ISP_AE_B42_MEAN_S) +#define ISP_AE_B42_MEAN_V 0x000000FFU +#define ISP_AE_B42_MEAN_S 8 +/** ISP_AE_B41_MEAN : RO; bitpos: [23:16]; default: 0; + * this field configures block41 Y mean data + */ +#define ISP_AE_B41_MEAN 0x000000FFU +#define ISP_AE_B41_MEAN_M (ISP_AE_B41_MEAN_V << ISP_AE_B41_MEAN_S) +#define ISP_AE_B41_MEAN_V 0x000000FFU +#define ISP_AE_B41_MEAN_S 16 +/** ISP_AE_B40_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block40 Y mean data + */ +#define ISP_AE_B40_MEAN 0x000000FFU +#define ISP_AE_B40_MEAN_M (ISP_AE_B40_MEAN_V << ISP_AE_B40_MEAN_S) +#define ISP_AE_B40_MEAN_V 0x000000FFU +#define ISP_AE_B40_MEAN_S 24 + +/** ISP_AE_BLOCK_MEAN_6_REG register + * ae statistic result register 6 + */ +#define ISP_AE_BLOCK_MEAN_6_REG (DR_REG_ISP_BASE + 0xf0) +/** ISP_AE_B44_MEAN : RO; bitpos: [31:24]; default: 0; + * this field configures block44 Y mean data + */ +#define ISP_AE_B44_MEAN 0x000000FFU +#define ISP_AE_B44_MEAN_M (ISP_AE_B44_MEAN_V << ISP_AE_B44_MEAN_S) +#define ISP_AE_B44_MEAN_V 0x000000FFU +#define ISP_AE_B44_MEAN_S 24 + +/** ISP_SHARP_CTRL0_REG register + * sharp control register 0 + */ +#define ISP_SHARP_CTRL0_REG (DR_REG_ISP_BASE + 0xf4) +/** ISP_SHARP_THRESHOLD_LOW : R/W; bitpos: [7:0]; default: 0; + * this field configures sharpen threshold for detail + */ +#define ISP_SHARP_THRESHOLD_LOW 0x000000FFU +#define ISP_SHARP_THRESHOLD_LOW_M (ISP_SHARP_THRESHOLD_LOW_V << ISP_SHARP_THRESHOLD_LOW_S) +#define ISP_SHARP_THRESHOLD_LOW_V 0x000000FFU +#define ISP_SHARP_THRESHOLD_LOW_S 0 +/** ISP_SHARP_THRESHOLD_HIGH : R/W; bitpos: [15:8]; default: 0; + * this field configures sharpen threshold for edge + */ +#define ISP_SHARP_THRESHOLD_HIGH 0x000000FFU +#define ISP_SHARP_THRESHOLD_HIGH_M (ISP_SHARP_THRESHOLD_HIGH_V << ISP_SHARP_THRESHOLD_HIGH_S) +#define ISP_SHARP_THRESHOLD_HIGH_V 0x000000FFU +#define ISP_SHARP_THRESHOLD_HIGH_S 8 +/** ISP_SHARP_AMOUNT_LOW : R/W; bitpos: [23:16]; default: 0; + * this field configures sharpen amount for detail + */ +#define ISP_SHARP_AMOUNT_LOW 0x000000FFU +#define ISP_SHARP_AMOUNT_LOW_M (ISP_SHARP_AMOUNT_LOW_V << ISP_SHARP_AMOUNT_LOW_S) +#define ISP_SHARP_AMOUNT_LOW_V 0x000000FFU +#define ISP_SHARP_AMOUNT_LOW_S 16 +/** ISP_SHARP_AMOUNT_HIGH : R/W; bitpos: [31:24]; default: 0; + * this field configures sharpen amount for edge + */ +#define ISP_SHARP_AMOUNT_HIGH 0x000000FFU +#define ISP_SHARP_AMOUNT_HIGH_M (ISP_SHARP_AMOUNT_HIGH_V << ISP_SHARP_AMOUNT_HIGH_S) +#define ISP_SHARP_AMOUNT_HIGH_V 0x000000FFU +#define ISP_SHARP_AMOUNT_HIGH_S 24 + +/** ISP_SHARP_FILTER0_REG register + * sharp usm config register 0 + */ +#define ISP_SHARP_FILTER0_REG (DR_REG_ISP_BASE + 0xf8) +/** ISP_SHARP_FILTER_COE00 : R/W; bitpos: [4:0]; default: 1; + * this field configures unsharp masking(usm) filter coefficient + */ +#define ISP_SHARP_FILTER_COE00 0x0000001FU +#define ISP_SHARP_FILTER_COE00_M (ISP_SHARP_FILTER_COE00_V << ISP_SHARP_FILTER_COE00_S) +#define ISP_SHARP_FILTER_COE00_V 0x0000001FU +#define ISP_SHARP_FILTER_COE00_S 0 +/** ISP_SHARP_FILTER_COE01 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE01 0x0000001FU +#define ISP_SHARP_FILTER_COE01_M (ISP_SHARP_FILTER_COE01_V << ISP_SHARP_FILTER_COE01_S) +#define ISP_SHARP_FILTER_COE01_V 0x0000001FU +#define ISP_SHARP_FILTER_COE01_S 5 +/** ISP_SHARP_FILTER_COE02 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE02 0x0000001FU +#define ISP_SHARP_FILTER_COE02_M (ISP_SHARP_FILTER_COE02_V << ISP_SHARP_FILTER_COE02_S) +#define ISP_SHARP_FILTER_COE02_V 0x0000001FU +#define ISP_SHARP_FILTER_COE02_S 10 + +/** ISP_SHARP_FILTER1_REG register + * sharp usm config register 1 + */ +#define ISP_SHARP_FILTER1_REG (DR_REG_ISP_BASE + 0xfc) +/** ISP_SHARP_FILTER_COE10 : R/W; bitpos: [4:0]; default: 2; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE10 0x0000001FU +#define ISP_SHARP_FILTER_COE10_M (ISP_SHARP_FILTER_COE10_V << ISP_SHARP_FILTER_COE10_S) +#define ISP_SHARP_FILTER_COE10_V 0x0000001FU +#define ISP_SHARP_FILTER_COE10_S 0 +/** ISP_SHARP_FILTER_COE11 : R/W; bitpos: [9:5]; default: 4; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE11 0x0000001FU +#define ISP_SHARP_FILTER_COE11_M (ISP_SHARP_FILTER_COE11_V << ISP_SHARP_FILTER_COE11_S) +#define ISP_SHARP_FILTER_COE11_V 0x0000001FU +#define ISP_SHARP_FILTER_COE11_S 5 +/** ISP_SHARP_FILTER_COE12 : R/W; bitpos: [14:10]; default: 2; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE12 0x0000001FU +#define ISP_SHARP_FILTER_COE12_M (ISP_SHARP_FILTER_COE12_V << ISP_SHARP_FILTER_COE12_S) +#define ISP_SHARP_FILTER_COE12_V 0x0000001FU +#define ISP_SHARP_FILTER_COE12_S 10 + +/** ISP_SHARP_FILTER2_REG register + * sharp usm config register 2 + */ +#define ISP_SHARP_FILTER2_REG (DR_REG_ISP_BASE + 0x100) +/** ISP_SHARP_FILTER_COE20 : R/W; bitpos: [4:0]; default: 1; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE20 0x0000001FU +#define ISP_SHARP_FILTER_COE20_M (ISP_SHARP_FILTER_COE20_V << ISP_SHARP_FILTER_COE20_S) +#define ISP_SHARP_FILTER_COE20_V 0x0000001FU +#define ISP_SHARP_FILTER_COE20_S 0 +/** ISP_SHARP_FILTER_COE21 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE21 0x0000001FU +#define ISP_SHARP_FILTER_COE21_M (ISP_SHARP_FILTER_COE21_V << ISP_SHARP_FILTER_COE21_S) +#define ISP_SHARP_FILTER_COE21_V 0x0000001FU +#define ISP_SHARP_FILTER_COE21_S 5 +/** ISP_SHARP_FILTER_COE22 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ +#define ISP_SHARP_FILTER_COE22 0x0000001FU +#define ISP_SHARP_FILTER_COE22_M (ISP_SHARP_FILTER_COE22_V << ISP_SHARP_FILTER_COE22_S) +#define ISP_SHARP_FILTER_COE22_V 0x0000001FU +#define ISP_SHARP_FILTER_COE22_S 10 + +/** ISP_SHARP_MATRIX_CTRL_REG register + * sharp pix2matrix ctrl + */ +#define ISP_SHARP_MATRIX_CTRL_REG (DR_REG_ISP_BASE + 0x104) +/** ISP_SHARP_TAIL_PIXEN_PULSE_TL : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and + * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < + * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + */ +#define ISP_SHARP_TAIL_PIXEN_PULSE_TL 0x000000FFU +#define ISP_SHARP_TAIL_PIXEN_PULSE_TL_M (ISP_SHARP_TAIL_PIXEN_PULSE_TL_V << ISP_SHARP_TAIL_PIXEN_PULSE_TL_S) +#define ISP_SHARP_TAIL_PIXEN_PULSE_TL_V 0x000000FFU +#define ISP_SHARP_TAIL_PIXEN_PULSE_TL_S 0 +/** ISP_SHARP_TAIL_PIXEN_PULSE_TH : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and + * reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail + * pulse function + */ +#define ISP_SHARP_TAIL_PIXEN_PULSE_TH 0x000000FFU +#define ISP_SHARP_TAIL_PIXEN_PULSE_TH_M (ISP_SHARP_TAIL_PIXEN_PULSE_TH_V << ISP_SHARP_TAIL_PIXEN_PULSE_TH_S) +#define ISP_SHARP_TAIL_PIXEN_PULSE_TH_V 0x000000FFU +#define ISP_SHARP_TAIL_PIXEN_PULSE_TH_S 8 +/** ISP_SHARP_PADDING_DATA : R/W; bitpos: [23:16]; default: 0; + * this field configures sharp padding data + */ +#define ISP_SHARP_PADDING_DATA 0x000000FFU +#define ISP_SHARP_PADDING_DATA_M (ISP_SHARP_PADDING_DATA_V << ISP_SHARP_PADDING_DATA_S) +#define ISP_SHARP_PADDING_DATA_V 0x000000FFU +#define ISP_SHARP_PADDING_DATA_S 16 +/** ISP_SHARP_PADDING_MODE : R/W; bitpos: [24]; default: 0; + * this field configures sharp padding mode + */ +#define ISP_SHARP_PADDING_MODE (BIT(24)) +#define ISP_SHARP_PADDING_MODE_M (ISP_SHARP_PADDING_MODE_V << ISP_SHARP_PADDING_MODE_S) +#define ISP_SHARP_PADDING_MODE_V 0x00000001U +#define ISP_SHARP_PADDING_MODE_S 24 + +/** ISP_SHARP_CTRL1_REG register + * sharp control register 1 + */ +#define ISP_SHARP_CTRL1_REG (DR_REG_ISP_BASE + 0x108) +/** ISP_SHARP_GRADIENT_MAX : RO; bitpos: [7:0]; default: 0; + * this field configures sharp max gradient, refresh at the end of each frame end + */ +#define ISP_SHARP_GRADIENT_MAX 0x000000FFU +#define ISP_SHARP_GRADIENT_MAX_M (ISP_SHARP_GRADIENT_MAX_V << ISP_SHARP_GRADIENT_MAX_S) +#define ISP_SHARP_GRADIENT_MAX_V 0x000000FFU +#define ISP_SHARP_GRADIENT_MAX_S 0 + +/** ISP_DMA_CNTL_REG register + * isp dma source trans control register + */ +#define ISP_DMA_CNTL_REG (DR_REG_ISP_BASE + 0x10c) +/** ISP_DMA_EN : WT; bitpos: [0]; default: 0; + * write 1 to trigger dma to get 1 frame + */ +#define ISP_DMA_EN (BIT(0)) +#define ISP_DMA_EN_M (ISP_DMA_EN_V << ISP_DMA_EN_S) +#define ISP_DMA_EN_V 0x00000001U +#define ISP_DMA_EN_S 0 +/** ISP_DMA_UPDATE_REG : R/W; bitpos: [1]; default: 0; + * write 1 to update reg_dma_burst_len & reg_dma_data_type + */ +#define ISP_DMA_UPDATE_REG (BIT(1)) +#define ISP_DMA_UPDATE_REG_M (ISP_DMA_UPDATE_REG_V << ISP_DMA_UPDATE_REG_S) +#define ISP_DMA_UPDATE_REG_V 0x00000001U +#define ISP_DMA_UPDATE_REG_S 1 +/** ISP_DMA_DATA_TYPE : R/W; bitpos: [7:2]; default: 42; + * this field configures the idi data type for image data + */ +#define ISP_DMA_DATA_TYPE 0x0000003FU +#define ISP_DMA_DATA_TYPE_M (ISP_DMA_DATA_TYPE_V << ISP_DMA_DATA_TYPE_S) +#define ISP_DMA_DATA_TYPE_V 0x0000003FU +#define ISP_DMA_DATA_TYPE_S 2 +/** ISP_DMA_BURST_LEN : R/W; bitpos: [19:8]; default: 128; + * this field configures dma burst len when data source is dma. set according to + * dma_msize, it is the number of 64bits in a dma transfer + */ +#define ISP_DMA_BURST_LEN 0x00000FFFU +#define ISP_DMA_BURST_LEN_M (ISP_DMA_BURST_LEN_V << ISP_DMA_BURST_LEN_S) +#define ISP_DMA_BURST_LEN_V 0x00000FFFU +#define ISP_DMA_BURST_LEN_S 8 +/** ISP_DMA_INTERVAL : R/W; bitpos: [31:20]; default: 1; + * this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... + */ +#define ISP_DMA_INTERVAL 0x00000FFFU +#define ISP_DMA_INTERVAL_M (ISP_DMA_INTERVAL_V << ISP_DMA_INTERVAL_S) +#define ISP_DMA_INTERVAL_V 0x00000FFFU +#define ISP_DMA_INTERVAL_S 20 + +/** ISP_DMA_RAW_DATA_REG register + * isp dma source total raw number set register + */ +#define ISP_DMA_RAW_DATA_REG (DR_REG_ISP_BASE + 0x110) +/** ISP_DMA_RAW_NUM_TOTAL : R/W; bitpos: [21:0]; default: 0; + * this field configures the the number of 64bits in a frame + */ +#define ISP_DMA_RAW_NUM_TOTAL 0x003FFFFFU +#define ISP_DMA_RAW_NUM_TOTAL_M (ISP_DMA_RAW_NUM_TOTAL_V << ISP_DMA_RAW_NUM_TOTAL_S) +#define ISP_DMA_RAW_NUM_TOTAL_V 0x003FFFFFU +#define ISP_DMA_RAW_NUM_TOTAL_S 0 +/** ISP_DMA_RAW_NUM_TOTAL_SET : WT; bitpos: [31]; default: 0; + * write 1 to update reg_dma_raw_num_total + */ +#define ISP_DMA_RAW_NUM_TOTAL_SET (BIT(31)) +#define ISP_DMA_RAW_NUM_TOTAL_SET_M (ISP_DMA_RAW_NUM_TOTAL_SET_V << ISP_DMA_RAW_NUM_TOTAL_SET_S) +#define ISP_DMA_RAW_NUM_TOTAL_SET_V 0x00000001U +#define ISP_DMA_RAW_NUM_TOTAL_SET_S 31 + +/** ISP_CAM_CNTL_REG register + * isp cam source control register + */ +#define ISP_CAM_CNTL_REG (DR_REG_ISP_BASE + 0x114) +/** ISP_CAM_EN : R/W; bitpos: [0]; default: 0; + * write 1 to start receive camera data, write 0 to disable + */ +#define ISP_CAM_EN (BIT(0)) +#define ISP_CAM_EN_M (ISP_CAM_EN_V << ISP_CAM_EN_S) +#define ISP_CAM_EN_V 0x00000001U +#define ISP_CAM_EN_S 0 +/** ISP_CAM_UPDATE_REG : R/W; bitpos: [1]; default: 0; + * write 1 to update ISP_CAM_CONF + */ +#define ISP_CAM_UPDATE_REG (BIT(1)) +#define ISP_CAM_UPDATE_REG_M (ISP_CAM_UPDATE_REG_V << ISP_CAM_UPDATE_REG_S) +#define ISP_CAM_UPDATE_REG_V 0x00000001U +#define ISP_CAM_UPDATE_REG_S 1 +/** ISP_CAM_RESET : R/W; bitpos: [2]; default: 1; + * this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset + */ +#define ISP_CAM_RESET (BIT(2)) +#define ISP_CAM_RESET_M (ISP_CAM_RESET_V << ISP_CAM_RESET_S) +#define ISP_CAM_RESET_V 0x00000001U +#define ISP_CAM_RESET_S 2 +/** ISP_CAM_CLK_INV : R/W; bitpos: [3]; default: 0; + * this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1: + * invert cam clk + */ +#define ISP_CAM_CLK_INV (BIT(3)) +#define ISP_CAM_CLK_INV_M (ISP_CAM_CLK_INV_V << ISP_CAM_CLK_INV_S) +#define ISP_CAM_CLK_INV_V 0x00000001U +#define ISP_CAM_CLK_INV_S 3 + +/** ISP_CAM_CONF_REG register + * isp cam source config register + */ +#define ISP_CAM_CONF_REG (DR_REG_ISP_BASE + 0x118) +/** ISP_CAM_DATA_ORDER : R/W; bitpos: [0]; default: 0; + * this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], + * cam_data_in[15:8]} + */ +#define ISP_CAM_DATA_ORDER (BIT(0)) +#define ISP_CAM_DATA_ORDER_M (ISP_CAM_DATA_ORDER_V << ISP_CAM_DATA_ORDER_S) +#define ISP_CAM_DATA_ORDER_V 0x00000001U +#define ISP_CAM_DATA_ORDER_S 0 +/** ISP_CAM_2BYTE_MODE : R/W; bitpos: [1]; default: 0; + * this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: + * disable, 1: enable + */ +#define ISP_CAM_2BYTE_MODE (BIT(1)) +#define ISP_CAM_2BYTE_MODE_M (ISP_CAM_2BYTE_MODE_V << ISP_CAM_2BYTE_MODE_S) +#define ISP_CAM_2BYTE_MODE_V 0x00000001U +#define ISP_CAM_2BYTE_MODE_S 1 +/** ISP_CAM_DATA_TYPE : R/W; bitpos: [7:2]; default: 42; + * this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: + * RAW12 + */ +#define ISP_CAM_DATA_TYPE 0x0000003FU +#define ISP_CAM_DATA_TYPE_M (ISP_CAM_DATA_TYPE_V << ISP_CAM_DATA_TYPE_S) +#define ISP_CAM_DATA_TYPE_V 0x0000003FU +#define ISP_CAM_DATA_TYPE_S 2 +/** ISP_CAM_DE_INV : R/W; bitpos: [8]; default: 0; + * this bit configures cam data enable invert. 0: not invert, 1: invert + */ +#define ISP_CAM_DE_INV (BIT(8)) +#define ISP_CAM_DE_INV_M (ISP_CAM_DE_INV_V << ISP_CAM_DE_INV_S) +#define ISP_CAM_DE_INV_V 0x00000001U +#define ISP_CAM_DE_INV_S 8 +/** ISP_CAM_HSYNC_INV : R/W; bitpos: [9]; default: 0; + * this bit configures cam hsync invert. 0: not invert, 1: invert + */ +#define ISP_CAM_HSYNC_INV (BIT(9)) +#define ISP_CAM_HSYNC_INV_M (ISP_CAM_HSYNC_INV_V << ISP_CAM_HSYNC_INV_S) +#define ISP_CAM_HSYNC_INV_V 0x00000001U +#define ISP_CAM_HSYNC_INV_S 9 +/** ISP_CAM_VSYNC_INV : R/W; bitpos: [10]; default: 0; + * this bit configures cam vsync invert. 0: not invert, 1: invert + */ +#define ISP_CAM_VSYNC_INV (BIT(10)) +#define ISP_CAM_VSYNC_INV_M (ISP_CAM_VSYNC_INV_V << ISP_CAM_VSYNC_INV_S) +#define ISP_CAM_VSYNC_INV_V 0x00000001U +#define ISP_CAM_VSYNC_INV_S 10 +/** ISP_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [13:11]; default: 0; + * this bit configures the number of clock of vsync filter length + */ +#define ISP_CAM_VSYNC_FILTER_THRES 0x00000007U +#define ISP_CAM_VSYNC_FILTER_THRES_M (ISP_CAM_VSYNC_FILTER_THRES_V << ISP_CAM_VSYNC_FILTER_THRES_S) +#define ISP_CAM_VSYNC_FILTER_THRES_V 0x00000007U +#define ISP_CAM_VSYNC_FILTER_THRES_S 11 +/** ISP_CAM_VSYNC_FILTER_EN : R/W; bitpos: [14]; default: 0; + * this bit configures vsync filter en + */ +#define ISP_CAM_VSYNC_FILTER_EN (BIT(14)) +#define ISP_CAM_VSYNC_FILTER_EN_M (ISP_CAM_VSYNC_FILTER_EN_V << ISP_CAM_VSYNC_FILTER_EN_S) +#define ISP_CAM_VSYNC_FILTER_EN_V 0x00000001U +#define ISP_CAM_VSYNC_FILTER_EN_S 14 +/** ISP_CAM_DE_ONLY : R/W; bitpos: [15]; default: 0; + * configures whether cam inf only has de, no hsync data. 0: has hsync, 1: no hsync + */ +#define ISP_CAM_DE_ONLY (BIT(15)) +#define ISP_CAM_DE_ONLY_M (ISP_CAM_DE_ONLY_V << ISP_CAM_DE_ONLY_S) +#define ISP_CAM_DE_ONLY_V 0x00000001U +#define ISP_CAM_DE_ONLY_S 15 + +/** ISP_AF_CTRL0_REG register + * af control register 0 + */ +#define ISP_AF_CTRL0_REG (DR_REG_ISP_BASE + 0x11c) +/** ISP_AF_AUTO_UPDATE : R/W; bitpos: [0]; default: 0; + * this bit configures auto_update enable. when set to 1, will update sum and lum each + * frame + */ +#define ISP_AF_AUTO_UPDATE (BIT(0)) +#define ISP_AF_AUTO_UPDATE_M (ISP_AF_AUTO_UPDATE_V << ISP_AF_AUTO_UPDATE_S) +#define ISP_AF_AUTO_UPDATE_V 0x00000001U +#define ISP_AF_AUTO_UPDATE_S 0 +/** ISP_AF_MANUAL_UPDATE : WT; bitpos: [4]; default: 0; + * write 1 to this bit will update the sum and lum once + */ +#define ISP_AF_MANUAL_UPDATE (BIT(4)) +#define ISP_AF_MANUAL_UPDATE_M (ISP_AF_MANUAL_UPDATE_V << ISP_AF_MANUAL_UPDATE_S) +#define ISP_AF_MANUAL_UPDATE_V 0x00000001U +#define ISP_AF_MANUAL_UPDATE_S 4 +/** ISP_AF_ENV_THRESHOLD : R/W; bitpos: [11:8]; default: 0; + * this field configures env threshold. when both sum and lum changes larger than this + * value, consider environment changes and need to trigger a new autofocus. 4Bit + * fractional + */ +#define ISP_AF_ENV_THRESHOLD 0x0000000FU +#define ISP_AF_ENV_THRESHOLD_M (ISP_AF_ENV_THRESHOLD_V << ISP_AF_ENV_THRESHOLD_S) +#define ISP_AF_ENV_THRESHOLD_V 0x0000000FU +#define ISP_AF_ENV_THRESHOLD_S 8 +/** ISP_AF_ENV_PERIOD : R/W; bitpos: [23:16]; default: 0; + * this field configures environment changes detection period (frame). When set to 0, + * disable this function + */ +#define ISP_AF_ENV_PERIOD 0x000000FFU +#define ISP_AF_ENV_PERIOD_M (ISP_AF_ENV_PERIOD_V << ISP_AF_ENV_PERIOD_S) +#define ISP_AF_ENV_PERIOD_V 0x000000FFU +#define ISP_AF_ENV_PERIOD_S 16 + +/** ISP_AF_CTRL1_REG register + * af control register 1 + */ +#define ISP_AF_CTRL1_REG (DR_REG_ISP_BASE + 0x120) +/** ISP_AF_THPIXNUM : R/W; bitpos: [21:0]; default: 0; + * this field configures pixnum used when calculating the autofocus threshold. Set to + * 0 to disable threshold calculation + */ +#define ISP_AF_THPIXNUM 0x003FFFFFU +#define ISP_AF_THPIXNUM_M (ISP_AF_THPIXNUM_V << ISP_AF_THPIXNUM_S) +#define ISP_AF_THPIXNUM_V 0x003FFFFFU +#define ISP_AF_THPIXNUM_S 0 + +/** ISP_AF_GEN_TH_CTRL_REG register + * af gen threshold control register + */ +#define ISP_AF_GEN_TH_CTRL_REG (DR_REG_ISP_BASE + 0x124) +/** ISP_AF_GEN_THRESHOLD_MIN : R/W; bitpos: [15:0]; default: 128; + * this field configures min threshold when use auto_threshold + */ +#define ISP_AF_GEN_THRESHOLD_MIN 0x0000FFFFU +#define ISP_AF_GEN_THRESHOLD_MIN_M (ISP_AF_GEN_THRESHOLD_MIN_V << ISP_AF_GEN_THRESHOLD_MIN_S) +#define ISP_AF_GEN_THRESHOLD_MIN_V 0x0000FFFFU +#define ISP_AF_GEN_THRESHOLD_MIN_S 0 +/** ISP_AF_GEN_THRESHOLD_MAX : R/W; bitpos: [31:16]; default: 1088; + * this field configures max threshold when use auto_threshold + */ +#define ISP_AF_GEN_THRESHOLD_MAX 0x0000FFFFU +#define ISP_AF_GEN_THRESHOLD_MAX_M (ISP_AF_GEN_THRESHOLD_MAX_V << ISP_AF_GEN_THRESHOLD_MAX_S) +#define ISP_AF_GEN_THRESHOLD_MAX_V 0x0000FFFFU +#define ISP_AF_GEN_THRESHOLD_MAX_S 16 + +/** ISP_AF_ENV_USER_TH_SUM_REG register + * af monitor user sum threshold register + */ +#define ISP_AF_ENV_USER_TH_SUM_REG (DR_REG_ISP_BASE + 0x128) +/** ISP_AF_ENV_USER_THRESHOLD_SUM : R/W; bitpos: [31:0]; default: 0; + * this field configures user setup env detect sum threshold + */ +#define ISP_AF_ENV_USER_THRESHOLD_SUM 0xFFFFFFFFU +#define ISP_AF_ENV_USER_THRESHOLD_SUM_M (ISP_AF_ENV_USER_THRESHOLD_SUM_V << ISP_AF_ENV_USER_THRESHOLD_SUM_S) +#define ISP_AF_ENV_USER_THRESHOLD_SUM_V 0xFFFFFFFFU +#define ISP_AF_ENV_USER_THRESHOLD_SUM_S 0 + +/** ISP_AF_ENV_USER_TH_LUM_REG register + * af monitor user lum threshold register + */ +#define ISP_AF_ENV_USER_TH_LUM_REG (DR_REG_ISP_BASE + 0x12c) +/** ISP_AF_ENV_USER_THRESHOLD_LUM : R/W; bitpos: [29:0]; default: 0; + * this field configures user setup env detect lum threshold + */ +#define ISP_AF_ENV_USER_THRESHOLD_LUM 0x3FFFFFFFU +#define ISP_AF_ENV_USER_THRESHOLD_LUM_M (ISP_AF_ENV_USER_THRESHOLD_LUM_V << ISP_AF_ENV_USER_THRESHOLD_LUM_S) +#define ISP_AF_ENV_USER_THRESHOLD_LUM_V 0x3FFFFFFFU +#define ISP_AF_ENV_USER_THRESHOLD_LUM_S 0 + +/** ISP_AF_THRESHOLD_REG register + * af threshold register + */ +#define ISP_AF_THRESHOLD_REG (DR_REG_ISP_BASE + 0x130) +/** ISP_AF_THRESHOLD : R/W; bitpos: [15:0]; default: 256; + * this field configures user threshold. When set to non-zero, autofocus will use this + * threshold + */ +#define ISP_AF_THRESHOLD 0x0000FFFFU +#define ISP_AF_THRESHOLD_M (ISP_AF_THRESHOLD_V << ISP_AF_THRESHOLD_S) +#define ISP_AF_THRESHOLD_V 0x0000FFFFU +#define ISP_AF_THRESHOLD_S 0 +/** ISP_AF_GEN_THRESHOLD : RO; bitpos: [31:16]; default: 0; + * this field represents the last calculated threshold + */ +#define ISP_AF_GEN_THRESHOLD 0x0000FFFFU +#define ISP_AF_GEN_THRESHOLD_M (ISP_AF_GEN_THRESHOLD_V << ISP_AF_GEN_THRESHOLD_S) +#define ISP_AF_GEN_THRESHOLD_V 0x0000FFFFU +#define ISP_AF_GEN_THRESHOLD_S 16 + +/** ISP_AF_HSCALE_A_REG register + * h-scale of af window a register + */ +#define ISP_AF_HSCALE_A_REG (DR_REG_ISP_BASE + 0x134) +/** ISP_AF_RPOINT_A : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window a, must >= 2 + */ +#define ISP_AF_RPOINT_A 0x00000FFFU +#define ISP_AF_RPOINT_A_M (ISP_AF_RPOINT_A_V << ISP_AF_RPOINT_A_S) +#define ISP_AF_RPOINT_A_V 0x00000FFFU +#define ISP_AF_RPOINT_A_S 0 +/** ISP_AF_LPOINT_A : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window a, must >= 2 + */ +#define ISP_AF_LPOINT_A 0x00000FFFU +#define ISP_AF_LPOINT_A_M (ISP_AF_LPOINT_A_V << ISP_AF_LPOINT_A_S) +#define ISP_AF_LPOINT_A_V 0x00000FFFU +#define ISP_AF_LPOINT_A_S 16 + +/** ISP_AF_VSCALE_A_REG register + * v-scale of af window a register + */ +#define ISP_AF_VSCALE_A_REG (DR_REG_ISP_BASE + 0x138) +/** ISP_AF_BPOINT_A : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window a, must <= hnum-2 + */ +#define ISP_AF_BPOINT_A 0x00000FFFU +#define ISP_AF_BPOINT_A_M (ISP_AF_BPOINT_A_V << ISP_AF_BPOINT_A_S) +#define ISP_AF_BPOINT_A_V 0x00000FFFU +#define ISP_AF_BPOINT_A_S 0 +/** ISP_AF_TPOINT_A : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window a, must <= hnum-2 + */ +#define ISP_AF_TPOINT_A 0x00000FFFU +#define ISP_AF_TPOINT_A_M (ISP_AF_TPOINT_A_V << ISP_AF_TPOINT_A_S) +#define ISP_AF_TPOINT_A_V 0x00000FFFU +#define ISP_AF_TPOINT_A_S 16 + +/** ISP_AF_HSCALE_B_REG register + * h-scale of af window b register + */ +#define ISP_AF_HSCALE_B_REG (DR_REG_ISP_BASE + 0x13c) +/** ISP_AF_RPOINT_B : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window b, must >= 2 + */ +#define ISP_AF_RPOINT_B 0x00000FFFU +#define ISP_AF_RPOINT_B_M (ISP_AF_RPOINT_B_V << ISP_AF_RPOINT_B_S) +#define ISP_AF_RPOINT_B_V 0x00000FFFU +#define ISP_AF_RPOINT_B_S 0 +/** ISP_AF_LPOINT_B : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window b, must >= 2 + */ +#define ISP_AF_LPOINT_B 0x00000FFFU +#define ISP_AF_LPOINT_B_M (ISP_AF_LPOINT_B_V << ISP_AF_LPOINT_B_S) +#define ISP_AF_LPOINT_B_V 0x00000FFFU +#define ISP_AF_LPOINT_B_S 16 + +/** ISP_AF_VSCALE_B_REG register + * v-scale of af window b register + */ +#define ISP_AF_VSCALE_B_REG (DR_REG_ISP_BASE + 0x140) +/** ISP_AF_BPOINT_B : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window b, must <= hnum-2 + */ +#define ISP_AF_BPOINT_B 0x00000FFFU +#define ISP_AF_BPOINT_B_M (ISP_AF_BPOINT_B_V << ISP_AF_BPOINT_B_S) +#define ISP_AF_BPOINT_B_V 0x00000FFFU +#define ISP_AF_BPOINT_B_S 0 +/** ISP_AF_TPOINT_B : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window b, must <= hnum-2 + */ +#define ISP_AF_TPOINT_B 0x00000FFFU +#define ISP_AF_TPOINT_B_M (ISP_AF_TPOINT_B_V << ISP_AF_TPOINT_B_S) +#define ISP_AF_TPOINT_B_V 0x00000FFFU +#define ISP_AF_TPOINT_B_S 16 + +/** ISP_AF_HSCALE_C_REG register + * v-scale of af window c register + */ +#define ISP_AF_HSCALE_C_REG (DR_REG_ISP_BASE + 0x144) +/** ISP_AF_RPOINT_C : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window c, must >= 2 + */ +#define ISP_AF_RPOINT_C 0x00000FFFU +#define ISP_AF_RPOINT_C_M (ISP_AF_RPOINT_C_V << ISP_AF_RPOINT_C_S) +#define ISP_AF_RPOINT_C_V 0x00000FFFU +#define ISP_AF_RPOINT_C_S 0 +/** ISP_AF_LPOINT_C : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window c, must >= 2 + */ +#define ISP_AF_LPOINT_C 0x00000FFFU +#define ISP_AF_LPOINT_C_M (ISP_AF_LPOINT_C_V << ISP_AF_LPOINT_C_S) +#define ISP_AF_LPOINT_C_V 0x00000FFFU +#define ISP_AF_LPOINT_C_S 16 + +/** ISP_AF_VSCALE_C_REG register + * v-scale of af window c register + */ +#define ISP_AF_VSCALE_C_REG (DR_REG_ISP_BASE + 0x148) +/** ISP_AF_BPOINT_C : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window c, must <= hnum-2 + */ +#define ISP_AF_BPOINT_C 0x00000FFFU +#define ISP_AF_BPOINT_C_M (ISP_AF_BPOINT_C_V << ISP_AF_BPOINT_C_S) +#define ISP_AF_BPOINT_C_V 0x00000FFFU +#define ISP_AF_BPOINT_C_S 0 +/** ISP_AF_TPOINT_C : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window c, must <= hnum-2 + */ +#define ISP_AF_TPOINT_C 0x00000FFFU +#define ISP_AF_TPOINT_C_M (ISP_AF_TPOINT_C_V << ISP_AF_TPOINT_C_S) +#define ISP_AF_TPOINT_C_V 0x00000FFFU +#define ISP_AF_TPOINT_C_S 16 + +/** ISP_AF_SUM_A_REG register + * result of sum of af window a + */ +#define ISP_AF_SUM_A_REG (DR_REG_ISP_BASE + 0x14c) +/** ISP_AF_SUMA : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window a + */ +#define ISP_AF_SUMA 0x3FFFFFFFU +#define ISP_AF_SUMA_M (ISP_AF_SUMA_V << ISP_AF_SUMA_S) +#define ISP_AF_SUMA_V 0x3FFFFFFFU +#define ISP_AF_SUMA_S 0 + +/** ISP_AF_SUM_B_REG register + * result of sum of af window b + */ +#define ISP_AF_SUM_B_REG (DR_REG_ISP_BASE + 0x150) +/** ISP_AF_SUMB : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window b + */ +#define ISP_AF_SUMB 0x3FFFFFFFU +#define ISP_AF_SUMB_M (ISP_AF_SUMB_V << ISP_AF_SUMB_S) +#define ISP_AF_SUMB_V 0x3FFFFFFFU +#define ISP_AF_SUMB_S 0 + +/** ISP_AF_SUM_C_REG register + * result of sum of af window c + */ +#define ISP_AF_SUM_C_REG (DR_REG_ISP_BASE + 0x154) +/** ISP_AF_SUMC : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window c + */ +#define ISP_AF_SUMC 0x3FFFFFFFU +#define ISP_AF_SUMC_M (ISP_AF_SUMC_V << ISP_AF_SUMC_S) +#define ISP_AF_SUMC_V 0x3FFFFFFFU +#define ISP_AF_SUMC_S 0 + +/** ISP_AF_LUM_A_REG register + * result of lum of af window a + */ +#define ISP_AF_LUM_A_REG (DR_REG_ISP_BASE + 0x158) +/** ISP_AF_LUMA : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window a + */ +#define ISP_AF_LUMA 0x0FFFFFFFU +#define ISP_AF_LUMA_M (ISP_AF_LUMA_V << ISP_AF_LUMA_S) +#define ISP_AF_LUMA_V 0x0FFFFFFFU +#define ISP_AF_LUMA_S 0 + +/** ISP_AF_LUM_B_REG register + * result of lum of af window b + */ +#define ISP_AF_LUM_B_REG (DR_REG_ISP_BASE + 0x15c) +/** ISP_AF_LUMB : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window b + */ +#define ISP_AF_LUMB 0x0FFFFFFFU +#define ISP_AF_LUMB_M (ISP_AF_LUMB_V << ISP_AF_LUMB_S) +#define ISP_AF_LUMB_V 0x0FFFFFFFU +#define ISP_AF_LUMB_S 0 + +/** ISP_AF_LUM_C_REG register + * result of lum of af window c + */ +#define ISP_AF_LUM_C_REG (DR_REG_ISP_BASE + 0x160) +/** ISP_AF_LUMC : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window c + */ +#define ISP_AF_LUMC 0x0FFFFFFFU +#define ISP_AF_LUMC_M (ISP_AF_LUMC_V << ISP_AF_LUMC_S) +#define ISP_AF_LUMC_V 0x0FFFFFFFU +#define ISP_AF_LUMC_S 0 + +/** ISP_AWB_MODE_REG register + * awb mode control register + */ +#define ISP_AWB_MODE_REG (DR_REG_ISP_BASE + 0x164) +/** ISP_AWB_MODE : R/W; bitpos: [1:0]; default: 3; + * this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel + * algo1. 11: sel both algo0 and algo1 + */ +#define ISP_AWB_MODE 0x00000003U +#define ISP_AWB_MODE_M (ISP_AWB_MODE_V << ISP_AWB_MODE_S) +#define ISP_AWB_MODE_V 0x00000003U +#define ISP_AWB_MODE_S 0 +/** ISP_AWB_SAMPLE : R/W; bitpos: [4]; default: 0; + * this bit configures awb sample location, 0:before ccm, 1:after ccm + */ +#define ISP_AWB_SAMPLE (BIT(4)) +#define ISP_AWB_SAMPLE_M (ISP_AWB_SAMPLE_V << ISP_AWB_SAMPLE_S) +#define ISP_AWB_SAMPLE_V 0x00000001U +#define ISP_AWB_SAMPLE_S 4 + +/** ISP_AWB_HSCALE_REG register + * h-scale of awb window + */ +#define ISP_AWB_HSCALE_REG (DR_REG_ISP_BASE + 0x168) +/** ISP_AWB_RPOINT : R/W; bitpos: [11:0]; default: 1919; + * this field configures awb window right coordinate + */ +#define ISP_AWB_RPOINT 0x00000FFFU +#define ISP_AWB_RPOINT_M (ISP_AWB_RPOINT_V << ISP_AWB_RPOINT_S) +#define ISP_AWB_RPOINT_V 0x00000FFFU +#define ISP_AWB_RPOINT_S 0 +/** ISP_AWB_LPOINT : R/W; bitpos: [27:16]; default: 0; + * this field configures awb window left coordinate + */ +#define ISP_AWB_LPOINT 0x00000FFFU +#define ISP_AWB_LPOINT_M (ISP_AWB_LPOINT_V << ISP_AWB_LPOINT_S) +#define ISP_AWB_LPOINT_V 0x00000FFFU +#define ISP_AWB_LPOINT_S 16 + +/** ISP_AWB_VSCALE_REG register + * v-scale of awb window + */ +#define ISP_AWB_VSCALE_REG (DR_REG_ISP_BASE + 0x16c) +/** ISP_AWB_BPOINT : R/W; bitpos: [11:0]; default: 1079; + * this field configures awb window bottom coordinate + */ +#define ISP_AWB_BPOINT 0x00000FFFU +#define ISP_AWB_BPOINT_M (ISP_AWB_BPOINT_V << ISP_AWB_BPOINT_S) +#define ISP_AWB_BPOINT_V 0x00000FFFU +#define ISP_AWB_BPOINT_S 0 +/** ISP_AWB_TPOINT : R/W; bitpos: [27:16]; default: 0; + * this field configures awb window top coordinate + */ +#define ISP_AWB_TPOINT 0x00000FFFU +#define ISP_AWB_TPOINT_M (ISP_AWB_TPOINT_V << ISP_AWB_TPOINT_S) +#define ISP_AWB_TPOINT_V 0x00000FFFU +#define ISP_AWB_TPOINT_S 16 + +/** ISP_AWB_TH_LUM_REG register + * awb lum threshold register + */ +#define ISP_AWB_TH_LUM_REG (DR_REG_ISP_BASE + 0x170) +/** ISP_AWB_MIN_LUM : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of r+g+b + */ +#define ISP_AWB_MIN_LUM 0x000003FFU +#define ISP_AWB_MIN_LUM_M (ISP_AWB_MIN_LUM_V << ISP_AWB_MIN_LUM_S) +#define ISP_AWB_MIN_LUM_V 0x000003FFU +#define ISP_AWB_MIN_LUM_S 0 +/** ISP_AWB_MAX_LUM : R/W; bitpos: [25:16]; default: 765; + * this field configures upper threshold of r+g+b + */ +#define ISP_AWB_MAX_LUM 0x000003FFU +#define ISP_AWB_MAX_LUM_M (ISP_AWB_MAX_LUM_V << ISP_AWB_MAX_LUM_S) +#define ISP_AWB_MAX_LUM_V 0x000003FFU +#define ISP_AWB_MAX_LUM_S 16 + +/** ISP_AWB_TH_RG_REG register + * awb r/g threshold register + */ +#define ISP_AWB_TH_RG_REG (DR_REG_ISP_BASE + 0x174) +/** ISP_AWB_MIN_RG : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of r/g, 2bit integer and 8bit fraction + */ +#define ISP_AWB_MIN_RG 0x000003FFU +#define ISP_AWB_MIN_RG_M (ISP_AWB_MIN_RG_V << ISP_AWB_MIN_RG_S) +#define ISP_AWB_MIN_RG_V 0x000003FFU +#define ISP_AWB_MIN_RG_S 0 +/** ISP_AWB_MAX_RG : R/W; bitpos: [25:16]; default: 1023; + * this field configures upper threshold of r/g, 2bit integer and 8bit fraction + */ +#define ISP_AWB_MAX_RG 0x000003FFU +#define ISP_AWB_MAX_RG_M (ISP_AWB_MAX_RG_V << ISP_AWB_MAX_RG_S) +#define ISP_AWB_MAX_RG_V 0x000003FFU +#define ISP_AWB_MAX_RG_S 16 + +/** ISP_AWB_TH_BG_REG register + * awb b/g threshold register + */ +#define ISP_AWB_TH_BG_REG (DR_REG_ISP_BASE + 0x178) +/** ISP_AWB_MIN_BG : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of b/g, 2bit integer and 8bit fraction + */ +#define ISP_AWB_MIN_BG 0x000003FFU +#define ISP_AWB_MIN_BG_M (ISP_AWB_MIN_BG_V << ISP_AWB_MIN_BG_S) +#define ISP_AWB_MIN_BG_V 0x000003FFU +#define ISP_AWB_MIN_BG_S 0 +/** ISP_AWB_MAX_BG : R/W; bitpos: [25:16]; default: 1023; + * this field configures upper threshold of b/g, 2bit integer and 8bit fraction + */ +#define ISP_AWB_MAX_BG 0x000003FFU +#define ISP_AWB_MAX_BG_M (ISP_AWB_MAX_BG_V << ISP_AWB_MAX_BG_S) +#define ISP_AWB_MAX_BG_V 0x000003FFU +#define ISP_AWB_MAX_BG_S 16 + +/** ISP_AWB0_WHITE_CNT_REG register + * result of awb white point number + */ +#define ISP_AWB0_WHITE_CNT_REG (DR_REG_ISP_BASE + 0x17c) +/** ISP_AWB0_WHITE_CNT : RO; bitpos: [23:0]; default: 0; + * this field configures number of white point detected of algo0 + */ +#define ISP_AWB0_WHITE_CNT 0x00FFFFFFU +#define ISP_AWB0_WHITE_CNT_M (ISP_AWB0_WHITE_CNT_V << ISP_AWB0_WHITE_CNT_S) +#define ISP_AWB0_WHITE_CNT_V 0x00FFFFFFU +#define ISP_AWB0_WHITE_CNT_S 0 + +/** ISP_AWB0_ACC_R_REG register + * result of accumulate of r channel of all white points + */ +#define ISP_AWB0_ACC_R_REG (DR_REG_ISP_BASE + 0x180) +/** ISP_AWB0_ACC_R : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel r of all white point of algo0 + */ +#define ISP_AWB0_ACC_R 0xFFFFFFFFU +#define ISP_AWB0_ACC_R_M (ISP_AWB0_ACC_R_V << ISP_AWB0_ACC_R_S) +#define ISP_AWB0_ACC_R_V 0xFFFFFFFFU +#define ISP_AWB0_ACC_R_S 0 + +/** ISP_AWB0_ACC_G_REG register + * result of accumulate of g channel of all white points + */ +#define ISP_AWB0_ACC_G_REG (DR_REG_ISP_BASE + 0x184) +/** ISP_AWB0_ACC_G : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel g of all white point of algo0 + */ +#define ISP_AWB0_ACC_G 0xFFFFFFFFU +#define ISP_AWB0_ACC_G_M (ISP_AWB0_ACC_G_V << ISP_AWB0_ACC_G_S) +#define ISP_AWB0_ACC_G_V 0xFFFFFFFFU +#define ISP_AWB0_ACC_G_S 0 + +/** ISP_AWB0_ACC_B_REG register + * result of accumulate of b channel of all white points + */ +#define ISP_AWB0_ACC_B_REG (DR_REG_ISP_BASE + 0x188) +/** ISP_AWB0_ACC_B : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel b of all white point of algo0 + */ +#define ISP_AWB0_ACC_B 0xFFFFFFFFU +#define ISP_AWB0_ACC_B_M (ISP_AWB0_ACC_B_V << ISP_AWB0_ACC_B_S) +#define ISP_AWB0_ACC_B_V 0xFFFFFFFFU +#define ISP_AWB0_ACC_B_S 0 + +/** ISP_COLOR_CTRL_REG register + * color control register + */ +#define ISP_COLOR_CTRL_REG (DR_REG_ISP_BASE + 0x18c) +/** ISP_COLOR_SATURATION : R/W; bitpos: [7:0]; default: 128; + * this field configures the color saturation value + */ +#define ISP_COLOR_SATURATION 0x000000FFU +#define ISP_COLOR_SATURATION_M (ISP_COLOR_SATURATION_V << ISP_COLOR_SATURATION_S) +#define ISP_COLOR_SATURATION_V 0x000000FFU +#define ISP_COLOR_SATURATION_S 0 +/** ISP_COLOR_HUE : R/W; bitpos: [15:8]; default: 0; + * this field configures the color hue angle + */ +#define ISP_COLOR_HUE 0x000000FFU +#define ISP_COLOR_HUE_M (ISP_COLOR_HUE_V << ISP_COLOR_HUE_S) +#define ISP_COLOR_HUE_V 0x000000FFU +#define ISP_COLOR_HUE_S 8 +/** ISP_COLOR_CONTRAST : R/W; bitpos: [23:16]; default: 128; + * this field configures the color contrast value + */ +#define ISP_COLOR_CONTRAST 0x000000FFU +#define ISP_COLOR_CONTRAST_M (ISP_COLOR_CONTRAST_V << ISP_COLOR_CONTRAST_S) +#define ISP_COLOR_CONTRAST_V 0x000000FFU +#define ISP_COLOR_CONTRAST_S 16 +/** ISP_COLOR_BRIGHTNESS : R/W; bitpos: [31:24]; default: 0; + * this field configures the color brightness value, signed 2's complement + */ +#define ISP_COLOR_BRIGHTNESS 0x000000FFU +#define ISP_COLOR_BRIGHTNESS_M (ISP_COLOR_BRIGHTNESS_V << ISP_COLOR_BRIGHTNESS_S) +#define ISP_COLOR_BRIGHTNESS_V 0x000000FFU +#define ISP_COLOR_BRIGHTNESS_S 24 + +/** ISP_BLC_VALUE_REG register + * blc black level register + */ +#define ISP_BLC_VALUE_REG (DR_REG_ISP_BASE + 0x190) +/** ISP_BLC_R3_VALUE : R/W; bitpos: [7:0]; default: 0; + * this field configures the black level of bottom right channel of bayer img + */ +#define ISP_BLC_R3_VALUE 0x000000FFU +#define ISP_BLC_R3_VALUE_M (ISP_BLC_R3_VALUE_V << ISP_BLC_R3_VALUE_S) +#define ISP_BLC_R3_VALUE_V 0x000000FFU +#define ISP_BLC_R3_VALUE_S 0 +/** ISP_BLC_R2_VALUE : R/W; bitpos: [15:8]; default: 0; + * this field configures the black level of bottom left channel of bayer img + */ +#define ISP_BLC_R2_VALUE 0x000000FFU +#define ISP_BLC_R2_VALUE_M (ISP_BLC_R2_VALUE_V << ISP_BLC_R2_VALUE_S) +#define ISP_BLC_R2_VALUE_V 0x000000FFU +#define ISP_BLC_R2_VALUE_S 8 +/** ISP_BLC_R1_VALUE : R/W; bitpos: [23:16]; default: 0; + * this field configures the black level of top right channel of bayer img + */ +#define ISP_BLC_R1_VALUE 0x000000FFU +#define ISP_BLC_R1_VALUE_M (ISP_BLC_R1_VALUE_V << ISP_BLC_R1_VALUE_S) +#define ISP_BLC_R1_VALUE_V 0x000000FFU +#define ISP_BLC_R1_VALUE_S 16 +/** ISP_BLC_R0_VALUE : R/W; bitpos: [31:24]; default: 0; + * this field configures the black level of top left channel of bayer img + */ +#define ISP_BLC_R0_VALUE 0x000000FFU +#define ISP_BLC_R0_VALUE_M (ISP_BLC_R0_VALUE_V << ISP_BLC_R0_VALUE_S) +#define ISP_BLC_R0_VALUE_V 0x000000FFU +#define ISP_BLC_R0_VALUE_S 24 + +/** ISP_BLC_CTRL0_REG register + * blc stretch control register + */ +#define ISP_BLC_CTRL0_REG (DR_REG_ISP_BASE + 0x194) +/** ISP_BLC_R3_STRETCH : R/W; bitpos: [0]; default: 0; + * this bit configures the stretch feature of bottom right channel. 0: stretch + * disable, 1: stretch enable + */ +#define ISP_BLC_R3_STRETCH (BIT(0)) +#define ISP_BLC_R3_STRETCH_M (ISP_BLC_R3_STRETCH_V << ISP_BLC_R3_STRETCH_S) +#define ISP_BLC_R3_STRETCH_V 0x00000001U +#define ISP_BLC_R3_STRETCH_S 0 +/** ISP_BLC_R2_STRETCH : R/W; bitpos: [1]; default: 0; + * this bit configures the stretch feature of bottom left channel. 0: stretch disable, + * 1: stretch enable + */ +#define ISP_BLC_R2_STRETCH (BIT(1)) +#define ISP_BLC_R2_STRETCH_M (ISP_BLC_R2_STRETCH_V << ISP_BLC_R2_STRETCH_S) +#define ISP_BLC_R2_STRETCH_V 0x00000001U +#define ISP_BLC_R2_STRETCH_S 1 +/** ISP_BLC_R1_STRETCH : R/W; bitpos: [2]; default: 0; + * this bit configures the stretch feature of top right channel. 0: stretch disable, + * 1: stretch enable + */ +#define ISP_BLC_R1_STRETCH (BIT(2)) +#define ISP_BLC_R1_STRETCH_M (ISP_BLC_R1_STRETCH_V << ISP_BLC_R1_STRETCH_S) +#define ISP_BLC_R1_STRETCH_V 0x00000001U +#define ISP_BLC_R1_STRETCH_S 2 +/** ISP_BLC_R0_STRETCH : R/W; bitpos: [3]; default: 0; + * this bit configures the stretch feature of top left channel. 0: stretch disable, 1: + * stretch enable + */ +#define ISP_BLC_R0_STRETCH (BIT(3)) +#define ISP_BLC_R0_STRETCH_M (ISP_BLC_R0_STRETCH_V << ISP_BLC_R0_STRETCH_S) +#define ISP_BLC_R0_STRETCH_V 0x00000001U +#define ISP_BLC_R0_STRETCH_S 3 + +/** ISP_BLC_CTRL1_REG register + * blc window control register + */ +#define ISP_BLC_CTRL1_REG (DR_REG_ISP_BASE + 0x198) +/** ISP_BLC_WINDOW_TOP : R/W; bitpos: [10:0]; default: 0; + * this field configures blc average calculation window top + */ +#define ISP_BLC_WINDOW_TOP 0x000007FFU +#define ISP_BLC_WINDOW_TOP_M (ISP_BLC_WINDOW_TOP_V << ISP_BLC_WINDOW_TOP_S) +#define ISP_BLC_WINDOW_TOP_V 0x000007FFU +#define ISP_BLC_WINDOW_TOP_S 0 +/** ISP_BLC_WINDOW_LEFT : R/W; bitpos: [21:11]; default: 0; + * this field configures blc average calculation window left + */ +#define ISP_BLC_WINDOW_LEFT 0x000007FFU +#define ISP_BLC_WINDOW_LEFT_M (ISP_BLC_WINDOW_LEFT_V << ISP_BLC_WINDOW_LEFT_S) +#define ISP_BLC_WINDOW_LEFT_V 0x000007FFU +#define ISP_BLC_WINDOW_LEFT_S 11 +/** ISP_BLC_WINDOW_VNUM : R/W; bitpos: [25:22]; default: 0; + * this field configures blc average calculation window vnum + */ +#define ISP_BLC_WINDOW_VNUM 0x0000000FU +#define ISP_BLC_WINDOW_VNUM_M (ISP_BLC_WINDOW_VNUM_V << ISP_BLC_WINDOW_VNUM_S) +#define ISP_BLC_WINDOW_VNUM_V 0x0000000FU +#define ISP_BLC_WINDOW_VNUM_S 22 +/** ISP_BLC_WINDOW_HNUM : R/W; bitpos: [29:26]; default: 0; + * this field configures blc average calculation window hnum + */ +#define ISP_BLC_WINDOW_HNUM 0x0000000FU +#define ISP_BLC_WINDOW_HNUM_M (ISP_BLC_WINDOW_HNUM_V << ISP_BLC_WINDOW_HNUM_S) +#define ISP_BLC_WINDOW_HNUM_V 0x0000000FU +#define ISP_BLC_WINDOW_HNUM_S 26 +/** ISP_BLC_FILTER_EN : R/W; bitpos: [30]; default: 0; + * this bit configures enable blc average input filter. 0: disable, 1: enable + */ +#define ISP_BLC_FILTER_EN (BIT(30)) +#define ISP_BLC_FILTER_EN_M (ISP_BLC_FILTER_EN_V << ISP_BLC_FILTER_EN_S) +#define ISP_BLC_FILTER_EN_V 0x00000001U +#define ISP_BLC_FILTER_EN_S 30 + +/** ISP_BLC_CTRL2_REG register + * blc black threshold control register + */ +#define ISP_BLC_CTRL2_REG (DR_REG_ISP_BASE + 0x19c) +/** ISP_BLC_R3_TH : R/W; bitpos: [7:0]; default: 0; + * this field configures black threshold when get blc average of bottom right channel + */ +#define ISP_BLC_R3_TH 0x000000FFU +#define ISP_BLC_R3_TH_M (ISP_BLC_R3_TH_V << ISP_BLC_R3_TH_S) +#define ISP_BLC_R3_TH_V 0x000000FFU +#define ISP_BLC_R3_TH_S 0 +/** ISP_BLC_R2_TH : R/W; bitpos: [15:8]; default: 0; + * this field configures black threshold when get blc average of bottom left channel + */ +#define ISP_BLC_R2_TH 0x000000FFU +#define ISP_BLC_R2_TH_M (ISP_BLC_R2_TH_V << ISP_BLC_R2_TH_S) +#define ISP_BLC_R2_TH_V 0x000000FFU +#define ISP_BLC_R2_TH_S 8 +/** ISP_BLC_R1_TH : R/W; bitpos: [23:16]; default: 0; + * this field configures black threshold when get blc average of top right channel + */ +#define ISP_BLC_R1_TH 0x000000FFU +#define ISP_BLC_R1_TH_M (ISP_BLC_R1_TH_V << ISP_BLC_R1_TH_S) +#define ISP_BLC_R1_TH_V 0x000000FFU +#define ISP_BLC_R1_TH_S 16 +/** ISP_BLC_R0_TH : R/W; bitpos: [31:24]; default: 0; + * this field configures black threshold when get blc average of top left channel + */ +#define ISP_BLC_R0_TH 0x000000FFU +#define ISP_BLC_R0_TH_M (ISP_BLC_R0_TH_V << ISP_BLC_R0_TH_S) +#define ISP_BLC_R0_TH_V 0x000000FFU +#define ISP_BLC_R0_TH_S 24 + +/** ISP_BLC_MEAN_REG register + * results of the average of black window + */ +#define ISP_BLC_MEAN_REG (DR_REG_ISP_BASE + 0x1a0) +/** ISP_BLC_R3_MEAN : RO; bitpos: [7:0]; default: 0; + * this field represents the average black value of bottom right channel + */ +#define ISP_BLC_R3_MEAN 0x000000FFU +#define ISP_BLC_R3_MEAN_M (ISP_BLC_R3_MEAN_V << ISP_BLC_R3_MEAN_S) +#define ISP_BLC_R3_MEAN_V 0x000000FFU +#define ISP_BLC_R3_MEAN_S 0 +/** ISP_BLC_R2_MEAN : RO; bitpos: [15:8]; default: 0; + * this field represents the average black value of bottom left channel + */ +#define ISP_BLC_R2_MEAN 0x000000FFU +#define ISP_BLC_R2_MEAN_M (ISP_BLC_R2_MEAN_V << ISP_BLC_R2_MEAN_S) +#define ISP_BLC_R2_MEAN_V 0x000000FFU +#define ISP_BLC_R2_MEAN_S 8 +/** ISP_BLC_R1_MEAN : RO; bitpos: [23:16]; default: 0; + * this field represents the average black value of top right channel + */ +#define ISP_BLC_R1_MEAN 0x000000FFU +#define ISP_BLC_R1_MEAN_M (ISP_BLC_R1_MEAN_V << ISP_BLC_R1_MEAN_S) +#define ISP_BLC_R1_MEAN_V 0x000000FFU +#define ISP_BLC_R1_MEAN_S 16 +/** ISP_BLC_R0_MEAN : RO; bitpos: [31:24]; default: 0; + * this field represents the average black value of top left channel + */ +#define ISP_BLC_R0_MEAN 0x000000FFU +#define ISP_BLC_R0_MEAN_M (ISP_BLC_R0_MEAN_V << ISP_BLC_R0_MEAN_S) +#define ISP_BLC_R0_MEAN_V 0x000000FFU +#define ISP_BLC_R0_MEAN_S 24 + +/** ISP_HIST_MODE_REG register + * histogram mode control register + */ +#define ISP_HIST_MODE_REG (DR_REG_ISP_BASE + 0x1a4) +/** ISP_HIST_MODE : R/W; bitpos: [2:0]; default: 4; + * this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: + * RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V + */ +#define ISP_HIST_MODE 0x00000007U +#define ISP_HIST_MODE_M (ISP_HIST_MODE_V << ISP_HIST_MODE_S) +#define ISP_HIST_MODE_V 0x00000007U +#define ISP_HIST_MODE_S 0 + +/** ISP_HIST_COEFF_REG register + * histogram rgb to gray coefficients register + */ +#define ISP_HIST_COEFF_REG (DR_REG_ISP_BASE + 0x1a8) +/** ISP_HIST_COEFF_B : R/W; bitpos: [7:0]; default: 85; + * this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ +#define ISP_HIST_COEFF_B 0x000000FFU +#define ISP_HIST_COEFF_B_M (ISP_HIST_COEFF_B_V << ISP_HIST_COEFF_B_S) +#define ISP_HIST_COEFF_B_V 0x000000FFU +#define ISP_HIST_COEFF_B_S 0 +/** ISP_HIST_COEFF_G : R/W; bitpos: [15:8]; default: 85; + * this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ +#define ISP_HIST_COEFF_G 0x000000FFU +#define ISP_HIST_COEFF_G_M (ISP_HIST_COEFF_G_V << ISP_HIST_COEFF_G_S) +#define ISP_HIST_COEFF_G_V 0x000000FFU +#define ISP_HIST_COEFF_G_S 8 +/** ISP_HIST_COEFF_R : R/W; bitpos: [23:16]; default: 85; + * this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ +#define ISP_HIST_COEFF_R 0x000000FFU +#define ISP_HIST_COEFF_R_M (ISP_HIST_COEFF_R_V << ISP_HIST_COEFF_R_S) +#define ISP_HIST_COEFF_R_V 0x000000FFU +#define ISP_HIST_COEFF_R_S 16 + +/** ISP_HIST_OFFS_REG register + * histogram window offsets register + */ +#define ISP_HIST_OFFS_REG (DR_REG_ISP_BASE + 0x1ac) +/** ISP_HIST_Y_OFFS : R/W; bitpos: [11:0]; default: 0; + * this field configures y coordinate of first window + */ +#define ISP_HIST_Y_OFFS 0x00000FFFU +#define ISP_HIST_Y_OFFS_M (ISP_HIST_Y_OFFS_V << ISP_HIST_Y_OFFS_S) +#define ISP_HIST_Y_OFFS_V 0x00000FFFU +#define ISP_HIST_Y_OFFS_S 0 +/** ISP_HIST_X_OFFS : R/W; bitpos: [27:16]; default: 0; + * this field configures x coordinate of first window + */ +#define ISP_HIST_X_OFFS 0x00000FFFU +#define ISP_HIST_X_OFFS_M (ISP_HIST_X_OFFS_V << ISP_HIST_X_OFFS_S) +#define ISP_HIST_X_OFFS_V 0x00000FFFU +#define ISP_HIST_X_OFFS_S 16 + +/** ISP_HIST_SIZE_REG register + * histogram sub-window size register + */ +#define ISP_HIST_SIZE_REG (DR_REG_ISP_BASE + 0x1b0) +/** ISP_HIST_Y_SIZE : R/W; bitpos: [8:0]; default: 32; + * this field configures y direction size of subwindow + */ +#define ISP_HIST_Y_SIZE 0x000001FFU +#define ISP_HIST_Y_SIZE_M (ISP_HIST_Y_SIZE_V << ISP_HIST_Y_SIZE_S) +#define ISP_HIST_Y_SIZE_V 0x000001FFU +#define ISP_HIST_Y_SIZE_S 0 +/** ISP_HIST_X_SIZE : R/W; bitpos: [24:16]; default: 18; + * this field configures x direction size of subwindow + */ +#define ISP_HIST_X_SIZE 0x000001FFU +#define ISP_HIST_X_SIZE_M (ISP_HIST_X_SIZE_V << ISP_HIST_X_SIZE_S) +#define ISP_HIST_X_SIZE_V 0x000001FFU +#define ISP_HIST_X_SIZE_S 16 + +/** ISP_HIST_SEG0_REG register + * histogram bin control register 0 + */ +#define ISP_HIST_SEG0_REG (DR_REG_ISP_BASE + 0x1b4) +/** ISP_HIST_SEG_3_4 : R/W; bitpos: [7:0]; default: 64; + * this field configures threshold of histogram bin 3 and bin 4 + */ +#define ISP_HIST_SEG_3_4 0x000000FFU +#define ISP_HIST_SEG_3_4_M (ISP_HIST_SEG_3_4_V << ISP_HIST_SEG_3_4_S) +#define ISP_HIST_SEG_3_4_V 0x000000FFU +#define ISP_HIST_SEG_3_4_S 0 +/** ISP_HIST_SEG_2_3 : R/W; bitpos: [15:8]; default: 48; + * this field configures threshold of histogram bin 2 and bin 3 + */ +#define ISP_HIST_SEG_2_3 0x000000FFU +#define ISP_HIST_SEG_2_3_M (ISP_HIST_SEG_2_3_V << ISP_HIST_SEG_2_3_S) +#define ISP_HIST_SEG_2_3_V 0x000000FFU +#define ISP_HIST_SEG_2_3_S 8 +/** ISP_HIST_SEG_1_2 : R/W; bitpos: [23:16]; default: 32; + * this field configures threshold of histogram bin 1 and bin 2 + */ +#define ISP_HIST_SEG_1_2 0x000000FFU +#define ISP_HIST_SEG_1_2_M (ISP_HIST_SEG_1_2_V << ISP_HIST_SEG_1_2_S) +#define ISP_HIST_SEG_1_2_V 0x000000FFU +#define ISP_HIST_SEG_1_2_S 16 +/** ISP_HIST_SEG_0_1 : R/W; bitpos: [31:24]; default: 16; + * this field configures threshold of histogram bin 0 and bin 1 + */ +#define ISP_HIST_SEG_0_1 0x000000FFU +#define ISP_HIST_SEG_0_1_M (ISP_HIST_SEG_0_1_V << ISP_HIST_SEG_0_1_S) +#define ISP_HIST_SEG_0_1_V 0x000000FFU +#define ISP_HIST_SEG_0_1_S 24 + +/** ISP_HIST_SEG1_REG register + * histogram bin control register 1 + */ +#define ISP_HIST_SEG1_REG (DR_REG_ISP_BASE + 0x1b8) +/** ISP_HIST_SEG_7_8 : R/W; bitpos: [7:0]; default: 128; + * this field configures threshold of histogram bin 7 and bin 8 + */ +#define ISP_HIST_SEG_7_8 0x000000FFU +#define ISP_HIST_SEG_7_8_M (ISP_HIST_SEG_7_8_V << ISP_HIST_SEG_7_8_S) +#define ISP_HIST_SEG_7_8_V 0x000000FFU +#define ISP_HIST_SEG_7_8_S 0 +/** ISP_HIST_SEG_6_7 : R/W; bitpos: [15:8]; default: 112; + * this field configures threshold of histogram bin 6 and bin 7 + */ +#define ISP_HIST_SEG_6_7 0x000000FFU +#define ISP_HIST_SEG_6_7_M (ISP_HIST_SEG_6_7_V << ISP_HIST_SEG_6_7_S) +#define ISP_HIST_SEG_6_7_V 0x000000FFU +#define ISP_HIST_SEG_6_7_S 8 +/** ISP_HIST_SEG_5_6 : R/W; bitpos: [23:16]; default: 96; + * this field configures threshold of histogram bin 5 and bin 6 + */ +#define ISP_HIST_SEG_5_6 0x000000FFU +#define ISP_HIST_SEG_5_6_M (ISP_HIST_SEG_5_6_V << ISP_HIST_SEG_5_6_S) +#define ISP_HIST_SEG_5_6_V 0x000000FFU +#define ISP_HIST_SEG_5_6_S 16 +/** ISP_HIST_SEG_4_5 : R/W; bitpos: [31:24]; default: 80; + * this field configures threshold of histogram bin 4 and bin 5 + */ +#define ISP_HIST_SEG_4_5 0x000000FFU +#define ISP_HIST_SEG_4_5_M (ISP_HIST_SEG_4_5_V << ISP_HIST_SEG_4_5_S) +#define ISP_HIST_SEG_4_5_V 0x000000FFU +#define ISP_HIST_SEG_4_5_S 24 + +/** ISP_HIST_SEG2_REG register + * histogram bin control register 2 + */ +#define ISP_HIST_SEG2_REG (DR_REG_ISP_BASE + 0x1bc) +/** ISP_HIST_SEG_11_12 : R/W; bitpos: [7:0]; default: 192; + * this field configures threshold of histogram bin 11 and bin 12 + */ +#define ISP_HIST_SEG_11_12 0x000000FFU +#define ISP_HIST_SEG_11_12_M (ISP_HIST_SEG_11_12_V << ISP_HIST_SEG_11_12_S) +#define ISP_HIST_SEG_11_12_V 0x000000FFU +#define ISP_HIST_SEG_11_12_S 0 +/** ISP_HIST_SEG_10_11 : R/W; bitpos: [15:8]; default: 176; + * this field configures threshold of histogram bin 10 and bin 11 + */ +#define ISP_HIST_SEG_10_11 0x000000FFU +#define ISP_HIST_SEG_10_11_M (ISP_HIST_SEG_10_11_V << ISP_HIST_SEG_10_11_S) +#define ISP_HIST_SEG_10_11_V 0x000000FFU +#define ISP_HIST_SEG_10_11_S 8 +/** ISP_HIST_SEG_9_10 : R/W; bitpos: [23:16]; default: 160; + * this field configures threshold of histogram bin 9 and bin 10 + */ +#define ISP_HIST_SEG_9_10 0x000000FFU +#define ISP_HIST_SEG_9_10_M (ISP_HIST_SEG_9_10_V << ISP_HIST_SEG_9_10_S) +#define ISP_HIST_SEG_9_10_V 0x000000FFU +#define ISP_HIST_SEG_9_10_S 16 +/** ISP_HIST_SEG_8_9 : R/W; bitpos: [31:24]; default: 144; + * this field configures threshold of histogram bin 8 and bin 9 + */ +#define ISP_HIST_SEG_8_9 0x000000FFU +#define ISP_HIST_SEG_8_9_M (ISP_HIST_SEG_8_9_V << ISP_HIST_SEG_8_9_S) +#define ISP_HIST_SEG_8_9_V 0x000000FFU +#define ISP_HIST_SEG_8_9_S 24 + +/** ISP_HIST_SEG3_REG register + * histogram bin control register 3 + */ +#define ISP_HIST_SEG3_REG (DR_REG_ISP_BASE + 0x1c0) +/** ISP_HIST_SEG_14_15 : R/W; bitpos: [7:0]; default: 240; + * this field configures threshold of histogram bin 14 and bin 15 + */ +#define ISP_HIST_SEG_14_15 0x000000FFU +#define ISP_HIST_SEG_14_15_M (ISP_HIST_SEG_14_15_V << ISP_HIST_SEG_14_15_S) +#define ISP_HIST_SEG_14_15_V 0x000000FFU +#define ISP_HIST_SEG_14_15_S 0 +/** ISP_HIST_SEG_13_14 : R/W; bitpos: [15:8]; default: 224; + * this field configures threshold of histogram bin 13 and bin 14 + */ +#define ISP_HIST_SEG_13_14 0x000000FFU +#define ISP_HIST_SEG_13_14_M (ISP_HIST_SEG_13_14_V << ISP_HIST_SEG_13_14_S) +#define ISP_HIST_SEG_13_14_V 0x000000FFU +#define ISP_HIST_SEG_13_14_S 8 +/** ISP_HIST_SEG_12_13 : R/W; bitpos: [23:16]; default: 208; + * this field configures threshold of histogram bin 12 and bin 13 + */ +#define ISP_HIST_SEG_12_13 0x000000FFU +#define ISP_HIST_SEG_12_13_M (ISP_HIST_SEG_12_13_V << ISP_HIST_SEG_12_13_S) +#define ISP_HIST_SEG_12_13_V 0x000000FFU +#define ISP_HIST_SEG_12_13_S 16 + +/** ISP_HIST_WEIGHT0_REG register + * histogram sub-window weight register 0 + */ +#define ISP_HIST_WEIGHT0_REG (DR_REG_ISP_BASE + 0x1c4) +/** ISP_HIST_WEIGHT_03 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 03 + */ +#define ISP_HIST_WEIGHT_03 0x000000FFU +#define ISP_HIST_WEIGHT_03_M (ISP_HIST_WEIGHT_03_V << ISP_HIST_WEIGHT_03_S) +#define ISP_HIST_WEIGHT_03_V 0x000000FFU +#define ISP_HIST_WEIGHT_03_S 0 +/** ISP_HIST_WEIGHT_02 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 02 + */ +#define ISP_HIST_WEIGHT_02 0x000000FFU +#define ISP_HIST_WEIGHT_02_M (ISP_HIST_WEIGHT_02_V << ISP_HIST_WEIGHT_02_S) +#define ISP_HIST_WEIGHT_02_V 0x000000FFU +#define ISP_HIST_WEIGHT_02_S 8 +/** ISP_HIST_WEIGHT_01 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 01 + */ +#define ISP_HIST_WEIGHT_01 0x000000FFU +#define ISP_HIST_WEIGHT_01_M (ISP_HIST_WEIGHT_01_V << ISP_HIST_WEIGHT_01_S) +#define ISP_HIST_WEIGHT_01_V 0x000000FFU +#define ISP_HIST_WEIGHT_01_S 16 +/** ISP_HIST_WEIGHT_00 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 00 and sum of all weight should be 256 + */ +#define ISP_HIST_WEIGHT_00 0x000000FFU +#define ISP_HIST_WEIGHT_00_M (ISP_HIST_WEIGHT_00_V << ISP_HIST_WEIGHT_00_S) +#define ISP_HIST_WEIGHT_00_V 0x000000FFU +#define ISP_HIST_WEIGHT_00_S 24 + +/** ISP_HIST_WEIGHT1_REG register + * histogram sub-window weight register 1 + */ +#define ISP_HIST_WEIGHT1_REG (DR_REG_ISP_BASE + 0x1c8) +/** ISP_HIST_WEIGHT_12 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 12 + */ +#define ISP_HIST_WEIGHT_12 0x000000FFU +#define ISP_HIST_WEIGHT_12_M (ISP_HIST_WEIGHT_12_V << ISP_HIST_WEIGHT_12_S) +#define ISP_HIST_WEIGHT_12_V 0x000000FFU +#define ISP_HIST_WEIGHT_12_S 0 +/** ISP_HIST_WEIGHT_11 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 11 + */ +#define ISP_HIST_WEIGHT_11 0x000000FFU +#define ISP_HIST_WEIGHT_11_M (ISP_HIST_WEIGHT_11_V << ISP_HIST_WEIGHT_11_S) +#define ISP_HIST_WEIGHT_11_V 0x000000FFU +#define ISP_HIST_WEIGHT_11_S 8 +/** ISP_HIST_WEIGHT_10 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 10 + */ +#define ISP_HIST_WEIGHT_10 0x000000FFU +#define ISP_HIST_WEIGHT_10_M (ISP_HIST_WEIGHT_10_V << ISP_HIST_WEIGHT_10_S) +#define ISP_HIST_WEIGHT_10_V 0x000000FFU +#define ISP_HIST_WEIGHT_10_S 16 +/** ISP_HIST_WEIGHT_04 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 04 + */ +#define ISP_HIST_WEIGHT_04 0x000000FFU +#define ISP_HIST_WEIGHT_04_M (ISP_HIST_WEIGHT_04_V << ISP_HIST_WEIGHT_04_S) +#define ISP_HIST_WEIGHT_04_V 0x000000FFU +#define ISP_HIST_WEIGHT_04_S 24 + +/** ISP_HIST_WEIGHT2_REG register + * histogram sub-window weight register 2 + */ +#define ISP_HIST_WEIGHT2_REG (DR_REG_ISP_BASE + 0x1cc) +/** ISP_HIST_WEIGHT_21 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 21 + */ +#define ISP_HIST_WEIGHT_21 0x000000FFU +#define ISP_HIST_WEIGHT_21_M (ISP_HIST_WEIGHT_21_V << ISP_HIST_WEIGHT_21_S) +#define ISP_HIST_WEIGHT_21_V 0x000000FFU +#define ISP_HIST_WEIGHT_21_S 0 +/** ISP_HIST_WEIGHT_20 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 20 + */ +#define ISP_HIST_WEIGHT_20 0x000000FFU +#define ISP_HIST_WEIGHT_20_M (ISP_HIST_WEIGHT_20_V << ISP_HIST_WEIGHT_20_S) +#define ISP_HIST_WEIGHT_20_V 0x000000FFU +#define ISP_HIST_WEIGHT_20_S 8 +/** ISP_HIST_WEIGHT_14 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 04 + */ +#define ISP_HIST_WEIGHT_14 0x000000FFU +#define ISP_HIST_WEIGHT_14_M (ISP_HIST_WEIGHT_14_V << ISP_HIST_WEIGHT_14_S) +#define ISP_HIST_WEIGHT_14_V 0x000000FFU +#define ISP_HIST_WEIGHT_14_S 16 +/** ISP_HIST_WEIGHT_13 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 13 + */ +#define ISP_HIST_WEIGHT_13 0x000000FFU +#define ISP_HIST_WEIGHT_13_M (ISP_HIST_WEIGHT_13_V << ISP_HIST_WEIGHT_13_S) +#define ISP_HIST_WEIGHT_13_V 0x000000FFU +#define ISP_HIST_WEIGHT_13_S 24 + +/** ISP_HIST_WEIGHT3_REG register + * histogram sub-window weight register 3 + */ +#define ISP_HIST_WEIGHT3_REG (DR_REG_ISP_BASE + 0x1d0) +/** ISP_HIST_WEIGHT_30 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 30 + */ +#define ISP_HIST_WEIGHT_30 0x000000FFU +#define ISP_HIST_WEIGHT_30_M (ISP_HIST_WEIGHT_30_V << ISP_HIST_WEIGHT_30_S) +#define ISP_HIST_WEIGHT_30_V 0x000000FFU +#define ISP_HIST_WEIGHT_30_S 0 +/** ISP_HIST_WEIGHT_24 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 24 + */ +#define ISP_HIST_WEIGHT_24 0x000000FFU +#define ISP_HIST_WEIGHT_24_M (ISP_HIST_WEIGHT_24_V << ISP_HIST_WEIGHT_24_S) +#define ISP_HIST_WEIGHT_24_V 0x000000FFU +#define ISP_HIST_WEIGHT_24_S 8 +/** ISP_HIST_WEIGHT_23 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 23 + */ +#define ISP_HIST_WEIGHT_23 0x000000FFU +#define ISP_HIST_WEIGHT_23_M (ISP_HIST_WEIGHT_23_V << ISP_HIST_WEIGHT_23_S) +#define ISP_HIST_WEIGHT_23_V 0x000000FFU +#define ISP_HIST_WEIGHT_23_S 16 +/** ISP_HIST_WEIGHT_22 : R/W; bitpos: [31:24]; default: 232; + * this field configures weight of subwindow 22 + */ +#define ISP_HIST_WEIGHT_22 0x000000FFU +#define ISP_HIST_WEIGHT_22_M (ISP_HIST_WEIGHT_22_V << ISP_HIST_WEIGHT_22_S) +#define ISP_HIST_WEIGHT_22_V 0x000000FFU +#define ISP_HIST_WEIGHT_22_S 24 + +/** ISP_HIST_WEIGHT4_REG register + * histogram sub-window weight register 4 + */ +#define ISP_HIST_WEIGHT4_REG (DR_REG_ISP_BASE + 0x1d4) +/** ISP_HIST_WEIGHT_34 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 34 + */ +#define ISP_HIST_WEIGHT_34 0x000000FFU +#define ISP_HIST_WEIGHT_34_M (ISP_HIST_WEIGHT_34_V << ISP_HIST_WEIGHT_34_S) +#define ISP_HIST_WEIGHT_34_V 0x000000FFU +#define ISP_HIST_WEIGHT_34_S 0 +/** ISP_HIST_WEIGHT_33 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 33 + */ +#define ISP_HIST_WEIGHT_33 0x000000FFU +#define ISP_HIST_WEIGHT_33_M (ISP_HIST_WEIGHT_33_V << ISP_HIST_WEIGHT_33_S) +#define ISP_HIST_WEIGHT_33_V 0x000000FFU +#define ISP_HIST_WEIGHT_33_S 8 +/** ISP_HIST_WEIGHT_32 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 32 + */ +#define ISP_HIST_WEIGHT_32 0x000000FFU +#define ISP_HIST_WEIGHT_32_M (ISP_HIST_WEIGHT_32_V << ISP_HIST_WEIGHT_32_S) +#define ISP_HIST_WEIGHT_32_V 0x000000FFU +#define ISP_HIST_WEIGHT_32_S 16 +/** ISP_HIST_WEIGHT_31 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 31 + */ +#define ISP_HIST_WEIGHT_31 0x000000FFU +#define ISP_HIST_WEIGHT_31_M (ISP_HIST_WEIGHT_31_V << ISP_HIST_WEIGHT_31_S) +#define ISP_HIST_WEIGHT_31_V 0x000000FFU +#define ISP_HIST_WEIGHT_31_S 24 + +/** ISP_HIST_WEIGHT5_REG register + * histogram sub-window weight register 5 + */ +#define ISP_HIST_WEIGHT5_REG (DR_REG_ISP_BASE + 0x1d8) +/** ISP_HIST_WEIGHT_43 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 43 + */ +#define ISP_HIST_WEIGHT_43 0x000000FFU +#define ISP_HIST_WEIGHT_43_M (ISP_HIST_WEIGHT_43_V << ISP_HIST_WEIGHT_43_S) +#define ISP_HIST_WEIGHT_43_V 0x000000FFU +#define ISP_HIST_WEIGHT_43_S 0 +/** ISP_HIST_WEIGHT_42 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 42 + */ +#define ISP_HIST_WEIGHT_42 0x000000FFU +#define ISP_HIST_WEIGHT_42_M (ISP_HIST_WEIGHT_42_V << ISP_HIST_WEIGHT_42_S) +#define ISP_HIST_WEIGHT_42_V 0x000000FFU +#define ISP_HIST_WEIGHT_42_S 8 +/** ISP_HIST_WEIGHT_41 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 41 + */ +#define ISP_HIST_WEIGHT_41 0x000000FFU +#define ISP_HIST_WEIGHT_41_M (ISP_HIST_WEIGHT_41_V << ISP_HIST_WEIGHT_41_S) +#define ISP_HIST_WEIGHT_41_V 0x000000FFU +#define ISP_HIST_WEIGHT_41_S 16 +/** ISP_HIST_WEIGHT_40 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 40 + */ +#define ISP_HIST_WEIGHT_40 0x000000FFU +#define ISP_HIST_WEIGHT_40_M (ISP_HIST_WEIGHT_40_V << ISP_HIST_WEIGHT_40_S) +#define ISP_HIST_WEIGHT_40_V 0x000000FFU +#define ISP_HIST_WEIGHT_40_S 24 + +/** ISP_HIST_WEIGHT6_REG register + * histogram sub-window weight register 6 + */ +#define ISP_HIST_WEIGHT6_REG (DR_REG_ISP_BASE + 0x1dc) +/** ISP_HIST_WEIGHT_44 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 44 + */ +#define ISP_HIST_WEIGHT_44 0x000000FFU +#define ISP_HIST_WEIGHT_44_M (ISP_HIST_WEIGHT_44_V << ISP_HIST_WEIGHT_44_S) +#define ISP_HIST_WEIGHT_44_V 0x000000FFU +#define ISP_HIST_WEIGHT_44_S 0 + +/** ISP_HIST_BIN0_REG register + * result of histogram bin 0 + */ +#define ISP_HIST_BIN0_REG (DR_REG_ISP_BASE + 0x1e0) +/** ISP_HIST_BIN_0 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 0 + */ +#define ISP_HIST_BIN_0 0x0001FFFFU +#define ISP_HIST_BIN_0_M (ISP_HIST_BIN_0_V << ISP_HIST_BIN_0_S) +#define ISP_HIST_BIN_0_V 0x0001FFFFU +#define ISP_HIST_BIN_0_S 0 + +/** ISP_HIST_BIN1_REG register + * result of histogram bin 1 + */ +#define ISP_HIST_BIN1_REG (DR_REG_ISP_BASE + 0x1e4) +/** ISP_HIST_BIN_1 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 1 + */ +#define ISP_HIST_BIN_1 0x0001FFFFU +#define ISP_HIST_BIN_1_M (ISP_HIST_BIN_1_V << ISP_HIST_BIN_1_S) +#define ISP_HIST_BIN_1_V 0x0001FFFFU +#define ISP_HIST_BIN_1_S 0 + +/** ISP_HIST_BIN2_REG register + * result of histogram bin 2 + */ +#define ISP_HIST_BIN2_REG (DR_REG_ISP_BASE + 0x1e8) +/** ISP_HIST_BIN_2 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 2 + */ +#define ISP_HIST_BIN_2 0x0001FFFFU +#define ISP_HIST_BIN_2_M (ISP_HIST_BIN_2_V << ISP_HIST_BIN_2_S) +#define ISP_HIST_BIN_2_V 0x0001FFFFU +#define ISP_HIST_BIN_2_S 0 + +/** ISP_HIST_BIN3_REG register + * result of histogram bin 3 + */ +#define ISP_HIST_BIN3_REG (DR_REG_ISP_BASE + 0x1ec) +/** ISP_HIST_BIN_3 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 3 + */ +#define ISP_HIST_BIN_3 0x0001FFFFU +#define ISP_HIST_BIN_3_M (ISP_HIST_BIN_3_V << ISP_HIST_BIN_3_S) +#define ISP_HIST_BIN_3_V 0x0001FFFFU +#define ISP_HIST_BIN_3_S 0 + +/** ISP_HIST_BIN4_REG register + * result of histogram bin 4 + */ +#define ISP_HIST_BIN4_REG (DR_REG_ISP_BASE + 0x1f0) +/** ISP_HIST_BIN_4 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 4 + */ +#define ISP_HIST_BIN_4 0x0001FFFFU +#define ISP_HIST_BIN_4_M (ISP_HIST_BIN_4_V << ISP_HIST_BIN_4_S) +#define ISP_HIST_BIN_4_V 0x0001FFFFU +#define ISP_HIST_BIN_4_S 0 + +/** ISP_HIST_BIN5_REG register + * result of histogram bin 5 + */ +#define ISP_HIST_BIN5_REG (DR_REG_ISP_BASE + 0x1f4) +/** ISP_HIST_BIN_5 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 5 + */ +#define ISP_HIST_BIN_5 0x0001FFFFU +#define ISP_HIST_BIN_5_M (ISP_HIST_BIN_5_V << ISP_HIST_BIN_5_S) +#define ISP_HIST_BIN_5_V 0x0001FFFFU +#define ISP_HIST_BIN_5_S 0 + +/** ISP_HIST_BIN6_REG register + * result of histogram bin 6 + */ +#define ISP_HIST_BIN6_REG (DR_REG_ISP_BASE + 0x1f8) +/** ISP_HIST_BIN_6 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 6 + */ +#define ISP_HIST_BIN_6 0x0001FFFFU +#define ISP_HIST_BIN_6_M (ISP_HIST_BIN_6_V << ISP_HIST_BIN_6_S) +#define ISP_HIST_BIN_6_V 0x0001FFFFU +#define ISP_HIST_BIN_6_S 0 + +/** ISP_HIST_BIN7_REG register + * result of histogram bin 7 + */ +#define ISP_HIST_BIN7_REG (DR_REG_ISP_BASE + 0x1fc) +/** ISP_HIST_BIN_7 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 7 + */ +#define ISP_HIST_BIN_7 0x0001FFFFU +#define ISP_HIST_BIN_7_M (ISP_HIST_BIN_7_V << ISP_HIST_BIN_7_S) +#define ISP_HIST_BIN_7_V 0x0001FFFFU +#define ISP_HIST_BIN_7_S 0 + +/** ISP_HIST_BIN8_REG register + * result of histogram bin 8 + */ +#define ISP_HIST_BIN8_REG (DR_REG_ISP_BASE + 0x200) +/** ISP_HIST_BIN_8 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 8 + */ +#define ISP_HIST_BIN_8 0x0001FFFFU +#define ISP_HIST_BIN_8_M (ISP_HIST_BIN_8_V << ISP_HIST_BIN_8_S) +#define ISP_HIST_BIN_8_V 0x0001FFFFU +#define ISP_HIST_BIN_8_S 0 + +/** ISP_HIST_BIN9_REG register + * result of histogram bin 9 + */ +#define ISP_HIST_BIN9_REG (DR_REG_ISP_BASE + 0x204) +/** ISP_HIST_BIN_9 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 9 + */ +#define ISP_HIST_BIN_9 0x0001FFFFU +#define ISP_HIST_BIN_9_M (ISP_HIST_BIN_9_V << ISP_HIST_BIN_9_S) +#define ISP_HIST_BIN_9_V 0x0001FFFFU +#define ISP_HIST_BIN_9_S 0 + +/** ISP_HIST_BIN10_REG register + * result of histogram bin 10 + */ +#define ISP_HIST_BIN10_REG (DR_REG_ISP_BASE + 0x208) +/** ISP_HIST_BIN_10 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 10 + */ +#define ISP_HIST_BIN_10 0x0001FFFFU +#define ISP_HIST_BIN_10_M (ISP_HIST_BIN_10_V << ISP_HIST_BIN_10_S) +#define ISP_HIST_BIN_10_V 0x0001FFFFU +#define ISP_HIST_BIN_10_S 0 + +/** ISP_HIST_BIN11_REG register + * result of histogram bin 11 + */ +#define ISP_HIST_BIN11_REG (DR_REG_ISP_BASE + 0x20c) +/** ISP_HIST_BIN_11 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 11 + */ +#define ISP_HIST_BIN_11 0x0001FFFFU +#define ISP_HIST_BIN_11_M (ISP_HIST_BIN_11_V << ISP_HIST_BIN_11_S) +#define ISP_HIST_BIN_11_V 0x0001FFFFU +#define ISP_HIST_BIN_11_S 0 + +/** ISP_HIST_BIN12_REG register + * result of histogram bin 12 + */ +#define ISP_HIST_BIN12_REG (DR_REG_ISP_BASE + 0x210) +/** ISP_HIST_BIN_12 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 12 + */ +#define ISP_HIST_BIN_12 0x0001FFFFU +#define ISP_HIST_BIN_12_M (ISP_HIST_BIN_12_V << ISP_HIST_BIN_12_S) +#define ISP_HIST_BIN_12_V 0x0001FFFFU +#define ISP_HIST_BIN_12_S 0 + +/** ISP_HIST_BIN13_REG register + * result of histogram bin 13 + */ +#define ISP_HIST_BIN13_REG (DR_REG_ISP_BASE + 0x214) +/** ISP_HIST_BIN_13 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 13 + */ +#define ISP_HIST_BIN_13 0x0001FFFFU +#define ISP_HIST_BIN_13_M (ISP_HIST_BIN_13_V << ISP_HIST_BIN_13_S) +#define ISP_HIST_BIN_13_V 0x0001FFFFU +#define ISP_HIST_BIN_13_S 0 + +/** ISP_HIST_BIN14_REG register + * result of histogram bin 14 + */ +#define ISP_HIST_BIN14_REG (DR_REG_ISP_BASE + 0x218) +/** ISP_HIST_BIN_14 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 14 + */ +#define ISP_HIST_BIN_14 0x0001FFFFU +#define ISP_HIST_BIN_14_M (ISP_HIST_BIN_14_V << ISP_HIST_BIN_14_S) +#define ISP_HIST_BIN_14_V 0x0001FFFFU +#define ISP_HIST_BIN_14_S 0 + +/** ISP_HIST_BIN15_REG register + * result of histogram bin 15 + */ +#define ISP_HIST_BIN15_REG (DR_REG_ISP_BASE + 0x21c) +/** ISP_HIST_BIN_15 : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin 15 + */ +#define ISP_HIST_BIN_15 0x0001FFFFU +#define ISP_HIST_BIN_15_M (ISP_HIST_BIN_15_V << ISP_HIST_BIN_15_S) +#define ISP_HIST_BIN_15_V 0x0001FFFFU +#define ISP_HIST_BIN_15_S 0 + +/** ISP_MEM_AUX_CTRL_0_REG register + * mem aux control register 0 + */ +#define ISP_MEM_AUX_CTRL_0_REG (DR_REG_ISP_BASE + 0x220) +/** ISP_HEADER_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of isp input buffer memory + */ +#define ISP_HEADER_MEM_AUX_CTRL 0x00003FFFU +#define ISP_HEADER_MEM_AUX_CTRL_M (ISP_HEADER_MEM_AUX_CTRL_V << ISP_HEADER_MEM_AUX_CTRL_S) +#define ISP_HEADER_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_HEADER_MEM_AUX_CTRL_S 0 +/** ISP_DPC_LUT_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * this field represents this field configures the mem_aux of dpc lut memory + */ +#define ISP_DPC_LUT_MEM_AUX_CTRL 0x00003FFFU +#define ISP_DPC_LUT_MEM_AUX_CTRL_M (ISP_DPC_LUT_MEM_AUX_CTRL_V << ISP_DPC_LUT_MEM_AUX_CTRL_S) +#define ISP_DPC_LUT_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_DPC_LUT_MEM_AUX_CTRL_S 16 + +/** ISP_MEM_AUX_CTRL_1_REG register + * mem aux control register 1 + */ +#define ISP_MEM_AUX_CTRL_1_REG (DR_REG_ISP_BASE + 0x224) +/** ISP_LSC_LUT_R_GR_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of lsc r gr lut memory + */ +#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL 0x00003FFFU +#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_M (ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_V << ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_S) +#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_LSC_LUT_R_GR_MEM_AUX_CTRL_S 0 +/** ISP_LSC_LUT_GB_B_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of lsc gb b lut memory + */ +#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL 0x00003FFFU +#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_M (ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_V << ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_S) +#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_LSC_LUT_GB_B_MEM_AUX_CTRL_S 16 + +/** ISP_MEM_AUX_CTRL_2_REG register + * mem aux control register 2 + */ +#define ISP_MEM_AUX_CTRL_2_REG (DR_REG_ISP_BASE + 0x228) +/** ISP_BF_MATRIX_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of bf line buffer memory + */ +#define ISP_BF_MATRIX_MEM_AUX_CTRL 0x00003FFFU +#define ISP_BF_MATRIX_MEM_AUX_CTRL_M (ISP_BF_MATRIX_MEM_AUX_CTRL_V << ISP_BF_MATRIX_MEM_AUX_CTRL_S) +#define ISP_BF_MATRIX_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_BF_MATRIX_MEM_AUX_CTRL_S 0 +/** ISP_DPC_MATRIX_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of dpc line buffer memory + */ +#define ISP_DPC_MATRIX_MEM_AUX_CTRL 0x00003FFFU +#define ISP_DPC_MATRIX_MEM_AUX_CTRL_M (ISP_DPC_MATRIX_MEM_AUX_CTRL_V << ISP_DPC_MATRIX_MEM_AUX_CTRL_S) +#define ISP_DPC_MATRIX_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_DPC_MATRIX_MEM_AUX_CTRL_S 16 + +/** ISP_MEM_AUX_CTRL_3_REG register + * mem aux control register 3 + */ +#define ISP_MEM_AUX_CTRL_3_REG (DR_REG_ISP_BASE + 0x22c) +/** ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of sharp y line buffer memory + */ +#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL 0x00003FFFU +#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_M (ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_V << ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_S) +#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_SHARP_MATRIX_Y_MEM_AUX_CTRL_S 0 +/** ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of demosaic line buffer memory + */ +#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL 0x00003FFFU +#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_M (ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_V << ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_S) +#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_DEMOSAIC_MATRIX_MEM_AUX_CTRL_S 16 + +/** ISP_MEM_AUX_CTRL_4_REG register + * mem aux control register 4 + */ +#define ISP_MEM_AUX_CTRL_4_REG (DR_REG_ISP_BASE + 0x230) +/** ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of sharp uv line buffer memory + */ +#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL 0x00003FFFU +#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_M (ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_V << ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_S) +#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_V 0x00003FFFU +#define ISP_SHARP_MATRIX_UV_MEM_AUX_CTRL_S 0 + +/** ISP_YUV_FORMAT_REG register + * yuv format control register + */ +#define ISP_YUV_FORMAT_REG (DR_REG_ISP_BASE + 0x234) +/** ISP_YUV_MODE : R/W; bitpos: [0]; default: 0; + * this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 + */ +#define ISP_YUV_MODE (BIT(0)) +#define ISP_YUV_MODE_M (ISP_YUV_MODE_V << ISP_YUV_MODE_S) +#define ISP_YUV_MODE_V 0x00000001U +#define ISP_YUV_MODE_S 0 +/** ISP_YUV_RANGE : R/W; bitpos: [1]; default: 0; + * this bit configures the yuv range. 0: full range, 1: limit range + */ +#define ISP_YUV_RANGE (BIT(1)) +#define ISP_YUV_RANGE_M (ISP_YUV_RANGE_V << ISP_YUV_RANGE_S) +#define ISP_YUV_RANGE_V 0x00000001U +#define ISP_YUV_RANGE_S 1 + +/** ISP_RDN_ECO_CS_REG register + * rdn eco cs register + */ +#define ISP_RDN_ECO_CS_REG (DR_REG_ISP_BASE + 0x238) +/** ISP_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; + * rdn_eco_en + */ +#define ISP_RDN_ECO_EN (BIT(0)) +#define ISP_RDN_ECO_EN_M (ISP_RDN_ECO_EN_V << ISP_RDN_ECO_EN_S) +#define ISP_RDN_ECO_EN_V 0x00000001U +#define ISP_RDN_ECO_EN_S 0 +/** ISP_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0; + * rdn_eco_result + */ +#define ISP_RDN_ECO_RESULT (BIT(1)) +#define ISP_RDN_ECO_RESULT_M (ISP_RDN_ECO_RESULT_V << ISP_RDN_ECO_RESULT_S) +#define ISP_RDN_ECO_RESULT_V 0x00000001U +#define ISP_RDN_ECO_RESULT_S 1 + +/** ISP_RDN_ECO_LOW_REG register + * rdn eco all low register + */ +#define ISP_RDN_ECO_LOW_REG (DR_REG_ISP_BASE + 0x23c) +/** ISP_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * rdn_eco_low + */ +#define ISP_RDN_ECO_LOW 0xFFFFFFFFU +#define ISP_RDN_ECO_LOW_M (ISP_RDN_ECO_LOW_V << ISP_RDN_ECO_LOW_S) +#define ISP_RDN_ECO_LOW_V 0xFFFFFFFFU +#define ISP_RDN_ECO_LOW_S 0 + +/** ISP_RDN_ECO_HIGH_REG register + * rdn eco all high register + */ +#define ISP_RDN_ECO_HIGH_REG (DR_REG_ISP_BASE + 0x240) +/** ISP_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * rdn_eco_high + */ +#define ISP_RDN_ECO_HIGH 0xFFFFFFFFU +#define ISP_RDN_ECO_HIGH_M (ISP_RDN_ECO_HIGH_V << ISP_RDN_ECO_HIGH_S) +#define ISP_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define ISP_RDN_ECO_HIGH_S 0 + +/** ISP_CROP_CTRL_REG register + * isp_crop ctrl register + */ +#define ISP_CROP_CTRL_REG (DR_REG_ISP_BASE + 0x244) +/** ISP_CROP_SFT_RST : WT; bitpos: [0]; default: 0; + * Write 1 to clear err st + */ +#define ISP_CROP_SFT_RST (BIT(0)) +#define ISP_CROP_SFT_RST_M (ISP_CROP_SFT_RST_V << ISP_CROP_SFT_RST_S) +#define ISP_CROP_SFT_RST_V 0x00000001U +#define ISP_CROP_SFT_RST_S 0 + +/** ISP_CROP_Y_CAPTURE_REG register + * isp_crop row capture range register + */ +#define ISP_CROP_Y_CAPTURE_REG (DR_REG_ISP_BASE + 0x248) +/** ISP_CROP_Y_START : R/W; bitpos: [11:0]; default: 0; + * isp_crop capture row start index + */ +#define ISP_CROP_Y_START 0x00000FFFU +#define ISP_CROP_Y_START_M (ISP_CROP_Y_START_V << ISP_CROP_Y_START_S) +#define ISP_CROP_Y_START_V 0x00000FFFU +#define ISP_CROP_Y_START_S 0 +/** ISP_CROP_Y_END : R/W; bitpos: [23:12]; default: 0; + * isp_crop capture row end index + */ +#define ISP_CROP_Y_END 0x00000FFFU +#define ISP_CROP_Y_END_M (ISP_CROP_Y_END_V << ISP_CROP_Y_END_S) +#define ISP_CROP_Y_END_V 0x00000FFFU +#define ISP_CROP_Y_END_S 12 + +/** ISP_CROP_X_CAPTURE_REG register + * isp_crop col capture range register + */ +#define ISP_CROP_X_CAPTURE_REG (DR_REG_ISP_BASE + 0x24c) +/** ISP_CROP_X_START : R/W; bitpos: [11:0]; default: 0; + * isp_crop capture col start index + */ +#define ISP_CROP_X_START 0x00000FFFU +#define ISP_CROP_X_START_M (ISP_CROP_X_START_V << ISP_CROP_X_START_S) +#define ISP_CROP_X_START_V 0x00000FFFU +#define ISP_CROP_X_START_S 0 +/** ISP_CROP_X_END : R/W; bitpos: [23:12]; default: 0; + * isp_crop capture col end index + */ +#define ISP_CROP_X_END 0x00000FFFU +#define ISP_CROP_X_END_M (ISP_CROP_X_END_V << ISP_CROP_X_END_S) +#define ISP_CROP_X_END_V 0x00000FFFU +#define ISP_CROP_X_END_S 12 + +/** ISP_CROP_ERR_ST_REG register + * crop error state register + */ +#define ISP_CROP_ERR_ST_REG (DR_REG_ISP_BASE + 0x250) +/** ISP_CROP_Y_MISMATCH : RO; bitpos: [0]; default: 0; + * Represents isp_corp row end index over image size + */ +#define ISP_CROP_Y_MISMATCH (BIT(0)) +#define ISP_CROP_Y_MISMATCH_M (ISP_CROP_Y_MISMATCH_V << ISP_CROP_Y_MISMATCH_S) +#define ISP_CROP_Y_MISMATCH_V 0x00000001U +#define ISP_CROP_Y_MISMATCH_S 0 +/** ISP_CROP_X_MISMATCH : RO; bitpos: [1]; default: 0; + * Represents isp_corp col end index over image size + */ +#define ISP_CROP_X_MISMATCH (BIT(1)) +#define ISP_CROP_X_MISMATCH_M (ISP_CROP_X_MISMATCH_V << ISP_CROP_X_MISMATCH_S) +#define ISP_CROP_X_MISMATCH_V 0x00000001U +#define ISP_CROP_X_MISMATCH_S 1 +/** ISP_CROP_Y_END_EVEN : RO; bitpos: [2]; default: 0; + * Represents isp_corp row end index is an even number + */ +#define ISP_CROP_Y_END_EVEN (BIT(2)) +#define ISP_CROP_Y_END_EVEN_M (ISP_CROP_Y_END_EVEN_V << ISP_CROP_Y_END_EVEN_S) +#define ISP_CROP_Y_END_EVEN_V 0x00000001U +#define ISP_CROP_Y_END_EVEN_S 2 +/** ISP_CROP_X_END_EVEN : RO; bitpos: [3]; default: 0; + * Represents isp_corp col end index is an even number + */ +#define ISP_CROP_X_END_EVEN (BIT(3)) +#define ISP_CROP_X_END_EVEN_M (ISP_CROP_X_END_EVEN_V << ISP_CROP_X_END_EVEN_S) +#define ISP_CROP_X_END_EVEN_V 0x00000001U +#define ISP_CROP_X_END_EVEN_S 3 +/** ISP_CROP_Y_START_ODD : RO; bitpos: [4]; default: 0; + * Represents isp_corp row start index is an odd number + */ +#define ISP_CROP_Y_START_ODD (BIT(4)) +#define ISP_CROP_Y_START_ODD_M (ISP_CROP_Y_START_ODD_V << ISP_CROP_Y_START_ODD_S) +#define ISP_CROP_Y_START_ODD_V 0x00000001U +#define ISP_CROP_Y_START_ODD_S 4 +/** ISP_CROP_X_START_ODD : RO; bitpos: [5]; default: 0; + * Represents isp_corp col start index is an odd number + */ +#define ISP_CROP_X_START_ODD (BIT(5)) +#define ISP_CROP_X_START_ODD_M (ISP_CROP_X_START_ODD_V << ISP_CROP_X_START_ODD_S) +#define ISP_CROP_X_START_ODD_V 0x00000001U +#define ISP_CROP_X_START_ODD_S 5 + +/** ISP_WBG_COEF_R_REG register + * white balance red gain register 0 + */ +#define ISP_WBG_COEF_R_REG (DR_REG_ISP_BASE + 0x254) +/** ISP_WBG_R : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance red gain + */ +#define ISP_WBG_R 0x00000FFFU +#define ISP_WBG_R_M (ISP_WBG_R_V << ISP_WBG_R_S) +#define ISP_WBG_R_V 0x00000FFFU +#define ISP_WBG_R_S 0 + +/** ISP_WBG_COEF_G_REG register + * white balance green gain register 0 + */ +#define ISP_WBG_COEF_G_REG (DR_REG_ISP_BASE + 0x258) +/** ISP_WBG_G : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance green gain + */ +#define ISP_WBG_G 0x00000FFFU +#define ISP_WBG_G_M (ISP_WBG_G_V << ISP_WBG_G_S) +#define ISP_WBG_G_V 0x00000FFFU +#define ISP_WBG_G_S 0 + +/** ISP_WBG_COEF_B_REG register + * white balance blue gain register 0 + */ +#define ISP_WBG_COEF_B_REG (DR_REG_ISP_BASE + 0x25c) +/** ISP_WBG_B : R/W; bitpos: [11:0]; default: 256; + * Configures the white balance blue gain + */ +#define ISP_WBG_B 0x00000FFFU +#define ISP_WBG_B_M (ISP_WBG_B_V << ISP_WBG_B_S) +#define ISP_WBG_B_V 0x00000FFFU +#define ISP_WBG_B_S 0 + +/** ISP_COLOR_HUE_CTRL_REG register + * color control register + */ +#define ISP_COLOR_HUE_CTRL_REG (DR_REG_ISP_BASE + 0x260) +/** ISP_COLOR_HUE_H : R/W; bitpos: [0]; default: 0; + * Configures the color hue angle most bit + */ +#define ISP_COLOR_HUE_H (BIT(0)) +#define ISP_COLOR_HUE_H_M (ISP_COLOR_HUE_H_V << ISP_COLOR_HUE_H_S) +#define ISP_COLOR_HUE_H_V 0x00000001U +#define ISP_COLOR_HUE_H_S 0 + +/** ISP_AWB_BX_REG register + * awb window register in x-direction + */ +#define ISP_AWB_BX_REG (DR_REG_ISP_BASE + 0x264) +/** ISP_AWB_X_BSIZE : R/W; bitpos: [11:0]; default: 0; + * Configures every block x size, min number is 4 + */ +#define ISP_AWB_X_BSIZE 0x00000FFFU +#define ISP_AWB_X_BSIZE_M (ISP_AWB_X_BSIZE_V << ISP_AWB_X_BSIZE_S) +#define ISP_AWB_X_BSIZE_V 0x00000FFFU +#define ISP_AWB_X_BSIZE_S 0 +/** ISP_AWB_X_START : R/W; bitpos: [23:12]; default: 0; + * Configures first block start x address + */ +#define ISP_AWB_X_START 0x00000FFFU +#define ISP_AWB_X_START_M (ISP_AWB_X_START_V << ISP_AWB_X_START_S) +#define ISP_AWB_X_START_V 0x00000FFFU +#define ISP_AWB_X_START_S 12 + +/** ISP_AWB_BY_REG register + * awb window register in y-direction + */ +#define ISP_AWB_BY_REG (DR_REG_ISP_BASE + 0x268) +/** ISP_AWB_Y_BSIZE : R/W; bitpos: [11:0]; default: 0; + * Configures every block y size + */ +#define ISP_AWB_Y_BSIZE 0x00000FFFU +#define ISP_AWB_Y_BSIZE_M (ISP_AWB_Y_BSIZE_V << ISP_AWB_Y_BSIZE_S) +#define ISP_AWB_Y_BSIZE_V 0x00000FFFU +#define ISP_AWB_Y_BSIZE_S 0 +/** ISP_AWB_Y_START : R/W; bitpos: [23:12]; default: 0; + * Configures first block start y address + */ +#define ISP_AWB_Y_START 0x00000FFFU +#define ISP_AWB_Y_START_M (ISP_AWB_Y_START_V << ISP_AWB_Y_START_S) +#define ISP_AWB_Y_START_V 0x00000FFFU +#define ISP_AWB_Y_START_S 12 + +/** ISP_STATE_REG register + * awb window register in y-direction + */ +#define ISP_STATE_REG (DR_REG_ISP_BASE + 0x26c) +/** ISP_TAIL_BUSY : RO; bitpos: [0]; default: 0; + * Represents isp_tail state + */ +#define ISP_TAIL_BUSY (BIT(0)) +#define ISP_TAIL_BUSY_M (ISP_TAIL_BUSY_V << ISP_TAIL_BUSY_S) +#define ISP_TAIL_BUSY_V 0x00000001U +#define ISP_TAIL_BUSY_S 0 +/** ISP_HEADER_BUSY : RO; bitpos: [1]; default: 0; + * Represents isp_header state + */ +#define ISP_HEADER_BUSY (BIT(1)) +#define ISP_HEADER_BUSY_M (ISP_HEADER_BUSY_V << ISP_HEADER_BUSY_S) +#define ISP_HEADER_BUSY_V 0x00000001U +#define ISP_HEADER_BUSY_S 1 + +/** ISP_SHADOW_REG_CTRL_REG register + * shadow register ctrl register + */ +#define ISP_SHADOW_REG_CTRL_REG (DR_REG_ISP_BASE + 0x270) +/** ISP_BLC_UPDATE : R/W; bitpos: [0]; default: 0; + * Write 1 to update blc configuration register + */ +#define ISP_BLC_UPDATE (BIT(0)) +#define ISP_BLC_UPDATE_M (ISP_BLC_UPDATE_V << ISP_BLC_UPDATE_S) +#define ISP_BLC_UPDATE_V 0x00000001U +#define ISP_BLC_UPDATE_S 0 +/** ISP_DPC_UPDATE : R/W; bitpos: [1]; default: 0; + * Write 1 to update dpc configuration register + */ +#define ISP_DPC_UPDATE (BIT(1)) +#define ISP_DPC_UPDATE_M (ISP_DPC_UPDATE_V << ISP_DPC_UPDATE_S) +#define ISP_DPC_UPDATE_V 0x00000001U +#define ISP_DPC_UPDATE_S 1 +/** ISP_BF_UPDATE : R/W; bitpos: [2]; default: 0; + * Write 1 to update bf configuration register + */ +#define ISP_BF_UPDATE (BIT(2)) +#define ISP_BF_UPDATE_M (ISP_BF_UPDATE_V << ISP_BF_UPDATE_S) +#define ISP_BF_UPDATE_V 0x00000001U +#define ISP_BF_UPDATE_S 2 +/** ISP_WBG_UPDATE : R/W; bitpos: [3]; default: 0; + * Write 1 to update wbg configuration register + */ +#define ISP_WBG_UPDATE (BIT(3)) +#define ISP_WBG_UPDATE_M (ISP_WBG_UPDATE_V << ISP_WBG_UPDATE_S) +#define ISP_WBG_UPDATE_V 0x00000001U +#define ISP_WBG_UPDATE_S 3 +/** ISP_CCM_UPDATE : R/W; bitpos: [4]; default: 0; + * Write 1 to update ccm configuration register + */ +#define ISP_CCM_UPDATE (BIT(4)) +#define ISP_CCM_UPDATE_M (ISP_CCM_UPDATE_V << ISP_CCM_UPDATE_S) +#define ISP_CCM_UPDATE_V 0x00000001U +#define ISP_CCM_UPDATE_S 4 +/** ISP_SHARP_UPDATE : R/W; bitpos: [6]; default: 0; + * Write 1 to update sharp configuration register + */ +#define ISP_SHARP_UPDATE (BIT(6)) +#define ISP_SHARP_UPDATE_M (ISP_SHARP_UPDATE_V << ISP_SHARP_UPDATE_S) +#define ISP_SHARP_UPDATE_V 0x00000001U +#define ISP_SHARP_UPDATE_S 6 +/** ISP_COLOR_UPDATE : R/W; bitpos: [7]; default: 0; + * Write 1 to update color configuration register + */ +#define ISP_COLOR_UPDATE (BIT(7)) +#define ISP_COLOR_UPDATE_M (ISP_COLOR_UPDATE_V << ISP_COLOR_UPDATE_S) +#define ISP_COLOR_UPDATE_V 0x00000001U +#define ISP_COLOR_UPDATE_S 7 +/** ISP_SHADOW_UPDATE_SEL : R/W; bitpos: [31:30]; default: 1; + * Configures shadow register update type. 0: no shadow register. 1: update every + * vsyn. 2: update only the next vsync after write reg_xxx_update + */ +#define ISP_SHADOW_UPDATE_SEL 0x00000003U +#define ISP_SHADOW_UPDATE_SEL_M (ISP_SHADOW_UPDATE_SEL_V << ISP_SHADOW_UPDATE_SEL_S) +#define ISP_SHADOW_UPDATE_SEL_V 0x00000003U +#define ISP_SHADOW_UPDATE_SEL_S 30 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/isp_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/isp_struct.h new file mode 100644 index 0000000000..8f65f76752 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/isp_struct.h @@ -0,0 +1,3285 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Version Register */ +/** Type of ver_date register + * version control register + */ +typedef union { + struct { + /** ver_data : R/W; bitpos: [31:0]; default: 539035144; + * csv version + */ + uint32_t ver_data:32; + }; + uint32_t val; +} isp_ver_date_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clk_en register + * isp clk control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * this bit configures the clk force on of isp reg. 0: disable, 1: enable + */ + uint32_t clk_en:1; + /** clk_blc_force_on : R/W; bitpos: [1]; default: 0; + * this bit configures the clk force on of blc. 0: disable, 1: enable + */ + uint32_t clk_blc_force_on:1; + /** clk_dpc_force_on : R/W; bitpos: [2]; default: 0; + * this bit configures the clk force on of dpc. 0: disable, 1: enable + */ + uint32_t clk_dpc_force_on:1; + /** clk_bf_force_on : R/W; bitpos: [3]; default: 0; + * this bit configures the clk force on of bf. 0: disable, 1: enable + */ + uint32_t clk_bf_force_on:1; + /** clk_lsc_force_on : R/W; bitpos: [4]; default: 0; + * this bit configures the clk force on of lsc. 0: disable, 1: enable + */ + uint32_t clk_lsc_force_on:1; + /** clk_demosaic_force_on : R/W; bitpos: [5]; default: 0; + * this bit configures the clk force on of demosaic. 0: disable, 1: enable + */ + uint32_t clk_demosaic_force_on:1; + /** clk_median_force_on : R/W; bitpos: [6]; default: 0; + * this bit configures the clk force on of median. 0: disable, 1: enable + */ + uint32_t clk_median_force_on:1; + /** clk_ccm_force_on : R/W; bitpos: [7]; default: 0; + * this bit configures the clk force on of ccm. 0: disable, 1: enable + */ + uint32_t clk_ccm_force_on:1; + /** clk_gamma_force_on : R/W; bitpos: [8]; default: 0; + * this bit configures the clk force on of gamma. 0: disable, 1: enable + */ + uint32_t clk_gamma_force_on:1; + /** clk_rgb2yuv_force_on : R/W; bitpos: [9]; default: 0; + * this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable + */ + uint32_t clk_rgb2yuv_force_on:1; + /** clk_sharp_force_on : R/W; bitpos: [10]; default: 0; + * this bit configures the clk force on of sharp. 0: disable, 1: enable + */ + uint32_t clk_sharp_force_on:1; + /** clk_color_force_on : R/W; bitpos: [11]; default: 0; + * this bit configures the clk force on of color. 0: disable, 1: enable + */ + uint32_t clk_color_force_on:1; + /** clk_yuv2rgb_force_on : R/W; bitpos: [12]; default: 0; + * this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable + */ + uint32_t clk_yuv2rgb_force_on:1; + /** clk_ae_force_on : R/W; bitpos: [13]; default: 0; + * this bit configures the clk force on of ae. 0: disable, 1: enable + */ + uint32_t clk_ae_force_on:1; + /** clk_af_force_on : R/W; bitpos: [14]; default: 0; + * this bit configures the clk force on of af. 0: disable, 1: enable + */ + uint32_t clk_af_force_on:1; + /** clk_awb_force_on : R/W; bitpos: [15]; default: 0; + * this bit configures the clk force on of awb. 0: disable, 1: enable + */ + uint32_t clk_awb_force_on:1; + /** clk_hist_force_on : R/W; bitpos: [16]; default: 0; + * this bit configures the clk force on of hist. 0: disable, 1: enable + */ + uint32_t clk_hist_force_on:1; + /** clk_mipi_idi_force_on : R/W; bitpos: [17]; default: 0; + * this bit configures the clk force on of mipi idi input. 0: disable, 1: enable + */ + uint32_t clk_mipi_idi_force_on:1; + /** isp_mem_clk_force_on : R/W; bitpos: [18]; default: 0; + * this bit configures the clk force on of all isp memory. 0: disable, 1: enable + */ + uint32_t isp_mem_clk_force_on:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} isp_clk_en_reg_t; + +/** Type of cntl register + * isp module enable control register + */ +typedef union { + struct { + /** mipi_data_en : R/W; bitpos: [0]; default: 0; + * this bit configures mipi input data enable. 0: disable, 1: enable + */ + uint32_t mipi_data_en:1; + /** isp_en : R/W; bitpos: [1]; default: 1; + * this bit configures isp global enable. 0: disable, 1: enable + */ + uint32_t isp_en:1; + /** blc_en : R/W; bitpos: [2]; default: 0; + * this bit configures blc enable. 0: disable, 1: enable + */ + uint32_t blc_en:1; + /** dpc_en : R/W; bitpos: [3]; default: 0; + * this bit configures dpc enable. 0: disable, 1: enable + */ + uint32_t dpc_en:1; + /** bf_en : R/W; bitpos: [4]; default: 0; + * this bit configures bf enable. 0: disable, 1: enable + */ + uint32_t bf_en:1; + /** lsc_en : R/W; bitpos: [5]; default: 0; + * this bit configures lsc enable. 0: disable, 1: enable + */ + uint32_t lsc_en:1; + /** demosaic_en : R/W; bitpos: [6]; default: 1; + * this bit configures demosaic enable. 0: disable, 1: enable + */ + uint32_t demosaic_en:1; + /** median_en : R/W; bitpos: [7]; default: 0; + * this bit configures median enable. 0: disable, 1: enable + */ + uint32_t median_en:1; + /** ccm_en : R/W; bitpos: [8]; default: 0; + * this bit configures ccm enable. 0: disable, 1: enable + */ + uint32_t ccm_en:1; + /** gamma_en : R/W; bitpos: [9]; default: 0; + * this bit configures gamma enable. 0: disable, 1: enable + */ + uint32_t gamma_en:1; + /** rgb2yuv_en : R/W; bitpos: [10]; default: 1; + * this bit configures rgb2yuv enable. 0: disable, 1: enable + */ + uint32_t rgb2yuv_en:1; + /** sharp_en : R/W; bitpos: [11]; default: 0; + * this bit configures sharp enable. 0: disable, 1: enable + */ + uint32_t sharp_en:1; + /** color_en : R/W; bitpos: [12]; default: 0; + * this bit configures color enable. 0: disable, 1: enable + */ + uint32_t color_en:1; + /** yuv2rgb_en : R/W; bitpos: [13]; default: 1; + * this bit configures yuv2rgb enable. 0: disable, 1: enable + */ + uint32_t yuv2rgb_en:1; + /** ae_en : R/W; bitpos: [14]; default: 0; + * this bit configures ae enable. 0: disable, 1: enable + */ + uint32_t ae_en:1; + /** af_en : R/W; bitpos: [15]; default: 0; + * this bit configures af enable. 0: disable, 1: enable + */ + uint32_t af_en:1; + /** awb_en : R/W; bitpos: [16]; default: 0; + * this bit configures awb enable. 0: disable, 1: enable + */ + uint32_t awb_en:1; + /** hist_en : R/W; bitpos: [17]; default: 0; + * this bit configures hist enable. 0: disable, 1: enable + */ + uint32_t hist_en:1; + uint32_t reserved_18:6; + /** byte_endian_order : R/W; bitpos: [24]; default: 0; + * select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: + * {[7:0], [15:8], [23:16], [31:24]} + */ + uint32_t byte_endian_order:1; + /** isp_data_type : R/W; bitpos: [26:25]; default: 0; + * this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 + */ + uint32_t isp_data_type:2; + /** isp_in_src : R/W; bitpos: [28:27]; default: 0; + * this field configures input data source, 0:CSI HOST 1:CAM 2:DMA + */ + uint32_t isp_in_src:2; + /** isp_out_type : R/W; bitpos: [31:29]; default: 2; + * this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: + * RGB565 + */ + uint32_t isp_out_type:3; + }; + uint32_t val; +} isp_cntl_reg_t; + +/** Type of hsync_cnt register + * header hsync interval control register + */ +typedef union { + struct { + /** hsync_cnt : R/W; bitpos: [7:0]; default: 7; + * this field configures the number of clock before hsync and after vsync and line_end + * when decodes pix data from idi to isp + */ + uint32_t hsync_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} isp_hsync_cnt_reg_t; + +/** Type of frame_cfg register + * frame control parameter register + */ +typedef union { + struct { + /** vadr_num : R/W; bitpos: [11:0]; default: 480; + * this field configures input image size in y-direction, image row number - 1 + */ + uint32_t vadr_num:12; + /** hadr_num : R/W; bitpos: [23:12]; default: 480; + * this field configures input image size in x-direction, image line number - 1 + */ + uint32_t hadr_num:12; + uint32_t reserved_24:3; + /** bayer_mode : R/W; bitpos: [28:27]; default: 0; + * this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 + * : GR/BG 11 : RG/GB + */ + uint32_t bayer_mode:2; + /** hsync_start_exist : R/W; bitpos: [29]; default: 1; + * this bit configures the line end start exist or not. 0: not exist, 1: exist + */ + uint32_t hsync_start_exist:1; + /** hsync_end_exist : R/W; bitpos: [30]; default: 1; + * this bit configures the line end packet exist or not. 0: not exist, 1: exist + */ + uint32_t hsync_end_exist:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} isp_frame_cfg_reg_t; + +/** Type of ccm_coef0 register + * ccm coef register 0 + */ +typedef union { + struct { + /** ccm_rr : R/W; bitpos: [12:0]; default: 1856; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_rr:13; + /** ccm_rg : R/W; bitpos: [25:13]; default: 4736; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_rg:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef0_reg_t; + +/** Type of ccm_coef1 register + * ccm coef register 1 + */ +typedef union { + struct { + /** ccm_rb : R/W; bitpos: [12:0]; default: 4288; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_rb:13; + /** ccm_gr : R/W; bitpos: [25:13]; default: 4416; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_gr:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef1_reg_t; + +/** Type of ccm_coef3 register + * ccm coef register 3 + */ +typedef union { + struct { + /** ccm_gg : R/W; bitpos: [12:0]; default: 1664; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_gg:13; + /** ccm_gb : R/W; bitpos: [25:13]; default: 4352; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_gb:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef3_reg_t; + +/** Type of ccm_coef4 register + * ccm coef register 4 + */ +typedef union { + struct { + /** ccm_br : R/W; bitpos: [12:0]; default: 4160; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_br:13; + /** ccm_bg : R/W; bitpos: [25:13]; default: 4800; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_bg:13; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_ccm_coef4_reg_t; + +/** Type of ccm_coef5 register + * ccm coef register 5 + */ +typedef union { + struct { + /** ccm_bb : R/W; bitpos: [12:0]; default: 1856; + * this field configures the color correction matrix coefficient + */ + uint32_t ccm_bb:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} isp_ccm_coef5_reg_t; + +/** Type of bf_matrix_ctrl register + * bf pix2matrix ctrl + */ +typedef union { + struct { + /** bf_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 + * and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse + * function + */ + uint32_t bf_tail_pixen_pulse_tl:8; + /** bf_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and + * reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse + * function + */ + uint32_t bf_tail_pixen_pulse_th:8; + /** bf_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures bf matrix padding data + */ + uint32_t bf_padding_data:8; + /** bf_padding_mode : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of bf matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ + uint32_t bf_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_bf_matrix_ctrl_reg_t; + +/** Type of bf_sigma register + * bf denoising level control register + */ +typedef union { + struct { + /** sigma : R/W; bitpos: [5:0]; default: 2; + * this field configures the bayer denoising level, valid data from 2 to 20 + */ + uint32_t sigma:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_bf_sigma_reg_t; + +/** Type of bf_gau0 register + * bf gau template register 0 + */ +typedef union { + struct { + /** gau_template21 : R/W; bitpos: [3:0]; default: 15; + * this field configures index 21 of gaussian template + */ + uint32_t gau_template21:4; + /** gau_template20 : R/W; bitpos: [7:4]; default: 15; + * this field configures index 20 of gaussian template + */ + uint32_t gau_template20:4; + /** gau_template12 : R/W; bitpos: [11:8]; default: 15; + * this field configures index 12 of gaussian template + */ + uint32_t gau_template12:4; + /** gau_template11 : R/W; bitpos: [15:12]; default: 15; + * this field configures index 11 of gaussian template + */ + uint32_t gau_template11:4; + /** gau_template10 : R/W; bitpos: [19:16]; default: 15; + * this field configures index 10 of gaussian template + */ + uint32_t gau_template10:4; + /** gau_template02 : R/W; bitpos: [23:20]; default: 15; + * this field configures index 02 of gaussian template + */ + uint32_t gau_template02:4; + /** gau_template01 : R/W; bitpos: [27:24]; default: 15; + * this field configures index 01 of gaussian template + */ + uint32_t gau_template01:4; + /** gau_template00 : R/W; bitpos: [31:28]; default: 15; + * this field configures index 00 of gaussian template + */ + uint32_t gau_template00:4; + }; + uint32_t val; +} isp_bf_gau0_reg_t; + +/** Type of bf_gau1 register + * bf gau template register 1 + */ +typedef union { + struct { + /** gau_template22 : R/W; bitpos: [3:0]; default: 15; + * this field configures index 22 of gaussian template + */ + uint32_t gau_template22:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_bf_gau1_reg_t; + +/** Type of dpc_ctrl register + * DPC mode control register + */ +typedef union { + struct { + /** dpc_check_en : R/W; bitpos: [0]; default: 0; + * this bit configures the check mode enable. 0: disable, 1: enable + */ + uint32_t dpc_check_en:1; + /** sta_en : R/W; bitpos: [1]; default: 0; + * this bit configures the sta dpc enable. 0: disable, 1: enable + */ + uint32_t sta_en:1; + /** dyn_en : R/W; bitpos: [2]; default: 1; + * this bit configures the dyn dpc enable. 0: disable, 1: enable + */ + uint32_t dyn_en:1; + /** dpc_black_en : R/W; bitpos: [3]; default: 0; + * this bit configures input image type select when in check mode, 0: white img, 1: + * black img + */ + uint32_t dpc_black_en:1; + /** dpc_method_sel : R/W; bitpos: [4]; default: 0; + * this bit configures dyn dpc method select. 0: simple method, 1: hard method + */ + uint32_t dpc_method_sel:1; + /** dpc_check_od_en : R/W; bitpos: [5]; default: 0; + * this bit configures output pixel data when in check mode or not. 0: no data output, + * 1: data output + */ + uint32_t dpc_check_od_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_dpc_ctrl_reg_t; + +/** Type of dpc_conf register + * DPC parameter config register + */ +typedef union { + struct { + /** dpc_threshold_l : R/W; bitpos: [7:0]; default: 48; + * this bit configures the threshold to detect black img in check mode, or the low + * threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit + * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + */ + uint32_t dpc_threshold_l:8; + /** dpc_threshold_h : R/W; bitpos: [15:8]; default: 48; + * this bit configures the threshold to detect white img in check mode, or the high + * threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit + * 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + */ + uint32_t dpc_threshold_h:8; + /** dpc_factor_dark : R/W; bitpos: [21:16]; default: 16; + * this field configures the dynamic correction method 1 dark factor + */ + uint32_t dpc_factor_dark:6; + /** dpc_factor_brig : R/W; bitpos: [27:22]; default: 16; + * this field configures the dynamic correction method 1 bright factor + */ + uint32_t dpc_factor_brig:6; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_dpc_conf_reg_t; + +/** Type of dpc_matrix_ctrl register + * dpc pix2matrix ctrl + */ +typedef union { + struct { + /** dpc_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 + * and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail + * pulse function + */ + uint32_t dpc_tail_pixen_pulse_tl:8; + /** dpc_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and + * reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse + * function + */ + uint32_t dpc_tail_pixen_pulse_th:8; + /** dpc_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures dpc matrix padding data + */ + uint32_t dpc_padding_data:8; + /** dpc_padding_mode : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of dpc matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ + uint32_t dpc_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_dpc_matrix_ctrl_reg_t; + +/** Type of lut_cmd register + * LUT command register + */ +typedef union { + struct { + /** lut_addr : WT; bitpos: [11:0]; default: 0; + * this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b + * lut, 01 sel r_gr lut + */ + uint32_t lut_addr:12; + /** lut_num : WT; bitpos: [15:12]; default: 0; + * this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT + */ + uint32_t lut_num:4; + /** lut_cmd : WT; bitpos: [16]; default: 0; + * this bit configures the access event of lut. 0:rd 1: wr + */ + uint32_t lut_cmd:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_lut_cmd_reg_t; + +/** Type of lut_wdata register + * LUT write data register + */ +typedef union { + struct { + /** lut_wdata : R/W; bitpos: [31:0]; default: 0; + * this field configures the write data of lut. please initial ISP_LUT_WDATA before + * write ISP_LUT_CMD register + */ + uint32_t lut_wdata:32; + }; + uint32_t val; +} isp_lut_wdata_reg_t; + +/** Type of lsc_tablesize register + * LSC point in x-direction + */ +typedef union { + struct { + /** lsc_xtablesize : R/W; bitpos: [4:0]; default: 31; + * this field configures lsc table size in x-direction + */ + uint32_t lsc_xtablesize:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} isp_lsc_tablesize_reg_t; + +/** Type of demosaic_matrix_ctrl register + * demosaic pix2matrix ctrl + */ +typedef union { + struct { + /** demosaic_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and + * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < + * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + */ + uint32_t demosaic_tail_pixen_pulse_tl:8; + /** demosaic_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and + * reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable + * tail pulse function + */ + uint32_t demosaic_tail_pixen_pulse_th:8; + /** demosaic_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures demosaic matrix padding data + */ + uint32_t demosaic_padding_data:8; + /** demosaic_padding_mode : R/W; bitpos: [24]; default: 0; + * this bit configures the padding mode of demosaic matrix. 0: use pixel in image to + * do padding 1: use reg_padding_data to do padding + */ + uint32_t demosaic_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_demosaic_matrix_ctrl_reg_t; + +/** Type of demosaic_grad_ratio register + * demosaic gradient select ratio + */ +typedef union { + struct { + /** demosaic_grad_ratio : R/W; bitpos: [5:0]; default: 16; + * this field configures demosaic gradient select ratio + */ + uint32_t demosaic_grad_ratio:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} isp_demosaic_grad_ratio_reg_t; + +/** Type of median_matrix_ctrl register + * median pix2matrix ctrl + */ +typedef union { + struct { + /** median_padding_data : R/W; bitpos: [7:0]; default: 0; + * this field configures median matrix padding data + */ + uint32_t median_padding_data:8; + /** median_padding_mode : R/W; bitpos: [8]; default: 0; + * this bit configures the padding mode of median matrix. 0: use pixel in image to do + * padding 1: use reg_padding_data to do padding + */ + uint32_t median_padding_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} isp_median_matrix_ctrl_reg_t; + +/** Type of gamma_ctrl register + * gamma control register + */ +typedef union { + struct { + /** gamma_update : R/W; bitpos: [0]; default: 0; + * Indicates that gamma register configuration is complete + */ + uint32_t gamma_update:1; + /** gamma_b_last_correct : R/W; bitpos: [1]; default: 1; + * this bit configures enable of last b segment correcction. 0: disable, 1: enable + */ + uint32_t gamma_b_last_correct:1; + /** gamma_g_last_correct : R/W; bitpos: [2]; default: 1; + * this bit configures enable of last g segment correcction. 0: disable, 1: enable + */ + uint32_t gamma_g_last_correct:1; + /** gamma_r_last_correct : R/W; bitpos: [3]; default: 1; + * this bit configures enable of last r segment correcction. 0: disable, 1: enable + */ + uint32_t gamma_r_last_correct:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_gamma_ctrl_reg_t; + +/** Type of gamma_y1 register + * point of Y-axis of r/g/b channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_y03 : R/W; bitpos: [7:0]; default: 64; + * this field configures the point 3 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y03:8; + /** gamma_y02 : R/W; bitpos: [15:8]; default: 48; + * this field configures the point 2 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y02:8; + /** gamma_y01 : R/W; bitpos: [23:16]; default: 32; + * this field configures the point 1 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y01:8; + /** gamma_y00 : R/W; bitpos: [31:24]; default: 16; + * this field configures the point 0 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y00:8; + }; + uint32_t val; +} isp_gamma_y1_reg_t; + +/** Type of gamma_y2 register + * point of Y-axis of r/g/b channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_y07 : R/W; bitpos: [7:0]; default: 128; + * this field configures the point 7 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y07:8; + /** gamma_y06 : R/W; bitpos: [15:8]; default: 112; + * this field configures the point 6 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y06:8; + /** gamma_y05 : R/W; bitpos: [23:16]; default: 96; + * this field configures the point 5 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y05:8; + /** gamma_y04 : R/W; bitpos: [31:24]; default: 80; + * this field configures the point 4 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y04:8; + }; + uint32_t val; +} isp_gamma_y2_reg_t; + +/** Type of gamma_y3 register + * point of Y-axis of r/g/b channel gamma curve register 3 + */ +typedef union { + struct { + /** gamma_y0b : R/W; bitpos: [7:0]; default: 192; + * this field configures the point 11 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y0b:8; + /** gamma_y0a : R/W; bitpos: [15:8]; default: 176; + * this field configures the point 10 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y0a:8; + /** gamma_y09 : R/W; bitpos: [23:16]; default: 160; + * this field configures the point 9 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y09:8; + /** gamma_y08 : R/W; bitpos: [31:24]; default: 144; + * this field configures the point 8 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y08:8; + }; + uint32_t val; +} isp_gamma_y3_reg_t; + +/** Type of gamma_y4 register + * point of Y-axis of r/g/b channel gamma curve register 4 + */ +typedef union { + struct { + /** gamma_y0f : R/W; bitpos: [7:0]; default: 255; + * this field configures the point 15 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y0f:8; + /** gamma_y0e : R/W; bitpos: [15:8]; default: 240; + * this field configures the point 14 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y0e:8; + /** gamma_y0d : R/W; bitpos: [23:16]; default: 224; + * this field configures the point 13 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y0d:8; + /** gamma_y0c : R/W; bitpos: [31:24]; default: 208; + * this field configures the point 12 of Y-axis of r/g/b channel gamma curve + */ + uint32_t gamma_y0c:8; + }; + uint32_t val; +} isp_gamma_y4_reg_t; + +/** Type of gamma_x1 register + * point of X-axis of r/g/b channel gamma curve register 1 + */ +typedef union { + struct { + /** gamma_r_x07 : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 7 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x07:3; + /** gamma_r_x06 : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 6 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x06:3; + /** gamma_x05 : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 5 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x05:3; + /** gamma_x04 : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 4 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x04:3; + /** gamma_x03 : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 3 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x03:3; + /** gamma_x02 : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 2 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x02:3; + /** gamma_x01 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 1 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x01:3; + /** gamma_x00 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 0 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x00:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_x1_reg_t; + +/** Type of gamma_x2 register + * point of X-axis of r/g/b channel gamma curve register 2 + */ +typedef union { + struct { + /** gamma_x0f : R/W; bitpos: [2:0]; default: 4; + * this field configures the point 15 of X-axis of r/g/b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_x0f:3; + /** gamma_x0e : R/W; bitpos: [5:3]; default: 4; + * this field configures the point 14 of X-axis of r/g/b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_x0e:3; + /** gamma_x0d : R/W; bitpos: [8:6]; default: 4; + * this field configures the point 13 of X-axis of r/g/b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_x0d:3; + /** gamma_x0c : R/W; bitpos: [11:9]; default: 4; + * this field configures the point 12 of X-axis of r/g/b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_x0c:3; + /** gamma_x0b : R/W; bitpos: [14:12]; default: 4; + * this field configures the point 11 of X-axis of r/g/b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_x0b:3; + /** gamma_x0a : R/W; bitpos: [17:15]; default: 4; + * this field configures the point 10 of X-axis of r/g/b channel gamma curve, it + * represents the power of the distance from the previous point + */ + uint32_t gamma_x0a:3; + /** gamma_x09 : R/W; bitpos: [20:18]; default: 4; + * this field configures the point 9 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x09:3; + /** gamma_x08 : R/W; bitpos: [23:21]; default: 4; + * this field configures the point 8 of X-axis of r/g/b channel gamma curve, it represents + * the power of the distance from the previous point + */ + uint32_t gamma_x08:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_gamma_x2_reg_t; + +/** Type of ae_ctrl register + * ae control register + */ +typedef union { + struct { + /** ae_update : WT; bitpos: [0]; default: 0; + * write 1 to this bit triggers one statistic event + */ + uint32_t ae_update:1; + /** ae_select : R/W; bitpos: [1]; default: 0; + * this field configures ae input data source, 0: data from median, 1: data from gama + */ + uint32_t ae_select:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_ae_ctrl_reg_t; + +/** Type of ae_monitor register + * ae monitor control register + */ +typedef union { + struct { + /** ae_monitor_tl : R/W; bitpos: [7:0]; default: 0; + * this field configures the lower lum threshold of ae monitor + */ + uint32_t ae_monitor_tl:8; + /** ae_monitor_th : R/W; bitpos: [15:8]; default: 0; + * this field configures the higher lum threshold of ae monitor + */ + uint32_t ae_monitor_th:8; + /** ae_monitor_period : R/W; bitpos: [21:16]; default: 0; + * this field configures ae monitor frame period + */ + uint32_t ae_monitor_period:6; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_ae_monitor_reg_t; + +/** Type of ae_bx register + * ae window register in x-direction + */ +typedef union { + struct { + /** ae_x_bsize : R/W; bitpos: [10:0]; default: 384; + * this field configures every block x size + */ + uint32_t ae_x_bsize:11; + /** ae_x_start : R/W; bitpos: [21:11]; default: 0; + * this field configures first block start x address + */ + uint32_t ae_x_start:11; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_ae_bx_reg_t; + +/** Type of ae_by register + * ae window register in y-direction + */ +typedef union { + struct { + /** ae_y_bsize : R/W; bitpos: [10:0]; default: 216; + * this field configures every block y size + */ + uint32_t ae_y_bsize:11; + /** ae_y_start : R/W; bitpos: [21:11]; default: 0; + * this field configures first block start y address + */ + uint32_t ae_y_start:11; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_ae_by_reg_t; + +/** Type of ae_winpixnum register + * ae sub-window pix num register + */ +typedef union { + struct { + /** ae_subwin_pixnum : R/W; bitpos: [16:0]; default: 82944; + * this field configures the pixel number of each sub win + */ + uint32_t ae_subwin_pixnum:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_ae_winpixnum_reg_t; + +/** Type of ae_win_reciprocal register + * reciprocal of ae sub-window pixel number + */ +typedef union { + struct { + /** ae_subwin_recip : R/W; bitpos: [19:0]; default: 0; + * this field configures the reciprocal of each subwin_pixnum, 20bit fraction + */ + uint32_t ae_subwin_recip:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} isp_ae_win_reciprocal_reg_t; + +/** Type of sharp_ctrl0 register + * sharp control register 0 + */ +typedef union { + struct { + /** sharp_threshold_low : R/W; bitpos: [7:0]; default: 0; + * this field configures sharpen threshold for detail + */ + uint32_t sharp_threshold_low:8; + /** sharp_threshold_high : R/W; bitpos: [15:8]; default: 0; + * this field configures sharpen threshold for edge + */ + uint32_t sharp_threshold_high:8; + /** sharp_amount_low : R/W; bitpos: [23:16]; default: 0; + * this field configures sharpen amount for detail + */ + uint32_t sharp_amount_low:8; + /** sharp_amount_high : R/W; bitpos: [31:24]; default: 0; + * this field configures sharpen amount for edge + */ + uint32_t sharp_amount_high:8; + }; + uint32_t val; +} isp_sharp_ctrl0_reg_t; + +/** Type of sharp_filter0 register + * sharp usm config register 0 + */ +typedef union { + struct { + /** sharp_filter_coe00 : R/W; bitpos: [4:0]; default: 1; + * this field configures unsharp masking(usm) filter coefficient + */ + uint32_t sharp_filter_coe00:5; + /** sharp_filter_coe01 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe01:5; + /** sharp_filter_coe02 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe02:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter0_reg_t; + +/** Type of sharp_filter1 register + * sharp usm config register 1 + */ +typedef union { + struct { + /** sharp_filter_coe10 : R/W; bitpos: [4:0]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe10:5; + /** sharp_filter_coe11 : R/W; bitpos: [9:5]; default: 4; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe11:5; + /** sharp_filter_coe12 : R/W; bitpos: [14:10]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe12:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter1_reg_t; + +/** Type of sharp_filter2 register + * sharp usm config register 2 + */ +typedef union { + struct { + /** sharp_filter_coe20 : R/W; bitpos: [4:0]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe20:5; + /** sharp_filter_coe21 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe21:5; + /** sharp_filter_coe22 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe22:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter2_reg_t; + +typedef union { + struct { + /** sharp_filter_coe0 : R/W; bitpos: [4:0]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe0:5; + /** sharp_filter_coe1 : R/W; bitpos: [9:5]; default: 2; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe1:5; + /** sharp_filter_coe2 : R/W; bitpos: [14:10]; default: 1; + * this field configures usm filter coefficient + */ + uint32_t sharp_filter_coe2:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_sharp_filter_reg_t; + +/** Type of sharp_matrix_ctrl register + * sharp pix2matrix ctrl + */ +typedef union { + struct { + /** sharp_tail_pixen_pulse_tl : R/W; bitpos: [7:0]; default: 0; + * matrix tail pixen low level threshold, should not to large to prevent expanding to + * next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and + * reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < + * reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + */ + uint32_t sharp_tail_pixen_pulse_tl:8; + /** sharp_tail_pixen_pulse_th : R/W; bitpos: [15:8]; default: 0; + * matrix tail pixen high level threshold, must < hnum-1, only + * reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and + * reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail + * pulse function + */ + uint32_t sharp_tail_pixen_pulse_th:8; + /** sharp_padding_data : R/W; bitpos: [23:16]; default: 0; + * this field configures sharp padding data + */ + uint32_t sharp_padding_data:8; + /** sharp_padding_mode : R/W; bitpos: [24]; default: 0; + * this field configures sharp padding mode + */ + uint32_t sharp_padding_mode:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_sharp_matrix_ctrl_reg_t; + +/** Type of sharp_ctrl1 register + * sharp control register 1 + */ +typedef union { + struct { + /** sharp_gradient_max : RO; bitpos: [7:0]; default: 0; + * this field configures sharp max gradient, refresh at the end of each frame end + */ + uint32_t sharp_gradient_max:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} isp_sharp_ctrl1_reg_t; + +/** Type of dma_cntl register + * isp dma source trans control register + */ +typedef union { + struct { + /** dma_en : WT; bitpos: [0]; default: 0; + * write 1 to trigger dma to get 1 frame + */ + uint32_t dma_en:1; + /** dma_update_reg : R/W; bitpos: [1]; default: 0; + * write 1 to update reg_dma_burst_len & reg_dma_data_type + */ + uint32_t dma_update_reg:1; + /** dma_data_type : R/W; bitpos: [7:2]; default: 42; + * this field configures the idi data type for image data + */ + uint32_t dma_data_type:6; + /** dma_burst_len : R/W; bitpos: [19:8]; default: 128; + * this field configures dma burst len when data source is dma. set according to + * dma_msize, it is the number of 64bits in a dma transfer + */ + uint32_t dma_burst_len:12; + /** dma_interval : R/W; bitpos: [31:20]; default: 1; + * this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... + */ + uint32_t dma_interval:12; + }; + uint32_t val; +} isp_dma_cntl_reg_t; + +/** Type of dma_raw_data register + * isp dma source total raw number set register + */ +typedef union { + struct { + /** dma_raw_num_total : R/W; bitpos: [21:0]; default: 0; + * this field configures the the number of 64bits in a frame + */ + uint32_t dma_raw_num_total:22; + uint32_t reserved_22:9; + /** dma_raw_num_total_set : WT; bitpos: [31]; default: 0; + * write 1 to update reg_dma_raw_num_total + */ + uint32_t dma_raw_num_total_set:1; + }; + uint32_t val; +} isp_dma_raw_data_reg_t; + +/** Type of cam_cntl register + * isp cam source control register + */ +typedef union { + struct { + /** cam_en : R/W; bitpos: [0]; default: 0; + * write 1 to start receive camera data, write 0 to disable + */ + uint32_t cam_en:1; + /** cam_update_reg : R/W; bitpos: [1]; default: 0; + * write 1 to update ISP_CAM_CONF + */ + uint32_t cam_update_reg:1; + /** cam_reset : R/W; bitpos: [2]; default: 1; + * this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset + */ + uint32_t cam_reset:1; + /** cam_clk_inv : R/W; bitpos: [3]; default: 0; + * this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1: + * invert cam clk + */ + uint32_t cam_clk_inv:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_cam_cntl_reg_t; + +/** Type of cam_conf register + * isp cam source config register + */ +typedef union { + struct { + /** cam_data_order : R/W; bitpos: [0]; default: 0; + * this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], + * cam_data_in[15:8]} + */ + uint32_t cam_data_order:1; + /** cam_2byte_mode : R/W; bitpos: [1]; default: 0; + * this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: + * disable, 1: enable + */ + uint32_t cam_2byte_mode:1; + /** cam_data_type : R/W; bitpos: [7:2]; default: 42; + * this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: + * RAW12 + */ + uint32_t cam_data_type:6; + /** cam_de_inv : R/W; bitpos: [8]; default: 0; + * this bit configures cam data enable invert. 0: not invert, 1: invert + */ + uint32_t cam_de_inv:1; + /** cam_hsync_inv : R/W; bitpos: [9]; default: 0; + * this bit configures cam hsync invert. 0: not invert, 1: invert + */ + uint32_t cam_hsync_inv:1; + /** cam_vsync_inv : R/W; bitpos: [10]; default: 0; + * this bit configures cam vsync invert. 0: not invert, 1: invert + */ + uint32_t cam_vsync_inv:1; + /** cam_vsync_filter_thres : R/W; bitpos: [13:11]; default: 0; + * this bit configures the number of clock of vsync filter length + */ + uint32_t cam_vsync_filter_thres:3; + /** cam_vsync_filter_en : R/W; bitpos: [14]; default: 0; + * this bit configures vsync filter en + */ + uint32_t cam_vsync_filter_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} isp_cam_conf_reg_t; + +/** Type of af_ctrl0 register + * af control register 0 + */ +typedef union { + struct { + /** af_auto_update : R/W; bitpos: [0]; default: 0; + * this bit configures auto_update enable. when set to 1, will update sum and lum each + * frame + */ + uint32_t af_auto_update:1; + uint32_t reserved_1:3; + /** af_manual_update : WT; bitpos: [4]; default: 0; + * write 1 to this bit will update the sum and lum once + */ + uint32_t af_manual_update:1; + uint32_t reserved_5:3; + /** af_env_threshold : R/W; bitpos: [11:8]; default: 0; + * this field configures env threshold. when both sum and lum changes larger than this + * value, consider environment changes and need to trigger a new autofocus. 4Bit + * fractional + */ + uint32_t af_env_threshold:4; + uint32_t reserved_12:4; + /** af_env_period : R/W; bitpos: [23:16]; default: 0; + * this field configures environment changes detection period (frame). When set to 0, + * disable this function + */ + uint32_t af_env_period:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_af_ctrl0_reg_t; + +/** Type of af_ctrl1 register + * af control register 1 + */ +typedef union { + struct { + /** af_thpixnum : R/W; bitpos: [21:0]; default: 0; + * this field configures pixnum used when calculating the autofocus threshold. Set to + * 0 to disable threshold calculation + */ + uint32_t af_thpixnum:22; + uint32_t reserved_22:10; + }; + uint32_t val; +} isp_af_ctrl1_reg_t; + +/** Type of af_gen_th_ctrl register + * af gen threshold control register + */ +typedef union { + struct { + /** af_gen_threshold_min : R/W; bitpos: [15:0]; default: 128; + * this field configures min threshold when use auto_threshold + */ + uint32_t af_gen_threshold_min:16; + /** af_gen_threshold_max : R/W; bitpos: [31:16]; default: 1088; + * this field configures max threshold when use auto_threshold + */ + uint32_t af_gen_threshold_max:16; + }; + uint32_t val; +} isp_af_gen_th_ctrl_reg_t; + +/** Type of af_env_user_th_sum register + * af monitor user sum threshold register + */ +typedef union { + struct { + /** af_env_user_threshold_sum : R/W; bitpos: [31:0]; default: 0; + * this field configures user setup env detect sum threshold + */ + uint32_t af_env_user_threshold_sum:32; + }; + uint32_t val; +} isp_af_env_user_th_sum_reg_t; + +/** Type of af_env_user_th_lum register + * af monitor user lum threshold register + */ +typedef union { + struct { + /** af_env_user_threshold_lum : R/W; bitpos: [29:0]; default: 0; + * this field configures user setup env detect lum threshold + */ + uint32_t af_env_user_threshold_lum:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_env_user_th_lum_reg_t; + +/** Type of af_threshold register + * af threshold register + */ +typedef union { + struct { + /** af_threshold : R/W; bitpos: [15:0]; default: 256; + * this field configures user threshold. When set to non-zero, autofocus will use this + * threshold + */ + uint32_t af_threshold:16; + /** af_gen_threshold : RO; bitpos: [31:16]; default: 0; + * this field represents the last calculated threshold + */ + uint32_t af_gen_threshold:16; + }; + uint32_t val; +} isp_af_threshold_reg_t; + +/** Type of af_hscale_a register + * h-scale of af window a register + */ +typedef union { + struct { + /** af_rpoint_a : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window a, must >= 2 + */ + uint32_t af_rpoint_a:12; + uint32_t reserved_12:4; + /** af_lpoint_a : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window a, must >= 2 + */ + uint32_t af_lpoint_a:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_hscale_a_reg_t; + +/** Type of af_vscale_a register + * v-scale of af window a register + */ +typedef union { + struct { + /** af_bpoint_a : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window a, must <= hnum-2 + */ + uint32_t af_bpoint_a:12; + uint32_t reserved_12:4; + /** af_tpoint_a : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window a, must <= hnum-2 + */ + uint32_t af_tpoint_a:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_vscale_a_reg_t; + +/** Type of af_hscale_b register + * h-scale of af window b register + */ +typedef union { + struct { + /** af_rpoint_b : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window b, must >= 2 + */ + uint32_t af_rpoint_b:12; + uint32_t reserved_12:4; + /** af_lpoint_b : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window b, must >= 2 + */ + uint32_t af_lpoint_b:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_hscale_b_reg_t; + +/** Type of af_vscale_b register + * v-scale of af window b register + */ +typedef union { + struct { + /** af_bpoint_b : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window b, must <= hnum-2 + */ + uint32_t af_bpoint_b:12; + uint32_t reserved_12:4; + /** af_tpoint_b : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window b, must <= hnum-2 + */ + uint32_t af_tpoint_b:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_vscale_b_reg_t; + +/** Type of af_hscale_c register + * v-scale of af window c register + */ +typedef union { + struct { + /** af_rpoint_c : R/W; bitpos: [11:0]; default: 128; + * this field configures left coordinate of focus window c, must >= 2 + */ + uint32_t af_rpoint_c:12; + uint32_t reserved_12:4; + /** af_lpoint_c : R/W; bitpos: [27:16]; default: 1; + * this field configures top coordinate of focus window c, must >= 2 + */ + uint32_t af_lpoint_c:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_hscale_c_reg_t; + +/** Type of af_vscale_c register + * v-scale of af window c register + */ +typedef union { + struct { + /** af_bpoint_c : R/W; bitpos: [11:0]; default: 128; + * this field configures right coordinate of focus window c, must <= hnum-2 + */ + uint32_t af_bpoint_c:12; + uint32_t reserved_12:4; + /** af_tpoint_c : R/W; bitpos: [27:16]; default: 1; + * this field configures bottom coordinate of focus window c, must <= hnum-2 + */ + uint32_t af_tpoint_c:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_vscale_c_reg_t; + +/** Type of awb_mode register + * awb mode control register + */ +typedef union { + struct { + /** awb_mode : R/W; bitpos: [1:0]; default: 3; + * this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel + * algo1. 11: sel both algo0 and algo1 + */ + uint32_t awb_mode:2; + uint32_t reserved_2:2; + /** awb_sample : R/W; bitpos: [4]; default: 0; + * this bit configures awb sample location, 0:before ccm, 1:after ccm + */ + uint32_t awb_sample:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} isp_awb_mode_reg_t; + +/** Type of awb_hscale register + * h-scale of awb window + */ +typedef union { + struct { + /** awb_rpoint : R/W; bitpos: [11:0]; default: 1919; + * this field configures awb window right coordinate + */ + uint32_t awb_rpoint:12; + uint32_t reserved_12:4; + /** awb_lpoint : R/W; bitpos: [27:16]; default: 0; + * this field configures awb window left coordinate + */ + uint32_t awb_lpoint:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_awb_hscale_reg_t; + +/** Type of awb_vscale register + * v-scale of awb window + */ +typedef union { + struct { + /** awb_bpoint : R/W; bitpos: [11:0]; default: 1079; + * this field configures awb window bottom coordinate + */ + uint32_t awb_bpoint:12; + uint32_t reserved_12:4; + /** awb_tpoint : R/W; bitpos: [27:16]; default: 0; + * this field configures awb window top coordinate + */ + uint32_t awb_tpoint:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_awb_vscale_reg_t; + +/** Type of awb_th_lum register + * awb lum threshold register + */ +typedef union { + struct { + /** awb_min_lum : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of r+g+b + */ + uint32_t awb_min_lum:10; + uint32_t reserved_10:6; + /** awb_max_lum : R/W; bitpos: [25:16]; default: 765; + * this field configures upper threshold of r+g+b + */ + uint32_t awb_max_lum:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_awb_th_lum_reg_t; + +/** Type of awb_th_rg register + * awb r/g threshold register + */ +typedef union { + struct { + /** awb_min_rg : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of r/g, 2bit integer and 8bit fraction + */ + uint32_t awb_min_rg:10; + uint32_t reserved_10:6; + /** awb_max_rg : R/W; bitpos: [25:16]; default: 1023; + * this field configures upper threshold of r/g, 2bit integer and 8bit fraction + */ + uint32_t awb_max_rg:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_awb_th_rg_reg_t; + +/** Type of awb_th_bg register + * awb b/g threshold register + */ +typedef union { + struct { + /** awb_min_bg : R/W; bitpos: [9:0]; default: 0; + * this field configures lower threshold of b/g, 2bit integer and 8bit fraction + */ + uint32_t awb_min_bg:10; + uint32_t reserved_10:6; + /** awb_max_bg : R/W; bitpos: [25:16]; default: 1023; + * this field configures upper threshold of b/g, 2bit integer and 8bit fraction + */ + uint32_t awb_max_bg:10; + uint32_t reserved_26:6; + }; + uint32_t val; +} isp_awb_th_bg_reg_t; + +/** Type of color_ctrl register + * color control register + */ +typedef union { + struct { + /** color_saturation : R/W; bitpos: [7:0]; default: 128; + * this field configures the color saturation value + */ + uint32_t color_saturation:8; + /** color_hue : R/W; bitpos: [15:8]; default: 0; + * this field configures the color hue angle + */ + uint32_t color_hue:8; + /** color_contrast : R/W; bitpos: [23:16]; default: 128; + * this field configures the color contrast value + */ + uint32_t color_contrast:8; + /** color_brightness : R/W; bitpos: [31:24]; default: 0; + * this field configures the color brightness value, signed 2's complement + */ + uint32_t color_brightness:8; + }; + uint32_t val; +} isp_color_ctrl_reg_t; + +/** Type of blc_value register + * blc black level register + */ +typedef union { + struct { + /** blc_r3_value : R/W; bitpos: [7:0]; default: 0; + * this field configures the black level of bottom right channel of bayer img + */ + uint32_t blc_r3_value:8; + /** blc_r2_value : R/W; bitpos: [15:8]; default: 0; + * this field configures the black level of bottom left channel of bayer img + */ + uint32_t blc_r2_value:8; + /** blc_r1_value : R/W; bitpos: [23:16]; default: 0; + * this field configures the black level of top right channel of bayer img + */ + uint32_t blc_r1_value:8; + /** blc_r0_value : R/W; bitpos: [31:24]; default: 0; + * this field configures the black level of top left channel of bayer img + */ + uint32_t blc_r0_value:8; + }; + uint32_t val; +} isp_blc_value_reg_t; + +/** Type of blc_ctrl0 register + * blc stretch control register + */ +typedef union { + struct { + /** blc_r3_stretch : R/W; bitpos: [0]; default: 0; + * this bit configures the stretch feature of bottom right channel. 0: stretch + * disable, 1: stretch enable + */ + uint32_t blc_r3_stretch:1; + /** blc_r2_stretch : R/W; bitpos: [1]; default: 0; + * this bit configures the stretch feature of bottom left channel. 0: stretch disable, + * 1: stretch enable + */ + uint32_t blc_r2_stretch:1; + /** blc_r1_stretch : R/W; bitpos: [2]; default: 0; + * this bit configures the stretch feature of top right channel. 0: stretch disable, + * 1: stretch enable + */ + uint32_t blc_r1_stretch:1; + /** blc_r0_stretch : R/W; bitpos: [3]; default: 0; + * this bit configures the stretch feature of top left channel. 0: stretch disable, 1: + * stretch enable + */ + uint32_t blc_r0_stretch:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} isp_blc_ctrl0_reg_t; + +/** Type of blc_ctrl1 register + * blc window control register + */ +typedef union { + struct { + /** blc_window_top : R/W; bitpos: [10:0]; default: 0; + * this field configures blc average calculation window top + */ + uint32_t blc_window_top:11; + /** blc_window_left : R/W; bitpos: [21:11]; default: 0; + * this field configures blc average calculation window left + */ + uint32_t blc_window_left:11; + /** blc_window_vnum : R/W; bitpos: [25:22]; default: 0; + * this field configures blc average calculation window vnum + */ + uint32_t blc_window_vnum:4; + /** blc_window_hnum : R/W; bitpos: [29:26]; default: 0; + * this field configures blc average calculation window hnum + */ + uint32_t blc_window_hnum:4; + /** blc_filter_en : R/W; bitpos: [30]; default: 0; + * this bit configures enable blc average input filter. 0: disable, 1: enable + */ + uint32_t blc_filter_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} isp_blc_ctrl1_reg_t; + +/** Type of blc_ctrl2 register + * blc black threshold control register + */ +typedef union { + struct { + /** blc_r3_th : R/W; bitpos: [7:0]; default: 0; + * this field configures black threshold when get blc average of bottom right channel + */ + uint32_t blc_r3_th:8; + /** blc_r2_th : R/W; bitpos: [15:8]; default: 0; + * this field configures black threshold when get blc average of bottom left channel + */ + uint32_t blc_r2_th:8; + /** blc_r1_th : R/W; bitpos: [23:16]; default: 0; + * this field configures black threshold when get blc average of top right channel + */ + uint32_t blc_r1_th:8; + /** blc_r0_th : R/W; bitpos: [31:24]; default: 0; + * this field configures black threshold when get blc average of top left channel + */ + uint32_t blc_r0_th:8; + }; + uint32_t val; +} isp_blc_ctrl2_reg_t; + +/** Type of hist_mode register + * histogram mode control register + */ +typedef union { + struct { + /** hist_mode : R/W; bitpos: [2:0]; default: 4; + * this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: + * RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V + */ + uint32_t hist_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} isp_hist_mode_reg_t; + +/** Type of hist_coeff register + * histogram rgb to gray coefficients register + */ +typedef union { + struct { + /** hist_coeff_b : R/W; bitpos: [7:0]; default: 85; + * this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ + uint32_t hist_coeff_b:8; + /** hist_coeff_g : R/W; bitpos: [15:8]; default: 85; + * this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ + uint32_t hist_coeff_g:8; + /** hist_coeff_r : R/W; bitpos: [23:16]; default: 85; + * this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r + * and coeff_g and coeff_b should be 256 + */ + uint32_t hist_coeff_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_hist_coeff_reg_t; + +/** Type of hist_offs register + * histogram window offsets register + */ +typedef union { + struct { + /** hist_y_offs : R/W; bitpos: [11:0]; default: 0; + * this field configures y coordinate of first window + */ + uint32_t hist_y_offs:12; + uint32_t reserved_12:4; + /** hist_x_offs : R/W; bitpos: [27:16]; default: 0; + * this field configures x coordinate of first window + */ + uint32_t hist_x_offs:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_hist_offs_reg_t; + +/** Type of hist_size register + * histogram sub-window size register + */ +typedef union { + struct { + /** hist_y_size : R/W; bitpos: [8:0]; default: 32; + * this field configures y direction size of subwindow + */ + uint32_t hist_y_size:9; + uint32_t reserved_9:7; + /** hist_x_size : R/W; bitpos: [24:16]; default: 18; + * this field configures x direction size of subwindow + */ + uint32_t hist_x_size:9; + uint32_t reserved_25:7; + }; + uint32_t val; +} isp_hist_size_reg_t; + +/** Type of hist_seg register + * histogram bin control register + */ +typedef union { + struct { + /** hist_seg: R/W; + * default: + * 16, 32, 48, 64, + * 80, 96, 112, 128, + * 144, 160, 176, 192, + * 208, 224, 240 + * this field configures threshold of histogram + */ + uint8_t hist_seg_b[4]; + }; + uint32_t val; +} isp_hist_seg_reg_t; + + +/** Type of hist_seg0 register + * histogram bin control register 0 + */ +typedef union { + struct { + /** hist_seg_3_4 : R/W; bitpos: [7:0]; default: 64; + * this field configures threshold of histogram bin 3 and bin 4 + */ + uint32_t hist_seg_3_4:8; + /** hist_seg_2_3 : R/W; bitpos: [15:8]; default: 48; + * this field configures threshold of histogram bin 2 and bin 3 + */ + uint32_t hist_seg_2_3:8; + /** hist_seg_1_2 : R/W; bitpos: [23:16]; default: 32; + * this field configures threshold of histogram bin 1 and bin 2 + */ + uint32_t hist_seg_1_2:8; + /** hist_seg_0_1 : R/W; bitpos: [31:24]; default: 16; + * this field configures threshold of histogram bin 0 and bin 1 + */ + uint32_t hist_seg_0_1:8; + }; + uint32_t val; +} isp_hist_seg0_reg_t; + +/** Type of hist_seg1 register + * histogram bin control register 1 + */ +typedef union { + struct { + /** hist_seg_7_8 : R/W; bitpos: [7:0]; default: 128; + * this field configures threshold of histogram bin 7 and bin 8 + */ + uint32_t hist_seg_7_8:8; + /** hist_seg_6_7 : R/W; bitpos: [15:8]; default: 112; + * this field configures threshold of histogram bin 6 and bin 7 + */ + uint32_t hist_seg_6_7:8; + /** hist_seg_5_6 : R/W; bitpos: [23:16]; default: 96; + * this field configures threshold of histogram bin 5 and bin 6 + */ + uint32_t hist_seg_5_6:8; + /** hist_seg_4_5 : R/W; bitpos: [31:24]; default: 80; + * this field configures threshold of histogram bin 4 and bin 5 + */ + uint32_t hist_seg_4_5:8; + }; + uint32_t val; +} isp_hist_seg1_reg_t; + +/** Type of hist_seg2 register + * histogram bin control register 2 + */ +typedef union { + struct { + /** hist_seg_11_12 : R/W; bitpos: [7:0]; default: 192; + * this field configures threshold of histogram bin 11 and bin 12 + */ + uint32_t hist_seg_11_12:8; + /** hist_seg_10_11 : R/W; bitpos: [15:8]; default: 176; + * this field configures threshold of histogram bin 10 and bin 11 + */ + uint32_t hist_seg_10_11:8; + /** hist_seg_9_10 : R/W; bitpos: [23:16]; default: 160; + * this field configures threshold of histogram bin 9 and bin 10 + */ + uint32_t hist_seg_9_10:8; + /** hist_seg_8_9 : R/W; bitpos: [31:24]; default: 144; + * this field configures threshold of histogram bin 8 and bin 9 + */ + uint32_t hist_seg_8_9:8; + }; + uint32_t val; +} isp_hist_seg2_reg_t; + +/** Type of hist_seg3 register + * histogram bin control register 3 + */ +typedef union { + struct { + /** hist_seg_14_15 : R/W; bitpos: [7:0]; default: 240; + * this field configures threshold of histogram bin 14 and bin 15 + */ + uint32_t hist_seg_14_15:8; + /** hist_seg_13_14 : R/W; bitpos: [15:8]; default: 224; + * this field configures threshold of histogram bin 13 and bin 14 + */ + uint32_t hist_seg_13_14:8; + /** hist_seg_12_13 : R/W; bitpos: [23:16]; default: 208; + * this field configures threshold of histogram bin 12 and bin 13 + */ + uint32_t hist_seg_12_13:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_hist_seg3_reg_t; + +/** Type of hist_weight register + * histogram sub-window weight register 0 + */ +typedef union { + struct { + /** histogram weight : RO; bitpos: [31:0]; + * weight[12] default 232, others default 1 + * this field represents the weight of histogram subwindow, sum of all weight should be 256 + */ + uint8_t hist_weight_b[4]; + }; + uint32_t val; +} isp_hist_weight_reg_t; + +/** Type of hist_weight0 register + * histogram sub-window weight register 0 + */ +typedef union { + struct { + /** hist_weight_03 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 03 + */ + uint32_t hist_weight_03:8; + /** hist_weight_02 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 02 + */ + uint32_t hist_weight_02:8; + /** hist_weight_01 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 01 + */ + uint32_t hist_weight_01:8; + /** hist_weight_00 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 00 and sum of all weight should be 256 + */ + uint32_t hist_weight_00:8; + }; + uint32_t val; +} isp_hist_weight0_reg_t; + +/** Type of hist_weight1 register + * histogram sub-window weight register 1 + */ +typedef union { + struct { + /** hist_weight_12 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 12 + */ + uint32_t hist_weight_12:8; + /** hist_weight_11 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 11 + */ + uint32_t hist_weight_11:8; + /** hist_weight_10 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 10 + */ + uint32_t hist_weight_10:8; + /** hist_weight_04 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 04 + */ + uint32_t hist_weight_04:8; + }; + uint32_t val; +} isp_hist_weight1_reg_t; + +/** Type of hist_weight2 register + * histogram sub-window weight register 2 + */ +typedef union { + struct { + /** hist_weight_21 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 21 + */ + uint32_t hist_weight_21:8; + /** hist_weight_20 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 20 + */ + uint32_t hist_weight_20:8; + /** hist_weight_14 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 04 + */ + uint32_t hist_weight_14:8; + /** hist_weight_13 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 13 + */ + uint32_t hist_weight_13:8; + }; + uint32_t val; +} isp_hist_weight2_reg_t; + +/** Type of hist_weight3 register + * histogram sub-window weight register 3 + */ +typedef union { + struct { + /** hist_weight_30 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 30 + */ + uint32_t hist_weight_30:8; + /** hist_weight_24 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 24 + */ + uint32_t hist_weight_24:8; + /** hist_weight_23 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 23 + */ + uint32_t hist_weight_23:8; + /** hist_weight_22 : R/W; bitpos: [31:24]; default: 232; + * this field configures weight of subwindow 22 + */ + uint32_t hist_weight_22:8; + }; + uint32_t val; +} isp_hist_weight3_reg_t; + +/** Type of hist_weight4 register + * histogram sub-window weight register 4 + */ +typedef union { + struct { + /** hist_weight_34 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 34 + */ + uint32_t hist_weight_34:8; + /** hist_weight_33 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 33 + */ + uint32_t hist_weight_33:8; + /** hist_weight_32 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 32 + */ + uint32_t hist_weight_32:8; + /** hist_weight_31 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 31 + */ + uint32_t hist_weight_31:8; + }; + uint32_t val; +} isp_hist_weight4_reg_t; + +/** Type of hist_weight5 register + * histogram sub-window weight register 5 + */ +typedef union { + struct { + /** hist_weight_43 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 43 + */ + uint32_t hist_weight_43:8; + /** hist_weight_42 : R/W; bitpos: [15:8]; default: 1; + * this field configures weight of subwindow 42 + */ + uint32_t hist_weight_42:8; + /** hist_weight_41 : R/W; bitpos: [23:16]; default: 1; + * this field configures weight of subwindow 41 + */ + uint32_t hist_weight_41:8; + /** hist_weight_40 : R/W; bitpos: [31:24]; default: 1; + * this field configures weight of subwindow 40 + */ + uint32_t hist_weight_40:8; + }; + uint32_t val; +} isp_hist_weight5_reg_t; + +/** Type of hist_weight6 register + * histogram sub-window weight register 6 + */ +typedef union { + struct { + /** hist_weight_44 : R/W; bitpos: [7:0]; default: 1; + * this field configures weight of subwindow 44 + */ + uint32_t hist_weight_44:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} isp_hist_weight6_reg_t; + +/** Type of mem_aux_ctrl_0 register + * mem aux control register 0 + */ +typedef union { + struct { + /** header_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of isp input buffer memory + */ + uint32_t header_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** dpc_lut_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field represents this field configures the mem_aux of dpc lut memory + */ + uint32_t dpc_lut_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_0_reg_t; + +/** Type of mem_aux_ctrl_1 register + * mem aux control register 1 + */ +typedef union { + struct { + /** lsc_lut_r_gr_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of lsc r gr lut memory + */ + uint32_t lsc_lut_r_gr_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** lsc_lut_gb_b_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of lsc gb b lut memory + */ + uint32_t lsc_lut_gb_b_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_1_reg_t; + +/** Type of mem_aux_ctrl_2 register + * mem aux control register 2 + */ +typedef union { + struct { + /** bf_matrix_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of bf line buffer memory + */ + uint32_t bf_matrix_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** dpc_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of dpc line buffer memory + */ + uint32_t dpc_matrix_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_2_reg_t; + +/** Type of mem_aux_ctrl_3 register + * mem aux control register 3 + */ +typedef union { + struct { + /** sharp_matrix_y_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of sharp y line buffer memory + */ + uint32_t sharp_matrix_y_mem_aux_ctrl:14; + uint32_t reserved_14:2; + /** demosaic_matrix_mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; + * this field configures the mem_aux of demosaic line buffer memory + */ + uint32_t demosaic_matrix_mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_mem_aux_ctrl_3_reg_t; + +/** Type of mem_aux_ctrl_4 register + * mem aux control register 4 + */ +typedef union { + struct { + /** sharp_matrix_uv_mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; + * this field configures the mem_aux of sharp uv line buffer memory + */ + uint32_t sharp_matrix_uv_mem_aux_ctrl:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} isp_mem_aux_ctrl_4_reg_t; + +/** Type of yuv_format register + * yuv format control register + */ +typedef union { + struct { + /** yuv_mode : R/W; bitpos: [0]; default: 0; + * this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 + */ + uint32_t yuv_mode:1; + /** yuv_range : R/W; bitpos: [1]; default: 0; + * this bit configures the yuv range. 0: full range, 1: limit range + */ + uint32_t yuv_range:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_yuv_format_reg_t; + +/** Type of rdn_eco_low register + * rdn eco all low register + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * rdn_eco_low + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} isp_rdn_eco_low_reg_t; + +/** Type of rdn_eco_high register + * rdn eco all high register + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * rdn_eco_high + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} isp_rdn_eco_high_reg_t; + + +/** Group: Status Registers */ +/** Type of dpc_deadpix_cnt register + * DPC dead-pix number register + */ +typedef union { + struct { + /** dpc_deadpix_cnt : RO; bitpos: [9:0]; default: 0; + * this field represents the dead pixel count + */ + uint32_t dpc_deadpix_cnt:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} isp_dpc_deadpix_cnt_reg_t; + +/** Type of lut_rdata register + * LUT read data register + */ +typedef union { + struct { + /** lut_rdata : RO; bitpos: [31:0]; default: 0; + * this field represents the read data of lut. read ISP_LUT_RDATA after write + * ISP_LUT_CMD register + */ + uint32_t lut_rdata:32; + }; + uint32_t val; +} isp_lut_rdata_reg_t; + +/** Type of ae_block_mean register + * ae statistic result + */ +typedef union { + struct { + /** ae_lum : RO; bitpos: [31:0]; default: 0; + * this field represents the result of AE block + */ + uint8_t ae_b_mean[4]; + }; + uint32_t val; +} isp_ae_block_mean_reg_t; + +/** Type of ae_block_mean_0 register + * ae statistic result register 0 + */ +typedef union { + struct { + /** ae_b03_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block03 Y mean data + */ + uint32_t ae_b03_mean:8; + /** ae_b02_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block02 Y mean data + */ + uint32_t ae_b02_mean:8; + /** ae_b01_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block01 Y mean data + */ + uint32_t ae_b01_mean:8; + /** ae_b00_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block00 Y mean data + */ + uint32_t ae_b00_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_0_reg_t; + +/** Type of ae_block_mean_1 register + * ae statistic result register 1 + */ +typedef union { + struct { + /** ae_b12_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block12 Y mean data + */ + uint32_t ae_b12_mean:8; + /** ae_b11_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block11 Y mean data + */ + uint32_t ae_b11_mean:8; + /** ae_b10_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block10 Y mean data + */ + uint32_t ae_b10_mean:8; + /** ae_b04_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block04 Y mean data + */ + uint32_t ae_b04_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_1_reg_t; + +/** Type of ae_block_mean_2 register + * ae statistic result register 2 + */ +typedef union { + struct { + /** ae_b21_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block21 Y mean data + */ + uint32_t ae_b21_mean:8; + /** ae_b20_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block20 Y mean data + */ + uint32_t ae_b20_mean:8; + /** ae_b14_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block14 Y mean data + */ + uint32_t ae_b14_mean:8; + /** ae_b13_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block13 Y mean data + */ + uint32_t ae_b13_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_2_reg_t; + +/** Type of ae_block_mean_3 register + * ae statistic result register 3 + */ +typedef union { + struct { + /** ae_b30_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block30 Y mean data + */ + uint32_t ae_b30_mean:8; + /** ae_b24_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block24 Y mean data + */ + uint32_t ae_b24_mean:8; + /** ae_b23_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block23 Y mean data + */ + uint32_t ae_b23_mean:8; + /** ae_b22_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block22 Y mean data + */ + uint32_t ae_b22_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_3_reg_t; + +/** Type of ae_block_mean_4 register + * ae statistic result register 4 + */ +typedef union { + struct { + /** ae_b34_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block34 Y mean data + */ + uint32_t ae_b34_mean:8; + /** ae_b33_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block33 Y mean data + */ + uint32_t ae_b33_mean:8; + /** ae_b32_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block32 Y mean data + */ + uint32_t ae_b32_mean:8; + /** ae_b31_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block31 Y mean data + */ + uint32_t ae_b31_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_4_reg_t; + +/** Type of ae_block_mean_5 register + * ae statistic result register 5 + */ +typedef union { + struct { + /** ae_b43_mean : RO; bitpos: [7:0]; default: 0; + * this field configures block43 Y mean data + */ + uint32_t ae_b43_mean:8; + /** ae_b42_mean : RO; bitpos: [15:8]; default: 0; + * this field configures block42 Y mean data + */ + uint32_t ae_b42_mean:8; + /** ae_b41_mean : RO; bitpos: [23:16]; default: 0; + * this field configures block41 Y mean data + */ + uint32_t ae_b41_mean:8; + /** ae_b40_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block40 Y mean data + */ + uint32_t ae_b40_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_5_reg_t; + +/** Type of ae_block_mean_6 register + * ae statistic result register 6 + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** ae_b44_mean : RO; bitpos: [31:24]; default: 0; + * this field configures block44 Y mean data + */ + uint32_t ae_b44_mean:8; + }; + uint32_t val; +} isp_ae_block_mean_6_reg_t; +/** Type of af_sum_a register + * result of sum of af window a + */ +typedef union { + struct { + /** af_suma : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window a + */ + uint32_t af_suma:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_sum_a_reg_t; + +/** Type of af_sum_b register + * result of sum of af window b + */ +typedef union { + struct { + /** af_sumb : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window b + */ + uint32_t af_sumb:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_sum_b_reg_t; + +/** Type of af_sum_c register + * result of sum of af window c + */ +typedef union { + struct { + /** af_sumc : RO; bitpos: [29:0]; default: 0; + * this field represents the result of accumulation of pix grad of focus window c + */ + uint32_t af_sumc:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} isp_af_sum_c_reg_t; + +/** Type of af_lum_a register + * result of lum of af window a + */ +typedef union { + struct { + /** af_luma : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window a + */ + uint32_t af_luma:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_lum_a_reg_t; + +/** Type of af_lum_b register + * result of lum of af window b + */ +typedef union { + struct { + /** af_lumb : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window b + */ + uint32_t af_lumb:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_lum_b_reg_t; + +/** Type of af_lum_c register + * result of lum of af window c + */ +typedef union { + struct { + /** af_lumc : RO; bitpos: [27:0]; default: 0; + * this field represents the result of accumulation of pix light of focus window c + */ + uint32_t af_lumc:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} isp_af_lum_c_reg_t; + +/** Type of awb0_white_cnt register + * result of awb white point number + */ +typedef union { + struct { + /** awb0_white_cnt : RO; bitpos: [23:0]; default: 0; + * this field configures number of white point detected of algo0 + */ + uint32_t awb0_white_cnt:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} isp_awb0_white_cnt_reg_t; + +/** Type of awb0_acc_r register + * result of accumulate of r channel of all white points + */ +typedef union { + struct { + /** awb0_acc_r : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel r of all white point of algo0 + */ + uint32_t awb0_acc_r:32; + }; + uint32_t val; +} isp_awb0_acc_r_reg_t; + +/** Type of awb0_acc_g register + * result of accumulate of g channel of all white points + */ +typedef union { + struct { + /** awb0_acc_g : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel g of all white point of algo0 + */ + uint32_t awb0_acc_g:32; + }; + uint32_t val; +} isp_awb0_acc_g_reg_t; + +/** Type of awb0_acc_b register + * result of accumulate of b channel of all white points + */ +typedef union { + struct { + /** awb0_acc_b : RO; bitpos: [31:0]; default: 0; + * this field represents accumulate of channel b of all white point of algo0 + */ + uint32_t awb0_acc_b:32; + }; + uint32_t val; +} isp_awb0_acc_b_reg_t; + +/** Type of blc_mean register + * results of the average of black window + */ +typedef union { + struct { + /** blc_r3_mean : RO; bitpos: [7:0]; default: 0; + * this field represents the average black value of bottom right channel + */ + uint32_t blc_r3_mean:8; + /** blc_r2_mean : RO; bitpos: [15:8]; default: 0; + * this field represents the average black value of bottom left channel + */ + uint32_t blc_r2_mean:8; + /** blc_r1_mean : RO; bitpos: [23:16]; default: 0; + * this field represents the average black value of top right channel + */ + uint32_t blc_r1_mean:8; + /** blc_r0_mean : RO; bitpos: [31:24]; default: 0; + * this field represents the average black value of top left channel + */ + uint32_t blc_r0_mean:8; + }; + uint32_t val; +} isp_blc_mean_reg_t; + +/** Type of hist_bin register + * result of histogram bin n + */ +typedef union { + struct { + /** hist_bin_n : RO; bitpos: [16:0]; default: 0; + * this field represents result of histogram bin n + */ + uint32_t hist_bin_n:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} isp_hist_binn_reg_t; + +/** Type of rdn_eco_cs register + * rdn eco cs register + */ +typedef union { + struct { + /** rdn_eco_en : R/W; bitpos: [0]; default: 0; + * rdn_eco_en + */ + uint32_t rdn_eco_en:1; + /** rdn_eco_result : RO; bitpos: [1]; default: 0; + * rdn_eco_result + */ + uint32_t rdn_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} isp_rdn_eco_cs_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * raw interrupt register + */ +typedef union { + struct { + /** isp_data_type_err_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * the raw interrupt status of input data type error. isp only support RGB bayer data + * type, other type will report type_err_int + */ + uint32_t isp_data_type_err_int_raw:1; + /** isp_async_fifo_ovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * the raw interrupt status of isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_raw:1; + /** isp_buf_full_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * the raw interrupt status of isp input buffer full + */ + uint32_t isp_buf_full_int_raw:1; + /** isp_hvnum_setting_err_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * the raw interrupt status of hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_raw:1; + /** isp_data_type_setting_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * the raw interrupt status of setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_raw:1; + /** isp_mipi_hnum_unmatch_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * the raw interrupt status of hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_raw:1; + /** dpc_check_done_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * the raw interrupt status of dpc check done + */ + uint32_t dpc_check_done_int_raw:1; + /** gamma_xcoord_err_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * the raw interrupt status of gamma setting error. it report the sum of the lengths + * represented by reg_gamma_x00~x0F isn't equal to 256 + */ + uint32_t gamma_xcoord_err_int_raw:1; + /** ae_monitor_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * the raw interrupt status of ae monitor + */ + uint32_t ae_monitor_int_raw:1; + /** ae_frame_done_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * the raw interrupt status of ae. + */ + uint32_t ae_frame_done_int_raw:1; + /** af_fdone_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * the raw interrupt status of af statistic. when auto_update enable, each frame done + * will send one int pulse when manual_update, each time when write 1 to + * reg_manual_update will send a int pulse when next frame done + */ + uint32_t af_fdone_int_raw:1; + /** af_env_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * the raw interrupt status of af monitor. send a int pulse when env_det function + * enabled and environment changes detected + */ + uint32_t af_env_int_raw:1; + /** awb_fdone_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * the raw interrupt status of awb. send a int pulse when statistic of one awb frame + * done + */ + uint32_t awb_fdone_int_raw:1; + /** hist_fdone_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * the raw interrupt status of histogram. send a int pulse when statistic of one frame + * histogram done + */ + uint32_t hist_fdone_int_raw:1; + /** frame_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * the raw interrupt status of isp frame end + */ + uint32_t frame_int_raw:1; + /** blc_frame_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * the raw interrupt status of blc frame done + */ + uint32_t blc_frame_int_raw:1; + /** lsc_frame_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * the raw interrupt status of lsc frame done + */ + uint32_t lsc_frame_int_raw:1; + /** dpc_frame_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * the raw interrupt status of dpc frame done + */ + uint32_t dpc_frame_int_raw:1; + /** bf_frame_int_raw : R/SS/WTC; bitpos: [18]; default: 0; + * the raw interrupt status of bf frame done + */ + uint32_t bf_frame_int_raw:1; + /** demosaic_frame_int_raw : R/SS/WTC; bitpos: [19]; default: 0; + * the raw interrupt status of demosaic frame done + */ + uint32_t demosaic_frame_int_raw:1; + /** median_frame_int_raw : R/SS/WTC; bitpos: [20]; default: 0; + * the raw interrupt status of median frame done + */ + uint32_t median_frame_int_raw:1; + /** ccm_frame_int_raw : R/SS/WTC; bitpos: [21]; default: 0; + * the raw interrupt status of ccm frame done + */ + uint32_t ccm_frame_int_raw:1; + /** gamma_frame_int_raw : R/SS/WTC; bitpos: [22]; default: 0; + * the raw interrupt status of gamma frame done + */ + uint32_t gamma_frame_int_raw:1; + /** rgb2yuv_frame_int_raw : R/SS/WTC; bitpos: [23]; default: 0; + * the raw interrupt status of rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_raw:1; + /** sharp_frame_int_raw : R/SS/WTC; bitpos: [24]; default: 0; + * the raw interrupt status of sharp frame done + */ + uint32_t sharp_frame_int_raw:1; + /** color_frame_int_raw : R/SS/WTC; bitpos: [25]; default: 0; + * the raw interrupt status of color frame done + */ + uint32_t color_frame_int_raw:1; + /** yuv2rgb_frame_int_raw : R/SS/WTC; bitpos: [26]; default: 0; + * the raw interrupt status of yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_raw:1; + /** tail_idi_frame_int_raw : R/SS/WTC; bitpos: [27]; default: 0; + * the raw interrupt status of isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_raw:1; + /** header_idi_frame_int_raw : R/SS/WTC; bitpos: [28]; default: 0; + * the raw interrupt status of real input frame end of isp_input + */ + uint32_t header_idi_frame_int_raw:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} isp_int_raw_reg_t; + +/** Type of int_st register + * masked interrupt register + */ +typedef union { + struct { + /** isp_data_type_err_int_st : RO; bitpos: [0]; default: 0; + * the masked interrupt status of input data type error + */ + uint32_t isp_data_type_err_int_st:1; + /** isp_async_fifo_ovf_int_st : RO; bitpos: [1]; default: 0; + * the masked interrupt status of isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_st:1; + /** isp_buf_full_int_st : RO; bitpos: [2]; default: 0; + * the masked interrupt status of isp input buffer full + */ + uint32_t isp_buf_full_int_st:1; + /** isp_hvnum_setting_err_int_st : RO; bitpos: [3]; default: 0; + * the masked interrupt status of hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_st:1; + /** isp_data_type_setting_err_int_st : RO; bitpos: [4]; default: 0; + * the masked interrupt status of setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_st:1; + /** isp_mipi_hnum_unmatch_int_st : RO; bitpos: [5]; default: 0; + * the masked interrupt status of hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_st:1; + /** dpc_check_done_int_st : RO; bitpos: [6]; default: 0; + * the masked interrupt status of dpc check done + */ + uint32_t dpc_check_done_int_st:1; + /** gamma_xcoord_err_int_st : RO; bitpos: [7]; default: 0; + * the masked interrupt status of gamma setting error + */ + uint32_t gamma_xcoord_err_int_st:1; + /** ae_monitor_int_st : RO; bitpos: [8]; default: 0; + * the masked interrupt status of ae monitor + */ + uint32_t ae_monitor_int_st:1; + /** ae_frame_done_int_st : RO; bitpos: [9]; default: 0; + * the masked interrupt status of ae + */ + uint32_t ae_frame_done_int_st:1; + /** af_fdone_int_st : RO; bitpos: [10]; default: 0; + * the masked interrupt status of af statistic + */ + uint32_t af_fdone_int_st:1; + /** af_env_int_st : RO; bitpos: [11]; default: 0; + * the masked interrupt status of af monitor + */ + uint32_t af_env_int_st:1; + /** awb_fdone_int_st : RO; bitpos: [12]; default: 0; + * the masked interrupt status of awb + */ + uint32_t awb_fdone_int_st:1; + /** hist_fdone_int_st : RO; bitpos: [13]; default: 0; + * the masked interrupt status of histogram + */ + uint32_t hist_fdone_int_st:1; + /** frame_int_st : RO; bitpos: [14]; default: 0; + * the masked interrupt status of isp frame end + */ + uint32_t frame_int_st:1; + /** blc_frame_int_st : RO; bitpos: [15]; default: 0; + * the masked interrupt status of blc frame done + */ + uint32_t blc_frame_int_st:1; + /** lsc_frame_int_st : RO; bitpos: [16]; default: 0; + * the masked interrupt status of lsc frame done + */ + uint32_t lsc_frame_int_st:1; + /** dpc_frame_int_st : RO; bitpos: [17]; default: 0; + * the masked interrupt status of dpc frame done + */ + uint32_t dpc_frame_int_st:1; + /** bf_frame_int_st : RO; bitpos: [18]; default: 0; + * the masked interrupt status of bf frame done + */ + uint32_t bf_frame_int_st:1; + /** demosaic_frame_int_st : RO; bitpos: [19]; default: 0; + * the masked interrupt status of demosaic frame done + */ + uint32_t demosaic_frame_int_st:1; + /** median_frame_int_st : RO; bitpos: [20]; default: 0; + * the masked interrupt status of median frame done + */ + uint32_t median_frame_int_st:1; + /** ccm_frame_int_st : RO; bitpos: [21]; default: 0; + * the masked interrupt status of ccm frame done + */ + uint32_t ccm_frame_int_st:1; + /** gamma_frame_int_st : RO; bitpos: [22]; default: 0; + * the masked interrupt status of gamma frame done + */ + uint32_t gamma_frame_int_st:1; + /** rgb2yuv_frame_int_st : RO; bitpos: [23]; default: 0; + * the masked interrupt status of rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_st:1; + /** sharp_frame_int_st : RO; bitpos: [24]; default: 0; + * the masked interrupt status of sharp frame done + */ + uint32_t sharp_frame_int_st:1; + /** color_frame_int_st : RO; bitpos: [25]; default: 0; + * the masked interrupt status of color frame done + */ + uint32_t color_frame_int_st:1; + /** yuv2rgb_frame_int_st : RO; bitpos: [26]; default: 0; + * the masked interrupt status of yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_st:1; + /** tail_idi_frame_int_st : RO; bitpos: [27]; default: 0; + * the masked interrupt status of isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_st:1; + /** header_idi_frame_int_st : RO; bitpos: [28]; default: 0; + * the masked interrupt status of real input frame end of isp_input + */ + uint32_t header_idi_frame_int_st:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} isp_int_st_reg_t; + +/** Type of int_ena register + * interrupt enable register + */ +typedef union { + struct { + /** isp_data_type_err_int_ena : R/W; bitpos: [0]; default: 1; + * write 1 to enable input data type error + */ + uint32_t isp_data_type_err_int_ena:1; + /** isp_async_fifo_ovf_int_ena : R/W; bitpos: [1]; default: 1; + * write 1 to enable isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_ena:1; + /** isp_buf_full_int_ena : R/W; bitpos: [2]; default: 0; + * write 1 to enable isp input buffer full + */ + uint32_t isp_buf_full_int_ena:1; + /** isp_hvnum_setting_err_int_ena : R/W; bitpos: [3]; default: 0; + * write 1 to enable hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_ena:1; + /** isp_data_type_setting_err_int_ena : R/W; bitpos: [4]; default: 0; + * write 1 to enable setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_ena:1; + /** isp_mipi_hnum_unmatch_int_ena : R/W; bitpos: [5]; default: 0; + * write 1 to enable hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_ena:1; + /** dpc_check_done_int_ena : R/W; bitpos: [6]; default: 1; + * write 1 to enable dpc check done + */ + uint32_t dpc_check_done_int_ena:1; + /** gamma_xcoord_err_int_ena : R/W; bitpos: [7]; default: 1; + * write 1 to enable gamma setting error + */ + uint32_t gamma_xcoord_err_int_ena:1; + /** ae_monitor_int_ena : R/W; bitpos: [8]; default: 0; + * write 1 to enable ae monitor + */ + uint32_t ae_monitor_int_ena:1; + /** ae_frame_done_int_ena : R/W; bitpos: [9]; default: 0; + * write 1 to enable ae + */ + uint32_t ae_frame_done_int_ena:1; + /** af_fdone_int_ena : R/W; bitpos: [10]; default: 0; + * write 1 to enable af statistic + */ + uint32_t af_fdone_int_ena:1; + /** af_env_int_ena : R/W; bitpos: [11]; default: 0; + * write 1 to enable af monitor + */ + uint32_t af_env_int_ena:1; + /** awb_fdone_int_ena : R/W; bitpos: [12]; default: 0; + * write 1 to enable awb + */ + uint32_t awb_fdone_int_ena:1; + /** hist_fdone_int_ena : R/W; bitpos: [13]; default: 0; + * write 1 to enable histogram + */ + uint32_t hist_fdone_int_ena:1; + /** frame_int_ena : R/W; bitpos: [14]; default: 0; + * write 1 to enable isp frame end + */ + uint32_t frame_int_ena:1; + /** blc_frame_int_ena : R/W; bitpos: [15]; default: 0; + * write 1 to enable blc frame done + */ + uint32_t blc_frame_int_ena:1; + /** lsc_frame_int_ena : R/W; bitpos: [16]; default: 0; + * write 1 to enable lsc frame done + */ + uint32_t lsc_frame_int_ena:1; + /** dpc_frame_int_ena : R/W; bitpos: [17]; default: 0; + * write 1 to enable dpc frame done + */ + uint32_t dpc_frame_int_ena:1; + /** bf_frame_int_ena : R/W; bitpos: [18]; default: 0; + * write 1 to enable bf frame done + */ + uint32_t bf_frame_int_ena:1; + /** demosaic_frame_int_ena : R/W; bitpos: [19]; default: 0; + * write 1 to enable demosaic frame done + */ + uint32_t demosaic_frame_int_ena:1; + /** median_frame_int_ena : R/W; bitpos: [20]; default: 0; + * write 1 to enable median frame done + */ + uint32_t median_frame_int_ena:1; + /** ccm_frame_int_ena : R/W; bitpos: [21]; default: 0; + * write 1 to enable ccm frame done + */ + uint32_t ccm_frame_int_ena:1; + /** gamma_frame_int_ena : R/W; bitpos: [22]; default: 0; + * write 1 to enable gamma frame done + */ + uint32_t gamma_frame_int_ena:1; + /** rgb2yuv_frame_int_ena : R/W; bitpos: [23]; default: 0; + * write 1 to enable rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_ena:1; + /** sharp_frame_int_ena : R/W; bitpos: [24]; default: 0; + * write 1 to enable sharp frame done + */ + uint32_t sharp_frame_int_ena:1; + /** color_frame_int_ena : R/W; bitpos: [25]; default: 0; + * write 1 to enable color frame done + */ + uint32_t color_frame_int_ena:1; + /** yuv2rgb_frame_int_ena : R/W; bitpos: [26]; default: 0; + * write 1 to enable yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_ena:1; + /** tail_idi_frame_int_ena : R/W; bitpos: [27]; default: 0; + * write 1 to enable isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_ena:1; + /** header_idi_frame_int_ena : R/W; bitpos: [28]; default: 0; + * write 1 to enable real input frame end of isp_input + */ + uint32_t header_idi_frame_int_ena:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} isp_int_ena_reg_t; + +/** Type of int_clr register + * interrupt clear register + */ +typedef union { + struct { + /** isp_data_type_err_int_clr : WT; bitpos: [0]; default: 0; + * write 1 to clear input data type error + */ + uint32_t isp_data_type_err_int_clr:1; + /** isp_async_fifo_ovf_int_clr : WT; bitpos: [1]; default: 0; + * write 1 to clear isp input fifo overflow + */ + uint32_t isp_async_fifo_ovf_int_clr:1; + /** isp_buf_full_int_clr : WT; bitpos: [2]; default: 0; + * write 1 to clear isp input buffer full + */ + uint32_t isp_buf_full_int_clr:1; + /** isp_hvnum_setting_err_int_clr : WT; bitpos: [3]; default: 0; + * write 1 to clear hnum and vnum setting format error + */ + uint32_t isp_hvnum_setting_err_int_clr:1; + /** isp_data_type_setting_err_int_clr : WT; bitpos: [4]; default: 0; + * write 1 to clear setting invalid reg_data_type + */ + uint32_t isp_data_type_setting_err_int_clr:1; + /** isp_mipi_hnum_unmatch_int_clr : WT; bitpos: [5]; default: 0; + * write 1 to clear hnum setting unmatch with mipi input + */ + uint32_t isp_mipi_hnum_unmatch_int_clr:1; + /** dpc_check_done_int_clr : WT; bitpos: [6]; default: 0; + * write 1 to clear dpc check done + */ + uint32_t dpc_check_done_int_clr:1; + /** gamma_xcoord_err_int_clr : WT; bitpos: [7]; default: 0; + * write 1 to clear gamma setting error + */ + uint32_t gamma_xcoord_err_int_clr:1; + /** ae_monitor_int_clr : WT; bitpos: [8]; default: 0; + * write 1 to clear ae monitor + */ + uint32_t ae_monitor_int_clr:1; + /** ae_frame_done_int_clr : WT; bitpos: [9]; default: 0; + * write 1 to clear ae + */ + uint32_t ae_frame_done_int_clr:1; + /** af_fdone_int_clr : WT; bitpos: [10]; default: 0; + * write 1 to clear af statistic + */ + uint32_t af_fdone_int_clr:1; + /** af_env_int_clr : WT; bitpos: [11]; default: 0; + * write 1 to clear af monitor + */ + uint32_t af_env_int_clr:1; + /** awb_fdone_int_clr : WT; bitpos: [12]; default: 0; + * write 1 to clear awb + */ + uint32_t awb_fdone_int_clr:1; + /** hist_fdone_int_clr : WT; bitpos: [13]; default: 0; + * write 1 to clear histogram + */ + uint32_t hist_fdone_int_clr:1; + /** frame_int_clr : WT; bitpos: [14]; default: 0; + * write 1 to clear isp frame end + */ + uint32_t frame_int_clr:1; + /** blc_frame_int_clr : WT; bitpos: [15]; default: 0; + * write 1 to clear blc frame done + */ + uint32_t blc_frame_int_clr:1; + /** lsc_frame_int_clr : WT; bitpos: [16]; default: 0; + * write 1 to clear lsc frame done + */ + uint32_t lsc_frame_int_clr:1; + /** dpc_frame_int_clr : WT; bitpos: [17]; default: 0; + * write 1 to clear dpc frame done + */ + uint32_t dpc_frame_int_clr:1; + /** bf_frame_int_clr : WT; bitpos: [18]; default: 0; + * write 1 to clear bf frame done + */ + uint32_t bf_frame_int_clr:1; + /** demosaic_frame_int_clr : WT; bitpos: [19]; default: 0; + * write 1 to clear demosaic frame done + */ + uint32_t demosaic_frame_int_clr:1; + /** median_frame_int_clr : WT; bitpos: [20]; default: 0; + * write 1 to clear median frame done + */ + uint32_t median_frame_int_clr:1; + /** ccm_frame_int_clr : WT; bitpos: [21]; default: 0; + * write 1 to clear ccm frame done + */ + uint32_t ccm_frame_int_clr:1; + /** gamma_frame_int_clr : WT; bitpos: [22]; default: 0; + * write 1 to clear gamma frame done + */ + uint32_t gamma_frame_int_clr:1; + /** rgb2yuv_frame_int_clr : WT; bitpos: [23]; default: 0; + * write 1 to clear rgb2yuv frame done + */ + uint32_t rgb2yuv_frame_int_clr:1; + /** sharp_frame_int_clr : WT; bitpos: [24]; default: 0; + * write 1 to clear sharp frame done + */ + uint32_t sharp_frame_int_clr:1; + /** color_frame_int_clr : WT; bitpos: [25]; default: 0; + * write 1 to clear color frame done + */ + uint32_t color_frame_int_clr:1; + /** yuv2rgb_frame_int_clr : WT; bitpos: [26]; default: 0; + * write 1 to clear yuv2rgb frame done + */ + uint32_t yuv2rgb_frame_int_clr:1; + /** tail_idi_frame_int_clr : WT; bitpos: [27]; default: 0; + * write 1 to clear isp_tail idi frame_end + */ + uint32_t tail_idi_frame_int_clr:1; + /** header_idi_frame_int_clr : WT; bitpos: [28]; default: 0; + * write 1 to clear real input frame end of isp_input + */ + uint32_t header_idi_frame_int_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} isp_int_clr_reg_t; + +typedef struct { + volatile isp_gamma_y1_reg_t gamma_y1; + volatile isp_gamma_y2_reg_t gamma_y2; + volatile isp_gamma_y3_reg_t gamma_y3; + volatile isp_gamma_y4_reg_t gamma_y4; +} isp_gamma_y_reg_t; + +typedef struct { + volatile isp_gamma_x1_reg_t gamma_x1; + volatile isp_gamma_x2_reg_t gamma_x2; +} isp_gamma_x_reg_t; + +typedef struct { + volatile isp_ver_date_reg_t ver_date; + volatile isp_clk_en_reg_t clk_en; + volatile isp_cntl_reg_t cntl; + volatile isp_hsync_cnt_reg_t hsync_cnt; + volatile isp_frame_cfg_reg_t frame_cfg; + volatile isp_ccm_coef0_reg_t ccm_coef0; + volatile isp_ccm_coef1_reg_t ccm_coef1; + volatile isp_ccm_coef3_reg_t ccm_coef3; + volatile isp_ccm_coef4_reg_t ccm_coef4; + volatile isp_ccm_coef5_reg_t ccm_coef5; + volatile isp_bf_matrix_ctrl_reg_t bf_matrix_ctrl; + volatile isp_bf_sigma_reg_t bf_sigma; + volatile isp_bf_gau0_reg_t bf_gau0; + volatile isp_bf_gau1_reg_t bf_gau1; + volatile isp_dpc_ctrl_reg_t dpc_ctrl; + volatile isp_dpc_conf_reg_t dpc_conf; + volatile isp_dpc_matrix_ctrl_reg_t dpc_matrix_ctrl; + volatile isp_dpc_deadpix_cnt_reg_t dpc_deadpix_cnt; + volatile isp_lut_cmd_reg_t lut_cmd; + volatile isp_lut_wdata_reg_t lut_wdata; + volatile isp_lut_rdata_reg_t lut_rdata; + volatile isp_lsc_tablesize_reg_t lsc_tablesize; + volatile isp_demosaic_matrix_ctrl_reg_t demosaic_matrix_ctrl; + volatile isp_demosaic_grad_ratio_reg_t demosaic_grad_ratio; + volatile isp_median_matrix_ctrl_reg_t median_matrix_ctrl; + volatile isp_int_raw_reg_t int_raw; + volatile isp_int_st_reg_t int_st; + volatile isp_int_ena_reg_t int_ena; + volatile isp_int_clr_reg_t int_clr; + volatile isp_gamma_ctrl_reg_t gamma_ctrl; + volatile isp_gamma_y_reg_t gamma_rgb_y[3]; // r: gamma_rgb_y[0], g: gamma_rgb_y[1], b: gamma_rgb_y[2] + volatile isp_gamma_x_reg_t gamma_rgb_x[3]; // r: gamma_rgb_x[0], g: gamma_rgb_x[1], b: gamma_rgb_x[2] + volatile isp_ae_ctrl_reg_t ae_ctrl; + volatile isp_ae_monitor_reg_t ae_monitor; + volatile isp_ae_bx_reg_t ae_bx; + volatile isp_ae_by_reg_t ae_by; + volatile isp_ae_winpixnum_reg_t ae_winpixnum; + volatile isp_ae_win_reciprocal_reg_t ae_win_reciprocal; + volatile isp_ae_block_mean_reg_t ae_block_mean[7]; + volatile isp_sharp_ctrl0_reg_t sharp_ctrl0; + volatile isp_sharp_filter_reg_t sharp_filter[3]; + volatile isp_sharp_matrix_ctrl_reg_t sharp_matrix_ctrl; + volatile isp_sharp_ctrl1_reg_t sharp_ctrl1; + volatile isp_dma_cntl_reg_t dma_cntl; + volatile isp_dma_raw_data_reg_t dma_raw_data; + volatile isp_cam_cntl_reg_t cam_cntl; + volatile isp_cam_conf_reg_t cam_conf; + volatile isp_af_ctrl0_reg_t af_ctrl0; + volatile isp_af_ctrl1_reg_t af_ctrl1; + volatile isp_af_gen_th_ctrl_reg_t af_gen_th_ctrl; + volatile isp_af_env_user_th_sum_reg_t af_env_user_th_sum; + volatile isp_af_env_user_th_lum_reg_t af_env_user_th_lum; + volatile isp_af_threshold_reg_t af_threshold; + volatile isp_af_hscale_a_reg_t af_hscale_a; + volatile isp_af_vscale_a_reg_t af_vscale_a; + volatile isp_af_hscale_b_reg_t af_hscale_b; + volatile isp_af_vscale_b_reg_t af_vscale_b; + volatile isp_af_hscale_c_reg_t af_hscale_c; + volatile isp_af_vscale_c_reg_t af_vscale_c; + volatile isp_af_sum_a_reg_t af_sum_a; + volatile isp_af_sum_b_reg_t af_sum_b; + volatile isp_af_sum_c_reg_t af_sum_c; + volatile isp_af_lum_a_reg_t af_lum_a; + volatile isp_af_lum_b_reg_t af_lum_b; + volatile isp_af_lum_c_reg_t af_lum_c; + volatile isp_awb_mode_reg_t awb_mode; + volatile isp_awb_hscale_reg_t awb_hscale; + volatile isp_awb_vscale_reg_t awb_vscale; + volatile isp_awb_th_lum_reg_t awb_th_lum; + volatile isp_awb_th_rg_reg_t awb_th_rg; + volatile isp_awb_th_bg_reg_t awb_th_bg; + volatile isp_awb0_white_cnt_reg_t awb0_white_cnt; + volatile isp_awb0_acc_r_reg_t awb0_acc_r; + volatile isp_awb0_acc_g_reg_t awb0_acc_g; + volatile isp_awb0_acc_b_reg_t awb0_acc_b; + volatile isp_color_ctrl_reg_t color_ctrl; + volatile isp_blc_value_reg_t blc_value; + volatile isp_blc_ctrl0_reg_t blc_ctrl0; + volatile isp_blc_ctrl1_reg_t blc_ctrl1; + volatile isp_blc_ctrl2_reg_t blc_ctrl2; + volatile isp_blc_mean_reg_t blc_mean; + volatile isp_hist_mode_reg_t hist_mode; + volatile isp_hist_coeff_reg_t hist_coeff; + volatile isp_hist_offs_reg_t hist_offs; + volatile isp_hist_size_reg_t hist_size; + volatile isp_hist_seg_reg_t hist_seg[4]; + volatile isp_hist_weight_reg_t hist_weight[7]; + volatile isp_hist_binn_reg_t hist_binn[16]; + volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0; + volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1; + volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2; + volatile isp_mem_aux_ctrl_3_reg_t mem_aux_ctrl_3; + volatile isp_mem_aux_ctrl_4_reg_t mem_aux_ctrl_4; + volatile isp_yuv_format_reg_t yuv_format; + volatile isp_rdn_eco_cs_reg_t rdn_eco_cs; + volatile isp_rdn_eco_low_reg_t rdn_eco_low; + volatile isp_rdn_eco_high_reg_t rdn_eco_high; +} isp_dev_t; + +extern isp_dev_t ISP; + +#ifndef __cplusplus +_Static_assert(sizeof(isp_dev_t) == 0x244, "Invalid size of isp_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/jpeg_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/jpeg_eco5_struct.h new file mode 100644 index 0000000000..c2c73c5bb5 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/jpeg_eco5_struct.h @@ -0,0 +1,1483 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of config register + * Control and configuration registers + */ +typedef union { + struct { + /** fsm_rst : WT; bitpos: [0]; default: 0; + * fsm reset + */ + uint32_t fsm_rst:1; + /** jpeg_start : WT; bitpos: [1]; default: 0; + * start to compress a new pic(in dma reg mode) + */ + uint32_t jpeg_start:1; + /** qnr_precision : R/W; bitpos: [2]; default: 0; + * 0:8bit qnr,1:12bit qnr(TBD) + */ + uint32_t qnr_precision:1; + /** ff_check_en : R/W; bitpos: [3]; default: 1; + * enable whether to add '00' after 'ff' + */ + uint32_t ff_check_en:1; + /** sample_sel : R/W; bitpos: [5:4]; default: 1; + * 0:yuv444,1:yuv422, 2:yuv420 + */ + uint32_t sample_sel:2; + /** dma_linklist_mode : RO; bitpos: [6]; default: 1; + * 1:use linklist to configure dma + */ + uint32_t dma_linklist_mode:1; + /** debug_direct_out_en : R/W; bitpos: [7]; default: 0; + * 0:normal mode,1:debug mode for direct output from input + */ + uint32_t debug_direct_out_en:1; + /** qnr_fifo_en : R/W; bitpos: [8]; default: 1; + * 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram + */ + uint32_t qnr_fifo_en:1; + /** lqnr_tbl_sel : R/W; bitpos: [10:9]; default: 0; + * choose luminance quntization table id(TBD) + */ + uint32_t lqnr_tbl_sel:2; + /** cqnr_tbl_sel : R/W; bitpos: [12:11]; default: 1; + * choose chrominance quntization table id (TBD) + */ + uint32_t cqnr_tbl_sel:2; + /** color_space : R/W; bitpos: [14:13]; default: 0; + * configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray + */ + uint32_t color_space:2; + /** dht_fifo_en : R/W; bitpos: [15]; default: 1; + * 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to + * write dht len_total/codemin/value table. Reading dht len_total/codemin/value table + * only has nonfifo way + */ + uint32_t dht_fifo_en:1; + /** mem_clk_force_on : R/W; bitpos: [16]; default: 0; + * force memory's clock enabled + */ + uint32_t mem_clk_force_on:1; + /** decode_timeout_thres : R/W; bitpos: [22:17]; default: 32; + * decode pause period to trigger decode_timeout int, the timeout periods =2 power + * (reg_decode_timeout_thres) -1 + */ + uint32_t decode_timeout_thres:6; + /** decode_timeout_task_sel : R/W; bitpos: [23]; default: 0; + * 0: software use reset to abort decode process ,1: decoder abort decode process by + * itself + */ + uint32_t decode_timeout_task_sel:1; + /** soft_rst : R/W; bitpos: [24]; default: 0; + * when set to 1, soft reset JPEG module except jpeg_reg module + */ + uint32_t soft_rst:1; + /** fifo_rst : R/W; bitpos: [25]; default: 0; + * fifo reset + */ + uint32_t fifo_rst:1; + /** pixel_rev : R/W; bitpos: [26]; default: 0; + * reverse the source color pixel + */ + uint32_t pixel_rev:1; + /** tailer_en : R/W; bitpos: [27]; default: 0; + * set this bit to add EOI of '0xffd9' at the end of bitstream + */ + uint32_t tailer_en:1; + /** pause_en : R/W; bitpos: [28]; default: 0; + * set this bit to pause jpeg encoding + */ + uint32_t pause_en:1; + /** mem_force_pd : R/W; bitpos: [29]; default: 0; + * 0: no operation,1:force jpeg memory to power down + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [30]; default: 0; + * 0: no operation,1:force jpeg memory to power up + */ + uint32_t mem_force_pu:1; + /** mode : R/W; bitpos: [31]; default: 0; + * 0:encoder mode, 1: decoder mode + */ + uint32_t mode:1; + }; + uint32_t val; +} jpeg_config_reg_t; + +/** Type of dqt_info register + * Control and configuration registers + */ +typedef union { + struct { + /** t0_dqt_info : R/W; bitpos: [7:0]; default: 0; + * Configure dqt table0's quantization coefficient precision in bit[7:4], configure + * dqt table0's table id in bit[3:0] + */ + uint32_t t0_dqt_info:8; + /** t1_dqt_info : R/W; bitpos: [15:8]; default: 1; + * Configure dqt table1's quantization coefficient precision in bit[7:4], configure + * dqt table1's table id in bit[3:0] + */ + uint32_t t1_dqt_info:8; + /** t2_dqt_info : R/W; bitpos: [23:16]; default: 2; + * Configure dqt table2's quantization coefficient precision in bit[7:4], configure + * dqt table2's table id in bit[3:0] + */ + uint32_t t2_dqt_info:8; + /** t3_dqt_info : R/W; bitpos: [31:24]; default: 3; + * Configure dqt table3's quantization coefficient precision in bit[7:4], configure + * dqt table3's table id in bit[3:0] + */ + uint32_t t3_dqt_info:8; + }; + uint32_t val; +} jpeg_dqt_info_reg_t; + +/** Type of pic_size register + * Control and configuration registers + */ +typedef union { + struct { + /** va : R/W; bitpos: [15:0]; default: 480; + * configure picture's height. when encode, the max configurable bits is 14, when + * decode, the max configurable bits is 16 + */ + uint32_t va:16; + /** ha : R/W; bitpos: [31:16]; default: 640; + * configure picture's width. when encode, the max configurable bits is 14, when + * decode, the max configurable bits is 16 + */ + uint32_t ha:16; + }; + uint32_t val; +} jpeg_pic_size_reg_t; + +/** Type of extd_config register + * Control and configuration registers + */ +typedef union { + struct { + /** extd_color_space_en : R/W; bitpos: [0]; default: 0; + * Configure whether to extend picture's color space + * 0:disable + * 1:enable + */ + uint32_t extd_color_space_en:1; + /** extd_color_space : R/W; bitpos: [1]; default: 0; + * Configure extended picture's color space. Valid when JPEG_EXTD_COLOR_SPACE_EN + * configured to 1 + * 0:yuv444 + * 1:yuv420 + */ + uint32_t extd_color_space:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} jpeg_extd_config_reg_t; + +/** Type of t0qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t0_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t0 table + */ + uint32_t t0_qnr_val:32; + }; + uint32_t val; +} jpeg_t0qnr_reg_t; + +/** Type of t1qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t1_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t1 table + */ + uint32_t t1_qnr_val:32; + }; + uint32_t val; +} jpeg_t1qnr_reg_t; + +/** Type of t2qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t2_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t2 table + */ + uint32_t t2_qnr_val:32; + }; + uint32_t val; +} jpeg_t2qnr_reg_t; + +/** Type of t3qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t3_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t3 table + */ + uint32_t t3_qnr_val:32; + }; + uint32_t val; +} jpeg_t3qnr_reg_t; + +/** Type of decode_conf register + * Control and configuration registers + */ +typedef union { + struct { + /** restart_interval : R/W; bitpos: [15:0]; default: 0; + * configure restart interval in DRI marker when decode + */ + uint32_t restart_interval:16; + /** component_num : R/W; bitpos: [23:16]; default: 3; + * configure number of components in frame when decode + */ + uint32_t component_num:8; + /** sw_dht_en : RO; bitpos: [24]; default: 1; + * software decode dht table enable + */ + uint32_t sw_dht_en:1; + /** sos_check_byte_num : R/W; bitpos: [26:25]; default: 3; + * Configure the byte number to check next sos marker in the multi-scan picture after + * one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + */ + uint32_t sos_check_byte_num:2; + /** rst_check_byte_num : R/W; bitpos: [28:27]; default: 3; + * Configure the byte number to check next rst marker after one rst interval is + * decoded down. The real check number is reg_rst_check_byte_num+1 + */ + uint32_t rst_check_byte_num:2; + /** multi_scan_err_check : R/W; bitpos: [29]; default: 0; + * reserved for decoder + */ + uint32_t multi_scan_err_check:1; + /** dezigzag_ready_ctl : R/W; bitpos: [30]; default: 1; + * reserved for decoder + */ + uint32_t dezigzag_ready_ctl:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} jpeg_decode_conf_reg_t; + +/** Type of c0 register + * Control and configuration registers + */ +typedef union { + struct { + /** c0_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c0 quntization table id (TBD) + */ + uint32_t c0_dqt_tbl_sel:8; + /** c0_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c0 + */ + uint32_t c0_y_factor:4; + /** c0_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c0 + */ + uint32_t c0_x_factor:4; + /** c0_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c0 + */ + uint32_t c0_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c0_reg_t; + +/** Type of c1 register + * Control and configuration registers + */ +typedef union { + struct { + /** c1_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c1 quntization table id (TBD) + */ + uint32_t c1_dqt_tbl_sel:8; + /** c1_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c1 + */ + uint32_t c1_y_factor:4; + /** c1_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c1 + */ + uint32_t c1_x_factor:4; + /** c1_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c1 + */ + uint32_t c1_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c1_reg_t; + +/** Type of c2 register + * Control and configuration registers + */ +typedef union { + struct { + /** c2_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c2 quntization table id (TBD) + */ + uint32_t c2_dqt_tbl_sel:8; + /** c2_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c2 + */ + uint32_t c2_y_factor:4; + /** c2_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c2 + */ + uint32_t c2_x_factor:4; + /** c2_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c2 + */ + uint32_t c2_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c2_reg_t; + +/** Type of c3 register + * Control and configuration registers + */ +typedef union { + struct { + /** c3_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c3 quntization table id (TBD) + */ + uint32_t c3_dqt_tbl_sel:8; + /** c3_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c3 + */ + uint32_t c3_y_factor:4; + /** c3_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c3 + */ + uint32_t c3_x_factor:4; + /** c3_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c3 + */ + uint32_t c3_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c3_reg_t; + +/** Type of dht_info register + * Control and configuration registers + */ +typedef union { + struct { + /** dc0_dht_id : R/W; bitpos: [3:0]; default: 0; + * configure dht dc table 0 id + */ + uint32_t dc0_dht_id:4; + /** dc1_dht_id : R/W; bitpos: [7:4]; default: 1; + * configure dht dc table 1 id + */ + uint32_t dc1_dht_id:4; + /** ac0_dht_id : R/W; bitpos: [11:8]; default: 0; + * configure dht ac table 0 id + */ + uint32_t ac0_dht_id:4; + /** ac1_dht_id : R/W; bitpos: [15:12]; default: 1; + * configure dht ac table 1 id + */ + uint32_t ac1_dht_id:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} jpeg_dht_info_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Interrupt raw registers + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + */ + uint32_t done_int_raw:1; + /** rle_parallel_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_raw:1; + /** cid_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit to sign that scan id check with component fails when decoding. + */ + uint32_t cid_err_int_raw:1; + /** c_dht_dc_id_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_raw:1; + /** c_dht_ac_id_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_raw:1; + /** c_dqt_id_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit to sign that scan component's dqt id check with dqt table's + * id fails when decoding. + */ + uint32_t c_dqt_id_err_int_raw:1; + /** rst_uxp_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_raw:1; + /** rst_check_none_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_raw:1; + /** rst_check_pos_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_raw:1; + /** sr_color_mode_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit to sign that the selected source color mode is not supported. + */ + uint32_t sr_color_mode_err_int_raw:1; + /** dct_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_raw:1; + /** bs_last_block_eof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_raw:1; + /** scan_check_none_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit to sign that SOS header marker is not detected but there are + * still components left to be decoded. + */ + uint32_t scan_check_none_err_int_raw:1; + /** scan_check_pos_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit to sign that SOS header marker position wrong when decoding. + */ + uint32_t scan_check_pos_err_int_raw:1; + /** uxp_det_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_raw:1; + /** en_frame_eof_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit to sign that received pixel blocks are smaller than expected + * when encoding. + */ + uint32_t en_frame_eof_err_int_raw:1; + /** en_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit to sign that the frame eof sign bit from dma input is missing + * when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_raw:1; + /** de_frame_eof_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_raw:1; + /** de_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_raw:1; + /** sos_unmatch_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit to sign that the component number of a scan is 0 or does not + * match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_raw:1; + /** marker_err_fst_scan_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_raw:1; + /** marker_err_other_scan_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit to sign that the following scans but not the first scan have + * header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_raw:1; + /** undet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit to sign that JPEG format is not detected at the eof data of a + * packet when decoding. + */ + uint32_t undet_int_raw:1; + /** decode_timeout_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_raw_reg_t; + +/** Type of int_ena register + * Interrupt enable registers + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * This enable interrupt bit turns to high level when JPEG finishes encoding a + * picture.. + */ + uint32_t done_int_ena:1; + /** rle_parallel_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_ena:1; + /** cid_err_int_ena : R/W; bitpos: [2]; default: 0; + * The enable interrupt bit to sign that scan id check with component fails when + * decoding. + */ + uint32_t cid_err_int_ena:1; + /** c_dht_dc_id_err_int_ena : R/W; bitpos: [3]; default: 0; + * The enable interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_ena:1; + /** c_dht_ac_id_err_int_ena : R/W; bitpos: [4]; default: 0; + * The enable interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_ena:1; + /** c_dqt_id_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable interrupt bit to sign that scan component's dqt id check with dqt + * table's id fails when decoding. + */ + uint32_t c_dqt_id_err_int_ena:1; + /** rst_uxp_err_int_ena : R/W; bitpos: [6]; default: 0; + * The enable interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_ena:1; + /** rst_check_none_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_ena:1; + /** rst_check_pos_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_ena:1; + /** out_eof_int_ena : R/W; bitpos: [9]; default: 0; + * The enable interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_ena:1; + /** sr_color_mode_err_int_ena : R/W; bitpos: [10]; default: 0; + * The enable interrupt bit to sign that the selected source color mode is not + * supported. + */ + uint32_t sr_color_mode_err_int_ena:1; + /** dct_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_ena:1; + /** bs_last_block_eof_int_ena : R/W; bitpos: [12]; default: 0; + * The enable interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_ena:1; + /** scan_check_none_err_int_ena : R/W; bitpos: [13]; default: 0; + * The enable interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ + uint32_t scan_check_none_err_int_ena:1; + /** scan_check_pos_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable interrupt bit to sign that SOS header marker position wrong when + * decoding. + */ + uint32_t scan_check_pos_err_int_ena:1; + /** uxp_det_int_ena : R/W; bitpos: [15]; default: 0; + * The enable interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_ena:1; + /** en_frame_eof_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ + uint32_t en_frame_eof_err_int_ena:1; + /** en_frame_eof_lack_int_ena : R/W; bitpos: [17]; default: 0; + * The enable interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_ena:1; + /** de_frame_eof_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_ena:1; + /** de_frame_eof_lack_int_ena : R/W; bitpos: [19]; default: 0; + * The enable interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_ena:1; + /** sos_unmatch_err_int_ena : R/W; bitpos: [20]; default: 0; + * The enable interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_ena:1; + /** marker_err_fst_scan_int_ena : R/W; bitpos: [21]; default: 0; + * The enable interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_ena:1; + /** marker_err_other_scan_int_ena : R/W; bitpos: [22]; default: 0; + * The enable interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_ena:1; + /** undet_int_ena : R/W; bitpos: [23]; default: 0; + * The enable interrupt bit to sign that JPEG format is not detected at the eof data + * of a packet when decoding. + */ + uint32_t undet_int_ena:1; + /** decode_timeout_int_ena : R/W; bitpos: [24]; default: 0; + * The enable interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_ena_reg_t; + +/** Type of int_st register + * Interrupt status registers + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * This status interrupt bit turns to high level when JPEG finishes encoding a + * picture.. + */ + uint32_t done_int_st:1; + /** rle_parallel_err_int_st : RO; bitpos: [1]; default: 0; + * The status interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_st:1; + /** cid_err_int_st : RO; bitpos: [2]; default: 0; + * The status interrupt bit to sign that scan id check with component fails when + * decoding. + */ + uint32_t cid_err_int_st:1; + /** c_dht_dc_id_err_int_st : RO; bitpos: [3]; default: 0; + * The status interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_st:1; + /** c_dht_ac_id_err_int_st : RO; bitpos: [4]; default: 0; + * The status interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_st:1; + /** c_dqt_id_err_int_st : RO; bitpos: [5]; default: 0; + * The status interrupt bit to sign that scan component's dqt id check with dqt + * table's id fails when decoding. + */ + uint32_t c_dqt_id_err_int_st:1; + /** rst_uxp_err_int_st : RO; bitpos: [6]; default: 0; + * The status interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_st:1; + /** rst_check_none_err_int_st : RO; bitpos: [7]; default: 0; + * The status interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_st:1; + /** rst_check_pos_err_int_st : RO; bitpos: [8]; default: 0; + * The status interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_st:1; + /** out_eof_int_st : RO; bitpos: [9]; default: 0; + * The status interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_st:1; + /** sr_color_mode_err_int_st : RO; bitpos: [10]; default: 0; + * The status interrupt bit to sign that the selected source color mode is not + * supported. + */ + uint32_t sr_color_mode_err_int_st:1; + /** dct_done_int_st : RO; bitpos: [11]; default: 0; + * The status interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_st:1; + /** bs_last_block_eof_int_st : RO; bitpos: [12]; default: 0; + * The status interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_st:1; + /** scan_check_none_err_int_st : RO; bitpos: [13]; default: 0; + * The status interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ + uint32_t scan_check_none_err_int_st:1; + /** scan_check_pos_err_int_st : RO; bitpos: [14]; default: 0; + * The status interrupt bit to sign that SOS header marker position wrong when + * decoding. + */ + uint32_t scan_check_pos_err_int_st:1; + /** uxp_det_int_st : RO; bitpos: [15]; default: 0; + * The status interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_st:1; + /** en_frame_eof_err_int_st : RO; bitpos: [16]; default: 0; + * The status interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ + uint32_t en_frame_eof_err_int_st:1; + /** en_frame_eof_lack_int_st : RO; bitpos: [17]; default: 0; + * The status interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_st:1; + /** de_frame_eof_err_int_st : RO; bitpos: [18]; default: 0; + * The status interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_st:1; + /** de_frame_eof_lack_int_st : RO; bitpos: [19]; default: 0; + * The status interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_st:1; + /** sos_unmatch_err_int_st : RO; bitpos: [20]; default: 0; + * The status interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_st:1; + /** marker_err_fst_scan_int_st : RO; bitpos: [21]; default: 0; + * The status interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_st:1; + /** marker_err_other_scan_int_st : RO; bitpos: [22]; default: 0; + * The status interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_st:1; + /** undet_int_st : RO; bitpos: [23]; default: 0; + * The status interrupt bit to sign that JPEG format is not detected at the eof data + * of a packet when decoding. + */ + uint32_t undet_int_st:1; + /** decode_timeout_int_st : RO; bitpos: [24]; default: 0; + * The status interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear registers + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + */ + uint32_t done_int_clr:1; + /** rle_parallel_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_clr:1; + /** cid_err_int_clr : WT; bitpos: [2]; default: 0; + * The clear interrupt bit to sign that scan id check with component fails when + * decoding. + */ + uint32_t cid_err_int_clr:1; + /** c_dht_dc_id_err_int_clr : WT; bitpos: [3]; default: 0; + * The clear interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_clr:1; + /** c_dht_ac_id_err_int_clr : WT; bitpos: [4]; default: 0; + * The clear interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_clr:1; + /** c_dqt_id_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear interrupt bit to sign that scan component's dqt id check with dqt table's + * id fails when decoding. + */ + uint32_t c_dqt_id_err_int_clr:1; + /** rst_uxp_err_int_clr : WT; bitpos: [6]; default: 0; + * The clear interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_clr:1; + /** rst_check_none_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_clr:1; + /** rst_check_pos_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_clr:1; + /** out_eof_int_clr : WT; bitpos: [9]; default: 0; + * The clear interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_clr:1; + /** sr_color_mode_err_int_clr : WT; bitpos: [10]; default: 0; + * The clear interrupt bit to sign that the selected source color mode is not + * supported. + */ + uint32_t sr_color_mode_err_int_clr:1; + /** dct_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_clr:1; + /** bs_last_block_eof_int_clr : WT; bitpos: [12]; default: 0; + * The clear interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_clr:1; + /** scan_check_none_err_int_clr : WT; bitpos: [13]; default: 0; + * The clear interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ + uint32_t scan_check_none_err_int_clr:1; + /** scan_check_pos_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear interrupt bit to sign that SOS header marker position wrong when decoding. + */ + uint32_t scan_check_pos_err_int_clr:1; + /** uxp_det_int_clr : WT; bitpos: [15]; default: 0; + * The clear interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_clr:1; + /** en_frame_eof_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ + uint32_t en_frame_eof_err_int_clr:1; + /** en_frame_eof_lack_int_clr : WT; bitpos: [17]; default: 0; + * The clear interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_clr:1; + /** de_frame_eof_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_clr:1; + /** de_frame_eof_lack_int_clr : WT; bitpos: [19]; default: 0; + * The clear interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_clr:1; + /** sos_unmatch_err_int_clr : WT; bitpos: [20]; default: 0; + * The clear interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_clr:1; + /** marker_err_fst_scan_int_clr : WT; bitpos: [21]; default: 0; + * The clear interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_clr:1; + /** marker_err_other_scan_int_clr : WT; bitpos: [22]; default: 0; + * The clear interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_clr:1; + /** undet_int_clr : WT; bitpos: [23]; default: 0; + * The clear interrupt bit to sign that JPEG format is not detected at the eof data of + * a packet when decoding. + */ + uint32_t undet_int_clr:1; + /** decode_timeout_int_clr : WT; bitpos: [24]; default: 0; + * The clear interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_clr_reg_t; + + +/** Group: Trace and Debug registers */ +/** Type of status0 register + * Trace and Debug registers + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** bitstream_eof_vld_cnt : RO; bitpos: [16:11]; default: 0; + * the valid bit count for last bitstream + */ + uint32_t bitstream_eof_vld_cnt:6; + /** dctout_zzscan_addr : RO; bitpos: [22:17]; default: 0; + * the zig-zag read addr from dctout_ram + */ + uint32_t dctout_zzscan_addr:6; + /** qnrval_zzscan_addr : RO; bitpos: [28:23]; default: 0; + * the zig-zag read addr from qnrval_ram + */ + uint32_t qnrval_zzscan_addr:6; + /** reg_state_yuv : RO; bitpos: [31:29]; default: 0; + * the state of jpeg fsm + */ + uint32_t reg_state_yuv:3; + }; + uint32_t val; +} jpeg_status0_reg_t; + +/** Type of status2 register + * Trace and Debug registers + */ +typedef union { + struct { + /** source_pixel : RO; bitpos: [23:0]; default: 0; + * source pixels fetched from dma + */ + uint32_t source_pixel:24; + /** last_block : RO; bitpos: [24]; default: 0; + * indicate the encoding process for the last mcu of the picture + */ + uint32_t last_block:1; + /** last_mcu : RO; bitpos: [25]; default: 0; + * indicate the encoding process for the last block of the picture + */ + uint32_t last_mcu:1; + /** last_dc : RO; bitpos: [26]; default: 0; + * indicate the encoding process is at the header of the last block of the picture + */ + uint32_t last_dc:1; + /** packfifo_ready : RO; bitpos: [27]; default: 1; + * the jpeg pack_fifo ready signal, high active + */ + uint32_t packfifo_ready:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} jpeg_status2_reg_t; + +/** Type of status3 register + * Trace and Debug registers + */ +typedef union { + struct { + /** yo : RO; bitpos: [8:0]; default: 0; + * component y transferred from rgb input + */ + uint32_t yo:9; + /** y_ready : RO; bitpos: [9]; default: 0; + * component y valid signal, high active + */ + uint32_t y_ready:1; + /** cbo : RO; bitpos: [18:10]; default: 0; + * component cb transferred from rgb input + */ + uint32_t cbo:9; + /** cb_ready : RO; bitpos: [19]; default: 0; + * component cb valid signal, high active + */ + uint32_t cb_ready:1; + /** cro : RO; bitpos: [28:20]; default: 0; + * component cr transferred from rgb input + */ + uint32_t cro:9; + /** cr_ready : RO; bitpos: [29]; default: 0; + * component cr valid signal, high active + */ + uint32_t cr_ready:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} jpeg_status3_reg_t; + +/** Type of status4 register + * Trace and Debug registers + */ +typedef union { + struct { + /** hfm_bitstream : RO; bitpos: [31:0]; default: 0; + * the hufman bitstream during encoding process + */ + uint32_t hfm_bitstream:32; + }; + uint32_t val; +} jpeg_status4_reg_t; + +/** Type of dht_totlen_dc0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_dc0 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of dc0 table + */ + uint32_t dht_totlen_dc0:32; + }; + uint32_t val; +} jpeg_dht_totlen_dc0_reg_t; + +/** Type of dht_val_dc0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_dc0 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of dc0 table + */ + uint32_t dht_val_dc0:32; + }; + uint32_t val; +} jpeg_dht_val_dc0_reg_t; + +/** Type of dht_totlen_ac0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_ac0 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of ac0 table + */ + uint32_t dht_totlen_ac0:32; + }; + uint32_t val; +} jpeg_dht_totlen_ac0_reg_t; + +/** Type of dht_val_ac0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_ac0 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of ac0 table + */ + uint32_t dht_val_ac0:32; + }; + uint32_t val; +} jpeg_dht_val_ac0_reg_t; + +/** Type of dht_totlen_dc1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_dc1 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of dc1 table + */ + uint32_t dht_totlen_dc1:32; + }; + uint32_t val; +} jpeg_dht_totlen_dc1_reg_t; + +/** Type of dht_val_dc1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_dc1 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of dc1 table + */ + uint32_t dht_val_dc1:32; + }; + uint32_t val; +} jpeg_dht_val_dc1_reg_t; + +/** Type of dht_totlen_ac1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_ac1 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of ac1 table + */ + uint32_t dht_totlen_ac1:32; + }; + uint32_t val; +} jpeg_dht_totlen_ac1_reg_t; + +/** Type of dht_val_ac1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_ac1 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of ac1 table + */ + uint32_t dht_val_ac1:32; + }; + uint32_t val; +} jpeg_dht_val_ac1_reg_t; + +/** Type of dht_codemin_dc0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_dc0 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of dc0 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_dc0:32; + }; + uint32_t val; +} jpeg_dht_codemin_dc0_reg_t; + +/** Type of dht_codemin_ac0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_ac0 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of ac0 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_ac0:32; + }; + uint32_t val; +} jpeg_dht_codemin_ac0_reg_t; + +/** Type of dht_codemin_dc1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_dc1 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of dc1 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_dc1:32; + }; + uint32_t val; +} jpeg_dht_codemin_dc1_reg_t; + +/** Type of dht_codemin_ac1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_ac1 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of ac1 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_ac1:32; + }; + uint32_t val; +} jpeg_dht_codemin_ac1_reg_t; + +/** Type of decoder_status0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** decode_byte_cnt : RO; bitpos: [25:0]; default: 0; + * Reserved + */ + uint32_t decode_byte_cnt:26; + /** header_dec_st : RO; bitpos: [29:26]; default: 0; + * Reserved + */ + uint32_t header_dec_st:4; + /** decode_sample_sel : RO; bitpos: [31:30]; default: 0; + * Reserved + */ + uint32_t decode_sample_sel:2; + }; + uint32_t val; +} jpeg_decoder_status0_reg_t; + +/** Type of decoder_status1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** encode_data : RO; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t encode_data:16; + /** count_q : RO; bitpos: [22:16]; default: 0; + * Reserved + */ + uint32_t count_q:7; + /** mcu_fsm_ready : RO; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t mcu_fsm_ready:1; + /** decode_data : RO; bitpos: [31:24]; default: 0; + * Reserved + */ + uint32_t decode_data:8; + }; + uint32_t val; +} jpeg_decoder_status1_reg_t; + +/** Type of decoder_status2 register + * Trace and Debug registers + */ +typedef union { + struct { + /** comp_block_num : RO; bitpos: [25:0]; default: 0; + * Reserved + */ + uint32_t comp_block_num:26; + /** scan_num : RO; bitpos: [28:26]; default: 0; + * Reserved + */ + uint32_t scan_num:3; + /** rst_check_wait : RO; bitpos: [29]; default: 0; + * Reserved + */ + uint32_t rst_check_wait:1; + /** scan_check_wait : RO; bitpos: [30]; default: 0; + * Reserved + */ + uint32_t scan_check_wait:1; + /** mcu_in_proc : RO; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t mcu_in_proc:1; + }; + uint32_t val; +} jpeg_decoder_status2_reg_t; + +/** Type of decoder_status3 register + * Trace and Debug registers + */ +typedef union { + struct { + /** lookup_data : RO; bitpos: [31:0]; default: 0; + * Reserved + */ + uint32_t lookup_data:32; + }; + uint32_t val; +} jpeg_decoder_status3_reg_t; + +/** Type of decoder_status4 register + * Trace and Debug registers + */ +typedef union { + struct { + /** block_eof_cnt : RO; bitpos: [25:0]; default: 0; + * Reserved + */ + uint32_t block_eof_cnt:26; + /** dezigzag_ready : RO; bitpos: [26]; default: 0; + * Reserved + */ + uint32_t dezigzag_ready:1; + /** de_frame_eof_check : RO; bitpos: [27]; default: 0; + * Reserved + */ + uint32_t de_frame_eof_check:1; + /** de_dma2d_in_push : RO; bitpos: [28]; default: 0; + * Reserved + */ + uint32_t de_dma2d_in_push:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} jpeg_decoder_status4_reg_t; + +/** Type of decoder_status5 register + * Trace and Debug registers + */ +typedef union { + struct { + /** idct_hfm_data : RO; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t idct_hfm_data:16; + /** ns0 : RO; bitpos: [18:16]; default: 0; + * Reserved + */ + uint32_t ns0:3; + /** ns1 : RO; bitpos: [21:19]; default: 0; + * Reserved + */ + uint32_t ns1:3; + /** ns2 : RO; bitpos: [24:22]; default: 0; + * Reserved + */ + uint32_t ns2:3; + /** ns3 : RO; bitpos: [27:25]; default: 0; + * Reserved + */ + uint32_t ns3:3; + /** data_last_o : RO; bitpos: [28]; default: 0; + * Reserved + */ + uint32_t data_last_o:1; + /** rdn_result : RO; bitpos: [29]; default: 0; + * redundant registers for jpeg + */ + uint32_t rdn_result:1; + /** rdn_ena : R/W; bitpos: [30]; default: 0; + * redundant control registers for jpeg + */ + uint32_t rdn_ena:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} jpeg_decoder_status5_reg_t; + +/** Type of status5 register + * Trace and Debug registers + */ +typedef union { + struct { + /** pic_block_num : RO; bitpos: [23:0]; default: 0; + * Reserved + */ + uint32_t pic_block_num:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_status5_reg_t; + +/** Type of eco_low register + * Trace and Debug registers + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * redundant registers for jpeg + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} jpeg_eco_low_reg_t; + +/** Type of eco_high register + * Trace and Debug registers + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * redundant registers for jpeg + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} jpeg_eco_high_reg_t; + +/** Type of sys register + * Trace and Debug registers + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + }; + uint32_t val; +} jpeg_sys_reg_t; + +/** Type of version register + * Trace and Debug registers + */ +typedef union { + struct { + /** jpeg_ver : R/W; bitpos: [27:0]; default: 37823072; + * Reserved + */ + uint32_t jpeg_ver:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} jpeg_version_reg_t; + + +typedef struct { + volatile jpeg_config_reg_t config; + volatile jpeg_dqt_info_reg_t dqt_info; + volatile jpeg_pic_size_reg_t pic_size; + volatile jpeg_extd_config_reg_t extd_config; + volatile jpeg_t0qnr_reg_t t0qnr; + volatile jpeg_t1qnr_reg_t t1qnr; + volatile jpeg_t2qnr_reg_t t2qnr; + volatile jpeg_t3qnr_reg_t t3qnr; + volatile jpeg_decode_conf_reg_t decode_conf; + volatile jpeg_c0_reg_t c0; + volatile jpeg_c1_reg_t c1; + volatile jpeg_c2_reg_t c2; + volatile jpeg_c3_reg_t c3; + volatile jpeg_dht_info_reg_t dht_info; + volatile jpeg_int_raw_reg_t int_raw; + volatile jpeg_int_ena_reg_t int_ena; + volatile jpeg_int_st_reg_t int_st; + volatile jpeg_int_clr_reg_t int_clr; + volatile jpeg_status0_reg_t status0; + volatile jpeg_status2_reg_t status2; + volatile jpeg_status3_reg_t status3; + volatile jpeg_status4_reg_t status4; + volatile jpeg_dht_totlen_dc0_reg_t dht_totlen_dc0; + volatile jpeg_dht_val_dc0_reg_t dht_val_dc0; + volatile jpeg_dht_totlen_ac0_reg_t dht_totlen_ac0; + volatile jpeg_dht_val_ac0_reg_t dht_val_ac0; + volatile jpeg_dht_totlen_dc1_reg_t dht_totlen_dc1; + volatile jpeg_dht_val_dc1_reg_t dht_val_dc1; + volatile jpeg_dht_totlen_ac1_reg_t dht_totlen_ac1; + volatile jpeg_dht_val_ac1_reg_t dht_val_ac1; + volatile jpeg_dht_codemin_dc0_reg_t dht_codemin_dc0; + volatile jpeg_dht_codemin_ac0_reg_t dht_codemin_ac0; + volatile jpeg_dht_codemin_dc1_reg_t dht_codemin_dc1; + volatile jpeg_dht_codemin_ac1_reg_t dht_codemin_ac1; + volatile jpeg_decoder_status0_reg_t decoder_status0; + volatile jpeg_decoder_status1_reg_t decoder_status1; + volatile jpeg_decoder_status2_reg_t decoder_status2; + volatile jpeg_decoder_status3_reg_t decoder_status3; + volatile jpeg_decoder_status4_reg_t decoder_status4; + volatile jpeg_decoder_status5_reg_t decoder_status5; + volatile jpeg_status5_reg_t status5; + volatile jpeg_eco_low_reg_t eco_low; + volatile jpeg_eco_high_reg_t eco_high; + uint32_t reserved_0ac[19]; + volatile jpeg_sys_reg_t sys; + volatile jpeg_version_reg_t version; +} jpeg_dev_t; + +extern jpeg_dev_t JPEG; + +#ifndef __cplusplus +_Static_assert(sizeof(jpeg_dev_t) == 0x100, "Invalid size of jpeg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/jpeg_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/jpeg_reg.h new file mode 100644 index 0000000000..17e1f4bee7 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/jpeg_reg.h @@ -0,0 +1,1884 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** JPEG_CONFIG_REG register + * Control and configuration registers + */ +#define JPEG_CONFIG_REG (DR_REG_JPEG_BASE + 0x0) +/** JPEG_FSM_RST : WT; bitpos: [0]; default: 0; + * fsm reset + */ +#define JPEG_FSM_RST (BIT(0)) +#define JPEG_FSM_RST_M (JPEG_FSM_RST_V << JPEG_FSM_RST_S) +#define JPEG_FSM_RST_V 0x00000001U +#define JPEG_FSM_RST_S 0 +/** JPEG_JPEG_START : WT; bitpos: [1]; default: 0; + * start to compress a new pic(in dma reg mode) + */ +#define JPEG_JPEG_START (BIT(1)) +#define JPEG_JPEG_START_M (JPEG_JPEG_START_V << JPEG_JPEG_START_S) +#define JPEG_JPEG_START_V 0x00000001U +#define JPEG_JPEG_START_S 1 +/** JPEG_QNR_PRECISION : R/W; bitpos: [2]; default: 0; + * 0:8bit qnr,1:12bit qnr(TBD) + */ +#define JPEG_QNR_PRECISION (BIT(2)) +#define JPEG_QNR_PRECISION_M (JPEG_QNR_PRECISION_V << JPEG_QNR_PRECISION_S) +#define JPEG_QNR_PRECISION_V 0x00000001U +#define JPEG_QNR_PRECISION_S 2 +/** JPEG_FF_CHECK_EN : R/W; bitpos: [3]; default: 1; + * enable whether to add '00' after 'ff' + */ +#define JPEG_FF_CHECK_EN (BIT(3)) +#define JPEG_FF_CHECK_EN_M (JPEG_FF_CHECK_EN_V << JPEG_FF_CHECK_EN_S) +#define JPEG_FF_CHECK_EN_V 0x00000001U +#define JPEG_FF_CHECK_EN_S 3 +/** JPEG_SAMPLE_SEL : R/W; bitpos: [5:4]; default: 1; + * 0:yuv444,1:yuv422, 2:yuv420 + */ +#define JPEG_SAMPLE_SEL 0x00000003U +#define JPEG_SAMPLE_SEL_M (JPEG_SAMPLE_SEL_V << JPEG_SAMPLE_SEL_S) +#define JPEG_SAMPLE_SEL_V 0x00000003U +#define JPEG_SAMPLE_SEL_S 4 +/** JPEG_DMA_LINKLIST_MODE : RO; bitpos: [6]; default: 1; + * 1:use linklist to configure dma + */ +#define JPEG_DMA_LINKLIST_MODE (BIT(6)) +#define JPEG_DMA_LINKLIST_MODE_M (JPEG_DMA_LINKLIST_MODE_V << JPEG_DMA_LINKLIST_MODE_S) +#define JPEG_DMA_LINKLIST_MODE_V 0x00000001U +#define JPEG_DMA_LINKLIST_MODE_S 6 +/** JPEG_DEBUG_DIRECT_OUT_EN : R/W; bitpos: [7]; default: 0; + * 0:normal mode,1:debug mode for direct output from input + */ +#define JPEG_DEBUG_DIRECT_OUT_EN (BIT(7)) +#define JPEG_DEBUG_DIRECT_OUT_EN_M (JPEG_DEBUG_DIRECT_OUT_EN_V << JPEG_DEBUG_DIRECT_OUT_EN_S) +#define JPEG_DEBUG_DIRECT_OUT_EN_V 0x00000001U +#define JPEG_DEBUG_DIRECT_OUT_EN_S 7 +/** JPEG_QNR_FIFO_EN : R/W; bitpos: [8]; default: 1; + * 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram + */ +#define JPEG_QNR_FIFO_EN (BIT(8)) +#define JPEG_QNR_FIFO_EN_M (JPEG_QNR_FIFO_EN_V << JPEG_QNR_FIFO_EN_S) +#define JPEG_QNR_FIFO_EN_V 0x00000001U +#define JPEG_QNR_FIFO_EN_S 8 +/** JPEG_LQNR_TBL_SEL : R/W; bitpos: [10:9]; default: 0; + * choose luminance quntization table id(TBD) + */ +#define JPEG_LQNR_TBL_SEL 0x00000003U +#define JPEG_LQNR_TBL_SEL_M (JPEG_LQNR_TBL_SEL_V << JPEG_LQNR_TBL_SEL_S) +#define JPEG_LQNR_TBL_SEL_V 0x00000003U +#define JPEG_LQNR_TBL_SEL_S 9 +/** JPEG_CQNR_TBL_SEL : R/W; bitpos: [12:11]; default: 1; + * choose chrominance quntization table id (TBD) + */ +#define JPEG_CQNR_TBL_SEL 0x00000003U +#define JPEG_CQNR_TBL_SEL_M (JPEG_CQNR_TBL_SEL_V << JPEG_CQNR_TBL_SEL_S) +#define JPEG_CQNR_TBL_SEL_V 0x00000003U +#define JPEG_CQNR_TBL_SEL_S 11 +/** JPEG_COLOR_SPACE : R/W; bitpos: [14:13]; default: 0; + * configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray + */ +#define JPEG_COLOR_SPACE 0x00000003U +#define JPEG_COLOR_SPACE_M (JPEG_COLOR_SPACE_V << JPEG_COLOR_SPACE_S) +#define JPEG_COLOR_SPACE_V 0x00000003U +#define JPEG_COLOR_SPACE_S 13 +/** JPEG_DHT_FIFO_EN : R/W; bitpos: [15]; default: 1; + * 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to + * write dht len_total/codemin/value table. Reading dht len_total/codemin/value table + * only has nonfifo way + */ +#define JPEG_DHT_FIFO_EN (BIT(15)) +#define JPEG_DHT_FIFO_EN_M (JPEG_DHT_FIFO_EN_V << JPEG_DHT_FIFO_EN_S) +#define JPEG_DHT_FIFO_EN_V 0x00000001U +#define JPEG_DHT_FIFO_EN_S 15 +/** JPEG_MEM_CLK_FORCE_ON : R/W; bitpos: [16]; default: 0; + * force memory's clock enabled + */ +#define JPEG_MEM_CLK_FORCE_ON (BIT(16)) +#define JPEG_MEM_CLK_FORCE_ON_M (JPEG_MEM_CLK_FORCE_ON_V << JPEG_MEM_CLK_FORCE_ON_S) +#define JPEG_MEM_CLK_FORCE_ON_V 0x00000001U +#define JPEG_MEM_CLK_FORCE_ON_S 16 +/** JPEG_DECODE_TIMEOUT_THRES : R/W; bitpos: [22:17]; default: 32; + * decode pause period to trigger decode_timeout int, the timeout periods =2 power + * (reg_decode_timeout_thres) -1 + */ +#define JPEG_DECODE_TIMEOUT_THRES 0x0000003FU +#define JPEG_DECODE_TIMEOUT_THRES_M (JPEG_DECODE_TIMEOUT_THRES_V << JPEG_DECODE_TIMEOUT_THRES_S) +#define JPEG_DECODE_TIMEOUT_THRES_V 0x0000003FU +#define JPEG_DECODE_TIMEOUT_THRES_S 17 +/** JPEG_DECODE_TIMEOUT_TASK_SEL : R/W; bitpos: [23]; default: 0; + * 0: software use reset to abort decode process ,1: decoder abort decode process by + * itself + */ +#define JPEG_DECODE_TIMEOUT_TASK_SEL (BIT(23)) +#define JPEG_DECODE_TIMEOUT_TASK_SEL_M (JPEG_DECODE_TIMEOUT_TASK_SEL_V << JPEG_DECODE_TIMEOUT_TASK_SEL_S) +#define JPEG_DECODE_TIMEOUT_TASK_SEL_V 0x00000001U +#define JPEG_DECODE_TIMEOUT_TASK_SEL_S 23 +/** JPEG_SOFT_RST : R/W; bitpos: [24]; default: 0; + * when set to 1, soft reset JPEG module except jpeg_reg module + */ +#define JPEG_SOFT_RST (BIT(24)) +#define JPEG_SOFT_RST_M (JPEG_SOFT_RST_V << JPEG_SOFT_RST_S) +#define JPEG_SOFT_RST_V 0x00000001U +#define JPEG_SOFT_RST_S 24 +/** JPEG_FIFO_RST : R/W; bitpos: [25]; default: 0; + * fifo reset + */ +#define JPEG_FIFO_RST (BIT(25)) +#define JPEG_FIFO_RST_M (JPEG_FIFO_RST_V << JPEG_FIFO_RST_S) +#define JPEG_FIFO_RST_V 0x00000001U +#define JPEG_FIFO_RST_S 25 +/** JPEG_PIXEL_REV : R/W; bitpos: [26]; default: 0; + * reverse the source color pixel + */ +#define JPEG_PIXEL_REV (BIT(26)) +#define JPEG_PIXEL_REV_M (JPEG_PIXEL_REV_V << JPEG_PIXEL_REV_S) +#define JPEG_PIXEL_REV_V 0x00000001U +#define JPEG_PIXEL_REV_S 26 +/** JPEG_TAILER_EN : R/W; bitpos: [27]; default: 0; + * set this bit to add EOI of '0xffd9' at the end of bitstream + */ +#define JPEG_TAILER_EN (BIT(27)) +#define JPEG_TAILER_EN_M (JPEG_TAILER_EN_V << JPEG_TAILER_EN_S) +#define JPEG_TAILER_EN_V 0x00000001U +#define JPEG_TAILER_EN_S 27 +/** JPEG_PAUSE_EN : R/W; bitpos: [28]; default: 0; + * set this bit to pause jpeg encoding + */ +#define JPEG_PAUSE_EN (BIT(28)) +#define JPEG_PAUSE_EN_M (JPEG_PAUSE_EN_V << JPEG_PAUSE_EN_S) +#define JPEG_PAUSE_EN_V 0x00000001U +#define JPEG_PAUSE_EN_S 28 +/** JPEG_MEM_FORCE_PD : R/W; bitpos: [29]; default: 0; + * 0: no operation,1:force jpeg memory to power down + */ +#define JPEG_MEM_FORCE_PD (BIT(29)) +#define JPEG_MEM_FORCE_PD_M (JPEG_MEM_FORCE_PD_V << JPEG_MEM_FORCE_PD_S) +#define JPEG_MEM_FORCE_PD_V 0x00000001U +#define JPEG_MEM_FORCE_PD_S 29 +/** JPEG_MEM_FORCE_PU : R/W; bitpos: [30]; default: 0; + * 0: no operation,1:force jpeg memory to power up + */ +#define JPEG_MEM_FORCE_PU (BIT(30)) +#define JPEG_MEM_FORCE_PU_M (JPEG_MEM_FORCE_PU_V << JPEG_MEM_FORCE_PU_S) +#define JPEG_MEM_FORCE_PU_V 0x00000001U +#define JPEG_MEM_FORCE_PU_S 30 +/** JPEG_MODE : R/W; bitpos: [31]; default: 0; + * 0:encoder mode, 1: decoder mode + */ +#define JPEG_MODE (BIT(31)) +#define JPEG_MODE_M (JPEG_MODE_V << JPEG_MODE_S) +#define JPEG_MODE_V 0x00000001U +#define JPEG_MODE_S 31 + +/** JPEG_DQT_INFO_REG register + * Control and configuration registers + */ +#define JPEG_DQT_INFO_REG (DR_REG_JPEG_BASE + 0x4) +/** JPEG_T0_DQT_INFO : R/W; bitpos: [7:0]; default: 0; + * Configure dqt table0's quantization coefficient precision in bit[7:4], configure + * dqt table0's table id in bit[3:0] + */ +#define JPEG_T0_DQT_INFO 0x000000FFU +#define JPEG_T0_DQT_INFO_M (JPEG_T0_DQT_INFO_V << JPEG_T0_DQT_INFO_S) +#define JPEG_T0_DQT_INFO_V 0x000000FFU +#define JPEG_T0_DQT_INFO_S 0 +/** JPEG_T1_DQT_INFO : R/W; bitpos: [15:8]; default: 1; + * Configure dqt table1's quantization coefficient precision in bit[7:4], configure + * dqt table1's table id in bit[3:0] + */ +#define JPEG_T1_DQT_INFO 0x000000FFU +#define JPEG_T1_DQT_INFO_M (JPEG_T1_DQT_INFO_V << JPEG_T1_DQT_INFO_S) +#define JPEG_T1_DQT_INFO_V 0x000000FFU +#define JPEG_T1_DQT_INFO_S 8 +/** JPEG_T2_DQT_INFO : R/W; bitpos: [23:16]; default: 2; + * Configure dqt table2's quantization coefficient precision in bit[7:4], configure + * dqt table2's table id in bit[3:0] + */ +#define JPEG_T2_DQT_INFO 0x000000FFU +#define JPEG_T2_DQT_INFO_M (JPEG_T2_DQT_INFO_V << JPEG_T2_DQT_INFO_S) +#define JPEG_T2_DQT_INFO_V 0x000000FFU +#define JPEG_T2_DQT_INFO_S 16 +/** JPEG_T3_DQT_INFO : R/W; bitpos: [31:24]; default: 3; + * Configure dqt table3's quantization coefficient precision in bit[7:4], configure + * dqt table3's table id in bit[3:0] + */ +#define JPEG_T3_DQT_INFO 0x000000FFU +#define JPEG_T3_DQT_INFO_M (JPEG_T3_DQT_INFO_V << JPEG_T3_DQT_INFO_S) +#define JPEG_T3_DQT_INFO_V 0x000000FFU +#define JPEG_T3_DQT_INFO_S 24 + +/** JPEG_PIC_SIZE_REG register + * Control and configuration registers + */ +#define JPEG_PIC_SIZE_REG (DR_REG_JPEG_BASE + 0x8) +/** JPEG_VA : R/W; bitpos: [15:0]; default: 480; + * configure picture's height. when encode, the max configurable bits is 14, when + * decode, the max configurable bits is 16 + */ +#define JPEG_VA 0x0000FFFFU +#define JPEG_VA_M (JPEG_VA_V << JPEG_VA_S) +#define JPEG_VA_V 0x0000FFFFU +#define JPEG_VA_S 0 +/** JPEG_HA : R/W; bitpos: [31:16]; default: 640; + * configure picture's width. when encode, the max configurable bits is 14, when + * decode, the max configurable bits is 16 + */ +#define JPEG_HA 0x0000FFFFU +#define JPEG_HA_M (JPEG_HA_V << JPEG_HA_S) +#define JPEG_HA_V 0x0000FFFFU +#define JPEG_HA_S 16 + +/** JPEG_EXTD_CONFIG_REG register + * Control and configuration registers + */ +#define JPEG_EXTD_CONFIG_REG (DR_REG_JPEG_BASE + 0xc) +/** JPEG_EXTD_COLOR_SPACE_EN : R/W; bitpos: [0]; default: 0; + * Configure whether to extend picture's color space + * 0:disable + * 1:enable + */ +#define JPEG_EXTD_COLOR_SPACE_EN (BIT(0)) +#define JPEG_EXTD_COLOR_SPACE_EN_M (JPEG_EXTD_COLOR_SPACE_EN_V << JPEG_EXTD_COLOR_SPACE_EN_S) +#define JPEG_EXTD_COLOR_SPACE_EN_V 0x00000001U +#define JPEG_EXTD_COLOR_SPACE_EN_S 0 +/** JPEG_EXTD_COLOR_SPACE : R/W; bitpos: [1]; default: 0; + * Configure extended picture's color space. Valid when JPEG_EXTD_COLOR_SPACE_EN + * configured to 1 + * 0:yuv444 + * 1:yuv420 + */ +#define JPEG_EXTD_COLOR_SPACE (BIT(1)) +#define JPEG_EXTD_COLOR_SPACE_M (JPEG_EXTD_COLOR_SPACE_V << JPEG_EXTD_COLOR_SPACE_S) +#define JPEG_EXTD_COLOR_SPACE_V 0x00000001U +#define JPEG_EXTD_COLOR_SPACE_S 1 + +/** JPEG_T0QNR_REG register + * Control and configuration registers + */ +#define JPEG_T0QNR_REG (DR_REG_JPEG_BASE + 0x10) +/** JPEG_T0_QNR_VAL : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t0 table + */ +#define JPEG_T0_QNR_VAL 0xFFFFFFFFU +#define JPEG_T0_QNR_VAL_M (JPEG_T0_QNR_VAL_V << JPEG_T0_QNR_VAL_S) +#define JPEG_T0_QNR_VAL_V 0xFFFFFFFFU +#define JPEG_T0_QNR_VAL_S 0 + +/** JPEG_T1QNR_REG register + * Control and configuration registers + */ +#define JPEG_T1QNR_REG (DR_REG_JPEG_BASE + 0x14) +/** JPEG_T1_QNR_VAL : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t1 table + */ +#define JPEG_T1_QNR_VAL 0xFFFFFFFFU +#define JPEG_T1_QNR_VAL_M (JPEG_T1_QNR_VAL_V << JPEG_T1_QNR_VAL_S) +#define JPEG_T1_QNR_VAL_V 0xFFFFFFFFU +#define JPEG_T1_QNR_VAL_S 0 + +/** JPEG_T2QNR_REG register + * Control and configuration registers + */ +#define JPEG_T2QNR_REG (DR_REG_JPEG_BASE + 0x18) +/** JPEG_T2_QNR_VAL : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t2 table + */ +#define JPEG_T2_QNR_VAL 0xFFFFFFFFU +#define JPEG_T2_QNR_VAL_M (JPEG_T2_QNR_VAL_V << JPEG_T2_QNR_VAL_S) +#define JPEG_T2_QNR_VAL_V 0xFFFFFFFFU +#define JPEG_T2_QNR_VAL_S 0 + +/** JPEG_T3QNR_REG register + * Control and configuration registers + */ +#define JPEG_T3QNR_REG (DR_REG_JPEG_BASE + 0x1c) +/** JPEG_T3_QNR_VAL : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t3 table + */ +#define JPEG_T3_QNR_VAL 0xFFFFFFFFU +#define JPEG_T3_QNR_VAL_M (JPEG_T3_QNR_VAL_V << JPEG_T3_QNR_VAL_S) +#define JPEG_T3_QNR_VAL_V 0xFFFFFFFFU +#define JPEG_T3_QNR_VAL_S 0 + +/** JPEG_DECODE_CONF_REG register + * Control and configuration registers + */ +#define JPEG_DECODE_CONF_REG (DR_REG_JPEG_BASE + 0x20) +/** JPEG_RESTART_INTERVAL : R/W; bitpos: [15:0]; default: 0; + * configure restart interval in DRI marker when decode + */ +#define JPEG_RESTART_INTERVAL 0x0000FFFFU +#define JPEG_RESTART_INTERVAL_M (JPEG_RESTART_INTERVAL_V << JPEG_RESTART_INTERVAL_S) +#define JPEG_RESTART_INTERVAL_V 0x0000FFFFU +#define JPEG_RESTART_INTERVAL_S 0 +/** JPEG_COMPONENT_NUM : R/W; bitpos: [23:16]; default: 3; + * configure number of components in frame when decode + */ +#define JPEG_COMPONENT_NUM 0x000000FFU +#define JPEG_COMPONENT_NUM_M (JPEG_COMPONENT_NUM_V << JPEG_COMPONENT_NUM_S) +#define JPEG_COMPONENT_NUM_V 0x000000FFU +#define JPEG_COMPONENT_NUM_S 16 +/** JPEG_SW_DHT_EN : RO; bitpos: [24]; default: 1; + * software decode dht table enable + */ +#define JPEG_SW_DHT_EN (BIT(24)) +#define JPEG_SW_DHT_EN_M (JPEG_SW_DHT_EN_V << JPEG_SW_DHT_EN_S) +#define JPEG_SW_DHT_EN_V 0x00000001U +#define JPEG_SW_DHT_EN_S 24 +/** JPEG_SOS_CHECK_BYTE_NUM : R/W; bitpos: [26:25]; default: 3; + * Configure the byte number to check next sos marker in the multi-scan picture after + * one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + */ +#define JPEG_SOS_CHECK_BYTE_NUM 0x00000003U +#define JPEG_SOS_CHECK_BYTE_NUM_M (JPEG_SOS_CHECK_BYTE_NUM_V << JPEG_SOS_CHECK_BYTE_NUM_S) +#define JPEG_SOS_CHECK_BYTE_NUM_V 0x00000003U +#define JPEG_SOS_CHECK_BYTE_NUM_S 25 +/** JPEG_RST_CHECK_BYTE_NUM : R/W; bitpos: [28:27]; default: 3; + * Configure the byte number to check next rst marker after one rst interval is + * decoded down. The real check number is reg_rst_check_byte_num+1 + */ +#define JPEG_RST_CHECK_BYTE_NUM 0x00000003U +#define JPEG_RST_CHECK_BYTE_NUM_M (JPEG_RST_CHECK_BYTE_NUM_V << JPEG_RST_CHECK_BYTE_NUM_S) +#define JPEG_RST_CHECK_BYTE_NUM_V 0x00000003U +#define JPEG_RST_CHECK_BYTE_NUM_S 27 +/** JPEG_MULTI_SCAN_ERR_CHECK : R/W; bitpos: [29]; default: 0; + * reserved for decoder + */ +#define JPEG_MULTI_SCAN_ERR_CHECK (BIT(29)) +#define JPEG_MULTI_SCAN_ERR_CHECK_M (JPEG_MULTI_SCAN_ERR_CHECK_V << JPEG_MULTI_SCAN_ERR_CHECK_S) +#define JPEG_MULTI_SCAN_ERR_CHECK_V 0x00000001U +#define JPEG_MULTI_SCAN_ERR_CHECK_S 29 +/** JPEG_DEZIGZAG_READY_CTL : R/W; bitpos: [30]; default: 1; + * reserved for decoder + */ +#define JPEG_DEZIGZAG_READY_CTL (BIT(30)) +#define JPEG_DEZIGZAG_READY_CTL_M (JPEG_DEZIGZAG_READY_CTL_V << JPEG_DEZIGZAG_READY_CTL_S) +#define JPEG_DEZIGZAG_READY_CTL_V 0x00000001U +#define JPEG_DEZIGZAG_READY_CTL_S 30 + +/** JPEG_C0_REG register + * Control and configuration registers + */ +#define JPEG_C0_REG (DR_REG_JPEG_BASE + 0x24) +/** JPEG_C0_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0; + * choose c0 quntization table id (TBD) + */ +#define JPEG_C0_DQT_TBL_SEL 0x000000FFU +#define JPEG_C0_DQT_TBL_SEL_M (JPEG_C0_DQT_TBL_SEL_V << JPEG_C0_DQT_TBL_SEL_S) +#define JPEG_C0_DQT_TBL_SEL_V 0x000000FFU +#define JPEG_C0_DQT_TBL_SEL_S 0 +/** JPEG_C0_Y_FACTOR : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c0 + */ +#define JPEG_C0_Y_FACTOR 0x0000000FU +#define JPEG_C0_Y_FACTOR_M (JPEG_C0_Y_FACTOR_V << JPEG_C0_Y_FACTOR_S) +#define JPEG_C0_Y_FACTOR_V 0x0000000FU +#define JPEG_C0_Y_FACTOR_S 8 +/** JPEG_C0_X_FACTOR : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c0 + */ +#define JPEG_C0_X_FACTOR 0x0000000FU +#define JPEG_C0_X_FACTOR_M (JPEG_C0_X_FACTOR_V << JPEG_C0_X_FACTOR_S) +#define JPEG_C0_X_FACTOR_V 0x0000000FU +#define JPEG_C0_X_FACTOR_S 12 +/** JPEG_C0_ID : R/W; bitpos: [23:16]; default: 0; + * the identifier of c0 + */ +#define JPEG_C0_ID 0x000000FFU +#define JPEG_C0_ID_M (JPEG_C0_ID_V << JPEG_C0_ID_S) +#define JPEG_C0_ID_V 0x000000FFU +#define JPEG_C0_ID_S 16 + +/** JPEG_C1_REG register + * Control and configuration registers + */ +#define JPEG_C1_REG (DR_REG_JPEG_BASE + 0x28) +/** JPEG_C1_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0; + * choose c1 quntization table id (TBD) + */ +#define JPEG_C1_DQT_TBL_SEL 0x000000FFU +#define JPEG_C1_DQT_TBL_SEL_M (JPEG_C1_DQT_TBL_SEL_V << JPEG_C1_DQT_TBL_SEL_S) +#define JPEG_C1_DQT_TBL_SEL_V 0x000000FFU +#define JPEG_C1_DQT_TBL_SEL_S 0 +/** JPEG_C1_Y_FACTOR : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c1 + */ +#define JPEG_C1_Y_FACTOR 0x0000000FU +#define JPEG_C1_Y_FACTOR_M (JPEG_C1_Y_FACTOR_V << JPEG_C1_Y_FACTOR_S) +#define JPEG_C1_Y_FACTOR_V 0x0000000FU +#define JPEG_C1_Y_FACTOR_S 8 +/** JPEG_C1_X_FACTOR : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c1 + */ +#define JPEG_C1_X_FACTOR 0x0000000FU +#define JPEG_C1_X_FACTOR_M (JPEG_C1_X_FACTOR_V << JPEG_C1_X_FACTOR_S) +#define JPEG_C1_X_FACTOR_V 0x0000000FU +#define JPEG_C1_X_FACTOR_S 12 +/** JPEG_C1_ID : R/W; bitpos: [23:16]; default: 0; + * the identifier of c1 + */ +#define JPEG_C1_ID 0x000000FFU +#define JPEG_C1_ID_M (JPEG_C1_ID_V << JPEG_C1_ID_S) +#define JPEG_C1_ID_V 0x000000FFU +#define JPEG_C1_ID_S 16 + +/** JPEG_C2_REG register + * Control and configuration registers + */ +#define JPEG_C2_REG (DR_REG_JPEG_BASE + 0x2c) +/** JPEG_C2_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0; + * choose c2 quntization table id (TBD) + */ +#define JPEG_C2_DQT_TBL_SEL 0x000000FFU +#define JPEG_C2_DQT_TBL_SEL_M (JPEG_C2_DQT_TBL_SEL_V << JPEG_C2_DQT_TBL_SEL_S) +#define JPEG_C2_DQT_TBL_SEL_V 0x000000FFU +#define JPEG_C2_DQT_TBL_SEL_S 0 +/** JPEG_C2_Y_FACTOR : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c2 + */ +#define JPEG_C2_Y_FACTOR 0x0000000FU +#define JPEG_C2_Y_FACTOR_M (JPEG_C2_Y_FACTOR_V << JPEG_C2_Y_FACTOR_S) +#define JPEG_C2_Y_FACTOR_V 0x0000000FU +#define JPEG_C2_Y_FACTOR_S 8 +/** JPEG_C2_X_FACTOR : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c2 + */ +#define JPEG_C2_X_FACTOR 0x0000000FU +#define JPEG_C2_X_FACTOR_M (JPEG_C2_X_FACTOR_V << JPEG_C2_X_FACTOR_S) +#define JPEG_C2_X_FACTOR_V 0x0000000FU +#define JPEG_C2_X_FACTOR_S 12 +/** JPEG_C2_ID : R/W; bitpos: [23:16]; default: 0; + * the identifier of c2 + */ +#define JPEG_C2_ID 0x000000FFU +#define JPEG_C2_ID_M (JPEG_C2_ID_V << JPEG_C2_ID_S) +#define JPEG_C2_ID_V 0x000000FFU +#define JPEG_C2_ID_S 16 + +/** JPEG_C3_REG register + * Control and configuration registers + */ +#define JPEG_C3_REG (DR_REG_JPEG_BASE + 0x30) +/** JPEG_C3_DQT_TBL_SEL : R/W; bitpos: [7:0]; default: 0; + * choose c3 quntization table id (TBD) + */ +#define JPEG_C3_DQT_TBL_SEL 0x000000FFU +#define JPEG_C3_DQT_TBL_SEL_M (JPEG_C3_DQT_TBL_SEL_V << JPEG_C3_DQT_TBL_SEL_S) +#define JPEG_C3_DQT_TBL_SEL_V 0x000000FFU +#define JPEG_C3_DQT_TBL_SEL_S 0 +/** JPEG_C3_Y_FACTOR : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c3 + */ +#define JPEG_C3_Y_FACTOR 0x0000000FU +#define JPEG_C3_Y_FACTOR_M (JPEG_C3_Y_FACTOR_V << JPEG_C3_Y_FACTOR_S) +#define JPEG_C3_Y_FACTOR_V 0x0000000FU +#define JPEG_C3_Y_FACTOR_S 8 +/** JPEG_C3_X_FACTOR : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c3 + */ +#define JPEG_C3_X_FACTOR 0x0000000FU +#define JPEG_C3_X_FACTOR_M (JPEG_C3_X_FACTOR_V << JPEG_C3_X_FACTOR_S) +#define JPEG_C3_X_FACTOR_V 0x0000000FU +#define JPEG_C3_X_FACTOR_S 12 +/** JPEG_C3_ID : R/W; bitpos: [23:16]; default: 0; + * the identifier of c3 + */ +#define JPEG_C3_ID 0x000000FFU +#define JPEG_C3_ID_M (JPEG_C3_ID_V << JPEG_C3_ID_S) +#define JPEG_C3_ID_V 0x000000FFU +#define JPEG_C3_ID_S 16 + +/** JPEG_DHT_INFO_REG register + * Control and configuration registers + */ +#define JPEG_DHT_INFO_REG (DR_REG_JPEG_BASE + 0x34) +/** JPEG_DC0_DHT_ID : R/W; bitpos: [3:0]; default: 0; + * configure dht dc table 0 id + */ +#define JPEG_DC0_DHT_ID 0x0000000FU +#define JPEG_DC0_DHT_ID_M (JPEG_DC0_DHT_ID_V << JPEG_DC0_DHT_ID_S) +#define JPEG_DC0_DHT_ID_V 0x0000000FU +#define JPEG_DC0_DHT_ID_S 0 +/** JPEG_DC1_DHT_ID : R/W; bitpos: [7:4]; default: 1; + * configure dht dc table 1 id + */ +#define JPEG_DC1_DHT_ID 0x0000000FU +#define JPEG_DC1_DHT_ID_M (JPEG_DC1_DHT_ID_V << JPEG_DC1_DHT_ID_S) +#define JPEG_DC1_DHT_ID_V 0x0000000FU +#define JPEG_DC1_DHT_ID_S 4 +/** JPEG_AC0_DHT_ID : R/W; bitpos: [11:8]; default: 0; + * configure dht ac table 0 id + */ +#define JPEG_AC0_DHT_ID 0x0000000FU +#define JPEG_AC0_DHT_ID_M (JPEG_AC0_DHT_ID_V << JPEG_AC0_DHT_ID_S) +#define JPEG_AC0_DHT_ID_V 0x0000000FU +#define JPEG_AC0_DHT_ID_S 8 +/** JPEG_AC1_DHT_ID : R/W; bitpos: [15:12]; default: 1; + * configure dht ac table 1 id + */ +#define JPEG_AC1_DHT_ID 0x0000000FU +#define JPEG_AC1_DHT_ID_M (JPEG_AC1_DHT_ID_V << JPEG_AC1_DHT_ID_S) +#define JPEG_AC1_DHT_ID_V 0x0000000FU +#define JPEG_AC1_DHT_ID_S 12 + +/** JPEG_INT_RAW_REG register + * Interrupt raw registers + */ +#define JPEG_INT_RAW_REG (DR_REG_JPEG_BASE + 0x38) +/** JPEG_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + */ +#define JPEG_DONE_INT_RAW (BIT(0)) +#define JPEG_DONE_INT_RAW_M (JPEG_DONE_INT_RAW_V << JPEG_DONE_INT_RAW_S) +#define JPEG_DONE_INT_RAW_V 0x00000001U +#define JPEG_DONE_INT_RAW_S 0 +/** JPEG_RLE_PARALLEL_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit to sign that rle parallel error when decoding. + */ +#define JPEG_RLE_PARALLEL_ERR_INT_RAW (BIT(1)) +#define JPEG_RLE_PARALLEL_ERR_INT_RAW_M (JPEG_RLE_PARALLEL_ERR_INT_RAW_V << JPEG_RLE_PARALLEL_ERR_INT_RAW_S) +#define JPEG_RLE_PARALLEL_ERR_INT_RAW_V 0x00000001U +#define JPEG_RLE_PARALLEL_ERR_INT_RAW_S 1 +/** JPEG_CID_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit to sign that scan id check with component fails when decoding. + */ +#define JPEG_CID_ERR_INT_RAW (BIT(2)) +#define JPEG_CID_ERR_INT_RAW_M (JPEG_CID_ERR_INT_RAW_V << JPEG_CID_ERR_INT_RAW_S) +#define JPEG_CID_ERR_INT_RAW_V 0x00000001U +#define JPEG_CID_ERR_INT_RAW_S 2 +/** JPEG_C_DHT_DC_ID_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_DC_ID_ERR_INT_RAW (BIT(3)) +#define JPEG_C_DHT_DC_ID_ERR_INT_RAW_M (JPEG_C_DHT_DC_ID_ERR_INT_RAW_V << JPEG_C_DHT_DC_ID_ERR_INT_RAW_S) +#define JPEG_C_DHT_DC_ID_ERR_INT_RAW_V 0x00000001U +#define JPEG_C_DHT_DC_ID_ERR_INT_RAW_S 3 +/** JPEG_C_DHT_AC_ID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_AC_ID_ERR_INT_RAW (BIT(4)) +#define JPEG_C_DHT_AC_ID_ERR_INT_RAW_M (JPEG_C_DHT_AC_ID_ERR_INT_RAW_V << JPEG_C_DHT_AC_ID_ERR_INT_RAW_S) +#define JPEG_C_DHT_AC_ID_ERR_INT_RAW_V 0x00000001U +#define JPEG_C_DHT_AC_ID_ERR_INT_RAW_S 4 +/** JPEG_C_DQT_ID_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit to sign that scan component's dqt id check with dqt table's + * id fails when decoding. + */ +#define JPEG_C_DQT_ID_ERR_INT_RAW (BIT(5)) +#define JPEG_C_DQT_ID_ERR_INT_RAW_M (JPEG_C_DQT_ID_ERR_INT_RAW_V << JPEG_C_DQT_ID_ERR_INT_RAW_S) +#define JPEG_C_DQT_ID_ERR_INT_RAW_V 0x00000001U +#define JPEG_C_DQT_ID_ERR_INT_RAW_S 5 +/** JPEG_RST_UXP_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ +#define JPEG_RST_UXP_ERR_INT_RAW (BIT(6)) +#define JPEG_RST_UXP_ERR_INT_RAW_M (JPEG_RST_UXP_ERR_INT_RAW_V << JPEG_RST_UXP_ERR_INT_RAW_S) +#define JPEG_RST_UXP_ERR_INT_RAW_V 0x00000001U +#define JPEG_RST_UXP_ERR_INT_RAW_S 6 +/** JPEG_RST_CHECK_NONE_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ +#define JPEG_RST_CHECK_NONE_ERR_INT_RAW (BIT(7)) +#define JPEG_RST_CHECK_NONE_ERR_INT_RAW_M (JPEG_RST_CHECK_NONE_ERR_INT_RAW_V << JPEG_RST_CHECK_NONE_ERR_INT_RAW_S) +#define JPEG_RST_CHECK_NONE_ERR_INT_RAW_V 0x00000001U +#define JPEG_RST_CHECK_NONE_ERR_INT_RAW_S 7 +/** JPEG_RST_CHECK_POS_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ +#define JPEG_RST_CHECK_POS_ERR_INT_RAW (BIT(8)) +#define JPEG_RST_CHECK_POS_ERR_INT_RAW_M (JPEG_RST_CHECK_POS_ERR_INT_RAW_V << JPEG_RST_CHECK_POS_ERR_INT_RAW_S) +#define JPEG_RST_CHECK_POS_ERR_INT_RAW_V 0x00000001U +#define JPEG_RST_CHECK_POS_ERR_INT_RAW_S 8 +/** JPEG_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ +#define JPEG_OUT_EOF_INT_RAW (BIT(9)) +#define JPEG_OUT_EOF_INT_RAW_M (JPEG_OUT_EOF_INT_RAW_V << JPEG_OUT_EOF_INT_RAW_S) +#define JPEG_OUT_EOF_INT_RAW_V 0x00000001U +#define JPEG_OUT_EOF_INT_RAW_S 9 +/** JPEG_SR_COLOR_MODE_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit to sign that the selected source color mode is not supported. + */ +#define JPEG_SR_COLOR_MODE_ERR_INT_RAW (BIT(10)) +#define JPEG_SR_COLOR_MODE_ERR_INT_RAW_M (JPEG_SR_COLOR_MODE_ERR_INT_RAW_V << JPEG_SR_COLOR_MODE_ERR_INT_RAW_S) +#define JPEG_SR_COLOR_MODE_ERR_INT_RAW_V 0x00000001U +#define JPEG_SR_COLOR_MODE_ERR_INT_RAW_S 10 +/** JPEG_DCT_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit to sign that one dct calculation is finished. + */ +#define JPEG_DCT_DONE_INT_RAW (BIT(11)) +#define JPEG_DCT_DONE_INT_RAW_M (JPEG_DCT_DONE_INT_RAW_V << JPEG_DCT_DONE_INT_RAW_S) +#define JPEG_DCT_DONE_INT_RAW_V 0x00000001U +#define JPEG_DCT_DONE_INT_RAW_S 11 +/** JPEG_BS_LAST_BLOCK_EOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit to sign that the coding process for last block is finished. + */ +#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW (BIT(12)) +#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW_M (JPEG_BS_LAST_BLOCK_EOF_INT_RAW_V << JPEG_BS_LAST_BLOCK_EOF_INT_RAW_S) +#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW_V 0x00000001U +#define JPEG_BS_LAST_BLOCK_EOF_INT_RAW_S 12 +/** JPEG_SCAN_CHECK_NONE_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit to sign that SOS header marker is not detected but there are + * still components left to be decoded. + */ +#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW (BIT(13)) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_M (JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_V << JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_S) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_V 0x00000001U +#define JPEG_SCAN_CHECK_NONE_ERR_INT_RAW_S 13 +/** JPEG_SCAN_CHECK_POS_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit to sign that SOS header marker position wrong when decoding. + */ +#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW (BIT(14)) +#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW_M (JPEG_SCAN_CHECK_POS_ERR_INT_RAW_V << JPEG_SCAN_CHECK_POS_ERR_INT_RAW_S) +#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW_V 0x00000001U +#define JPEG_SCAN_CHECK_POS_ERR_INT_RAW_S 14 +/** JPEG_UXP_DET_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ +#define JPEG_UXP_DET_INT_RAW (BIT(15)) +#define JPEG_UXP_DET_INT_RAW_M (JPEG_UXP_DET_INT_RAW_V << JPEG_UXP_DET_INT_RAW_S) +#define JPEG_UXP_DET_INT_RAW_V 0x00000001U +#define JPEG_UXP_DET_INT_RAW_S 15 +/** JPEG_EN_FRAME_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit to sign that received pixel blocks are smaller than expected + * when encoding. + */ +#define JPEG_EN_FRAME_EOF_ERR_INT_RAW (BIT(16)) +#define JPEG_EN_FRAME_EOF_ERR_INT_RAW_M (JPEG_EN_FRAME_EOF_ERR_INT_RAW_V << JPEG_EN_FRAME_EOF_ERR_INT_RAW_S) +#define JPEG_EN_FRAME_EOF_ERR_INT_RAW_V 0x00000001U +#define JPEG_EN_FRAME_EOF_ERR_INT_RAW_S 16 +/** JPEG_EN_FRAME_EOF_LACK_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit to sign that the frame eof sign bit from dma input is missing + * when encoding. But the number of pixel blocks is enough. + */ +#define JPEG_EN_FRAME_EOF_LACK_INT_RAW (BIT(17)) +#define JPEG_EN_FRAME_EOF_LACK_INT_RAW_M (JPEG_EN_FRAME_EOF_LACK_INT_RAW_V << JPEG_EN_FRAME_EOF_LACK_INT_RAW_S) +#define JPEG_EN_FRAME_EOF_LACK_INT_RAW_V 0x00000001U +#define JPEG_EN_FRAME_EOF_LACK_INT_RAW_S 17 +/** JPEG_DE_FRAME_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ +#define JPEG_DE_FRAME_EOF_ERR_INT_RAW (BIT(18)) +#define JPEG_DE_FRAME_EOF_ERR_INT_RAW_M (JPEG_DE_FRAME_EOF_ERR_INT_RAW_V << JPEG_DE_FRAME_EOF_ERR_INT_RAW_S) +#define JPEG_DE_FRAME_EOF_ERR_INT_RAW_V 0x00000001U +#define JPEG_DE_FRAME_EOF_ERR_INT_RAW_S 18 +/** JPEG_DE_FRAME_EOF_LACK_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ +#define JPEG_DE_FRAME_EOF_LACK_INT_RAW (BIT(19)) +#define JPEG_DE_FRAME_EOF_LACK_INT_RAW_M (JPEG_DE_FRAME_EOF_LACK_INT_RAW_V << JPEG_DE_FRAME_EOF_LACK_INT_RAW_S) +#define JPEG_DE_FRAME_EOF_LACK_INT_RAW_V 0x00000001U +#define JPEG_DE_FRAME_EOF_LACK_INT_RAW_S 19 +/** JPEG_SOS_UNMATCH_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit to sign that the component number of a scan is 0 or does not + * match the sos marker's length when decoding. + */ +#define JPEG_SOS_UNMATCH_ERR_INT_RAW (BIT(20)) +#define JPEG_SOS_UNMATCH_ERR_INT_RAW_M (JPEG_SOS_UNMATCH_ERR_INT_RAW_V << JPEG_SOS_UNMATCH_ERR_INT_RAW_S) +#define JPEG_SOS_UNMATCH_ERR_INT_RAW_V 0x00000001U +#define JPEG_SOS_UNMATCH_ERR_INT_RAW_S 20 +/** JPEG_MARKER_ERR_FST_SCAN_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit to sign that the first scan has header marker error when + * decoding. + */ +#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW (BIT(21)) +#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW_M (JPEG_MARKER_ERR_FST_SCAN_INT_RAW_V << JPEG_MARKER_ERR_FST_SCAN_INT_RAW_S) +#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW_V 0x00000001U +#define JPEG_MARKER_ERR_FST_SCAN_INT_RAW_S 21 +/** JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit to sign that the following scans but not the first scan have + * header marker error when decoding. + */ +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW (BIT(22)) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_M (JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_S) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_V 0x00000001U +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_RAW_S 22 +/** JPEG_UNDET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit to sign that JPEG format is not detected at the eof data of a + * packet when decoding. + */ +#define JPEG_UNDET_INT_RAW (BIT(23)) +#define JPEG_UNDET_INT_RAW_M (JPEG_UNDET_INT_RAW_V << JPEG_UNDET_INT_RAW_S) +#define JPEG_UNDET_INT_RAW_V 0x00000001U +#define JPEG_UNDET_INT_RAW_S 23 +/** JPEG_DECODE_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ +#define JPEG_DECODE_TIMEOUT_INT_RAW (BIT(24)) +#define JPEG_DECODE_TIMEOUT_INT_RAW_M (JPEG_DECODE_TIMEOUT_INT_RAW_V << JPEG_DECODE_TIMEOUT_INT_RAW_S) +#define JPEG_DECODE_TIMEOUT_INT_RAW_V 0x00000001U +#define JPEG_DECODE_TIMEOUT_INT_RAW_S 24 + +/** JPEG_INT_ENA_REG register + * Interrupt enable registers + */ +#define JPEG_INT_ENA_REG (DR_REG_JPEG_BASE + 0x3c) +/** JPEG_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * This enable interrupt bit turns to high level when JPEG finishes encoding a + * picture.. + */ +#define JPEG_DONE_INT_ENA (BIT(0)) +#define JPEG_DONE_INT_ENA_M (JPEG_DONE_INT_ENA_V << JPEG_DONE_INT_ENA_S) +#define JPEG_DONE_INT_ENA_V 0x00000001U +#define JPEG_DONE_INT_ENA_S 0 +/** JPEG_RLE_PARALLEL_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable interrupt bit to sign that rle parallel error when decoding. + */ +#define JPEG_RLE_PARALLEL_ERR_INT_ENA (BIT(1)) +#define JPEG_RLE_PARALLEL_ERR_INT_ENA_M (JPEG_RLE_PARALLEL_ERR_INT_ENA_V << JPEG_RLE_PARALLEL_ERR_INT_ENA_S) +#define JPEG_RLE_PARALLEL_ERR_INT_ENA_V 0x00000001U +#define JPEG_RLE_PARALLEL_ERR_INT_ENA_S 1 +/** JPEG_CID_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable interrupt bit to sign that scan id check with component fails when + * decoding. + */ +#define JPEG_CID_ERR_INT_ENA (BIT(2)) +#define JPEG_CID_ERR_INT_ENA_M (JPEG_CID_ERR_INT_ENA_V << JPEG_CID_ERR_INT_ENA_S) +#define JPEG_CID_ERR_INT_ENA_V 0x00000001U +#define JPEG_CID_ERR_INT_ENA_S 2 +/** JPEG_C_DHT_DC_ID_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_DC_ID_ERR_INT_ENA (BIT(3)) +#define JPEG_C_DHT_DC_ID_ERR_INT_ENA_M (JPEG_C_DHT_DC_ID_ERR_INT_ENA_V << JPEG_C_DHT_DC_ID_ERR_INT_ENA_S) +#define JPEG_C_DHT_DC_ID_ERR_INT_ENA_V 0x00000001U +#define JPEG_C_DHT_DC_ID_ERR_INT_ENA_S 3 +/** JPEG_C_DHT_AC_ID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_AC_ID_ERR_INT_ENA (BIT(4)) +#define JPEG_C_DHT_AC_ID_ERR_INT_ENA_M (JPEG_C_DHT_AC_ID_ERR_INT_ENA_V << JPEG_C_DHT_AC_ID_ERR_INT_ENA_S) +#define JPEG_C_DHT_AC_ID_ERR_INT_ENA_V 0x00000001U +#define JPEG_C_DHT_AC_ID_ERR_INT_ENA_S 4 +/** JPEG_C_DQT_ID_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable interrupt bit to sign that scan component's dqt id check with dqt + * table's id fails when decoding. + */ +#define JPEG_C_DQT_ID_ERR_INT_ENA (BIT(5)) +#define JPEG_C_DQT_ID_ERR_INT_ENA_M (JPEG_C_DQT_ID_ERR_INT_ENA_V << JPEG_C_DQT_ID_ERR_INT_ENA_S) +#define JPEG_C_DQT_ID_ERR_INT_ENA_V 0x00000001U +#define JPEG_C_DQT_ID_ERR_INT_ENA_S 5 +/** JPEG_RST_UXP_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ +#define JPEG_RST_UXP_ERR_INT_ENA (BIT(6)) +#define JPEG_RST_UXP_ERR_INT_ENA_M (JPEG_RST_UXP_ERR_INT_ENA_V << JPEG_RST_UXP_ERR_INT_ENA_S) +#define JPEG_RST_UXP_ERR_INT_ENA_V 0x00000001U +#define JPEG_RST_UXP_ERR_INT_ENA_S 6 +/** JPEG_RST_CHECK_NONE_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ +#define JPEG_RST_CHECK_NONE_ERR_INT_ENA (BIT(7)) +#define JPEG_RST_CHECK_NONE_ERR_INT_ENA_M (JPEG_RST_CHECK_NONE_ERR_INT_ENA_V << JPEG_RST_CHECK_NONE_ERR_INT_ENA_S) +#define JPEG_RST_CHECK_NONE_ERR_INT_ENA_V 0x00000001U +#define JPEG_RST_CHECK_NONE_ERR_INT_ENA_S 7 +/** JPEG_RST_CHECK_POS_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ +#define JPEG_RST_CHECK_POS_ERR_INT_ENA (BIT(8)) +#define JPEG_RST_CHECK_POS_ERR_INT_ENA_M (JPEG_RST_CHECK_POS_ERR_INT_ENA_V << JPEG_RST_CHECK_POS_ERR_INT_ENA_S) +#define JPEG_RST_CHECK_POS_ERR_INT_ENA_V 0x00000001U +#define JPEG_RST_CHECK_POS_ERR_INT_ENA_S 8 +/** JPEG_OUT_EOF_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ +#define JPEG_OUT_EOF_INT_ENA (BIT(9)) +#define JPEG_OUT_EOF_INT_ENA_M (JPEG_OUT_EOF_INT_ENA_V << JPEG_OUT_EOF_INT_ENA_S) +#define JPEG_OUT_EOF_INT_ENA_V 0x00000001U +#define JPEG_OUT_EOF_INT_ENA_S 9 +/** JPEG_SR_COLOR_MODE_ERR_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable interrupt bit to sign that the selected source color mode is not + * supported. + */ +#define JPEG_SR_COLOR_MODE_ERR_INT_ENA (BIT(10)) +#define JPEG_SR_COLOR_MODE_ERR_INT_ENA_M (JPEG_SR_COLOR_MODE_ERR_INT_ENA_V << JPEG_SR_COLOR_MODE_ERR_INT_ENA_S) +#define JPEG_SR_COLOR_MODE_ERR_INT_ENA_V 0x00000001U +#define JPEG_SR_COLOR_MODE_ERR_INT_ENA_S 10 +/** JPEG_DCT_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable interrupt bit to sign that one dct calculation is finished. + */ +#define JPEG_DCT_DONE_INT_ENA (BIT(11)) +#define JPEG_DCT_DONE_INT_ENA_M (JPEG_DCT_DONE_INT_ENA_V << JPEG_DCT_DONE_INT_ENA_S) +#define JPEG_DCT_DONE_INT_ENA_V 0x00000001U +#define JPEG_DCT_DONE_INT_ENA_S 11 +/** JPEG_BS_LAST_BLOCK_EOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable interrupt bit to sign that the coding process for last block is finished. + */ +#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA (BIT(12)) +#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA_M (JPEG_BS_LAST_BLOCK_EOF_INT_ENA_V << JPEG_BS_LAST_BLOCK_EOF_INT_ENA_S) +#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA_V 0x00000001U +#define JPEG_BS_LAST_BLOCK_EOF_INT_ENA_S 12 +/** JPEG_SCAN_CHECK_NONE_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA (BIT(13)) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_M (JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_V << JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_S) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_V 0x00000001U +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ENA_S 13 +/** JPEG_SCAN_CHECK_POS_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable interrupt bit to sign that SOS header marker position wrong when + * decoding. + */ +#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA (BIT(14)) +#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA_M (JPEG_SCAN_CHECK_POS_ERR_INT_ENA_V << JPEG_SCAN_CHECK_POS_ERR_INT_ENA_S) +#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA_V 0x00000001U +#define JPEG_SCAN_CHECK_POS_ERR_INT_ENA_S 14 +/** JPEG_UXP_DET_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ +#define JPEG_UXP_DET_INT_ENA (BIT(15)) +#define JPEG_UXP_DET_INT_ENA_M (JPEG_UXP_DET_INT_ENA_V << JPEG_UXP_DET_INT_ENA_S) +#define JPEG_UXP_DET_INT_ENA_V 0x00000001U +#define JPEG_UXP_DET_INT_ENA_S 15 +/** JPEG_EN_FRAME_EOF_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ +#define JPEG_EN_FRAME_EOF_ERR_INT_ENA (BIT(16)) +#define JPEG_EN_FRAME_EOF_ERR_INT_ENA_M (JPEG_EN_FRAME_EOF_ERR_INT_ENA_V << JPEG_EN_FRAME_EOF_ERR_INT_ENA_S) +#define JPEG_EN_FRAME_EOF_ERR_INT_ENA_V 0x00000001U +#define JPEG_EN_FRAME_EOF_ERR_INT_ENA_S 16 +/** JPEG_EN_FRAME_EOF_LACK_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ +#define JPEG_EN_FRAME_EOF_LACK_INT_ENA (BIT(17)) +#define JPEG_EN_FRAME_EOF_LACK_INT_ENA_M (JPEG_EN_FRAME_EOF_LACK_INT_ENA_V << JPEG_EN_FRAME_EOF_LACK_INT_ENA_S) +#define JPEG_EN_FRAME_EOF_LACK_INT_ENA_V 0x00000001U +#define JPEG_EN_FRAME_EOF_LACK_INT_ENA_S 17 +/** JPEG_DE_FRAME_EOF_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ +#define JPEG_DE_FRAME_EOF_ERR_INT_ENA (BIT(18)) +#define JPEG_DE_FRAME_EOF_ERR_INT_ENA_M (JPEG_DE_FRAME_EOF_ERR_INT_ENA_V << JPEG_DE_FRAME_EOF_ERR_INT_ENA_S) +#define JPEG_DE_FRAME_EOF_ERR_INT_ENA_V 0x00000001U +#define JPEG_DE_FRAME_EOF_ERR_INT_ENA_S 18 +/** JPEG_DE_FRAME_EOF_LACK_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ +#define JPEG_DE_FRAME_EOF_LACK_INT_ENA (BIT(19)) +#define JPEG_DE_FRAME_EOF_LACK_INT_ENA_M (JPEG_DE_FRAME_EOF_LACK_INT_ENA_V << JPEG_DE_FRAME_EOF_LACK_INT_ENA_S) +#define JPEG_DE_FRAME_EOF_LACK_INT_ENA_V 0x00000001U +#define JPEG_DE_FRAME_EOF_LACK_INT_ENA_S 19 +/** JPEG_SOS_UNMATCH_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ +#define JPEG_SOS_UNMATCH_ERR_INT_ENA (BIT(20)) +#define JPEG_SOS_UNMATCH_ERR_INT_ENA_M (JPEG_SOS_UNMATCH_ERR_INT_ENA_V << JPEG_SOS_UNMATCH_ERR_INT_ENA_S) +#define JPEG_SOS_UNMATCH_ERR_INT_ENA_V 0x00000001U +#define JPEG_SOS_UNMATCH_ERR_INT_ENA_S 20 +/** JPEG_MARKER_ERR_FST_SCAN_INT_ENA : R/W; bitpos: [21]; default: 0; + * The enable interrupt bit to sign that the first scan has header marker error when + * decoding. + */ +#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA (BIT(21)) +#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA_M (JPEG_MARKER_ERR_FST_SCAN_INT_ENA_V << JPEG_MARKER_ERR_FST_SCAN_INT_ENA_S) +#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA_V 0x00000001U +#define JPEG_MARKER_ERR_FST_SCAN_INT_ENA_S 21 +/** JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA : R/W; bitpos: [22]; default: 0; + * The enable interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA (BIT(22)) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_M (JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_S) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_V 0x00000001U +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ENA_S 22 +/** JPEG_UNDET_INT_ENA : R/W; bitpos: [23]; default: 0; + * The enable interrupt bit to sign that JPEG format is not detected at the eof data + * of a packet when decoding. + */ +#define JPEG_UNDET_INT_ENA (BIT(23)) +#define JPEG_UNDET_INT_ENA_M (JPEG_UNDET_INT_ENA_V << JPEG_UNDET_INT_ENA_S) +#define JPEG_UNDET_INT_ENA_V 0x00000001U +#define JPEG_UNDET_INT_ENA_S 23 +/** JPEG_DECODE_TIMEOUT_INT_ENA : R/W; bitpos: [24]; default: 0; + * The enable interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ +#define JPEG_DECODE_TIMEOUT_INT_ENA (BIT(24)) +#define JPEG_DECODE_TIMEOUT_INT_ENA_M (JPEG_DECODE_TIMEOUT_INT_ENA_V << JPEG_DECODE_TIMEOUT_INT_ENA_S) +#define JPEG_DECODE_TIMEOUT_INT_ENA_V 0x00000001U +#define JPEG_DECODE_TIMEOUT_INT_ENA_S 24 + +/** JPEG_INT_ST_REG register + * Interrupt status registers + */ +#define JPEG_INT_ST_REG (DR_REG_JPEG_BASE + 0x40) +/** JPEG_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * This status interrupt bit turns to high level when JPEG finishes encoding a + * picture.. + */ +#define JPEG_DONE_INT_ST (BIT(0)) +#define JPEG_DONE_INT_ST_M (JPEG_DONE_INT_ST_V << JPEG_DONE_INT_ST_S) +#define JPEG_DONE_INT_ST_V 0x00000001U +#define JPEG_DONE_INT_ST_S 0 +/** JPEG_RLE_PARALLEL_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status interrupt bit to sign that rle parallel error when decoding. + */ +#define JPEG_RLE_PARALLEL_ERR_INT_ST (BIT(1)) +#define JPEG_RLE_PARALLEL_ERR_INT_ST_M (JPEG_RLE_PARALLEL_ERR_INT_ST_V << JPEG_RLE_PARALLEL_ERR_INT_ST_S) +#define JPEG_RLE_PARALLEL_ERR_INT_ST_V 0x00000001U +#define JPEG_RLE_PARALLEL_ERR_INT_ST_S 1 +/** JPEG_CID_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * The status interrupt bit to sign that scan id check with component fails when + * decoding. + */ +#define JPEG_CID_ERR_INT_ST (BIT(2)) +#define JPEG_CID_ERR_INT_ST_M (JPEG_CID_ERR_INT_ST_V << JPEG_CID_ERR_INT_ST_S) +#define JPEG_CID_ERR_INT_ST_V 0x00000001U +#define JPEG_CID_ERR_INT_ST_S 2 +/** JPEG_C_DHT_DC_ID_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * The status interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_DC_ID_ERR_INT_ST (BIT(3)) +#define JPEG_C_DHT_DC_ID_ERR_INT_ST_M (JPEG_C_DHT_DC_ID_ERR_INT_ST_V << JPEG_C_DHT_DC_ID_ERR_INT_ST_S) +#define JPEG_C_DHT_DC_ID_ERR_INT_ST_V 0x00000001U +#define JPEG_C_DHT_DC_ID_ERR_INT_ST_S 3 +/** JPEG_C_DHT_AC_ID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The status interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_AC_ID_ERR_INT_ST (BIT(4)) +#define JPEG_C_DHT_AC_ID_ERR_INT_ST_M (JPEG_C_DHT_AC_ID_ERR_INT_ST_V << JPEG_C_DHT_AC_ID_ERR_INT_ST_S) +#define JPEG_C_DHT_AC_ID_ERR_INT_ST_V 0x00000001U +#define JPEG_C_DHT_AC_ID_ERR_INT_ST_S 4 +/** JPEG_C_DQT_ID_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The status interrupt bit to sign that scan component's dqt id check with dqt + * table's id fails when decoding. + */ +#define JPEG_C_DQT_ID_ERR_INT_ST (BIT(5)) +#define JPEG_C_DQT_ID_ERR_INT_ST_M (JPEG_C_DQT_ID_ERR_INT_ST_V << JPEG_C_DQT_ID_ERR_INT_ST_S) +#define JPEG_C_DQT_ID_ERR_INT_ST_V 0x00000001U +#define JPEG_C_DQT_ID_ERR_INT_ST_S 5 +/** JPEG_RST_UXP_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The status interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ +#define JPEG_RST_UXP_ERR_INT_ST (BIT(6)) +#define JPEG_RST_UXP_ERR_INT_ST_M (JPEG_RST_UXP_ERR_INT_ST_V << JPEG_RST_UXP_ERR_INT_ST_S) +#define JPEG_RST_UXP_ERR_INT_ST_V 0x00000001U +#define JPEG_RST_UXP_ERR_INT_ST_S 6 +/** JPEG_RST_CHECK_NONE_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The status interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ +#define JPEG_RST_CHECK_NONE_ERR_INT_ST (BIT(7)) +#define JPEG_RST_CHECK_NONE_ERR_INT_ST_M (JPEG_RST_CHECK_NONE_ERR_INT_ST_V << JPEG_RST_CHECK_NONE_ERR_INT_ST_S) +#define JPEG_RST_CHECK_NONE_ERR_INT_ST_V 0x00000001U +#define JPEG_RST_CHECK_NONE_ERR_INT_ST_S 7 +/** JPEG_RST_CHECK_POS_ERR_INT_ST : RO; bitpos: [8]; default: 0; + * The status interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ +#define JPEG_RST_CHECK_POS_ERR_INT_ST (BIT(8)) +#define JPEG_RST_CHECK_POS_ERR_INT_ST_M (JPEG_RST_CHECK_POS_ERR_INT_ST_V << JPEG_RST_CHECK_POS_ERR_INT_ST_S) +#define JPEG_RST_CHECK_POS_ERR_INT_ST_V 0x00000001U +#define JPEG_RST_CHECK_POS_ERR_INT_ST_S 8 +/** JPEG_OUT_EOF_INT_ST : RO; bitpos: [9]; default: 0; + * The status interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ +#define JPEG_OUT_EOF_INT_ST (BIT(9)) +#define JPEG_OUT_EOF_INT_ST_M (JPEG_OUT_EOF_INT_ST_V << JPEG_OUT_EOF_INT_ST_S) +#define JPEG_OUT_EOF_INT_ST_V 0x00000001U +#define JPEG_OUT_EOF_INT_ST_S 9 +/** JPEG_SR_COLOR_MODE_ERR_INT_ST : RO; bitpos: [10]; default: 0; + * The status interrupt bit to sign that the selected source color mode is not + * supported. + */ +#define JPEG_SR_COLOR_MODE_ERR_INT_ST (BIT(10)) +#define JPEG_SR_COLOR_MODE_ERR_INT_ST_M (JPEG_SR_COLOR_MODE_ERR_INT_ST_V << JPEG_SR_COLOR_MODE_ERR_INT_ST_S) +#define JPEG_SR_COLOR_MODE_ERR_INT_ST_V 0x00000001U +#define JPEG_SR_COLOR_MODE_ERR_INT_ST_S 10 +/** JPEG_DCT_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status interrupt bit to sign that one dct calculation is finished. + */ +#define JPEG_DCT_DONE_INT_ST (BIT(11)) +#define JPEG_DCT_DONE_INT_ST_M (JPEG_DCT_DONE_INT_ST_V << JPEG_DCT_DONE_INT_ST_S) +#define JPEG_DCT_DONE_INT_ST_V 0x00000001U +#define JPEG_DCT_DONE_INT_ST_S 11 +/** JPEG_BS_LAST_BLOCK_EOF_INT_ST : RO; bitpos: [12]; default: 0; + * The status interrupt bit to sign that the coding process for last block is finished. + */ +#define JPEG_BS_LAST_BLOCK_EOF_INT_ST (BIT(12)) +#define JPEG_BS_LAST_BLOCK_EOF_INT_ST_M (JPEG_BS_LAST_BLOCK_EOF_INT_ST_V << JPEG_BS_LAST_BLOCK_EOF_INT_ST_S) +#define JPEG_BS_LAST_BLOCK_EOF_INT_ST_V 0x00000001U +#define JPEG_BS_LAST_BLOCK_EOF_INT_ST_S 12 +/** JPEG_SCAN_CHECK_NONE_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The status interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST (BIT(13)) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST_M (JPEG_SCAN_CHECK_NONE_ERR_INT_ST_V << JPEG_SCAN_CHECK_NONE_ERR_INT_ST_S) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST_V 0x00000001U +#define JPEG_SCAN_CHECK_NONE_ERR_INT_ST_S 13 +/** JPEG_SCAN_CHECK_POS_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status interrupt bit to sign that SOS header marker position wrong when + * decoding. + */ +#define JPEG_SCAN_CHECK_POS_ERR_INT_ST (BIT(14)) +#define JPEG_SCAN_CHECK_POS_ERR_INT_ST_M (JPEG_SCAN_CHECK_POS_ERR_INT_ST_V << JPEG_SCAN_CHECK_POS_ERR_INT_ST_S) +#define JPEG_SCAN_CHECK_POS_ERR_INT_ST_V 0x00000001U +#define JPEG_SCAN_CHECK_POS_ERR_INT_ST_S 14 +/** JPEG_UXP_DET_INT_ST : RO; bitpos: [15]; default: 0; + * The status interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ +#define JPEG_UXP_DET_INT_ST (BIT(15)) +#define JPEG_UXP_DET_INT_ST_M (JPEG_UXP_DET_INT_ST_V << JPEG_UXP_DET_INT_ST_S) +#define JPEG_UXP_DET_INT_ST_V 0x00000001U +#define JPEG_UXP_DET_INT_ST_S 15 +/** JPEG_EN_FRAME_EOF_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ +#define JPEG_EN_FRAME_EOF_ERR_INT_ST (BIT(16)) +#define JPEG_EN_FRAME_EOF_ERR_INT_ST_M (JPEG_EN_FRAME_EOF_ERR_INT_ST_V << JPEG_EN_FRAME_EOF_ERR_INT_ST_S) +#define JPEG_EN_FRAME_EOF_ERR_INT_ST_V 0x00000001U +#define JPEG_EN_FRAME_EOF_ERR_INT_ST_S 16 +/** JPEG_EN_FRAME_EOF_LACK_INT_ST : RO; bitpos: [17]; default: 0; + * The status interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ +#define JPEG_EN_FRAME_EOF_LACK_INT_ST (BIT(17)) +#define JPEG_EN_FRAME_EOF_LACK_INT_ST_M (JPEG_EN_FRAME_EOF_LACK_INT_ST_V << JPEG_EN_FRAME_EOF_LACK_INT_ST_S) +#define JPEG_EN_FRAME_EOF_LACK_INT_ST_V 0x00000001U +#define JPEG_EN_FRAME_EOF_LACK_INT_ST_S 17 +/** JPEG_DE_FRAME_EOF_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ +#define JPEG_DE_FRAME_EOF_ERR_INT_ST (BIT(18)) +#define JPEG_DE_FRAME_EOF_ERR_INT_ST_M (JPEG_DE_FRAME_EOF_ERR_INT_ST_V << JPEG_DE_FRAME_EOF_ERR_INT_ST_S) +#define JPEG_DE_FRAME_EOF_ERR_INT_ST_V 0x00000001U +#define JPEG_DE_FRAME_EOF_ERR_INT_ST_S 18 +/** JPEG_DE_FRAME_EOF_LACK_INT_ST : RO; bitpos: [19]; default: 0; + * The status interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ +#define JPEG_DE_FRAME_EOF_LACK_INT_ST (BIT(19)) +#define JPEG_DE_FRAME_EOF_LACK_INT_ST_M (JPEG_DE_FRAME_EOF_LACK_INT_ST_V << JPEG_DE_FRAME_EOF_LACK_INT_ST_S) +#define JPEG_DE_FRAME_EOF_LACK_INT_ST_V 0x00000001U +#define JPEG_DE_FRAME_EOF_LACK_INT_ST_S 19 +/** JPEG_SOS_UNMATCH_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The status interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ +#define JPEG_SOS_UNMATCH_ERR_INT_ST (BIT(20)) +#define JPEG_SOS_UNMATCH_ERR_INT_ST_M (JPEG_SOS_UNMATCH_ERR_INT_ST_V << JPEG_SOS_UNMATCH_ERR_INT_ST_S) +#define JPEG_SOS_UNMATCH_ERR_INT_ST_V 0x00000001U +#define JPEG_SOS_UNMATCH_ERR_INT_ST_S 20 +/** JPEG_MARKER_ERR_FST_SCAN_INT_ST : RO; bitpos: [21]; default: 0; + * The status interrupt bit to sign that the first scan has header marker error when + * decoding. + */ +#define JPEG_MARKER_ERR_FST_SCAN_INT_ST (BIT(21)) +#define JPEG_MARKER_ERR_FST_SCAN_INT_ST_M (JPEG_MARKER_ERR_FST_SCAN_INT_ST_V << JPEG_MARKER_ERR_FST_SCAN_INT_ST_S) +#define JPEG_MARKER_ERR_FST_SCAN_INT_ST_V 0x00000001U +#define JPEG_MARKER_ERR_FST_SCAN_INT_ST_S 21 +/** JPEG_MARKER_ERR_OTHER_SCAN_INT_ST : RO; bitpos: [22]; default: 0; + * The status interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST (BIT(22)) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_M (JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_S) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_V 0x00000001U +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_ST_S 22 +/** JPEG_UNDET_INT_ST : RO; bitpos: [23]; default: 0; + * The status interrupt bit to sign that JPEG format is not detected at the eof data + * of a packet when decoding. + */ +#define JPEG_UNDET_INT_ST (BIT(23)) +#define JPEG_UNDET_INT_ST_M (JPEG_UNDET_INT_ST_V << JPEG_UNDET_INT_ST_S) +#define JPEG_UNDET_INT_ST_V 0x00000001U +#define JPEG_UNDET_INT_ST_S 23 +/** JPEG_DECODE_TIMEOUT_INT_ST : RO; bitpos: [24]; default: 0; + * The status interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ +#define JPEG_DECODE_TIMEOUT_INT_ST (BIT(24)) +#define JPEG_DECODE_TIMEOUT_INT_ST_M (JPEG_DECODE_TIMEOUT_INT_ST_V << JPEG_DECODE_TIMEOUT_INT_ST_S) +#define JPEG_DECODE_TIMEOUT_INT_ST_V 0x00000001U +#define JPEG_DECODE_TIMEOUT_INT_ST_S 24 + +/** JPEG_INT_CLR_REG register + * Interrupt clear registers + */ +#define JPEG_INT_CLR_REG (DR_REG_JPEG_BASE + 0x44) +/** JPEG_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + */ +#define JPEG_DONE_INT_CLR (BIT(0)) +#define JPEG_DONE_INT_CLR_M (JPEG_DONE_INT_CLR_V << JPEG_DONE_INT_CLR_S) +#define JPEG_DONE_INT_CLR_V 0x00000001U +#define JPEG_DONE_INT_CLR_S 0 +/** JPEG_RLE_PARALLEL_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear interrupt bit to sign that rle parallel error when decoding. + */ +#define JPEG_RLE_PARALLEL_ERR_INT_CLR (BIT(1)) +#define JPEG_RLE_PARALLEL_ERR_INT_CLR_M (JPEG_RLE_PARALLEL_ERR_INT_CLR_V << JPEG_RLE_PARALLEL_ERR_INT_CLR_S) +#define JPEG_RLE_PARALLEL_ERR_INT_CLR_V 0x00000001U +#define JPEG_RLE_PARALLEL_ERR_INT_CLR_S 1 +/** JPEG_CID_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear interrupt bit to sign that scan id check with component fails when + * decoding. + */ +#define JPEG_CID_ERR_INT_CLR (BIT(2)) +#define JPEG_CID_ERR_INT_CLR_M (JPEG_CID_ERR_INT_CLR_V << JPEG_CID_ERR_INT_CLR_S) +#define JPEG_CID_ERR_INT_CLR_V 0x00000001U +#define JPEG_CID_ERR_INT_CLR_S 2 +/** JPEG_C_DHT_DC_ID_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_DC_ID_ERR_INT_CLR (BIT(3)) +#define JPEG_C_DHT_DC_ID_ERR_INT_CLR_M (JPEG_C_DHT_DC_ID_ERR_INT_CLR_V << JPEG_C_DHT_DC_ID_ERR_INT_CLR_S) +#define JPEG_C_DHT_DC_ID_ERR_INT_CLR_V 0x00000001U +#define JPEG_C_DHT_DC_ID_ERR_INT_CLR_S 3 +/** JPEG_C_DHT_AC_ID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ +#define JPEG_C_DHT_AC_ID_ERR_INT_CLR (BIT(4)) +#define JPEG_C_DHT_AC_ID_ERR_INT_CLR_M (JPEG_C_DHT_AC_ID_ERR_INT_CLR_V << JPEG_C_DHT_AC_ID_ERR_INT_CLR_S) +#define JPEG_C_DHT_AC_ID_ERR_INT_CLR_V 0x00000001U +#define JPEG_C_DHT_AC_ID_ERR_INT_CLR_S 4 +/** JPEG_C_DQT_ID_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear interrupt bit to sign that scan component's dqt id check with dqt table's + * id fails when decoding. + */ +#define JPEG_C_DQT_ID_ERR_INT_CLR (BIT(5)) +#define JPEG_C_DQT_ID_ERR_INT_CLR_M (JPEG_C_DQT_ID_ERR_INT_CLR_V << JPEG_C_DQT_ID_ERR_INT_CLR_S) +#define JPEG_C_DQT_ID_ERR_INT_CLR_V 0x00000001U +#define JPEG_C_DQT_ID_ERR_INT_CLR_S 5 +/** JPEG_RST_UXP_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ +#define JPEG_RST_UXP_ERR_INT_CLR (BIT(6)) +#define JPEG_RST_UXP_ERR_INT_CLR_M (JPEG_RST_UXP_ERR_INT_CLR_V << JPEG_RST_UXP_ERR_INT_CLR_S) +#define JPEG_RST_UXP_ERR_INT_CLR_V 0x00000001U +#define JPEG_RST_UXP_ERR_INT_CLR_S 6 +/** JPEG_RST_CHECK_NONE_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ +#define JPEG_RST_CHECK_NONE_ERR_INT_CLR (BIT(7)) +#define JPEG_RST_CHECK_NONE_ERR_INT_CLR_M (JPEG_RST_CHECK_NONE_ERR_INT_CLR_V << JPEG_RST_CHECK_NONE_ERR_INT_CLR_S) +#define JPEG_RST_CHECK_NONE_ERR_INT_CLR_V 0x00000001U +#define JPEG_RST_CHECK_NONE_ERR_INT_CLR_S 7 +/** JPEG_RST_CHECK_POS_ERR_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ +#define JPEG_RST_CHECK_POS_ERR_INT_CLR (BIT(8)) +#define JPEG_RST_CHECK_POS_ERR_INT_CLR_M (JPEG_RST_CHECK_POS_ERR_INT_CLR_V << JPEG_RST_CHECK_POS_ERR_INT_CLR_S) +#define JPEG_RST_CHECK_POS_ERR_INT_CLR_V 0x00000001U +#define JPEG_RST_CHECK_POS_ERR_INT_CLR_S 8 +/** JPEG_OUT_EOF_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ +#define JPEG_OUT_EOF_INT_CLR (BIT(9)) +#define JPEG_OUT_EOF_INT_CLR_M (JPEG_OUT_EOF_INT_CLR_V << JPEG_OUT_EOF_INT_CLR_S) +#define JPEG_OUT_EOF_INT_CLR_V 0x00000001U +#define JPEG_OUT_EOF_INT_CLR_S 9 +/** JPEG_SR_COLOR_MODE_ERR_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear interrupt bit to sign that the selected source color mode is not + * supported. + */ +#define JPEG_SR_COLOR_MODE_ERR_INT_CLR (BIT(10)) +#define JPEG_SR_COLOR_MODE_ERR_INT_CLR_M (JPEG_SR_COLOR_MODE_ERR_INT_CLR_V << JPEG_SR_COLOR_MODE_ERR_INT_CLR_S) +#define JPEG_SR_COLOR_MODE_ERR_INT_CLR_V 0x00000001U +#define JPEG_SR_COLOR_MODE_ERR_INT_CLR_S 10 +/** JPEG_DCT_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear interrupt bit to sign that one dct calculation is finished. + */ +#define JPEG_DCT_DONE_INT_CLR (BIT(11)) +#define JPEG_DCT_DONE_INT_CLR_M (JPEG_DCT_DONE_INT_CLR_V << JPEG_DCT_DONE_INT_CLR_S) +#define JPEG_DCT_DONE_INT_CLR_V 0x00000001U +#define JPEG_DCT_DONE_INT_CLR_S 11 +/** JPEG_BS_LAST_BLOCK_EOF_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear interrupt bit to sign that the coding process for last block is finished. + */ +#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR (BIT(12)) +#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR_M (JPEG_BS_LAST_BLOCK_EOF_INT_CLR_V << JPEG_BS_LAST_BLOCK_EOF_INT_CLR_S) +#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR_V 0x00000001U +#define JPEG_BS_LAST_BLOCK_EOF_INT_CLR_S 12 +/** JPEG_SCAN_CHECK_NONE_ERR_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ +#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR (BIT(13)) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_M (JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_V << JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_S) +#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_V 0x00000001U +#define JPEG_SCAN_CHECK_NONE_ERR_INT_CLR_S 13 +/** JPEG_SCAN_CHECK_POS_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear interrupt bit to sign that SOS header marker position wrong when decoding. + */ +#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR (BIT(14)) +#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR_M (JPEG_SCAN_CHECK_POS_ERR_INT_CLR_V << JPEG_SCAN_CHECK_POS_ERR_INT_CLR_S) +#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR_V 0x00000001U +#define JPEG_SCAN_CHECK_POS_ERR_INT_CLR_S 14 +/** JPEG_UXP_DET_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ +#define JPEG_UXP_DET_INT_CLR (BIT(15)) +#define JPEG_UXP_DET_INT_CLR_M (JPEG_UXP_DET_INT_CLR_V << JPEG_UXP_DET_INT_CLR_S) +#define JPEG_UXP_DET_INT_CLR_V 0x00000001U +#define JPEG_UXP_DET_INT_CLR_S 15 +/** JPEG_EN_FRAME_EOF_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ +#define JPEG_EN_FRAME_EOF_ERR_INT_CLR (BIT(16)) +#define JPEG_EN_FRAME_EOF_ERR_INT_CLR_M (JPEG_EN_FRAME_EOF_ERR_INT_CLR_V << JPEG_EN_FRAME_EOF_ERR_INT_CLR_S) +#define JPEG_EN_FRAME_EOF_ERR_INT_CLR_V 0x00000001U +#define JPEG_EN_FRAME_EOF_ERR_INT_CLR_S 16 +/** JPEG_EN_FRAME_EOF_LACK_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ +#define JPEG_EN_FRAME_EOF_LACK_INT_CLR (BIT(17)) +#define JPEG_EN_FRAME_EOF_LACK_INT_CLR_M (JPEG_EN_FRAME_EOF_LACK_INT_CLR_V << JPEG_EN_FRAME_EOF_LACK_INT_CLR_S) +#define JPEG_EN_FRAME_EOF_LACK_INT_CLR_V 0x00000001U +#define JPEG_EN_FRAME_EOF_LACK_INT_CLR_S 17 +/** JPEG_DE_FRAME_EOF_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ +#define JPEG_DE_FRAME_EOF_ERR_INT_CLR (BIT(18)) +#define JPEG_DE_FRAME_EOF_ERR_INT_CLR_M (JPEG_DE_FRAME_EOF_ERR_INT_CLR_V << JPEG_DE_FRAME_EOF_ERR_INT_CLR_S) +#define JPEG_DE_FRAME_EOF_ERR_INT_CLR_V 0x00000001U +#define JPEG_DE_FRAME_EOF_ERR_INT_CLR_S 18 +/** JPEG_DE_FRAME_EOF_LACK_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ +#define JPEG_DE_FRAME_EOF_LACK_INT_CLR (BIT(19)) +#define JPEG_DE_FRAME_EOF_LACK_INT_CLR_M (JPEG_DE_FRAME_EOF_LACK_INT_CLR_V << JPEG_DE_FRAME_EOF_LACK_INT_CLR_S) +#define JPEG_DE_FRAME_EOF_LACK_INT_CLR_V 0x00000001U +#define JPEG_DE_FRAME_EOF_LACK_INT_CLR_S 19 +/** JPEG_SOS_UNMATCH_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ +#define JPEG_SOS_UNMATCH_ERR_INT_CLR (BIT(20)) +#define JPEG_SOS_UNMATCH_ERR_INT_CLR_M (JPEG_SOS_UNMATCH_ERR_INT_CLR_V << JPEG_SOS_UNMATCH_ERR_INT_CLR_S) +#define JPEG_SOS_UNMATCH_ERR_INT_CLR_V 0x00000001U +#define JPEG_SOS_UNMATCH_ERR_INT_CLR_S 20 +/** JPEG_MARKER_ERR_FST_SCAN_INT_CLR : WT; bitpos: [21]; default: 0; + * The clear interrupt bit to sign that the first scan has header marker error when + * decoding. + */ +#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR (BIT(21)) +#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR_M (JPEG_MARKER_ERR_FST_SCAN_INT_CLR_V << JPEG_MARKER_ERR_FST_SCAN_INT_CLR_S) +#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR_V 0x00000001U +#define JPEG_MARKER_ERR_FST_SCAN_INT_CLR_S 21 +/** JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR : WT; bitpos: [22]; default: 0; + * The clear interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR (BIT(22)) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_M (JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_V << JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_S) +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_V 0x00000001U +#define JPEG_MARKER_ERR_OTHER_SCAN_INT_CLR_S 22 +/** JPEG_UNDET_INT_CLR : WT; bitpos: [23]; default: 0; + * The clear interrupt bit to sign that JPEG format is not detected at the eof data of + * a packet when decoding. + */ +#define JPEG_UNDET_INT_CLR (BIT(23)) +#define JPEG_UNDET_INT_CLR_M (JPEG_UNDET_INT_CLR_V << JPEG_UNDET_INT_CLR_S) +#define JPEG_UNDET_INT_CLR_V 0x00000001U +#define JPEG_UNDET_INT_CLR_S 23 +/** JPEG_DECODE_TIMEOUT_INT_CLR : WT; bitpos: [24]; default: 0; + * The clear interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ +#define JPEG_DECODE_TIMEOUT_INT_CLR (BIT(24)) +#define JPEG_DECODE_TIMEOUT_INT_CLR_M (JPEG_DECODE_TIMEOUT_INT_CLR_V << JPEG_DECODE_TIMEOUT_INT_CLR_S) +#define JPEG_DECODE_TIMEOUT_INT_CLR_V 0x00000001U +#define JPEG_DECODE_TIMEOUT_INT_CLR_S 24 + +/** JPEG_STATUS0_REG register + * Trace and Debug registers + */ +#define JPEG_STATUS0_REG (DR_REG_JPEG_BASE + 0x48) +/** JPEG_BITSTREAM_EOF_VLD_CNT : RO; bitpos: [16:11]; default: 0; + * the valid bit count for last bitstream + */ +#define JPEG_BITSTREAM_EOF_VLD_CNT 0x0000003FU +#define JPEG_BITSTREAM_EOF_VLD_CNT_M (JPEG_BITSTREAM_EOF_VLD_CNT_V << JPEG_BITSTREAM_EOF_VLD_CNT_S) +#define JPEG_BITSTREAM_EOF_VLD_CNT_V 0x0000003FU +#define JPEG_BITSTREAM_EOF_VLD_CNT_S 11 +/** JPEG_DCTOUT_ZZSCAN_ADDR : RO; bitpos: [22:17]; default: 0; + * the zig-zag read addr from dctout_ram + */ +#define JPEG_DCTOUT_ZZSCAN_ADDR 0x0000003FU +#define JPEG_DCTOUT_ZZSCAN_ADDR_M (JPEG_DCTOUT_ZZSCAN_ADDR_V << JPEG_DCTOUT_ZZSCAN_ADDR_S) +#define JPEG_DCTOUT_ZZSCAN_ADDR_V 0x0000003FU +#define JPEG_DCTOUT_ZZSCAN_ADDR_S 17 +/** JPEG_QNRVAL_ZZSCAN_ADDR : RO; bitpos: [28:23]; default: 0; + * the zig-zag read addr from qnrval_ram + */ +#define JPEG_QNRVAL_ZZSCAN_ADDR 0x0000003FU +#define JPEG_QNRVAL_ZZSCAN_ADDR_M (JPEG_QNRVAL_ZZSCAN_ADDR_V << JPEG_QNRVAL_ZZSCAN_ADDR_S) +#define JPEG_QNRVAL_ZZSCAN_ADDR_V 0x0000003FU +#define JPEG_QNRVAL_ZZSCAN_ADDR_S 23 +/** JPEG_REG_STATE_YUV : RO; bitpos: [31:29]; default: 0; + * the state of jpeg fsm + */ +#define JPEG_REG_STATE_YUV 0x00000007U +#define JPEG_REG_STATE_YUV_M (JPEG_REG_STATE_YUV_V << JPEG_REG_STATE_YUV_S) +#define JPEG_REG_STATE_YUV_V 0x00000007U +#define JPEG_REG_STATE_YUV_S 29 + +/** JPEG_STATUS2_REG register + * Trace and Debug registers + */ +#define JPEG_STATUS2_REG (DR_REG_JPEG_BASE + 0x4c) +/** JPEG_SOURCE_PIXEL : RO; bitpos: [23:0]; default: 0; + * source pixels fetched from dma + */ +#define JPEG_SOURCE_PIXEL 0x00FFFFFFU +#define JPEG_SOURCE_PIXEL_M (JPEG_SOURCE_PIXEL_V << JPEG_SOURCE_PIXEL_S) +#define JPEG_SOURCE_PIXEL_V 0x00FFFFFFU +#define JPEG_SOURCE_PIXEL_S 0 +/** JPEG_LAST_BLOCK : RO; bitpos: [24]; default: 0; + * indicate the encoding process for the last mcu of the picture + */ +#define JPEG_LAST_BLOCK (BIT(24)) +#define JPEG_LAST_BLOCK_M (JPEG_LAST_BLOCK_V << JPEG_LAST_BLOCK_S) +#define JPEG_LAST_BLOCK_V 0x00000001U +#define JPEG_LAST_BLOCK_S 24 +/** JPEG_LAST_MCU : RO; bitpos: [25]; default: 0; + * indicate the encoding process for the last block of the picture + */ +#define JPEG_LAST_MCU (BIT(25)) +#define JPEG_LAST_MCU_M (JPEG_LAST_MCU_V << JPEG_LAST_MCU_S) +#define JPEG_LAST_MCU_V 0x00000001U +#define JPEG_LAST_MCU_S 25 +/** JPEG_LAST_DC : RO; bitpos: [26]; default: 0; + * indicate the encoding process is at the header of the last block of the picture + */ +#define JPEG_LAST_DC (BIT(26)) +#define JPEG_LAST_DC_M (JPEG_LAST_DC_V << JPEG_LAST_DC_S) +#define JPEG_LAST_DC_V 0x00000001U +#define JPEG_LAST_DC_S 26 +/** JPEG_PACKFIFO_READY : RO; bitpos: [27]; default: 1; + * the jpeg pack_fifo ready signal, high active + */ +#define JPEG_PACKFIFO_READY (BIT(27)) +#define JPEG_PACKFIFO_READY_M (JPEG_PACKFIFO_READY_V << JPEG_PACKFIFO_READY_S) +#define JPEG_PACKFIFO_READY_V 0x00000001U +#define JPEG_PACKFIFO_READY_S 27 + +/** JPEG_STATUS3_REG register + * Trace and Debug registers + */ +#define JPEG_STATUS3_REG (DR_REG_JPEG_BASE + 0x50) +/** JPEG_YO : RO; bitpos: [8:0]; default: 0; + * component y transferred from rgb input + */ +#define JPEG_YO 0x000001FFU +#define JPEG_YO_M (JPEG_YO_V << JPEG_YO_S) +#define JPEG_YO_V 0x000001FFU +#define JPEG_YO_S 0 +/** JPEG_Y_READY : RO; bitpos: [9]; default: 0; + * component y valid signal, high active + */ +#define JPEG_Y_READY (BIT(9)) +#define JPEG_Y_READY_M (JPEG_Y_READY_V << JPEG_Y_READY_S) +#define JPEG_Y_READY_V 0x00000001U +#define JPEG_Y_READY_S 9 +/** JPEG_CBO : RO; bitpos: [18:10]; default: 0; + * component cb transferred from rgb input + */ +#define JPEG_CBO 0x000001FFU +#define JPEG_CBO_M (JPEG_CBO_V << JPEG_CBO_S) +#define JPEG_CBO_V 0x000001FFU +#define JPEG_CBO_S 10 +/** JPEG_CB_READY : RO; bitpos: [19]; default: 0; + * component cb valid signal, high active + */ +#define JPEG_CB_READY (BIT(19)) +#define JPEG_CB_READY_M (JPEG_CB_READY_V << JPEG_CB_READY_S) +#define JPEG_CB_READY_V 0x00000001U +#define JPEG_CB_READY_S 19 +/** JPEG_CRO : RO; bitpos: [28:20]; default: 0; + * component cr transferred from rgb input + */ +#define JPEG_CRO 0x000001FFU +#define JPEG_CRO_M (JPEG_CRO_V << JPEG_CRO_S) +#define JPEG_CRO_V 0x000001FFU +#define JPEG_CRO_S 20 +/** JPEG_CR_READY : RO; bitpos: [29]; default: 0; + * component cr valid signal, high active + */ +#define JPEG_CR_READY (BIT(29)) +#define JPEG_CR_READY_M (JPEG_CR_READY_V << JPEG_CR_READY_S) +#define JPEG_CR_READY_V 0x00000001U +#define JPEG_CR_READY_S 29 + +/** JPEG_STATUS4_REG register + * Trace and Debug registers + */ +#define JPEG_STATUS4_REG (DR_REG_JPEG_BASE + 0x54) +/** JPEG_HFM_BITSTREAM : RO; bitpos: [31:0]; default: 0; + * the hufman bitstream during encoding process + */ +#define JPEG_HFM_BITSTREAM 0xFFFFFFFFU +#define JPEG_HFM_BITSTREAM_M (JPEG_HFM_BITSTREAM_V << JPEG_HFM_BITSTREAM_S) +#define JPEG_HFM_BITSTREAM_V 0xFFFFFFFFU +#define JPEG_HFM_BITSTREAM_S 0 + +/** JPEG_DHT_TOTLEN_DC0_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_TOTLEN_DC0_REG (DR_REG_JPEG_BASE + 0x58) +/** JPEG_DHT_TOTLEN_DC0 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of dc0 table + */ +#define JPEG_DHT_TOTLEN_DC0 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_DC0_M (JPEG_DHT_TOTLEN_DC0_V << JPEG_DHT_TOTLEN_DC0_S) +#define JPEG_DHT_TOTLEN_DC0_V 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_DC0_S 0 + +/** JPEG_DHT_VAl_DC0_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_VAL_DC0_REG (DR_REG_JPEG_BASE + 0x5c) +/** JPEG_DHT_VAL_DC0 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of dc0 table + */ +#define JPEG_DHT_VAL_DC0 0xFFFFFFFFU +#define JPEG_DHT_VAL_DC0_M (JPEG_DHT_VAL_DC0_V << JPEG_DHT_VAL_DC0_S) +#define JPEG_DHT_VAL_DC0_V 0xFFFFFFFFU +#define JPEG_DHT_VAL_DC0_S 0 + +/** JPEG_DHT_TOTLEN_AC0_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_TOTLEN_AC0_REG (DR_REG_JPEG_BASE + 0x60) +/** JPEG_DHT_TOTLEN_AC0 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of ac0 table + */ +#define JPEG_DHT_TOTLEN_AC0 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_AC0_M (JPEG_DHT_TOTLEN_AC0_V << JPEG_DHT_TOTLEN_AC0_S) +#define JPEG_DHT_TOTLEN_AC0_V 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_AC0_S 0 + +/** JPEG_DHT_VAl_AC0_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_VAL_AC0_REG (DR_REG_JPEG_BASE + 0x64) +/** JPEG_DHT_VAL_AC0 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of ac0 table + */ +#define JPEG_DHT_VAL_AC0 0xFFFFFFFFU +#define JPEG_DHT_VAL_AC0_M (JPEG_DHT_VAL_AC0_V << JPEG_DHT_VAL_AC0_S) +#define JPEG_DHT_VAL_AC0_V 0xFFFFFFFFU +#define JPEG_DHT_VAL_AC0_S 0 + +/** JPEG_DHT_TOTLEN_DC1_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_TOTLEN_DC1_REG (DR_REG_JPEG_BASE + 0x68) +/** JPEG_DHT_TOTLEN_DC1 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of dc1 table + */ +#define JPEG_DHT_TOTLEN_DC1 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_DC1_M (JPEG_DHT_TOTLEN_DC1_V << JPEG_DHT_TOTLEN_DC1_S) +#define JPEG_DHT_TOTLEN_DC1_V 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_DC1_S 0 + +/** JPEG_DHT_VAl_DC1_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_VAL_DC1_REG (DR_REG_JPEG_BASE + 0x6c) +/** JPEG_DHT_VAL_DC1 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of dc1 table + */ +#define JPEG_DHT_VAL_DC1 0xFFFFFFFFU +#define JPEG_DHT_VAL_DC1_M (JPEG_DHT_VAL_DC1_V << JPEG_DHT_VAL_DC1_S) +#define JPEG_DHT_VAL_DC1_V 0xFFFFFFFFU +#define JPEG_DHT_VAL_DC1_S 0 + +/** JPEG_DHT_TOTLEN_AC1_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_TOTLEN_AC1_REG (DR_REG_JPEG_BASE + 0x70) +/** JPEG_DHT_TOTLEN_AC1 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of ac1 table + */ +#define JPEG_DHT_TOTLEN_AC1 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_AC1_M (JPEG_DHT_TOTLEN_AC1_V << JPEG_DHT_TOTLEN_AC1_S) +#define JPEG_DHT_TOTLEN_AC1_V 0xFFFFFFFFU +#define JPEG_DHT_TOTLEN_AC1_S 0 + +/** JPEG_DHT_VAl_AC1_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_VAL_AC1_REG (DR_REG_JPEG_BASE + 0x74) +/** JPEG_DHT_VAL_AC1 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of ac1 table + */ +#define JPEG_DHT_VAL_AC1 0xFFFFFFFFU +#define JPEG_DHT_VAL_AC1_M (JPEG_DHT_VAL_AC1_V << JPEG_DHT_VAL_AC1_S) +#define JPEG_DHT_VAL_AC1_V 0xFFFFFFFFU +#define JPEG_DHT_VAL_AC1_S 0 + +/** JPEG_DHT_CODEMIN_DC0_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_CODEMIN_DC0_REG (DR_REG_JPEG_BASE + 0x78) +/** JPEG_DHT_CODEMIN_DC0 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of dc0 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ +#define JPEG_DHT_CODEMIN_DC0 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_DC0_M (JPEG_DHT_CODEMIN_DC0_V << JPEG_DHT_CODEMIN_DC0_S) +#define JPEG_DHT_CODEMIN_DC0_V 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_DC0_S 0 + +/** JPEG_DHT_CODEMIN_AC0_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_CODEMIN_AC0_REG (DR_REG_JPEG_BASE + 0x7c) +/** JPEG_DHT_CODEMIN_AC0 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of ac0 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ +#define JPEG_DHT_CODEMIN_AC0 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_AC0_M (JPEG_DHT_CODEMIN_AC0_V << JPEG_DHT_CODEMIN_AC0_S) +#define JPEG_DHT_CODEMIN_AC0_V 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_AC0_S 0 + +/** JPEG_DHT_CODEMIN_DC1_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_CODEMIN_DC1_REG (DR_REG_JPEG_BASE + 0x80) +/** JPEG_DHT_CODEMIN_DC1 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of dc1 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ +#define JPEG_DHT_CODEMIN_DC1 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_DC1_M (JPEG_DHT_CODEMIN_DC1_V << JPEG_DHT_CODEMIN_DC1_S) +#define JPEG_DHT_CODEMIN_DC1_V 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_DC1_S 0 + +/** JPEG_DHT_CODEMIN_AC1_REG register + * Trace and Debug registers + */ +#define JPEG_DHT_CODEMIN_AC1_REG (DR_REG_JPEG_BASE + 0x84) +/** JPEG_DHT_CODEMIN_AC1 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of ac1 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ +#define JPEG_DHT_CODEMIN_AC1 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_AC1_M (JPEG_DHT_CODEMIN_AC1_V << JPEG_DHT_CODEMIN_AC1_S) +#define JPEG_DHT_CODEMIN_AC1_V 0xFFFFFFFFU +#define JPEG_DHT_CODEMIN_AC1_S 0 + +/** JPEG_DECODER_STATUS0_REG register + * Trace and Debug registers + */ +#define JPEG_DECODER_STATUS0_REG (DR_REG_JPEG_BASE + 0x88) +/** JPEG_DECODE_BYTE_CNT : RO; bitpos: [25:0]; default: 0; + * Reserved + */ +#define JPEG_DECODE_BYTE_CNT 0x03FFFFFFU +#define JPEG_DECODE_BYTE_CNT_M (JPEG_DECODE_BYTE_CNT_V << JPEG_DECODE_BYTE_CNT_S) +#define JPEG_DECODE_BYTE_CNT_V 0x03FFFFFFU +#define JPEG_DECODE_BYTE_CNT_S 0 +/** JPEG_HEADER_DEC_ST : RO; bitpos: [29:26]; default: 0; + * Reserved + */ +#define JPEG_HEADER_DEC_ST 0x0000000FU +#define JPEG_HEADER_DEC_ST_M (JPEG_HEADER_DEC_ST_V << JPEG_HEADER_DEC_ST_S) +#define JPEG_HEADER_DEC_ST_V 0x0000000FU +#define JPEG_HEADER_DEC_ST_S 26 +/** JPEG_DECODE_SAMPLE_SEL : RO; bitpos: [31:30]; default: 0; + * Reserved + */ +#define JPEG_DECODE_SAMPLE_SEL 0x00000003U +#define JPEG_DECODE_SAMPLE_SEL_M (JPEG_DECODE_SAMPLE_SEL_V << JPEG_DECODE_SAMPLE_SEL_S) +#define JPEG_DECODE_SAMPLE_SEL_V 0x00000003U +#define JPEG_DECODE_SAMPLE_SEL_S 30 + +/** JPEG_DECODER_STATUS1_REG register + * Trace and Debug registers + */ +#define JPEG_DECODER_STATUS1_REG (DR_REG_JPEG_BASE + 0x8c) +/** JPEG_ENCODE_DATA : RO; bitpos: [15:0]; default: 0; + * Reserved + */ +#define JPEG_ENCODE_DATA 0x0000FFFFU +#define JPEG_ENCODE_DATA_M (JPEG_ENCODE_DATA_V << JPEG_ENCODE_DATA_S) +#define JPEG_ENCODE_DATA_V 0x0000FFFFU +#define JPEG_ENCODE_DATA_S 0 +/** JPEG_COUNT_Q : RO; bitpos: [22:16]; default: 0; + * Reserved + */ +#define JPEG_COUNT_Q 0x0000007FU +#define JPEG_COUNT_Q_M (JPEG_COUNT_Q_V << JPEG_COUNT_Q_S) +#define JPEG_COUNT_Q_V 0x0000007FU +#define JPEG_COUNT_Q_S 16 +/** JPEG_MCU_FSM_READY : RO; bitpos: [23]; default: 0; + * Reserved + */ +#define JPEG_MCU_FSM_READY (BIT(23)) +#define JPEG_MCU_FSM_READY_M (JPEG_MCU_FSM_READY_V << JPEG_MCU_FSM_READY_S) +#define JPEG_MCU_FSM_READY_V 0x00000001U +#define JPEG_MCU_FSM_READY_S 23 +/** JPEG_DECODE_DATA : RO; bitpos: [31:24]; default: 0; + * Reserved + */ +#define JPEG_DECODE_DATA 0x000000FFU +#define JPEG_DECODE_DATA_M (JPEG_DECODE_DATA_V << JPEG_DECODE_DATA_S) +#define JPEG_DECODE_DATA_V 0x000000FFU +#define JPEG_DECODE_DATA_S 24 + +/** JPEG_DECODER_STATUS2_REG register + * Trace and Debug registers + */ +#define JPEG_DECODER_STATUS2_REG (DR_REG_JPEG_BASE + 0x90) +/** JPEG_COMP_BLOCK_NUM : RO; bitpos: [25:0]; default: 0; + * Reserved + */ +#define JPEG_COMP_BLOCK_NUM 0x03FFFFFFU +#define JPEG_COMP_BLOCK_NUM_M (JPEG_COMP_BLOCK_NUM_V << JPEG_COMP_BLOCK_NUM_S) +#define JPEG_COMP_BLOCK_NUM_V 0x03FFFFFFU +#define JPEG_COMP_BLOCK_NUM_S 0 +/** JPEG_SCAN_NUM : RO; bitpos: [28:26]; default: 0; + * Reserved + */ +#define JPEG_SCAN_NUM 0x00000007U +#define JPEG_SCAN_NUM_M (JPEG_SCAN_NUM_V << JPEG_SCAN_NUM_S) +#define JPEG_SCAN_NUM_V 0x00000007U +#define JPEG_SCAN_NUM_S 26 +/** JPEG_RST_CHECK_WAIT : RO; bitpos: [29]; default: 0; + * Reserved + */ +#define JPEG_RST_CHECK_WAIT (BIT(29)) +#define JPEG_RST_CHECK_WAIT_M (JPEG_RST_CHECK_WAIT_V << JPEG_RST_CHECK_WAIT_S) +#define JPEG_RST_CHECK_WAIT_V 0x00000001U +#define JPEG_RST_CHECK_WAIT_S 29 +/** JPEG_SCAN_CHECK_WAIT : RO; bitpos: [30]; default: 0; + * Reserved + */ +#define JPEG_SCAN_CHECK_WAIT (BIT(30)) +#define JPEG_SCAN_CHECK_WAIT_M (JPEG_SCAN_CHECK_WAIT_V << JPEG_SCAN_CHECK_WAIT_S) +#define JPEG_SCAN_CHECK_WAIT_V 0x00000001U +#define JPEG_SCAN_CHECK_WAIT_S 30 +/** JPEG_MCU_IN_PROC : RO; bitpos: [31]; default: 0; + * Reserved + */ +#define JPEG_MCU_IN_PROC (BIT(31)) +#define JPEG_MCU_IN_PROC_M (JPEG_MCU_IN_PROC_V << JPEG_MCU_IN_PROC_S) +#define JPEG_MCU_IN_PROC_V 0x00000001U +#define JPEG_MCU_IN_PROC_S 31 + +/** JPEG_DECODER_STATUS3_REG register + * Trace and Debug registers + */ +#define JPEG_DECODER_STATUS3_REG (DR_REG_JPEG_BASE + 0x94) +/** JPEG_LOOKUP_DATA : RO; bitpos: [31:0]; default: 0; + * Reserved + */ +#define JPEG_LOOKUP_DATA 0xFFFFFFFFU +#define JPEG_LOOKUP_DATA_M (JPEG_LOOKUP_DATA_V << JPEG_LOOKUP_DATA_S) +#define JPEG_LOOKUP_DATA_V 0xFFFFFFFFU +#define JPEG_LOOKUP_DATA_S 0 + +/** JPEG_DECODER_STATUS4_REG register + * Trace and Debug registers + */ +#define JPEG_DECODER_STATUS4_REG (DR_REG_JPEG_BASE + 0x98) +/** JPEG_BLOCK_EOF_CNT : RO; bitpos: [25:0]; default: 0; + * Reserved + */ +#define JPEG_BLOCK_EOF_CNT 0x03FFFFFFU +#define JPEG_BLOCK_EOF_CNT_M (JPEG_BLOCK_EOF_CNT_V << JPEG_BLOCK_EOF_CNT_S) +#define JPEG_BLOCK_EOF_CNT_V 0x03FFFFFFU +#define JPEG_BLOCK_EOF_CNT_S 0 +/** JPEG_DEZIGZAG_READY : RO; bitpos: [26]; default: 0; + * Reserved + */ +#define JPEG_DEZIGZAG_READY (BIT(26)) +#define JPEG_DEZIGZAG_READY_M (JPEG_DEZIGZAG_READY_V << JPEG_DEZIGZAG_READY_S) +#define JPEG_DEZIGZAG_READY_V 0x00000001U +#define JPEG_DEZIGZAG_READY_S 26 +/** JPEG_DE_FRAME_EOF_CHECK : RO; bitpos: [27]; default: 0; + * Reserved + */ +#define JPEG_DE_FRAME_EOF_CHECK (BIT(27)) +#define JPEG_DE_FRAME_EOF_CHECK_M (JPEG_DE_FRAME_EOF_CHECK_V << JPEG_DE_FRAME_EOF_CHECK_S) +#define JPEG_DE_FRAME_EOF_CHECK_V 0x00000001U +#define JPEG_DE_FRAME_EOF_CHECK_S 27 +/** JPEG_DE_DMA2D_IN_PUSH : RO; bitpos: [28]; default: 0; + * Reserved + */ +#define JPEG_DE_DMA2D_IN_PUSH (BIT(28)) +#define JPEG_DE_DMA2D_IN_PUSH_M (JPEG_DE_DMA2D_IN_PUSH_V << JPEG_DE_DMA2D_IN_PUSH_S) +#define JPEG_DE_DMA2D_IN_PUSH_V 0x00000001U +#define JPEG_DE_DMA2D_IN_PUSH_S 28 + +/** JPEG_DECODER_STATUS5_REG register + * Trace and Debug registers + */ +#define JPEG_DECODER_STATUS5_REG (DR_REG_JPEG_BASE + 0x9c) +/** JPEG_IDCT_HFM_DATA : RO; bitpos: [15:0]; default: 0; + * Reserved + */ +#define JPEG_IDCT_HFM_DATA 0x0000FFFFU +#define JPEG_IDCT_HFM_DATA_M (JPEG_IDCT_HFM_DATA_V << JPEG_IDCT_HFM_DATA_S) +#define JPEG_IDCT_HFM_DATA_V 0x0000FFFFU +#define JPEG_IDCT_HFM_DATA_S 0 +/** JPEG_NS0 : RO; bitpos: [18:16]; default: 0; + * Reserved + */ +#define JPEG_NS0 0x00000007U +#define JPEG_NS0_M (JPEG_NS0_V << JPEG_NS0_S) +#define JPEG_NS0_V 0x00000007U +#define JPEG_NS0_S 16 +/** JPEG_NS1 : RO; bitpos: [21:19]; default: 0; + * Reserved + */ +#define JPEG_NS1 0x00000007U +#define JPEG_NS1_M (JPEG_NS1_V << JPEG_NS1_S) +#define JPEG_NS1_V 0x00000007U +#define JPEG_NS1_S 19 +/** JPEG_NS2 : RO; bitpos: [24:22]; default: 0; + * Reserved + */ +#define JPEG_NS2 0x00000007U +#define JPEG_NS2_M (JPEG_NS2_V << JPEG_NS2_S) +#define JPEG_NS2_V 0x00000007U +#define JPEG_NS2_S 22 +/** JPEG_NS3 : RO; bitpos: [27:25]; default: 0; + * Reserved + */ +#define JPEG_NS3 0x00000007U +#define JPEG_NS3_M (JPEG_NS3_V << JPEG_NS3_S) +#define JPEG_NS3_V 0x00000007U +#define JPEG_NS3_S 25 +/** JPEG_DATA_LAST_O : RO; bitpos: [28]; default: 0; + * Reserved + */ +#define JPEG_DATA_LAST_O (BIT(28)) +#define JPEG_DATA_LAST_O_M (JPEG_DATA_LAST_O_V << JPEG_DATA_LAST_O_S) +#define JPEG_DATA_LAST_O_V 0x00000001U +#define JPEG_DATA_LAST_O_S 28 +/** JPEG_RDN_RESULT : RO; bitpos: [29]; default: 0; + * redundant registers for jpeg + */ +#define JPEG_RDN_RESULT (BIT(29)) +#define JPEG_RDN_RESULT_M (JPEG_RDN_RESULT_V << JPEG_RDN_RESULT_S) +#define JPEG_RDN_RESULT_V 0x00000001U +#define JPEG_RDN_RESULT_S 29 +/** JPEG_RDN_ENA : R/W; bitpos: [30]; default: 0; + * redundant control registers for jpeg + */ +#define JPEG_RDN_ENA (BIT(30)) +#define JPEG_RDN_ENA_M (JPEG_RDN_ENA_V << JPEG_RDN_ENA_S) +#define JPEG_RDN_ENA_V 0x00000001U +#define JPEG_RDN_ENA_S 30 + +/** JPEG_STATUS5_REG register + * Trace and Debug registers + */ +#define JPEG_STATUS5_REG (DR_REG_JPEG_BASE + 0xa0) +/** JPEG_PIC_BLOCK_NUM : RO; bitpos: [23:0]; default: 0; + * Reserved + */ +#define JPEG_PIC_BLOCK_NUM 0x00FFFFFFU +#define JPEG_PIC_BLOCK_NUM_M (JPEG_PIC_BLOCK_NUM_V << JPEG_PIC_BLOCK_NUM_S) +#define JPEG_PIC_BLOCK_NUM_V 0x00FFFFFFU +#define JPEG_PIC_BLOCK_NUM_S 0 + +/** JPEG_ECO_LOW_REG register + * Trace and Debug registers + */ +#define JPEG_ECO_LOW_REG (DR_REG_JPEG_BASE + 0xa4) +/** JPEG_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * redundant registers for jpeg + */ +#define JPEG_RDN_ECO_LOW 0xFFFFFFFFU +#define JPEG_RDN_ECO_LOW_M (JPEG_RDN_ECO_LOW_V << JPEG_RDN_ECO_LOW_S) +#define JPEG_RDN_ECO_LOW_V 0xFFFFFFFFU +#define JPEG_RDN_ECO_LOW_S 0 + +/** JPEG_ECO_HIGH_REG register + * Trace and Debug registers + */ +#define JPEG_ECO_HIGH_REG (DR_REG_JPEG_BASE + 0xa8) +/** JPEG_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * redundant registers for jpeg + */ +#define JPEG_RDN_ECO_HIGH 0xFFFFFFFFU +#define JPEG_RDN_ECO_HIGH_M (JPEG_RDN_ECO_HIGH_V << JPEG_RDN_ECO_HIGH_S) +#define JPEG_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define JPEG_RDN_ECO_HIGH_S 0 + +/** JPEG_SYS_REG register + * Trace and Debug registers + */ +#define JPEG_SYS_REG (DR_REG_JPEG_BASE + 0xf8) +/** JPEG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Reserved + */ +#define JPEG_CLK_EN (BIT(31)) +#define JPEG_CLK_EN_M (JPEG_CLK_EN_V << JPEG_CLK_EN_S) +#define JPEG_CLK_EN_V 0x00000001U +#define JPEG_CLK_EN_S 31 + +/** JPEG_VERSION_REG register + * Trace and Debug registers + */ +#define JPEG_VERSION_REG (DR_REG_JPEG_BASE + 0xfc) +/** JPEG_JPEG_VER : R/W; bitpos: [27:0]; default: 37823072; + * Reserved + */ +#define JPEG_JPEG_VER 0x0FFFFFFFU +#define JPEG_JPEG_VER_M (JPEG_JPEG_VER_V << JPEG_JPEG_VER_S) +#define JPEG_JPEG_VER_V 0x0FFFFFFFU +#define JPEG_JPEG_VER_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/jpeg_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/jpeg_struct.h new file mode 100644 index 0000000000..854c04e63b --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/jpeg_struct.h @@ -0,0 +1,1460 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of config register + * Control and configuration registers + */ +typedef union { + struct { + /** fsm_rst : WT; bitpos: [0]; default: 0; + * fsm reset + */ + uint32_t fsm_rst:1; + /** jpeg_start : WT; bitpos: [1]; default: 0; + * start to compress a new pic(in dma reg mode) + */ + uint32_t jpeg_start:1; + /** qnr_presition : R/W; bitpos: [2]; default: 0; + * 0:8bit qnr,1:12bit qnr(TBD) + */ + uint32_t qnr_presition:1; + /** ff_check_en : R/W; bitpos: [3]; default: 1; + * enable whether to add "00" after "ff" + */ + uint32_t ff_check_en:1; + /** sample_sel : R/W; bitpos: [5:4]; default: 1; + * 0:yuv444,1:yuv422, 2:yuv420 + */ + uint32_t sample_sel:2; + /** dma_linklist_mode : RO; bitpos: [6]; default: 1; + * 1:use linklist to configure dma + */ + uint32_t dma_linklist_mode:1; + /** debug_direct_out_en : R/W; bitpos: [7]; default: 0; + * 0:normal mode,1:debug mode for direct output from input + */ + uint32_t debug_direct_out_en:1; + /** qnr_fifo_en : R/W; bitpos: [8]; default: 1; + * 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram + */ + uint32_t qnr_fifo_en:1; + /** lqnr_tbl_sel : R/W; bitpos: [10:9]; default: 0; + * choose luminance quntization table id(TBD) + */ + uint32_t lqnr_tbl_sel:2; + /** cqnr_tbl_sel : R/W; bitpos: [12:11]; default: 1; + * choose chrominance quntization table id (TBD) + */ + uint32_t cqnr_tbl_sel:2; + /** color_space : R/W; bitpos: [14:13]; default: 0; + * configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray + */ + uint32_t color_space:2; + /** dht_fifo_en : R/W; bitpos: [15]; default: 1; + * 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to + * write dht len_total/codemin/value table. Reading dht len_total/codemin/value table + * only has nonfifo way + */ + uint32_t dht_fifo_en:1; + /** mem_clk_force_on : R/W; bitpos: [16]; default: 0; + * force memory's clock enabled + */ + uint32_t mem_clk_force_on:1; + /** jfif_ver : R/W; bitpos: [22:17]; default: 32; + * decode pause period to trigger decode_timeout int, the timeout periods =2 power + * (reg_decode_timeout_thres) -1 + */ + uint32_t jfif_ver:6; + /** decode_timeout_task_sel : R/W; bitpos: [23]; default: 0; + * 0: software use reset to abort decode process ,1: decoder abort decode process by + * itself + */ + uint32_t decode_timeout_task_sel:1; + /** soft_rst : R/W; bitpos: [24]; default: 0; + * when set to 1, soft reset JPEG module except jpeg_reg module + */ + uint32_t soft_rst:1; + /** fifo_rst : R/W; bitpos: [25]; default: 0; + * fifo reset + */ + uint32_t fifo_rst:1; + /** pixel_rev : R/W; bitpos: [26]; default: 0; + * reverse the source color pixel + */ + uint32_t pixel_rev:1; + /** tailer_en : R/W; bitpos: [27]; default: 0; + * set this bit to add EOI of "0xffd9" at the end of bitstream + */ + uint32_t tailer_en:1; + /** pause_en : R/W; bitpos: [28]; default: 0; + * set this bit to pause jpeg encoding + */ + uint32_t pause_en:1; + /** mem_force_pd : R/W; bitpos: [29]; default: 0; + * 0: no operation,1:force jpeg memory to power down + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [30]; default: 0; + * 0: no operation,1:force jpeg memory to power up + */ + uint32_t mem_force_pu:1; + /** mode : R/W; bitpos: [31]; default: 0; + * 0:encoder mode, 1: decoder mode + */ + uint32_t mode:1; + }; + uint32_t val; +} jpeg_config_reg_t; + +/** Type of dqt_info register + * Control and configuration registers + */ +typedef union { + struct { + /** t0_dqt_info : R/W; bitpos: [7:0]; default: 0; + * Configure dqt table0's quantization coefficient precision in bit[7:4], configure + * dqt table0's table id in bit[3:0] + */ + uint32_t t0_dqt_info:8; + /** t1_dqt_info : R/W; bitpos: [15:8]; default: 1; + * Configure dqt table1's quantization coefficient precision in bit[7:4], configure + * dqt table1's table id in bit[3:0] + */ + uint32_t t1_dqt_info:8; + /** t2_dqt_info : R/W; bitpos: [23:16]; default: 2; + * Configure dqt table2's quantization coefficient precision in bit[7:4], configure + * dqt table2's table id in bit[3:0] + */ + uint32_t t2_dqt_info:8; + /** t3_dqt_info : R/W; bitpos: [31:24]; default: 3; + * Configure dqt table3's quantization coefficient precision in bit[7:4], configure + * dqt table3's table id in bit[3:0] + */ + uint32_t t3_dqt_info:8; + }; + uint32_t val; +} jpeg_dqt_info_reg_t; + +/** Type of pic_size register + * Control and configuration registers + */ +typedef union { + struct { + /** va : R/W; bitpos: [15:0]; default: 480; + * configure picture's height. when encode, the max configurable bits is 14, when + * decode, the max configurable bits is 16 + */ + uint32_t va:16; + /** ha : R/W; bitpos: [31:16]; default: 640; + * configure picture's width. when encode, the max configurable bits is 14, when + * decode, the max configurable bits is 16 + */ + uint32_t ha:16; + }; + uint32_t val; +} jpeg_pic_size_reg_t; + +/** Type of t0qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t0_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t0 table + */ + uint32_t t0_qnr_val:32; + }; + uint32_t val; +} jpeg_t0qnr_reg_t; + +/** Type of t1qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** chrominance_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t1 table + */ + uint32_t chrominance_qnr_val:32; + }; + uint32_t val; +} jpeg_t1qnr_reg_t; + +/** Type of t2qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t2_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t2 table + */ + uint32_t t2_qnr_val:32; + }; + uint32_t val; +} jpeg_t2qnr_reg_t; + +/** Type of t3qnr register + * Control and configuration registers + */ +typedef union { + struct { + /** t3_qnr_val : HRO; bitpos: [31:0]; default: 0; + * write this reg to configure 64 quantization coefficient in t3 table + */ + uint32_t t3_qnr_val:32; + }; + uint32_t val; +} jpeg_t3qnr_reg_t; + +/** Type of decode_conf register + * Control and configuration registers + */ +typedef union { + struct { + /** restart_interval : R/W; bitpos: [15:0]; default: 0; + * configure restart interval in DRI marker when decode + */ + uint32_t restart_interval:16; + /** component_num : R/W; bitpos: [23:16]; default: 3; + * configure number of components in frame when decode + */ + uint32_t component_num:8; + /** sw_dht_en : RO; bitpos: [24]; default: 1; + * software decode dht table enable + */ + uint32_t sw_dht_en:1; + /** sos_check_byte_num : R/W; bitpos: [26:25]; default: 3; + * Configure the byte number to check next sos marker in the multi-scan picture after + * one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + */ + uint32_t sos_check_byte_num:2; + /** rst_check_byte_num : R/W; bitpos: [28:27]; default: 3; + * Configure the byte number to check next rst marker after one rst interval is + * decoded down. The real check number is reg_rst_check_byte_num+1 + */ + uint32_t rst_check_byte_num:2; + /** multi_scan_err_check : R/W; bitpos: [29]; default: 0; + * reserved for decoder + */ + uint32_t multi_scan_err_check:1; + /** dezigzag_ready_ctl : R/W; bitpos: [30]; default: 1; + * reserved for decoder + */ + uint32_t dezigzag_ready_ctl:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} jpeg_decode_conf_reg_t; + +/** Type of c0 register + * Control and configuration registers + */ +typedef union { + struct { + /** c0_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c0 quntization table id (TBD) + */ + uint32_t c0_dqt_tbl_sel:8; + /** c0_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c0 + */ + uint32_t c0_y_factor:4; + /** c0_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c0 + */ + uint32_t c0_x_factor:4; + /** c0_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c0 + */ + uint32_t c0_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c0_reg_t; + +/** Type of c1 register + * Control and configuration registers + */ +typedef union { + struct { + /** c1_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c1 quntization table id (TBD) + */ + uint32_t c1_dqt_tbl_sel:8; + /** c1_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c1 + */ + uint32_t c1_y_factor:4; + /** c1_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c1 + */ + uint32_t c1_x_factor:4; + /** c1_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c1 + */ + uint32_t c1_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c1_reg_t; + +/** Type of c2 register + * Control and configuration registers + */ +typedef union { + struct { + /** c2_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c2 quntization table id (TBD) + */ + uint32_t c2_dqt_tbl_sel:8; + /** c2_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c2 + */ + uint32_t c2_y_factor:4; + /** c2_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c2 + */ + uint32_t c2_x_factor:4; + /** c2_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c2 + */ + uint32_t c2_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c2_reg_t; + +/** Type of c3 register + * Control and configuration registers + */ +typedef union { + struct { + /** c3_dqt_tbl_sel : R/W; bitpos: [7:0]; default: 0; + * choose c3 quntization table id (TBD) + */ + uint32_t c3_dqt_tbl_sel:8; + /** c3_y_factor : R/W; bitpos: [11:8]; default: 1; + * vertical sampling factor of c3 + */ + uint32_t c3_y_factor:4; + /** c3_x_factor : R/W; bitpos: [15:12]; default: 1; + * horizontal sampling factor of c3 + */ + uint32_t c3_x_factor:4; + /** c3_id : R/W; bitpos: [23:16]; default: 0; + * the identifier of c3 + */ + uint32_t c3_id:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_c3_reg_t; + +/** Type of dht_info register + * Control and configuration registers + */ +typedef union { + struct { + /** dc0_dht_id : R/W; bitpos: [3:0]; default: 0; + * configure dht dc table 0 id + */ + uint32_t dc0_dht_id:4; + /** dc1_dht_id : R/W; bitpos: [7:4]; default: 1; + * configure dht dc table 1 id + */ + uint32_t dc1_dht_id:4; + /** ac0_dht_id : R/W; bitpos: [11:8]; default: 0; + * configure dht ac table 0 id + */ + uint32_t ac0_dht_id:4; + /** ac1_dht_id : R/W; bitpos: [15:12]; default: 1; + * configure dht ac table 1 id + */ + uint32_t ac1_dht_id:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} jpeg_dht_info_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Interrupt raw registers + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + */ + uint32_t done_int_raw:1; + /** rle_parallel_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_raw:1; + /** cid_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit to sign that scan id check with component fails when decoding. + */ + uint32_t cid_err_int_raw:1; + /** c_dht_dc_id_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_raw:1; + /** c_dht_ac_id_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_raw:1; + /** c_dqt_id_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit to sign that scan component's dqt id check with dqt table's + * id fails when decoding. + */ + uint32_t c_dqt_id_err_int_raw:1; + /** rst_uxp_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_raw:1; + /** rst_check_none_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_raw:1; + /** rst_check_pos_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_raw:1; + /** out_eof_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_raw:1; + /** sr_color_mode_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit to sign that the selected source color mode is not supported. + */ + uint32_t sr_color_mode_err_int_raw:1; + /** dct_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_raw:1; + /** bs_last_block_eof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_raw:1; + /** scan_check_none_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit to sign that SOS header marker is not detected but there are + * still components left to be decoded. + */ + uint32_t scan_check_none_err_int_raw:1; + /** scan_check_pos_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit to sign that SOS header marker position wrong when decoding. + */ + uint32_t scan_check_pos_err_int_raw:1; + /** uxp_det_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_raw:1; + /** en_frame_eof_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit to sign that received pixel blocks are smaller than expected + * when encoding. + */ + uint32_t en_frame_eof_err_int_raw:1; + /** en_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit to sign that the frame eof sign bit from dma input is missing + * when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_raw:1; + /** de_frame_eof_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_raw:1; + /** de_frame_eof_lack_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_raw:1; + /** sos_unmatch_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit to sign that the component number of a scan is 0 or does not + * match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_raw:1; + /** marker_err_fst_scan_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_raw:1; + /** marker_err_other_scan_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit to sign that the following scans but not the first scan have + * header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_raw:1; + /** undet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit to sign that JPEG format is not detected at the eof data of a + * packet when decoding. + */ + uint32_t undet_int_raw:1; + /** decode_timeout_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_raw_reg_t; + +/** Type of int_ena register + * Interrupt enable registers + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * This enable interrupt bit turns to high level when JPEG finishes encoding a + * picture.. + */ + uint32_t done_int_ena:1; + /** rle_parallel_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_ena:1; + /** cid_err_int_ena : R/W; bitpos: [2]; default: 0; + * The enable interrupt bit to sign that scan id check with component fails when + * decoding. + */ + uint32_t cid_err_int_ena:1; + /** c_dht_dc_id_err_int_ena : R/W; bitpos: [3]; default: 0; + * The enable interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_ena:1; + /** c_dht_ac_id_err_int_ena : R/W; bitpos: [4]; default: 0; + * The enable interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_ena:1; + /** c_dqt_id_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable interrupt bit to sign that scan component's dqt id check with dqt + * table's id fails when decoding. + */ + uint32_t c_dqt_id_err_int_ena:1; + /** rst_uxp_err_int_ena : R/W; bitpos: [6]; default: 0; + * The enable interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_ena:1; + /** rst_check_none_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_ena:1; + /** rst_check_pos_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_ena:1; + /** out_eof_int_ena : R/W; bitpos: [9]; default: 0; + * The enable interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_ena:1; + /** sr_color_mode_err_int_ena : R/W; bitpos: [10]; default: 0; + * The enable interrupt bit to sign that the selected source color mode is not + * supported. + */ + uint32_t sr_color_mode_err_int_ena:1; + /** dct_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_ena:1; + /** bs_last_block_eof_int_ena : R/W; bitpos: [12]; default: 0; + * The enable interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_ena:1; + /** scan_check_none_err_int_ena : R/W; bitpos: [13]; default: 0; + * The enable interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ + uint32_t scan_check_none_err_int_ena:1; + /** scan_check_pos_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable interrupt bit to sign that SOS header marker position wrong when + * decoding. + */ + uint32_t scan_check_pos_err_int_ena:1; + /** uxp_det_int_ena : R/W; bitpos: [15]; default: 0; + * The enable interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_ena:1; + /** en_frame_eof_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ + uint32_t en_frame_eof_err_int_ena:1; + /** en_frame_eof_lack_int_ena : R/W; bitpos: [17]; default: 0; + * The enable interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_ena:1; + /** de_frame_eof_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_ena:1; + /** de_frame_eof_lack_int_ena : R/W; bitpos: [19]; default: 0; + * The enable interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_ena:1; + /** sos_unmatch_err_int_ena : R/W; bitpos: [20]; default: 0; + * The enable interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_ena:1; + /** marker_err_fst_scan_int_ena : R/W; bitpos: [21]; default: 0; + * The enable interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_ena:1; + /** marker_err_other_scan_int_ena : R/W; bitpos: [22]; default: 0; + * The enable interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_ena:1; + /** undet_int_ena : R/W; bitpos: [23]; default: 0; + * The enable interrupt bit to sign that JPEG format is not detected at the eof data + * of a packet when decoding. + */ + uint32_t undet_int_ena:1; + /** decode_timeout_int_ena : R/W; bitpos: [24]; default: 0; + * The enable interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_ena_reg_t; + +/** Type of int_st register + * Interrupt status registers + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * This status interrupt bit turns to high level when JPEG finishes encoding a + * picture.. + */ + uint32_t done_int_st:1; + /** rle_parallel_err_int_st : RO; bitpos: [1]; default: 0; + * The status interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_st:1; + /** cid_err_int_st : RO; bitpos: [2]; default: 0; + * The status interrupt bit to sign that scan id check with component fails when + * decoding. + */ + uint32_t cid_err_int_st:1; + /** c_dht_dc_id_err_int_st : RO; bitpos: [3]; default: 0; + * The status interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_st:1; + /** c_dht_ac_id_err_int_st : RO; bitpos: [4]; default: 0; + * The status interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_st:1; + /** c_dqt_id_err_int_st : RO; bitpos: [5]; default: 0; + * The status interrupt bit to sign that scan component's dqt id check with dqt + * table's id fails when decoding. + */ + uint32_t c_dqt_id_err_int_st:1; + /** rst_uxp_err_int_st : RO; bitpos: [6]; default: 0; + * The status interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_st:1; + /** rst_check_none_err_int_st : RO; bitpos: [7]; default: 0; + * The status interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_st:1; + /** rst_check_pos_err_int_st : RO; bitpos: [8]; default: 0; + * The status interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_st:1; + /** out_eof_int_st : RO; bitpos: [9]; default: 0; + * The status interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_st:1; + /** sr_color_mode_err_int_st : RO; bitpos: [10]; default: 0; + * The status interrupt bit to sign that the selected source color mode is not + * supported. + */ + uint32_t sr_color_mode_err_int_st:1; + /** dct_done_int_st : RO; bitpos: [11]; default: 0; + * The status interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_st:1; + /** bs_last_block_eof_int_st : RO; bitpos: [12]; default: 0; + * The status interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_st:1; + /** scan_check_none_err_int_st : RO; bitpos: [13]; default: 0; + * The status interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ + uint32_t scan_check_none_err_int_st:1; + /** scan_check_pos_err_int_st : RO; bitpos: [14]; default: 0; + * The status interrupt bit to sign that SOS header marker position wrong when + * decoding. + */ + uint32_t scan_check_pos_err_int_st:1; + /** uxp_det_int_st : RO; bitpos: [15]; default: 0; + * The status interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_st:1; + /** en_frame_eof_err_int_st : RO; bitpos: [16]; default: 0; + * The status interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ + uint32_t en_frame_eof_err_int_st:1; + /** en_frame_eof_lack_int_st : RO; bitpos: [17]; default: 0; + * The status interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_st:1; + /** de_frame_eof_err_int_st : RO; bitpos: [18]; default: 0; + * The status interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_st:1; + /** de_frame_eof_lack_int_st : RO; bitpos: [19]; default: 0; + * The status interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_st:1; + /** sos_unmatch_err_int_st : RO; bitpos: [20]; default: 0; + * The status interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_st:1; + /** marker_err_fst_scan_int_st : RO; bitpos: [21]; default: 0; + * The status interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_st:1; + /** marker_err_other_scan_int_st : RO; bitpos: [22]; default: 0; + * The status interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_st:1; + /** undet_int_st : RO; bitpos: [23]; default: 0; + * The status interrupt bit to sign that JPEG format is not detected at the eof data + * of a packet when decoding. + */ + uint32_t undet_int_st:1; + /** decode_timeout_int_st : RO; bitpos: [24]; default: 0; + * The status interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear registers + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + */ + uint32_t done_int_clr:1; + /** rle_parallel_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear interrupt bit to sign that rle parallel error when decoding. + */ + uint32_t rle_parallel_err_int_clr:1; + /** cid_err_int_clr : WT; bitpos: [2]; default: 0; + * The clear interrupt bit to sign that scan id check with component fails when + * decoding. + */ + uint32_t cid_err_int_clr:1; + /** c_dht_dc_id_err_int_clr : WT; bitpos: [3]; default: 0; + * The clear interrupt bit to sign that scan component's dc dht id check with dc dht + * table's id fails when decoding. + */ + uint32_t c_dht_dc_id_err_int_clr:1; + /** c_dht_ac_id_err_int_clr : WT; bitpos: [4]; default: 0; + * The clear interrupt bit to sign that scan component's ac dht id check with ac dht + * table's id fails when decoding. + */ + uint32_t c_dht_ac_id_err_int_clr:1; + /** c_dqt_id_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear interrupt bit to sign that scan component's dqt id check with dqt table's + * id fails when decoding. + */ + uint32_t c_dqt_id_err_int_clr:1; + /** rst_uxp_err_int_clr : WT; bitpos: [6]; default: 0; + * The clear interrupt bit to sign that RST header marker is detected but restart + * interval is 0 when decoding. + */ + uint32_t rst_uxp_err_int_clr:1; + /** rst_check_none_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear interrupt bit to sign that RST header marker is not detected but restart + * interval is not 0 when decoding. + */ + uint32_t rst_check_none_err_int_clr:1; + /** rst_check_pos_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear interrupt bit to sign that RST header marker position mismatches with + * restart interval when decoding. + */ + uint32_t rst_check_pos_err_int_clr:1; + /** out_eof_int_clr : WT; bitpos: [9]; default: 0; + * The clear interrupt bit turns to high level when the last pixel of one square has + * been transmitted for Tx channel. + */ + uint32_t out_eof_int_clr:1; + /** sr_color_mode_err_int_clr : WT; bitpos: [10]; default: 0; + * The clear interrupt bit to sign that the selected source color mode is not + * supported. + */ + uint32_t sr_color_mode_err_int_clr:1; + /** dct_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear interrupt bit to sign that one dct calculation is finished. + */ + uint32_t dct_done_int_clr:1; + /** bs_last_block_eof_int_clr : WT; bitpos: [12]; default: 0; + * The clear interrupt bit to sign that the coding process for last block is finished. + */ + uint32_t bs_last_block_eof_int_clr:1; + /** scan_check_none_err_int_clr : WT; bitpos: [13]; default: 0; + * The clear interrupt bit to sign that SOS header marker is not detected but there + * are still components left to be decoded. + */ + uint32_t scan_check_none_err_int_clr:1; + /** scan_check_pos_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear interrupt bit to sign that SOS header marker position wrong when decoding. + */ + uint32_t scan_check_pos_err_int_clr:1; + /** uxp_det_int_clr : WT; bitpos: [15]; default: 0; + * The clear interrupt bit to sign that unsupported header marker is detected when + * decoding. + */ + uint32_t uxp_det_int_clr:1; + /** en_frame_eof_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear interrupt bit to sign that received pixel blocks are smaller than + * expected when encoding. + */ + uint32_t en_frame_eof_err_int_clr:1; + /** en_frame_eof_lack_int_clr : WT; bitpos: [17]; default: 0; + * The clear interrupt bit to sign that the frame eof sign bit from dma input is + * missing when encoding. But the number of pixel blocks is enough. + */ + uint32_t en_frame_eof_lack_int_clr:1; + /** de_frame_eof_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear interrupt bit to sign that decoded blocks are smaller than expected when + * decoding. + */ + uint32_t de_frame_eof_err_int_clr:1; + /** de_frame_eof_lack_int_clr : WT; bitpos: [19]; default: 0; + * The clear interrupt bit to sign that the either frame eof from dma input or eoi + * marker is missing when encoding. But the number of decoded blocks is enough. + */ + uint32_t de_frame_eof_lack_int_clr:1; + /** sos_unmatch_err_int_clr : WT; bitpos: [20]; default: 0; + * The clear interrupt bit to sign that the component number of a scan is 0 or does + * not match the sos marker's length when decoding. + */ + uint32_t sos_unmatch_err_int_clr:1; + /** marker_err_fst_scan_int_clr : WT; bitpos: [21]; default: 0; + * The clear interrupt bit to sign that the first scan has header marker error when + * decoding. + */ + uint32_t marker_err_fst_scan_int_clr:1; + /** marker_err_other_scan_int_clr : WT; bitpos: [22]; default: 0; + * The clear interrupt bit to sign that the following scans but not the first scan + * have header marker error when decoding. + */ + uint32_t marker_err_other_scan_int_clr:1; + /** undet_int_clr : WT; bitpos: [23]; default: 0; + * The clear interrupt bit to sign that JPEG format is not detected at the eof data of + * a packet when decoding. + */ + uint32_t undet_int_clr:1; + /** decode_timeout_int_clr : WT; bitpos: [24]; default: 0; + * The clear interrupt bit to sign that decode pause time is longer than the setting + * decode timeout time when decoding. + */ + uint32_t decode_timeout_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} jpeg_int_clr_reg_t; + + +/** Group: Trace and Debug registers */ +/** Type of status0 register + * Trace and Debug registers + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** bitstream_eof_vld_cnt : RO; bitpos: [16:11]; default: 0; + * the valid bit count for last bitstream + */ + uint32_t bitstream_eof_vld_cnt:6; + /** dctout_zzscan_addr : RO; bitpos: [22:17]; default: 0; + * the zig-zag read addr from dctout_ram + */ + uint32_t dctout_zzscan_addr:6; + /** qnrval_zzscan_addr : RO; bitpos: [28:23]; default: 0; + * the zig-zag read addr from qnrval_ram + */ + uint32_t qnrval_zzscan_addr:6; + /** reg_state_yuv : RO; bitpos: [31:29]; default: 0; + * the state of jpeg fsm + */ + uint32_t reg_state_yuv:3; + }; + uint32_t val; +} jpeg_status0_reg_t; + +/** Type of status2 register + * Trace and Debug registers + */ +typedef union { + struct { + /** source_pixel : RO; bitpos: [23:0]; default: 0; + * source pixels fetched from dma + */ + uint32_t source_pixel:24; + /** last_block : RO; bitpos: [24]; default: 0; + * indicate the encoding process for the last mcu of the picture + */ + uint32_t last_block:1; + /** last_mcu : RO; bitpos: [25]; default: 0; + * indicate the encoding process for the last block of the picture + */ + uint32_t last_mcu:1; + /** last_dc : RO; bitpos: [26]; default: 0; + * indicate the encoding process is at the header of the last block of the picture + */ + uint32_t last_dc:1; + /** packfifo_ready : RO; bitpos: [27]; default: 1; + * the jpeg pack_fifo ready signal, high active + */ + uint32_t packfifo_ready:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} jpeg_status2_reg_t; + +/** Type of status3 register + * Trace and Debug registers + */ +typedef union { + struct { + /** yo : RO; bitpos: [8:0]; default: 0; + * component y transferred from rgb input + */ + uint32_t yo:9; + /** y_ready : RO; bitpos: [9]; default: 0; + * component y valid signal, high active + */ + uint32_t y_ready:1; + /** cbo : RO; bitpos: [18:10]; default: 0; + * component cb transferred from rgb input + */ + uint32_t cbo:9; + /** cb_ready : RO; bitpos: [19]; default: 0; + * component cb valid signal, high active + */ + uint32_t cb_ready:1; + /** cro : RO; bitpos: [28:20]; default: 0; + * component cr transferred from rgb input + */ + uint32_t cro:9; + /** cr_ready : RO; bitpos: [29]; default: 0; + * component cr valid signal, high active + */ + uint32_t cr_ready:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} jpeg_status3_reg_t; + +/** Type of status4 register + * Trace and Debug registers + */ +typedef union { + struct { + /** hfm_bitstream : RO; bitpos: [31:0]; default: 0; + * the hufman bitstream during encoding process + */ + uint32_t hfm_bitstream:32; + }; + uint32_t val; +} jpeg_status4_reg_t; + +/** Type of dht_totlen_dc0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_dc0 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of dc0 table + */ + uint32_t dht_totlen_dc0:32; + }; + uint32_t val; +} jpeg_dht_totlen_dc0_reg_t; + +/** Type of dht_val_dc0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_dc0 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of dc0 table + */ + uint32_t dht_val_dc0:32; + }; + uint32_t val; +} jpeg_dht_val_dc0_reg_t; + +/** Type of dht_totlen_ac0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_ac0 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of ac0 table + */ + uint32_t dht_totlen_ac0:32; + }; + uint32_t val; +} jpeg_dht_totlen_ac0_reg_t; + +/** Type of dht_val_ac0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_ac0 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of ac0 table + */ + uint32_t dht_val_ac0:32; + }; + uint32_t val; +} jpeg_dht_val_ac0_reg_t; + +/** Type of dht_totlen_dc1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_dc1 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of dc1 table + */ + uint32_t dht_totlen_dc1:32; + }; + uint32_t val; +} jpeg_dht_totlen_dc1_reg_t; + +/** Type of dht_val_dc1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_dc1 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of dc1 table + */ + uint32_t dht_val_dc1:32; + }; + uint32_t val; +} jpeg_dht_val_dc1_reg_t; + +/** Type of dht_totlen_ac1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_totlen_ac1 : HRO; bitpos: [31:0]; default: 0; + * write the numbers of 1~n codeword length sum from 1~16 of ac1 table + */ + uint32_t dht_totlen_ac1:32; + }; + uint32_t val; +} jpeg_dht_totlen_ac1_reg_t; + +/** Type of dht_val_ac1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_val_ac1 : HRO; bitpos: [31:0]; default: 0; + * write codeword corresponding huffman values of ac1 table + */ + uint32_t dht_val_ac1:32; + }; + uint32_t val; +} jpeg_dht_val_ac1_reg_t; + +/** Type of dht_codemin_dc0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_dc0 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of dc0 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_dc0:32; + }; + uint32_t val; +} jpeg_dht_codemin_dc0_reg_t; + +/** Type of dht_codemin_ac0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_ac0 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of ac0 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_ac0:32; + }; + uint32_t val; +} jpeg_dht_codemin_ac0_reg_t; + +/** Type of dht_codemin_dc1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_dc1 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of dc1 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_dc1:32; + }; + uint32_t val; +} jpeg_dht_codemin_dc1_reg_t; + +/** Type of dht_codemin_ac1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** dht_codemin_ac1 : HRO; bitpos: [31:0]; default: 0; + * write the minimum codeword of code length from 1~16 of ac1 table. The codeword is + * left shifted to the MSB position of a 16bit word + */ + uint32_t dht_codemin_ac1:32; + }; + uint32_t val; +} jpeg_dht_codemin_ac1_reg_t; + +/** Type of decoder_status0 register + * Trace and Debug registers + */ +typedef union { + struct { + /** decode_byte_cnt : RO; bitpos: [25:0]; default: 0; + * Reserved + */ + uint32_t decode_byte_cnt:26; + /** header_dec_st : RO; bitpos: [29:26]; default: 0; + * Reserved + */ + uint32_t header_dec_st:4; + /** decode_sample_sel : RO; bitpos: [31:30]; default: 0; + * Reserved + */ + uint32_t decode_sample_sel:2; + }; + uint32_t val; +} jpeg_decoder_status0_reg_t; + +/** Type of decoder_status1 register + * Trace and Debug registers + */ +typedef union { + struct { + /** encode_data : RO; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t encode_data:16; + /** count_q : RO; bitpos: [22:16]; default: 0; + * Reserved + */ + uint32_t count_q:7; + /** mcu_fsm_ready : RO; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t mcu_fsm_ready:1; + /** decode_data : RO; bitpos: [31:24]; default: 0; + * Reserved + */ + uint32_t decode_data:8; + }; + uint32_t val; +} jpeg_decoder_status1_reg_t; + +/** Type of decoder_status2 register + * Trace and Debug registers + */ +typedef union { + struct { + /** comp_block_num : RO; bitpos: [25:0]; default: 0; + * Reserved + */ + uint32_t comp_block_num:26; + /** scan_num : RO; bitpos: [28:26]; default: 0; + * Reserved + */ + uint32_t scan_num:3; + /** rst_check_wait : RO; bitpos: [29]; default: 0; + * Reserved + */ + uint32_t rst_check_wait:1; + /** scan_check_wait : RO; bitpos: [30]; default: 0; + * Reserved + */ + uint32_t scan_check_wait:1; + /** mcu_in_proc : RO; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t mcu_in_proc:1; + }; + uint32_t val; +} jpeg_decoder_status2_reg_t; + +/** Type of decoder_status3 register + * Trace and Debug registers + */ +typedef union { + struct { + /** lookup_data : RO; bitpos: [31:0]; default: 0; + * Reserved + */ + uint32_t lookup_data:32; + }; + uint32_t val; +} jpeg_decoder_status3_reg_t; + +/** Type of decoder_status4 register + * Trace and Debug registers + */ +typedef union { + struct { + /** block_eof_cnt : RO; bitpos: [25:0]; default: 0; + * Reserved + */ + uint32_t block_eof_cnt:26; + /** dezigzag_ready : RO; bitpos: [26]; default: 0; + * Reserved + */ + uint32_t dezigzag_ready:1; + /** de_frame_eof_check : RO; bitpos: [27]; default: 0; + * Reserved + */ + uint32_t de_frame_eof_check:1; + /** de_dma2d_in_push : RO; bitpos: [28]; default: 0; + * Reserved + */ + uint32_t de_dma2d_in_push:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} jpeg_decoder_status4_reg_t; + +/** Type of decoder_status5 register + * Trace and Debug registers + */ +typedef union { + struct { + /** idct_hfm_data : RO; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t idct_hfm_data:16; + /** ns0 : RO; bitpos: [18:16]; default: 0; + * Reserved + */ + uint32_t ns0:3; + /** ns1 : RO; bitpos: [21:19]; default: 0; + * Reserved + */ + uint32_t ns1:3; + /** ns2 : RO; bitpos: [24:22]; default: 0; + * Reserved + */ + uint32_t ns2:3; + /** ns3 : RO; bitpos: [27:25]; default: 0; + * Reserved + */ + uint32_t ns3:3; + /** data_last_o : RO; bitpos: [28]; default: 0; + * Reserved + */ + uint32_t data_last_o:1; + /** rdn_result : RO; bitpos: [29]; default: 0; + * redundant registers for jpeg + */ + uint32_t rdn_result:1; + /** rdn_ena : R/W; bitpos: [30]; default: 0; + * redundant control registers for jpeg + */ + uint32_t rdn_ena:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} jpeg_decoder_status5_reg_t; + +/** Type of status5 register + * Trace and Debug registers + */ +typedef union { + struct { + /** pic_block_num : RO; bitpos: [23:0]; default: 0; + * Reserved + */ + uint32_t pic_block_num:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} jpeg_status5_reg_t; + +/** Type of eco_low register + * Trace and Debug registers + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * redundant registers for jpeg + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} jpeg_eco_low_reg_t; + +/** Type of eco_high register + * Trace and Debug registers + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * redundant registers for jpeg + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} jpeg_eco_high_reg_t; + +/** Type of sys register + * Trace and Debug registers + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + }; + uint32_t val; +} jpeg_sys_reg_t; + +/** Type of version register + * Trace and Debug registers + */ +typedef union { + struct { + /** jpeg_ver : R/W; bitpos: [27:0]; default: 34673040; + * Reserved + */ + uint32_t jpeg_ver:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} jpeg_version_reg_t; + + +typedef struct jpeg_dev_t { + volatile jpeg_config_reg_t config; + volatile jpeg_dqt_info_reg_t dqt_info; + volatile jpeg_pic_size_reg_t pic_size; + uint32_t reserved_00c; + volatile jpeg_t0qnr_reg_t t0qnr; + volatile jpeg_t1qnr_reg_t t1qnr; + volatile jpeg_t2qnr_reg_t t2qnr; + volatile jpeg_t3qnr_reg_t t3qnr; + volatile jpeg_decode_conf_reg_t decode_conf; + volatile jpeg_c0_reg_t c0; + volatile jpeg_c1_reg_t c1; + volatile jpeg_c2_reg_t c2; + volatile jpeg_c3_reg_t c3; + volatile jpeg_dht_info_reg_t dht_info; + volatile jpeg_int_raw_reg_t int_raw; + volatile jpeg_int_ena_reg_t int_ena; + volatile jpeg_int_st_reg_t int_st; + volatile jpeg_int_clr_reg_t int_clr; + volatile jpeg_status0_reg_t status0; + volatile jpeg_status2_reg_t status2; + volatile jpeg_status3_reg_t status3; + volatile jpeg_status4_reg_t status4; + volatile jpeg_dht_totlen_dc0_reg_t dht_totlen_dc0; + volatile jpeg_dht_val_dc0_reg_t dht_val_dc0; + volatile jpeg_dht_totlen_ac0_reg_t dht_totlen_ac0; + volatile jpeg_dht_val_ac0_reg_t dht_val_ac0; + volatile jpeg_dht_totlen_dc1_reg_t dht_totlen_dc1; + volatile jpeg_dht_val_dc1_reg_t dht_val_dc1; + volatile jpeg_dht_totlen_ac1_reg_t dht_totlen_ac1; + volatile jpeg_dht_val_ac1_reg_t dht_val_ac1; + volatile jpeg_dht_codemin_dc0_reg_t dht_codemin_dc0; + volatile jpeg_dht_codemin_ac0_reg_t dht_codemin_ac0; + volatile jpeg_dht_codemin_dc1_reg_t dht_codemin_dc1; + volatile jpeg_dht_codemin_ac1_reg_t dht_codemin_ac1; + volatile jpeg_decoder_status0_reg_t decoder_status0; + volatile jpeg_decoder_status1_reg_t decoder_status1; + volatile jpeg_decoder_status2_reg_t decoder_status2; + volatile jpeg_decoder_status3_reg_t decoder_status3; + volatile jpeg_decoder_status4_reg_t decoder_status4; + volatile jpeg_decoder_status5_reg_t decoder_status5; + volatile jpeg_status5_reg_t status5; + volatile jpeg_eco_low_reg_t eco_low; + volatile jpeg_eco_high_reg_t eco_high; + uint32_t reserved_0ac[19]; + volatile jpeg_sys_reg_t sys; + volatile jpeg_version_reg_t version; +} jpeg_dev_t; + +extern jpeg_dev_t JPEG; + +#ifndef __cplusplus +_Static_assert(sizeof(jpeg_dev_t) == 0x100, "Invalid size of jpeg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/keymng_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/keymng_eco5_reg.h new file mode 100644 index 0000000000..a385df2586 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/keymng_eco5_reg.h @@ -0,0 +1,395 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** KEYMNG_CLK_REG register + * Key Manager clock gate control register + */ +#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) +/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define KEYMNG_REG_CG_FORCE_ON (BIT(0)) +#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S) +#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_REG_CG_FORCE_ON_S 0 +/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) +#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) +#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_MEM_CG_FORCE_ON_S 1 + +/** KEYMNG_INT_RAW_REG register + * Key Manager interrupt raw register, valid in level. + */ +#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) +/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) +#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) +#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_RAW_S 0 +/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) +#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) +#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_RAW_S 1 +/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) +#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) +#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_POST_DONE_INT_RAW_S 2 + +/** KEYMNG_INT_ST_REG register + * Key Manager interrupt status register. + */ +#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) +/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) +#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ST_S 0 +/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) +#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ST_S 1 +/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ST (BIT(2)) +#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) +#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ST_S 2 + +/** KEYMNG_INT_ENA_REG register + * Key Manager interrupt enable register. + */ +#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) +/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) +#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ENA_S 0 +/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) +#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ENA_S 1 +/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) +#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) +#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ENA_S 2 + +/** KEYMNG_INT_CLR_REG register + * Key Manager interrupt clear register. + */ +#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) +/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) +#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) +#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_CLR_S 0 +/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) +#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) +#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_CLR_S 1 +/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) +#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) +#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_POST_DONE_INT_CLR_S 2 + +/** KEYMNG_STATIC_REG register + * Key Manager static configuration register + */ +#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) +/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; + * bit 1 for flash_key; bit 0 for ecdsa_key + */ +#define KEYMNG_USE_EFUSE_KEY 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S) +#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_S 0 +/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ +#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) +#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_S 5 +/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY (BIT(10)) +#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) +#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_S 10 +/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0; + * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ +#define KEYMNG_FLASH_KEY_LEN (BIT(11)) +#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S) +#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U +#define KEYMNG_FLASH_KEY_LEN_S 11 +/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0; + * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ +#define KEYMNG_PSRAM_KEY_LEN (BIT(12)) +#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S) +#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U +#define KEYMNG_PSRAM_KEY_LEN_S 12 + +/** KEYMNG_LOCK_REG register + * Key Manager static configuration locker register + */ +#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) +/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU +#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 +/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ +#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5)) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5 +/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6)) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6 +/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0; + * Write 1 to lock reg_flash_key_len. + */ +#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7)) +#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S) +#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7 +/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0; + * Write 1 to lock reg_psram_key_len. + */ +#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8)) +#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S) +#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8 + +/** KEYMNG_CONF_REG register + * Key Manager configuration register + */ +#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) +/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ +#define KEYMNG_KGEN_MODE 0x00000007U +#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) +#define KEYMNG_KGEN_MODE_V 0x00000007U +#define KEYMNG_KGEN_MODE_S 0 +/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. + */ +#define KEYMNG_KEY_PURPOSE 0x0000000FU +#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) +#define KEYMNG_KEY_PURPOSE_V 0x0000000FU +#define KEYMNG_KEY_PURPOSE_S 3 + +/** KEYMNG_START_REG register + * Key Manager control register + */ +#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) +/** KEYMNG_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ +#define KEYMNG_START (BIT(0)) +#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) +#define KEYMNG_START_V 0x00000001U +#define KEYMNG_START_S 0 +/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ +#define KEYMNG_CONTINUE (BIT(1)) +#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) +#define KEYMNG_CONTINUE_V 0x00000001U +#define KEYMNG_CONTINUE_S 1 + +/** KEYMNG_STATE_REG register + * Key Manager state register + */ +#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) +/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define KEYMNG_STATE 0x00000003U +#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) +#define KEYMNG_STATE_V 0x00000003U +#define KEYMNG_STATE_S 0 + +/** KEYMNG_RESULT_REG register + * Key Manager operation result register + */ +#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) +/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ +#define KEYMNG_PROC_RESULT (BIT(0)) +#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) +#define KEYMNG_PROC_RESULT_V 0x00000001U +#define KEYMNG_PROC_RESULT_S 0 + +/** KEYMNG_KEY_VLD_REG register + * Key Manager key status register + */ +#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) +/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S) +#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_192_VLD_S 0 +/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1)) +#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S) +#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_256_VLD_S 1 +/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0; + * The status bit for key_flash. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_FLASH_VLD (BIT(2)) +#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S) +#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U +#define KEYMNG_KEY_FLASH_VLD_S 2 +/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0; + * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_HMAC_VLD (BIT(3)) +#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S) +#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U +#define KEYMNG_KEY_HMAC_VLD_S 3 +/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0; + * The status bit for key_ds. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_DS_VLD (BIT(4)) +#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S) +#define KEYMNG_KEY_DS_VLD_V 0x00000001U +#define KEYMNG_KEY_DS_VLD_S 4 +/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0; + * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_PSRAM_VLD (BIT(5)) +#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S) +#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U +#define KEYMNG_KEY_PSRAM_VLD_S 5 +/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6)) +#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S) +#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_384_VLD_S 6 + +/** KEYMNG_HUK_VLD_REG register + * Key Manager HUK status register + */ +#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) +/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ +#define KEYMNG_HUK_VALID (BIT(0)) +#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) +#define KEYMNG_HUK_VALID_V 0x00000001U +#define KEYMNG_HUK_VALID_S 0 + +/** KEYMNG_DATE_REG register + * Version control register + */ +#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824; + * Key Manager version control register. + */ +#define KEYMNG_DATE 0x0FFFFFFFU +#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) +#define KEYMNG_DATE_V 0x0FFFFFFFU +#define KEYMNG_DATE_S 0 + +/** KEYMNG_ASSIST_INFO_MEM register + * The memory that stores assist key info. + */ +#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) +#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_PUBLIC_INFO_MEM register + * The memory that stores public key info. + */ +#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) +#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_SW_INIT_KEY_MEM register + * The memory that stores software written init key. + */ +#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) +#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/keymng_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/keymng_reg.h new file mode 100644 index 0000000000..86cef480c0 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/keymng_reg.h @@ -0,0 +1,366 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** KEYMNG_CLK_REG register + * Key Manager clock gate control register + */ +#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) +/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define KEYMNG_CLK_EN (BIT(0)) +#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S) +#define KEYMNG_CLK_EN_V 0x00000001U +#define KEYMNG_CLK_EN_S 0 +/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) +#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) +#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_MEM_CG_FORCE_ON_S 1 + +/** KEYMNG_INT_RAW_REG register + * Key Manager interrupt raw register, valid in level. + */ +#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) +/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) +#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) +#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_RAW_S 0 +/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) +#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) +#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_RAW_S 1 +/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) +#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) +#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_POST_DONE_INT_RAW_S 2 + +/** KEYMNG_INT_ST_REG register + * Key Manager interrupt status register. + */ +#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) +/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) +#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ST_S 0 +/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) +#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ST_S 1 +/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ST (BIT(2)) +#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) +#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ST_S 2 + +/** KEYMNG_INT_ENA_REG register + * Key Manager interrupt enable register. + */ +#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) +/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) +#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ENA_S 0 +/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) +#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ENA_S 1 +/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) +#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) +#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ENA_S 2 + +/** KEYMNG_INT_CLR_REG register + * Key Manager interrupt clear register. + */ +#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) +/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) +#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) +#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_CLR_S 0 +/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) +#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) +#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_CLR_S 1 +/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) +#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) +#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_POST_DONE_INT_CLR_S 2 + +/** KEYMNG_STATIC_REG register + * Key Manager static configuration register + */ +#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) + +/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set this bit to choose efuse key instead of key manager deployed key for xts_key.*/ +#define KEYMNG_USE_EFUSE_KEY_XTS (BIT(1)) +#define KEYMNG_USE_EFUSE_KEY_XTS_M ((KEYMNG_USE_EFUSE_KEY_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_XTS_S)) +#define KEYMNG_USE_EFUSE_KEY_XTS_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_XTS_S 1 + +/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa_key.*/ +#define KEYMNG_USE_EFUSE_KEY_ECDSA (BIT(0)) +#define KEYMNG_USE_EFUSE_KEY_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S)) +#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_ECDSA_S 0 + +/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ +#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) +#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_S 4 +/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY (BIT(9)) +#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) +#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_S 9 +/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0; + * Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use + * xts-aes-128. + */ +#define KEYMNG_XTS_AES_KEY_LEN (BIT(10)) +#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S) +#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U +#define KEYMNG_XTS_AES_KEY_LEN_S 10 + +/** KEYMNG_LOCK_REG register + * Key Manager static configuration locker register + */ +#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) + +/* KEYMNG_USE_EFUSE_KEY_XTS : R/W ; bitpos:[1] ; default: 1'd0 ; */ +/* description: Set thus bit to choose efuse key instead of key manager deployed key for xts_key */ +#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS (BIT(1)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_M ((KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_LOCK_XTS_S 1 + +/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W ; bitpos:[0] ; default: 1'd0 ; */ +/* description: Write 1 to lock ecdsa-key */ +#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA (BIT(0)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S 0 + +/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ +#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4)) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4 +/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5)) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5 +/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_xts_aes_key_len. + */ +#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6)) +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S) +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6 + +/** KEYMNG_CONF_REG register + * Key Manager configuration register + */ +#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) +/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ +#define KEYMNG_KGEN_MODE 0x00000007U +#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) +#define KEYMNG_KGEN_MODE_V 0x00000007U +#define KEYMNG_KGEN_MODE_S 0 +/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3: + * xts_256_2_key. 4. xts_128_key. others: reserved. + */ +#define KEYMNG_KEY_PURPOSE 0x0000000FU +#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) +#define KEYMNG_KEY_PURPOSE_V 0x0000000FU +#define KEYMNG_KEY_PURPOSE_S 3 + +#define KEYMNG_KEY_PURPOSE_ECDSA (BIT(0)) +#define KEYMNG_KEY_PURPOSE_ECDSA_M (KEYMNG_KEY_PURPOSE_ECDSA_V << KEYMNG_KEY_PURPOSE_ECDSA_S) +#define KEYMNG_KEY_PURPOSE_ECDSA_V 0x00000001U +#define KEYMNG_KEY_PURPOSE_ECDSA_S 0 + +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1 (BIT(1)) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V 0x00000001U +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S 1 + +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2 (BIT(2)) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V 0x00000001U +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S 2 + +/** KEYMNG_START_REG register + * Key Manager control register + */ +#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) +/** KEYMNG_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ +#define KEYMNG_START (BIT(0)) +#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) +#define KEYMNG_START_V 0x00000001U +#define KEYMNG_START_S 0 +/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ +#define KEYMNG_CONTINUE (BIT(1)) +#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) +#define KEYMNG_CONTINUE_V 0x00000001U +#define KEYMNG_CONTINUE_S 1 + +/** KEYMNG_STATE_REG register + * Key Manager state register + */ +#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) +/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define KEYMNG_STATE 0x00000003U +#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) +#define KEYMNG_STATE_V 0x00000003U +#define KEYMNG_STATE_S 0 + +/** KEYMNG_RESULT_REG register + * Key Manager operation result register + */ +#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) +/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ +#define KEYMNG_PROC_RESULT (BIT(0)) +#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) +#define KEYMNG_PROC_RESULT_V 0x00000001U +#define KEYMNG_PROC_RESULT_S 0 + +/** KEYMNG_KEY_VLD_REG register + * Key Manager key status register + */ +#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) +/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S) +#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_VLD_S 0 +/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_xts. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_XTS_VLD (BIT(1)) +#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S) +#define KEYMNG_KEY_XTS_VLD_V 0x00000001U +#define KEYMNG_KEY_XTS_VLD_S 1 + +/** KEYMNG_HUK_VLD_REG register + * Key Manager HUK status register + */ +#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) +/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ +#define KEYMNG_HUK_VALID (BIT(0)) +#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) +#define KEYMNG_HUK_VALID_V 0x00000001U +#define KEYMNG_HUK_VALID_S 0 + +/** KEYMNG_DATE_REG register + * Version control register + */ +#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704; + * Key Manager version control register. + */ +#define KEYMNG_DATE 0x0FFFFFFFU +#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) +#define KEYMNG_DATE_V 0x0FFFFFFFU +#define KEYMNG_DATE_S 0 + +/** KEYMNG_ASSIST_INFO_MEM register + * The memory that stores assist key info. + */ +#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) +#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_PUBLIC_INFO_MEM register + * The memory that stores public key info. + */ +#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) +#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_SW_INIT_KEY_MEM register + * The memory that stores software written init key. + */ +#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) +#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/keymng_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/keymng_struct.h new file mode 100644 index 0000000000..d46c34fcd5 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/keymng_struct.h @@ -0,0 +1,375 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * Key Manager clock gate control register + */ +typedef union { + struct { + /** reg_cg_force_on : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t reg_cg_force_on:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Key Manager interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_raw_reg_t; + +/** Type of int_st register + * Key Manager interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_st_reg_t; + +/** Type of int_ena register + * Key Manager interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_ena_reg_t; + +/** Type of int_clr register + * Key Manager interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_clr_reg_t; + + +/** Group: Static configuration registers */ +/** Type of static register + * Key Manager static configuration register + */ +typedef union { + struct { + /** use_efuse_key : R/W; bitpos: [4:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; + * bit 1 for flash_key; bit 0 for ecdsa_key + */ + uint32_t use_efuse_key:5; + /** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ + uint32_t rnd_switch_cycle:5; + /** use_sw_init_key : R/W; bitpos: [10]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ + uint32_t use_sw_init_key:1; + /** flash_key_len : R/W; bitpos: [11]; default: 0; + * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ + uint32_t flash_key_len:1; + /** psram_key_len : R/W; bitpos: [12]; default: 0; + * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use + * xts-aes-256. 0: use xts-aes-128. + */ + uint32_t psram_key_len:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} keymng_static_reg_t; + +/** Type of lock register + * Key Manager static configuration locker register + */ +typedef union { + struct { + /** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ + uint32_t use_efuse_key_lock:5; + /** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ + uint32_t rnd_switch_cycle_lock:1; + /** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ + uint32_t use_sw_init_key_lock:1; + /** flash_key_len_lock : R/W1; bitpos: [7]; default: 0; + * Write 1 to lock reg_flash_key_len. + */ + uint32_t flash_key_len_lock:1; + /** psram_key_len_lock : R/W1; bitpos: [8]; default: 0; + * Write 1 to lock reg_psram_key_len. + */ + uint32_t psram_key_len_lock:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} keymng_lock_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** kgen_mode : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ + uint32_t kgen_mode:3; + /** key_purpose : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. + */ + uint32_t key_purpose:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * Key Manager control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ + uint32_t conti:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * Key Manager state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * Key Manager operation result register + */ +typedef union { + struct { + /** proc_result : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ + uint32_t proc_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_result_reg_t; + +/** Type of key_vld register + * Key Manager key status register + */ +typedef union { + struct { + /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_192_vld:1; + /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_256_vld:1; + /** key_flash_vld : RO; bitpos: [2]; default: 0; + * The status bit for key_flash. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_flash_vld:1; + /** key_hmac_vld : RO; bitpos: [3]; default: 0; + * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_hmac_vld:1; + /** key_ds_vld : RO; bitpos: [4]; default: 0; + * The status bit for key_ds. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ds_vld:1; + /** key_psram_vld : RO; bitpos: [5]; default: 0; + * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_psram_vld:1; + /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_384_vld:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_key_vld_reg_t; + +/** Type of huk_vld register + * Key Manager HUK status register + */ +typedef union { + struct { + /** huk_valid : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ + uint32_t huk_valid:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_huk_vld_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37781824; + * Key Manager version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} keymng_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile keymng_clk_reg_t clk; + volatile keymng_int_raw_reg_t int_raw; + volatile keymng_int_st_reg_t int_st; + volatile keymng_int_ena_reg_t int_ena; + volatile keymng_int_clr_reg_t int_clr; + volatile keymng_static_reg_t static_conf; + volatile keymng_lock_reg_t lock; + volatile keymng_conf_reg_t conf; + volatile keymng_start_reg_t start; + volatile keymng_state_reg_t state; + volatile keymng_result_reg_t result; + volatile keymng_key_vld_reg_t key_vld; + volatile keymng_huk_vld_reg_t huk_vld; + uint32_t reserved_038[49]; + volatile keymng_date_reg_t date; + volatile uint32_t assist_info[16]; + volatile uint32_t public_info[16]; + volatile uint32_t sw_init_key[8]; +} keymng_dev_t; + +extern keymng_dev_t KEYMNG; + +#ifndef __cplusplus +_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_eco5_struct.h new file mode 100644 index 0000000000..6864fab433 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_eco5_struct.h @@ -0,0 +1,875 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: lcd configuration registers */ +/** Type of lcd_clock register + * LCD clock config register. + */ +typedef union { + struct { + /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; + * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + */ + uint32_t lcd_clkcnt_n:6; + /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; + * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + */ + uint32_t lcd_clk_equ_sysclk:1; + /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; + * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + */ + uint32_t lcd_ck_idle_edge:1; + /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; + * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low + * in the second half data cycle. + */ + uint32_t lcd_ck_out_edge:1; + /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; + * Integral LCD clock divider value + */ + uint32_t lcd_clkm_div_num:8; + /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t lcd_clkm_div_b:6; + /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t lcd_clkm_div_a:6; + /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; + * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ + uint32_t lcd_clk_sel:2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lcdcam_lcd_clock_reg_t; + +/** Type of lcd_rgb_yuv register + * LCD YUV/RGB converter configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3; + * 0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled + */ + uint32_t lcd_conv_rgb2rgb_mode:2; + /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ + uint32_t lcd_conv_8bits_data_inv:1; + /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; + * 0: txtorx mode off. 1: txtorx mode on. + */ + uint32_t lcd_conv_txtorx:1; + /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 2: to yuv411. 1,3: disabled. To enable yuv2yuv mode, trans_mode + * must be set to 1. + */ + uint32_t lcd_conv_yuv2yuv_mode:2; + /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + */ + uint32_t lcd_conv_yuv_mode:2; + /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ + uint32_t lcd_conv_protocol_mode:1; + /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ + uint32_t lcd_conv_data_out_mode:1; + /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ + uint32_t lcd_conv_data_in_mode:1; + /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ + uint32_t lcd_conv_mode_8bits_on:1; + /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ + uint32_t lcd_conv_trans_mode:1; + /** lcd_conv_enable : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ + uint32_t lcd_conv_enable:1; + }; + uint32_t val; +} lcdcam_lcd_rgb_yuv_reg_t; + +/** Type of lcd_user register + * LCD config register. + */ +typedef union { + struct { + /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; + * The output data cycles minus 1 of LCD module. + */ + uint32_t lcd_dout_cyclelen:13; + /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; + * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or + * reg_lcd_reset is set. + */ + uint32_t lcd_always_out_en:1; + /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0; + * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + */ + uint32_t lcd_dout_byte_swizzle_mode:3; + /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0; + * 1: enable byte swizzle 0: disable + */ + uint32_t lcd_dout_byte_swizzle_enable:1; + /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0; + * 1: change bit order in every byte. 0: Not change. + */ + uint32_t lcd_dout_bit_order:1; + /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0; + * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + */ + uint32_t lcd_byte_mode:2; + /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0; + * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + */ + uint32_t lcd_update_reg:1; + /** lcd_bit_order : R/W; bitpos: [22]; default: 0; + * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ + uint32_t lcd_bit_order:1; + /** lcd_byte_order : R/W; bitpos: [23]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ + uint32_t lcd_byte_order:1; + /** lcd_dout : R/W; bitpos: [24]; default: 0; + * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_dout:1; + /** lcd_dummy : R/W; bitpos: [25]; default: 0; + * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_dummy:1; + /** lcd_cmd : R/W; bitpos: [26]; default: 0; + * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_cmd:1; + /** lcd_start : R/W/SC; bitpos: [27]; default: 0; + * LCD start sending data enable signal, valid in high level. + */ + uint32_t lcd_start:1; + /** lcd_reset : WT; bitpos: [28]; default: 0; + * The value of command. + */ + uint32_t lcd_reset:1; + /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; + * The dummy cycle length minus 1. + */ + uint32_t lcd_dummy_cyclelen:2; + /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + */ + uint32_t lcd_cmd_2_cycle_en:1; + }; + uint32_t val; +} lcdcam_lcd_user_reg_t; + +/** Type of lcd_misc register + * LCD config register. + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0; + * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + */ + uint32_t lcd_wire_mode:2; + /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; + * The setup cycle length minus 1 in LCD non-RGB mode. + */ + uint32_t lcd_vfk_cyclelen:6; + /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; + * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold + * time cycle length in LCD non-RGB mode. + */ + uint32_t lcd_vbk_cyclelen:13; + /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; + * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when + * the current frame is sent out. + */ + uint32_t lcd_next_frame_en:1; + /** lcd_bk_en : R/W; bitpos: [26]; default: 0; + * 1: Enable blank region when LCD sends data out. 0: No blank region. + */ + uint32_t lcd_bk_en:1; + /** lcd_afifo_reset : WT; bitpos: [27]; default: 0; + * LCD AFIFO reset signal. + */ + uint32_t lcd_afifo_reset:1; + /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_data_set:1; + /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_dummy_set:1; + /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_cmd_set:1; + /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; + * The default value of LCD_CD. + */ + uint32_t lcd_cd_idle_edge:1; + }; + uint32_t val; +} lcdcam_lcd_misc_reg_t; + +/** Type of lcd_ctrl register + * LCD config register. + */ +typedef union { + struct { + /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ + uint32_t lcd_hb_front:11; + /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ + uint32_t lcd_va_height:10; + /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ + uint32_t lcd_vt_height:10; + /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + */ + uint32_t lcd_rgb_mode_en:1; + }; + uint32_t val; +} lcdcam_lcd_ctrl_reg_t; + +/** Type of lcd_ctrl1 register + * LCD config register. + */ +typedef union { + struct { + /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ + uint32_t lcd_vb_front:8; + /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ + uint32_t lcd_ha_width:12; + /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ + uint32_t lcd_ht_width:12; + }; + uint32_t val; +} lcdcam_lcd_ctrl1_reg_t; + +/** Type of lcd_ctrl2 register + * LCD config register. + */ +typedef union { + struct { + /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; + * It is the position of LCD_VSYNC active pulse in a line. + */ + uint32_t lcd_vsync_width:7; + /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; + * It is the idle value of LCD_VSYNC. + */ + uint32_t lcd_vsync_idle_pol:1; + /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0; + * It is the idle value of LCD_DE. + */ + uint32_t lcd_de_idle_pol:1; + /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC + * pulse is valid only in active region lines in RGB mode. + */ + uint32_t lcd_hs_blank_en:1; + uint32_t reserved_10:6; + /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; + * It is the position of LCD_HSYNC active pulse in a line. + */ + uint32_t lcd_hsync_width:7; + /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; + * It is the idle value of LCD_HSYNC. + */ + uint32_t lcd_hsync_idle_pol:1; + /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; + * It is the position of LCD_HSYNC active pulse in a line. + */ + uint32_t lcd_hsync_position:8; + }; + uint32_t val; +} lcdcam_lcd_ctrl2_reg_t; + +/** Type of lcd_first_cmd_val register + * LCD config register. + */ +typedef union { + struct { + /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of first cmd cycle. + */ + uint32_t lcd_first_cmd_value:32; + }; + uint32_t val; +} lcdcam_lcd_first_cmd_val_reg_t; + +/** Type of lcd_latter_cmd_val register + * LCD config register. + */ +typedef union { + struct { + /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of latter cmd cycle. + */ + uint32_t lcd_latter_cmd_value:32; + }; + uint32_t val; +} lcdcam_lcd_latter_cmd_val_reg_t; + +/** Type of lcd_dly_mode_cfg1 register + * LCD config register. + */ +typedef union { + struct { + /** dout16_mode : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout16_mode:2; + /** dout17_mode : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout17_mode:2; + /** dout18_mode : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout18_mode:2; + /** dout19_mode : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout19_mode:2; + /** dout20_mode : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout20_mode:2; + /** dout21_mode : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout21_mode:2; + /** dout22_mode : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout22_mode:2; + /** dout23_mode : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout23_mode:2; + /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0; + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_cd_mode:2; + /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0; + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_de_mode:2; + /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0; + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_hsync_mode:2; + /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0; + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_vsync_mode:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} lcdcam_lcd_dly_mode_cfg1_reg_t; + +/** Type of lcd_dly_mode_cfg2 register + * LCD config register. + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout0_mode:2; + /** dout1_mode : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout1_mode:2; + /** dout2_mode : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout2_mode:2; + /** dout3_mode : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout3_mode:2; + /** dout4_mode : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout4_mode:2; + /** dout5_mode : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout5_mode:2; + /** dout6_mode : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout6_mode:2; + /** dout7_mode : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout7_mode:2; + /** dout8_mode : R/W; bitpos: [17:16]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout8_mode:2; + /** dout9_mode : R/W; bitpos: [19:18]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout9_mode:2; + /** dout10_mode : R/W; bitpos: [21:20]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout10_mode:2; + /** dout11_mode : R/W; bitpos: [23:22]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout11_mode:2; + /** dout12_mode : R/W; bitpos: [25:24]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout12_mode:2; + /** dout13_mode : R/W; bitpos: [27:26]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout13_mode:2; + /** dout14_mode : R/W; bitpos: [29:28]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout14_mode:2; + /** dout15_mode : R/W; bitpos: [31:30]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout15_mode:2; + }; + uint32_t val; +} lcdcam_lcd_dly_mode_cfg2_reg_t; + + +/** Group: cam configuration registers */ +/** Type of cam_ctrl register + * CAM config register. + */ +typedef union { + struct { + /** cam_stop_en : R/W; bitpos: [0]; default: 0; + * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + */ + uint32_t cam_stop_en:1; + /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; + * Filter threshold value for CAM_VSYNC signal. + */ + uint32_t cam_vsync_filter_thres:3; + /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0; + * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + */ + uint32_t cam_update_reg:1; + /** cam_byte_order : R/W; bitpos: [5]; default: 0; + * 1: invert data byte order. 0: Not change. + */ + uint32_t cam_byte_order:1; + /** cam_bit_order : R/W; bitpos: [6]; default: 0; + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ + uint32_t cam_bit_order:1; + /** cam_line_int_en : R/W; bitpos: [7]; default: 0; + * 1: Enable to generate CAM_HS_INT. 0: Disable. + */ + uint32_t cam_line_int_en:1; + /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; + * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * reg_cam_rec_data_cyclelen. + */ + uint32_t cam_vs_eof_en:1; + /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; + * Integral Camera clock divider value + */ + uint32_t cam_clkm_div_num:8; + /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t cam_clkm_div_b:6; + /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t cam_clkm_div_a:6; + /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; + * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ + uint32_t cam_clk_sel:2; + uint32_t reserved_31:1; + }; + uint32_t val; +} lcdcam_cam_ctrl_reg_t; + +/** Type of cam_ctrl1 register + * CAM config register. + */ +typedef union { + struct { + /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; + * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + */ + uint32_t cam_rec_data_bytelen:16; + /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; + * The line number minus 1 to generate cam_hs_int. + */ + uint32_t cam_line_int_num:6; + /** cam_clk_inv : R/W; bitpos: [22]; default: 0; + * 1: Invert the input signal CAM_PCLK. 0: Not invert. + */ + uint32_t cam_clk_inv:1; + /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; + * 1: Enable CAM_VSYNC filter function. 0: bypass. + */ + uint32_t cam_vsync_filter_en:1; + /** cam_2byte_en : R/W; bitpos: [24]; default: 0; + * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + */ + uint32_t cam_2byte_en:1; + /** cam_de_inv : R/W; bitpos: [25]; default: 0; + * CAM_DE invert enable signal, valid in high level. + */ + uint32_t cam_de_inv:1; + /** cam_hsync_inv : R/W; bitpos: [26]; default: 0; + * CAM_HSYNC invert enable signal, valid in high level. + */ + uint32_t cam_hsync_inv:1; + /** cam_vsync_inv : R/W; bitpos: [27]; default: 0; + * CAM_VSYNC invert enable signal, valid in high level. + */ + uint32_t cam_vsync_inv:1; + /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; + * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control + * signals are CAM_DE and CAM_VSYNC. + */ + uint32_t cam_vh_de_mode_en:1; + /** cam_start : R/W/SC; bitpos: [29]; default: 0; + * Camera module start signal. + */ + uint32_t cam_start:1; + /** cam_reset : WT; bitpos: [30]; default: 0; + * Camera module reset signal. + */ + uint32_t cam_reset:1; + /** cam_afifo_reset : WT; bitpos: [31]; default: 0; + * Camera AFIFO reset signal. + */ + uint32_t cam_afifo_reset:1; + }; + uint32_t val; +} lcdcam_cam_ctrl1_reg_t; + +/** Type of cam_rgb_yuv register + * CAM YUV/RGB converter configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ + uint32_t cam_conv_8bits_data_inv:1; + /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ + uint32_t cam_conv_yuv2yuv_mode:2; + /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ + uint32_t cam_conv_yuv_mode:2; + /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ + uint32_t cam_conv_protocol_mode:1; + /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ + uint32_t cam_conv_data_out_mode:1; + /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ + uint32_t cam_conv_data_in_mode:1; + /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ + uint32_t cam_conv_mode_8bits_on:1; + /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ + uint32_t cam_conv_trans_mode:1; + /** cam_conv_enable : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ + uint32_t cam_conv_enable:1; + }; + uint32_t val; +} lcdcam_cam_rgb_yuv_reg_t; + + +/** Group: Interrupt registers */ +/** Type of lc_dma_int_ena register + * LCDCAM interrupt enable register. + */ +typedef union { + struct { + /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_ena:1; + /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_ena:1; + /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_ena:1; + /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for Camera line interrupt. + */ + uint32_t cam_hs_int_ena:1; + /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lcdcam_lc_dma_int_ena_reg_t; + +/** Type of lc_dma_int_raw register + * LCDCAM interrupt raw register, valid in level. + */ +typedef union { + struct { + /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_raw:1; + /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_raw:1; + /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_raw:1; + /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for Camera line interrupt. + */ + uint32_t cam_hs_int_raw:1; + /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lcdcam_lc_dma_int_raw_reg_t; + +/** Type of lc_dma_int_st register + * LCDCAM interrupt status register. + */ +typedef union { + struct { + /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; + * The status bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_st:1; + /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; + * The status bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_st:1; + /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; + * The status bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_st:1; + /** cam_hs_int_st : RO; bitpos: [3]; default: 0; + * The status bit for Camera transfer end interrupt. + */ + uint32_t cam_hs_int_st:1; + /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0; + * The status bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lcdcam_lc_dma_int_st_reg_t; + +/** Type of lc_dma_int_clr register + * LCDCAM interrupt clear register. + */ +typedef union { + struct { + /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_clr:1; + /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_clr:1; + /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_clr:1; + /** cam_hs_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for Camera line interrupt. + */ + uint32_t cam_hs_int_clr:1; + /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for LCD underrun interrupt + */ + uint32_t lcd_underrun_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lcdcam_lc_dma_int_clr_reg_t; + + +/** Group: Version register */ +/** Type of lc_reg_date register + * Version register + */ +typedef union { + struct { + /** lc_date : R/W; bitpos: [27:0]; default: 38806054; + * LCD_CAM version control register + */ + uint32_t lc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lcdcam_lc_reg_date_reg_t; + + +typedef struct { + volatile lcdcam_lcd_clock_reg_t lcd_clock; + volatile lcdcam_cam_ctrl_reg_t cam_ctrl; + volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1; + volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv; + volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv; + volatile lcdcam_lcd_user_reg_t lcd_user; + volatile lcdcam_lcd_misc_reg_t lcd_misc; + volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl; + volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1; + volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2; + volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val; + volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val; + volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1; + uint32_t reserved_034; + volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2; + uint32_t reserved_03c[10]; + volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena; + volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw; + volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st; + volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr; + uint32_t reserved_074[34]; + volatile lcdcam_lc_reg_date_reg_t lc_reg_date; +} lcdcam_dev_t; + +extern lcdcam_dev_t LCD_CAM; + +#ifndef __cplusplus +_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_reg.h new file mode 100644 index 0000000000..971324f56c --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_reg.h @@ -0,0 +1,1179 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LCDCAM_LCD_CLOCK_REG register + * LCD clock config register. + */ +#define LCDCAM_LCD_CLOCK_REG (DR_REG_LCDCAM_BASE + 0x0) +/** LCDCAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3; + * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + */ +#define LCDCAM_LCD_CLKCNT_N 0x0000003FU +#define LCDCAM_LCD_CLKCNT_N_M (LCDCAM_LCD_CLKCNT_N_V << LCDCAM_LCD_CLKCNT_N_S) +#define LCDCAM_LCD_CLKCNT_N_V 0x0000003FU +#define LCDCAM_LCD_CLKCNT_N_S 0 +/** LCDCAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1; + * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + */ +#define LCDCAM_LCD_CLK_EQU_SYSCLK (BIT(6)) +#define LCDCAM_LCD_CLK_EQU_SYSCLK_M (LCDCAM_LCD_CLK_EQU_SYSCLK_V << LCDCAM_LCD_CLK_EQU_SYSCLK_S) +#define LCDCAM_LCD_CLK_EQU_SYSCLK_V 0x00000001U +#define LCDCAM_LCD_CLK_EQU_SYSCLK_S 6 +/** LCDCAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0; + * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + */ +#define LCDCAM_LCD_CK_IDLE_EDGE (BIT(7)) +#define LCDCAM_LCD_CK_IDLE_EDGE_M (LCDCAM_LCD_CK_IDLE_EDGE_V << LCDCAM_LCD_CK_IDLE_EDGE_S) +#define LCDCAM_LCD_CK_IDLE_EDGE_V 0x00000001U +#define LCDCAM_LCD_CK_IDLE_EDGE_S 7 +/** LCDCAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0; + * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low + * in the second half data cycle. + */ +#define LCDCAM_LCD_CK_OUT_EDGE (BIT(8)) +#define LCDCAM_LCD_CK_OUT_EDGE_M (LCDCAM_LCD_CK_OUT_EDGE_V << LCDCAM_LCD_CK_OUT_EDGE_S) +#define LCDCAM_LCD_CK_OUT_EDGE_V 0x00000001U +#define LCDCAM_LCD_CK_OUT_EDGE_S 8 +/** LCDCAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; + * Integral LCD clock divider value + */ +#define LCDCAM_LCD_CLKM_DIV_NUM 0x000000FFU +#define LCDCAM_LCD_CLKM_DIV_NUM_M (LCDCAM_LCD_CLKM_DIV_NUM_V << LCDCAM_LCD_CLKM_DIV_NUM_S) +#define LCDCAM_LCD_CLKM_DIV_NUM_V 0x000000FFU +#define LCDCAM_LCD_CLKM_DIV_NUM_S 9 +/** LCDCAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ +#define LCDCAM_LCD_CLKM_DIV_B 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_B_M (LCDCAM_LCD_CLKM_DIV_B_V << LCDCAM_LCD_CLKM_DIV_B_S) +#define LCDCAM_LCD_CLKM_DIV_B_V 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_B_S 17 +/** LCDCAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ +#define LCDCAM_LCD_CLKM_DIV_A 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_A_M (LCDCAM_LCD_CLKM_DIV_A_V << LCDCAM_LCD_CLKM_DIV_A_S) +#define LCDCAM_LCD_CLKM_DIV_A_V 0x0000003FU +#define LCDCAM_LCD_CLKM_DIV_A_S 23 +/** LCDCAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0; + * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ +#define LCDCAM_LCD_CLK_SEL 0x00000003U +#define LCDCAM_LCD_CLK_SEL_M (LCDCAM_LCD_CLK_SEL_V << LCDCAM_LCD_CLK_SEL_S) +#define LCDCAM_LCD_CLK_SEL_V 0x00000003U +#define LCDCAM_LCD_CLK_SEL_S 29 +/** LCDCAM_CLK_EN : R/W; bitpos: [31]; default: 0; + * Set this bit to enable clk gate + */ +#define LCDCAM_CLK_EN (BIT(31)) +#define LCDCAM_CLK_EN_M (LCDCAM_CLK_EN_V << LCDCAM_CLK_EN_S) +#define LCDCAM_CLK_EN_V 0x00000001U +#define LCDCAM_CLK_EN_S 31 + +/** LCDCAM_CAM_CTRL_REG register + * CAM config register. + */ +#define LCDCAM_CAM_CTRL_REG (DR_REG_LCDCAM_BASE + 0x4) +/** LCDCAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0; + * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + */ +#define LCDCAM_CAM_STOP_EN (BIT(0)) +#define LCDCAM_CAM_STOP_EN_M (LCDCAM_CAM_STOP_EN_V << LCDCAM_CAM_STOP_EN_S) +#define LCDCAM_CAM_STOP_EN_V 0x00000001U +#define LCDCAM_CAM_STOP_EN_S 0 +/** LCDCAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0; + * Filter threshold value for CAM_VSYNC signal. + */ +#define LCDCAM_CAM_VSYNC_FILTER_THRES 0x00000007U +#define LCDCAM_CAM_VSYNC_FILTER_THRES_M (LCDCAM_CAM_VSYNC_FILTER_THRES_V << LCDCAM_CAM_VSYNC_FILTER_THRES_S) +#define LCDCAM_CAM_VSYNC_FILTER_THRES_V 0x00000007U +#define LCDCAM_CAM_VSYNC_FILTER_THRES_S 1 +/** LCDCAM_CAM_UPDATE_REG : R/W/SC; bitpos: [4]; default: 0; + * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + */ +#define LCDCAM_CAM_UPDATE_REG (BIT(4)) +#define LCDCAM_CAM_UPDATE_REG_M (LCDCAM_CAM_UPDATE_REG_V << LCDCAM_CAM_UPDATE_REG_S) +#define LCDCAM_CAM_UPDATE_REG_V 0x00000001U +#define LCDCAM_CAM_UPDATE_REG_S 4 +/** LCDCAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0; + * 1: invert data byte order. 0: Not change. + */ +#define LCDCAM_CAM_BYTE_ORDER (BIT(5)) +#define LCDCAM_CAM_BYTE_ORDER_M (LCDCAM_CAM_BYTE_ORDER_V << LCDCAM_CAM_BYTE_ORDER_S) +#define LCDCAM_CAM_BYTE_ORDER_V 0x00000001U +#define LCDCAM_CAM_BYTE_ORDER_S 5 +/** LCDCAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0; + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ +#define LCDCAM_CAM_BIT_ORDER (BIT(6)) +#define LCDCAM_CAM_BIT_ORDER_M (LCDCAM_CAM_BIT_ORDER_V << LCDCAM_CAM_BIT_ORDER_S) +#define LCDCAM_CAM_BIT_ORDER_V 0x00000001U +#define LCDCAM_CAM_BIT_ORDER_S 6 +/** LCDCAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable to generate CAM_HS_INT. 0: Disable. + */ +#define LCDCAM_CAM_LINE_INT_EN (BIT(7)) +#define LCDCAM_CAM_LINE_INT_EN_M (LCDCAM_CAM_LINE_INT_EN_V << LCDCAM_CAM_LINE_INT_EN_S) +#define LCDCAM_CAM_LINE_INT_EN_V 0x00000001U +#define LCDCAM_CAM_LINE_INT_EN_S 7 +/** LCDCAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0; + * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * reg_cam_rec_data_cyclelen. + */ +#define LCDCAM_CAM_VS_EOF_EN (BIT(8)) +#define LCDCAM_CAM_VS_EOF_EN_M (LCDCAM_CAM_VS_EOF_EN_V << LCDCAM_CAM_VS_EOF_EN_S) +#define LCDCAM_CAM_VS_EOF_EN_V 0x00000001U +#define LCDCAM_CAM_VS_EOF_EN_S 8 +/** LCDCAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4; + * Integral Camera clock divider value + */ +#define LCDCAM_CAM_CLKM_DIV_NUM 0x000000FFU +#define LCDCAM_CAM_CLKM_DIV_NUM_M (LCDCAM_CAM_CLKM_DIV_NUM_V << LCDCAM_CAM_CLKM_DIV_NUM_S) +#define LCDCAM_CAM_CLKM_DIV_NUM_V 0x000000FFU +#define LCDCAM_CAM_CLKM_DIV_NUM_S 9 +/** LCDCAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ +#define LCDCAM_CAM_CLKM_DIV_B 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_B_M (LCDCAM_CAM_CLKM_DIV_B_V << LCDCAM_CAM_CLKM_DIV_B_S) +#define LCDCAM_CAM_CLKM_DIV_B_V 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_B_S 17 +/** LCDCAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ +#define LCDCAM_CAM_CLKM_DIV_A 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_A_M (LCDCAM_CAM_CLKM_DIV_A_V << LCDCAM_CAM_CLKM_DIV_A_S) +#define LCDCAM_CAM_CLKM_DIV_A_V 0x0000003FU +#define LCDCAM_CAM_CLKM_DIV_A_S 23 +/** LCDCAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0; + * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ +#define LCDCAM_CAM_CLK_SEL 0x00000003U +#define LCDCAM_CAM_CLK_SEL_M (LCDCAM_CAM_CLK_SEL_V << LCDCAM_CAM_CLK_SEL_S) +#define LCDCAM_CAM_CLK_SEL_V 0x00000003U +#define LCDCAM_CAM_CLK_SEL_S 29 + +/** LCDCAM_CAM_CTRL1_REG register + * CAM config register. + */ +#define LCDCAM_CAM_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x8) +/** LCDCAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0; + * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + */ +#define LCDCAM_CAM_REC_DATA_BYTELEN 0x0000FFFFU +#define LCDCAM_CAM_REC_DATA_BYTELEN_M (LCDCAM_CAM_REC_DATA_BYTELEN_V << LCDCAM_CAM_REC_DATA_BYTELEN_S) +#define LCDCAM_CAM_REC_DATA_BYTELEN_V 0x0000FFFFU +#define LCDCAM_CAM_REC_DATA_BYTELEN_S 0 +/** LCDCAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0; + * The line number minus 1 to generate cam_hs_int. + */ +#define LCDCAM_CAM_LINE_INT_NUM 0x0000003FU +#define LCDCAM_CAM_LINE_INT_NUM_M (LCDCAM_CAM_LINE_INT_NUM_V << LCDCAM_CAM_LINE_INT_NUM_S) +#define LCDCAM_CAM_LINE_INT_NUM_V 0x0000003FU +#define LCDCAM_CAM_LINE_INT_NUM_S 16 +/** LCDCAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0; + * 1: Invert the input signal CAM_PCLK. 0: Not invert. + */ +#define LCDCAM_CAM_CLK_INV (BIT(22)) +#define LCDCAM_CAM_CLK_INV_M (LCDCAM_CAM_CLK_INV_V << LCDCAM_CAM_CLK_INV_S) +#define LCDCAM_CAM_CLK_INV_V 0x00000001U +#define LCDCAM_CAM_CLK_INV_S 22 +/** LCDCAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0; + * 1: Enable CAM_VSYNC filter function. 0: bypass. + */ +#define LCDCAM_CAM_VSYNC_FILTER_EN (BIT(23)) +#define LCDCAM_CAM_VSYNC_FILTER_EN_M (LCDCAM_CAM_VSYNC_FILTER_EN_V << LCDCAM_CAM_VSYNC_FILTER_EN_S) +#define LCDCAM_CAM_VSYNC_FILTER_EN_V 0x00000001U +#define LCDCAM_CAM_VSYNC_FILTER_EN_S 23 +/** LCDCAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0; + * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + */ +#define LCDCAM_CAM_2BYTE_EN (BIT(24)) +#define LCDCAM_CAM_2BYTE_EN_M (LCDCAM_CAM_2BYTE_EN_V << LCDCAM_CAM_2BYTE_EN_S) +#define LCDCAM_CAM_2BYTE_EN_V 0x00000001U +#define LCDCAM_CAM_2BYTE_EN_S 24 +/** LCDCAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0; + * CAM_DE invert enable signal, valid in high level. + */ +#define LCDCAM_CAM_DE_INV (BIT(25)) +#define LCDCAM_CAM_DE_INV_M (LCDCAM_CAM_DE_INV_V << LCDCAM_CAM_DE_INV_S) +#define LCDCAM_CAM_DE_INV_V 0x00000001U +#define LCDCAM_CAM_DE_INV_S 25 +/** LCDCAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0; + * CAM_HSYNC invert enable signal, valid in high level. + */ +#define LCDCAM_CAM_HSYNC_INV (BIT(26)) +#define LCDCAM_CAM_HSYNC_INV_M (LCDCAM_CAM_HSYNC_INV_V << LCDCAM_CAM_HSYNC_INV_S) +#define LCDCAM_CAM_HSYNC_INV_V 0x00000001U +#define LCDCAM_CAM_HSYNC_INV_S 26 +/** LCDCAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0; + * CAM_VSYNC invert enable signal, valid in high level. + */ +#define LCDCAM_CAM_VSYNC_INV (BIT(27)) +#define LCDCAM_CAM_VSYNC_INV_M (LCDCAM_CAM_VSYNC_INV_V << LCDCAM_CAM_VSYNC_INV_S) +#define LCDCAM_CAM_VSYNC_INV_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INV_S 27 +/** LCDCAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0; + * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control + * signals are CAM_DE and CAM_VSYNC. + */ +#define LCDCAM_CAM_VH_DE_MODE_EN (BIT(28)) +#define LCDCAM_CAM_VH_DE_MODE_EN_M (LCDCAM_CAM_VH_DE_MODE_EN_V << LCDCAM_CAM_VH_DE_MODE_EN_S) +#define LCDCAM_CAM_VH_DE_MODE_EN_V 0x00000001U +#define LCDCAM_CAM_VH_DE_MODE_EN_S 28 +/** LCDCAM_CAM_START : R/W/SC; bitpos: [29]; default: 0; + * Camera module start signal. + */ +#define LCDCAM_CAM_START (BIT(29)) +#define LCDCAM_CAM_START_M (LCDCAM_CAM_START_V << LCDCAM_CAM_START_S) +#define LCDCAM_CAM_START_V 0x00000001U +#define LCDCAM_CAM_START_S 29 +/** LCDCAM_CAM_RESET : WT; bitpos: [30]; default: 0; + * Camera module reset signal. + */ +#define LCDCAM_CAM_RESET (BIT(30)) +#define LCDCAM_CAM_RESET_M (LCDCAM_CAM_RESET_V << LCDCAM_CAM_RESET_S) +#define LCDCAM_CAM_RESET_V 0x00000001U +#define LCDCAM_CAM_RESET_S 30 +/** LCDCAM_CAM_AFIFO_RESET : WT; bitpos: [31]; default: 0; + * Camera AFIFO reset signal. + */ +#define LCDCAM_CAM_AFIFO_RESET (BIT(31)) +#define LCDCAM_CAM_AFIFO_RESET_M (LCDCAM_CAM_AFIFO_RESET_V << LCDCAM_CAM_AFIFO_RESET_S) +#define LCDCAM_CAM_AFIFO_RESET_V 0x00000001U +#define LCDCAM_CAM_AFIFO_RESET_S 31 + +/** LCDCAM_CAM_RGB_YUV_REG register + * CAM YUV/RGB converter configuration register. + */ +#define LCDCAM_CAM_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0xc) +/** LCDCAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ +#define LCDCAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) +#define LCDCAM_CAM_CONV_8BITS_DATA_INV_M (LCDCAM_CAM_CONV_8BITS_DATA_INV_V << LCDCAM_CAM_CONV_8BITS_DATA_INV_S) +#define LCDCAM_CAM_CONV_8BITS_DATA_INV_V 0x00000001U +#define LCDCAM_CAM_CONV_8BITS_DATA_INV_S 21 +/** LCDCAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ +#define LCDCAM_CAM_CONV_YUV2YUV_MODE 0x00000003U +#define LCDCAM_CAM_CONV_YUV2YUV_MODE_M (LCDCAM_CAM_CONV_YUV2YUV_MODE_V << LCDCAM_CAM_CONV_YUV2YUV_MODE_S) +#define LCDCAM_CAM_CONV_YUV2YUV_MODE_V 0x00000003U +#define LCDCAM_CAM_CONV_YUV2YUV_MODE_S 22 +/** LCDCAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ +#define LCDCAM_CAM_CONV_YUV_MODE 0x00000003U +#define LCDCAM_CAM_CONV_YUV_MODE_M (LCDCAM_CAM_CONV_YUV_MODE_V << LCDCAM_CAM_CONV_YUV_MODE_S) +#define LCDCAM_CAM_CONV_YUV_MODE_V 0x00000003U +#define LCDCAM_CAM_CONV_YUV_MODE_S 24 +/** LCDCAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ +#define LCDCAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) +#define LCDCAM_CAM_CONV_PROTOCOL_MODE_M (LCDCAM_CAM_CONV_PROTOCOL_MODE_V << LCDCAM_CAM_CONV_PROTOCOL_MODE_S) +#define LCDCAM_CAM_CONV_PROTOCOL_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_PROTOCOL_MODE_S 26 +/** LCDCAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ +#define LCDCAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) +#define LCDCAM_CAM_CONV_DATA_OUT_MODE_M (LCDCAM_CAM_CONV_DATA_OUT_MODE_V << LCDCAM_CAM_CONV_DATA_OUT_MODE_S) +#define LCDCAM_CAM_CONV_DATA_OUT_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_DATA_OUT_MODE_S 27 +/** LCDCAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ +#define LCDCAM_CAM_CONV_DATA_IN_MODE (BIT(28)) +#define LCDCAM_CAM_CONV_DATA_IN_MODE_M (LCDCAM_CAM_CONV_DATA_IN_MODE_V << LCDCAM_CAM_CONV_DATA_IN_MODE_S) +#define LCDCAM_CAM_CONV_DATA_IN_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_DATA_IN_MODE_S 28 +/** LCDCAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ +#define LCDCAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) +#define LCDCAM_CAM_CONV_MODE_8BITS_ON_M (LCDCAM_CAM_CONV_MODE_8BITS_ON_V << LCDCAM_CAM_CONV_MODE_8BITS_ON_S) +#define LCDCAM_CAM_CONV_MODE_8BITS_ON_V 0x00000001U +#define LCDCAM_CAM_CONV_MODE_8BITS_ON_S 29 +/** LCDCAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ +#define LCDCAM_CAM_CONV_TRANS_MODE (BIT(30)) +#define LCDCAM_CAM_CONV_TRANS_MODE_M (LCDCAM_CAM_CONV_TRANS_MODE_V << LCDCAM_CAM_CONV_TRANS_MODE_S) +#define LCDCAM_CAM_CONV_TRANS_MODE_V 0x00000001U +#define LCDCAM_CAM_CONV_TRANS_MODE_S 30 +/** LCDCAM_CAM_CONV_ENABLE : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ +#define LCDCAM_CAM_CONV_ENABLE (BIT(31)) +#define LCDCAM_CAM_CONV_ENABLE_M (LCDCAM_CAM_CONV_ENABLE_V << LCDCAM_CAM_CONV_ENABLE_S) +#define LCDCAM_CAM_CONV_ENABLE_V 0x00000001U +#define LCDCAM_CAM_CONV_ENABLE_S 31 + +/** LCDCAM_LCD_RGB_YUV_REG register + * LCD YUV/RGB converter configuration register. + */ +#define LCDCAM_LCD_RGB_YUV_REG (DR_REG_LCDCAM_BASE + 0x10) +/** LCDCAM_LCD_CONV_RGB2RGB_MODE : R/W; bitpos: [19:18]; default: 3; + * 0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled + */ +#define LCDCAM_LCD_CONV_RGB2RGB_MODE 0x00000003U +#define LCDCAM_LCD_CONV_RGB2RGB_MODE_M (LCDCAM_LCD_CONV_RGB2RGB_MODE_V << LCDCAM_LCD_CONV_RGB2RGB_MODE_S) +#define LCDCAM_LCD_CONV_RGB2RGB_MODE_V 0x00000003U +#define LCDCAM_LCD_CONV_RGB2RGB_MODE_S 18 +/** LCDCAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ +#define LCDCAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) +#define LCDCAM_LCD_CONV_8BITS_DATA_INV_M (LCDCAM_LCD_CONV_8BITS_DATA_INV_V << LCDCAM_LCD_CONV_8BITS_DATA_INV_S) +#define LCDCAM_LCD_CONV_8BITS_DATA_INV_V 0x00000001U +#define LCDCAM_LCD_CONV_8BITS_DATA_INV_S 20 +/** LCDCAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0; + * 0: txtorx mode off. 1: txtorx mode on. + */ +#define LCDCAM_LCD_CONV_TXTORX (BIT(21)) +#define LCDCAM_LCD_CONV_TXTORX_M (LCDCAM_LCD_CONV_TXTORX_V << LCDCAM_LCD_CONV_TXTORX_S) +#define LCDCAM_LCD_CONV_TXTORX_V 0x00000001U +#define LCDCAM_LCD_CONV_TXTORX_S 21 +/** LCDCAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 2: to yuv411. 1,3: disabled. To enable yuv2yuv mode, trans_mode + * must be set to 1. + */ +#define LCDCAM_LCD_CONV_YUV2YUV_MODE 0x00000003U +#define LCDCAM_LCD_CONV_YUV2YUV_MODE_M (LCDCAM_LCD_CONV_YUV2YUV_MODE_V << LCDCAM_LCD_CONV_YUV2YUV_MODE_S) +#define LCDCAM_LCD_CONV_YUV2YUV_MODE_V 0x00000003U +#define LCDCAM_LCD_CONV_YUV2YUV_MODE_S 22 +/** LCDCAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + */ +#define LCDCAM_LCD_CONV_YUV_MODE 0x00000003U +#define LCDCAM_LCD_CONV_YUV_MODE_M (LCDCAM_LCD_CONV_YUV_MODE_V << LCDCAM_LCD_CONV_YUV_MODE_S) +#define LCDCAM_LCD_CONV_YUV_MODE_V 0x00000003U +#define LCDCAM_LCD_CONV_YUV_MODE_S 24 +/** LCDCAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ +#define LCDCAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) +#define LCDCAM_LCD_CONV_PROTOCOL_MODE_M (LCDCAM_LCD_CONV_PROTOCOL_MODE_V << LCDCAM_LCD_CONV_PROTOCOL_MODE_S) +#define LCDCAM_LCD_CONV_PROTOCOL_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_PROTOCOL_MODE_S 26 +/** LCDCAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ +#define LCDCAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) +#define LCDCAM_LCD_CONV_DATA_OUT_MODE_M (LCDCAM_LCD_CONV_DATA_OUT_MODE_V << LCDCAM_LCD_CONV_DATA_OUT_MODE_S) +#define LCDCAM_LCD_CONV_DATA_OUT_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_DATA_OUT_MODE_S 27 +/** LCDCAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ +#define LCDCAM_LCD_CONV_DATA_IN_MODE (BIT(28)) +#define LCDCAM_LCD_CONV_DATA_IN_MODE_M (LCDCAM_LCD_CONV_DATA_IN_MODE_V << LCDCAM_LCD_CONV_DATA_IN_MODE_S) +#define LCDCAM_LCD_CONV_DATA_IN_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_DATA_IN_MODE_S 28 +/** LCDCAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ +#define LCDCAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) +#define LCDCAM_LCD_CONV_MODE_8BITS_ON_M (LCDCAM_LCD_CONV_MODE_8BITS_ON_V << LCDCAM_LCD_CONV_MODE_8BITS_ON_S) +#define LCDCAM_LCD_CONV_MODE_8BITS_ON_V 0x00000001U +#define LCDCAM_LCD_CONV_MODE_8BITS_ON_S 29 +/** LCDCAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ +#define LCDCAM_LCD_CONV_TRANS_MODE (BIT(30)) +#define LCDCAM_LCD_CONV_TRANS_MODE_M (LCDCAM_LCD_CONV_TRANS_MODE_V << LCDCAM_LCD_CONV_TRANS_MODE_S) +#define LCDCAM_LCD_CONV_TRANS_MODE_V 0x00000001U +#define LCDCAM_LCD_CONV_TRANS_MODE_S 30 +/** LCDCAM_LCD_CONV_ENABLE : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ +#define LCDCAM_LCD_CONV_ENABLE (BIT(31)) +#define LCDCAM_LCD_CONV_ENABLE_M (LCDCAM_LCD_CONV_ENABLE_V << LCDCAM_LCD_CONV_ENABLE_S) +#define LCDCAM_LCD_CONV_ENABLE_V 0x00000001U +#define LCDCAM_LCD_CONV_ENABLE_S 31 + +/** LCDCAM_LCD_USER_REG register + * LCD config register. + */ +#define LCDCAM_LCD_USER_REG (DR_REG_LCDCAM_BASE + 0x14) +/** LCDCAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1; + * The output data cycles minus 1 of LCD module. + */ +#define LCDCAM_LCD_DOUT_CYCLELEN 0x00001FFFU +#define LCDCAM_LCD_DOUT_CYCLELEN_M (LCDCAM_LCD_DOUT_CYCLELEN_V << LCDCAM_LCD_DOUT_CYCLELEN_S) +#define LCDCAM_LCD_DOUT_CYCLELEN_V 0x00001FFFU +#define LCDCAM_LCD_DOUT_CYCLELEN_S 0 +/** LCDCAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0; + * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or + * reg_lcd_reset is set. + */ +#define LCDCAM_LCD_ALWAYS_OUT_EN (BIT(13)) +#define LCDCAM_LCD_ALWAYS_OUT_EN_M (LCDCAM_LCD_ALWAYS_OUT_EN_V << LCDCAM_LCD_ALWAYS_OUT_EN_S) +#define LCDCAM_LCD_ALWAYS_OUT_EN_V 0x00000001U +#define LCDCAM_LCD_ALWAYS_OUT_EN_S 13 +/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W; bitpos: [16:14]; default: 0; + * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + */ +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE 0x00000007U +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S) +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V 0x00000007U +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S 14 +/** LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W; bitpos: [17]; default: 0; + * 1: enable byte swizzle 0: disable + */ +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE (BIT(17)) +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M (LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V << LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S) +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V 0x00000001U +#define LCDCAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S 17 +/** LCDCAM_LCD_DOUT_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * 1: change bit order in every byte. 0: Not change. + */ +#define LCDCAM_LCD_DOUT_BIT_ORDER (BIT(18)) +#define LCDCAM_LCD_DOUT_BIT_ORDER_M (LCDCAM_LCD_DOUT_BIT_ORDER_V << LCDCAM_LCD_DOUT_BIT_ORDER_S) +#define LCDCAM_LCD_DOUT_BIT_ORDER_V 0x00000001U +#define LCDCAM_LCD_DOUT_BIT_ORDER_S 18 +/** LCDCAM_LCD_BYTE_MODE : R/W; bitpos: [20:19]; default: 0; + * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + */ +#define LCDCAM_LCD_BYTE_MODE 0x00000003U +#define LCDCAM_LCD_BYTE_MODE_M (LCDCAM_LCD_BYTE_MODE_V << LCDCAM_LCD_BYTE_MODE_S) +#define LCDCAM_LCD_BYTE_MODE_V 0x00000003U +#define LCDCAM_LCD_BYTE_MODE_S 19 +/** LCDCAM_LCD_UPDATE_REG : R/W/SC; bitpos: [21]; default: 0; + * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + */ +#define LCDCAM_LCD_UPDATE_REG (BIT(21)) +#define LCDCAM_LCD_UPDATE_REG_M (LCDCAM_LCD_UPDATE_REG_V << LCDCAM_LCD_UPDATE_REG_S) +#define LCDCAM_LCD_UPDATE_REG_V 0x00000001U +#define LCDCAM_LCD_UPDATE_REG_S 21 +/** LCDCAM_LCD_BIT_ORDER : R/W; bitpos: [22]; default: 0; + * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ +#define LCDCAM_LCD_BIT_ORDER (BIT(22)) +#define LCDCAM_LCD_BIT_ORDER_M (LCDCAM_LCD_BIT_ORDER_V << LCDCAM_LCD_BIT_ORDER_S) +#define LCDCAM_LCD_BIT_ORDER_V 0x00000001U +#define LCDCAM_LCD_BIT_ORDER_S 22 +/** LCDCAM_LCD_BYTE_ORDER : R/W; bitpos: [23]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ +#define LCDCAM_LCD_BYTE_ORDER (BIT(23)) +#define LCDCAM_LCD_BYTE_ORDER_M (LCDCAM_LCD_BYTE_ORDER_V << LCDCAM_LCD_BYTE_ORDER_S) +#define LCDCAM_LCD_BYTE_ORDER_V 0x00000001U +#define LCDCAM_LCD_BYTE_ORDER_S 23 +/** LCDCAM_LCD_DOUT : R/W; bitpos: [24]; default: 0; + * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + */ +#define LCDCAM_LCD_DOUT (BIT(24)) +#define LCDCAM_LCD_DOUT_M (LCDCAM_LCD_DOUT_V << LCDCAM_LCD_DOUT_S) +#define LCDCAM_LCD_DOUT_V 0x00000001U +#define LCDCAM_LCD_DOUT_S 24 +/** LCDCAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0; + * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + */ +#define LCDCAM_LCD_DUMMY (BIT(25)) +#define LCDCAM_LCD_DUMMY_M (LCDCAM_LCD_DUMMY_V << LCDCAM_LCD_DUMMY_S) +#define LCDCAM_LCD_DUMMY_V 0x00000001U +#define LCDCAM_LCD_DUMMY_S 25 +/** LCDCAM_LCD_CMD : R/W; bitpos: [26]; default: 0; + * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + */ +#define LCDCAM_LCD_CMD (BIT(26)) +#define LCDCAM_LCD_CMD_M (LCDCAM_LCD_CMD_V << LCDCAM_LCD_CMD_S) +#define LCDCAM_LCD_CMD_V 0x00000001U +#define LCDCAM_LCD_CMD_S 26 +/** LCDCAM_LCD_START : R/W/SC; bitpos: [27]; default: 0; + * LCD start sending data enable signal, valid in high level. + */ +#define LCDCAM_LCD_START (BIT(27)) +#define LCDCAM_LCD_START_M (LCDCAM_LCD_START_V << LCDCAM_LCD_START_S) +#define LCDCAM_LCD_START_V 0x00000001U +#define LCDCAM_LCD_START_S 27 +/** LCDCAM_LCD_RESET : WT; bitpos: [28]; default: 0; + * The value of command. + */ +#define LCDCAM_LCD_RESET (BIT(28)) +#define LCDCAM_LCD_RESET_M (LCDCAM_LCD_RESET_V << LCDCAM_LCD_RESET_S) +#define LCDCAM_LCD_RESET_V 0x00000001U +#define LCDCAM_LCD_RESET_S 28 +/** LCDCAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0; + * The dummy cycle length minus 1. + */ +#define LCDCAM_LCD_DUMMY_CYCLELEN 0x00000003U +#define LCDCAM_LCD_DUMMY_CYCLELEN_M (LCDCAM_LCD_DUMMY_CYCLELEN_V << LCDCAM_LCD_DUMMY_CYCLELEN_S) +#define LCDCAM_LCD_DUMMY_CYCLELEN_V 0x00000003U +#define LCDCAM_LCD_DUMMY_CYCLELEN_S 29 +/** LCDCAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0; + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + */ +#define LCDCAM_LCD_CMD_2_CYCLE_EN (BIT(31)) +#define LCDCAM_LCD_CMD_2_CYCLE_EN_M (LCDCAM_LCD_CMD_2_CYCLE_EN_V << LCDCAM_LCD_CMD_2_CYCLE_EN_S) +#define LCDCAM_LCD_CMD_2_CYCLE_EN_V 0x00000001U +#define LCDCAM_LCD_CMD_2_CYCLE_EN_S 31 + +/** LCDCAM_LCD_MISC_REG register + * LCD config register. + */ +#define LCDCAM_LCD_MISC_REG (DR_REG_LCDCAM_BASE + 0x18) +/** LCDCAM_LCD_WIRE_MODE : R/W; bitpos: [5:4]; default: 0; + * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + */ +#define LCDCAM_LCD_WIRE_MODE 0x00000003U +#define LCDCAM_LCD_WIRE_MODE_M (LCDCAM_LCD_WIRE_MODE_V << LCDCAM_LCD_WIRE_MODE_S) +#define LCDCAM_LCD_WIRE_MODE_V 0x00000003U +#define LCDCAM_LCD_WIRE_MODE_S 4 +/** LCDCAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3; + * The setup cycle length minus 1 in LCD non-RGB mode. + */ +#define LCDCAM_LCD_VFK_CYCLELEN 0x0000003FU +#define LCDCAM_LCD_VFK_CYCLELEN_M (LCDCAM_LCD_VFK_CYCLELEN_V << LCDCAM_LCD_VFK_CYCLELEN_S) +#define LCDCAM_LCD_VFK_CYCLELEN_V 0x0000003FU +#define LCDCAM_LCD_VFK_CYCLELEN_S 6 +/** LCDCAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0; + * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold + * time cycle length in LCD non-RGB mode. + */ +#define LCDCAM_LCD_VBK_CYCLELEN 0x00001FFFU +#define LCDCAM_LCD_VBK_CYCLELEN_M (LCDCAM_LCD_VBK_CYCLELEN_V << LCDCAM_LCD_VBK_CYCLELEN_S) +#define LCDCAM_LCD_VBK_CYCLELEN_V 0x00001FFFU +#define LCDCAM_LCD_VBK_CYCLELEN_S 12 +/** LCDCAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0; + * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when + * the current frame is sent out. + */ +#define LCDCAM_LCD_NEXT_FRAME_EN (BIT(25)) +#define LCDCAM_LCD_NEXT_FRAME_EN_M (LCDCAM_LCD_NEXT_FRAME_EN_V << LCDCAM_LCD_NEXT_FRAME_EN_S) +#define LCDCAM_LCD_NEXT_FRAME_EN_V 0x00000001U +#define LCDCAM_LCD_NEXT_FRAME_EN_S 25 +/** LCDCAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0; + * 1: Enable blank region when LCD sends data out. 0: No blank region. + */ +#define LCDCAM_LCD_BK_EN (BIT(26)) +#define LCDCAM_LCD_BK_EN_M (LCDCAM_LCD_BK_EN_V << LCDCAM_LCD_BK_EN_S) +#define LCDCAM_LCD_BK_EN_V 0x00000001U +#define LCDCAM_LCD_BK_EN_S 26 +/** LCDCAM_LCD_AFIFO_RESET : WT; bitpos: [27]; default: 0; + * LCD AFIFO reset signal. + */ +#define LCDCAM_LCD_AFIFO_RESET (BIT(27)) +#define LCDCAM_LCD_AFIFO_RESET_M (LCDCAM_LCD_AFIFO_RESET_V << LCDCAM_LCD_AFIFO_RESET_S) +#define LCDCAM_LCD_AFIFO_RESET_V 0x00000001U +#define LCDCAM_LCD_AFIFO_RESET_S 27 +/** LCDCAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = + * reg_cd_idle_edge. + */ +#define LCDCAM_LCD_CD_DATA_SET (BIT(28)) +#define LCDCAM_LCD_CD_DATA_SET_M (LCDCAM_LCD_CD_DATA_SET_V << LCDCAM_LCD_CD_DATA_SET_S) +#define LCDCAM_LCD_CD_DATA_SET_V 0x00000001U +#define LCDCAM_LCD_CD_DATA_SET_S 28 +/** LCDCAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = + * reg_cd_idle_edge. + */ +#define LCDCAM_LCD_CD_DUMMY_SET (BIT(29)) +#define LCDCAM_LCD_CD_DUMMY_SET_M (LCDCAM_LCD_CD_DUMMY_SET_V << LCDCAM_LCD_CD_DUMMY_SET_S) +#define LCDCAM_LCD_CD_DUMMY_SET_V 0x00000001U +#define LCDCAM_LCD_CD_DUMMY_SET_S 29 +/** LCDCAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = + * reg_cd_idle_edge. + */ +#define LCDCAM_LCD_CD_CMD_SET (BIT(30)) +#define LCDCAM_LCD_CD_CMD_SET_M (LCDCAM_LCD_CD_CMD_SET_V << LCDCAM_LCD_CD_CMD_SET_S) +#define LCDCAM_LCD_CD_CMD_SET_V 0x00000001U +#define LCDCAM_LCD_CD_CMD_SET_S 30 +/** LCDCAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0; + * The default value of LCD_CD. + */ +#define LCDCAM_LCD_CD_IDLE_EDGE (BIT(31)) +#define LCDCAM_LCD_CD_IDLE_EDGE_M (LCDCAM_LCD_CD_IDLE_EDGE_V << LCDCAM_LCD_CD_IDLE_EDGE_S) +#define LCDCAM_LCD_CD_IDLE_EDGE_V 0x00000001U +#define LCDCAM_LCD_CD_IDLE_EDGE_S 31 + +/** LCDCAM_LCD_CTRL_REG register + * LCD config register. + */ +#define LCDCAM_LCD_CTRL_REG (DR_REG_LCDCAM_BASE + 0x1c) +/** LCDCAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ +#define LCDCAM_LCD_HB_FRONT 0x000007FFU +#define LCDCAM_LCD_HB_FRONT_M (LCDCAM_LCD_HB_FRONT_V << LCDCAM_LCD_HB_FRONT_S) +#define LCDCAM_LCD_HB_FRONT_V 0x000007FFU +#define LCDCAM_LCD_HB_FRONT_S 0 +/** LCDCAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ +#define LCDCAM_LCD_VA_HEIGHT 0x000003FFU +#define LCDCAM_LCD_VA_HEIGHT_M (LCDCAM_LCD_VA_HEIGHT_V << LCDCAM_LCD_VA_HEIGHT_S) +#define LCDCAM_LCD_VA_HEIGHT_V 0x000003FFU +#define LCDCAM_LCD_VA_HEIGHT_S 11 +/** LCDCAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ +#define LCDCAM_LCD_VT_HEIGHT 0x000003FFU +#define LCDCAM_LCD_VT_HEIGHT_M (LCDCAM_LCD_VT_HEIGHT_V << LCDCAM_LCD_VT_HEIGHT_S) +#define LCDCAM_LCD_VT_HEIGHT_V 0x000003FFU +#define LCDCAM_LCD_VT_HEIGHT_S 21 +/** LCDCAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + */ +#define LCDCAM_LCD_RGB_MODE_EN (BIT(31)) +#define LCDCAM_LCD_RGB_MODE_EN_M (LCDCAM_LCD_RGB_MODE_EN_V << LCDCAM_LCD_RGB_MODE_EN_S) +#define LCDCAM_LCD_RGB_MODE_EN_V 0x00000001U +#define LCDCAM_LCD_RGB_MODE_EN_S 31 + +/** LCDCAM_LCD_CTRL1_REG register + * LCD config register. + */ +#define LCDCAM_LCD_CTRL1_REG (DR_REG_LCDCAM_BASE + 0x20) +/** LCDCAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ +#define LCDCAM_LCD_VB_FRONT 0x000000FFU +#define LCDCAM_LCD_VB_FRONT_M (LCDCAM_LCD_VB_FRONT_V << LCDCAM_LCD_VB_FRONT_S) +#define LCDCAM_LCD_VB_FRONT_V 0x000000FFU +#define LCDCAM_LCD_VB_FRONT_S 0 +/** LCDCAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ +#define LCDCAM_LCD_HA_WIDTH 0x00000FFFU +#define LCDCAM_LCD_HA_WIDTH_M (LCDCAM_LCD_HA_WIDTH_V << LCDCAM_LCD_HA_WIDTH_S) +#define LCDCAM_LCD_HA_WIDTH_V 0x00000FFFU +#define LCDCAM_LCD_HA_WIDTH_S 8 +/** LCDCAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ +#define LCDCAM_LCD_HT_WIDTH 0x00000FFFU +#define LCDCAM_LCD_HT_WIDTH_M (LCDCAM_LCD_HT_WIDTH_V << LCDCAM_LCD_HT_WIDTH_S) +#define LCDCAM_LCD_HT_WIDTH_V 0x00000FFFU +#define LCDCAM_LCD_HT_WIDTH_S 20 + +/** LCDCAM_LCD_CTRL2_REG register + * LCD config register. + */ +#define LCDCAM_LCD_CTRL2_REG (DR_REG_LCDCAM_BASE + 0x24) +/** LCDCAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1; + * It is the position of LCD_VSYNC active pulse in a line. + */ +#define LCDCAM_LCD_VSYNC_WIDTH 0x0000007FU +#define LCDCAM_LCD_VSYNC_WIDTH_M (LCDCAM_LCD_VSYNC_WIDTH_V << LCDCAM_LCD_VSYNC_WIDTH_S) +#define LCDCAM_LCD_VSYNC_WIDTH_V 0x0000007FU +#define LCDCAM_LCD_VSYNC_WIDTH_S 0 +/** LCDCAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0; + * It is the idle value of LCD_VSYNC. + */ +#define LCDCAM_LCD_VSYNC_IDLE_POL (BIT(7)) +#define LCDCAM_LCD_VSYNC_IDLE_POL_M (LCDCAM_LCD_VSYNC_IDLE_POL_V << LCDCAM_LCD_VSYNC_IDLE_POL_S) +#define LCDCAM_LCD_VSYNC_IDLE_POL_V 0x00000001U +#define LCDCAM_LCD_VSYNC_IDLE_POL_S 7 +/** LCDCAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0; + * It is the idle value of LCD_DE. + */ +#define LCDCAM_LCD_DE_IDLE_POL (BIT(8)) +#define LCDCAM_LCD_DE_IDLE_POL_M (LCDCAM_LCD_DE_IDLE_POL_V << LCDCAM_LCD_DE_IDLE_POL_S) +#define LCDCAM_LCD_DE_IDLE_POL_V 0x00000001U +#define LCDCAM_LCD_DE_IDLE_POL_S 8 +/** LCDCAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0; + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC + * pulse is valid only in active region lines in RGB mode. + */ +#define LCDCAM_LCD_HS_BLANK_EN (BIT(9)) +#define LCDCAM_LCD_HS_BLANK_EN_M (LCDCAM_LCD_HS_BLANK_EN_V << LCDCAM_LCD_HS_BLANK_EN_S) +#define LCDCAM_LCD_HS_BLANK_EN_V 0x00000001U +#define LCDCAM_LCD_HS_BLANK_EN_S 9 +/** LCDCAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1; + * It is the position of LCD_HSYNC active pulse in a line. + */ +#define LCDCAM_LCD_HSYNC_WIDTH 0x0000007FU +#define LCDCAM_LCD_HSYNC_WIDTH_M (LCDCAM_LCD_HSYNC_WIDTH_V << LCDCAM_LCD_HSYNC_WIDTH_S) +#define LCDCAM_LCD_HSYNC_WIDTH_V 0x0000007FU +#define LCDCAM_LCD_HSYNC_WIDTH_S 16 +/** LCDCAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0; + * It is the idle value of LCD_HSYNC. + */ +#define LCDCAM_LCD_HSYNC_IDLE_POL (BIT(23)) +#define LCDCAM_LCD_HSYNC_IDLE_POL_M (LCDCAM_LCD_HSYNC_IDLE_POL_V << LCDCAM_LCD_HSYNC_IDLE_POL_S) +#define LCDCAM_LCD_HSYNC_IDLE_POL_V 0x00000001U +#define LCDCAM_LCD_HSYNC_IDLE_POL_S 23 +/** LCDCAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0; + * It is the position of LCD_HSYNC active pulse in a line. + */ +#define LCDCAM_LCD_HSYNC_POSITION 0x000000FFU +#define LCDCAM_LCD_HSYNC_POSITION_M (LCDCAM_LCD_HSYNC_POSITION_V << LCDCAM_LCD_HSYNC_POSITION_S) +#define LCDCAM_LCD_HSYNC_POSITION_V 0x000000FFU +#define LCDCAM_LCD_HSYNC_POSITION_S 24 + +/** LCDCAM_LCD_FIRST_CMD_VAL_REG register + * LCD config register. + */ +#define LCDCAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x28) +/** LCDCAM_LCD_FIRST_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of first cmd cycle. + */ +#define LCDCAM_LCD_FIRST_CMD_VALUE 0xFFFFFFFFU +#define LCDCAM_LCD_FIRST_CMD_VALUE_M (LCDCAM_LCD_FIRST_CMD_VALUE_V << LCDCAM_LCD_FIRST_CMD_VALUE_S) +#define LCDCAM_LCD_FIRST_CMD_VALUE_V 0xFFFFFFFFU +#define LCDCAM_LCD_FIRST_CMD_VALUE_S 0 + +/** LCDCAM_LCD_LATTER_CMD_VAL_REG register + * LCD config register. + */ +#define LCDCAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCDCAM_BASE + 0x2c) +/** LCDCAM_LCD_LATTER_CMD_VALUE : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of latter cmd cycle. + */ +#define LCDCAM_LCD_LATTER_CMD_VALUE 0xFFFFFFFFU +#define LCDCAM_LCD_LATTER_CMD_VALUE_M (LCDCAM_LCD_LATTER_CMD_VALUE_V << LCDCAM_LCD_LATTER_CMD_VALUE_S) +#define LCDCAM_LCD_LATTER_CMD_VALUE_V 0xFFFFFFFFU +#define LCDCAM_LCD_LATTER_CMD_VALUE_S 0 + +/** LCDCAM_LCD_DLY_MODE_CFG1_REG register + * LCD config register. + */ +#define LCDCAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCDCAM_BASE + 0x30) +/** LCDCAM_DOUT16_MODE : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT16_MODE 0x00000003U +#define LCDCAM_DOUT16_MODE_M (LCDCAM_DOUT16_MODE_V << LCDCAM_DOUT16_MODE_S) +#define LCDCAM_DOUT16_MODE_V 0x00000003U +#define LCDCAM_DOUT16_MODE_S 0 +/** LCDCAM_DOUT17_MODE : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT17_MODE 0x00000003U +#define LCDCAM_DOUT17_MODE_M (LCDCAM_DOUT17_MODE_V << LCDCAM_DOUT17_MODE_S) +#define LCDCAM_DOUT17_MODE_V 0x00000003U +#define LCDCAM_DOUT17_MODE_S 2 +/** LCDCAM_DOUT18_MODE : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT18_MODE 0x00000003U +#define LCDCAM_DOUT18_MODE_M (LCDCAM_DOUT18_MODE_V << LCDCAM_DOUT18_MODE_S) +#define LCDCAM_DOUT18_MODE_V 0x00000003U +#define LCDCAM_DOUT18_MODE_S 4 +/** LCDCAM_DOUT19_MODE : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT19_MODE 0x00000003U +#define LCDCAM_DOUT19_MODE_M (LCDCAM_DOUT19_MODE_V << LCDCAM_DOUT19_MODE_S) +#define LCDCAM_DOUT19_MODE_V 0x00000003U +#define LCDCAM_DOUT19_MODE_S 6 +/** LCDCAM_DOUT20_MODE : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT20_MODE 0x00000003U +#define LCDCAM_DOUT20_MODE_M (LCDCAM_DOUT20_MODE_V << LCDCAM_DOUT20_MODE_S) +#define LCDCAM_DOUT20_MODE_V 0x00000003U +#define LCDCAM_DOUT20_MODE_S 8 +/** LCDCAM_DOUT21_MODE : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT21_MODE 0x00000003U +#define LCDCAM_DOUT21_MODE_M (LCDCAM_DOUT21_MODE_V << LCDCAM_DOUT21_MODE_S) +#define LCDCAM_DOUT21_MODE_V 0x00000003U +#define LCDCAM_DOUT21_MODE_S 10 +/** LCDCAM_DOUT22_MODE : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT22_MODE 0x00000003U +#define LCDCAM_DOUT22_MODE_M (LCDCAM_DOUT22_MODE_V << LCDCAM_DOUT22_MODE_S) +#define LCDCAM_DOUT22_MODE_V 0x00000003U +#define LCDCAM_DOUT22_MODE_S 12 +/** LCDCAM_DOUT23_MODE : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT23_MODE 0x00000003U +#define LCDCAM_DOUT23_MODE_M (LCDCAM_DOUT23_MODE_V << LCDCAM_DOUT23_MODE_S) +#define LCDCAM_DOUT23_MODE_V 0x00000003U +#define LCDCAM_DOUT23_MODE_S 14 +/** LCDCAM_LCD_CD_MODE : R/W; bitpos: [17:16]; default: 0; + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_CD_MODE 0x00000003U +#define LCDCAM_LCD_CD_MODE_M (LCDCAM_LCD_CD_MODE_V << LCDCAM_LCD_CD_MODE_S) +#define LCDCAM_LCD_CD_MODE_V 0x00000003U +#define LCDCAM_LCD_CD_MODE_S 16 +/** LCDCAM_LCD_DE_MODE : R/W; bitpos: [19:18]; default: 0; + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_DE_MODE 0x00000003U +#define LCDCAM_LCD_DE_MODE_M (LCDCAM_LCD_DE_MODE_V << LCDCAM_LCD_DE_MODE_S) +#define LCDCAM_LCD_DE_MODE_V 0x00000003U +#define LCDCAM_LCD_DE_MODE_S 18 +/** LCDCAM_LCD_HSYNC_MODE : R/W; bitpos: [21:20]; default: 0; + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_HSYNC_MODE 0x00000003U +#define LCDCAM_LCD_HSYNC_MODE_M (LCDCAM_LCD_HSYNC_MODE_V << LCDCAM_LCD_HSYNC_MODE_S) +#define LCDCAM_LCD_HSYNC_MODE_V 0x00000003U +#define LCDCAM_LCD_HSYNC_MODE_S 20 +/** LCDCAM_LCD_VSYNC_MODE : R/W; bitpos: [23:22]; default: 0; + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ +#define LCDCAM_LCD_VSYNC_MODE 0x00000003U +#define LCDCAM_LCD_VSYNC_MODE_M (LCDCAM_LCD_VSYNC_MODE_V << LCDCAM_LCD_VSYNC_MODE_S) +#define LCDCAM_LCD_VSYNC_MODE_V 0x00000003U +#define LCDCAM_LCD_VSYNC_MODE_S 22 + +/** LCDCAM_LCD_DLY_MODE_CFG2_REG register + * LCD config register. + */ +#define LCDCAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCDCAM_BASE + 0x38) +/** LCDCAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT0_MODE 0x00000003U +#define LCDCAM_DOUT0_MODE_M (LCDCAM_DOUT0_MODE_V << LCDCAM_DOUT0_MODE_S) +#define LCDCAM_DOUT0_MODE_V 0x00000003U +#define LCDCAM_DOUT0_MODE_S 0 +/** LCDCAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT1_MODE 0x00000003U +#define LCDCAM_DOUT1_MODE_M (LCDCAM_DOUT1_MODE_V << LCDCAM_DOUT1_MODE_S) +#define LCDCAM_DOUT1_MODE_V 0x00000003U +#define LCDCAM_DOUT1_MODE_S 2 +/** LCDCAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT2_MODE 0x00000003U +#define LCDCAM_DOUT2_MODE_M (LCDCAM_DOUT2_MODE_V << LCDCAM_DOUT2_MODE_S) +#define LCDCAM_DOUT2_MODE_V 0x00000003U +#define LCDCAM_DOUT2_MODE_S 4 +/** LCDCAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT3_MODE 0x00000003U +#define LCDCAM_DOUT3_MODE_M (LCDCAM_DOUT3_MODE_V << LCDCAM_DOUT3_MODE_S) +#define LCDCAM_DOUT3_MODE_V 0x00000003U +#define LCDCAM_DOUT3_MODE_S 6 +/** LCDCAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT4_MODE 0x00000003U +#define LCDCAM_DOUT4_MODE_M (LCDCAM_DOUT4_MODE_V << LCDCAM_DOUT4_MODE_S) +#define LCDCAM_DOUT4_MODE_V 0x00000003U +#define LCDCAM_DOUT4_MODE_S 8 +/** LCDCAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT5_MODE 0x00000003U +#define LCDCAM_DOUT5_MODE_M (LCDCAM_DOUT5_MODE_V << LCDCAM_DOUT5_MODE_S) +#define LCDCAM_DOUT5_MODE_V 0x00000003U +#define LCDCAM_DOUT5_MODE_S 10 +/** LCDCAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT6_MODE 0x00000003U +#define LCDCAM_DOUT6_MODE_M (LCDCAM_DOUT6_MODE_V << LCDCAM_DOUT6_MODE_S) +#define LCDCAM_DOUT6_MODE_V 0x00000003U +#define LCDCAM_DOUT6_MODE_S 12 +/** LCDCAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT7_MODE 0x00000003U +#define LCDCAM_DOUT7_MODE_M (LCDCAM_DOUT7_MODE_V << LCDCAM_DOUT7_MODE_S) +#define LCDCAM_DOUT7_MODE_V 0x00000003U +#define LCDCAM_DOUT7_MODE_S 14 +/** LCDCAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT8_MODE 0x00000003U +#define LCDCAM_DOUT8_MODE_M (LCDCAM_DOUT8_MODE_V << LCDCAM_DOUT8_MODE_S) +#define LCDCAM_DOUT8_MODE_V 0x00000003U +#define LCDCAM_DOUT8_MODE_S 16 +/** LCDCAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT9_MODE 0x00000003U +#define LCDCAM_DOUT9_MODE_M (LCDCAM_DOUT9_MODE_V << LCDCAM_DOUT9_MODE_S) +#define LCDCAM_DOUT9_MODE_V 0x00000003U +#define LCDCAM_DOUT9_MODE_S 18 +/** LCDCAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT10_MODE 0x00000003U +#define LCDCAM_DOUT10_MODE_M (LCDCAM_DOUT10_MODE_V << LCDCAM_DOUT10_MODE_S) +#define LCDCAM_DOUT10_MODE_V 0x00000003U +#define LCDCAM_DOUT10_MODE_S 20 +/** LCDCAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT11_MODE 0x00000003U +#define LCDCAM_DOUT11_MODE_M (LCDCAM_DOUT11_MODE_V << LCDCAM_DOUT11_MODE_S) +#define LCDCAM_DOUT11_MODE_V 0x00000003U +#define LCDCAM_DOUT11_MODE_S 22 +/** LCDCAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT12_MODE 0x00000003U +#define LCDCAM_DOUT12_MODE_M (LCDCAM_DOUT12_MODE_V << LCDCAM_DOUT12_MODE_S) +#define LCDCAM_DOUT12_MODE_V 0x00000003U +#define LCDCAM_DOUT12_MODE_S 24 +/** LCDCAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT13_MODE 0x00000003U +#define LCDCAM_DOUT13_MODE_M (LCDCAM_DOUT13_MODE_V << LCDCAM_DOUT13_MODE_S) +#define LCDCAM_DOUT13_MODE_V 0x00000003U +#define LCDCAM_DOUT13_MODE_S 26 +/** LCDCAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT14_MODE 0x00000003U +#define LCDCAM_DOUT14_MODE_M (LCDCAM_DOUT14_MODE_V << LCDCAM_DOUT14_MODE_S) +#define LCDCAM_DOUT14_MODE_V 0x00000003U +#define LCDCAM_DOUT14_MODE_S 28 +/** LCDCAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ +#define LCDCAM_DOUT15_MODE 0x00000003U +#define LCDCAM_DOUT15_MODE_M (LCDCAM_DOUT15_MODE_V << LCDCAM_DOUT15_MODE_S) +#define LCDCAM_DOUT15_MODE_V 0x00000003U +#define LCDCAM_DOUT15_MODE_S 30 + +/** LCDCAM_LC_DMA_INT_ENA_REG register + * LCDCAM interrupt enable register. + */ +#define LCDCAM_LC_DMA_INT_ENA_REG (DR_REG_LCDCAM_BASE + 0x64) +/** LCDCAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_ENA (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_ENA_M (LCDCAM_LCD_VSYNC_INT_ENA_V << LCDCAM_LCD_VSYNC_INT_ENA_S) +#define LCDCAM_LCD_VSYNC_INT_ENA_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_ENA_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_ENA_M (LCDCAM_LCD_TRANS_DONE_INT_ENA_V << LCDCAM_LCD_TRANS_DONE_INT_ENA_S) +#define LCDCAM_LCD_TRANS_DONE_INT_ENA_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_ENA_S 1 +/** LCDCAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_ENA (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_ENA_M (LCDCAM_CAM_VSYNC_INT_ENA_V << LCDCAM_CAM_VSYNC_INT_ENA_S) +#define LCDCAM_CAM_VSYNC_INT_ENA_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_ENA_S 2 +/** LCDCAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for Camera line interrupt. + */ +#define LCDCAM_CAM_HS_INT_ENA (BIT(3)) +#define LCDCAM_CAM_HS_INT_ENA_M (LCDCAM_CAM_HS_INT_ENA_V << LCDCAM_CAM_HS_INT_ENA_S) +#define LCDCAM_CAM_HS_INT_ENA_V 0x00000001U +#define LCDCAM_CAM_HS_INT_ENA_S 3 +/** LCDCAM_LCD_UNDERRUN_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for LCD underrun interrupt + */ +#define LCDCAM_LCD_UNDERRUN_INT_ENA (BIT(4)) +#define LCDCAM_LCD_UNDERRUN_INT_ENA_M (LCDCAM_LCD_UNDERRUN_INT_ENA_V << LCDCAM_LCD_UNDERRUN_INT_ENA_S) +#define LCDCAM_LCD_UNDERRUN_INT_ENA_V 0x00000001U +#define LCDCAM_LCD_UNDERRUN_INT_ENA_S 4 + +/** LCDCAM_LC_DMA_INT_RAW_REG register + * LCDCAM interrupt raw register, valid in level. + */ +#define LCDCAM_LC_DMA_INT_RAW_REG (DR_REG_LCDCAM_BASE + 0x68) +/** LCDCAM_LCD_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_RAW (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_RAW_M (LCDCAM_LCD_VSYNC_INT_RAW_V << LCDCAM_LCD_VSYNC_INT_RAW_S) +#define LCDCAM_LCD_VSYNC_INT_RAW_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_RAW_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_RAW_M (LCDCAM_LCD_TRANS_DONE_INT_RAW_V << LCDCAM_LCD_TRANS_DONE_INT_RAW_S) +#define LCDCAM_LCD_TRANS_DONE_INT_RAW_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_RAW_S 1 +/** LCDCAM_CAM_VSYNC_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_RAW (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_RAW_M (LCDCAM_CAM_VSYNC_INT_RAW_V << LCDCAM_CAM_VSYNC_INT_RAW_S) +#define LCDCAM_CAM_VSYNC_INT_RAW_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_RAW_S 2 +/** LCDCAM_CAM_HS_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for Camera line interrupt. + */ +#define LCDCAM_CAM_HS_INT_RAW (BIT(3)) +#define LCDCAM_CAM_HS_INT_RAW_M (LCDCAM_CAM_HS_INT_RAW_V << LCDCAM_CAM_HS_INT_RAW_S) +#define LCDCAM_CAM_HS_INT_RAW_V 0x00000001U +#define LCDCAM_CAM_HS_INT_RAW_S 3 +/** LCDCAM_LCD_UNDERRUN_INT_RAW : RO/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for LCD underrun interrupt + */ +#define LCDCAM_LCD_UNDERRUN_INT_RAW (BIT(4)) +#define LCDCAM_LCD_UNDERRUN_INT_RAW_M (LCDCAM_LCD_UNDERRUN_INT_RAW_V << LCDCAM_LCD_UNDERRUN_INT_RAW_S) +#define LCDCAM_LCD_UNDERRUN_INT_RAW_V 0x00000001U +#define LCDCAM_LCD_UNDERRUN_INT_RAW_S 4 + +/** LCDCAM_LC_DMA_INT_ST_REG register + * LCDCAM interrupt status register. + */ +#define LCDCAM_LC_DMA_INT_ST_REG (DR_REG_LCDCAM_BASE + 0x6c) +/** LCDCAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_ST (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_ST_M (LCDCAM_LCD_VSYNC_INT_ST_V << LCDCAM_LCD_VSYNC_INT_ST_S) +#define LCDCAM_LCD_VSYNC_INT_ST_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_ST_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_ST (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_ST_M (LCDCAM_LCD_TRANS_DONE_INT_ST_V << LCDCAM_LCD_TRANS_DONE_INT_ST_S) +#define LCDCAM_LCD_TRANS_DONE_INT_ST_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_ST_S 1 +/** LCDCAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_ST (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_ST_M (LCDCAM_CAM_VSYNC_INT_ST_V << LCDCAM_CAM_VSYNC_INT_ST_S) +#define LCDCAM_CAM_VSYNC_INT_ST_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_ST_S 2 +/** LCDCAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for Camera transfer end interrupt. + */ +#define LCDCAM_CAM_HS_INT_ST (BIT(3)) +#define LCDCAM_CAM_HS_INT_ST_M (LCDCAM_CAM_HS_INT_ST_V << LCDCAM_CAM_HS_INT_ST_S) +#define LCDCAM_CAM_HS_INT_ST_V 0x00000001U +#define LCDCAM_CAM_HS_INT_ST_S 3 +/** LCDCAM_LCD_UNDERRUN_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for LCD underrun interrupt + */ +#define LCDCAM_LCD_UNDERRUN_INT_ST (BIT(4)) +#define LCDCAM_LCD_UNDERRUN_INT_ST_M (LCDCAM_LCD_UNDERRUN_INT_ST_V << LCDCAM_LCD_UNDERRUN_INT_ST_S) +#define LCDCAM_LCD_UNDERRUN_INT_ST_V 0x00000001U +#define LCDCAM_LCD_UNDERRUN_INT_ST_S 4 + +/** LCDCAM_LC_DMA_INT_CLR_REG register + * LCDCAM interrupt clear register. + */ +#define LCDCAM_LC_DMA_INT_CLR_REG (DR_REG_LCDCAM_BASE + 0x70) +/** LCDCAM_LCD_VSYNC_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for LCD frame end interrupt. + */ +#define LCDCAM_LCD_VSYNC_INT_CLR (BIT(0)) +#define LCDCAM_LCD_VSYNC_INT_CLR_M (LCDCAM_LCD_VSYNC_INT_CLR_V << LCDCAM_LCD_VSYNC_INT_CLR_S) +#define LCDCAM_LCD_VSYNC_INT_CLR_V 0x00000001U +#define LCDCAM_LCD_VSYNC_INT_CLR_S 0 +/** LCDCAM_LCD_TRANS_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for lcd transfer end interrupt. + */ +#define LCDCAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) +#define LCDCAM_LCD_TRANS_DONE_INT_CLR_M (LCDCAM_LCD_TRANS_DONE_INT_CLR_V << LCDCAM_LCD_TRANS_DONE_INT_CLR_S) +#define LCDCAM_LCD_TRANS_DONE_INT_CLR_V 0x00000001U +#define LCDCAM_LCD_TRANS_DONE_INT_CLR_S 1 +/** LCDCAM_CAM_VSYNC_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for Camera frame end interrupt. + */ +#define LCDCAM_CAM_VSYNC_INT_CLR (BIT(2)) +#define LCDCAM_CAM_VSYNC_INT_CLR_M (LCDCAM_CAM_VSYNC_INT_CLR_V << LCDCAM_CAM_VSYNC_INT_CLR_S) +#define LCDCAM_CAM_VSYNC_INT_CLR_V 0x00000001U +#define LCDCAM_CAM_VSYNC_INT_CLR_S 2 +/** LCDCAM_CAM_HS_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for Camera line interrupt. + */ +#define LCDCAM_CAM_HS_INT_CLR (BIT(3)) +#define LCDCAM_CAM_HS_INT_CLR_M (LCDCAM_CAM_HS_INT_CLR_V << LCDCAM_CAM_HS_INT_CLR_S) +#define LCDCAM_CAM_HS_INT_CLR_V 0x00000001U +#define LCDCAM_CAM_HS_INT_CLR_S 3 +/** LCDCAM_LCD_UNDERRUN_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for LCD underrun interrupt + */ +#define LCDCAM_LCD_UNDERRUN_INT_CLR (BIT(4)) +#define LCDCAM_LCD_UNDERRUN_INT_CLR_M (LCDCAM_LCD_UNDERRUN_INT_CLR_V << LCDCAM_LCD_UNDERRUN_INT_CLR_S) +#define LCDCAM_LCD_UNDERRUN_INT_CLR_V 0x00000001U +#define LCDCAM_LCD_UNDERRUN_INT_CLR_S 4 + +/** LCDCAM_LC_REG_DATE_REG register + * Version register + */ +#define LCDCAM_LC_REG_DATE_REG (DR_REG_LCDCAM_BASE + 0xfc) +/** LCDCAM_LC_DATE : R/W; bitpos: [27:0]; default: 38806054; + * LCD_CAM version control register + */ +#define LCDCAM_LC_DATE 0x0FFFFFFFU +#define LCDCAM_LC_DATE_M (LCDCAM_LC_DATE_V << LCDCAM_LC_DATE_S) +#define LCDCAM_LC_DATE_V 0x0FFFFFFFU +#define LCDCAM_LC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_struct.h new file mode 100644 index 0000000000..470ef9961a --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lcd_cam_struct.h @@ -0,0 +1,857 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: lcd configuration registers */ +/** Type of lcd_clock register + * LCD clock config register. + */ +typedef union { + struct { + /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3; + * f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + */ + uint32_t lcd_clkcnt_n:6; + /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1; + * 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + */ + uint32_t lcd_clk_equ_sysclk:1; + /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0; + * 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + */ + uint32_t lcd_ck_idle_edge:1; + /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0; + * 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low + * in the second half data cycle. + */ + uint32_t lcd_ck_out_edge:1; + /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4; + * Integral LCD clock divider value + */ + uint32_t lcd_clkm_div_num:8; + /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t lcd_clkm_div_b:6; + /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t lcd_clkm_div_a:6; + /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0; + * Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ + uint32_t lcd_clk_sel:2; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lcdcam_lcd_clock_reg_t; + +/** Type of lcd_rgb_yuv register + * LCD YUV/RGB converter configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ + uint32_t lcd_conv_8bits_data_inv:1; + /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0; + * 0: txtorx mode off. 1: txtorx mode on. + */ + uint32_t lcd_conv_txtorx:1; + /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ + uint32_t lcd_conv_yuv2yuv_mode:2; + /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ + uint32_t lcd_conv_yuv_mode:2; + /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ + uint32_t lcd_conv_protocol_mode:1; + /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ + uint32_t lcd_conv_data_out_mode:1; + /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ + uint32_t lcd_conv_data_in_mode:1; + /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ + uint32_t lcd_conv_mode_8bits_on:1; + /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ + uint32_t lcd_conv_trans_mode:1; + /** lcd_conv_enable : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ + uint32_t lcd_conv_enable:1; + }; + uint32_t val; +} lcdcam_lcd_rgb_yuv_reg_t; + +/** Type of lcd_user register + * LCD config register. + */ +typedef union { + struct { + /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1; + * The output data cycles minus 1 of LCD module. + */ + uint32_t lcd_dout_cyclelen:13; + /** lcd_always_out_en : R/W; bitpos: [13]; default: 0; + * LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or + * reg_lcd_reset is set. + */ + uint32_t lcd_always_out_en:1; + /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0; + * 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + */ + uint32_t lcd_dout_byte_swizzle_mode:3; + /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0; + * 1: enable byte swizzle 0: disable + */ + uint32_t lcd_dout_byte_swizzle_enable:1; + /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0; + * 1: change bit order in every byte. 0: Not change. + */ + uint32_t lcd_dout_bit_order:1; + /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0; + * 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + */ + uint32_t lcd_byte_mode:2; + /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0; + * 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + */ + uint32_t lcd_update_reg:1; + /** lcd_bit_order : R/W; bitpos: [22]; default: 0; + * 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ + uint32_t lcd_bit_order:1; + /** lcd_byte_order : R/W; bitpos: [23]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ + uint32_t lcd_byte_order:1; + /** lcd_dout : R/W; bitpos: [24]; default: 0; + * 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_dout:1; + /** lcd_dummy : R/W; bitpos: [25]; default: 0; + * 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_dummy:1; + /** lcd_cmd : R/W; bitpos: [26]; default: 0; + * 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + */ + uint32_t lcd_cmd:1; + /** lcd_start : R/W/SC; bitpos: [27]; default: 0; + * LCD start sending data enable signal, valid in high level. + */ + uint32_t lcd_start:1; + /** lcd_reset : WT; bitpos: [28]; default: 0; + * The value of command. + */ + uint32_t lcd_reset:1; + /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0; + * The dummy cycle length minus 1. + */ + uint32_t lcd_dummy_cyclelen:2; + /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0; + * The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + */ + uint32_t lcd_cmd_2_cycle_en:1; + }; + uint32_t val; +} lcdcam_lcd_user_reg_t; + +/** Type of lcd_misc register + * LCD config register. + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0; + * The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + */ + uint32_t lcd_wire_mode:2; + /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3; + * The setup cycle length minus 1 in LCD non-RGB mode. + */ + uint32_t lcd_vfk_cyclelen:6; + /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0; + * The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold + * time cycle length in LCD non-RGB mode. + */ + uint32_t lcd_vbk_cyclelen:13; + /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0; + * 1: Send the next frame data when the current frame is sent out. 0: LCD stops when + * the current frame is sent out. + */ + uint32_t lcd_next_frame_en:1; + /** lcd_bk_en : R/W; bitpos: [26]; default: 0; + * 1: Enable blank region when LCD sends data out. 0: No blank region. + */ + uint32_t lcd_bk_en:1; + /** lcd_afifo_reset : WT; bitpos: [27]; default: 0; + * LCD AFIFO reset signal. + */ + uint32_t lcd_afifo_reset:1; + /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_data_set:1; + /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_dummy_set:1; + /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0; + * 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = + * reg_cd_idle_edge. + */ + uint32_t lcd_cd_cmd_set:1; + /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0; + * The default value of LCD_CD. + */ + uint32_t lcd_cd_idle_edge:1; + }; + uint32_t val; +} lcdcam_lcd_misc_reg_t; + +/** Type of lcd_ctrl register + * LCD config register. + */ +typedef union { + struct { + /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ + uint32_t lcd_hb_front:11; + /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ + uint32_t lcd_va_height:10; + /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ + uint32_t lcd_vt_height:10; + /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + */ + uint32_t lcd_rgb_mode_en:1; + }; + uint32_t val; +} lcdcam_lcd_ctrl_reg_t; + +/** Type of lcd_ctrl1 register + * LCD config register. + */ +typedef union { + struct { + /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ + uint32_t lcd_vb_front:8; + /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ + uint32_t lcd_ha_width:12; + /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ + uint32_t lcd_ht_width:12; + }; + uint32_t val; +} lcdcam_lcd_ctrl1_reg_t; + +/** Type of lcd_ctrl2 register + * LCD config register. + */ +typedef union { + struct { + /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; + * It is the position of LCD_VSYNC active pulse in a line. + */ + uint32_t lcd_vsync_width:7; + /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0; + * It is the idle value of LCD_VSYNC. + */ + uint32_t lcd_vsync_idle_pol:1; + /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0; + * It is the idle value of LCD_DE. + */ + uint32_t lcd_de_idle_pol:1; + /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0; + * 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC + * pulse is valid only in active region lines in RGB mode. + */ + uint32_t lcd_hs_blank_en:1; + uint32_t reserved_10:6; + /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; + * It is the position of LCD_HSYNC active pulse in a line. + */ + uint32_t lcd_hsync_width:7; + /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0; + * It is the idle value of LCD_HSYNC. + */ + uint32_t lcd_hsync_idle_pol:1; + /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; + * It is the position of LCD_HSYNC active pulse in a line. + */ + uint32_t lcd_hsync_position:8; + }; + uint32_t val; +} lcdcam_lcd_ctrl2_reg_t; + +/** Type of lcd_first_cmd_val register + * LCD config register. + */ +typedef union { + struct { + /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of first cmd cycle. + */ + uint32_t lcd_first_cmd_value:32; + }; + uint32_t val; +} lcdcam_lcd_first_cmd_val_reg_t; + +/** Type of lcd_latter_cmd_val register + * LCD config register. + */ +typedef union { + struct { + /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0; + * The LCD write command value of latter cmd cycle. + */ + uint32_t lcd_latter_cmd_value:32; + }; + uint32_t val; +} lcdcam_lcd_latter_cmd_val_reg_t; + +/** Type of lcd_dly_mode_cfg1 register + * LCD config register. + */ +typedef union { + struct { + /** dout16_mode : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout16_mode:2; + /** dout17_mode : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout17_mode:2; + /** dout18_mode : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout18_mode:2; + /** dout19_mode : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout19_mode:2; + /** dout20_mode : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout20_mode:2; + /** dout21_mode : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout21_mode:2; + /** dout22_mode : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout22_mode:2; + /** dout23_mode : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout23_mode:2; + /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0; + * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_cd_mode:2; + /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0; + * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: + * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_de_mode:2; + /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0; + * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_hsync_mode:2; + /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0; + * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. + * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + */ + uint32_t lcd_vsync_mode:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} lcdcam_lcd_dly_mode_cfg1_reg_t; + +/** Type of lcd_dly_mode_cfg2 register + * LCD config register. + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [1:0]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout0_mode:2; + /** dout1_mode : R/W; bitpos: [3:2]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout1_mode:2; + /** dout2_mode : R/W; bitpos: [5:4]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout2_mode:2; + /** dout3_mode : R/W; bitpos: [7:6]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout3_mode:2; + /** dout4_mode : R/W; bitpos: [9:8]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout4_mode:2; + /** dout5_mode : R/W; bitpos: [11:10]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout5_mode:2; + /** dout6_mode : R/W; bitpos: [13:12]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout6_mode:2; + /** dout7_mode : R/W; bitpos: [15:14]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout7_mode:2; + /** dout8_mode : R/W; bitpos: [17:16]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout8_mode:2; + /** dout9_mode : R/W; bitpos: [19:18]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout9_mode:2; + /** dout10_mode : R/W; bitpos: [21:20]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout10_mode:2; + /** dout11_mode : R/W; bitpos: [23:22]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout11_mode:2; + /** dout12_mode : R/W; bitpos: [25:24]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout12_mode:2; + /** dout13_mode : R/W; bitpos: [27:26]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout13_mode:2; + /** dout14_mode : R/W; bitpos: [29:28]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout14_mode:2; + /** dout15_mode : R/W; bitpos: [31:30]; default: 0; + * The output data bit $n is delayed by module clock LCD_CLK. 0: output without + * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of + * LCD_CLK. + */ + uint32_t dout15_mode:2; + }; + uint32_t val; +} lcdcam_lcd_dly_mode_cfg2_reg_t; + + +/** Group: cam configuration registers */ +/** Type of cam_ctrl register + * CAM config register. + */ +typedef union { + struct { + /** cam_stop_en : R/W; bitpos: [0]; default: 0; + * Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + */ + uint32_t cam_stop_en:1; + /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0; + * Filter threshold value for CAM_VSYNC signal. + */ + uint32_t cam_vsync_filter_thres:3; + /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0; + * 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + */ + uint32_t cam_update_reg:1; + /** cam_byte_order : R/W; bitpos: [5]; default: 0; + * 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte + * mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + */ + uint32_t cam_byte_order:1; + /** cam_bit_order : R/W; bitpos: [6]; default: 0; + * 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + */ + uint32_t cam_bit_order:1; + /** cam_line_int_en : R/W; bitpos: [7]; default: 0; + * 1: Enable to generate CAM_HS_INT. 0: Disable. + */ + uint32_t cam_line_int_en:1; + /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0; + * 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by + * reg_cam_rec_data_cyclelen. + */ + uint32_t cam_vs_eof_en:1; + /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4; + * Integral Camera clock divider value + */ + uint32_t cam_clkm_div_num:8; + /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0; + * Fractional clock divider numerator value + */ + uint32_t cam_clkm_div_b:6; + /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0; + * Fractional clock divider denominator value + */ + uint32_t cam_clkm_div_a:6; + /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0; + * Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + */ + uint32_t cam_clk_sel:2; + uint32_t reserved_31:1; + }; + uint32_t val; +} lcdcam_cam_ctrl_reg_t; + +/** Type of cam_ctrl1 register + * CAM config register. + */ +typedef union { + struct { + /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0; + * Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + */ + uint32_t cam_rec_data_bytelen:16; + /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0; + * The line number minus 1 to generate cam_hs_int. + */ + uint32_t cam_line_int_num:6; + /** cam_clk_inv : R/W; bitpos: [22]; default: 0; + * 1: Invert the input signal CAM_PCLK. 0: Not invert. + */ + uint32_t cam_clk_inv:1; + /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0; + * 1: Enable CAM_VSYNC filter function. 0: bypass. + */ + uint32_t cam_vsync_filter_en:1; + /** cam_2byte_en : R/W; bitpos: [24]; default: 0; + * 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + */ + uint32_t cam_2byte_en:1; + /** cam_de_inv : R/W; bitpos: [25]; default: 0; + * CAM_DE invert enable signal, valid in high level. + */ + uint32_t cam_de_inv:1; + /** cam_hsync_inv : R/W; bitpos: [26]; default: 0; + * CAM_HSYNC invert enable signal, valid in high level. + */ + uint32_t cam_hsync_inv:1; + /** cam_vsync_inv : R/W; bitpos: [27]; default: 0; + * CAM_VSYNC invert enable signal, valid in high level. + */ + uint32_t cam_vsync_inv:1; + /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0; + * 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control + * signals are CAM_DE and CAM_VSYNC. + */ + uint32_t cam_vh_de_mode_en:1; + /** cam_start : R/W/SC; bitpos: [29]; default: 0; + * Camera module start signal. + */ + uint32_t cam_start:1; + /** cam_reset : WT; bitpos: [30]; default: 0; + * Camera module reset signal. + */ + uint32_t cam_reset:1; + /** cam_afifo_reset : WT; bitpos: [31]; default: 0; + * Camera AFIFO reset signal. + */ + uint32_t cam_afifo_reset:1; + }; + uint32_t val; +} lcdcam_cam_ctrl1_reg_t; + +/** Type of cam_rgb_yuv register + * CAM YUV/RGB converter configuration register. + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0; + * 1:invert every two 8bits input data. 2. disabled. + */ + uint32_t cam_conv_8bits_data_inv:1; + /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3; + * 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, + * trans_mode must be set to 1. + */ + uint32_t cam_conv_yuv2yuv_mode:2; + /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0; + * 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv + * mode of Data_in + */ + uint32_t cam_conv_yuv_mode:2; + /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0; + * 0:BT601. 1:BT709. + */ + uint32_t cam_conv_protocol_mode:1; + /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0; + * LIMIT or FULL mode of Data out. 0: limit. 1: full + */ + uint32_t cam_conv_data_out_mode:1; + /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0; + * LIMIT or FULL mode of Data in. 0: limit. 1: full + */ + uint32_t cam_conv_data_in_mode:1; + /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0; + * 0: 16bits mode. 1: 8bits mode. + */ + uint32_t cam_conv_mode_8bits_on:1; + /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0; + * 0: YUV to RGB. 1: RGB to YUV. + */ + uint32_t cam_conv_trans_mode:1; + /** cam_conv_enable : R/W; bitpos: [31]; default: 0; + * 0: Bypass converter. 1: Enable converter. + */ + uint32_t cam_conv_enable:1; + }; + uint32_t val; +} lcdcam_cam_rgb_yuv_reg_t; + + +/** Group: Interrupt registers */ +/** Type of lc_dma_int_ena register + * LCDCAM interrupt enable register. + */ +typedef union { + struct { + /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_ena:1; + /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_ena:1; + /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_ena:1; + /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for Camera line interrupt. + */ + uint32_t cam_hs_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_ena_reg_t; + +/** Type of lc_dma_int_raw register + * LCDCAM interrupt raw register, valid in level. + */ +typedef union { + struct { + /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_raw:1; + /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_raw:1; + /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_raw:1; + /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for Camera line interrupt. + */ + uint32_t cam_hs_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_raw_reg_t; + +/** Type of lc_dma_int_st register + * LCDCAM interrupt status register. + */ +typedef union { + struct { + /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0; + * The status bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_st:1; + /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0; + * The status bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_st:1; + /** cam_vsync_int_st : RO; bitpos: [2]; default: 0; + * The status bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_st:1; + /** cam_hs_int_st : RO; bitpos: [3]; default: 0; + * The status bit for Camera transfer end interrupt. + */ + uint32_t cam_hs_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_st_reg_t; + +/** Type of lc_dma_int_clr register + * LCDCAM interrupt clear register. + */ +typedef union { + struct { + /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for LCD frame end interrupt. + */ + uint32_t lcd_vsync_int_clr:1; + /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for lcd transfer end interrupt. + */ + uint32_t lcd_trans_done_int_clr:1; + /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for Camera frame end interrupt. + */ + uint32_t cam_vsync_int_clr:1; + /** cam_hs_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for Camera line interrupt. + */ + uint32_t cam_hs_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lcdcam_lc_dma_int_clr_reg_t; + + +/** Group: Version register */ +/** Type of lc_reg_date register + * Version register + */ +typedef union { + struct { + /** lc_date : R/W; bitpos: [27:0]; default: 36712592; + * LCD_CAM version control register + */ + uint32_t lc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lcdcam_lc_reg_date_reg_t; + + +typedef struct lcd_cam_dev_t { + volatile lcdcam_lcd_clock_reg_t lcd_clock; + volatile lcdcam_cam_ctrl_reg_t cam_ctrl; + volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1; + volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv; + volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv; + volatile lcdcam_lcd_user_reg_t lcd_user; + volatile lcdcam_lcd_misc_reg_t lcd_misc; + volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl; + volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1; + volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2; + volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val; + volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val; + volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1; + uint32_t reserved_034; + volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2; + uint32_t reserved_03c[10]; + volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena; + volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw; + volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st; + volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr; + uint32_t reserved_074[34]; + volatile lcdcam_lc_reg_date_reg_t lc_reg_date; +} lcd_cam_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure"); +#endif + +extern lcd_cam_dev_t LCD_CAM; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ledc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ledc_eco5_reg.h new file mode 100644 index 0000000000..b10ff9f379 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ledc_eco5_reg.h @@ -0,0 +1,3116 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 0 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 0. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 0 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH0 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, + * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel + * 0, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt + * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 0. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 0. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 0. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 0. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 1 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 1. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 1 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH1 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, + * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel + * 1, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt + * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 1. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 1. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 1. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 1. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 2 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 2. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 2 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH2 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, + * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel + * 2, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt + * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 2. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 2. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 2. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 2. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 3 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 3. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 3 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH3 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, + * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel + * 3, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt + * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 3. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 3. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 3. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 3. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 4 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 4. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 4 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH4 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, + * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel + * 4, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt + * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 4. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 4. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 4. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 4. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 5 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 5. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 5 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH5 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, + * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel + * 5, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt + * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 5. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 5. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 5. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 5. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_CH6_CONF0_REG register + * Configuration register 0 for channel 6 + */ +#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) +/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 6 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH6 0x00000003U +#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) +#define LEDC_TIMER_SEL_CH6_V 0x00000003U +#define LEDC_TIMER_SEL_CH6_S 0 +/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 6. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) +#define LEDC_SIG_OUT_EN_CH6_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH6_S 2 +/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 6 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH6 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH6 (BIT(3)) +#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) +#define LEDC_IDLE_LV_CH6_V 0x00000001U +#define LEDC_IDLE_LV_CH6_S 3 +/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, + * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, + * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel + * 6, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH6 (BIT(4)) +#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) +#define LEDC_PARA_UP_CH6_V 0x00000001U +#define LEDC_PARA_UP_CH6_S 4 +/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt + * will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times. + */ +#define LEDC_OVF_NUM_CH6 0x000003FFU +#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) +#define LEDC_OVF_NUM_CH6_V 0x000003FFU +#define LEDC_OVF_NUM_CH6_S 5 +/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 6. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) +#define LEDC_OVF_CNT_EN_CH6_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH6_S 15 +/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 6. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) +#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH6_S 16 + +/** LEDC_CH6_HPOINT_REG register + * High point register for channel 6 + */ +#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) +/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 6. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH6 0x000FFFFFU +#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) +#define LEDC_HPOINT_CH6_V 0x000FFFFFU +#define LEDC_HPOINT_CH6_S 0 + +/** LEDC_CH6_DUTY_REG register + * Initial duty cycle register for channel 6 + */ +#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) +/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 6. + */ +#define LEDC_DUTY_CH6 0x01FFFFFFU +#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) +#define LEDC_DUTY_CH6_V 0x01FFFFFFU +#define LEDC_DUTY_CH6_S 0 + +/** LEDC_CH6_CONF1_REG register + * Configuration register 1 for channel 6 + */ +#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) +/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH6 (BIT(31)) +#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) +#define LEDC_DUTY_START_CH6_V 0x00000001U +#define LEDC_DUTY_START_CH6_S 31 + +/** LEDC_CH6_DUTY_R_REG register + * Current duty cycle register for channel 6 + */ +#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) +/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 6. + */ +#define LEDC_DUTY_CH6_R 0x01FFFFFFU +#define LEDC_DUTY_CH6_R_M (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S) +#define LEDC_DUTY_CH6_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH6_R_S 0 + +/** LEDC_CH7_CONF0_REG register + * Configuration register 0 for channel 7 + */ +#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) +/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 7 selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH7 0x00000003U +#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) +#define LEDC_TIMER_SEL_CH7_V 0x00000003U +#define LEDC_TIMER_SEL_CH7_S 0 +/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 7. + * 0: Signal output disable + * 1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) +#define LEDC_SIG_OUT_EN_CH7_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH7_S 2 +/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 7 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH7 is 0. + * 0: Output level is low + * 1: Output level is high + */ +#define LEDC_IDLE_LV_CH7 (BIT(3)) +#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) +#define LEDC_IDLE_LV_CH7_V 0x00000001U +#define LEDC_IDLE_LV_CH7_S 3 +/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, + * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, + * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel + * 7, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_PARA_UP_CH7 (BIT(4)) +#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) +#define LEDC_PARA_UP_CH7_V 0x00000001U +#define LEDC_PARA_UP_CH7_S 4 +/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt + * will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times. + */ +#define LEDC_OVF_NUM_CH7 0x000003FFU +#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) +#define LEDC_OVF_NUM_CH7_V 0x000003FFU +#define LEDC_OVF_NUM_CH7_S 5 +/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 7. + * 0: Disable + * 1: Enable + */ +#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) +#define LEDC_OVF_CNT_EN_CH7_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH7_S 15 +/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 7. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) +#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH7_S 16 + +/** LEDC_CH7_HPOINT_REG register + * High point register for channel 7 + */ +#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) +/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 7. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH7 0x000FFFFFU +#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) +#define LEDC_HPOINT_CH7_V 0x000FFFFFU +#define LEDC_HPOINT_CH7_S 0 + +/** LEDC_CH7_DUTY_REG register + * Initial duty cycle register for channel 7 + */ +#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) +/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 7. + */ +#define LEDC_DUTY_CH7 0x01FFFFFFU +#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) +#define LEDC_DUTY_CH7_V 0x01FFFFFFU +#define LEDC_DUTY_CH7_S 0 + +/** LEDC_CH7_CONF1_REG register + * Configuration register 1 for channel 7 + */ +#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) +/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ +#define LEDC_DUTY_START_CH7 (BIT(31)) +#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) +#define LEDC_DUTY_START_CH7_V 0x00000001U +#define LEDC_DUTY_START_CH7_S 31 + +/** LEDC_CH7_DUTY_R_REG register + * Current duty cycle register for channel 7 + */ +#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) +/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 7. + */ +#define LEDC_DUTY_CH7_R 0x01FFFFFFU +#define LEDC_DUTY_CH7_R_M (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S) +#define LEDC_DUTY_CH7_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH7_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration register + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 0. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 0.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 0. + * 0: Normal + * 1: Pause + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 0. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value register + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration register + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 1. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 1.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 1. + * 0: Normal + * 1: Pause + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 1. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value register + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration register + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 2. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 2.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 2. + * 0: Normal + * 1: Pause + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 2. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value register + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration register + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 3. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 3.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 3. + * 0: Normal + * 1: Pause + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 3. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + * 0: Invalid. No effect + * 1: Update + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value register + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Interrupt raw status register + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 +/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + */ +#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) +#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 +/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + */ +#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) +#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 + +/** LEDC_INT_ST_REG register + * Interrupt masked status register + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 +/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only + * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) +#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_ST_S 18 +/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only + * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) +#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_ST_S 19 + +/** LEDC_INT_ENA_REG register + * Interrupt enable register + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 +/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + */ +#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) +#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 +/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + */ +#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) +#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 + +/** LEDC_INT_CLR_REG register + * Interrupt clear register + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 +/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + */ +#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) +#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 +/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + */ +#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) +#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch0. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch0. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch1. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch1. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch2. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch2. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch3. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch3. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch4. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch4. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch5. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch5. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_CH6_GAMMA_CONF_REG register + * Ledc ch6 gamma config register. + */ +#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118) +/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch6. + */ +#define LEDC_CH6_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH6_GAMMA_ENTRY_NUM_M (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S) +#define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH6_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) +#define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH6_GAMMA_PAUSE_S 5 +/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch6. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH6_GAMMA_RESUME (BIT(6)) +#define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) +#define LEDC_CH6_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH6_GAMMA_RESUME_S 6 + +/** LEDC_CH7_GAMMA_CONF_REG register + * Ledc ch7 gamma config register. + */ +#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c) +/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch7. + */ +#define LEDC_CH7_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH7_GAMMA_ENTRY_NUM_M (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S) +#define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Pause + */ +#define LEDC_CH7_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) +#define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH7_GAMMA_PAUSE_S 5 +/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch7. + * 0: Invalid. No effect + * 1: Resume + */ +#define LEDC_CH7_GAMMA_RESUME (BIT(6)) +#define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) +#define LEDC_CH7_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH7_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 +/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 +/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S 31 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 +/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) +#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 +/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) +#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) +#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 +/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) +#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 +/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 +/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) +#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 +/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) +#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S 23 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer0. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer1. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer2. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer3. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 captured count value register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 captured count value register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 captured count value register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 captured count value register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * LEDC global configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) +/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock + */ +#define LEDC_APB_CLK_SEL 0x00000003U +#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) +#define LEDC_APB_CLK_SEL_V 0x00000003U +#define LEDC_APB_CLK_SEL_S 0 +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) +#define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 +/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) +#define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 37765152; + * Configures the version. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ledc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ledc_eco5_struct.h new file mode 100644 index 0000000000..ef59597ded --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ledc_eco5_struct.h @@ -0,0 +1,1359 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel n selected. + * 0: Select timer0 + * 1: Select timer1 + * 2: Select timer2 + * 3: Select timer3 + */ + uint32_t timer_sel_chn:2; + /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel n. + * 0: Signal output disable + * 1: Signal output enable + */ + uint32_t sig_out_en_chn:1; + /** idle_lv_chn : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel n is inactive. Valid only when + * LEDC_SIG_OUT_EN_CHn is 0. + * 0: Output level is low + * 1: Output level is high + */ + uint32_t idle_lv_chn:1; + /** para_up_chn : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, + * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel + * n, and will be automatically cleared by hardware. + * 0: Invalid. No effect + * 1: Update + */ + uint32_t para_up_chn:1; + /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt + * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num_chn:10; + /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel n. + * 0: Disable + * 1: Enable + */ + uint32_t ovf_cnt_en_chn:1; + /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel n. + * 0: Invalid. No effect + * 1: Reset the ovf_cnt + */ + uint32_t ovf_cnt_reset_chn:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel n. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ + uint32_t hpoint_chn:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + +/** Type of chn_duty register + * Initial duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel n. + */ + uint32_t duty_chn:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect. + * 0: Not take effect + * 1: Take effect + */ + uint32_t duty_start_chn:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of timern_conf register + * Timer n configuration register + */ +typedef union { + struct { + /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer n. + */ + uint32_t timern_duty_res:5; + /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer n.The least significant eight bits + * represent the fractional part. + */ + uint32_t clk_div_timern:18; + /** timern_pause : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer n. + * 0: Normal + * 1: Pause + */ + uint32_t timern_pause:1; + /** timern_rst : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer n. The counter will show 0 after reset. + * 0: Not reset + * 1: Reset + */ + uint32_t timern_rst:1; + uint32_t reserved_25:1; + /** timern_para_up : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES. + * 0: Invalid. No effect + * 1: Update + */ + uint32_t timern_para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timern_conf_reg_t; + +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t chn_gamma_entry_num:5; + /** chn_gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Pause + */ + uint32_t chn_gamma_pause:1; + /** chn_gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn. + * 0: Invalid. No effect + * 1: Resume + */ + uint32_t chn_gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch6_en:1; + /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_duty_chng_end_ch7_en:1; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch6_en:1; + /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_ovf_cnt_pls_ch7_en:1; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event. + * 0: Disable + * 1: Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch6_en:1; + /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_duty_scale_update_ch7_en:1; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch6_en:1; + /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task. + * 0: Disable + * 1: Enable + */ + uint32_t task_sig_out_dis_ch7_en:1; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch6_en:1; + /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_ovf_cnt_rst_ch7_en:1; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch6_en:1; + /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_restart_ch7_en:1; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch6_en:1; + /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_pause_ch7_en:1; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch6_en:1; + /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task. + * 0: Disable + * 1: Enable + */ + uint32_t task_gamma_resume_ch7_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timern_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timern_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers. + * 0: APB_CLK + * 1: RC_FAST_CLK + * 2: XTAL_CLK + * 3: Invalid. No clock + */ + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram + * 1: Force open the clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram + * 1: Force open the clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram + * 1: Force open the clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram + * 1: Force open the clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram + * 1: Force open the clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram + * 1: Force open the clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram + * 1: Force open the clock gate for LEDC ch6 gamma ram + */ + uint32_t gamma_ram_clk_en_ch6:1; + /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate. + * 0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram + * 1: Force open the clock gate for LEDC ch7 gamma ram + */ + uint32_t gamma_ram_clk_en_ch7:1; + uint32_t reserved_10:21; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Status Register */ +/** Type of chn_duty_r register + * Current duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn_r : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel n. + */ + uint32_t duty_chn_r:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + +/** Type of timern_value register + * Timer n current counter value register + */ +typedef union { + struct { + /** timern_cnt : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer n. + */ + uint32_t timern_cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_value_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timern_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch6_int_raw:1; + /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch7_int_raw:1; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + */ + uint32_t ovf_cnt_ch6_int_raw:1; + /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + */ + uint32_t ovf_cnt_ch7_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch6_int_st:1; + /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch7_int_st:1; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only + * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch6_int_st:1; + /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only + * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch7_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + */ + uint32_t duty_chng_end_ch6_int_ena:1; + /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + */ + uint32_t duty_chng_end_ch7_int_ena:1; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + */ + uint32_t ovf_cnt_ch6_int_ena:1; + /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + */ + uint32_t ovf_cnt_ch7_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + */ + uint32_t duty_chng_end_ch6_int_clr:1; + /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + */ + uint32_t duty_chng_end_ch7_int_clr:1; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + */ + uint32_t ovf_cnt_ch6_int_clr:1; + /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + */ + uint32_t ovf_cnt_ch7_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 37765152; + * Configures the version. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + + +typedef struct { + volatile ledc_chn_conf0_reg_t ch0_conf0; + volatile ledc_chn_hpoint_reg_t ch0_hpoint; + volatile ledc_chn_duty_reg_t ch0_duty; + volatile ledc_chn_conf1_reg_t ch0_conf1; + volatile ledc_chn_duty_r_reg_t ch0_duty_r; + volatile ledc_chn_conf0_reg_t ch1_conf0; + volatile ledc_chn_hpoint_reg_t ch1_hpoint; + volatile ledc_chn_duty_reg_t ch1_duty; + volatile ledc_chn_conf1_reg_t ch1_conf1; + volatile ledc_chn_duty_r_reg_t ch1_duty_r; + volatile ledc_chn_conf0_reg_t ch2_conf0; + volatile ledc_chn_hpoint_reg_t ch2_hpoint; + volatile ledc_chn_duty_reg_t ch2_duty; + volatile ledc_chn_conf1_reg_t ch2_conf1; + volatile ledc_chn_duty_r_reg_t ch2_duty_r; + volatile ledc_chn_conf0_reg_t ch3_conf0; + volatile ledc_chn_hpoint_reg_t ch3_hpoint; + volatile ledc_chn_duty_reg_t ch3_duty; + volatile ledc_chn_conf1_reg_t ch3_conf1; + volatile ledc_chn_duty_r_reg_t ch3_duty_r; + volatile ledc_chn_conf0_reg_t ch4_conf0; + volatile ledc_chn_hpoint_reg_t ch4_hpoint; + volatile ledc_chn_duty_reg_t ch4_duty; + volatile ledc_chn_conf1_reg_t ch4_conf1; + volatile ledc_chn_duty_r_reg_t ch4_duty_r; + volatile ledc_chn_conf0_reg_t ch5_conf0; + volatile ledc_chn_hpoint_reg_t ch5_hpoint; + volatile ledc_chn_duty_reg_t ch5_duty; + volatile ledc_chn_conf1_reg_t ch5_conf1; + volatile ledc_chn_duty_r_reg_t ch5_duty_r; + volatile ledc_chn_conf0_reg_t ch6_conf0; + volatile ledc_chn_hpoint_reg_t ch6_hpoint; + volatile ledc_chn_duty_reg_t ch6_duty; + volatile ledc_chn_conf1_reg_t ch6_conf1; + volatile ledc_chn_duty_r_reg_t ch6_duty_r; + volatile ledc_chn_conf0_reg_t ch7_conf0; + volatile ledc_chn_hpoint_reg_t ch7_hpoint; + volatile ledc_chn_duty_reg_t ch7_duty; + volatile ledc_chn_conf1_reg_t ch7_conf1; + volatile ledc_chn_duty_r_reg_t ch7_duty_r; + volatile ledc_timern_conf_reg_t timer0_conf; + volatile ledc_timern_value_reg_t timer0_value; + volatile ledc_timern_conf_reg_t timer1_conf; + volatile ledc_timern_value_reg_t timer1_value; + volatile ledc_timern_conf_reg_t timer2_conf; + volatile ledc_timern_value_reg_t timer2_value; + volatile ledc_timern_conf_reg_t timer3_conf; + volatile ledc_timern_value_reg_t timer3_value; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_12c[5]; + volatile ledc_timern_cmp_reg_t timern_cmp[4]; + volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; + uint32_t reserved_160[4]; + volatile ledc_conf_reg_t conf; + volatile ledc_date_reg_t date; +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ledc_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ledc_reg.h new file mode 100644 index 0000000000..05d7e02bbc --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ledc_reg.h @@ -0,0 +1,5742 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 0.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 0 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, + * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel + * 0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt + * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 0. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 0. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 1.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 1 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, + * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel + * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt + * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 1. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 1. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 2.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 2 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, + * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel + * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt + * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 2. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 2. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 3.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 3 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, + * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel + * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt + * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 3. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 3. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 4.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 4 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, + * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel + * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt + * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 4. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 4. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 5.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 5 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, + * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel + * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt + * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 5. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 5. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_CH6_CONF0_REG register + * Configuration register 0 for channel 6 + */ +#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) +/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 6 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH6 0x00000003U +#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) +#define LEDC_TIMER_SEL_CH6_V 0x00000003U +#define LEDC_TIMER_SEL_CH6_S 0 +/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 6.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) +#define LEDC_SIG_OUT_EN_CH6_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH6_S 2 +/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 6 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH6 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH6 (BIT(3)) +#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) +#define LEDC_IDLE_LV_CH6_V 0x00000001U +#define LEDC_IDLE_LV_CH6_S 3 +/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, + * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, + * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel + * 6, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH6 (BIT(4)) +#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) +#define LEDC_PARA_UP_CH6_V 0x00000001U +#define LEDC_PARA_UP_CH6_S 4 +/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt + * will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times. + */ +#define LEDC_OVF_NUM_CH6 0x000003FFU +#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) +#define LEDC_OVF_NUM_CH6_V 0x000003FFU +#define LEDC_OVF_NUM_CH6_S 5 +/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 6.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) +#define LEDC_OVF_CNT_EN_CH6_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH6_S 15 +/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 6.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) +#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH6_S 16 + +/** LEDC_CH6_HPOINT_REG register + * High point register for channel 6 + */ +#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) +/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 6. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH6 0x000FFFFFU +#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) +#define LEDC_HPOINT_CH6_V 0x000FFFFFU +#define LEDC_HPOINT_CH6_S 0 + +/** LEDC_CH6_DUTY_REG register + * Initial duty cycle register for channel 6 + */ +#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) +/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 6. + */ +#define LEDC_DUTY_CH6 0x01FFFFFFU +#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) +#define LEDC_DUTY_CH6_V 0x01FFFFFFU +#define LEDC_DUTY_CH6_S 0 + +/** LEDC_CH6_CONF1_REG register + * Configuration register 1 for channel 6 + */ +#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) +/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH6 (BIT(31)) +#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) +#define LEDC_DUTY_START_CH6_V 0x00000001U +#define LEDC_DUTY_START_CH6_S 31 + +/** LEDC_CH6_DUTY_R_REG register + * Current duty cycle register for channel 6 + */ +#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) +/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 6. + */ +#define LEDC_DUTY_CH6_R 0x01FFFFFFU +#define LEDC_DUTY_CH6_R_M (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S) +#define LEDC_DUTY_CH6_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH6_R_S 0 + +/** LEDC_CH7_CONF0_REG register + * Configuration register 0 for channel 7 + */ +#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) +/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 7 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH7 0x00000003U +#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) +#define LEDC_TIMER_SEL_CH7_V 0x00000003U +#define LEDC_TIMER_SEL_CH7_S 0 +/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 7.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) +#define LEDC_SIG_OUT_EN_CH7_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH7_S 2 +/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 7 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH7 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH7 (BIT(3)) +#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) +#define LEDC_IDLE_LV_CH7_V 0x00000001U +#define LEDC_IDLE_LV_CH7_S 3 +/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, + * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, + * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel + * 7, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH7 (BIT(4)) +#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) +#define LEDC_PARA_UP_CH7_V 0x00000001U +#define LEDC_PARA_UP_CH7_S 4 +/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt + * will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times. + */ +#define LEDC_OVF_NUM_CH7 0x000003FFU +#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) +#define LEDC_OVF_NUM_CH7_V 0x000003FFU +#define LEDC_OVF_NUM_CH7_S 5 +/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 7.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) +#define LEDC_OVF_CNT_EN_CH7_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH7_S 15 +/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 7.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) +#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH7_S 16 + +/** LEDC_CH7_HPOINT_REG register + * High point register for channel 7 + */ +#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) +/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 7. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH7 0x000FFFFFU +#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) +#define LEDC_HPOINT_CH7_V 0x000FFFFFU +#define LEDC_HPOINT_CH7_S 0 + +/** LEDC_CH7_DUTY_REG register + * Initial duty cycle register for channel 7 + */ +#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) +/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 7. + */ +#define LEDC_DUTY_CH7 0x01FFFFFFU +#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) +#define LEDC_DUTY_CH7_V 0x01FFFFFFU +#define LEDC_DUTY_CH7_S 0 + +/** LEDC_CH7_CONF1_REG register + * Configuration register 1 for channel 7 + */ +#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) +/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH7 (BIT(31)) +#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) +#define LEDC_DUTY_START_CH7_V 0x00000001U +#define LEDC_DUTY_START_CH7_S 31 + +/** LEDC_CH7_DUTY_R_REG register + * Current duty cycle register for channel 7 + */ +#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) +/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 7. + */ +#define LEDC_DUTY_CH7_R 0x01FFFFFFU +#define LEDC_DUTY_CH7_R_M (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S) +#define LEDC_DUTY_CH7_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH7_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration register + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 0. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 0.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 0. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 0 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER0 (BIT(25)) +#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) +#define LEDC_TICK_SEL_TIMER0_V 0x00000001U +#define LEDC_TICK_SEL_TIMER0_S 25 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and + * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value register + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration register + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 1. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 1.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 1. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 1 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER1 (BIT(25)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001U +#define LEDC_TICK_SEL_TIMER1_S 25 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and + * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value register + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration register + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 2. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 2.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 2. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 2 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER2 (BIT(25)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001U +#define LEDC_TICK_SEL_TIMER2_S 25 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and + * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value register + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration register + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 3. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 3.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 3. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer 3 selected. Unused. + */ +#define LEDC_TICK_SEL_TIMER3 (BIT(25)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001U +#define LEDC_TICK_SEL_TIMER3_S 25 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and + * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value register + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Interrupt raw status register + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 +/** LEDC_OVF_CNT_CH6_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + */ +#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) +#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 +/** LEDC_OVF_CNT_CH7_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + */ +#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) +#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 + +/** LEDC_INT_ST_REG register + * Interrupt masked status register + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 +/** LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only + * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) +#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_ST_S 18 +/** LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only + * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) +#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_ST_S 19 + +/** LEDC_INT_ENA_REG register + * Interrupt enable register + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 +/** LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + */ +#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) +#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 +/** LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + */ +#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) +#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 + +/** LEDC_INT_CLR_REG register + * Interrupt clear register + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_DUTY_CHNG_END_CH6_INT_CLR : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + */ +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 +/** LEDC_DUTY_CHNG_END_CH7_INT_CLR : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + */ +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 +/** LEDC_OVF_CNT_CH6_INT_CLR : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + */ +#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) +#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 +/** LEDC_OVF_CNT_CH7_INT_CLR : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + */ +#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) +#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch0. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch1. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch2. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch3. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch4. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch5. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_CH6_GAMMA_CONF_REG register + * Ledc ch6 gamma config register. + */ +#define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118) +/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch6. + */ +#define LEDC_CH6_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH6_GAMMA_ENTRY_NUM_M (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S) +#define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch6.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH6_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) +#define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH6_GAMMA_PAUSE_S 5 +/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch6.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH6_GAMMA_RESUME (BIT(6)) +#define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) +#define LEDC_CH6_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH6_GAMMA_RESUME_S 6 + +/** LEDC_CH7_GAMMA_CONF_REG register + * Ledc ch7 gamma config register. + */ +#define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c) +/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch7. + */ +#define LEDC_CH7_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH7_GAMMA_ENTRY_NUM_M (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S) +#define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch7.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH7_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) +#define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH7_GAMMA_PAUSE_S 5 +/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch7.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH7_GAMMA_RESUME (BIT(6)) +#define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) +#define LEDC_CH7_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH7_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_DUTY_CHNG_END_CH6_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN (BIT(6)) +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_M (LEDC_EVT_DUTY_CHNG_END_CH6_EN_V << LEDC_EVT_DUTY_CHNG_END_CH6_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH6_EN_S 6 +/** LEDC_EVT_DUTY_CHNG_END_CH7_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN (BIT(7)) +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_M (LEDC_EVT_DUTY_CHNG_END_CH7_EN_V << LEDC_EVT_DUTY_CHNG_END_CH7_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH7_EN_S 7 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_OVF_CNT_PLS_CH6_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN (BIT(14)) +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_M (LEDC_EVT_OVF_CNT_PLS_CH6_EN_V << LEDC_EVT_OVF_CNT_PLS_CH6_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH6_EN_S 14 +/** LEDC_EVT_OVF_CNT_PLS_CH7_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN (BIT(15)) +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_M (LEDC_EVT_OVF_CNT_PLS_CH7_EN_V << LEDC_EVT_OVF_CNT_PLS_CH7_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH7_EN_S 15 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIMER0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIMER0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIMER0_CMP_EN_M (LEDC_EVT_TIMER0_CMP_EN_V << LEDC_EVT_TIMER0_CMP_EN_S) +#define LEDC_EVT_TIMER0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIMER0_CMP_EN_S 20 +/** LEDC_EVT_TIMER1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIMER1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIMER1_CMP_EN_M (LEDC_EVT_TIMER1_CMP_EN_V << LEDC_EVT_TIMER1_CMP_EN_S) +#define LEDC_EVT_TIMER1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIMER1_CMP_EN_S 21 +/** LEDC_EVT_TIMER2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIMER2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIMER2_CMP_EN_M (LEDC_EVT_TIMER2_CMP_EN_V << LEDC_EVT_TIMER2_CMP_EN_S) +#define LEDC_EVT_TIMER2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIMER2_CMP_EN_S 22 +/** LEDC_EVT_TIMER3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIMER3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIMER3_CMP_EN_M (LEDC_EVT_TIMER3_CMP_EN_V << LEDC_EVT_TIMER3_CMP_EN_S) +#define LEDC_EVT_TIMER3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIMER3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN (BIT(30)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6_EN_S 30 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN (BIT(31)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7_EN_S 31 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_SIG_OUT_DIS_CH6_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN (BIT(14)) +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_M (LEDC_TASK_SIG_OUT_DIS_CH6_EN_V << LEDC_TASK_SIG_OUT_DIS_CH6_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH6_EN_S 14 +/** LEDC_TASK_SIG_OUT_DIS_CH7_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN (BIT(15)) +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_M (LEDC_TASK_SIG_OUT_DIS_CH7_EN_V << LEDC_TASK_SIG_OUT_DIS_CH7_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH7_EN_S 15 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_OVF_CNT_RST_CH6_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH6_EN (BIT(22)) +#define LEDC_TASK_OVF_CNT_RST_CH6_EN_M (LEDC_TASK_OVF_CNT_RST_CH6_EN_V << LEDC_TASK_OVF_CNT_RST_CH6_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH6_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH6_EN_S 22 +/** LEDC_TASK_OVF_CNT_RST_CH7_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH7_EN (BIT(23)) +#define LEDC_TASK_OVF_CNT_RST_CH7_EN_M (LEDC_TASK_OVF_CNT_RST_CH7_EN_V << LEDC_TASK_OVF_CNT_RST_CH7_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH7_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH7_EN_S 23 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_RESTART_CH6_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH6_EN (BIT(6)) +#define LEDC_TASK_GAMMA_RESTART_CH6_EN_M (LEDC_TASK_GAMMA_RESTART_CH6_EN_V << LEDC_TASK_GAMMA_RESTART_CH6_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH6_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH6_EN_S 6 +/** LEDC_TASK_GAMMA_RESTART_CH7_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH7_EN (BIT(7)) +#define LEDC_TASK_GAMMA_RESTART_CH7_EN_M (LEDC_TASK_GAMMA_RESTART_CH7_EN_V << LEDC_TASK_GAMMA_RESTART_CH7_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH7_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH7_EN_S 7 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_PAUSE_CH6_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN (BIT(14)) +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_M (LEDC_TASK_GAMMA_PAUSE_CH6_EN_V << LEDC_TASK_GAMMA_PAUSE_CH6_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH6_EN_S 14 +/** LEDC_TASK_GAMMA_PAUSE_CH7_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN (BIT(15)) +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_M (LEDC_TASK_GAMMA_PAUSE_CH7_EN_V << LEDC_TASK_GAMMA_PAUSE_CH7_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH7_EN_S 15 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 +/** LEDC_TASK_GAMMA_RESUME_CH6_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH6_EN (BIT(22)) +#define LEDC_TASK_GAMMA_RESUME_CH6_EN_M (LEDC_TASK_GAMMA_RESUME_CH6_EN_V << LEDC_TASK_GAMMA_RESUME_CH6_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH6_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH6_EN_S 22 +/** LEDC_TASK_GAMMA_RESUME_CH7_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH7_EN (BIT(23)) +#define LEDC_TASK_GAMMA_RESUME_CH7_EN_M (LEDC_TASK_GAMMA_RESUME_CH7_EN_V << LEDC_TASK_GAMMA_RESUME_CH7_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH7_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH7_EN_S 23 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer0. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer1. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer2. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer3. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 captured count value register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 captured count value register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 captured count value register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 captured count value register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * LEDC global configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) +/** LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: + * XTAL_CLK\\3: Invalid. No clock + */ +#define LEDC_APB_CLK_SEL 0x00000003U +#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) +#define LEDC_APB_CLK_SEL_V 0x00000003U +#define LEDC_APB_CLK_SEL_S 0 +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_GAMMA_RAM_CLK_EN_CH6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the + * clock gate for LEDC ch6 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH6 (BIT(8)) +#define LEDC_GAMMA_RAM_CLK_EN_CH6_M (LEDC_GAMMA_RAM_CLK_EN_CH6_V << LEDC_GAMMA_RAM_CLK_EN_CH6_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH6_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH6_S 8 +/** LEDC_GAMMA_RAM_CLK_EN_CH7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the + * clock gate for LEDC ch7 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH7 (BIT(9)) +#define LEDC_GAMMA_RAM_CLK_EN_CH7_M (LEDC_GAMMA_RAM_CLK_EN_CH7_V << LEDC_GAMMA_RAM_CLK_EN_CH7_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH7_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH7_S 9 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 36712560; + * Configures the version. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +/** LEDC gamma fade config ram registers + * 16 words (32bit) per channel * 8 channels + */ +#define LEDC_CH0_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x400) +/* LEDC_CH0_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE0_SCALE_M ((LEDC_CH0_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x404) +/* LEDC_CH0_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE1_SCALE_M ((LEDC_CH0_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x408) +/* LEDC_CH0_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE2_SCALE_M ((LEDC_CH0_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x40c) +/* LEDC_CH0_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE3_SCALE_M ((LEDC_CH0_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x410) +/* LEDC_CH0_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE4_SCALE_M ((LEDC_CH0_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x414) +/* LEDC_CH0_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE5_SCALE_M ((LEDC_CH0_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x418) +/* LEDC_CH0_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE6_SCALE_M ((LEDC_CH0_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x41c) +/* LEDC_CH0_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE7_SCALE_M ((LEDC_CH0_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x420) +/* LEDC_CH0_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE8_SCALE_M ((LEDC_CH0_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x424) +/* LEDC_CH0_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE9_SCALE_M ((LEDC_CH0_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x428) +/* LEDC_CH0_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE10_SCALE_M ((LEDC_CH0_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x42c) +/* LEDC_CH0_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE11_SCALE_M ((LEDC_CH0_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x430) +/* LEDC_CH0_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE12_SCALE_M ((LEDC_CH0_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x434) +/* LEDC_CH0_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE13_SCALE_M ((LEDC_CH0_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x438) +/* LEDC_CH0_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE14_SCALE_M ((LEDC_CH0_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x43c) +/* LEDC_CH0_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE15_SCALE_M ((LEDC_CH0_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH1_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x440) +/* LEDC_CH1_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE0_SCALE_M ((LEDC_CH1_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x444) +/* LEDC_CH1_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE1_SCALE_M ((LEDC_CH1_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x448) +/* LEDC_CH1_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE2_SCALE_M ((LEDC_CH1_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x44c) +/* LEDC_CH1_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE3_SCALE_M ((LEDC_CH1_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x450) +/* LEDC_CH1_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE4_SCALE_M ((LEDC_CH1_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x454) +/* LEDC_CH1_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE5_SCALE_M ((LEDC_CH1_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x458) +/* LEDC_CH1_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE6_SCALE_M ((LEDC_CH1_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x45c) +/* LEDC_CH1_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE7_SCALE_M ((LEDC_CH1_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x460) +/* LEDC_CH1_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE8_SCALE_M ((LEDC_CH1_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x464) +/* LEDC_CH1_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE9_SCALE_M ((LEDC_CH1_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x468) +/* LEDC_CH1_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE10_SCALE_M ((LEDC_CH1_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x46c) +/* LEDC_CH1_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE11_SCALE_M ((LEDC_CH1_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x470) +/* LEDC_CH1_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE12_SCALE_M ((LEDC_CH1_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x474) +/* LEDC_CH1_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE13_SCALE_M ((LEDC_CH1_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x478) +/* LEDC_CH1_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE14_SCALE_M ((LEDC_CH1_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x47c) +/* LEDC_CH1_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE15_SCALE_M ((LEDC_CH1_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH2_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x480) +/* LEDC_CH2_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE0_SCALE_M ((LEDC_CH2_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x484) +/* LEDC_CH2_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE1_SCALE_M ((LEDC_CH2_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x488) +/* LEDC_CH2_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE2_SCALE_M ((LEDC_CH2_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x48c) +/* LEDC_CH2_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE3_SCALE_M ((LEDC_CH2_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x490) +/* LEDC_CH2_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE4_SCALE_M ((LEDC_CH2_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x494) +/* LEDC_CH2_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE5_SCALE_M ((LEDC_CH2_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x498) +/* LEDC_CH2_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE6_SCALE_M ((LEDC_CH2_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x49c) +/* LEDC_CH2_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE7_SCALE_M ((LEDC_CH2_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x4a0) +/* LEDC_CH2_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE8_SCALE_M ((LEDC_CH2_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x4a4) +/* LEDC_CH2_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE9_SCALE_M ((LEDC_CH2_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x4a8) +/* LEDC_CH2_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE10_SCALE_M ((LEDC_CH2_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x4ac) +/* LEDC_CH2_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE11_SCALE_M ((LEDC_CH2_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x4b0) +/* LEDC_CH2_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE12_SCALE_M ((LEDC_CH2_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x4b4) +/* LEDC_CH2_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE13_SCALE_M ((LEDC_CH2_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x4b8) +/* LEDC_CH2_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE14_SCALE_M ((LEDC_CH2_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x4bc) +/* LEDC_CH2_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE15_SCALE_M ((LEDC_CH2_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH3_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x4c0) +/* LEDC_CH3_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE0_SCALE_M ((LEDC_CH3_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x4c4) +/* LEDC_CH3_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE1_SCALE_M ((LEDC_CH3_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x4c8) +/* LEDC_CH3_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE2_SCALE_M ((LEDC_CH3_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x4cc) +/* LEDC_CH3_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE3_SCALE_M ((LEDC_CH3_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x4d0) +/* LEDC_CH3_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE4_SCALE_M ((LEDC_CH3_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x4d4) +/* LEDC_CH3_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE5_SCALE_M ((LEDC_CH3_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x4d8) +/* LEDC_CH3_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE6_SCALE_M ((LEDC_CH3_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x4dc) +/* LEDC_CH3_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE7_SCALE_M ((LEDC_CH3_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x4e0) +/* LEDC_CH3_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE8_SCALE_M ((LEDC_CH3_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x4e4) +/* LEDC_CH3_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE9_SCALE_M ((LEDC_CH3_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x4e8) +/* LEDC_CH3_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE10_SCALE_M ((LEDC_CH3_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x4ec) +/* LEDC_CH3_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE11_SCALE_M ((LEDC_CH3_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x4f0) +/* LEDC_CH3_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE12_SCALE_M ((LEDC_CH3_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x4f4) +/* LEDC_CH3_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE13_SCALE_M ((LEDC_CH3_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x4f8) +/* LEDC_CH3_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE14_SCALE_M ((LEDC_CH3_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x4fc) +/* LEDC_CH3_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE15_SCALE_M ((LEDC_CH3_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH4_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x500) +/* LEDC_CH4_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE0_SCALE_M ((LEDC_CH4_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x504) +/* LEDC_CH4_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE1_SCALE_M ((LEDC_CH4_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x508) +/* LEDC_CH4_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE2_SCALE_M ((LEDC_CH4_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x50c) +/* LEDC_CH4_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE3_SCALE_M ((LEDC_CH4_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x510) +/* LEDC_CH4_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE4_SCALE_M ((LEDC_CH4_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x514) +/* LEDC_CH4_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE5_SCALE_M ((LEDC_CH4_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x518) +/* LEDC_CH4_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE6_SCALE_M ((LEDC_CH4_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x51c) +/* LEDC_CH4_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE7_SCALE_M ((LEDC_CH4_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x520) +/* LEDC_CH4_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE8_SCALE_M ((LEDC_CH4_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x524) +/* LEDC_CH4_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE9_SCALE_M ((LEDC_CH4_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x528) +/* LEDC_CH4_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE10_SCALE_M ((LEDC_CH4_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x52c) +/* LEDC_CH4_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE11_SCALE_M ((LEDC_CH4_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x530) +/* LEDC_CH4_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE12_SCALE_M ((LEDC_CH4_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x534) +/* LEDC_CH4_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE13_SCALE_M ((LEDC_CH4_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x538) +/* LEDC_CH4_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE14_SCALE_M ((LEDC_CH4_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x53c) +/* LEDC_CH4_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE15_SCALE_M ((LEDC_CH4_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH5_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x540) +/* LEDC_CH5_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE0_SCALE_M ((LEDC_CH5_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x544) +/* LEDC_CH5_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE1_SCALE_M ((LEDC_CH5_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x548) +/* LEDC_CH5_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE2_SCALE_M ((LEDC_CH5_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x54c) +/* LEDC_CH5_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE3_SCALE_M ((LEDC_CH5_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x550) +/* LEDC_CH5_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE4_SCALE_M ((LEDC_CH5_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x554) +/* LEDC_CH5_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE5_SCALE_M ((LEDC_CH5_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x558) +/* LEDC_CH5_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE6_SCALE_M ((LEDC_CH5_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x55c) +/* LEDC_CH5_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE7_SCALE_M ((LEDC_CH5_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x560) +/* LEDC_CH5_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE8_SCALE_M ((LEDC_CH5_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x564) +/* LEDC_CH5_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE9_SCALE_M ((LEDC_CH5_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x568) +/* LEDC_CH5_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE10_SCALE_M ((LEDC_CH5_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x56c) +/* LEDC_CH5_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE11_SCALE_M ((LEDC_CH5_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x570) +/* LEDC_CH5_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE12_SCALE_M ((LEDC_CH5_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x574) +/* LEDC_CH5_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE13_SCALE_M ((LEDC_CH5_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x578) +/* LEDC_CH5_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE14_SCALE_M ((LEDC_CH5_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x57c) +/* LEDC_CH5_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE15_SCALE_M ((LEDC_CH5_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH6_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x580) +/* LEDC_CH6_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE0_SCALE_M ((LEDC_CH6_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x584) +/* LEDC_CH6_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE1_SCALE_M ((LEDC_CH6_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x588) +/* LEDC_CH6_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE2_SCALE_M ((LEDC_CH6_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x58c) +/* LEDC_CH6_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE3_SCALE_M ((LEDC_CH6_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x590) +/* LEDC_CH6_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE4_SCALE_M ((LEDC_CH6_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x594) +/* LEDC_CH6_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE5_SCALE_M ((LEDC_CH6_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x598) +/* LEDC_CH6_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE6_SCALE_M ((LEDC_CH6_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x59c) +/* LEDC_CH6_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE7_SCALE_M ((LEDC_CH6_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x5a0) +/* LEDC_CH6_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE8_SCALE_M ((LEDC_CH6_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x5a4) +/* LEDC_CH6_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE9_SCALE_M ((LEDC_CH6_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x5a8) +/* LEDC_CH6_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE10_SCALE_M ((LEDC_CH6_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x5ac) +/* LEDC_CH6_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE11_SCALE_M ((LEDC_CH6_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x5b0) +/* LEDC_CH6_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE12_SCALE_M ((LEDC_CH6_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x5b4) +/* LEDC_CH6_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE13_SCALE_M ((LEDC_CH6_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x5b8) +/* LEDC_CH6_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE14_SCALE_M ((LEDC_CH6_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x5bc) +/* LEDC_CH6_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE15_SCALE_M ((LEDC_CH6_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH7_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x5c0) +/* LEDC_CH7_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE0_SCALE_M ((LEDC_CH7_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x5c4) +/* LEDC_CH7_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE1_SCALE_M ((LEDC_CH7_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x5c8) +/* LEDC_CH7_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE2_SCALE_M ((LEDC_CH7_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x5cc) +/* LEDC_CH7_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE3_SCALE_M ((LEDC_CH7_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x5d0) +/* LEDC_CH7_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE4_SCALE_M ((LEDC_CH7_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x5d4) +/* LEDC_CH7_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE5_SCALE_M ((LEDC_CH7_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x5d8) +/* LEDC_CH7_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE6_SCALE_M ((LEDC_CH7_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x5dc) +/* LEDC_CH7_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE7_SCALE_M ((LEDC_CH7_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x5e0) +/* LEDC_CH7_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE8_SCALE_M ((LEDC_CH7_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x5e4) +/* LEDC_CH7_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE9_SCALE_M ((LEDC_CH7_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x5e8) +/* LEDC_CH7_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE10_SCALE_M ((LEDC_CH7_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x5ec) +/* LEDC_CH7_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE11_SCALE_M ((LEDC_CH7_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x5f0) +/* LEDC_CH7_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE12_SCALE_M ((LEDC_CH7_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x5f4) +/* LEDC_CH7_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE13_SCALE_M ((LEDC_CH7_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x5f8) +/* LEDC_CH7_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE14_SCALE_M ((LEDC_CH7_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x5fc) +/* LEDC_CH7_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE15_SCALE_M ((LEDC_CH7_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ledc_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ledc_struct.h new file mode 100644 index 0000000000..23029726e8 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/ledc_struct.h @@ -0,0 +1,1258 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: conf0 */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel n selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ + uint32_t timer_sel:2; + /** sig_out_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel n.\\0: Signal output + * disable\\1: Signal output enable + */ + uint32_t sig_out_en:1; + /** idle_lv : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel n is inactive. Valid only when + * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + */ + uint32_t idle_lv:1; + /** para_up : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, + * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel + * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ + uint32_t para_up:1; + /** ovf_num : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt + * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num:10; + /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + */ + uint32_t ovf_cnt_en:1; + /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ + uint32_t ovf_cnt_reset:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel n. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ + uint32_t hpoint:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + +/** Type of chn_duty register + * Initial duty cycle register for channel n + */ +typedef union { + struct { + /** duty : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel n. + */ + uint32_t duty:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ + uint32_t duty_start:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of chn_duty_r register + * Current duty cycle register for channel n + */ +typedef union { + struct { + /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel n. + */ + uint32_t duty:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + + +/** Group: conf1 */ +/** Type of timern_conf register + * Timer n configuration register + */ +typedef union { + struct { + /** duty_res : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer n. + */ + uint32_t duty_res:5; + /** clk_div : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer n.The least significant eight bits + * represent the fractional part. + */ + uint32_t clk_div:18; + /** pause : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + */ + uint32_t pause:1; + /** rst : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer n. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ + uint32_t rst:1; + /** tick_sel : R/W; bitpos: [25]; default: 0; + * Configures which clock is timer n selected. Unused. + */ + uint32_t tick_sel:1; + /** para_up : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and + * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ + uint32_t para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timern_conf_reg_t; + +/** Type of timern_value register + * Timer n current counter value register + */ +typedef union { + struct { + /** cnt : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer n. + */ + uint32_t cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_value_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + /** duty_chng_end_ch6_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch6_int_raw:1; + /** duty_chng_end_ch7_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch7_int_raw:1; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + /** ovf_cnt_ch6_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + */ + uint32_t ovf_cnt_ch6_int_raw:1; + /** ovf_cnt_ch7_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + */ + uint32_t ovf_cnt_ch7_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + /** duty_chng_end_ch6_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch6_int_st:1; + /** duty_chng_end_ch7_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch7_int_st:1; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + /** ovf_cnt_ch6_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only + * when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch6_int_st:1; + /** ovf_cnt_ch7_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only + * when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch7_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + /** duty_chng_end_ch6_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + */ + uint32_t duty_chng_end_ch6_int_ena:1; + /** duty_chng_end_ch7_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + */ + uint32_t duty_chng_end_ch7_int_ena:1; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + /** ovf_cnt_ch6_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + */ + uint32_t ovf_cnt_ch6_int_ena:1; + /** ovf_cnt_ch7_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + */ + uint32_t ovf_cnt_ch7_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + /** duty_chng_end_ch6_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + */ + uint32_t duty_chng_end_ch6_int_clr:1; + /** duty_chng_end_ch7_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + */ + uint32_t duty_chng_end_ch7_int_clr:1; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + /** ovf_cnt_ch6_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + */ + uint32_t ovf_cnt_ch6_int_clr:1; + /** ovf_cnt_ch7_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + */ + uint32_t ovf_cnt_ch7_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: gamma */ +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t ch0_gamma_entry_num:5; + /** ch0_gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Pause + */ + uint32_t ch0_gamma_pause:1; + /** ch0_gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Resume + */ + uint32_t ch0_gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + + +/** Group: en0 */ +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + /** evt_duty_chng_end_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch6_en:1; + /** evt_duty_chng_end_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch7_en:1; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + /** evt_ovf_cnt_pls_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch6_en:1; + /** evt_ovf_cnt_pls_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch7_en:1; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_timer0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer0_cmp_en:1; + /** evt_timer1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer1_cmp_en:1; + /** evt_timer2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer2_cmp_en:1; + /** evt_timer3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + /** task_duty_scale_update_ch6_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch6_en:1; + /** task_duty_scale_update_ch7_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch7_en:1; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + + +/** Group: en1 */ +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + /** task_sig_out_dis_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch6_en:1; + /** task_sig_out_dis_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch7_en:1; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + /** task_ovf_cnt_rst_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch6_en:1; + /** task_ovf_cnt_rst_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch7_en:1; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + + +/** Group: en2 */ +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + /** task_gamma_restart_ch6_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch6_en:1; + /** task_gamma_restart_ch7_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch7_en:1; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + /** task_gamma_pause_ch6_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch6_en:1; + /** task_gamma_pause_ch7_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch7_en:1; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + /** task_gamma_resume_ch6_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch6_en:1; + /** task_gamma_resume_ch7_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch7_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + + +/** Group: cmp */ +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timer0_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timer0_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + + +/** Group: cap */ +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timer0_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timer_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + + +/** Group: Configuration Register */ +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: + * XTAL_CLK\\3: Invalid. No clock + */ + uint32_t apb_clk_sel:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + /** gamma_ram_clk_en_ch6 : R/W; bitpos: [8]; default: 0; + * Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the + * clock gate for LEDC ch6 gamma ram + */ + uint32_t gamma_ram_clk_en_ch6:1; + /** gamma_ram_clk_en_ch7 : R/W; bitpos: [9]; default: 0; + * Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the + * clock gate for LEDC ch7 gamma ram + */ + uint32_t gamma_ram_clk_en_ch7:1; + uint32_t reserved_10:21; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 36712560; + * Configures the version. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + +typedef struct { + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty_init; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_r; +} ledc_chn_reg_t; + +typedef struct { + volatile ledc_chn_reg_t channel[8]; +} ledc_ch_group_reg_t; + +typedef struct { + volatile ledc_timern_conf_reg_t conf; + volatile ledc_timern_value_reg_t value; +} ledc_timerx_reg_t; + +typedef struct { + volatile ledc_timerx_reg_t timer[4]; +} ledc_timer_group_reg_t; + +typedef struct { + volatile ledc_ch_group_reg_t channel_group[1]; + volatile ledc_timer_group_reg_t timer_group[1]; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[8]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_12c[5]; + volatile ledc_timern_cmp_reg_t timern_cmp[4]; + volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; + uint32_t reserved_160[4]; + volatile ledc_conf_reg_t conf; + volatile ledc_date_reg_t date; +} ledc_dev_t; + + +/** + * Gamma fade param group ram type + */ +typedef union { + struct { + uint32_t duty_inc :1; + uint32_t duty_cycle :10; + uint32_t scale :10; + uint32_t duty_num :10; + uint32_t reserved :1; + }; + uint32_t val; +} ledc_channel_gamma_fade_param_t; + +typedef struct { + volatile ledc_channel_gamma_fade_param_t entry[16]; +} ledc_gamma_channel_t; + +typedef struct { + volatile ledc_gamma_channel_t channel[8]; +} ledc_gamma_ram_t; + + +extern ledc_dev_t LEDC; +extern ledc_gamma_ram_t LEDC_GAMMA_RAM; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); +_Static_assert(sizeof(ledc_gamma_ram_t) == 0x200, "Invalid size of ledc_gamma_ram_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_eco5_reg.h new file mode 100644 index 0000000000..0d7ce67bd9 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_eco5_reg.h @@ -0,0 +1,585 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_LP2HP_PMS_DATE_REG register + * NA + */ +#define TEE_LP2HP_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943; + * NA + */ +#define TEE_TEE_DATE 0xFFFFFFFFU +#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S) +#define TEE_TEE_DATE_V 0xFFFFFFFFU +#define TEE_TEE_DATE_S 0 + +/** TEE_PMS_CLK_EN_REG register + * NA + */ +#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_CLK_EN (BIT(0)) +#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S) +#define TEE_REG_CLK_EN_V 0x00000001U +#define TEE_REG_CLK_EN_S 0 + +/** TEE_LP_MM_PMS_REG0_REG register + * NA + */ +#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_REG_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_PSRAM_ALLOW (BIT(0)) +#define TEE_REG_LP_MM_PSRAM_ALLOW_M (TEE_REG_LP_MM_PSRAM_ALLOW_V << TEE_REG_LP_MM_PSRAM_ALLOW_S) +#define TEE_REG_LP_MM_PSRAM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_PSRAM_ALLOW_S 0 +/** TEE_REG_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_FLASH_ALLOW (BIT(1)) +#define TEE_REG_LP_MM_FLASH_ALLOW_M (TEE_REG_LP_MM_FLASH_ALLOW_V << TEE_REG_LP_MM_FLASH_ALLOW_S) +#define TEE_REG_LP_MM_FLASH_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_FLASH_ALLOW_S 1 +/** TEE_REG_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_L2MEM_ALLOW (BIT(2)) +#define TEE_REG_LP_MM_L2MEM_ALLOW_M (TEE_REG_LP_MM_L2MEM_ALLOW_V << TEE_REG_LP_MM_L2MEM_ALLOW_S) +#define TEE_REG_LP_MM_L2MEM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_L2MEM_ALLOW_S 2 +/** TEE_REG_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_L2ROM_ALLOW (BIT(3)) +#define TEE_REG_LP_MM_L2ROM_ALLOW_M (TEE_REG_LP_MM_L2ROM_ALLOW_V << TEE_REG_LP_MM_L2ROM_ALLOW_S) +#define TEE_REG_LP_MM_L2ROM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_L2ROM_ALLOW_S 3 +/** TEE_REG_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_TRACE0_ALLOW (BIT(6)) +#define TEE_REG_LP_MM_TRACE0_ALLOW_M (TEE_REG_LP_MM_TRACE0_ALLOW_V << TEE_REG_LP_MM_TRACE0_ALLOW_S) +#define TEE_REG_LP_MM_TRACE0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_TRACE0_ALLOW_S 6 +/** TEE_REG_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_TRACE1_ALLOW (BIT(7)) +#define TEE_REG_LP_MM_TRACE1_ALLOW_M (TEE_REG_LP_MM_TRACE1_ALLOW_V << TEE_REG_LP_MM_TRACE1_ALLOW_S) +#define TEE_REG_LP_MM_TRACE1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_TRACE1_ALLOW_S 7 +/** TEE_REG_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW (BIT(8)) +#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_M (TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S) +#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S 8 +/** TEE_REG_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_L2MEM_MON_ALLOW (BIT(9)) +#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_M (TEE_REG_LP_MM_L2MEM_MON_ALLOW_V << TEE_REG_LP_MM_L2MEM_MON_ALLOW_S) +#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_S 9 +/** TEE_REG_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_TCM_MON_ALLOW (BIT(10)) +#define TEE_REG_LP_MM_TCM_MON_ALLOW_M (TEE_REG_LP_MM_TCM_MON_ALLOW_V << TEE_REG_LP_MM_TCM_MON_ALLOW_S) +#define TEE_REG_LP_MM_TCM_MON_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_TCM_MON_ALLOW_S 10 +/** TEE_REG_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_CACHE_ALLOW (BIT(11)) +#define TEE_REG_LP_MM_CACHE_ALLOW_M (TEE_REG_LP_MM_CACHE_ALLOW_V << TEE_REG_LP_MM_CACHE_ALLOW_S) +#define TEE_REG_LP_MM_CACHE_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_CACHE_ALLOW_S 11 + +/** TEE_LP_MM_PMS_REG1_REG register + * NA + */ +#define TEE_LP_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_REG_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_USBOTG_ALLOW (BIT(0)) +#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG_ALLOW_S) +#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_S 0 +/** TEE_REG_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW (BIT(1)) +#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S) +#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S 1 +/** TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) +#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S) +#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S 2 +/** TEE_REG_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_GDMA_ALLOW (BIT(3)) +#define TEE_REG_LP_MM_HP_GDMA_ALLOW_M (TEE_REG_LP_MM_HP_GDMA_ALLOW_V << TEE_REG_LP_MM_HP_GDMA_ALLOW_S) +#define TEE_REG_LP_MM_HP_GDMA_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_GDMA_ALLOW_S 3 +/** TEE_REG_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_REGDMA_ALLOW (BIT(4)) +#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_M (TEE_REG_LP_MM_HP_REGDMA_ALLOW_V << TEE_REG_LP_MM_HP_REGDMA_ALLOW_S) +#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_S 4 +/** TEE_REG_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_SDMMC_ALLOW (BIT(5)) +#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_M (TEE_REG_LP_MM_HP_SDMMC_ALLOW_V << TEE_REG_LP_MM_HP_SDMMC_ALLOW_S) +#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_S 5 +/** TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW (BIT(6)) +#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S) +#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S 6 +/** TEE_REG_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_JPEG_ALLOW (BIT(7)) +#define TEE_REG_LP_MM_HP_JPEG_ALLOW_M (TEE_REG_LP_MM_HP_JPEG_ALLOW_V << TEE_REG_LP_MM_HP_JPEG_ALLOW_S) +#define TEE_REG_LP_MM_HP_JPEG_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_JPEG_ALLOW_S 7 +/** TEE_REG_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_PPA_ALLOW (BIT(8)) +#define TEE_REG_LP_MM_HP_PPA_ALLOW_M (TEE_REG_LP_MM_HP_PPA_ALLOW_V << TEE_REG_LP_MM_HP_PPA_ALLOW_S) +#define TEE_REG_LP_MM_HP_PPA_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_PPA_ALLOW_S 8 +/** TEE_REG_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_DMA2D_ALLOW (BIT(9)) +#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_DMA2D_ALLOW_S) +#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_S 9 +/** TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW (BIT(10)) +#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S) +#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S 10 +/** TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW (BIT(11)) +#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S) +#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S 11 +/** TEE_REG_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_FLASH_ALLOW (BIT(12)) +#define TEE_REG_LP_MM_HP_FLASH_ALLOW_M (TEE_REG_LP_MM_HP_FLASH_ALLOW_V << TEE_REG_LP_MM_HP_FLASH_ALLOW_S) +#define TEE_REG_LP_MM_HP_FLASH_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_FLASH_ALLOW_S 12 +/** TEE_REG_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_PSRAM_ALLOW (BIT(13)) +#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_M (TEE_REG_LP_MM_HP_PSRAM_ALLOW_V << TEE_REG_LP_MM_HP_PSRAM_ALLOW_S) +#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_S 13 +/** TEE_REG_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW (BIT(14)) +#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_M (TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V << TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S) +#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S 14 +/** TEE_REG_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_GMAC_ALLOW (BIT(15)) +#define TEE_REG_LP_MM_HP_GMAC_ALLOW_M (TEE_REG_LP_MM_HP_GMAC_ALLOW_V << TEE_REG_LP_MM_HP_GMAC_ALLOW_S) +#define TEE_REG_LP_MM_HP_GMAC_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_GMAC_ALLOW_S 15 +/** TEE_REG_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW (BIT(16)) +#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_M (TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V << TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S) +#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S 16 +/** TEE_REG_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_PVT_ALLOW (BIT(17)) +#define TEE_REG_LP_MM_HP_PVT_ALLOW_M (TEE_REG_LP_MM_HP_PVT_ALLOW_V << TEE_REG_LP_MM_HP_PVT_ALLOW_S) +#define TEE_REG_LP_MM_HP_PVT_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_PVT_ALLOW_S 17 +/** TEE_REG_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW (BIT(18)) +#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S) +#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S 18 +/** TEE_REG_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW (BIT(19)) +#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S) +#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S 19 +/** TEE_REG_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_ISP_ALLOW (BIT(20)) +#define TEE_REG_LP_MM_HP_ISP_ALLOW_M (TEE_REG_LP_MM_HP_ISP_ALLOW_V << TEE_REG_LP_MM_HP_ISP_ALLOW_S) +#define TEE_REG_LP_MM_HP_ISP_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_ISP_ALLOW_S 20 +/** TEE_REG_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW (BIT(21)) +#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_M (TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V << TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S) +#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S 21 +/** TEE_REG_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_RMT_ALLOW (BIT(22)) +#define TEE_REG_LP_MM_HP_RMT_ALLOW_M (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S) +#define TEE_REG_LP_MM_HP_RMT_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_RMT_ALLOW_S 22 +/** TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) +#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_M (TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S) +#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_BITSRAMBLER_ALLOW_S 23 +/** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW (BIT(24)) +#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_M (TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S) +#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S 24 +/** TEE_REG_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW (BIT(25)) +#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S) +#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S 25 +/** TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW (BIT(26)) +#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S) +#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S 26 +/** TEE_REG_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_DMA_PMS_ALLOW (BIT(27)) +#define TEE_REG_LP_MM_DMA_PMS_ALLOW_M (TEE_REG_LP_MM_DMA_PMS_ALLOW_V << TEE_REG_LP_MM_DMA_PMS_ALLOW_S) +#define TEE_REG_LP_MM_DMA_PMS_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_DMA_PMS_ALLOW_S 27 +/** TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW (BIT(28)) +#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S) +#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S 28 +/** TEE_REG_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW (BIT(29)) +#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_M (TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S) +#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S 29 + +/** TEE_LP_MM_PMS_REG2_REG register + * NA + */ +#define TEE_LP_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0xa4) +/** TEE_REG_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW (BIT(0)) +#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S) +#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S 0 +/** TEE_REG_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW (BIT(1)) +#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S) +#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S 1 +/** TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW (BIT(2)) +#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S) +#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S 2 +/** TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW (BIT(3)) +#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S) +#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S 3 +/** TEE_REG_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I2C0_ALLOW (BIT(4)) +#define TEE_REG_LP_MM_HP_I2C0_ALLOW_M (TEE_REG_LP_MM_HP_I2C0_ALLOW_V << TEE_REG_LP_MM_HP_I2C0_ALLOW_S) +#define TEE_REG_LP_MM_HP_I2C0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I2C0_ALLOW_S 4 +/** TEE_REG_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I2C1_ALLOW (BIT(5)) +#define TEE_REG_LP_MM_HP_I2C1_ALLOW_M (TEE_REG_LP_MM_HP_I2C1_ALLOW_V << TEE_REG_LP_MM_HP_I2C1_ALLOW_S) +#define TEE_REG_LP_MM_HP_I2C1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I2C1_ALLOW_S 5 +/** TEE_REG_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I2S0_ALLOW (BIT(6)) +#define TEE_REG_LP_MM_HP_I2S0_ALLOW_M (TEE_REG_LP_MM_HP_I2S0_ALLOW_V << TEE_REG_LP_MM_HP_I2S0_ALLOW_S) +#define TEE_REG_LP_MM_HP_I2S0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I2S0_ALLOW_S 6 +/** TEE_REG_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I2S1_ALLOW (BIT(7)) +#define TEE_REG_LP_MM_HP_I2S1_ALLOW_M (TEE_REG_LP_MM_HP_I2S1_ALLOW_V << TEE_REG_LP_MM_HP_I2S1_ALLOW_S) +#define TEE_REG_LP_MM_HP_I2S1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I2S1_ALLOW_S 7 +/** TEE_REG_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I2S2_ALLOW (BIT(8)) +#define TEE_REG_LP_MM_HP_I2S2_ALLOW_M (TEE_REG_LP_MM_HP_I2S2_ALLOW_V << TEE_REG_LP_MM_HP_I2S2_ALLOW_S) +#define TEE_REG_LP_MM_HP_I2S2_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I2S2_ALLOW_S 8 +/** TEE_REG_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_PCNT_ALLOW (BIT(9)) +#define TEE_REG_LP_MM_HP_PCNT_ALLOW_M (TEE_REG_LP_MM_HP_PCNT_ALLOW_V << TEE_REG_LP_MM_HP_PCNT_ALLOW_S) +#define TEE_REG_LP_MM_HP_PCNT_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_PCNT_ALLOW_S 9 +/** TEE_REG_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_UART0_ALLOW (BIT(10)) +#define TEE_REG_LP_MM_HP_UART0_ALLOW_M (TEE_REG_LP_MM_HP_UART0_ALLOW_V << TEE_REG_LP_MM_HP_UART0_ALLOW_S) +#define TEE_REG_LP_MM_HP_UART0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_UART0_ALLOW_S 10 +/** TEE_REG_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_UART1_ALLOW (BIT(11)) +#define TEE_REG_LP_MM_HP_UART1_ALLOW_M (TEE_REG_LP_MM_HP_UART1_ALLOW_V << TEE_REG_LP_MM_HP_UART1_ALLOW_S) +#define TEE_REG_LP_MM_HP_UART1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_UART1_ALLOW_S 11 +/** TEE_REG_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_UART2_ALLOW (BIT(12)) +#define TEE_REG_LP_MM_HP_UART2_ALLOW_M (TEE_REG_LP_MM_HP_UART2_ALLOW_V << TEE_REG_LP_MM_HP_UART2_ALLOW_S) +#define TEE_REG_LP_MM_HP_UART2_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_UART2_ALLOW_S 12 +/** TEE_REG_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_UART3_ALLOW (BIT(13)) +#define TEE_REG_LP_MM_HP_UART3_ALLOW_M (TEE_REG_LP_MM_HP_UART3_ALLOW_V << TEE_REG_LP_MM_HP_UART3_ALLOW_S) +#define TEE_REG_LP_MM_HP_UART3_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_UART3_ALLOW_S 13 +/** TEE_REG_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_UART4_ALLOW (BIT(14)) +#define TEE_REG_LP_MM_HP_UART4_ALLOW_M (TEE_REG_LP_MM_HP_UART4_ALLOW_V << TEE_REG_LP_MM_HP_UART4_ALLOW_S) +#define TEE_REG_LP_MM_HP_UART4_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_UART4_ALLOW_S 14 +/** TEE_REG_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_PARLIO_ALLOW (BIT(15)) +#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_M (TEE_REG_LP_MM_HP_PARLIO_ALLOW_V << TEE_REG_LP_MM_HP_PARLIO_ALLOW_S) +#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_S 15 +/** TEE_REG_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW (BIT(16)) +#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S) +#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S 16 +/** TEE_REG_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW (BIT(17)) +#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S) +#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S 17 +/** TEE_REG_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW (BIT(18)) +#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_M (TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S) +#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S 18 +/** TEE_REG_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_LEDC_ALLOW (BIT(19)) +#define TEE_REG_LP_MM_HP_LEDC_ALLOW_M (TEE_REG_LP_MM_HP_LEDC_ALLOW_V << TEE_REG_LP_MM_HP_LEDC_ALLOW_S) +#define TEE_REG_LP_MM_HP_LEDC_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_LEDC_ALLOW_S 19 +/** TEE_REG_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_ETM_ALLOW (BIT(21)) +#define TEE_REG_LP_MM_HP_ETM_ALLOW_M (TEE_REG_LP_MM_HP_ETM_ALLOW_V << TEE_REG_LP_MM_HP_ETM_ALLOW_S) +#define TEE_REG_LP_MM_HP_ETM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_ETM_ALLOW_S 21 +/** TEE_REG_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW (BIT(22)) +#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_M (TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V << TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S) +#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S 22 +/** TEE_REG_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_TWAI0_ALLOW (BIT(23)) +#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_M (TEE_REG_LP_MM_HP_TWAI0_ALLOW_V << TEE_REG_LP_MM_HP_TWAI0_ALLOW_S) +#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_S 23 +/** TEE_REG_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_TWAI1_ALLOW (BIT(24)) +#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_M (TEE_REG_LP_MM_HP_TWAI1_ALLOW_V << TEE_REG_LP_MM_HP_TWAI1_ALLOW_S) +#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_S 24 +/** TEE_REG_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_TWAI2_ALLOW (BIT(25)) +#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_M (TEE_REG_LP_MM_HP_TWAI2_ALLOW_V << TEE_REG_LP_MM_HP_TWAI2_ALLOW_S) +#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_S 25 +/** TEE_REG_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW (BIT(26)) +#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_M (TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V << TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S) +#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S 26 +/** TEE_REG_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW (BIT(27)) +#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_M (TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S) +#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S 27 +/** TEE_REG_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW (BIT(28)) +#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_M (TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V << TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S) +#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S 28 +/** TEE_REG_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_ADC_ALLOW (BIT(30)) +#define TEE_REG_LP_MM_HP_ADC_ALLOW_M (TEE_REG_LP_MM_HP_ADC_ALLOW_V << TEE_REG_LP_MM_HP_ADC_ALLOW_S) +#define TEE_REG_LP_MM_HP_ADC_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_ADC_ALLOW_S 30 +/** TEE_REG_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_UHCI_ALLOW (BIT(31)) +#define TEE_REG_LP_MM_HP_UHCI_ALLOW_M (TEE_REG_LP_MM_HP_UHCI_ALLOW_V << TEE_REG_LP_MM_HP_UHCI_ALLOW_S) +#define TEE_REG_LP_MM_HP_UHCI_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_UHCI_ALLOW_S 31 + +/** TEE_LP_MM_PMS_REG3_REG register + * NA + */ +#define TEE_LP_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x11c) +/** TEE_REG_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_GPIO_ALLOW (BIT(0)) +#define TEE_REG_LP_MM_HP_GPIO_ALLOW_M (TEE_REG_LP_MM_HP_GPIO_ALLOW_V << TEE_REG_LP_MM_HP_GPIO_ALLOW_S) +#define TEE_REG_LP_MM_HP_GPIO_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_GPIO_ALLOW_S 0 +/** TEE_REG_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_IOMUX_ALLOW (BIT(1)) +#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_M (TEE_REG_LP_MM_HP_IOMUX_ALLOW_V << TEE_REG_LP_MM_HP_IOMUX_ALLOW_S) +#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_S 1 +/** TEE_REG_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW (BIT(2)) +#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_M (TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S) +#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S 2 +/** TEE_REG_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW (BIT(3)) +#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_M (TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V << TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S) +#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S 3 +/** TEE_REG_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP_CLKRST_ALLOW (BIT(4)) +#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_M (TEE_REG_LP_MM_HP_CLKRST_ALLOW_V << TEE_REG_LP_MM_HP_CLKRST_ALLOW_S) +#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_S 4 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_reg.h new file mode 100644 index 0000000000..acd5976904 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_reg.h @@ -0,0 +1,749 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMS_LP2HP_PERI_PMS_DATE_REG register + * Version control register + */ +#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0) +/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790; + * Version control register. + */ +#define PMS_LP2HP_PERI_PMS_DATE 0xFFFFFFFFU +#define PMS_LP2HP_PERI_PMS_DATE_M (PMS_LP2HP_PERI_PMS_DATE_V << PMS_LP2HP_PERI_PMS_DATE_S) +#define PMS_LP2HP_PERI_PMS_DATE_V 0xFFFFFFFFU +#define PMS_LP2HP_PERI_PMS_DATE_S 0 + +/** PMS_LP2HP_PERI_PMS_CLK_EN_REG register + * Clock gating register + */ +#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x4) +/** PMS_LP2HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating. + * 1: Keep the clock always on. + */ +#define PMS_LP2HP_PERI_PMS_CLK_EN (BIT(0)) +#define PMS_LP2HP_PERI_PMS_CLK_EN_M (PMS_LP2HP_PERI_PMS_CLK_EN_V << PMS_LP2HP_PERI_PMS_CLK_EN_S) +#define PMS_LP2HP_PERI_PMS_CLK_EN_V 0x00000001U +#define PMS_LP2HP_PERI_PMS_CLK_EN_S 0 + +/** PMS_LP_MM_PMS_REG0_REG register + * Permission control register0 for the LP CPU in machine mode + */ +#define PMS_LP_MM_PMS_REG0_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x8) +/** PMS_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access external RAM + * without going through cache. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_PSRAM_ALLOW (BIT(0)) +#define PMS_LP_MM_PSRAM_ALLOW_M (PMS_LP_MM_PSRAM_ALLOW_V << PMS_LP_MM_PSRAM_ALLOW_S) +#define PMS_LP_MM_PSRAM_ALLOW_V 0x00000001U +#define PMS_LP_MM_PSRAM_ALLOW_S 0 +/** PMS_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access external + * flash without going through cache. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_FLASH_ALLOW (BIT(1)) +#define PMS_LP_MM_FLASH_ALLOW_M (PMS_LP_MM_FLASH_ALLOW_V << PMS_LP_MM_FLASH_ALLOW_S) +#define PMS_LP_MM_FLASH_ALLOW_V 0x00000001U +#define PMS_LP_MM_FLASH_ALLOW_S 1 +/** PMS_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP L2M2M + * without going through cache. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_L2MEM_ALLOW (BIT(2)) +#define PMS_LP_MM_L2MEM_ALLOW_M (PMS_LP_MM_L2MEM_ALLOW_V << PMS_LP_MM_L2MEM_ALLOW_S) +#define PMS_LP_MM_L2MEM_ALLOW_V 0x00000001U +#define PMS_LP_MM_L2MEM_ALLOW_S 2 +/** PMS_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ROM + * without going through cache. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_L2ROM_ALLOW (BIT(3)) +#define PMS_LP_MM_L2ROM_ALLOW_M (PMS_LP_MM_L2ROM_ALLOW_V << PMS_LP_MM_L2ROM_ALLOW_S) +#define PMS_LP_MM_L2ROM_ALLOW_V 0x00000001U +#define PMS_LP_MM_L2ROM_ALLOW_S 3 +/** PMS_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access TRACE0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_TRACE0_ALLOW (BIT(6)) +#define PMS_LP_MM_TRACE0_ALLOW_M (PMS_LP_MM_TRACE0_ALLOW_V << PMS_LP_MM_TRACE0_ALLOW_S) +#define PMS_LP_MM_TRACE0_ALLOW_V 0x00000001U +#define PMS_LP_MM_TRACE0_ALLOW_S 6 +/** PMS_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access TRACE1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_TRACE1_ALLOW (BIT(7)) +#define PMS_LP_MM_TRACE1_ALLOW_M (PMS_LP_MM_TRACE1_ALLOW_V << PMS_LP_MM_TRACE1_ALLOW_S) +#define PMS_LP_MM_TRACE1_ALLOW_V 0x00000001U +#define PMS_LP_MM_TRACE1_ALLOW_S 7 +/** PMS_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access CPU bus + * monitor. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_CPU_BUS_MON_ALLOW (BIT(8)) +#define PMS_LP_MM_CPU_BUS_MON_ALLOW_M (PMS_LP_MM_CPU_BUS_MON_ALLOW_V << PMS_LP_MM_CPU_BUS_MON_ALLOW_S) +#define PMS_LP_MM_CPU_BUS_MON_ALLOW_V 0x00000001U +#define PMS_LP_MM_CPU_BUS_MON_ALLOW_S 8 +/** PMS_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access L2MEM + * monitor. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_L2MEM_MON_ALLOW (BIT(9)) +#define PMS_LP_MM_L2MEM_MON_ALLOW_M (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S) +#define PMS_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U +#define PMS_LP_MM_L2MEM_MON_ALLOW_S 9 +/** PMS_LP_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access SPM monitor. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_SPM_MON_ALLOW (BIT(10)) +#define PMS_LP_MM_SPM_MON_ALLOW_M (PMS_LP_MM_SPM_MON_ALLOW_V << PMS_LP_MM_SPM_MON_ALLOW_S) +#define PMS_LP_MM_SPM_MON_ALLOW_V 0x00000001U +#define PMS_LP_MM_SPM_MON_ALLOW_S 10 +/** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access cache. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_CACHE_ALLOW (BIT(11)) +#define PMS_LP_MM_CACHE_ALLOW_M (PMS_LP_MM_CACHE_ALLOW_V << PMS_LP_MM_CACHE_ALLOW_S) +#define PMS_LP_MM_CACHE_ALLOW_V 0x00000001U +#define PMS_LP_MM_CACHE_ALLOW_S 11 + +/** PMS_LP_MM_PMS_REG1_REG register + * Permission control register1 for the LP CPU in machine mode + */ +#define PMS_LP_MM_PMS_REG1_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x30) +/** PMS_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * high-speed USB 2.0 OTG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_USBOTG_ALLOW (BIT(0)) +#define PMS_LP_MM_HP_USBOTG_ALLOW_M (PMS_LP_MM_HP_USBOTG_ALLOW_V << PMS_LP_MM_HP_USBOTG_ALLOW_S) +#define PMS_LP_MM_HP_USBOTG_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_USBOTG_ALLOW_S 0 +/** PMS_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * full-speed USB 2.0 OTG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_USBOTG11_ALLOW (BIT(1)) +#define PMS_LP_MM_HP_USBOTG11_ALLOW_M (PMS_LP_MM_HP_USBOTG11_ALLOW_V << PMS_LP_MM_HP_USBOTG11_ALLOW_S) +#define PMS_LP_MM_HP_USBOTG11_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_USBOTG11_ALLOW_S 1 +/** PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * full-speed USB 2.0 OTG's wrap. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2)) +#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_M (PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_S) +#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_USBOTG11_WRAP_ALLOW_S 2 +/** PMS_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_GDMA_ALLOW (BIT(3)) +#define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S) +#define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_GDMA_ALLOW_S 3 +/** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP SDMMC. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_SDMMC_ALLOW (BIT(5)) +#define PMS_LP_MM_HP_SDMMC_ALLOW_M (PMS_LP_MM_HP_SDMMC_ALLOW_V << PMS_LP_MM_HP_SDMMC_ALLOW_S) +#define PMS_LP_MM_HP_SDMMC_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_SDMMC_ALLOW_S 5 +/** PMS_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access GDMA-AHB. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_AHB_PDMA_ALLOW (BIT(6)) +#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_M (PMS_LP_MM_HP_AHB_PDMA_ALLOW_V << PMS_LP_MM_HP_AHB_PDMA_ALLOW_S) +#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_AHB_PDMA_ALLOW_S 6 +/** PMS_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP JPEG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_JPEG_ALLOW (BIT(7)) +#define PMS_LP_MM_HP_JPEG_ALLOW_M (PMS_LP_MM_HP_JPEG_ALLOW_V << PMS_LP_MM_HP_JPEG_ALLOW_S) +#define PMS_LP_MM_HP_JPEG_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_JPEG_ALLOW_S 7 +/** PMS_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PPA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_PPA_ALLOW (BIT(8)) +#define PMS_LP_MM_HP_PPA_ALLOW_M (PMS_LP_MM_HP_PPA_ALLOW_V << PMS_LP_MM_HP_PPA_ALLOW_S) +#define PMS_LP_MM_HP_PPA_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_PPA_ALLOW_S 8 +/** PMS_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_DMA2D_ALLOW (BIT(9)) +#define PMS_LP_MM_HP_DMA2D_ALLOW_M (PMS_LP_MM_HP_DMA2D_ALLOW_V << PMS_LP_MM_HP_DMA2D_ALLOW_S) +#define PMS_LP_MM_HP_DMA2D_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_DMA2D_ALLOW_S 9 +/** PMS_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP key + * manager. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW (BIT(10)) +#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_M (PMS_LP_MM_HP_KEY_MANAGER_ALLOW_V << PMS_LP_MM_HP_KEY_MANAGER_ALLOW_S) +#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_KEY_MANAGER_ALLOW_S 10 +/** PMS_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_AXI_PDMA_ALLOW (BIT(11)) +#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_M (PMS_LP_MM_HP_AXI_PDMA_ALLOW_V << PMS_LP_MM_HP_AXI_PDMA_ALLOW_S) +#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_AXI_PDMA_ALLOW_S 11 +/** PMS_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP flash + * MSPI controller. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_FLASH_ALLOW (BIT(12)) +#define PMS_LP_MM_HP_FLASH_ALLOW_M (PMS_LP_MM_HP_FLASH_ALLOW_V << PMS_LP_MM_HP_FLASH_ALLOW_S) +#define PMS_LP_MM_HP_FLASH_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_FLASH_ALLOW_S 12 +/** PMS_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PSRAM + * MSPI controller. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_PSRAM_ALLOW (BIT(13)) +#define PMS_LP_MM_HP_PSRAM_ALLOW_M (PMS_LP_MM_HP_PSRAM_ALLOW_V << PMS_LP_MM_HP_PSRAM_ALLOW_S) +#define PMS_LP_MM_HP_PSRAM_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_PSRAM_ALLOW_S 13 +/** PMS_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP CRYPTO. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_CRYPTO_ALLOW (BIT(14)) +#define PMS_LP_MM_HP_CRYPTO_ALLOW_M (PMS_LP_MM_HP_CRYPTO_ALLOW_V << PMS_LP_MM_HP_CRYPTO_ALLOW_S) +#define PMS_LP_MM_HP_CRYPTO_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_CRYPTO_ALLOW_S 14 +/** PMS_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP EMAC. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_GMAC_ALLOW (BIT(15)) +#define PMS_LP_MM_HP_GMAC_ALLOW_M (PMS_LP_MM_HP_GMAC_ALLOW_V << PMS_LP_MM_HP_GMAC_ALLOW_S) +#define PMS_LP_MM_HP_GMAC_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_GMAC_ALLOW_S 15 +/** PMS_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * high-speed USB 2.0 OTG PHY. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_USB_PHY_ALLOW (BIT(16)) +#define PMS_LP_MM_HP_USB_PHY_ALLOW_M (PMS_LP_MM_HP_USB_PHY_ALLOW_V << PMS_LP_MM_HP_USB_PHY_ALLOW_S) +#define PMS_LP_MM_HP_USB_PHY_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_USB_PHY_ALLOW_S 16 +/** PMS_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PVT. + * 0: Not allowed + * 1: Allow + */ +#define PMS_LP_MM_HP_PVT_ALLOW (BIT(17)) +#define PMS_LP_MM_HP_PVT_ALLOW_M (PMS_LP_MM_HP_PVT_ALLOW_V << PMS_LP_MM_HP_PVT_ALLOW_S) +#define PMS_LP_MM_HP_PVT_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_PVT_ALLOW_S 17 +/** PMS_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI + * host. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_CSI_HOST_ALLOW (BIT(18)) +#define PMS_LP_MM_HP_CSI_HOST_ALLOW_M (PMS_LP_MM_HP_CSI_HOST_ALLOW_V << PMS_LP_MM_HP_CSI_HOST_ALLOW_S) +#define PMS_LP_MM_HP_CSI_HOST_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_CSI_HOST_ALLOW_S 18 +/** PMS_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI + * host. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_DSI_HOST_ALLOW (BIT(19)) +#define PMS_LP_MM_HP_DSI_HOST_ALLOW_M (PMS_LP_MM_HP_DSI_HOST_ALLOW_V << PMS_LP_MM_HP_DSI_HOST_ALLOW_S) +#define PMS_LP_MM_HP_DSI_HOST_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_DSI_HOST_ALLOW_S 19 +/** PMS_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ISP. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_ISP_ALLOW (BIT(20)) +#define PMS_LP_MM_HP_ISP_ALLOW_M (PMS_LP_MM_HP_ISP_ALLOW_V << PMS_LP_MM_HP_ISP_ALLOW_S) +#define PMS_LP_MM_HP_ISP_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_ISP_ALLOW_S 20 +/** PMS_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP H264 + * Encoder. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_H264_CORE_ALLOW (BIT(21)) +#define PMS_LP_MM_HP_H264_CORE_ALLOW_M (PMS_LP_MM_HP_H264_CORE_ALLOW_V << PMS_LP_MM_HP_H264_CORE_ALLOW_S) +#define PMS_LP_MM_HP_H264_CORE_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_H264_CORE_ALLOW_S 21 +/** PMS_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP RMT. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_RMT_ALLOW (BIT(22)) +#define PMS_LP_MM_HP_RMT_ALLOW_M (PMS_LP_MM_HP_RMT_ALLOW_V << PMS_LP_MM_HP_RMT_ALLOW_S) +#define PMS_LP_MM_HP_RMT_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_RMT_ALLOW_S 22 +/** PMS_LP_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP bit + * scrambler. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW (BIT(23)) +#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_M (PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V << PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S) +#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_BITSRAMBLER_ALLOW_S 23 +/** PMS_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP AXI ICM. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_AXI_ICM_ALLOW (BIT(24)) +#define PMS_LP_MM_HP_AXI_ICM_ALLOW_M (PMS_LP_MM_HP_AXI_ICM_ALLOW_V << PMS_LP_MM_HP_AXI_ICM_ALLOW_S) +#define PMS_LP_MM_HP_AXI_ICM_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_AXI_ICM_ALLOW_S 24 +/** PMS_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_PERI_PMS_ALLOW (BIT(25)) +#define PMS_LP_MM_HP_PERI_PMS_ALLOW_M (PMS_LP_MM_HP_PERI_PMS_ALLOW_V << PMS_LP_MM_HP_PERI_PMS_ALLOW_S) +#define PMS_LP_MM_HP_PERI_PMS_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_PERI_PMS_ALLOW_S 25 +/** PMS_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * LP2HP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW (BIT(26)) +#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_M (PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_S) +#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP2HP_PERI_PMS_ALLOW_S 26 +/** PMS_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * HP_DMA_PMS_REG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_DMA_PMS_ALLOW (BIT(27)) +#define PMS_LP_MM_DMA_PMS_ALLOW_M (PMS_LP_MM_DMA_PMS_ALLOW_V << PMS_LP_MM_DMA_PMS_ALLOW_S) +#define PMS_LP_MM_DMA_PMS_ALLOW_V 0x00000001U +#define PMS_LP_MM_DMA_PMS_ALLOW_S 27 +/** PMS_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access 2D-DMA. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_H264_DMA2D_ALLOW (BIT(28)) +#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_M (PMS_LP_MM_HP_H264_DMA2D_ALLOW_V << PMS_LP_MM_HP_H264_DMA2D_ALLOW_S) +#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_S 28 + +/** PMS_LP_MM_PMS_REG2_REG register + * Permission control register2 for the LP CPU in machine mode + */ +#define PMS_LP_MM_PMS_REG2_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0xa4) +/** PMS_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MCPWM0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_MCPWM0_ALLOW (BIT(0)) +#define PMS_LP_MM_HP_MCPWM0_ALLOW_M (PMS_LP_MM_HP_MCPWM0_ALLOW_V << PMS_LP_MM_HP_MCPWM0_ALLOW_S) +#define PMS_LP_MM_HP_MCPWM0_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_MCPWM0_ALLOW_S 0 +/** PMS_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP MCPWM1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_MCPWM1_ALLOW (BIT(1)) +#define PMS_LP_MM_HP_MCPWM1_ALLOW_M (PMS_LP_MM_HP_MCPWM1_ALLOW_V << PMS_LP_MM_HP_MCPWM1_ALLOW_S) +#define PMS_LP_MM_HP_MCPWM1_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_MCPWM1_ALLOW_S 1 +/** PMS_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP timer + * group0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW (BIT(2)) +#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_M (PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_S) +#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_TIMER_GROUP0_ALLOW_S 2 +/** PMS_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP timer + * group1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW (BIT(3)) +#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_M (PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_S) +#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_TIMER_GROUP1_ALLOW_S 3 +/** PMS_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2C0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I2C0_ALLOW (BIT(4)) +#define PMS_LP_MM_HP_I2C0_ALLOW_M (PMS_LP_MM_HP_I2C0_ALLOW_V << PMS_LP_MM_HP_I2C0_ALLOW_S) +#define PMS_LP_MM_HP_I2C0_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I2C0_ALLOW_S 4 +/** PMS_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2C1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I2C1_ALLOW (BIT(5)) +#define PMS_LP_MM_HP_I2C1_ALLOW_M (PMS_LP_MM_HP_I2C1_ALLOW_V << PMS_LP_MM_HP_I2C1_ALLOW_S) +#define PMS_LP_MM_HP_I2C1_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I2C1_ALLOW_S 5 +/** PMS_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2S0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I2S0_ALLOW (BIT(6)) +#define PMS_LP_MM_HP_I2S0_ALLOW_M (PMS_LP_MM_HP_I2S0_ALLOW_V << PMS_LP_MM_HP_I2S0_ALLOW_S) +#define PMS_LP_MM_HP_I2S0_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I2S0_ALLOW_S 6 +/** PMS_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2S1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I2S1_ALLOW (BIT(7)) +#define PMS_LP_MM_HP_I2S1_ALLOW_M (PMS_LP_MM_HP_I2S1_ALLOW_V << PMS_LP_MM_HP_I2S1_ALLOW_S) +#define PMS_LP_MM_HP_I2S1_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I2S1_ALLOW_S 7 +/** PMS_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I2S2. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I2S2_ALLOW (BIT(8)) +#define PMS_LP_MM_HP_I2S2_ALLOW_M (PMS_LP_MM_HP_I2S2_ALLOW_V << PMS_LP_MM_HP_I2S2_ALLOW_S) +#define PMS_LP_MM_HP_I2S2_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I2S2_ALLOW_S 8 +/** PMS_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PCNT. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_PCNT_ALLOW (BIT(9)) +#define PMS_LP_MM_HP_PCNT_ALLOW_M (PMS_LP_MM_HP_PCNT_ALLOW_V << PMS_LP_MM_HP_PCNT_ALLOW_S) +#define PMS_LP_MM_HP_PCNT_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_PCNT_ALLOW_S 9 +/** PMS_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_UART0_ALLOW (BIT(10)) +#define PMS_LP_MM_HP_UART0_ALLOW_M (PMS_LP_MM_HP_UART0_ALLOW_V << PMS_LP_MM_HP_UART0_ALLOW_S) +#define PMS_LP_MM_HP_UART0_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_UART0_ALLOW_S 10 +/** PMS_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_UART1_ALLOW (BIT(11)) +#define PMS_LP_MM_HP_UART1_ALLOW_M (PMS_LP_MM_HP_UART1_ALLOW_V << PMS_LP_MM_HP_UART1_ALLOW_S) +#define PMS_LP_MM_HP_UART1_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_UART1_ALLOW_S 11 +/** PMS_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART2. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_UART2_ALLOW (BIT(12)) +#define PMS_LP_MM_HP_UART2_ALLOW_M (PMS_LP_MM_HP_UART2_ALLOW_V << PMS_LP_MM_HP_UART2_ALLOW_S) +#define PMS_LP_MM_HP_UART2_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_UART2_ALLOW_S 12 +/** PMS_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART3. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_UART3_ALLOW (BIT(13)) +#define PMS_LP_MM_HP_UART3_ALLOW_M (PMS_LP_MM_HP_UART3_ALLOW_V << PMS_LP_MM_HP_UART3_ALLOW_S) +#define PMS_LP_MM_HP_UART3_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_UART3_ALLOW_S 13 +/** PMS_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UART4. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_UART4_ALLOW (BIT(14)) +#define PMS_LP_MM_HP_UART4_ALLOW_M (PMS_LP_MM_HP_UART4_ALLOW_V << PMS_LP_MM_HP_UART4_ALLOW_S) +#define PMS_LP_MM_HP_UART4_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_UART4_ALLOW_S 14 +/** PMS_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP PARLIO. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_PARLIO_ALLOW (BIT(15)) +#define PMS_LP_MM_HP_PARLIO_ALLOW_M (PMS_LP_MM_HP_PARLIO_ALLOW_V << PMS_LP_MM_HP_PARLIO_ALLOW_S) +#define PMS_LP_MM_HP_PARLIO_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_PARLIO_ALLOW_S 15 +/** PMS_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_GPSPI2_ALLOW (BIT(16)) +#define PMS_LP_MM_HP_GPSPI2_ALLOW_M (PMS_LP_MM_HP_GPSPI2_ALLOW_V << PMS_LP_MM_HP_GPSPI2_ALLOW_S) +#define PMS_LP_MM_HP_GPSPI2_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_GPSPI2_ALLOW_S 16 +/** PMS_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_GPSPI3_ALLOW (BIT(17)) +#define PMS_LP_MM_HP_GPSPI3_ALLOW_M (PMS_LP_MM_HP_GPSPI3_ALLOW_V << PMS_LP_MM_HP_GPSPI3_ALLOW_S) +#define PMS_LP_MM_HP_GPSPI3_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_GPSPI3_ALLOW_S 17 +/** PMS_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP + * USB/Serial JTAG Controller. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_USBDEVICE_ALLOW (BIT(18)) +#define PMS_LP_MM_HP_USBDEVICE_ALLOW_M (PMS_LP_MM_HP_USBDEVICE_ALLOW_V << PMS_LP_MM_HP_USBDEVICE_ALLOW_S) +#define PMS_LP_MM_HP_USBDEVICE_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_USBDEVICE_ALLOW_S 18 +/** PMS_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP LEDC. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_LEDC_ALLOW (BIT(19)) +#define PMS_LP_MM_HP_LEDC_ALLOW_M (PMS_LP_MM_HP_LEDC_ALLOW_V << PMS_LP_MM_HP_LEDC_ALLOW_S) +#define PMS_LP_MM_HP_LEDC_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_LEDC_ALLOW_S 19 +/** PMS_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ETM. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_ETM_ALLOW (BIT(21)) +#define PMS_LP_MM_HP_ETM_ALLOW_M (PMS_LP_MM_HP_ETM_ALLOW_V << PMS_LP_MM_HP_ETM_ALLOW_S) +#define PMS_LP_MM_HP_ETM_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_ETM_ALLOW_S 21 +/** PMS_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP interrupt + * matrix. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_INTRMTX_ALLOW (BIT(22)) +#define PMS_LP_MM_HP_INTRMTX_ALLOW_M (PMS_LP_MM_HP_INTRMTX_ALLOW_V << PMS_LP_MM_HP_INTRMTX_ALLOW_S) +#define PMS_LP_MM_HP_INTRMTX_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_INTRMTX_ALLOW_S 22 +/** PMS_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP TWAI0. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_TWAI0_ALLOW (BIT(23)) +#define PMS_LP_MM_HP_TWAI0_ALLOW_M (PMS_LP_MM_HP_TWAI0_ALLOW_V << PMS_LP_MM_HP_TWAI0_ALLOW_S) +#define PMS_LP_MM_HP_TWAI0_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_TWAI0_ALLOW_S 23 +/** PMS_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP TWAI1. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_TWAI1_ALLOW (BIT(24)) +#define PMS_LP_MM_HP_TWAI1_ALLOW_M (PMS_LP_MM_HP_TWAI1_ALLOW_V << PMS_LP_MM_HP_TWAI1_ALLOW_S) +#define PMS_LP_MM_HP_TWAI1_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_TWAI1_ALLOW_S 24 +/** PMS_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP TWAI2. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_TWAI2_ALLOW (BIT(25)) +#define PMS_LP_MM_HP_TWAI2_ALLOW_M (PMS_LP_MM_HP_TWAI2_ALLOW_V << PMS_LP_MM_HP_TWAI2_ALLOW_S) +#define PMS_LP_MM_HP_TWAI2_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_TWAI2_ALLOW_S 25 +/** PMS_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I3C + * master controller. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I3C_MST_ALLOW (BIT(26)) +#define PMS_LP_MM_HP_I3C_MST_ALLOW_M (PMS_LP_MM_HP_I3C_MST_ALLOW_V << PMS_LP_MM_HP_I3C_MST_ALLOW_S) +#define PMS_LP_MM_HP_I3C_MST_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I3C_MST_ALLOW_S 26 +/** PMS_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP I3C slave + * controller. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_I3C_SLV_ALLOW (BIT(27)) +#define PMS_LP_MM_HP_I3C_SLV_ALLOW_M (PMS_LP_MM_HP_I3C_SLV_ALLOW_V << PMS_LP_MM_HP_I3C_SLV_ALLOW_S) +#define PMS_LP_MM_HP_I3C_SLV_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_I3C_SLV_ALLOW_S 27 +/** PMS_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_LCDCAM_ALLOW (BIT(28)) +#define PMS_LP_MM_HP_LCDCAM_ALLOW_M (PMS_LP_MM_HP_LCDCAM_ALLOW_V << PMS_LP_MM_HP_LCDCAM_ALLOW_S) +#define PMS_LP_MM_HP_LCDCAM_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_LCDCAM_ALLOW_S 28 +/** PMS_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP ADC. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_ADC_ALLOW (BIT(30)) +#define PMS_LP_MM_HP_ADC_ALLOW_M (PMS_LP_MM_HP_ADC_ALLOW_V << PMS_LP_MM_HP_ADC_ALLOW_S) +#define PMS_LP_MM_HP_ADC_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_ADC_ALLOW_S 30 +/** PMS_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP UHCI. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_UHCI_ALLOW (BIT(31)) +#define PMS_LP_MM_HP_UHCI_ALLOW_M (PMS_LP_MM_HP_UHCI_ALLOW_V << PMS_LP_MM_HP_UHCI_ALLOW_S) +#define PMS_LP_MM_HP_UHCI_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_UHCI_ALLOW_S 31 + +/** PMS_LP_MM_PMS_REG3_REG register + * Permission control register3 for the LP CPU in machine mode + */ +#define PMS_LP_MM_PMS_REG3_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x11c) +/** PMS_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP GPIO + * Matrix. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_GPIO_ALLOW (BIT(0)) +#define PMS_LP_MM_HP_GPIO_ALLOW_M (PMS_LP_MM_HP_GPIO_ALLOW_V << PMS_LP_MM_HP_GPIO_ALLOW_S) +#define PMS_LP_MM_HP_GPIO_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_GPIO_ALLOW_S 0 +/** PMS_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP IO MUX. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_IOMUX_ALLOW (BIT(1)) +#define PMS_LP_MM_HP_IOMUX_ALLOW_M (PMS_LP_MM_HP_IOMUX_ALLOW_V << PMS_LP_MM_HP_IOMUX_ALLOW_S) +#define PMS_LP_MM_HP_IOMUX_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_IOMUX_ALLOW_S 1 +/** PMS_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP system + * timer. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_SYSTIMER_ALLOW (BIT(2)) +#define PMS_LP_MM_HP_SYSTIMER_ALLOW_M (PMS_LP_MM_HP_SYSTIMER_ALLOW_V << PMS_LP_MM_HP_SYSTIMER_ALLOW_S) +#define PMS_LP_MM_HP_SYSTIMER_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_SYSTIMER_ALLOW_S 2 +/** PMS_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access HP system + * register. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_SYS_REG_ALLOW (BIT(3)) +#define PMS_LP_MM_HP_SYS_REG_ALLOW_M (PMS_LP_MM_HP_SYS_REG_ALLOW_V << PMS_LP_MM_HP_SYS_REG_ALLOW_S) +#define PMS_LP_MM_HP_SYS_REG_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_SYS_REG_ALLOW_S 3 +/** PMS_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether the LP CPU in machine mode has permission to access + * HP_SYS_CLKRST. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP_CLKRST_ALLOW (BIT(4)) +#define PMS_LP_MM_HP_CLKRST_ALLOW_M (PMS_LP_MM_HP_CLKRST_ALLOW_V << PMS_LP_MM_HP_CLKRST_ALLOW_S) +#define PMS_LP_MM_HP_CLKRST_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP_CLKRST_ALLOW_S 4 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_struct.h new file mode 100644 index 0000000000..6fe0b0dc70 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp2hp_peri_pms_struct.h @@ -0,0 +1,414 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: TEE LP2HP PMS DATE REG */ +/** Type of lp2hp_pms_date register + * NA + */ +typedef union { + struct { + /** tee_date : R/W; bitpos: [31:0]; default: 2363943; + * NA + */ + uint32_t tee_date:32; + }; + uint32_t val; +} tee_lp2hp_pms_date_reg_t; + + +/** Group: TEE PMS CLK EN REG */ +/** Type of pms_clk_en register + * NA + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_pms_clk_en_reg_t; + + +/** Group: TEE LP MM PMS REG0 REG */ +/** Type of lp_mm_pms_reg0 register + * NA + */ +typedef union { + struct { + /** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_lp_mm_psram_allow:1; + /** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1; + * NA + */ + uint32_t reg_lp_mm_flash_allow:1; + /** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1; + * NA + */ + uint32_t reg_lp_mm_l2mem_allow:1; + /** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1; + * NA + */ + uint32_t reg_lp_mm_l2rom_allow:1; + uint32_t reserved_4:2; + /** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1; + * NA + */ + uint32_t reg_lp_mm_trace0_allow:1; + /** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1; + * NA + */ + uint32_t reg_lp_mm_trace1_allow:1; + /** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1; + * NA + */ + uint32_t reg_lp_mm_cpu_bus_mon_allow:1; + /** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1; + * NA + */ + uint32_t reg_lp_mm_l2mem_mon_allow:1; + /** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; + * NA + */ + uint32_t reg_lp_mm_tcm_mon_allow:1; + /** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1; + * NA + */ + uint32_t reg_lp_mm_cache_allow:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} tee_lp_mm_pms_reg0_reg_t; + + +/** Group: TEE LP MM PMS REG1 REG */ +/** Type of lp_mm_pms_reg1 register + * NA + */ +typedef union { + struct { + /** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_usbotg_allow:1; + /** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_usbotg11_allow:1; + /** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1; + /** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_gdma_allow:1; + /** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_regdma_allow:1; + /** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_sdmmc_allow:1; + /** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_ahb_pdma_allow:1; + /** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_jpeg_allow:1; + /** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_ppa_allow:1; + /** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_dma2d_allow:1; + /** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_key_manager_allow:1; + /** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_axi_pdma_allow:1; + /** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_flash_allow:1; + /** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_psram_allow:1; + /** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_crypto_allow:1; + /** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_gmac_allow:1; + /** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_usb_phy_allow:1; + /** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_pvt_allow:1; + /** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_csi_host_allow:1; + /** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_dsi_host_allow:1; + /** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_isp_allow:1; + /** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_h264_core_allow:1; + /** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_rmt_allow:1; + /** reg_lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_bitsrambler_allow:1; + /** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_axi_icm_allow:1; + /** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_peri_pms_allow:1; + /** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1; + /** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1; + * NA + */ + uint32_t reg_lp_mm_dma_pms_allow:1; + /** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_h264_dma2d_allow:1; + /** reg_lp_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1; + * NA + */ + uint32_t reg_lp_mm_axi_perf_mon_allow:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} tee_lp_mm_pms_reg1_reg_t; + + +/** Group: TEE LP MM PMS REG2 REG */ +/** Type of lp_mm_pms_reg2 register + * NA + */ +typedef union { + struct { + /** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_mcpwm0_allow:1; + /** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_mcpwm1_allow:1; + /** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_timer_group0_allow:1; + /** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_timer_group1_allow:1; + /** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i2c0_allow:1; + /** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i2c1_allow:1; + /** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i2s0_allow:1; + /** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i2s1_allow:1; + /** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i2s2_allow:1; + /** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_pcnt_allow:1; + /** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_uart0_allow:1; + /** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_uart1_allow:1; + /** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_uart2_allow:1; + /** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_uart3_allow:1; + /** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_uart4_allow:1; + /** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_parlio_allow:1; + /** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_gpspi2_allow:1; + /** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_gpspi3_allow:1; + /** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_usbdevice_allow:1; + /** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_ledc_allow:1; + uint32_t reserved_20:1; + /** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_etm_allow:1; + /** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_intrmtx_allow:1; + /** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_twai0_allow:1; + /** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_twai1_allow:1; + /** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_twai2_allow:1; + /** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i3c_mst_allow:1; + /** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_i3c_slv_allow:1; + /** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_lcdcam_allow:1; + uint32_t reserved_29:1; + /** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_adc_allow:1; + /** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_uhci_allow:1; + }; + uint32_t val; +} tee_lp_mm_pms_reg2_reg_t; + + +/** Group: TEE LP MM PMS REG3 REG */ +/** Type of lp_mm_pms_reg3 register + * NA + */ +typedef union { + struct { + /** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_gpio_allow:1; + /** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_iomux_allow:1; + /** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_systimer_allow:1; + /** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_sys_reg_allow:1; + /** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp_clkrst_allow:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} tee_lp_mm_pms_reg3_reg_t; + + +typedef struct { + volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date; + volatile tee_pms_clk_en_reg_t pms_clk_en; + volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0; + uint32_t reserved_00c[9]; + volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1; + uint32_t reserved_034[28]; + volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2; + uint32_t reserved_0a8[29]; + volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3; +} tee_dev_t; + +extern tee_dev_t LP2HP_PERI_PMS; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_adc_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_adc_reg.h new file mode 100644 index 0000000000..ef3629ede9 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_adc_reg.h @@ -0,0 +1,704 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RTCADC_READER1_CTRL_REG register + * Control the read operation of ADC1. + */ +#define RTCADC_READER1_CTRL_REG (DR_REG_RTCADC_BASE + 0x0) +/** RTCADC_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2; + * Clock divider. + */ +#define RTCADC_SAR1_CLK_DIV 0x000000FFU +#define RTCADC_SAR1_CLK_DIV_M (RTCADC_SAR1_CLK_DIV_V << RTCADC_SAR1_CLK_DIV_S) +#define RTCADC_SAR1_CLK_DIV_V 0x000000FFU +#define RTCADC_SAR1_CLK_DIV_S 0 +/** RTCADC_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0; + * Invert SAR ADC1 data. + */ +#define RTCADC_SAR1_DATA_INV (BIT(28)) +#define RTCADC_SAR1_DATA_INV_M (RTCADC_SAR1_DATA_INV_V << RTCADC_SAR1_DATA_INV_S) +#define RTCADC_SAR1_DATA_INV_V 0x00000001U +#define RTCADC_SAR1_DATA_INV_S 28 +/** RTCADC_SAR1_INT_EN : R/W; bitpos: [29]; default: 1; + * Enable saradc1 to send out interrupt. + */ +#define RTCADC_SAR1_INT_EN (BIT(29)) +#define RTCADC_SAR1_INT_EN_M (RTCADC_SAR1_INT_EN_V << RTCADC_SAR1_INT_EN_S) +#define RTCADC_SAR1_INT_EN_V 0x00000001U +#define RTCADC_SAR1_INT_EN_S 29 +/** RTCADC_SAR1_EN_PAD_FORCE_ENABLE : R/W; bitpos: [31:30]; default: 0; + * Force enable adc en_pad to analog circuit 2'b11: force enable . + */ +#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE 0x00000003U +#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_M (RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S) +#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_V 0x00000003U +#define RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S 30 + +/** RTCADC_MEAS1_CTRL2_REG register + * ADC1 configuration registers. + */ +#define RTCADC_MEAS1_CTRL2_REG (DR_REG_RTCADC_BASE + 0xc) +/** RTCADC_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0; + * SAR ADC1 data. + */ +#define RTCADC_MEAS1_DATA_SAR 0x0000FFFFU +#define RTCADC_MEAS1_DATA_SAR_M (RTCADC_MEAS1_DATA_SAR_V << RTCADC_MEAS1_DATA_SAR_S) +#define RTCADC_MEAS1_DATA_SAR_V 0x0000FFFFU +#define RTCADC_MEAS1_DATA_SAR_S 0 +/** RTCADC_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0; + * SAR ADC1 conversion done indication. + */ +#define RTCADC_MEAS1_DONE_SAR (BIT(16)) +#define RTCADC_MEAS1_DONE_SAR_M (RTCADC_MEAS1_DONE_SAR_V << RTCADC_MEAS1_DONE_SAR_S) +#define RTCADC_MEAS1_DONE_SAR_V 0x00000001U +#define RTCADC_MEAS1_DONE_SAR_S 16 +/** RTCADC_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0; + * SAR ADC1 controller (in RTC) starts conversion. + */ +#define RTCADC_MEAS1_START_SAR (BIT(17)) +#define RTCADC_MEAS1_START_SAR_M (RTCADC_MEAS1_START_SAR_V << RTCADC_MEAS1_START_SAR_S) +#define RTCADC_MEAS1_START_SAR_V 0x00000001U +#define RTCADC_MEAS1_START_SAR_S 17 +/** RTCADC_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0; + * 1: SAR ADC1 controller (in RTC) is started by SW. + */ +#define RTCADC_MEAS1_START_FORCE (BIT(18)) +#define RTCADC_MEAS1_START_FORCE_M (RTCADC_MEAS1_START_FORCE_V << RTCADC_MEAS1_START_FORCE_S) +#define RTCADC_MEAS1_START_FORCE_V 0x00000001U +#define RTCADC_MEAS1_START_FORCE_S 18 +/** RTCADC_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0; + * SAR ADC1 pad enable bitmap. + */ +#define RTCADC_SAR1_EN_PAD 0x00000FFFU +#define RTCADC_SAR1_EN_PAD_M (RTCADC_SAR1_EN_PAD_V << RTCADC_SAR1_EN_PAD_S) +#define RTCADC_SAR1_EN_PAD_V 0x00000FFFU +#define RTCADC_SAR1_EN_PAD_S 19 +/** RTCADC_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0; + * 1: SAR ADC1 pad enable bitmap is controlled by SW. + */ +#define RTCADC_SAR1_EN_PAD_FORCE (BIT(31)) +#define RTCADC_SAR1_EN_PAD_FORCE_M (RTCADC_SAR1_EN_PAD_FORCE_V << RTCADC_SAR1_EN_PAD_FORCE_S) +#define RTCADC_SAR1_EN_PAD_FORCE_V 0x00000001U +#define RTCADC_SAR1_EN_PAD_FORCE_S 31 + +/** RTCADC_MEAS1_MUX_REG register + * SAR ADC1 MUX register. + */ +#define RTCADC_MEAS1_MUX_REG (DR_REG_RTCADC_BASE + 0x10) +/** RTCADC_SAR1_DIG_FORCE : R/W; bitpos: [31]; default: 0; + * 1: SAR ADC1 controlled by DIG ADC1 CTRL. + */ +#define RTCADC_SAR1_DIG_FORCE (BIT(31)) +#define RTCADC_SAR1_DIG_FORCE_M (RTCADC_SAR1_DIG_FORCE_V << RTCADC_SAR1_DIG_FORCE_S) +#define RTCADC_SAR1_DIG_FORCE_V 0x00000001U +#define RTCADC_SAR1_DIG_FORCE_S 31 + +/** RTCADC_ATTEN1_REG register + * ADC1 attenuation registers. + */ +#define RTCADC_ATTEN1_REG (DR_REG_RTCADC_BASE + 0x14) +/** RTCADC_SAR1_ATTEN : R/W; bitpos: [31:0]; default: 4294967295; + * 2-bit attenuation for each pad. + */ +#define RTCADC_SAR1_ATTEN 0xFFFFFFFFU +#define RTCADC_SAR1_ATTEN_M (RTCADC_SAR1_ATTEN_V << RTCADC_SAR1_ATTEN_S) +#define RTCADC_SAR1_ATTEN_V 0xFFFFFFFFU +#define RTCADC_SAR1_ATTEN_S 0 + +/** RTCADC_READER2_CTRL_REG register + * Control the read operation of ADC2. + */ +#define RTCADC_READER2_CTRL_REG (DR_REG_RTCADC_BASE + 0x24) +/** RTCADC_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2; + * Clock divider. + */ +#define RTCADC_SAR2_CLK_DIV 0x000000FFU +#define RTCADC_SAR2_CLK_DIV_M (RTCADC_SAR2_CLK_DIV_V << RTCADC_SAR2_CLK_DIV_S) +#define RTCADC_SAR2_CLK_DIV_V 0x000000FFU +#define RTCADC_SAR2_CLK_DIV_S 0 +/** RTCADC_SAR2_WAIT_ARB_CYCLE : R/W; bitpos: [17:16]; default: 1; + * Wait arbit stable after sar_done. + */ +#define RTCADC_SAR2_WAIT_ARB_CYCLE 0x00000003U +#define RTCADC_SAR2_WAIT_ARB_CYCLE_M (RTCADC_SAR2_WAIT_ARB_CYCLE_V << RTCADC_SAR2_WAIT_ARB_CYCLE_S) +#define RTCADC_SAR2_WAIT_ARB_CYCLE_V 0x00000003U +#define RTCADC_SAR2_WAIT_ARB_CYCLE_S 16 +/** RTCADC_SAR2_EN_PAD_FORCE_ENABLE : R/W; bitpos: [28:27]; default: 0; + * Force enable adc en_pad to analog circuit 2'b11: force enable . + */ +#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE 0x00000003U +#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_M (RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V << RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S) +#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_V 0x00000003U +#define RTCADC_SAR2_EN_PAD_FORCE_ENABLE_S 27 +/** RTCADC_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0; + * Invert SAR ADC2 data. + */ +#define RTCADC_SAR2_DATA_INV (BIT(29)) +#define RTCADC_SAR2_DATA_INV_M (RTCADC_SAR2_DATA_INV_V << RTCADC_SAR2_DATA_INV_S) +#define RTCADC_SAR2_DATA_INV_V 0x00000001U +#define RTCADC_SAR2_DATA_INV_S 29 +/** RTCADC_SAR2_INT_EN : R/W; bitpos: [30]; default: 1; + * Enable saradc2 to send out interrupt. + */ +#define RTCADC_SAR2_INT_EN (BIT(30)) +#define RTCADC_SAR2_INT_EN_M (RTCADC_SAR2_INT_EN_V << RTCADC_SAR2_INT_EN_S) +#define RTCADC_SAR2_INT_EN_V 0x00000001U +#define RTCADC_SAR2_INT_EN_S 30 + +/** RTCADC_MEAS2_CTRL1_REG register + * ADC2 configuration registers. + */ +#define RTCADC_MEAS2_CTRL1_REG (DR_REG_RTCADC_BASE + 0x2c) +/** RTCADC_SAR2_CNTL_STATE : RO; bitpos: [2:0]; default: 0; + * saradc2_cntl_fsm. + */ +#define RTCADC_SAR2_CNTL_STATE 0x00000007U +#define RTCADC_SAR2_CNTL_STATE_M (RTCADC_SAR2_CNTL_STATE_V << RTCADC_SAR2_CNTL_STATE_S) +#define RTCADC_SAR2_CNTL_STATE_V 0x00000007U +#define RTCADC_SAR2_CNTL_STATE_S 0 +/** RTCADC_SAR2_PWDET_CAL_EN : R/W; bitpos: [3]; default: 0; + * RTC control pwdet enable. + */ +#define RTCADC_SAR2_PWDET_CAL_EN (BIT(3)) +#define RTCADC_SAR2_PWDET_CAL_EN_M (RTCADC_SAR2_PWDET_CAL_EN_V << RTCADC_SAR2_PWDET_CAL_EN_S) +#define RTCADC_SAR2_PWDET_CAL_EN_V 0x00000001U +#define RTCADC_SAR2_PWDET_CAL_EN_S 3 +/** RTCADC_SAR2_PKDET_CAL_EN : R/W; bitpos: [4]; default: 0; + * RTC control pkdet enable. + */ +#define RTCADC_SAR2_PKDET_CAL_EN (BIT(4)) +#define RTCADC_SAR2_PKDET_CAL_EN_M (RTCADC_SAR2_PKDET_CAL_EN_V << RTCADC_SAR2_PKDET_CAL_EN_S) +#define RTCADC_SAR2_PKDET_CAL_EN_V 0x00000001U +#define RTCADC_SAR2_PKDET_CAL_EN_S 4 +/** RTCADC_SAR2_EN_TEST : R/W; bitpos: [5]; default: 0; + * SAR2_EN_TEST. + */ +#define RTCADC_SAR2_EN_TEST (BIT(5)) +#define RTCADC_SAR2_EN_TEST_M (RTCADC_SAR2_EN_TEST_V << RTCADC_SAR2_EN_TEST_S) +#define RTCADC_SAR2_EN_TEST_V 0x00000001U +#define RTCADC_SAR2_EN_TEST_S 5 + +/** RTCADC_MEAS2_CTRL2_REG register + * ADC2 configuration registers. + */ +#define RTCADC_MEAS2_CTRL2_REG (DR_REG_RTCADC_BASE + 0x30) +/** RTCADC_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0; + * SAR ADC2 data. + */ +#define RTCADC_MEAS2_DATA_SAR 0x0000FFFFU +#define RTCADC_MEAS2_DATA_SAR_M (RTCADC_MEAS2_DATA_SAR_V << RTCADC_MEAS2_DATA_SAR_S) +#define RTCADC_MEAS2_DATA_SAR_V 0x0000FFFFU +#define RTCADC_MEAS2_DATA_SAR_S 0 +/** RTCADC_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0; + * SAR ADC2 conversion done indication. + */ +#define RTCADC_MEAS2_DONE_SAR (BIT(16)) +#define RTCADC_MEAS2_DONE_SAR_M (RTCADC_MEAS2_DONE_SAR_V << RTCADC_MEAS2_DONE_SAR_S) +#define RTCADC_MEAS2_DONE_SAR_V 0x00000001U +#define RTCADC_MEAS2_DONE_SAR_S 16 +/** RTCADC_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0; + * SAR ADC2 controller (in RTC) starts conversion. + */ +#define RTCADC_MEAS2_START_SAR (BIT(17)) +#define RTCADC_MEAS2_START_SAR_M (RTCADC_MEAS2_START_SAR_V << RTCADC_MEAS2_START_SAR_S) +#define RTCADC_MEAS2_START_SAR_V 0x00000001U +#define RTCADC_MEAS2_START_SAR_S 17 +/** RTCADC_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0; + * 1: SAR ADC2 controller (in RTC) is started by SW. + */ +#define RTCADC_MEAS2_START_FORCE (BIT(18)) +#define RTCADC_MEAS2_START_FORCE_M (RTCADC_MEAS2_START_FORCE_V << RTCADC_MEAS2_START_FORCE_S) +#define RTCADC_MEAS2_START_FORCE_V 0x00000001U +#define RTCADC_MEAS2_START_FORCE_S 18 +/** RTCADC_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0; + * SAR ADC2 pad enable bitmap. + */ +#define RTCADC_SAR2_EN_PAD 0x00000FFFU +#define RTCADC_SAR2_EN_PAD_M (RTCADC_SAR2_EN_PAD_V << RTCADC_SAR2_EN_PAD_S) +#define RTCADC_SAR2_EN_PAD_V 0x00000FFFU +#define RTCADC_SAR2_EN_PAD_S 19 +/** RTCADC_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0; + * 1: SAR ADC2 pad enable bitmap is controlled by SW. + */ +#define RTCADC_SAR2_EN_PAD_FORCE (BIT(31)) +#define RTCADC_SAR2_EN_PAD_FORCE_M (RTCADC_SAR2_EN_PAD_FORCE_V << RTCADC_SAR2_EN_PAD_FORCE_S) +#define RTCADC_SAR2_EN_PAD_FORCE_V 0x00000001U +#define RTCADC_SAR2_EN_PAD_FORCE_S 31 + +/** RTCADC_MEAS2_MUX_REG register + * SAR ADC2 MUX register. + */ +#define RTCADC_MEAS2_MUX_REG (DR_REG_RTCADC_BASE + 0x34) +/** RTCADC_SAR2_PWDET_CCT : R/W; bitpos: [30:28]; default: 0; + * SAR2_PWDET_CCT. + */ +#define RTCADC_SAR2_PWDET_CCT 0x00000007U +#define RTCADC_SAR2_PWDET_CCT_M (RTCADC_SAR2_PWDET_CCT_V << RTCADC_SAR2_PWDET_CCT_S) +#define RTCADC_SAR2_PWDET_CCT_V 0x00000007U +#define RTCADC_SAR2_PWDET_CCT_S 28 +/** RTCADC_SAR2_RTC_FORCE : R/W; bitpos: [31]; default: 0; + * In sleep, force to use rtc to control ADC. + */ +#define RTCADC_SAR2_RTC_FORCE (BIT(31)) +#define RTCADC_SAR2_RTC_FORCE_M (RTCADC_SAR2_RTC_FORCE_V << RTCADC_SAR2_RTC_FORCE_S) +#define RTCADC_SAR2_RTC_FORCE_V 0x00000001U +#define RTCADC_SAR2_RTC_FORCE_S 31 + +/** RTCADC_ATTEN2_REG register + * ADC1 attenuation registers. + */ +#define RTCADC_ATTEN2_REG (DR_REG_RTCADC_BASE + 0x38) +/** RTCADC_SAR2_ATTEN : R/W; bitpos: [31:0]; default: 4294967295; + * 2-bit attenuation for each pad. + */ +#define RTCADC_SAR2_ATTEN 0xFFFFFFFFU +#define RTCADC_SAR2_ATTEN_M (RTCADC_SAR2_ATTEN_V << RTCADC_SAR2_ATTEN_S) +#define RTCADC_SAR2_ATTEN_V 0xFFFFFFFFU +#define RTCADC_SAR2_ATTEN_S 0 + +/** RTCADC_FORCE_WPD_SAR_REG register + * In sleep, force to use rtc to control ADC + */ +#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_RTCADC_BASE + 0x3c) +/** RTCADC_FORCE_XPD_SAR1 : R/W; bitpos: [1:0]; default: 0; + * 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware + * control. + */ +#define RTCADC_FORCE_XPD_SAR1 0x00000003U +#define RTCADC_FORCE_XPD_SAR1_M (RTCADC_FORCE_XPD_SAR1_V << RTCADC_FORCE_XPD_SAR1_S) +#define RTCADC_FORCE_XPD_SAR1_V 0x00000003U +#define RTCADC_FORCE_XPD_SAR1_S 0 +/** RTCADC_FORCE_XPD_SAR2 : R/W; bitpos: [3:2]; default: 0; + * 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware + * control. + */ +#define RTCADC_FORCE_XPD_SAR2 0x00000003U +#define RTCADC_FORCE_XPD_SAR2_M (RTCADC_FORCE_XPD_SAR2_V << RTCADC_FORCE_XPD_SAR2_S) +#define RTCADC_FORCE_XPD_SAR2_V 0x00000003U +#define RTCADC_FORCE_XPD_SAR2_S 2 + +/** RTCADC_COCPU_INT_RAW_REG register + * Interrupt raw registers. + */ +#define RTCADC_COCPU_INT_RAW_REG (DR_REG_RTCADC_BASE + 0x48) +/** RTCADC_COCPU_SARADC1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int raw. + */ +#define RTCADC_COCPU_SARADC1_INT_RAW (BIT(0)) +#define RTCADC_COCPU_SARADC1_INT_RAW_M (RTCADC_COCPU_SARADC1_INT_RAW_V << RTCADC_COCPU_SARADC1_INT_RAW_S) +#define RTCADC_COCPU_SARADC1_INT_RAW_V 0x00000001U +#define RTCADC_COCPU_SARADC1_INT_RAW_S 0 +/** RTCADC_COCPU_SARADC2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int raw. + */ +#define RTCADC_COCPU_SARADC2_INT_RAW (BIT(1)) +#define RTCADC_COCPU_SARADC2_INT_RAW_M (RTCADC_COCPU_SARADC2_INT_RAW_V << RTCADC_COCPU_SARADC2_INT_RAW_S) +#define RTCADC_COCPU_SARADC2_INT_RAW_V 0x00000001U +#define RTCADC_COCPU_SARADC2_INT_RAW_S 1 +/** RTCADC_COCPU_SARADC1_ERROR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * An error occurs from ADC1, int raw. + */ +#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW (BIT(2)) +#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_M (RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S) +#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V 0x00000001U +#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S 2 +/** RTCADC_COCPU_SARADC2_ERROR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * An error occurs from ADC2, int raw. + */ +#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW (BIT(3)) +#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_M (RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S) +#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V 0x00000001U +#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S 3 +/** RTCADC_COCPU_SARADC1_WAKE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int raw. + */ +#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW (BIT(4)) +#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_M (RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S) +#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_V 0x00000001U +#define RTCADC_COCPU_SARADC1_WAKE_INT_RAW_S 4 +/** RTCADC_COCPU_SARADC2_WAKE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int raw. + */ +#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW (BIT(5)) +#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_M (RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V << RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S) +#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_V 0x00000001U +#define RTCADC_COCPU_SARADC2_WAKE_INT_RAW_S 5 + +/** RTCADC_INT_ENA_REG register + * Interrupt enable registers. + */ +#define RTCADC_INT_ENA_REG (DR_REG_RTCADC_BASE + 0x4c) +/** RTCADC_COCPU_SARADC1_INT_ENA : R/WTC; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int enable. + */ +#define RTCADC_COCPU_SARADC1_INT_ENA (BIT(0)) +#define RTCADC_COCPU_SARADC1_INT_ENA_M (RTCADC_COCPU_SARADC1_INT_ENA_V << RTCADC_COCPU_SARADC1_INT_ENA_S) +#define RTCADC_COCPU_SARADC1_INT_ENA_V 0x00000001U +#define RTCADC_COCPU_SARADC1_INT_ENA_S 0 +/** RTCADC_COCPU_SARADC2_INT_ENA : R/WTC; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int enable. + */ +#define RTCADC_COCPU_SARADC2_INT_ENA (BIT(1)) +#define RTCADC_COCPU_SARADC2_INT_ENA_M (RTCADC_COCPU_SARADC2_INT_ENA_V << RTCADC_COCPU_SARADC2_INT_ENA_S) +#define RTCADC_COCPU_SARADC2_INT_ENA_V 0x00000001U +#define RTCADC_COCPU_SARADC2_INT_ENA_S 1 +/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA : R/WTC; bitpos: [2]; default: 0; + * An error occurs from ADC1, int enable. + */ +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA (BIT(2)) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V 0x00000001U +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S 2 +/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA : R/WTC; bitpos: [3]; default: 0; + * An error occurs from ADC2, int enable. + */ +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA (BIT(3)) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V 0x00000001U +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S 3 +/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA : R/WTC; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int enable. + */ +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA (BIT(4)) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_M (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_V 0x00000001U +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_S 4 +/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA : R/WTC; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int enable. + */ +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA (BIT(5)) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_M (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_V 0x00000001U +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_S 5 + +/** RTCADC_INT_ST_REG register + * Interrupt status registers. + */ +#define RTCADC_INT_ST_REG (DR_REG_RTCADC_BASE + 0x50) +/** RTCADC_COCPU_SARADC1_INT_ST : RO; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int status. + */ +#define RTCADC_COCPU_SARADC1_INT_ST (BIT(0)) +#define RTCADC_COCPU_SARADC1_INT_ST_M (RTCADC_COCPU_SARADC1_INT_ST_V << RTCADC_COCPU_SARADC1_INT_ST_S) +#define RTCADC_COCPU_SARADC1_INT_ST_V 0x00000001U +#define RTCADC_COCPU_SARADC1_INT_ST_S 0 +/** RTCADC_COCPU_SARADC2_INT_ST : RO; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int status. + */ +#define RTCADC_COCPU_SARADC2_INT_ST (BIT(1)) +#define RTCADC_COCPU_SARADC2_INT_ST_M (RTCADC_COCPU_SARADC2_INT_ST_V << RTCADC_COCPU_SARADC2_INT_ST_S) +#define RTCADC_COCPU_SARADC2_INT_ST_V 0x00000001U +#define RTCADC_COCPU_SARADC2_INT_ST_S 1 +/** RTCADC_COCPU_SARADC1_ERROR_INT_ST : RO; bitpos: [2]; default: 0; + * An error occurs from ADC1, int status. + */ +#define RTCADC_COCPU_SARADC1_ERROR_INT_ST (BIT(2)) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_M (RTCADC_COCPU_SARADC1_ERROR_INT_ST_V << RTCADC_COCPU_SARADC1_ERROR_INT_ST_S) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_V 0x00000001U +#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_S 2 +/** RTCADC_COCPU_SARADC2_ERROR_INT_ST : RO; bitpos: [3]; default: 0; + * An error occurs from ADC2, int status. + */ +#define RTCADC_COCPU_SARADC2_ERROR_INT_ST (BIT(3)) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_M (RTCADC_COCPU_SARADC2_ERROR_INT_ST_V << RTCADC_COCPU_SARADC2_ERROR_INT_ST_S) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_V 0x00000001U +#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_S 3 +/** RTCADC_COCPU_SARADC1_WAKE_INT_ST : RO; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int status. + */ +#define RTCADC_COCPU_SARADC1_WAKE_INT_ST (BIT(4)) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_M (RTCADC_COCPU_SARADC1_WAKE_INT_ST_V << RTCADC_COCPU_SARADC1_WAKE_INT_ST_S) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_V 0x00000001U +#define RTCADC_COCPU_SARADC1_WAKE_INT_ST_S 4 +/** RTCADC_COCPU_SARADC2_WAKE_INT_ST : RO; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int status. + */ +#define RTCADC_COCPU_SARADC2_WAKE_INT_ST (BIT(5)) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_M (RTCADC_COCPU_SARADC2_WAKE_INT_ST_V << RTCADC_COCPU_SARADC2_WAKE_INT_ST_S) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_V 0x00000001U +#define RTCADC_COCPU_SARADC2_WAKE_INT_ST_S 5 + +/** RTCADC_INT_CLR_REG register + * Interrupt clear registers. + */ +#define RTCADC_INT_CLR_REG (DR_REG_RTCADC_BASE + 0x54) +/** RTCADC_COCPU_SARADC1_INT_CLR : WT; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int clear. + */ +#define RTCADC_COCPU_SARADC1_INT_CLR (BIT(0)) +#define RTCADC_COCPU_SARADC1_INT_CLR_M (RTCADC_COCPU_SARADC1_INT_CLR_V << RTCADC_COCPU_SARADC1_INT_CLR_S) +#define RTCADC_COCPU_SARADC1_INT_CLR_V 0x00000001U +#define RTCADC_COCPU_SARADC1_INT_CLR_S 0 +/** RTCADC_COCPU_SARADC2_INT_CLR : WT; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int clear. + */ +#define RTCADC_COCPU_SARADC2_INT_CLR (BIT(1)) +#define RTCADC_COCPU_SARADC2_INT_CLR_M (RTCADC_COCPU_SARADC2_INT_CLR_V << RTCADC_COCPU_SARADC2_INT_CLR_S) +#define RTCADC_COCPU_SARADC2_INT_CLR_V 0x00000001U +#define RTCADC_COCPU_SARADC2_INT_CLR_S 1 +/** RTCADC_COCPU_SARADC1_ERROR_INT_CLR : WT; bitpos: [2]; default: 0; + * An error occurs from ADC1, int clear. + */ +#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR (BIT(2)) +#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_M (RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S) +#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V 0x00000001U +#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S 2 +/** RTCADC_COCPU_SARADC2_ERROR_INT_CLR : WT; bitpos: [3]; default: 0; + * An error occurs from ADC2, int clear. + */ +#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR (BIT(3)) +#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_M (RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S) +#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V 0x00000001U +#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S 3 +/** RTCADC_COCPU_SARADC1_WAKE_INT_CLR : WT; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int clear. + */ +#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR (BIT(4)) +#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_M (RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S) +#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_V 0x00000001U +#define RTCADC_COCPU_SARADC1_WAKE_INT_CLR_S 4 +/** RTCADC_COCPU_SARADC2_WAKE_INT_CLR : WT; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int clear. + */ +#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR (BIT(5)) +#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_M (RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V << RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S) +#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_V 0x00000001U +#define RTCADC_COCPU_SARADC2_WAKE_INT_CLR_S 5 + +/** RTCADC_INT_ENA_W1TS_REG register + * Interrupt enable assert registers. + */ +#define RTCADC_INT_ENA_W1TS_REG (DR_REG_RTCADC_BASE + 0x58) +/** RTCADC_COCPU_SARADC1_INT_ENA_W1TS : WT; bitpos: [0]; default: 0; + * ADC1 Conversion is done, write 1 to assert int enable. + */ +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS (BIT(0)) +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S) +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_V 0x00000001U +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TS_S 0 +/** RTCADC_COCPU_SARADC2_INT_ENA_W1TS : WT; bitpos: [1]; default: 0; + * ADC2 Conversion is done, write 1 to assert int enable. + */ +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS (BIT(1)) +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S) +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V 0x00000001U +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S 1 +/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS : WT; bitpos: [2]; default: 0; + * An error occurs from ADC1, write 1 to assert int enable. + */ +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS (BIT(2)) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V 0x00000001U +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S 2 +/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS : WT; bitpos: [3]; default: 0; + * An error occurs from ADC2, write 1 to assert int enable. + */ +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS (BIT(3)) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V 0x00000001U +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S 3 +/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS : WT; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, write 1 to assert int enable. + */ +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS (BIT(4)) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_V 0x00000001U +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TS_S 4 +/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS : WT; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, write 1 to assert int enable. + */ +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS (BIT(5)) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_V 0x00000001U +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TS_S 5 + +/** RTCADC_INT_ENA_W1TC_REG register + * Interrupt enable deassert registers. + */ +#define RTCADC_INT_ENA_W1TC_REG (DR_REG_RTCADC_BASE + 0x5c) +/** RTCADC_COCPU_SARADC1_INT_ENA_W1TC : WT; bitpos: [0]; default: 0; + * ADC1 Conversion is done, write 1 to deassert int enable. + */ +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC (BIT(0)) +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S) +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_V 0x00000001U +#define RTCADC_COCPU_SARADC1_INT_ENA_W1TC_S 0 +/** RTCADC_COCPU_SARADC2_INT_ENA_W1TC : WT; bitpos: [1]; default: 0; + * ADC2 Conversion is done, write 1 to deassert int enable. + */ +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC (BIT(1)) +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S) +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V 0x00000001U +#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S 1 +/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC : WT; bitpos: [2]; default: 0; + * An error occurs from ADC1, write 1 to deassert int enable. + */ +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC (BIT(2)) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S) +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V 0x00000001U +#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S 2 +/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC : WT; bitpos: [3]; default: 0; + * An error occurs from ADC2, write 1 to deassert int enable. + */ +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC (BIT(3)) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S) +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V 0x00000001U +#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S 3 +/** RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC : WT; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, write 1 to deassert int enable. + */ +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC (BIT(4)) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S) +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_V 0x00000001U +#define RTCADC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_S 4 +/** RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC : WT; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, write 1 to deassert int enable. + */ +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC (BIT(5)) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S) +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_V 0x00000001U +#define RTCADC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_S 5 + +/** RTCADC_WAKEUP1_REG register + * ADC1 wakeup configuration registers. + */ +#define RTCADC_WAKEUP1_REG (DR_REG_RTCADC_BASE + 0x60) +/** RTCADC_SAR1_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0; + * Lower threshold. + */ +#define RTCADC_SAR1_WAKEUP_TH_LOW 0x00000FFFU +#define RTCADC_SAR1_WAKEUP_TH_LOW_M (RTCADC_SAR1_WAKEUP_TH_LOW_V << RTCADC_SAR1_WAKEUP_TH_LOW_S) +#define RTCADC_SAR1_WAKEUP_TH_LOW_V 0x00000FFFU +#define RTCADC_SAR1_WAKEUP_TH_LOW_S 0 +/** RTCADC_SAR1_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095; + * Upper threshold. + */ +#define RTCADC_SAR1_WAKEUP_TH_HIGH 0x00000FFFU +#define RTCADC_SAR1_WAKEUP_TH_HIGH_M (RTCADC_SAR1_WAKEUP_TH_HIGH_V << RTCADC_SAR1_WAKEUP_TH_HIGH_S) +#define RTCADC_SAR1_WAKEUP_TH_HIGH_V 0x00000FFFU +#define RTCADC_SAR1_WAKEUP_TH_HIGH_S 14 +/** RTCADC_SAR1_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ +#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH (BIT(29)) +#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_M (RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S) +#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define RTCADC_SAR1_WAKEUP_OVER_UPPER_TH_S 29 +/** RTCADC_SAR1_WAKEUP_EN : R/W; bitpos: [30]; default: 0; + * Wakeup function enable. + */ +#define RTCADC_SAR1_WAKEUP_EN (BIT(30)) +#define RTCADC_SAR1_WAKEUP_EN_M (RTCADC_SAR1_WAKEUP_EN_V << RTCADC_SAR1_WAKEUP_EN_S) +#define RTCADC_SAR1_WAKEUP_EN_V 0x00000001U +#define RTCADC_SAR1_WAKEUP_EN_S 30 +/** RTCADC_SAR1_WAKEUP_MODE : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ +#define RTCADC_SAR1_WAKEUP_MODE (BIT(31)) +#define RTCADC_SAR1_WAKEUP_MODE_M (RTCADC_SAR1_WAKEUP_MODE_V << RTCADC_SAR1_WAKEUP_MODE_S) +#define RTCADC_SAR1_WAKEUP_MODE_V 0x00000001U +#define RTCADC_SAR1_WAKEUP_MODE_S 31 + +/** RTCADC_WAKEUP2_REG register + * ADC2 wakeup configuration registers. + */ +#define RTCADC_WAKEUP2_REG (DR_REG_RTCADC_BASE + 0x64) +/** RTCADC_SAR2_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0; + * Lower threshold. + */ +#define RTCADC_SAR2_WAKEUP_TH_LOW 0x00000FFFU +#define RTCADC_SAR2_WAKEUP_TH_LOW_M (RTCADC_SAR2_WAKEUP_TH_LOW_V << RTCADC_SAR2_WAKEUP_TH_LOW_S) +#define RTCADC_SAR2_WAKEUP_TH_LOW_V 0x00000FFFU +#define RTCADC_SAR2_WAKEUP_TH_LOW_S 0 +/** RTCADC_SAR2_WAKEUP_TH_HIGH : R/W; bitpos: [25:14]; default: 4095; + * Upper threshold. + */ +#define RTCADC_SAR2_WAKEUP_TH_HIGH 0x00000FFFU +#define RTCADC_SAR2_WAKEUP_TH_HIGH_M (RTCADC_SAR2_WAKEUP_TH_HIGH_V << RTCADC_SAR2_WAKEUP_TH_HIGH_S) +#define RTCADC_SAR2_WAKEUP_TH_HIGH_V 0x00000FFFU +#define RTCADC_SAR2_WAKEUP_TH_HIGH_S 14 +/** RTCADC_SAR2_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ +#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH (BIT(29)) +#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_M (RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V << RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S) +#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_V 0x00000001U +#define RTCADC_SAR2_WAKEUP_OVER_UPPER_TH_S 29 +/** RTCADC_SAR2_WAKEUP_EN : R/W; bitpos: [30]; default: 0; + * Wakeup function enable. + */ +#define RTCADC_SAR2_WAKEUP_EN (BIT(30)) +#define RTCADC_SAR2_WAKEUP_EN_M (RTCADC_SAR2_WAKEUP_EN_V << RTCADC_SAR2_WAKEUP_EN_S) +#define RTCADC_SAR2_WAKEUP_EN_V 0x00000001U +#define RTCADC_SAR2_WAKEUP_EN_S 30 +/** RTCADC_SAR2_WAKEUP_MODE : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ +#define RTCADC_SAR2_WAKEUP_MODE (BIT(31)) +#define RTCADC_SAR2_WAKEUP_MODE_M (RTCADC_SAR2_WAKEUP_MODE_V << RTCADC_SAR2_WAKEUP_MODE_S) +#define RTCADC_SAR2_WAKEUP_MODE_V 0x00000001U +#define RTCADC_SAR2_WAKEUP_MODE_S 31 + +/** RTCADC_WAKEUP_SEL_REG register + * Wakeup source select register. + */ +#define RTCADC_WAKEUP_SEL_REG (DR_REG_RTCADC_BASE + 0x68) +/** RTCADC_SAR_WAKEUP_SEL : R/W; bitpos: [0]; default: 0; + * 0: ADC1. 1: ADC2. + */ +#define RTCADC_SAR_WAKEUP_SEL (BIT(0)) +#define RTCADC_SAR_WAKEUP_SEL_M (RTCADC_SAR_WAKEUP_SEL_V << RTCADC_SAR_WAKEUP_SEL_S) +#define RTCADC_SAR_WAKEUP_SEL_V 0x00000001U +#define RTCADC_SAR_WAKEUP_SEL_S 0 + +/** RTCADC_SAR1_HW_WAKEUP_REG register + * Hardware automatic sampling registers for wakeup function. + */ +#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x6c) +/** RTCADC_ADC1_HW_READ_EN_I : R/W; bitpos: [0]; default: 0; + * Enable hardware automatic sampling. + */ +#define RTCADC_ADC1_HW_READ_EN_I (BIT(0)) +#define RTCADC_ADC1_HW_READ_EN_I_M (RTCADC_ADC1_HW_READ_EN_I_V << RTCADC_ADC1_HW_READ_EN_I_S) +#define RTCADC_ADC1_HW_READ_EN_I_V 0x00000001U +#define RTCADC_ADC1_HW_READ_EN_I_S 0 +/** RTCADC_ADC1_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100; + * Hardware automatic sampling rate. + */ +#define RTCADC_ADC1_HW_READ_RATE_I 0x0000FFFFU +#define RTCADC_ADC1_HW_READ_RATE_I_M (RTCADC_ADC1_HW_READ_RATE_I_V << RTCADC_ADC1_HW_READ_RATE_I_S) +#define RTCADC_ADC1_HW_READ_RATE_I_V 0x0000FFFFU +#define RTCADC_ADC1_HW_READ_RATE_I_S 1 + +/** RTCADC_SAR2_HW_WAKEUP_REG register + * Hardware automatic sampling registers for wakeup function. + */ +#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x70) +/** RTCADC_ADC2_HW_READ_EN_I : R/W; bitpos: [0]; default: 0; + * Enable hardware automatic sampling. + */ +#define RTCADC_ADC2_HW_READ_EN_I (BIT(0)) +#define RTCADC_ADC2_HW_READ_EN_I_M (RTCADC_ADC2_HW_READ_EN_I_V << RTCADC_ADC2_HW_READ_EN_I_S) +#define RTCADC_ADC2_HW_READ_EN_I_V 0x00000001U +#define RTCADC_ADC2_HW_READ_EN_I_S 0 +/** RTCADC_ADC2_HW_READ_RATE_I : R/W; bitpos: [16:1]; default: 100; + * Hardware automatic sampling rate. + */ +#define RTCADC_ADC2_HW_READ_RATE_I 0x0000FFFFU +#define RTCADC_ADC2_HW_READ_RATE_I_M (RTCADC_ADC2_HW_READ_RATE_I_V << RTCADC_ADC2_HW_READ_RATE_I_S) +#define RTCADC_ADC2_HW_READ_RATE_I_V 0x0000FFFFU +#define RTCADC_ADC2_HW_READ_RATE_I_S 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_adc_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_adc_struct.h new file mode 100644 index 0000000000..e256dd83d4 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_adc_struct.h @@ -0,0 +1,603 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: ADC1 control registers. */ +/** Type of reader1_ctrl register + * Control the read operation of ADC1. + */ +typedef union { + struct { + /** sar1_clk_div : R/W; bitpos: [7:0]; default: 2; + * Clock divider. + */ + uint32_t sar1_clk_div:8; + uint32_t reserved_8:20; + /** sar1_data_inv : R/W; bitpos: [28]; default: 0; + * Invert SAR ADC1 data. + */ + uint32_t sar1_data_inv:1; + /** sar1_int_en : R/W; bitpos: [29]; default: 1; + * Enable saradc1 to send out interrupt. + */ + uint32_t sar1_int_en:1; + /** sar1_en_pad_force_enable : R/W; bitpos: [31:30]; default: 0; + * Force enable adc en_pad to analog circuit 2'b11: force enable . + */ + uint32_t sar1_en_pad_force_enable:2; + }; + uint32_t val; +} rtcadc_reader1_ctrl_reg_t; + +/** Type of meas1_ctrl2 register + * ADC1 configuration registers. + */ +typedef union { + struct { + /** meas1_data_sar : RO; bitpos: [15:0]; default: 0; + * SAR ADC1 data. + */ + uint32_t meas1_data_sar:16; + /** meas1_done_sar : RO; bitpos: [16]; default: 0; + * SAR ADC1 conversion done indication. + */ + uint32_t meas1_done_sar:1; + /** meas1_start_sar : R/W; bitpos: [17]; default: 0; + * SAR ADC1 controller (in RTC) starts conversion. + */ + uint32_t meas1_start_sar:1; + /** meas1_start_force : R/W; bitpos: [18]; default: 0; + * 1: SAR ADC1 controller (in RTC) is started by SW. + */ + uint32_t meas1_start_force:1; + /** sar1_en_pad : R/W; bitpos: [30:19]; default: 0; + * SAR ADC1 pad enable bitmap. + */ + uint32_t sar1_en_pad:12; + /** sar1_en_pad_force : R/W; bitpos: [31]; default: 0; + * 1: SAR ADC1 pad enable bitmap is controlled by SW. + */ + uint32_t sar1_en_pad_force:1; + }; + uint32_t val; +} rtcadc_meas1_ctrl2_reg_t; + +/** Type of meas1_mux register + * SAR ADC1 MUX register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sar1_dig_force : R/W; bitpos: [31]; default: 0; + * 1: SAR ADC1 controlled by DIG ADC1 CTRL. + */ + uint32_t sar1_dig_force:1; + }; + uint32_t val; +} rtcadc_meas1_mux_reg_t; + +/** Type of atten1 register + * ADC1 attenuation registers. + */ +typedef union { + struct { + /** sar1_atten : R/W; bitpos: [31:0]; default: 4294967295; + * 2-bit attenuation for each pad. + */ + uint32_t sar1_atten:32; + }; + uint32_t val; +} rtcadc_atten1_reg_t; + + +/** Group: ADC2 control registers. */ +/** Type of reader2_ctrl register + * Control the read operation of ADC2. + */ +typedef union { + struct { + /** sar2_clk_div : R/W; bitpos: [7:0]; default: 2; + * Clock divider. + */ + uint32_t sar2_clk_div:8; + uint32_t reserved_8:8; + /** sar2_wait_arb_cycle : R/W; bitpos: [17:16]; default: 1; + * Wait arbit stable after sar_done. + */ + uint32_t sar2_wait_arb_cycle:2; + uint32_t reserved_18:9; + /** sar2_en_pad_force_enable : R/W; bitpos: [28:27]; default: 0; + * Force enable adc en_pad to analog circuit 2'b11: force enable . + */ + uint32_t sar2_en_pad_force_enable:2; + /** sar2_data_inv : R/W; bitpos: [29]; default: 0; + * Invert SAR ADC2 data. + */ + uint32_t sar2_data_inv:1; + /** sar2_int_en : R/W; bitpos: [30]; default: 1; + * Enable saradc2 to send out interrupt. + */ + uint32_t sar2_int_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} rtcadc_reader2_ctrl_reg_t; + +/** Type of meas2_ctrl1 register + * ADC2 configuration registers. + */ +typedef union { + struct { + /** sar2_cntl_state : RO; bitpos: [2:0]; default: 0; + * saradc2_cntl_fsm. + */ + uint32_t sar2_cntl_state:3; + /** sar2_pwdet_cal_en : R/W; bitpos: [3]; default: 0; + * RTC control pwdet enable. + */ + uint32_t sar2_pwdet_cal_en:1; + /** sar2_pkdet_cal_en : R/W; bitpos: [4]; default: 0; + * RTC control pkdet enable. + */ + uint32_t sar2_pkdet_cal_en:1; + /** sar2_en_test : R/W; bitpos: [5]; default: 0; + * SAR2_EN_TEST. + */ + uint32_t sar2_en_test:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_meas2_ctrl1_reg_t; + +/** Type of meas2_ctrl2 register + * ADC2 configuration registers. + */ +typedef union { + struct { + /** meas2_data_sar : RO; bitpos: [15:0]; default: 0; + * SAR ADC2 data. + */ + uint32_t meas2_data_sar:16; + /** meas2_done_sar : RO; bitpos: [16]; default: 0; + * SAR ADC2 conversion done indication. + */ + uint32_t meas2_done_sar:1; + /** meas2_start_sar : R/W; bitpos: [17]; default: 0; + * SAR ADC2 controller (in RTC) starts conversion. + */ + uint32_t meas2_start_sar:1; + /** meas2_start_force : R/W; bitpos: [18]; default: 0; + * 1: SAR ADC2 controller (in RTC) is started by SW. + */ + uint32_t meas2_start_force:1; + /** sar2_en_pad : R/W; bitpos: [30:19]; default: 0; + * SAR ADC2 pad enable bitmap. + */ + uint32_t sar2_en_pad:12; + /** sar2_en_pad_force : R/W; bitpos: [31]; default: 0; + * 1: SAR ADC2 pad enable bitmap is controlled by SW. + */ + uint32_t sar2_en_pad_force:1; + }; + uint32_t val; +} rtcadc_meas2_ctrl2_reg_t; + +/** Type of meas2_mux register + * SAR ADC2 MUX register. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** sar2_pwdet_cct : R/W; bitpos: [30:28]; default: 0; + * SAR2_PWDET_CCT. + */ + uint32_t sar2_pwdet_cct:3; + /** sar2_rtc_force : R/W; bitpos: [31]; default: 0; + * In sleep, force to use rtc to control ADC. + */ + uint32_t sar2_rtc_force:1; + }; + uint32_t val; +} rtcadc_meas2_mux_reg_t; + +/** Type of atten2 register + * ADC1 attenuation registers. + */ +typedef union { + struct { + /** sar2_atten : R/W; bitpos: [31:0]; default: 4294967295; + * 2-bit attenuation for each pad. + */ + uint32_t sar2_atten:32; + }; + uint32_t val; +} rtcadc_atten2_reg_t; + + +/** Group: ADC XPD control. */ +/** Type of force_wpd_sar register + * In sleep, force to use rtc to control ADC + */ +typedef union { + struct { + /** force_xpd_sar1 : R/W; bitpos: [1:0]; default: 0; + * 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware + * control. + */ + uint32_t force_xpd_sar1:2; + /** force_xpd_sar2 : R/W; bitpos: [3:2]; default: 0; + * 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware + * control. + */ + uint32_t force_xpd_sar2:2; + uint32_t reserved_4:28; + }; + uint32_t val; +} rtcadc_force_wpd_sar_reg_t; + + +/** Group: RTCADC interrupt registers. */ +/** Type of cocpu_int_raw register + * Interrupt raw registers. + */ +typedef union { + struct { + /** cocpu_saradc1_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int raw. + */ + uint32_t cocpu_saradc1_int_raw:1; + /** cocpu_saradc2_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int raw. + */ + uint32_t cocpu_saradc2_int_raw:1; + /** cocpu_saradc1_error_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * An error occurs from ADC1, int raw. + */ + uint32_t cocpu_saradc1_error_int_raw:1; + /** cocpu_saradc2_error_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * An error occurs from ADC2, int raw. + */ + uint32_t cocpu_saradc2_error_int_raw:1; + /** cocpu_saradc1_wake_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int raw. + */ + uint32_t cocpu_saradc1_wake_int_raw:1; + /** cocpu_saradc2_wake_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int raw. + */ + uint32_t cocpu_saradc2_wake_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_cocpu_int_raw_reg_t; + +/** Type of int_ena register + * Interrupt enable registers. + */ +typedef union { + struct { + /** cocpu_saradc1_int_ena : R/WTC; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int enable. + */ + uint32_t cocpu_saradc1_int_ena:1; + /** cocpu_saradc2_int_ena : R/WTC; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int enable. + */ + uint32_t cocpu_saradc2_int_ena:1; + /** cocpu_saradc1_error_int_ena : R/WTC; bitpos: [2]; default: 0; + * An error occurs from ADC1, int enable. + */ + uint32_t cocpu_saradc1_error_int_ena:1; + /** cocpu_saradc2_error_int_ena : R/WTC; bitpos: [3]; default: 0; + * An error occurs from ADC2, int enable. + */ + uint32_t cocpu_saradc2_error_int_ena:1; + /** cocpu_saradc1_wake_int_ena : R/WTC; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int enable. + */ + uint32_t cocpu_saradc1_wake_int_ena:1; + /** cocpu_saradc2_wake_int_ena : R/WTC; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int enable. + */ + uint32_t cocpu_saradc2_wake_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_int_ena_reg_t; + +/** Type of int_st register + * Interrupt status registers. + */ +typedef union { + struct { + /** cocpu_saradc1_int_st : RO; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int status. + */ + uint32_t cocpu_saradc1_int_st:1; + /** cocpu_saradc2_int_st : RO; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int status. + */ + uint32_t cocpu_saradc2_int_st:1; + /** cocpu_saradc1_error_int_st : RO; bitpos: [2]; default: 0; + * An error occurs from ADC1, int status. + */ + uint32_t cocpu_saradc1_error_int_st:1; + /** cocpu_saradc2_error_int_st : RO; bitpos: [3]; default: 0; + * An error occurs from ADC2, int status. + */ + uint32_t cocpu_saradc2_error_int_st:1; + /** cocpu_saradc1_wake_int_st : RO; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int status. + */ + uint32_t cocpu_saradc1_wake_int_st:1; + /** cocpu_saradc2_wake_int_st : RO; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int status. + */ + uint32_t cocpu_saradc2_wake_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear registers. + */ +typedef union { + struct { + /** cocpu_saradc1_int_clr : WT; bitpos: [0]; default: 0; + * ADC1 Conversion is done, int clear. + */ + uint32_t cocpu_saradc1_int_clr:1; + /** cocpu_saradc2_int_clr : WT; bitpos: [1]; default: 0; + * ADC2 Conversion is done, int clear. + */ + uint32_t cocpu_saradc2_int_clr:1; + /** cocpu_saradc1_error_int_clr : WT; bitpos: [2]; default: 0; + * An error occurs from ADC1, int clear. + */ + uint32_t cocpu_saradc1_error_int_clr:1; + /** cocpu_saradc2_error_int_clr : WT; bitpos: [3]; default: 0; + * An error occurs from ADC2, int clear. + */ + uint32_t cocpu_saradc2_error_int_clr:1; + /** cocpu_saradc1_wake_int_clr : WT; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, int clear. + */ + uint32_t cocpu_saradc1_wake_int_clr:1; + /** cocpu_saradc2_wake_int_clr : WT; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, int clear. + */ + uint32_t cocpu_saradc2_wake_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_int_clr_reg_t; + +/** Type of int_ena_w1ts register + * Interrupt enable assert registers. + */ +typedef union { + struct { + /** cocpu_saradc1_int_ena_w1ts : WT; bitpos: [0]; default: 0; + * ADC1 Conversion is done, write 1 to assert int enable. + */ + uint32_t cocpu_saradc1_int_ena_w1ts:1; + /** cocpu_saradc2_int_ena_w1ts : WT; bitpos: [1]; default: 0; + * ADC2 Conversion is done, write 1 to assert int enable. + */ + uint32_t cocpu_saradc2_int_ena_w1ts:1; + /** cocpu_saradc1_error_int_ena_w1ts : WT; bitpos: [2]; default: 0; + * An error occurs from ADC1, write 1 to assert int enable. + */ + uint32_t cocpu_saradc1_error_int_ena_w1ts:1; + /** cocpu_saradc2_error_int_ena_w1ts : WT; bitpos: [3]; default: 0; + * An error occurs from ADC2, write 1 to assert int enable. + */ + uint32_t cocpu_saradc2_error_int_ena_w1ts:1; + /** cocpu_saradc1_wake_int_ena_w1ts : WT; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, write 1 to assert int enable. + */ + uint32_t cocpu_saradc1_wake_int_ena_w1ts:1; + /** cocpu_saradc2_wake_int_ena_w1ts : WT; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, write 1 to assert int enable. + */ + uint32_t cocpu_saradc2_wake_int_ena_w1ts:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_int_ena_w1ts_reg_t; + +/** Type of int_ena_w1tc register + * Interrupt enable deassert registers. + */ +typedef union { + struct { + /** cocpu_saradc1_int_ena_w1tc : WT; bitpos: [0]; default: 0; + * ADC1 Conversion is done, write 1 to deassert int enable. + */ + uint32_t cocpu_saradc1_int_ena_w1tc:1; + /** cocpu_saradc2_int_ena_w1tc : WT; bitpos: [1]; default: 0; + * ADC2 Conversion is done, write 1 to deassert int enable. + */ + uint32_t cocpu_saradc2_int_ena_w1tc:1; + /** cocpu_saradc1_error_int_ena_w1tc : WT; bitpos: [2]; default: 0; + * An error occurs from ADC1, write 1 to deassert int enable. + */ + uint32_t cocpu_saradc1_error_int_ena_w1tc:1; + /** cocpu_saradc2_error_int_ena_w1tc : WT; bitpos: [3]; default: 0; + * An error occurs from ADC2, write 1 to deassert int enable. + */ + uint32_t cocpu_saradc2_error_int_ena_w1tc:1; + /** cocpu_saradc1_wake_int_ena_w1tc : WT; bitpos: [4]; default: 0; + * A wakeup event is triggered from ADC1, write 1 to deassert int enable. + */ + uint32_t cocpu_saradc1_wake_int_ena_w1tc:1; + /** cocpu_saradc2_wake_int_ena_w1tc : WT; bitpos: [5]; default: 0; + * A wakeup event is triggered from ADC2, write 1 to deassert int enable. + */ + uint32_t cocpu_saradc2_wake_int_ena_w1tc:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} rtcadc_int_ena_w1tc_reg_t; + + +/** Group: RTCADC wakeup control registers. */ +/** Type of wakeup1 register + * ADC1 wakeup configuration registers. + */ +typedef union { + struct { + /** sar1_wakeup_th_low : R/W; bitpos: [11:0]; default: 0; + * Lower threshold. + */ + uint32_t sar1_wakeup_th_low:12; + uint32_t reserved_12:2; + /** sar1_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095; + * Upper threshold. + */ + uint32_t sar1_wakeup_th_high:12; + uint32_t reserved_26:3; + /** sar1_wakeup_over_upper_th : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ + uint32_t sar1_wakeup_over_upper_th:1; + /** sar1_wakeup_en : R/W; bitpos: [30]; default: 0; + * Wakeup function enable. + */ + uint32_t sar1_wakeup_en:1; + /** sar1_wakeup_mode : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ + uint32_t sar1_wakeup_mode:1; + }; + uint32_t val; +} rtcadc_wakeup1_reg_t; + +/** Type of wakeup2 register + * ADC2 wakeup configuration registers. + */ +typedef union { + struct { + /** sar2_wakeup_th_low : R/W; bitpos: [11:0]; default: 0; + * Lower threshold. + */ + uint32_t sar2_wakeup_th_low:12; + uint32_t reserved_12:2; + /** sar2_wakeup_th_high : R/W; bitpos: [25:14]; default: 4095; + * Upper threshold. + */ + uint32_t sar2_wakeup_th_high:12; + uint32_t reserved_26:3; + /** sar2_wakeup_over_upper_th : RO; bitpos: [29]; default: 0; + * Indicates that this wakeup event arose from exceeding upper threshold. + */ + uint32_t sar2_wakeup_over_upper_th:1; + /** sar2_wakeup_en : R/W; bitpos: [30]; default: 0; + * Wakeup function enable. + */ + uint32_t sar2_wakeup_en:1; + /** sar2_wakeup_mode : R/W; bitpos: [31]; default: 0; + * 0:absolute value comparison mode. 1: relative value comparison mode. + */ + uint32_t sar2_wakeup_mode:1; + }; + uint32_t val; +} rtcadc_wakeup2_reg_t; + +/** Type of wakeup_sel register + * Wakeup source select register. + */ +typedef union { + struct { + /** sar_wakeup_sel : R/W; bitpos: [0]; default: 0; + * 0: ADC1. 1: ADC2. + */ + uint32_t sar_wakeup_sel:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} rtcadc_wakeup_sel_reg_t; + +/** Type of sar1_hw_wakeup register + * Hardware automatic sampling registers for wakeup function. + */ +typedef union { + struct { + /** adc1_hw_read_en_i : R/W; bitpos: [0]; default: 0; + * Enable hardware automatic sampling. + */ + uint32_t adc1_hw_read_en_i:1; + /** adc1_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100; + * Hardware automatic sampling rate. + */ + uint32_t adc1_hw_read_rate_i:16; + uint32_t reserved_17:15; + }; + uint32_t val; +} rtcadc_sar1_hw_wakeup_reg_t; + +/** Type of sar2_hw_wakeup register + * Hardware automatic sampling registers for wakeup function. + */ +typedef union { + struct { + /** adc2_hw_read_en_i : R/W; bitpos: [0]; default: 0; + * Enable hardware automatic sampling. + */ + uint32_t adc2_hw_read_en_i:1; + /** adc2_hw_read_rate_i : R/W; bitpos: [16:1]; default: 100; + * Hardware automatic sampling rate. + */ + uint32_t adc2_hw_read_rate_i:16; + uint32_t reserved_17:15; + }; + uint32_t val; +} rtcadc_sar2_hw_wakeup_reg_t; + + +typedef struct { + volatile rtcadc_reader1_ctrl_reg_t reader1_ctrl; + uint32_t reserved_004[2]; + volatile rtcadc_meas1_ctrl2_reg_t meas1_ctrl2; + volatile rtcadc_meas1_mux_reg_t meas1_mux; + volatile rtcadc_atten1_reg_t atten1; + uint32_t reserved_018[3]; + volatile rtcadc_reader2_ctrl_reg_t reader2_ctrl; + uint32_t reserved_028; + volatile rtcadc_meas2_ctrl1_reg_t meas2_ctrl1; + volatile rtcadc_meas2_ctrl2_reg_t meas2_ctrl2; + volatile rtcadc_meas2_mux_reg_t meas2_mux; + volatile rtcadc_atten2_reg_t atten2; + volatile rtcadc_force_wpd_sar_reg_t force_wpd_sar; + uint32_t reserved_040[2]; + volatile rtcadc_cocpu_int_raw_reg_t cocpu_int_raw; + volatile rtcadc_int_ena_reg_t int_ena; + volatile rtcadc_int_st_reg_t int_st; + volatile rtcadc_int_clr_reg_t int_clr; + volatile rtcadc_int_ena_w1ts_reg_t int_ena_w1ts; + volatile rtcadc_int_ena_w1tc_reg_t int_ena_w1tc; + volatile rtcadc_wakeup1_reg_t wakeup1; + volatile rtcadc_wakeup2_reg_t wakeup2; + volatile rtcadc_wakeup_sel_reg_t wakeup_sel; + volatile rtcadc_sar1_hw_wakeup_reg_t sar1_hw_wakeup; + volatile rtcadc_sar2_hw_wakeup_reg_t sar2_hw_wakeup; +} rtcadc_dev_t; + +extern rtcadc_dev_t LP_ADC; + +#ifndef __cplusplus +_Static_assert(sizeof(rtcadc_dev_t) == 0x74, "Invalid size of rtcadc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_reg.h new file mode 100644 index 0000000000..aa2d39a1cf --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_reg.h @@ -0,0 +1,1619 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13424 + +/** LP_ANALOG_PERI_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x0) +/** LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_M (LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_V << LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_M (LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_V << LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_S) +#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_M (LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_V << LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_S) +#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANALOG_PERI_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_M (LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_S) +#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANALOG_PERI_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_M (LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_V << LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANALOG_PERI_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_M (LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_V << LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_S) +#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANALOG_PERI_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_M (LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_V << LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE1_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x4) +/** LP_ANALOG_PERI_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_M (LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_V << LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_VDD_SOURCE_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_VDD_SOURCE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8) +/** LP_ANALOG_PERI_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_ANALOG_PERI_DETMODE_SEL 0x000000FFU +#define LP_ANALOG_PERI_DETMODE_SEL_M (LP_ANALOG_PERI_DETMODE_SEL_V << LP_ANALOG_PERI_DETMODE_SEL_S) +#define LP_ANALOG_PERI_DETMODE_SEL_V 0x000000FFU +#define LP_ANALOG_PERI_DETMODE_SEL_S 0 +/** LP_ANALOG_PERI_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD 0x000000FFU +#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_M (LP_ANALOG_PERI_VGOOD_EVENT_RECORD_V << LP_ANALOG_PERI_VGOOD_EVENT_RECORD_S) +#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_V 0x000000FFU +#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_S 8 +/** LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR 0x000000FFU +#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_M (LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_V << LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_S) +#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_V 0x000000FFU +#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_S 16 +/** LP_ANALOG_PERI_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4; + * need_des + */ +#define LP_ANALOG_PERI_BOD_SOURCE_ENA 0x000000FFU +#define LP_ANALOG_PERI_BOD_SOURCE_ENA_M (LP_ANALOG_PERI_BOD_SOURCE_ENA_V << LP_ANALOG_PERI_BOD_SOURCE_ENA_S) +#define LP_ANALOG_PERI_BOD_SOURCE_ENA_V 0x000000FFU +#define LP_ANALOG_PERI_BOD_SOURCE_ENA_S 24 + +/** LP_ANALOG_PERI_VDDBAT_BOD_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_BOD_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xc) +/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_M (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_S) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANALOG_PERI_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGER (BIT(10)) +#define LP_ANALOG_PERI_VDDBAT_CHARGER_M (LP_ANALOG_PERI_VDDBAT_CHARGER_V << LP_ANALOG_PERI_VDDBAT_CHARGER_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGER_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGER_S 10 +/** LP_ANALOG_PERI_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CNT_CLR (BIT(11)) +#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_M (LP_ANALOG_PERI_VDDBAT_CNT_CLR_V << LP_ANALOG_PERI_VDDBAT_CNT_CLR_S) +#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_S 11 +/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_M (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_S 12 +/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_M (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANALOG_PERI_VDDBAT_CHARGE_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10) +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER (BIT(10)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_M (LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_V << LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_S 10 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR (BIT(11)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_M (LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_S 11 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S 12 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANALOG_PERI_PG_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANALOG_PERI_PG_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18) +/** LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_S) +#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_S 31 + +/** LP_ANALOG_PERI_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANALOG_PERI_FIB_ENABLE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c) +/** LP_ANALOG_PERI_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_ANALOG_PERI_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANALOG_PERI_ANA_FIB_ENA_M (LP_ANALOG_PERI_ANA_FIB_ENA_V << LP_ANALOG_PERI_ANA_FIB_ENA_S) +#define LP_ANALOG_PERI_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANALOG_PERI_ANA_FIB_ENA_S 0 + +#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) + +/** LP_ANALOG_PERI_INT_RAW_REG register + * need_des + */ +#define LP_ANALOG_PERI_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x20) +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW (BIT(27)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S 27 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW (BIT(28)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S 28 +/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW (BIT(29)) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_S 29 +/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW (BIT(30)) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_M (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_S 30 +/** LP_ANALOG_PERI_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_M (LP_ANALOG_PERI_BOD_MODE0_INT_RAW_V << LP_ANALOG_PERI_BOD_MODE0_INT_RAW_S) +#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANALOG_PERI_INT_ST_REG register + * need_des + */ +#define LP_ANALOG_PERI_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x24) +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST (BIT(27)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S 27 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST (BIT(28)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S 28 +/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST (BIT(29)) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_M (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_S 29 +/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST (BIT(30)) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_M (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_S) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_S 30 +/** LP_ANALOG_PERI_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_M (LP_ANALOG_PERI_BOD_MODE0_INT_ST_V << LP_ANALOG_PERI_BOD_MODE0_INT_ST_S) +#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_S 31 + +/** LP_ANALOG_PERI_INT_ENA_REG register + * need_des + */ +#define LP_ANALOG_PERI_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x28) +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA (BIT(27)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S 27 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA (BIT(28)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S 28 +/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA (BIT(29)) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_S 29 +/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA (BIT(30)) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_M (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_S 30 +/** LP_ANALOG_PERI_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_M (LP_ANALOG_PERI_BOD_MODE0_INT_ENA_V << LP_ANALOG_PERI_BOD_MODE0_INT_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANALOG_PERI_INT_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x2c) +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR (BIT(27)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S 27 +/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR (BIT(28)) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S 28 +/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR (BIT(29)) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_S 29 +/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR (BIT(30)) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_M (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_S 30 +/** LP_ANALOG_PERI_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_M (LP_ANALOG_PERI_BOD_MODE0_INT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_INT_CLR_S) +#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANALOG_PERI_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x30) +/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_M (LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANALOG_PERI_LP_INT_ST_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x34) +/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_M (LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_S) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANALOG_PERI_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x38) +/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_M (LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANALOG_PERI_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_LP_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3c) +/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_M (LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANALOG_PERI_TOUCH_APPROACH_WORK_MEAS_NUM_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_WORK_MEAS_NUM_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xfc) +/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_M (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_V 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_S 0 +/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_M (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_V 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_S 10 +/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_M (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_V 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_S 20 + +/** LP_ANALOG_PERI_TOUCH_SCAN_CTRL1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SCAN_CTRL1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x100) +/** LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN (BIT(0)) +#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_M (LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_V << LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_S) +#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_S 0 +/** LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION (BIT(1)) +#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_M (LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_V << LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_S) +#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_S 1 +/** LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [16:2]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_M (LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_V << LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_S) +#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_S 2 +/** LP_ANALOG_PERI_TOUCH_XPD_WAIT : R/W; bitpos: [31:17]; default: 4; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_XPD_WAIT 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_M (LP_ANALOG_PERI_TOUCH_XPD_WAIT_V << LP_ANALOG_PERI_TOUCH_XPD_WAIT_S) +#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_S 17 + +/** LP_ANALOG_PERI_TOUCH_SCAN_CTRL2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SCAN_CTRL2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x104) +/** LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:6]; default: 65535; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_M (LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_V << LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_S) +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_S 6 +/** LP_ANALOG_PERI_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN (BIT(22)) +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_M (LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_V << LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_S) +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_S 22 +/** LP_ANALOG_PERI_TOUCH_OUT_RING : R/W; bitpos: [26:23]; default: 15; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_OUT_RING 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_OUT_RING_M (LP_ANALOG_PERI_TOUCH_OUT_RING_V << LP_ANALOG_PERI_TOUCH_OUT_RING_S) +#define LP_ANALOG_PERI_TOUCH_OUT_RING_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_OUT_RING_S 23 +/** LP_ANALOG_PERI_FREQ_SCAN_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_FREQ_SCAN_EN (BIT(27)) +#define LP_ANALOG_PERI_FREQ_SCAN_EN_M (LP_ANALOG_PERI_FREQ_SCAN_EN_V << LP_ANALOG_PERI_FREQ_SCAN_EN_S) +#define LP_ANALOG_PERI_FREQ_SCAN_EN_V 0x00000001U +#define LP_ANALOG_PERI_FREQ_SCAN_EN_S 27 +/** LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT : R/W; bitpos: [29:28]; default: 3; + * need_des + */ +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT 0x00000003U +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_M (LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_V << LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_S) +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_V 0x00000003U +#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_S 28 + +/** LP_ANALOG_PERI_TOUCH_WORK_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_WORK_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x108) +/** LP_ANALOG_PERI_DIV_NUM2 : R/W; bitpos: [18:16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_DIV_NUM2 0x00000007U +#define LP_ANALOG_PERI_DIV_NUM2_M (LP_ANALOG_PERI_DIV_NUM2_V << LP_ANALOG_PERI_DIV_NUM2_S) +#define LP_ANALOG_PERI_DIV_NUM2_V 0x00000007U +#define LP_ANALOG_PERI_DIV_NUM2_S 16 +/** LP_ANALOG_PERI_DIV_NUM1 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_DIV_NUM1 0x00000007U +#define LP_ANALOG_PERI_DIV_NUM1_M (LP_ANALOG_PERI_DIV_NUM1_V << LP_ANALOG_PERI_DIV_NUM1_S) +#define LP_ANALOG_PERI_DIV_NUM1_V 0x00000007U +#define LP_ANALOG_PERI_DIV_NUM1_S 19 +/** LP_ANALOG_PERI_DIV_NUM0 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_DIV_NUM0 0x00000007U +#define LP_ANALOG_PERI_DIV_NUM0_M (LP_ANALOG_PERI_DIV_NUM0_V << LP_ANALOG_PERI_DIV_NUM0_S) +#define LP_ANALOG_PERI_DIV_NUM0_V 0x00000007U +#define LP_ANALOG_PERI_DIV_NUM0_S 22 +/** LP_ANALOG_PERI_TOUCH_OUT_SEL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_OUT_SEL (BIT(25)) +#define LP_ANALOG_PERI_TOUCH_OUT_SEL_M (LP_ANALOG_PERI_TOUCH_OUT_SEL_V << LP_ANALOG_PERI_TOUCH_OUT_SEL_S) +#define LP_ANALOG_PERI_TOUCH_OUT_SEL_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_OUT_SEL_S 25 +/** LP_ANALOG_PERI_TOUCH_OUT_RESET : WT; bitpos: [26]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_OUT_RESET (BIT(26)) +#define LP_ANALOG_PERI_TOUCH_OUT_RESET_M (LP_ANALOG_PERI_TOUCH_OUT_RESET_V << LP_ANALOG_PERI_TOUCH_OUT_RESET_S) +#define LP_ANALOG_PERI_TOUCH_OUT_RESET_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_OUT_RESET_S 26 +/** LP_ANALOG_PERI_TOUCH_OUT_GATE : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_OUT_GATE (BIT(27)) +#define LP_ANALOG_PERI_TOUCH_OUT_GATE_M (LP_ANALOG_PERI_TOUCH_OUT_GATE_V << LP_ANALOG_PERI_TOUCH_OUT_GATE_S) +#define LP_ANALOG_PERI_TOUCH_OUT_GATE_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_OUT_GATE_S 27 + +/** LP_ANALOG_PERI_TOUCH_WORK_MEAS_NUM_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_WORK_MEAS_NUM_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10c) +/** LP_ANALOG_PERI_TOUCH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_M (LP_ANALOG_PERI_TOUCH_MEAS_NUM2_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM2_S) +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_V 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_S 0 +/** LP_ANALOG_PERI_TOUCH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_M (LP_ANALOG_PERI_TOUCH_MEAS_NUM1_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM1_S) +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_V 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_S 10 +/** LP_ANALOG_PERI_TOUCH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_M (LP_ANALOG_PERI_TOUCH_MEAS_NUM0_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM0_S) +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_V 0x000003FFU +#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_S 20 + +/** LP_ANALOG_PERI_TOUCH_FILTER1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FILTER1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x110) +/** LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN (BIT(0)) +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_M (LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_V << LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_S) +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_NN_DISUPDATE_BENCHMARK_EN_S 0 +/** LP_ANALOG_PERI_TOUCH_HYSTERESIS : R/W; bitpos: [2:1]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_HYSTERESIS 0x00000003U +#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_M (LP_ANALOG_PERI_TOUCH_HYSTERESIS_V << LP_ANALOG_PERI_TOUCH_HYSTERESIS_S) +#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_S 1 +/** LP_ANALOG_PERI_TOUCH_NN_THRES : R/W; bitpos: [4:3]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_NN_THRES 0x00000003U +#define LP_ANALOG_PERI_TOUCH_NN_THRES_M (LP_ANALOG_PERI_TOUCH_NN_THRES_V << LP_ANALOG_PERI_TOUCH_NN_THRES_S) +#define LP_ANALOG_PERI_TOUCH_NN_THRES_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_NN_THRES_S 3 +/** LP_ANALOG_PERI_TOUCH_NOISE_THRES : R/W; bitpos: [6:5]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_NOISE_THRES 0x00000003U +#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_M (LP_ANALOG_PERI_TOUCH_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_NOISE_THRES_S) +#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_S 5 +/** LP_ANALOG_PERI_TOUCH_SMOOTH_LVL : R/W; bitpos: [8:7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL 0x00000003U +#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_M (LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_V << LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_S) +#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_S 7 +/** LP_ANALOG_PERI_TOUCH_JITTER_STEP : R/W; bitpos: [12:9]; default: 1; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_JITTER_STEP 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_M (LP_ANALOG_PERI_TOUCH_JITTER_STEP_V << LP_ANALOG_PERI_TOUCH_JITTER_STEP_S) +#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_S 9 +/** LP_ANALOG_PERI_TOUCH_FILTER_MODE : R/W; bitpos: [15:13]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FILTER_MODE 0x00000007U +#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_M (LP_ANALOG_PERI_TOUCH_FILTER_MODE_V << LP_ANALOG_PERI_TOUCH_FILTER_MODE_S) +#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_V 0x00000007U +#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_S 13 +/** LP_ANALOG_PERI_TOUCH_FILTER_EN : R/W; bitpos: [16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FILTER_EN (BIT(16)) +#define LP_ANALOG_PERI_TOUCH_FILTER_EN_M (LP_ANALOG_PERI_TOUCH_FILTER_EN_V << LP_ANALOG_PERI_TOUCH_FILTER_EN_S) +#define LP_ANALOG_PERI_TOUCH_FILTER_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_FILTER_EN_S 16 +/** LP_ANALOG_PERI_TOUCH_NN_LIMIT : R/W; bitpos: [20:17]; default: 5; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_M (LP_ANALOG_PERI_TOUCH_NN_LIMIT_V << LP_ANALOG_PERI_TOUCH_NN_LIMIT_S) +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_NN_LIMIT_S 17 +/** LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT : R/W; bitpos: [28:21]; default: 80; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT 0x000000FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_M (LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_V << LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_V 0x000000FFU +#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_S 21 +/** LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT 0x00000007U +#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_M (LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_V << LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_S) +#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_V 0x00000007U +#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_S 29 + +/** LP_ANALOG_PERI_TOUCH_FILTER2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FILTER2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x114) +/** LP_ANALOG_PERI_TOUCH_OUTEN : R/W; bitpos: [29:15]; default: 16383; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_OUTEN 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_OUTEN_M (LP_ANALOG_PERI_TOUCH_OUTEN_V << LP_ANALOG_PERI_TOUCH_OUTEN_S) +#define LP_ANALOG_PERI_TOUCH_OUTEN_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_OUTEN_S 15 +/** LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES (BIT(30)) +#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_M (LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S) +#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S 30 +/** LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES (BIT(31)) +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_M (LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_S) +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_BYPASS_NN_THRES_S 31 + +/** LP_ANALOG_PERI_TOUCH_FILTER3_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FILTER3_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x118) +/** LP_ANALOG_PERI_TOUCH_BENCHMARK_SW : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_M (LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_V << LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_S) +#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_BENCHMARK_SW_S 0 +/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW : WT; bitpos: [16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW (BIT(16)) +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_M (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_S) +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_SW_S 16 + +/** LP_ANALOG_PERI_TOUCH_SLP0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x11c) +/** LP_ANALOG_PERI_TOUCH_SLP_TH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_SLP_TH0_M (LP_ANALOG_PERI_TOUCH_SLP_TH0_V << LP_ANALOG_PERI_TOUCH_SLP_TH0_S) +#define LP_ANALOG_PERI_TOUCH_SLP_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_SLP_TH0_S 0 +/** LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR : WT; bitpos: [16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR (BIT(16)) +#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_M (LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_V << LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_S) +#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_S 16 +/** LP_ANALOG_PERI_TOUCH_SLP_PAD : R/W; bitpos: [20:17]; default: 15; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP_PAD 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_SLP_PAD_M (LP_ANALOG_PERI_TOUCH_SLP_PAD_V << LP_ANALOG_PERI_TOUCH_SLP_PAD_S) +#define LP_ANALOG_PERI_TOUCH_SLP_PAD_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_SLP_PAD_S 17 + +/** LP_ANALOG_PERI_TOUCH_SLP1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x120) +/** LP_ANALOG_PERI_TOUCH_SLP_TH2 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_SLP_TH2_M (LP_ANALOG_PERI_TOUCH_SLP_TH2_V << LP_ANALOG_PERI_TOUCH_SLP_TH2_S) +#define LP_ANALOG_PERI_TOUCH_SLP_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_SLP_TH2_S 0 +/** LP_ANALOG_PERI_TOUCH_SLP_TH1 : R/W; bitpos: [31:16]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_SLP_TH1_M (LP_ANALOG_PERI_TOUCH_SLP_TH1_V << LP_ANALOG_PERI_TOUCH_SLP_TH1_S) +#define LP_ANALOG_PERI_TOUCH_SLP_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_SLP_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_CLR_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x124) +/** LP_ANALOG_PERI_TOUCH_CHANNEL_CLR : WT; bitpos: [14:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_M (LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_V << LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_S) +#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_S 0 +/** LP_ANALOG_PERI_TOUCH_STATUS_CLR : WT; bitpos: [15]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_STATUS_CLR (BIT(15)) +#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_M (LP_ANALOG_PERI_TOUCH_STATUS_CLR_V << LP_ANALOG_PERI_TOUCH_STATUS_CLR_S) +#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_S 15 + +/** LP_ANALOG_PERI_TOUCH_APPROACH_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x128) +/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD0 : R/W; bitpos: [3:0]; default: 15; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_M (LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_S 0 +/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD1 : R/W; bitpos: [7:4]; default: 15; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_M (LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_S 4 +/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD2 : R/W; bitpos: [11:8]; default: 15; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_M (LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_S) +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_S 8 +/** LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN (BIT(12)) +#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_M (LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_V << LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_S) +#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_S 12 + +/** LP_ANALOG_PERI_TOUCH_FREQ0_SCAN_PARA_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ0_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x12c) +/** LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF : R/W; bitpos: [6:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_M (LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_S) +#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_V 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_S 0 +/** LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF : R/W; bitpos: [8:7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_M (LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_S) +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_S 7 +/** LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS : R/W; bitpos: [12:9]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_M (LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_S 9 +/** LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS : R/W; bitpos: [17:13]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_M (LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_V 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_S 13 +/** LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS : R/W; bitpos: [22:18]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_M (LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_V 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_S 18 + +/** LP_ANALOG_PERI_TOUCH_FREQ1_SCAN_PARA_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ1_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x130) +/** LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF : R/W; bitpos: [6:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_M (LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_S) +#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_V 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_S 0 +/** LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF : R/W; bitpos: [8:7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_M (LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_S) +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_S 7 +/** LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS : R/W; bitpos: [12:9]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_M (LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_S 9 +/** LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS : R/W; bitpos: [17:13]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_M (LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_V 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_S 13 +/** LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS : R/W; bitpos: [22:18]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_M (LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_V 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_S 18 + +/** LP_ANALOG_PERI_TOUCH_FREQ2_SCAN_PARA_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ2_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x134) +/** LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF : R/W; bitpos: [6:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_M (LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_S) +#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_V 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_S 0 +/** LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF : R/W; bitpos: [8:7]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_M (LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_S) +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_S 7 +/** LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS : R/W; bitpos: [12:9]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_M (LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_V 0x0000000FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_S 9 +/** LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS : R/W; bitpos: [17:13]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_M (LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_V 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_S 13 +/** LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS : R/W; bitpos: [22:18]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_M (LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_S) +#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_V 0x0000001FU +#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_S 18 + +/** LP_ANALOG_PERI_TOUCH_ANA_PARA_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_ANA_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x138) +/** LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV : R/W; bitpos: [2:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV 0x00000007U +#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_M (LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_V << LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_S) +#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_V 0x00000007U +#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_S 0 +/** LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL (BIT(3)) +#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_M (LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_V << LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_S) +#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_S 3 +/** LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL : R/W; bitpos: [10:4]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_M (LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_V << LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_S) +#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_V 0x0000007FU +#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_S 4 + +/** LP_ANALOG_PERI_TOUCH_MUX0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_MUX0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x13c) +/** LP_ANALOG_PERI_TOUCH_DATA_SEL : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_DATA_SEL 0x00000003U +#define LP_ANALOG_PERI_TOUCH_DATA_SEL_M (LP_ANALOG_PERI_TOUCH_DATA_SEL_V << LP_ANALOG_PERI_TOUCH_DATA_SEL_S) +#define LP_ANALOG_PERI_TOUCH_DATA_SEL_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_DATA_SEL_S 8 +/** LP_ANALOG_PERI_TOUCH_FREQ_SEL : R/W; bitpos: [11:10]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FREQ_SEL 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_M (LP_ANALOG_PERI_TOUCH_FREQ_SEL_V << LP_ANALOG_PERI_TOUCH_FREQ_SEL_S) +#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_V 0x00000003U +#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_S 10 +/** LP_ANALOG_PERI_TOUCH_BUFSEL : R/W; bitpos: [26:12]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_BUFSEL 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_BUFSEL_M (LP_ANALOG_PERI_TOUCH_BUFSEL_V << LP_ANALOG_PERI_TOUCH_BUFSEL_S) +#define LP_ANALOG_PERI_TOUCH_BUFSEL_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_BUFSEL_S 12 +/** LP_ANALOG_PERI_TOUCH_DONE_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_DONE_EN (BIT(27)) +#define LP_ANALOG_PERI_TOUCH_DONE_EN_M (LP_ANALOG_PERI_TOUCH_DONE_EN_V << LP_ANALOG_PERI_TOUCH_DONE_EN_S) +#define LP_ANALOG_PERI_TOUCH_DONE_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_DONE_EN_S 27 +/** LP_ANALOG_PERI_TOUCH_DONE_FORCE : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_DONE_FORCE (BIT(28)) +#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_M (LP_ANALOG_PERI_TOUCH_DONE_FORCE_V << LP_ANALOG_PERI_TOUCH_DONE_FORCE_S) +#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_S 28 +/** LP_ANALOG_PERI_TOUCH_FSM_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_FSM_EN (BIT(29)) +#define LP_ANALOG_PERI_TOUCH_FSM_EN_M (LP_ANALOG_PERI_TOUCH_FSM_EN_V << LP_ANALOG_PERI_TOUCH_FSM_EN_S) +#define LP_ANALOG_PERI_TOUCH_FSM_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_FSM_EN_S 29 +/** LP_ANALOG_PERI_TOUCH_START_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_START_EN (BIT(30)) +#define LP_ANALOG_PERI_TOUCH_START_EN_M (LP_ANALOG_PERI_TOUCH_START_EN_V << LP_ANALOG_PERI_TOUCH_START_EN_S) +#define LP_ANALOG_PERI_TOUCH_START_EN_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_START_EN_S 30 +/** LP_ANALOG_PERI_TOUCH_START_FORCE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_START_FORCE (BIT(31)) +#define LP_ANALOG_PERI_TOUCH_START_FORCE_M (LP_ANALOG_PERI_TOUCH_START_FORCE_V << LP_ANALOG_PERI_TOUCH_START_FORCE_S) +#define LP_ANALOG_PERI_TOUCH_START_FORCE_V 0x00000001U +#define LP_ANALOG_PERI_TOUCH_START_FORCE_S 31 + +/** LP_ANALOG_PERI_TOUCH_MUX1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_MUX1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x140) +/** LP_ANALOG_PERI_TOUCH_START : R/W; bitpos: [14:0]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_START 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_START_M (LP_ANALOG_PERI_TOUCH_START_V << LP_ANALOG_PERI_TOUCH_START_S) +#define LP_ANALOG_PERI_TOUCH_START_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_START_S 0 +/** LP_ANALOG_PERI_TOUCH_XPD : R/W; bitpos: [29:15]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_XPD 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_XPD_M (LP_ANALOG_PERI_TOUCH_XPD_V << LP_ANALOG_PERI_TOUCH_XPD_S) +#define LP_ANALOG_PERI_TOUCH_XPD_V 0x00007FFFU +#define LP_ANALOG_PERI_TOUCH_XPD_S 15 + +/** LP_ANALOG_PERI_TOUCH_PAD0_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x144) +/** LP_ANALOG_PERI_TOUCH_PAD0_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD0_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_M (LP_ANALOG_PERI_TOUCH_PAD0_TH0_V << LP_ANALOG_PERI_TOUCH_PAD0_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD0_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x148) +/** LP_ANALOG_PERI_TOUCH_PAD0_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD0_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_M (LP_ANALOG_PERI_TOUCH_PAD0_TH1_V << LP_ANALOG_PERI_TOUCH_PAD0_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD0_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14c) +/** LP_ANALOG_PERI_TOUCH_PAD0_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD0_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_M (LP_ANALOG_PERI_TOUCH_PAD0_TH2_V << LP_ANALOG_PERI_TOUCH_PAD0_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD1_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x150) +/** LP_ANALOG_PERI_TOUCH_PAD1_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD1_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_M (LP_ANALOG_PERI_TOUCH_PAD1_TH0_V << LP_ANALOG_PERI_TOUCH_PAD1_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD1_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x154) +/** LP_ANALOG_PERI_TOUCH_PAD1_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD1_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_M (LP_ANALOG_PERI_TOUCH_PAD1_TH1_V << LP_ANALOG_PERI_TOUCH_PAD1_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD1_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x158) +/** LP_ANALOG_PERI_TOUCH_PAD1_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD1_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_M (LP_ANALOG_PERI_TOUCH_PAD1_TH2_V << LP_ANALOG_PERI_TOUCH_PAD1_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD2_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x15c) +/** LP_ANALOG_PERI_TOUCH_PAD2_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD2_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_M (LP_ANALOG_PERI_TOUCH_PAD2_TH0_V << LP_ANALOG_PERI_TOUCH_PAD2_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD2_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x160) +/** LP_ANALOG_PERI_TOUCH_PAD2_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD2_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_M (LP_ANALOG_PERI_TOUCH_PAD2_TH1_V << LP_ANALOG_PERI_TOUCH_PAD2_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD2_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x164) +/** LP_ANALOG_PERI_TOUCH_PAD2_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD2_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_M (LP_ANALOG_PERI_TOUCH_PAD2_TH2_V << LP_ANALOG_PERI_TOUCH_PAD2_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD3_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x168) +/** LP_ANALOG_PERI_TOUCH_PAD3_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD3_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_M (LP_ANALOG_PERI_TOUCH_PAD3_TH0_V << LP_ANALOG_PERI_TOUCH_PAD3_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD3_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x16c) +/** LP_ANALOG_PERI_TOUCH_PAD3_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD3_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_M (LP_ANALOG_PERI_TOUCH_PAD3_TH1_V << LP_ANALOG_PERI_TOUCH_PAD3_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD3_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x170) +/** LP_ANALOG_PERI_TOUCH_PAD3_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD3_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_M (LP_ANALOG_PERI_TOUCH_PAD3_TH2_V << LP_ANALOG_PERI_TOUCH_PAD3_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD4_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x174) +/** LP_ANALOG_PERI_TOUCH_PAD4_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD4_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_M (LP_ANALOG_PERI_TOUCH_PAD4_TH0_V << LP_ANALOG_PERI_TOUCH_PAD4_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD4_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x178) +/** LP_ANALOG_PERI_TOUCH_PAD4_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD4_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_M (LP_ANALOG_PERI_TOUCH_PAD4_TH1_V << LP_ANALOG_PERI_TOUCH_PAD4_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD4_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x17c) +/** LP_ANALOG_PERI_TOUCH_PAD4_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD4_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_M (LP_ANALOG_PERI_TOUCH_PAD4_TH2_V << LP_ANALOG_PERI_TOUCH_PAD4_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD5_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x180) +/** LP_ANALOG_PERI_TOUCH_PAD5_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD5_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_M (LP_ANALOG_PERI_TOUCH_PAD5_TH0_V << LP_ANALOG_PERI_TOUCH_PAD5_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD5_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x184) +/** LP_ANALOG_PERI_TOUCH_PAD5_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD5_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_M (LP_ANALOG_PERI_TOUCH_PAD5_TH1_V << LP_ANALOG_PERI_TOUCH_PAD5_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD5_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x188) +/** LP_ANALOG_PERI_TOUCH_PAD5_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD5_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_M (LP_ANALOG_PERI_TOUCH_PAD5_TH2_V << LP_ANALOG_PERI_TOUCH_PAD5_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD6_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18c) +/** LP_ANALOG_PERI_TOUCH_PAD6_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD6_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_M (LP_ANALOG_PERI_TOUCH_PAD6_TH0_V << LP_ANALOG_PERI_TOUCH_PAD6_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD6_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x190) +/** LP_ANALOG_PERI_TOUCH_PAD6_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD6_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_M (LP_ANALOG_PERI_TOUCH_PAD6_TH1_V << LP_ANALOG_PERI_TOUCH_PAD6_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD6_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x194) +/** LP_ANALOG_PERI_TOUCH_PAD6_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD6_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_M (LP_ANALOG_PERI_TOUCH_PAD6_TH2_V << LP_ANALOG_PERI_TOUCH_PAD6_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD7_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x198) +/** LP_ANALOG_PERI_TOUCH_PAD7_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD7_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_M (LP_ANALOG_PERI_TOUCH_PAD7_TH0_V << LP_ANALOG_PERI_TOUCH_PAD7_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD7_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x19c) +/** LP_ANALOG_PERI_TOUCH_PAD7_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD7_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_M (LP_ANALOG_PERI_TOUCH_PAD7_TH1_V << LP_ANALOG_PERI_TOUCH_PAD7_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD7_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a0) +/** LP_ANALOG_PERI_TOUCH_PAD7_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD7_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_M (LP_ANALOG_PERI_TOUCH_PAD7_TH2_V << LP_ANALOG_PERI_TOUCH_PAD7_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD8_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a4) +/** LP_ANALOG_PERI_TOUCH_PAD8_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD8_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_M (LP_ANALOG_PERI_TOUCH_PAD8_TH0_V << LP_ANALOG_PERI_TOUCH_PAD8_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD8_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a8) +/** LP_ANALOG_PERI_TOUCH_PAD8_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD8_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_M (LP_ANALOG_PERI_TOUCH_PAD8_TH1_V << LP_ANALOG_PERI_TOUCH_PAD8_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD8_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1ac) +/** LP_ANALOG_PERI_TOUCH_PAD8_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD8_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_M (LP_ANALOG_PERI_TOUCH_PAD8_TH2_V << LP_ANALOG_PERI_TOUCH_PAD8_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD9_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b0) +/** LP_ANALOG_PERI_TOUCH_PAD9_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD9_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_M (LP_ANALOG_PERI_TOUCH_PAD9_TH0_V << LP_ANALOG_PERI_TOUCH_PAD9_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD9_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b4) +/** LP_ANALOG_PERI_TOUCH_PAD9_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD9_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_M (LP_ANALOG_PERI_TOUCH_PAD9_TH1_V << LP_ANALOG_PERI_TOUCH_PAD9_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD9_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b8) +/** LP_ANALOG_PERI_TOUCH_PAD9_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD9_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_M (LP_ANALOG_PERI_TOUCH_PAD9_TH2_V << LP_ANALOG_PERI_TOUCH_PAD9_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD10_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1bc) +/** LP_ANALOG_PERI_TOUCH_PAD10_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD10_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_M (LP_ANALOG_PERI_TOUCH_PAD10_TH0_V << LP_ANALOG_PERI_TOUCH_PAD10_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD10_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c0) +/** LP_ANALOG_PERI_TOUCH_PAD10_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD10_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_M (LP_ANALOG_PERI_TOUCH_PAD10_TH1_V << LP_ANALOG_PERI_TOUCH_PAD10_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD10_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c4) +/** LP_ANALOG_PERI_TOUCH_PAD10_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD10_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_M (LP_ANALOG_PERI_TOUCH_PAD10_TH2_V << LP_ANALOG_PERI_TOUCH_PAD10_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD11_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c8) +/** LP_ANALOG_PERI_TOUCH_PAD11_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD11_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_M (LP_ANALOG_PERI_TOUCH_PAD11_TH0_V << LP_ANALOG_PERI_TOUCH_PAD11_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD11_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1cc) +/** LP_ANALOG_PERI_TOUCH_PAD11_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD11_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_M (LP_ANALOG_PERI_TOUCH_PAD11_TH1_V << LP_ANALOG_PERI_TOUCH_PAD11_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD11_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d0) +/** LP_ANALOG_PERI_TOUCH_PAD11_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD11_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_M (LP_ANALOG_PERI_TOUCH_PAD11_TH2_V << LP_ANALOG_PERI_TOUCH_PAD11_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD12_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d4) +/** LP_ANALOG_PERI_TOUCH_PAD12_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD12_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_M (LP_ANALOG_PERI_TOUCH_PAD12_TH0_V << LP_ANALOG_PERI_TOUCH_PAD12_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD12_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d8) +/** LP_ANALOG_PERI_TOUCH_PAD12_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD12_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_M (LP_ANALOG_PERI_TOUCH_PAD12_TH1_V << LP_ANALOG_PERI_TOUCH_PAD12_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD12_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1dc) +/** LP_ANALOG_PERI_TOUCH_PAD12_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD12_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_M (LP_ANALOG_PERI_TOUCH_PAD12_TH2_V << LP_ANALOG_PERI_TOUCH_PAD12_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD13_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e0) +/** LP_ANALOG_PERI_TOUCH_PAD13_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD13_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_M (LP_ANALOG_PERI_TOUCH_PAD13_TH0_V << LP_ANALOG_PERI_TOUCH_PAD13_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD13_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e4) +/** LP_ANALOG_PERI_TOUCH_PAD13_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD13_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_M (LP_ANALOG_PERI_TOUCH_PAD13_TH1_V << LP_ANALOG_PERI_TOUCH_PAD13_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD13_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e8) +/** LP_ANALOG_PERI_TOUCH_PAD13_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD13_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_M (LP_ANALOG_PERI_TOUCH_PAD13_TH2_V << LP_ANALOG_PERI_TOUCH_PAD13_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD14_TH0_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1ec) +/** LP_ANALOG_PERI_TOUCH_PAD14_TH0 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD14_TH0 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_M (LP_ANALOG_PERI_TOUCH_PAD14_TH0_V << LP_ANALOG_PERI_TOUCH_PAD14_TH0_S) +#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD14_TH1_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1f0) +/** LP_ANALOG_PERI_TOUCH_PAD14_TH1 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD14_TH1 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_M (LP_ANALOG_PERI_TOUCH_PAD14_TH1_V << LP_ANALOG_PERI_TOUCH_PAD14_TH1_S) +#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_S 16 + +/** LP_ANALOG_PERI_TOUCH_PAD14_TH2_REG register + * need_des + */ +#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1f4) +/** LP_ANALOG_PERI_TOUCH_PAD14_TH2 : R/W; bitpos: [31:16]; default: 0; + * Reserved + */ +#define LP_ANALOG_PERI_TOUCH_PAD14_TH2 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_M (LP_ANALOG_PERI_TOUCH_PAD14_TH2_V << LP_ANALOG_PERI_TOUCH_PAD14_TH2_S) +#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_V 0x0000FFFFU +#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_S 16 + +/** LP_ANALOG_PERI_DATE_REG register + * need_des + */ +#define LP_ANALOG_PERI_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc) +/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2294816; + * need_des + */ +#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE 0x7FFFFFFFU +#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_M (LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_V << LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_S) +#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_V 0x7FFFFFFFU +#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_S 0 +/** LP_ANALOG_PERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANALOG_PERI_CLK_EN (BIT(31)) +#define LP_ANALOG_PERI_CLK_EN_M (LP_ANALOG_PERI_CLK_EN_V << LP_ANALOG_PERI_CLK_EN_S) +#define LP_ANALOG_PERI_CLK_EN_V 0x00000001U +#define LP_ANALOG_PERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_struct.h new file mode 100644 index 0000000000..919afa0f27 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_analog_peri_struct.h @@ -0,0 +1,885 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-13424 + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_analog_peri_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_analog_peri_bod_mode1_cntl_reg_t; + +/** Type of vdd_source_cntl register + * need_des + */ +typedef union { + struct { + /** detmode_sel : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t detmode_sel:8; + /** vgood_event_record : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t vgood_event_record:8; + /** vbat_event_record_clr : WT; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t vbat_event_record_clr:8; + /** bod_source_ena : R/W; bitpos: [31:24]; default: 4; + * need_des + */ + uint32_t bod_source_ena:8; + }; + uint32_t val; +} lp_analog_peri_vdd_source_cntl_reg_t; + +/** Type of vddbat_bod_cntl register + * need_des + */ +typedef union { + struct { + /** vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_flag:1; + uint32_t reserved_1:9; + /** vddbat_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t vddbat_charger:1; + /** vddbat_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t vddbat_cnt_clr:1; + /** vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_target:10; + /** vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t vddbat_undervoltage_target:10; + }; + uint32_t val; +} lp_analog_peri_vddbat_bod_cntl_reg_t; + +/** Type of vddbat_charge_cntl register + * need_des + */ +typedef union { + struct { + /** vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_flag:1; + uint32_t reserved_1:9; + /** vddbat_charge_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t vddbat_charge_charger:1; + /** vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t vddbat_charge_cnt_clr:1; + /** vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_target:10; + /** vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t vddbat_charge_undervoltage_target:10; + }; + uint32_t val; +} lp_analog_peri_vddbat_charge_cntl_reg_t; + +/** Type of pg_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** power_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t power_glitch_reset_ena:1; + }; + uint32_t val; +} lp_analog_peri_pg_glitch_cntl_reg_t; + +/** Type of fib_enable register + * need_des + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_analog_peri_fib_enable_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_raw:1; + /** vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_raw:1; + /** vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_raw:1; + /** vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_raw:1; + /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_analog_peri_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_st:1; + /** vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_st:1; + /** vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_st:1; + /** vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_st:1; + /** bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_st:1; + }; + uint32_t val; +} lp_analog_peri_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_ena:1; + /** vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_ena:1; + /** vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_ena:1; + /** vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_ena:1; + /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_analog_peri_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t vddbat_charge_upvoltage_int_clr:1; + /** vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t vddbat_charge_undervoltage_int_clr:1; + /** vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t vddbat_upvoltage_int_clr:1; + /** vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t vddbat_undervoltage_int_clr:1; + /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_analog_peri_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_analog_peri_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_analog_peri_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_analog_peri_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_analog_peri_lp_int_clr_reg_t; + +/** Type of touch_approach_work_meas_num register + * need_des + */ +typedef union { + struct { + /** touch_approach_meas_num2 : R/W; bitpos: [9:0]; default: 100; + * need_des + */ + uint32_t touch_approach_meas_num2:10; + /** touch_approach_meas_num1 : R/W; bitpos: [19:10]; default: 100; + * need_des + */ + uint32_t touch_approach_meas_num1:10; + /** touch_approach_meas_num0 : R/W; bitpos: [29:20]; default: 100; + * need_des + */ + uint32_t touch_approach_meas_num0:10; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_analog_peri_touch_approach_work_meas_num_reg_t; + +/** Type of touch_scan_ctrl1 register + * need_des + */ +typedef union { + struct { + /** touch_shield_pad_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t touch_shield_pad_en:1; + /** touch_inactive_connection : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t touch_inactive_connection:1; + /** touch_scan_pad_map : R/W; bitpos: [16:2]; default: 0; + * need_des + */ + uint32_t touch_scan_pad_map:15; + /** touch_xpd_wait : R/W; bitpos: [31:17]; default: 4; + * need_des + */ + uint32_t touch_xpd_wait:15; + }; + uint32_t val; +} lp_analog_peri_touch_scan_ctrl1_reg_t; + +/** Type of touch_scan_ctrl2 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** touch_timeout_num : R/W; bitpos: [21:6]; default: 65535; + * need_des + */ + uint32_t touch_timeout_num:16; + /** touch_timeout_en : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t touch_timeout_en:1; + /** touch_out_ring : R/W; bitpos: [26:23]; default: 15; + * need_des + */ + uint32_t touch_out_ring:4; + /** freq_scan_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t freq_scan_en:1; + /** freq_scan_cnt_limit : R/W; bitpos: [29:28]; default: 3; + * need_des + */ + uint32_t freq_scan_cnt_limit:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_analog_peri_touch_scan_ctrl2_reg_t; + +/** Type of touch_work register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** div_num2 : R/W; bitpos: [18:16]; default: 0; + * need_des + */ + uint32_t div_num2:3; + /** div_num1 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t div_num1:3; + /** div_num0 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t div_num0:3; + /** touch_out_sel : R/W; bitpos: [25]; default: 0; + * 0: Select the output of the touch as data + * 1: Select the output of the touch as clock + */ + uint32_t touch_out_sel:1; + /** touch_out_reset : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t touch_out_reset:1; + /** touch_out_gate : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t touch_out_gate:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_analog_peri_touch_work_reg_t; + +/** Type of touch_work_meas_num register + * need_des + */ +typedef union { + struct { + /** touch_meas_num2 : R/W; bitpos: [9:0]; default: 100; + * need_des + */ + uint32_t touch_meas_num2:10; + /** touch_meas_num1 : R/W; bitpos: [19:10]; default: 100; + * need_des + */ + uint32_t touch_meas_num1:10; + /** touch_meas_num0 : R/W; bitpos: [29:20]; default: 100; + * need_des + */ + uint32_t touch_meas_num0:10; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_analog_peri_touch_work_meas_num_reg_t; + +/** Type of touch_filter1 register + * need_des + */ +typedef union { + struct { + /** touch_nn_disupdate_benchmark_en : R/W; bitpos: [0]; default: 0; + * Reserved + */ + uint32_t touch_nn_disupdate_benchmark_en:1; + /** touch_hysteresis : R/W; bitpos: [2:1]; default: 0; + * need_des + */ + uint32_t touch_hysteresis:2; + /** touch_nn_thres : R/W; bitpos: [4:3]; default: 0; + * need_des + */ + uint32_t touch_nn_thres:2; + /** touch_noise_thres : R/W; bitpos: [6:5]; default: 0; + * need_des + */ + uint32_t touch_noise_thres:2; + /** touch_smooth_lvl : R/W; bitpos: [8:7]; default: 0; + * need_des + */ + uint32_t touch_smooth_lvl:2; + /** touch_jitter_step : R/W; bitpos: [12:9]; default: 1; + * need_des + */ + uint32_t touch_jitter_step:4; + /** touch_filter_mode : R/W; bitpos: [15:13]; default: 0; + * need_des + */ + uint32_t touch_filter_mode:3; + /** touch_filter_en : R/W; bitpos: [16]; default: 0; + * need_des + */ + uint32_t touch_filter_en:1; + /** touch_nn_limit : R/W; bitpos: [20:17]; default: 5; + * need_des + */ + uint32_t touch_nn_limit:4; + /** touch_approach_limit : R/W; bitpos: [28:21]; default: 80; + * need_des + */ + uint32_t touch_approach_limit:8; + /** touch_debounce_limit : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t touch_debounce_limit:3; + }; + uint32_t val; +} lp_analog_peri_touch_filter1_reg_t; + +/** Type of touch_filter2 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** touch_outen : R/W; bitpos: [29:15]; default: 16383; + * need_des + */ + uint32_t touch_outen:15; + /** touch_bypass_noise_thres : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t touch_bypass_noise_thres:1; + /** touch_bypass_nn_thres : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t touch_bypass_nn_thres:1; + }; + uint32_t val; +} lp_analog_peri_touch_filter2_reg_t; + +/** Type of touch_filter3 register + * need_des + */ +typedef union { + struct { + /** touch_benchmark_sw : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t touch_benchmark_sw:16; + /** touch_update_benchmark_sw : WT; bitpos: [16]; default: 0; + * need_des + */ + uint32_t touch_update_benchmark_sw:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_analog_peri_touch_filter3_reg_t; + +/** Type of touch_slp0 register + * need_des + */ +typedef union { + struct { + /** touch_slp_th0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t touch_slp_th0:16; + /** touch_slp_channel_clr : WT; bitpos: [16]; default: 0; + * need_des + */ + uint32_t touch_slp_channel_clr:1; + /** touch_slp_pad : R/W; bitpos: [20:17]; default: 15; + * need_des + */ + uint32_t touch_slp_pad:4; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_analog_peri_touch_slp0_reg_t; + +/** Type of touch_slp1 register + * need_des + */ +typedef union { + struct { + /** touch_slp_th2 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t touch_slp_th2:16; + /** touch_slp_th1 : R/W; bitpos: [31:16]; default: 0; + * need_des + */ + uint32_t touch_slp_th1:16; + }; + uint32_t val; +} lp_analog_peri_touch_slp1_reg_t; + +/** Type of touch_clr register + * need_des + */ +typedef union { + struct { + /** touch_channel_clr : WT; bitpos: [14:0]; default: 0; + * need_des + */ + uint32_t touch_channel_clr:15; + /** touch_status_clr : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t touch_status_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_analog_peri_touch_clr_reg_t; + +/** Type of touch_approach register + * need_des + */ +typedef union { + struct { + /** touch_approach_pad0 : R/W; bitpos: [3:0]; default: 15; + * need_des + */ + uint32_t touch_approach_pad0:4; + /** touch_approach_pad1 : R/W; bitpos: [7:4]; default: 15; + * need_des + */ + uint32_t touch_approach_pad1:4; + /** touch_approach_pad2 : R/W; bitpos: [11:8]; default: 15; + * need_des + */ + uint32_t touch_approach_pad2:4; + /** touch_slp_approach_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t touch_slp_approach_en:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} lp_analog_peri_touch_approach_reg_t; + +/** Type of touch_freq_scan_para register + * need_des + */ +typedef union { + struct { + /** touch_freq_dcap_lpf : R/W; bitpos: [6:0]; default: 0; + * Capacity of the RC low pass filter + * 0 ~ 2.54 pF, step 20fF + */ + uint32_t touch_freq_dcap_lpf:7; + /** touch_freq_dres_lpf : R/W; bitpos: [8:7]; default: 0; + * Resistance of the RC low pass filter + * 0 ~ 4.5 K, step 1.5 K + */ + uint32_t touch_freq_dres_lpf:2; + /** touch_freq_drv_ls : R/W; bitpos: [12:9]; default: 0; + * Low speed touch driver, effective when high speed driver is disabled + */ + uint32_t touch_freq_drv_ls:4; + /** touch_freq_drv_hs : R/W; bitpos: [17:13]; default: 0; + * High speed touch driver + */ + uint32_t touch_freq_drv_hs:5; + /** touch_bypass_shield : R/W; bitpos: [18]; default: 0; + * bypass the shield channel output (only available since ECO1) + */ + uint32_t touch_bypass_shield:1; + /** touch_freq_dbias : R/W; bitpos: [22:19]; default: 0; + * Internal LDO voltage + */ + uint32_t touch_freq_dbias:4; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_analog_peri_touch_freq_scan_para_reg_t; + +/** Type of touch_ana_para register + * need_des + */ +typedef union { + struct { + /** touch_touch_buf_drv : R/W; bitpos: [2:0]; default: 0; + * The driver of water proof touch buff + */ + uint32_t touch_touch_buf_drv:3; + /** touch_touch_en_cal : R/W; bitpos: [3]; default: 0; + * Enable internal loop. Need to turn off touch pad. + * Tuning 'dcap_cal' to change the frequency + */ + uint32_t touch_touch_en_cal:1; + /** touch_touch_dcap_cal : R/W; bitpos: [10:4]; default: 0; + * The internal capacitor connected to the touch pad. Effective when 'en_cal' enabled + * Normally set to 0 + */ + uint32_t touch_touch_dcap_cal:7; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_analog_peri_touch_ana_para_reg_t; + +/** Type of touch_mux0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** touch_data_sel : R/W; bitpos: [9:8]; default: 0; + * The type of the output data for debugging + * 0/1: raw data + * 2: benchmark + * 3: smooth data + */ + uint32_t touch_data_sel:2; + /** touch_freq_sel : R/W; bitpos: [11:10]; default: 0; + * The frequency id of the output data for debugging + * 0: invalid + * 1: Frequency 1 + * 2: Frequency 2 + * 3: Frequency 3 + */ + uint32_t touch_freq_sel:2; + /** touch_bufsel : R/W; bitpos: [26:12]; default: 0; + * The bitmap of the shield pad + */ + uint32_t touch_bufsel:15; + /** touch_done_en : R/W; bitpos: [27]; default: 0; + * Force to terminate the touch by software + */ + uint32_t touch_done_en:1; + /** touch_done_force : R/W; bitpos: [28]; default: 0; + * 0: Select touch_meas_done as the touch timer input + * 1: Select software termination as the touch timer input + */ + uint32_t touch_done_force:1; + /** touch_fsm_en : R/W; bitpos: [29]; default: 1; + * 0: Select software configured parameters for ana + * 1: Select hardware calculated parameters for ana + */ + uint32_t touch_fsm_en:1; + /** touch_start_en : R/W; bitpos: [30]; default: 0; + * Force to start the touch by software + */ + uint32_t touch_start_en:1; + /** touch_start_force : R/W; bitpos: [31]; default: 0; + * 0: Select the touch timer to start the touch scanning + * 1: Select the software to start the touch scanning + */ + uint32_t touch_start_force:1; + }; + uint32_t val; +} lp_analog_peri_touch_mux0_reg_t; + +/** Type of touch_mux1 register + * need_des + */ +typedef union { + struct { + /** touch_start : R/W; bitpos: [14:0]; default: 0; + * The bitmap of the start touch channels + */ + uint32_t touch_start:15; + /** touch_xpd : R/W; bitpos: [29:15]; default: 0; + * The bitmap of the power on touch channels + */ + uint32_t touch_xpd:15; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_analog_peri_touch_mux1_reg_t; + +/** Type of touch_pad0_th0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** touch_pad_th : R/W; bitpos: [31:16]; default: 0; + * The threshold to activate a touch channel + */ + uint32_t threshold:16; + }; + uint32_t val; +} lp_analog_peri_touch_pad_thn_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2294816; + * need_des + */ + uint32_t lp_analog_peri_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_analog_peri_date_reg_t; + + +typedef struct { + volatile lp_analog_peri_touch_pad_thn_reg_t thresh[3]; +} lp_analog_peri_touch_padx_thn_reg_t; + +typedef struct { + volatile lp_analog_peri_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_analog_peri_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl; + volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl; + volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl; + uint32_t reserved_014; + volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl; + volatile lp_analog_peri_fib_enable_reg_t fib_enable; + volatile lp_analog_peri_int_raw_reg_t int_raw; + volatile lp_analog_peri_int_st_reg_t int_st; + volatile lp_analog_peri_int_ena_reg_t int_ena; + volatile lp_analog_peri_int_clr_reg_t int_clr; + volatile lp_analog_peri_lp_int_raw_reg_t lp_int_raw; + volatile lp_analog_peri_lp_int_st_reg_t lp_int_st; + volatile lp_analog_peri_lp_int_ena_reg_t lp_int_ena; + volatile lp_analog_peri_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_040[47]; + volatile lp_analog_peri_touch_approach_work_meas_num_reg_t touch_approach_work_meas_num; + volatile lp_analog_peri_touch_scan_ctrl1_reg_t touch_scan_ctrl1; + volatile lp_analog_peri_touch_scan_ctrl2_reg_t touch_scan_ctrl2; + volatile lp_analog_peri_touch_work_reg_t touch_work; + volatile lp_analog_peri_touch_work_meas_num_reg_t touch_work_meas_num; + volatile lp_analog_peri_touch_filter1_reg_t touch_filter1; + volatile lp_analog_peri_touch_filter2_reg_t touch_filter2; + volatile lp_analog_peri_touch_filter3_reg_t touch_filter3; + volatile lp_analog_peri_touch_slp0_reg_t touch_slp0; + volatile lp_analog_peri_touch_slp1_reg_t touch_slp1; + volatile lp_analog_peri_touch_clr_reg_t touch_clr; + volatile lp_analog_peri_touch_approach_reg_t touch_approach; + volatile lp_analog_peri_touch_freq_scan_para_reg_t touch_freq_scan_para[3]; + volatile lp_analog_peri_touch_ana_para_reg_t touch_ana_para; + volatile lp_analog_peri_touch_mux0_reg_t touch_mux0; + volatile lp_analog_peri_touch_mux1_reg_t touch_mux1; + volatile lp_analog_peri_touch_padx_thn_reg_t touch_padx_thn[15]; + uint32_t reserved_1f8[129]; + volatile lp_analog_peri_date_reg_t date; +} lp_analog_peri_dev_t; + +extern lp_analog_peri_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_analog_peri_dev_t) == 0x400, "Invalid size of lp_analog_peri_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..c6b37fe988 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_reg.h @@ -0,0 +1,1036 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x0000003FU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 +/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_SEL_REF_PLL8M (BIT(10)) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_M (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S) +#define LP_CLKRST_ANA_SEL_REF_PLL8M_V 0x00000001U +#define LP_CLKRST_ANA_SEL_REF_PLL8M_S 10 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_CORE_EFUSE_OEN (BIT(0)) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S 0 +/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_LP_BUS_OEN (BIT(1)) +#define LP_CLKRST_CLK_LP_BUS_OEN_M (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S) +#define LP_CLKRST_CLK_LP_BUS_OEN_V 0x00000001U +#define LP_CLKRST_CLK_LP_BUS_OEN_S 1 +/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_AON_SLOW_OEN (BIT(2)) +#define LP_CLKRST_CLK_AON_SLOW_OEN_M (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S) +#define LP_CLKRST_CLK_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_SLOW_OEN_S 2 +/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_AON_FAST_OEN (BIT(3)) +#define LP_CLKRST_CLK_AON_FAST_OEN_M (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S) +#define LP_CLKRST_CLK_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_AON_FAST_OEN_S 3 +/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_SLOW_OEN (BIT(4)) +#define LP_CLKRST_CLK_SLOW_OEN_M (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S) +#define LP_CLKRST_CLK_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SLOW_OEN_S 4 +/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_FAST_OEN (BIT(5)) +#define LP_CLKRST_CLK_FAST_OEN_M (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S) +#define LP_CLKRST_CLK_FAST_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FAST_OEN_S 5 +/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_FOSC_OEN (BIT(6)) +#define LP_CLKRST_CLK_FOSC_OEN_M (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S) +#define LP_CLKRST_CLK_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_FOSC_OEN_S 6 +/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_RC32K_OEN (BIT(7)) +#define LP_CLKRST_CLK_RC32K_OEN_M (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S) +#define LP_CLKRST_CLK_RC32K_OEN_V 0x00000001U +#define LP_CLKRST_CLK_RC32K_OEN_S 7 +/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_SXTAL_OEN (BIT(8)) +#define LP_CLKRST_CLK_SXTAL_OEN_M (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S) +#define LP_CLKRST_CLK_SXTAL_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SXTAL_OEN_S 8 +/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0; + * 1'b1: probe sosc clk on + * 1'b0: probe sosc clk off + */ +#define LP_CLKRST_CLK_SOSC_OEN (BIT(9)) +#define LP_CLKRST_CLK_SOSC_OEN_M (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S) +#define LP_CLKRST_CLK_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_CLK_SOSC_OEN_S 9 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON (BIT(26)) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S) +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S 26 +/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LP_CLKRST_CK_EN_LP_RAM (BIT(27)) +#define LP_CLKRST_CK_EN_LP_RAM_M (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S) +#define LP_CLKRST_CK_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_CK_EN_LP_RAM_S 27 +/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_ETM_EVENT_TICK_EN (BIT(28)) +#define LP_CLKRST_ETM_EVENT_TICK_EN_M (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S) +#define LP_CLKRST_ETM_EVENT_TICK_EN_V 0x00000001U +#define LP_CLKRST_ETM_EVENT_TICK_EN_S 28 +/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_PLL8M_CLK_FORCE_ON (BIT(29)) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S) +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S 29 +/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_XTAL_CLK_FORCE_ON (BIT(30)) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_M (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S) +#define LP_CLKRST_XTAL_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_XTAL_CLK_FORCE_ON_S 30 +/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FOSC_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_M (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S) +#define LP_CLKRST_FOSC_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_FOSC_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_HUK (BIT(24)) +#define LP_CLKRST_RST_EN_LP_HUK_M (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S) +#define LP_CLKRST_RST_EN_LP_HUK_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_HUK_S 24 +/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_ANAPERI (BIT(25)) +#define LP_CLKRST_RST_EN_LP_ANAPERI_M (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S) +#define LP_CLKRST_RST_EN_LP_ANAPERI_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_ANAPERI_S 25 +/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_WDT (BIT(26)) +#define LP_CLKRST_RST_EN_LP_WDT_M (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S) +#define LP_CLKRST_RST_EN_LP_WDT_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_WDT_S 26 +/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_TIMER (BIT(27)) +#define LP_CLKRST_RST_EN_LP_TIMER_M (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S) +#define LP_CLKRST_RST_EN_LP_TIMER_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_TIMER_S 27 +/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RTC (BIT(28)) +#define LP_CLKRST_RST_EN_LP_RTC_M (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S) +#define LP_CLKRST_RST_EN_LP_RTC_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RTC_S 28 +/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_MAILBOX (BIT(29)) +#define LP_CLKRST_RST_EN_LP_MAILBOX_M (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S) +#define LP_CLKRST_RST_EN_LP_MAILBOX_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_MAILBOX_S 29 +/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG (BIT(30)) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S) +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S 30 +/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_RST_EN_LP_RAM (BIT(31)) +#define LP_CLKRST_RST_EN_LP_RAM_M (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S) +#define LP_CLKRST_RST_EN_LP_RAM_V 0x00000001U +#define LP_CLKRST_RST_EN_LP_RAM_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0; + * 6'h1: POR reset + * 6'h9: PMU LP PERI power down reset + * 6'ha: PMU LP CPU reset + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: software reset + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_M (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_LPCORE_RESET_CAUSE_S 0 +/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_FLAG (BIT(6)) +#define LP_CLKRST_LPCORE_RESET_FLAG_M (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_S 6 +/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_M (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE0_RESET_CAUSE_S 7 +/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG (BIT(13)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_M (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_S 13 +/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_M (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_V 0x0000003FU +#define LP_CLKRST_HPCORE1_RESET_CAUSE_S 14 +/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG (BIT(20)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_M (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_S 20 +/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1; + * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore + * pmu_lp_cpu_reset reset_cause + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK (BIT(25)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S 25 +/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR (BIT(26)) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S) +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S 26 +/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR (BIT(27)) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S) +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S 27 +/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR (BIT(28)) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S 28 +/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR (BIT(29)) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S 29 +/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR (BIT(30)) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S 30 +/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S) +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(0)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 0 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S 1 +/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0; + * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset + * hpcore0 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN (BIT(4)) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S 4 +/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_M (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S) +#define LP_CLKRST_HPCORE0_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE0_STALL_WAIT_S 5 +/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_STALL_EN (BIT(12)) +#define LP_CLKRST_HPCORE0_STALL_EN_M (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S) +#define LP_CLKRST_HPCORE0_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_STALL_EN_S 12 +/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_SW_RESET (BIT(13)) +#define LP_CLKRST_HPCORE0_SW_RESET_M (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S) +#define LP_CLKRST_HPCORE0_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_SW_RESET_S 13 +/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET (BIT(14)) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S 14 +/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL (BIT(15)) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S 15 +/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0; + * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(16)) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S 16 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1; + * need_des + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S 17 +/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0; + * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset + * hpcore1 feature + */ +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN (BIT(20)) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S) +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S 20 +/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_WAIT 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_M (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S) +#define LP_CLKRST_HPCORE1_STALL_WAIT_V 0x0000007FU +#define LP_CLKRST_HPCORE1_STALL_WAIT_S 21 +/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_STALL_EN (BIT(28)) +#define LP_CLKRST_HPCORE1_STALL_EN_M (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S) +#define LP_CLKRST_HPCORE1_STALL_EN_V 0x00000001U +#define LP_CLKRST_HPCORE1_STALL_EN_S 28 +/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_SW_RESET (BIT(29)) +#define LP_CLKRST_HPCORE1_SW_RESET_M (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S) +#define LP_CLKRST_HPCORE1_SW_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_SW_RESET_S 29 +/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET (BIT(30)) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S) +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S 30 +/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL (BIT(31)) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S) +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V 0x00000001U +#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S 31 + +/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register + * need_des + */ +#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0; + * HP core0 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE0_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S 16 +/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0; + * HP core1 software stall when set to 8'h86 + */ +#define LP_CLKRST_HPCORE1_SW_STALL_CODE 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S) +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V 0x000000FFU +#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S 24 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0xFFFFFFFFU +#define LP_CLKRST_RC32K_DFREQ_S 0 + +/** LP_CLKRST_SOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_SOSC_DFREQ 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_M (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S) +#define LP_CLKRST_SOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_SOSC_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34) +/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S) +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38) +/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_0_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S 0 + +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register + * need_des + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c) +/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S) +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V 0xFFFFFFFFU +#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S 0 + +/** LP_CLKRST_HP_CLK_CTRL_REG register + * HP Clock Control Register. + */ +#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40) +/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0; + * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + */ +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S) +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S 0 +/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1; + * HP SoC Root Clock Enable. + */ +#define LP_CLKRST_HP_ROOT_CLK_EN (BIT(2)) +#define LP_CLKRST_HP_ROOT_CLK_EN_M (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S) +#define LP_CLKRST_HP_ROOT_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_ROOT_CLK_EN_S 2 +/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1; + * PARLIO TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN (BIT(3)) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S 3 +/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1; + * PARLIO RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN (BIT(4)) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S 4 +/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1; + * UART4 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN (BIT(5)) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S 5 +/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1; + * UART3 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN (BIT(6)) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S 6 +/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1; + * UART2 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN (BIT(7)) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S 7 +/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1; + * UART1 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN (BIT(8)) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S 8 +/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1; + * UART0 SLP Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN (BIT(9)) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S) +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S 9 +/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1; + * I2S2 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN (BIT(10)) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S 10 +/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1; + * I2S1 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN (BIT(11)) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S 11 +/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1; + * I2S0 MCLK Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN (BIT(12)) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S) +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S 12 +/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1; + * EMAC RX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN (BIT(13)) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S 13 +/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1; + * EMAC TX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN (BIT(14)) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S 14 +/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1; + * EMAC TXRX Clock From Pad Enable. + */ +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN (BIT(15)) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S) +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S 15 +/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1; + * XTAL 32K Clock Enable. + */ +#define LP_CLKRST_HP_XTAL_32K_CLK_EN (BIT(16)) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S 16 +/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1; + * RC 32K Clock Enable. + */ +#define LP_CLKRST_HP_RC_32K_CLK_EN (BIT(17)) +#define LP_CLKRST_HP_RC_32K_CLK_EN_M (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S) +#define LP_CLKRST_HP_RC_32K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_RC_32K_CLK_EN_S 17 +/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1; + * SOSC 150K Clock Enable. + */ +#define LP_CLKRST_HP_SOSC_150K_CLK_EN (BIT(18)) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S) +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S 18 +/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1; + * PLL 8M Clock Enable. + */ +#define LP_CLKRST_HP_PLL_8M_CLK_EN (BIT(19)) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_M (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S) +#define LP_CLKRST_HP_PLL_8M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_PLL_8M_CLK_EN_S 19 +/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1; + * AUDIO PLL Clock Enable. + */ +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN (BIT(20)) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S) +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S 20 +/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1; + * SDIO PLL2 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN (BIT(21)) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S 21 +/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1; + * SDIO PLL1 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN (BIT(22)) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S 22 +/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1; + * SDIO PLL0 Clock Enable. + */ +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN (BIT(23)) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S) +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S 23 +/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1; + * FOSC 20M Clock Enable. + */ +#define LP_CLKRST_HP_FOSC_20M_CLK_EN (BIT(24)) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S) +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S 24 +/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1; + * XTAL 40M Clock Enable. + */ +#define LP_CLKRST_HP_XTAL_40M_CLK_EN (BIT(25)) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S) +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S 25 +/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1; + * CPLL 400M Clock Enable. + */ +#define LP_CLKRST_HP_CPLL_400M_CLK_EN (BIT(26)) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S) +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S 26 +/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1; + * SPLL 480M Clock Enable. + */ +#define LP_CLKRST_HP_SPLL_480M_CLK_EN (BIT(27)) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S) +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S 27 +/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1; + * MPLL 500M Clock Enable. + */ +#define LP_CLKRST_HP_MPLL_500M_CLK_EN (BIT(28)) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S) +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V 0x00000001U +#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S 28 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44) +/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG20_SLEEP_MODE (BIT(0)) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S 0 +/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN (BIT(1)) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S 1 +/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0; + * unused. + */ +#define LP_CLKRST_USB_OTG11_SLEEP_MODE (BIT(2)) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S) +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V 0x00000001U +#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S 2 +/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1; + * unused. + */ +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN (BIT(3)) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S 3 +/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1; + * usb otg11 fs phy clock enable. + */ +#define LP_CLKRST_USB_OTG11_48M_CLK_EN (BIT(4)) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S) +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S 4 +/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * usb device fs phy clock enable. + */ +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN (BIT(5)) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S) +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S 5 +/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9; + * usb 480m to 25m divide number. + */ +#define LP_CLKRST_USB_48M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_M (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S) +#define LP_CLKRST_USB_48M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_48M_DIV_NUM_S 6 +/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19; + * usb 500m to 25m divide number. + */ +#define LP_CLKRST_USB_25M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_M (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S) +#define LP_CLKRST_USB_25M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_25M_DIV_NUM_S 14 +/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39; + * usb 480m to 12m divide number. + */ +#define LP_CLKRST_USB_12M_DIV_NUM 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_M (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S) +#define LP_CLKRST_USB_12M_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_USB_12M_DIV_NUM_S 22 + +/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register + * HP USB Clock Reset Control Register. + */ +#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48) +/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0; + * usb otg20 adp reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_ADP (BIT(0)) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S) +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S 0 +/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0; + * usb otg20 phy reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20_PHY (BIT(1)) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S) +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S 1 +/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0; + * usb otg20 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG20 (BIT(2)) +#define LP_CLKRST_RST_EN_USB_OTG20_M (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S) +#define LP_CLKRST_RST_EN_USB_OTG20_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG20_S 2 +/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0; + * usb org11 reset en + */ +#define LP_CLKRST_RST_EN_USB_OTG11 (BIT(3)) +#define LP_CLKRST_RST_EN_USB_OTG11_M (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S) +#define LP_CLKRST_RST_EN_USB_OTG11_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_OTG11_S 3 +/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0; + * usb device reset en + */ +#define LP_CLKRST_RST_EN_USB_DEVICE (BIT(4)) +#define LP_CLKRST_RST_EN_USB_DEVICE_M (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S) +#define LP_CLKRST_RST_EN_USB_DEVICE_V 0x00000001U +#define LP_CLKRST_RST_EN_USB_DEVICE_S 4 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0; + * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V 0x00000003U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S 28 +/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1; + * usb otg20 hs phy refclk enable. + */ +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN (BIT(30)) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S 30 +/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1; + * usb otg20 ulpi clock enable. + */ +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN (BIT(31)) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S) +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V 0x00000001U +#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S 31 + +/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register + * need_des + */ +#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c) +/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0; + * hp sdmmc reset en + */ +#define LP_CLKRST_RST_EN_SDMMC (BIT(28)) +#define LP_CLKRST_RST_EN_SDMMC_M (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S) +#define LP_CLKRST_RST_EN_SDMMC_V 0x00000001U +#define LP_CLKRST_RST_EN_SDMMC_S 28 +/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0; + * hp sdmmc force norst + */ +#define LP_CLKRST_FORCE_NORST_SDMMC (BIT(29)) +#define LP_CLKRST_FORCE_NORST_SDMMC_M (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S) +#define LP_CLKRST_FORCE_NORST_SDMMC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_SDMMC_S 29 +/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0; + * hp emac reset en + */ +#define LP_CLKRST_RST_EN_EMAC (BIT(30)) +#define LP_CLKRST_RST_EN_EMAC_M (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S) +#define LP_CLKRST_RST_EN_EMAC_V 0x00000001U +#define LP_CLKRST_RST_EN_EMAC_S 30 +/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0; + * hp emac force norst + */ +#define LP_CLKRST_FORCE_NORST_EMAC (BIT(31)) +#define LP_CLKRST_FORCE_NORST_EMAC_M (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S) +#define LP_CLKRST_FORCE_NORST_EMAC_V 0x00000001U +#define LP_CLKRST_FORCE_NORST_EMAC_S 31 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..49e42b840d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_clkrst_struct.h @@ -0,0 +1,796 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * need_des + */ + uint32_t fast_clk_sel:2; + /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0; + * need_des + */ + uint32_t lp_peri_div_num:6; + /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_sel_ref_pll8m:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_aonclkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t clk_core_efuse_oen:1; + /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t clk_lp_bus_oen:1; + /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t clk_aon_slow_oen:1; + /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0; + * need_des + */ + uint32_t clk_aon_fast_oen:1; + /** clk_slow_oen : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t clk_slow_oen:1; + /** clk_fast_oen : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t clk_fast_oen:1; + /** clk_fosc_oen : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t clk_fosc_oen:1; + /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t clk_rc32k_oen:1; + /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t clk_sxtal_oen:1; + /** clk_sosc_oen : R/W; bitpos: [9]; default: 0; + * 1'b1: probe sosc clk on + * 1'b0: probe sosc clk off + */ + uint32_t clk_sosc_oen:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} lp_aonclkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_rtc_xtal_force_on:1; + /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t ck_en_lp_ram:1; + /** etm_event_tick_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t etm_event_tick_en:1; + /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t pll8m_clk_force_on:1; + /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xtal_clk_force_on:1; + /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t fosc_clk_force_on:1; + }; + uint32_t val; +} lp_aonclkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t rst_en_lp_huk:1; + /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t rst_en_lp_anaperi:1; + /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t rst_en_lp_wdt:1; + /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t rst_en_lp_timer:1; + /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t rst_en_lp_rtc:1; + /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t rst_en_lp_mailbox:1; + /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t rst_en_lp_aonefusereg:1; + /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rst_en_lp_ram:1; + }; + uint32_t val; +} lp_aonclkrst_lp_rst_en_reg_t; + +/** Type of reset_cause register + * need_des + */ +typedef union { + struct { + /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0; + * 6'h1: POR reset + * 6'h9: PMU LP PERI power down reset + * 6'ha: PMU LP CPU reset + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: software reset + */ + uint32_t lpcore_reset_cause:6; + /** lpcore_reset_flag : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t lpcore_reset_flag:1; + /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ + uint32_t hpcore0_reset_cause:6; + /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hpcore0_reset_flag:1; + /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0; + * 6'h1: POR reset + * 6'h3: digital system software reset + * 6'h5: PMU HP system power down reset + * 6'h7: HP system reset from HP watchdog + * 6'h9: HP system reset from LP watchdog + * 6'hb: HP core reset from HP watchdog + * 6'hc: HP core software reset + * 6'hd: HP core reset from LP watchdog + * 6'hf: brown out reset + * 6'h10: LP watchdog chip reset + * 6'h12: super watch dog reset + * 6'h13: glitch reset + * 6'h14: efuse crc error reset + * 6'h16: HP usb jtag chip reset + * 6'h17: HP usb uart chip reset + * 6'h18: HP jtag reset + * 6'h1a: HP core lockup + */ + uint32_t hpcore1_reset_cause:6; + /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t hpcore1_reset_flag:1; + uint32_t reserved_21:4; + /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1; + * 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore + * pmu_lp_cpu_reset reset_cause + */ + uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1; + /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lpcore_reset_cause_clr:1; + /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lpcore_reset_flag_clr:1; + /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hpcore0_reset_cause_clr:1; + /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hpcore0_reset_flag_clr:1; + /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hpcore1_reset_cause_clr:1; + /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpcore1_reset_flag_clr:1; + }; + uint32_t val; +} lp_aonclkrst_reset_cause_reg_t; + +/** Type of hpcpu_reset_ctrl0 register + * need_des + */ +typedef union { + struct { + /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ + uint32_t hpcore0_lockup_reset_en:1; + /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1; + * need_des + */ + uint32_t lp_wdt_hpcore0_reset_length:3; + /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0; + * write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset + * hpcore0 feature + */ + uint32_t lp_wdt_hpcore0_reset_en:1; + /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0; + * need_des + */ + uint32_t hpcore0_stall_wait:7; + /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hpcore0_stall_en:1; + /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hpcore0_sw_reset:1; + /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t hpcore0_ocd_halt_on_reset:1; + /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ + uint32_t hpcore0_stat_vector_sel:1; + /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0; + * write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup + * reset feature + */ + uint32_t hpcore1_lockup_reset_en:1; + /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1; + * need_des + */ + uint32_t lp_wdt_hpcore1_reset_length:3; + /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0; + * write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset + * hpcore1 feature + */ + uint32_t lp_wdt_hpcore1_reset_en:1; + /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0; + * need_des + */ + uint32_t hpcore1_stall_wait:7; + /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hpcore1_stall_en:1; + /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hpcore1_sw_reset:1; + /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hpcore1_ocd_halt_on_reset:1; + /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1; + * 1'b1: boot from HP TCM ROM: 0x4FC00000 + * 1'b0: boot from LP TCM RAM: 0x50108000 + */ + uint32_t hpcore1_stat_vector_sel:1; + }; + uint32_t val; +} lp_aonclkrst_hpcpu_reset_ctrl0_reg_t; + +/** Type of hpcpu_reset_ctrl1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0; + * HP core0 software stall when set to 8'h86 + */ + uint32_t hpcore0_sw_stall_code:8; + /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0; + * HP core1 software stall when set to 8'h86 + */ + uint32_t hpcore1_sw_stall_code:8; + }; + uint32_t val; +} lp_aonclkrst_hpcpu_reset_ctrl1_reg_t; + +/** Type of fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400; + * need_des + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_aonclkrst_fosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * need_des + */ +typedef union { + struct { + /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650; + * need_des + */ + uint32_t rc32k_dfreq:32; + }; + uint32_t val; +} lp_aonclkrst_rc32k_cntl_reg_t; + +/** Type of sosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t sosc_dfreq:10; + }; + uint32_t val; +} lp_aonclkrst_sosc_cntl_reg_t; + +/** Type of clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * reserved + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * reserved + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * reserved + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * reserved + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_aonclkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_aonclkrst_lpmem_force_reg_t; + +/** Type of xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_aonclkrst_xtal32k_reg_t; + +/** Type of mux_hpsys_reset_bypass register + * need_des + */ +typedef union { + struct { + /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t mux_hpsys_reset_bypass:32; + }; + uint32_t val; +} lp_aonclkrst_mux_hpsys_reset_bypass_reg_t; + +/** Type of hpsys_0_reset_bypass register + * need_des + */ +typedef union { + struct { + /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t hpsys_0_reset_bypass:32; + }; + uint32_t val; +} lp_aonclkrst_hpsys_0_reset_bypass_reg_t; + +/** Type of hpsys_apm_reset_bypass register + * need_des + */ +typedef union { + struct { + /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t hpsys_apm_reset_bypass:32; + }; + uint32_t val; +} lp_aonclkrst_hpsys_apm_reset_bypass_reg_t; + +/** Type of hp_clk_ctrl register + * HP Clock Control Register. + */ +typedef union { + struct { + /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0; + * HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + */ + uint32_t hp_root_clk_src_sel:2; + /** hp_root_clk_en : R/W; bitpos: [2]; default: 1; + * HP SoC Root Clock Enable. + */ + uint32_t hp_root_clk_en:1; + /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1; + * PARLIO TX Clock From Pad Enable. + */ + uint32_t hp_pad_parlio_tx_clk_en:1; + /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1; + * PARLIO RX Clock From Pad Enable. + */ + uint32_t hp_pad_parlio_rx_clk_en:1; + /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1; + * UART4 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart4_slp_clk_en:1; + /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1; + * UART3 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart3_slp_clk_en:1; + /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1; + * UART2 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart2_slp_clk_en:1; + /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1; + * UART1 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart1_slp_clk_en:1; + /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1; + * UART0 SLP Clock From Pad Enable. + */ + uint32_t hp_pad_uart0_slp_clk_en:1; + /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1; + * I2S2 MCLK Clock From Pad Enable. + */ + uint32_t hp_pad_i2s2_mclk_en:1; + /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1; + * I2S1 MCLK Clock From Pad Enable. + */ + uint32_t hp_pad_i2s1_mclk_en:1; + /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1; + * I2S0 MCLK Clock From Pad Enable. + */ + uint32_t hp_pad_i2s0_mclk_en:1; + /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1; + * EMAC RX Clock From Pad Enable. + */ + uint32_t hp_pad_emac_tx_clk_en:1; + /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1; + * EMAC TX Clock From Pad Enable. + */ + uint32_t hp_pad_emac_rx_clk_en:1; + /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1; + * EMAC TXRX Clock From Pad Enable. + */ + uint32_t hp_pad_emac_txrx_clk_en:1; + /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1; + * XTAL 32K Clock Enable. + */ + uint32_t hp_xtal_32k_clk_en:1; + /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1; + * RC 32K Clock Enable. + */ + uint32_t hp_rc_32k_clk_en:1; + /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1; + * SOSC 150K Clock Enable. + */ + uint32_t hp_sosc_150k_clk_en:1; + /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1; + * PLL 8M Clock Enable. + */ + uint32_t hp_pll_8m_clk_en:1; + /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1; + * AUDIO PLL Clock Enable. + */ + uint32_t hp_audio_pll_clk_en:1; + /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1; + * SDIO PLL2 Clock Enable. + */ + uint32_t hp_sdio_pll2_clk_en:1; + /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1; + * SDIO PLL1 Clock Enable. + */ + uint32_t hp_sdio_pll1_clk_en:1; + /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1; + * SDIO PLL0 Clock Enable. + */ + uint32_t hp_sdio_pll0_clk_en:1; + /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1; + * FOSC 20M Clock Enable. + */ + uint32_t hp_fosc_20m_clk_en:1; + /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1; + * XTAL 40M Clock Enable. + */ + uint32_t hp_xtal_40m_clk_en:1; + /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1; + * CPLL 400M Clock Enable. + */ + uint32_t hp_cpll_400m_clk_en:1; + /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1; + * SPLL 480M Clock Enable. + */ + uint32_t hp_spll_480m_clk_en:1; + /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1; + * MPLL 500M Clock Enable. + */ + uint32_t hp_mpll_500m_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_aonclkrst_hp_clk_ctrl_reg_t; + +/** Type of hp_usb_clkrst_ctrl0 register + * HP USB Clock Reset Control Register. + */ +typedef union { + struct { + /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0; + * unused. + */ + uint32_t usb_otg20_sleep_mode:1; + /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1; + * unused. + */ + uint32_t usb_otg20_bk_sys_clk_en:1; + /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0; + * unused. + */ + uint32_t usb_otg11_sleep_mode:1; + /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1; + * unused. + */ + uint32_t usb_otg11_bk_sys_clk_en:1; + /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1; + * usb otg11 fs phy clock enable. + */ + uint32_t usb_otg11_48m_clk_en:1; + /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1; + * usb device fs phy clock enable. + */ + uint32_t usb_device_48m_clk_en:1; + /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9; + * usb 480m to 25m divide number. + */ + uint32_t usb_48m_div_num:8; + /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19; + * usb 500m to 25m divide number. + */ + uint32_t usb_25m_div_num:8; + /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39; + * usb 480m to 12m divide number. + */ + uint32_t usb_12m_div_num:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t; + +/** Type of hp_usb_clkrst_ctrl1 register + * HP USB Clock Reset Control Register. + */ +typedef union { + struct { + /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0; + * usb otg20 adp reset en + */ + uint32_t rst_en_usb_otg20_adp:1; + /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0; + * usb otg20 phy reset en + */ + uint32_t rst_en_usb_otg20_phy:1; + /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0; + * usb otg20 reset en + */ + uint32_t rst_en_usb_otg20:1; + /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0; + * usb org11 reset en + */ + uint32_t rst_en_usb_otg11:1; + /** rst_en_usb_device : R/W; bitpos: [4]; default: 0; + * usb device reset en + */ + uint32_t rst_en_usb_device:1; + uint32_t reserved_5:23; + /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0; + * usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + */ + uint32_t usb_otg20_phyref_clk_src_sel:2; + /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1; + * usb otg20 hs phy refclk enable. + */ + uint32_t usb_otg20_phyref_clk_en:1; + /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1; + * usb otg20 ulpi clock enable. + */ + uint32_t usb_otg20_ulpi_clk_en:1; + }; + uint32_t val; +} lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t; + +/** Type of hp_sdmmc_emac_rst_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0; + * hp sdmmc reset en + */ + uint32_t rst_en_sdmmc:1; + /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0; + * hp sdmmc force norst + */ + uint32_t force_norst_sdmmc:1; + /** rst_en_emac : R/W; bitpos: [30]; default: 0; + * hp emac reset en + */ + uint32_t rst_en_emac:1; + /** force_norst_emac : R/W; bitpos: [31]; default: 0; + * hp emac force norst + */ + uint32_t force_norst_emac:1; + }; + uint32_t val; +} lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_aonclkrst_date_reg_t; + + +typedef struct { + volatile lp_aonclkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_aonclkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_aonclkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_aonclkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_aonclkrst_reset_cause_reg_t reset_cause; + volatile lp_aonclkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0; + volatile lp_aonclkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1; + volatile lp_aonclkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_aonclkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_aonclkrst_sosc_cntl_reg_t sosc_cntl; + volatile lp_aonclkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_aonclkrst_lpmem_force_reg_t lpmem_force; + volatile lp_aonclkrst_xtal32k_reg_t xtal32k; + volatile lp_aonclkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass; + volatile lp_aonclkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass; + volatile lp_aonclkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass; + volatile lp_aonclkrst_hp_clk_ctrl_reg_t hp_clk_ctrl; + volatile lp_aonclkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0; + volatile lp_aonclkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1; + volatile lp_aonclkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl; + uint32_t reserved_050[235]; + volatile lp_aonclkrst_date_reg_t date; +} lp_aonclkrst_dev_t; + +extern lp_aonclkrst_dev_t LP_AON_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_reg.h new file mode 100644 index 0000000000..6e3da4f938 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_reg.h @@ -0,0 +1,1593 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_GPIO_CLK_EN_REG register + * Reserved + */ +#define LP_GPIO_CLK_EN_REG (DR_REG_LP_GPIO_BASE + 0x0) +/** LP_GPIO_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Reserved + */ +#define LP_GPIO_REG_CLK_EN (BIT(0)) +#define LP_GPIO_REG_CLK_EN_M (LP_GPIO_REG_CLK_EN_V << LP_GPIO_REG_CLK_EN_S) +#define LP_GPIO_REG_CLK_EN_V 0x00000001U +#define LP_GPIO_REG_CLK_EN_S 0 + +/** LP_GPIO_VER_DATE_REG register + * Reserved + */ +#define LP_GPIO_VER_DATE_REG (DR_REG_LP_GPIO_BASE + 0x4) +/** LP_GPIO_REG_VER_DATE : R/W; bitpos: [27:0]; default: 2294563; + * Reserved + */ +#define LP_GPIO_REG_VER_DATE 0x0FFFFFFFU +#define LP_GPIO_REG_VER_DATE_M (LP_GPIO_REG_VER_DATE_V << LP_GPIO_REG_VER_DATE_S) +#define LP_GPIO_REG_VER_DATE_V 0x0FFFFFFFU +#define LP_GPIO_REG_VER_DATE_S 0 + +/** LP_GPIO_OUT_REG register + * Reserved + */ +#define LP_GPIO_OUT_REG (DR_REG_LP_GPIO_BASE + 0x8) +/** LP_GPIO_REG_GPIO_OUT_DATA : R/W/WTC; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_OUT_DATA 0x0000FFFFU +#define LP_GPIO_REG_GPIO_OUT_DATA_M (LP_GPIO_REG_GPIO_OUT_DATA_V << LP_GPIO_REG_GPIO_OUT_DATA_S) +#define LP_GPIO_REG_GPIO_OUT_DATA_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_OUT_DATA_S 0 + +/** LP_GPIO_OUT_W1TS_REG register + * Reserved + */ +#define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_GPIO_BASE + 0xc) +/** LP_GPIO_REG_GPIO_OUT_DATA_W1TS : WT; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS 0x0000FFFFU +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS_M (LP_GPIO_REG_GPIO_OUT_DATA_W1TS_V << LP_GPIO_REG_GPIO_OUT_DATA_W1TS_S) +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TS_S 0 + +/** LP_GPIO_OUT_W1TC_REG register + * Reserved + */ +#define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x10) +/** LP_GPIO_REG_GPIO_OUT_DATA_W1TC : WT; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC 0x0000FFFFU +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC_M (LP_GPIO_REG_GPIO_OUT_DATA_W1TC_V << LP_GPIO_REG_GPIO_OUT_DATA_W1TC_S) +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_OUT_DATA_W1TC_S 0 + +/** LP_GPIO_ENABLE_REG register + * Reserved + */ +#define LP_GPIO_ENABLE_REG (DR_REG_LP_GPIO_BASE + 0x14) +/** LP_GPIO_REG_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_ENABLE_DATA 0x0000FFFFU +#define LP_GPIO_REG_GPIO_ENABLE_DATA_M (LP_GPIO_REG_GPIO_ENABLE_DATA_V << LP_GPIO_REG_GPIO_ENABLE_DATA_S) +#define LP_GPIO_REG_GPIO_ENABLE_DATA_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_ENABLE_DATA_S 0 + +/** LP_GPIO_ENABLE_W1TS_REG register + * Reserved + */ +#define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x18) +/** LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS : WT; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS 0x0000FFFFU +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_M (LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_V << LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_S) +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TS_S 0 + +/** LP_GPIO_ENABLE_W1TC_REG register + * Reserved + */ +#define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x1c) +/** LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC : WT; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC 0x0000FFFFU +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_M (LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_V << LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_S) +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_ENABLE_DATA_W1TC_S 0 + +/** LP_GPIO_STATUS_REG register + * Reserved + */ +#define LP_GPIO_STATUS_REG (DR_REG_LP_GPIO_BASE + 0x20) +/** LP_GPIO_REG_GPIO_STATUS_DATA : R/W/WTC; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_STATUS_DATA 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_DATA_M (LP_GPIO_REG_GPIO_STATUS_DATA_V << LP_GPIO_REG_GPIO_STATUS_DATA_S) +#define LP_GPIO_REG_GPIO_STATUS_DATA_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_DATA_S 0 + +/** LP_GPIO_STATUS_W1TS_REG register + * Reserved + */ +#define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x24) +/** LP_GPIO_REG_GPIO_STATUS_DATA_W1TS : WT; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_M (LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_V << LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_S) +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TS_S 0 + +/** LP_GPIO_STATUS_W1TC_REG register + * Reserved + */ +#define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x28) +/** LP_GPIO_REG_GPIO_STATUS_DATA_W1TC : WT; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_M (LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_V << LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_S) +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_DATA_W1TC_S 0 + +/** LP_GPIO_STATUS_NEXT_REG register + * Reserved + */ +#define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_GPIO_BASE + 0x2c) +/** LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_M (LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_S) +#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** LP_GPIO_IN_REG register + * Reserved + */ +#define LP_GPIO_IN_REG (DR_REG_LP_GPIO_BASE + 0x30) +/** LP_GPIO_REG_GPIO_IN_DATA_NEXT : RO; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_IN_DATA_NEXT 0x0000FFFFU +#define LP_GPIO_REG_GPIO_IN_DATA_NEXT_M (LP_GPIO_REG_GPIO_IN_DATA_NEXT_V << LP_GPIO_REG_GPIO_IN_DATA_NEXT_S) +#define LP_GPIO_REG_GPIO_IN_DATA_NEXT_V 0x0000FFFFU +#define LP_GPIO_REG_GPIO_IN_DATA_NEXT_S 0 + +/** LP_GPIO_PIN0_REG register + * Reserved + */ +#define LP_GPIO_PIN0_REG (DR_REG_LP_GPIO_BASE + 0x34) +/** LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN0_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN0_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN0_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN0_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN0_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN0_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN1_REG register + * Reserved + */ +#define LP_GPIO_PIN1_REG (DR_REG_LP_GPIO_BASE + 0x38) +/** LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN1_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN1_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN1_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN1_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN1_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN1_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN2_REG register + * Reserved + */ +#define LP_GPIO_PIN2_REG (DR_REG_LP_GPIO_BASE + 0x3c) +/** LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN2_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN2_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN2_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN2_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN2_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN2_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN3_REG register + * Reserved + */ +#define LP_GPIO_PIN3_REG (DR_REG_LP_GPIO_BASE + 0x40) +/** LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN3_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN3_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN3_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN3_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN3_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN3_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN4_REG register + * Reserved + */ +#define LP_GPIO_PIN4_REG (DR_REG_LP_GPIO_BASE + 0x44) +/** LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN4_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN4_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN4_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN4_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN4_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN4_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN5_REG register + * Reserved + */ +#define LP_GPIO_PIN5_REG (DR_REG_LP_GPIO_BASE + 0x48) +/** LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN5_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN5_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN5_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN5_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN5_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN5_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN6_REG register + * Reserved + */ +#define LP_GPIO_PIN6_REG (DR_REG_LP_GPIO_BASE + 0x4c) +/** LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN6_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN6_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN6_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN6_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN6_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN6_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN7_REG register + * Reserved + */ +#define LP_GPIO_PIN7_REG (DR_REG_LP_GPIO_BASE + 0x50) +/** LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN7_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN7_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN7_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN7_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN7_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN7_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN8_REG register + * Reserved + */ +#define LP_GPIO_PIN8_REG (DR_REG_LP_GPIO_BASE + 0x54) +/** LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN8_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN8_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN8_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN8_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN8_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN8_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN9_REG register + * Reserved + */ +#define LP_GPIO_PIN9_REG (DR_REG_LP_GPIO_BASE + 0x58) +/** LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN9_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN9_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN9_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN9_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN9_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN9_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN10_REG register + * Reserved + */ +#define LP_GPIO_PIN10_REG (DR_REG_LP_GPIO_BASE + 0x5c) +/** LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN10_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN10_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN10_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN10_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN10_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN10_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN11_REG register + * Reserved + */ +#define LP_GPIO_PIN11_REG (DR_REG_LP_GPIO_BASE + 0x60) +/** LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN11_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN11_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN11_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN11_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN11_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN11_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN12_REG register + * Reserved + */ +#define LP_GPIO_PIN12_REG (DR_REG_LP_GPIO_BASE + 0x64) +/** LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN12_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN12_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN12_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN12_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN12_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN12_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN13_REG register + * Reserved + */ +#define LP_GPIO_PIN13_REG (DR_REG_LP_GPIO_BASE + 0x68) +/** LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN13_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN13_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN13_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN13_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN13_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN13_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN14_REG register + * Reserved + */ +#define LP_GPIO_PIN14_REG (DR_REG_LP_GPIO_BASE + 0x6c) +/** LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN14_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN14_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN14_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN14_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN14_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN14_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_PIN15_REG register + * Reserved + */ +#define LP_GPIO_PIN15_REG (DR_REG_LP_GPIO_BASE + 0x70) +/** LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE (BIT(0)) +#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_M (LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_V << LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_S) +#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN15_WAKEUP_ENABLE_S 0 +/** LP_GPIO_REG_GPIO_PIN15_INT_TYPE : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE 0x00000007U +#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE_M (LP_GPIO_REG_GPIO_PIN15_INT_TYPE_V << LP_GPIO_REG_GPIO_PIN15_INT_TYPE_S) +#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE_V 0x00000007U +#define LP_GPIO_REG_GPIO_PIN15_INT_TYPE_S 1 +/** LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [4]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER (BIT(4)) +#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_M (LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_V << LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_S) +#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_REG_GPIO_PIN15_PAD_DRIVER_S 4 +/** LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * need des + */ +#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_S 5 + +/** LP_GPIO_FUNC0_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x74) +/** LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC0_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG0_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG0_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG0_IN_SEL_M (LP_GPIO_REG_GPIO_SIG0_IN_SEL_V << LP_GPIO_REG_GPIO_SIG0_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG0_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG0_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC0_IN_SEL : R/W; bitpos: [7:2]; default: 48; + * reg_gpio_func0_in_sel[5:4]==2'b11->constant + * 1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0 + */ +#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC0_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC0_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC0_IN_SEL_S 2 + +/** LP_GPIO_FUNC1_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x78) +/** LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC1_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG1_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG1_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG1_IN_SEL_M (LP_GPIO_REG_GPIO_SIG1_IN_SEL_V << LP_GPIO_REG_GPIO_SIG1_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG1_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG1_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC1_IN_SEL : R/W; bitpos: [7:2]; default: 48; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC1_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC1_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC1_IN_SEL_S 2 + +/** LP_GPIO_FUNC2_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x7c) +/** LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC2_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG2_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG2_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG2_IN_SEL_M (LP_GPIO_REG_GPIO_SIG2_IN_SEL_V << LP_GPIO_REG_GPIO_SIG2_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG2_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG2_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC2_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC2_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC2_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC2_IN_SEL_S 2 + +/** LP_GPIO_FUNC3_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x80) +/** LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC3_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG3_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG3_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG3_IN_SEL_M (LP_GPIO_REG_GPIO_SIG3_IN_SEL_V << LP_GPIO_REG_GPIO_SIG3_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG3_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG3_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC3_IN_SEL : R/W; bitpos: [7:2]; default: 48; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC3_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC3_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC3_IN_SEL_S 2 + +/** LP_GPIO_FUNC4_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x84) +/** LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC4_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG4_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG4_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG4_IN_SEL_M (LP_GPIO_REG_GPIO_SIG4_IN_SEL_V << LP_GPIO_REG_GPIO_SIG4_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG4_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG4_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC4_IN_SEL : R/W; bitpos: [7:2]; default: 48; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC4_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC4_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC4_IN_SEL_S 2 + +/** LP_GPIO_FUNC5_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x88) +/** LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC5_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG5_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG5_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG5_IN_SEL_M (LP_GPIO_REG_GPIO_SIG5_IN_SEL_V << LP_GPIO_REG_GPIO_SIG5_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG5_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG5_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC5_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC5_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC5_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC5_IN_SEL_S 2 + +/** LP_GPIO_FUNC6_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x8c) +/** LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC6_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG6_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG6_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG6_IN_SEL_M (LP_GPIO_REG_GPIO_SIG6_IN_SEL_V << LP_GPIO_REG_GPIO_SIG6_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG6_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG6_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC6_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC6_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC6_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC6_IN_SEL_S 2 + +/** LP_GPIO_FUNC7_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x90) +/** LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC7_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG7_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG7_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG7_IN_SEL_M (LP_GPIO_REG_GPIO_SIG7_IN_SEL_V << LP_GPIO_REG_GPIO_SIG7_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG7_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG7_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC7_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC7_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC7_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC7_IN_SEL_S 2 + +/** LP_GPIO_FUNC8_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x94) +/** LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC8_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG8_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG8_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG8_IN_SEL_M (LP_GPIO_REG_GPIO_SIG8_IN_SEL_V << LP_GPIO_REG_GPIO_SIG8_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG8_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG8_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC8_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC8_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC8_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC8_IN_SEL_S 2 + +/** LP_GPIO_FUNC9_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x98) +/** LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC9_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG9_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG9_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG9_IN_SEL_M (LP_GPIO_REG_GPIO_SIG9_IN_SEL_V << LP_GPIO_REG_GPIO_SIG9_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG9_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG9_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC9_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC9_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC9_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC9_IN_SEL_S 2 + +/** LP_GPIO_FUNC10_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x9c) +/** LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC10_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG10_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG10_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG10_IN_SEL_M (LP_GPIO_REG_GPIO_SIG10_IN_SEL_V << LP_GPIO_REG_GPIO_SIG10_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG10_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG10_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC10_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC10_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC10_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC10_IN_SEL_S 2 + +/** LP_GPIO_FUNC11_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xa0) +/** LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC11_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG11_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG11_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG11_IN_SEL_M (LP_GPIO_REG_GPIO_SIG11_IN_SEL_V << LP_GPIO_REG_GPIO_SIG11_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG11_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG11_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC11_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC11_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC11_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC11_IN_SEL_S 2 + +/** LP_GPIO_FUNC12_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xa4) +/** LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC12_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG12_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG12_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG12_IN_SEL_M (LP_GPIO_REG_GPIO_SIG12_IN_SEL_V << LP_GPIO_REG_GPIO_SIG12_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG12_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG12_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC12_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC12_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC12_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC12_IN_SEL_S 2 + +/** LP_GPIO_FUNC13_IN_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xa8) +/** LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC13_IN_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_SIG13_IN_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_SIG13_IN_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_SIG13_IN_SEL_M (LP_GPIO_REG_GPIO_SIG13_IN_SEL_V << LP_GPIO_REG_GPIO_SIG13_IN_SEL_S) +#define LP_GPIO_REG_GPIO_SIG13_IN_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_SIG13_IN_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC13_IN_SEL : R/W; bitpos: [7:2]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL_M (LP_GPIO_REG_GPIO_FUNC13_IN_SEL_V << LP_GPIO_REG_GPIO_FUNC13_IN_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC13_IN_SEL_S 2 + +/** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xf4) +/** LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC0_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC0_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC0_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC0_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC0_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC0_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad + */ +#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC0_OUT_SEL_S 3 + +/** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xf8) +/** LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC1_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC1_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC1_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC1_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC1_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC1_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC1_OUT_SEL_S 3 + +/** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0xfc) +/** LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC2_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC2_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC2_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC2_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC2_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC2_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC2_OUT_SEL_S 3 + +/** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x100) +/** LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC3_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC3_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC3_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC3_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC3_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC3_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC3_OUT_SEL_S 3 + +/** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x104) +/** LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC4_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC4_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC4_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC4_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC4_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC4_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC4_OUT_SEL_S 3 + +/** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x108) +/** LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC5_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC5_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC5_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC5_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC5_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC5_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC5_OUT_SEL_S 3 + +/** LP_GPIO_FUNC6_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x10c) +/** LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC6_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC6_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC6_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC6_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC6_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC6_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC6_OUT_SEL_S 3 + +/** LP_GPIO_FUNC7_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x110) +/** LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC7_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC7_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC7_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC7_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC7_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC7_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC7_OUT_SEL_S 3 + +/** LP_GPIO_FUNC8_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x114) +/** LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC8_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC8_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC8_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC8_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC8_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC8_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC8_OUT_SEL_S 3 + +/** LP_GPIO_FUNC9_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x118) +/** LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC9_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC9_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC9_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC9_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC9_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC9_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC9_OUT_SEL_S 3 + +/** LP_GPIO_FUNC10_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x11c) +/** LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC10_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC10_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC10_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC10_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC10_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC10_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC10_OUT_SEL_S 3 + +/** LP_GPIO_FUNC11_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x120) +/** LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC11_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC11_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC11_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC11_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC11_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC11_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC11_OUT_SEL_S 3 + +/** LP_GPIO_FUNC12_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x124) +/** LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC12_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC12_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC12_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC12_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC12_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC12_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC12_OUT_SEL_S 3 + +/** LP_GPIO_FUNC13_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x128) +/** LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC13_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC13_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC13_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC13_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC13_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC13_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC13_OUT_SEL_S 3 + +/** LP_GPIO_FUNC14_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x12c) +/** LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC14_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC14_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC14_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC14_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC14_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC14_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC14_OUT_SEL_S 3 + +/** LP_GPIO_FUNC15_OUT_SEL_CFG_REG register + * Reserved + */ +#define LP_GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x130) +/** LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL (BIT(0)) +#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC15_OE_INV_SEL_S 0 +/** LP_GPIO_REG_GPIO_FUNC15_OE_SEL : R/W; bitpos: [1]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL (BIT(1)) +#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL_M (LP_GPIO_REG_GPIO_FUNC15_OE_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OE_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC15_OE_SEL_S 1 +/** LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL (BIT(2)) +#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_M (LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_REG_GPIO_FUNC15_OUT_INV_SEL_S 2 +/** LP_GPIO_REG_GPIO_FUNC15_OUT_SEL : R/W; bitpos: [8:3]; default: 32; + * Reserved + */ +#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_M (LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_V << LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_S) +#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_V 0x0000003FU +#define LP_GPIO_REG_GPIO_FUNC15_OUT_SEL_S 3 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_sig_map.h new file mode 100644 index 0000000000..43e2e8043c --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_sig_map.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define LP_I2C_SCL_PAD_IN_IDX 0 +#define LP_I2C_SCL_PAD_OUT_IDX 0 +#define LP_I2C_SDA_PAD_IN_IDX 1 +#define LP_I2C_SDA_PAD_OUT_IDX 1 +#define LP_UART_RXD_PAD_IN_IDX 2 +#define LP_UART_TXD_PAD_OUT_IDX 2 +#define LP_UART_CTSN_PAD_IN_IDX 3 +#define LP_UART_RTSN_PAD_OUT_IDX 3 +#define LP_UART_DSRN_PAD_IN_IDX 4 +#define LP_UART_DTRN_PAD_OUT_IDX 4 +#define LP_SPI_CK_PAD_IN_IDX 5 +#define LP_SPI_CK_PAD_OUT_IDX 5 +#define LP_SPI_CS_PAD_IN_IDX 6 +#define LP_SPI_CS_PAD_OUT_IDX 6 +#define LP_SPI_D_PAD_IN_IDX 7 +#define LP_SPI_D_PAD_OUT_IDX 7 +#define LP_SPI_Q_PAD_IN_IDX 8 +#define LP_SPI_Q_PAD_OUT_IDX 8 +#define LP_I2S_I_BCK_PAD_IN_IDX 9 +#define LP_I2S_I_BCK_PAD_OUT_IDX 9 +#define LP_I2S_I_SD_PAD_IN_IDX 10 +#define LP_I2S_O_SD_PAD_OUT_IDX 10 +#define LP_I2S_I_WS_PAD_IN_IDX 11 +#define LP_I2S_I_WS_PAD_OUT_IDX 11 +#define LP_I2S_O_BCK_PAD_IN_IDX 12 +#define LP_I2S_O_BCK_PAD_OUT_IDX 12 +#define LP_I2S_O_WS_PAD_IN_IDX 13 +#define LP_I2S_O_WS_PAD_OUT_IDX 13 +#define LP_PROBE_TOP_OUT0_IDX 14 +#define LP_PROBE_TOP_OUT1_IDX 15 +#define LP_PROBE_TOP_OUT2_IDX 16 +#define LP_PROBE_TOP_OUT3_IDX 17 +#define LP_PROBE_TOP_OUT4_IDX 18 +#define LP_PROBE_TOP_OUT5_IDX 19 +#define LP_PROBE_TOP_OUT6_IDX 20 +#define LP_PROBE_TOP_OUT7_IDX 21 +#define LP_PROBE_TOP_OUT8_IDX 22 +#define LP_PROBE_TOP_OUT9_IDX 23 +#define LP_PROBE_TOP_OUT10_IDX 24 +#define LP_PROBE_TOP_OUT11_IDX 25 +#define LP_PROBE_TOP_OUT12_IDX 26 +#define LP_PROBE_TOP_OUT13_IDX 27 +#define LP_PROBE_TOP_OUT14_IDX 28 +#define LP_PROBE_TOP_OUT15_IDX 29 +#define PROBE_CHAIN_CLK_PAD_OUT_IDX 30 +// version date 230323 +#define SIG_GPIO_OUT_IDX 128 diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_struct.h new file mode 100644 index 0000000000..b00dc46894 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_gpio_struct.h @@ -0,0 +1,329 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: clk_en */ +/** Type of clk_en register + * Reserved + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * Reserved + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_gpio_clk_en_reg_t; + + +/** Group: ver_date */ +/** Type of ver_date register + * Reserved + */ +typedef union { + struct { + /** reg_ver_date : R/W; bitpos: [27:0]; default: 2294563; + * Reserved + */ + uint32_t reg_ver_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_gpio_ver_date_reg_t; + + +/** Group: out */ +/** Type of out register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_out_data : R/W/WTC; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_out_data:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_out_reg_t; + + +/** Group: out_w1ts */ +/** Type of out_w1ts register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_out_data_w1ts : WT; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_out_data_w1ts:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_out_w1ts_reg_t; + + +/** Group: out_w1tc */ +/** Type of out_w1tc register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_out_data_w1tc : WT; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_out_data_w1tc:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_out_w1tc_reg_t; + + +/** Group: enable */ +/** Type of enable register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_enable_data : R/W/WTC; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_enable_data:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_enable_reg_t; + + +/** Group: enable_w1ts */ +/** Type of enable_w1ts register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_enable_data_w1ts : WT; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_enable_data_w1ts:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_enable_w1ts_reg_t; + + +/** Group: enable_w1tc */ +/** Type of enable_w1tc register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_enable_data_w1tc : WT; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_enable_data_w1tc:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_enable_w1tc_reg_t; + + +/** Group: status */ +/** Type of status register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_status_data : R/W/WTC; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_status_data:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_status_reg_t; + + +/** Group: status_w1ts */ +/** Type of status_w1ts register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_status_data_w1ts : WT; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_status_data_w1ts:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_status_w1ts_reg_t; + + +/** Group: status_w1tc */ +/** Type of status_w1tc register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_status_data_w1tc : WT; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_status_data_w1tc:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_status_w1tc_reg_t; + + +/** Group: in */ +/** Type of status_next register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_status_interrupt_next : RO; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_status_interrupt_next:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_status_next_reg_t; + +/** Type of in register + * Reserved + */ +typedef union { + struct { + /** reg_gpio_in_data_next : RO; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_gpio_in_data_next:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_gpio_in_reg_t; + + +/** Group: pin */ +/** Type of pin register + * Reserved + */ +typedef union { + struct { + /** wakeup_enable : R/W; bitpos: [0]; default: 0; + * Reserved + */ + uint32_t wakeup_enable:1; + /** int_type : R/W; bitpos: [3:1]; default: 0; + * Reserved + */ + uint32_t int_type:3; + /** pad_driver : R/W; bitpos: [4]; default: 0; + * Reserved + */ + uint32_t pad_driver:1; + /** edge_wakeup_clr : WT; bitpos: [5]; default: 0; + * need des + */ + uint32_t edge_wakeup_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_gpio_pin_reg_t; + + +/** Group: func_in_sel_cfg */ +/** Type of func_in_sel_cfg register + * Reserved + */ +typedef union { + struct { + /** in_inv_sel : R/W; bitpos: [0]; default: 0; + * Reserved + */ + uint32_t in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t sig_in_sel:1; + /** func_in_sel : R/W; bitpos: [7:2]; default: 48 (for func0/1/3/4) 32 (for the rest); + * func_in_sel[5:4]==2'b11 (s=0x30) -> constant 1 + * func_in_sel[5:4]==2'b10 (s=0x20) -> constant 0 + */ + uint32_t func_in_sel:6; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_gpio_func_in_sel_cfg_reg_t; + + +/** Group: func_out_sel_cfg */ +/** Type of func0_out_sel_cfg register + * Reserved + */ +typedef union { + struct { + /** oe_inv_sel : R/W; bitpos: [0]; default: 0; + * Reserved + */ + uint32_t oe_inv_sel:1; + /** oe_sel : R/W; bitpos: [1]; default: 0; + * Reserved + */ + uint32_t oe_sel:1; + /** out_inv_sel : R/W; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t out_inv_sel:1; + /** func_out_sel : R/W; bitpos: [8:3]; default: 32; + * func_out_sel[5:1]==16 (s=32) -> output gpio register value to pad + */ + uint32_t func_out_sel:6; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_gpio_func_out_sel_cfg_reg_t; + + +typedef struct lp_gpio_dev_t { + volatile lp_gpio_clk_en_reg_t clk_en; + volatile lp_gpio_ver_date_reg_t ver_date; + volatile lp_gpio_out_reg_t out; + volatile lp_gpio_out_w1ts_reg_t out_w1ts; + volatile lp_gpio_out_w1tc_reg_t out_w1tc; + volatile lp_gpio_enable_reg_t enable; + volatile lp_gpio_enable_w1ts_reg_t enable_w1ts; + volatile lp_gpio_enable_w1tc_reg_t enable_w1tc; + volatile lp_gpio_status_reg_t status; + volatile lp_gpio_status_w1ts_reg_t status_w1ts; + volatile lp_gpio_status_w1tc_reg_t status_w1tc; + volatile lp_gpio_status_next_reg_t status_next; + volatile lp_gpio_in_reg_t in; + volatile lp_gpio_pin_reg_t pin[16]; + volatile lp_gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[14]; + uint32_t reserved_0ac[18]; + volatile lp_gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[16]; +} lp_gpio_dev_t; + +extern lp_gpio_dev_t LP_GPIO; + + +#ifndef __cplusplus +_Static_assert(sizeof(lp_gpio_dev_t) == 0x134, "Invalid size of lp_gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2c_reg.h new file mode 100644 index 0000000000..e7b75d50a4 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2c_reg.h @@ -0,0 +1,1194 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define I2C_SCL_LOW_PERIOD_S 0 + +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode.1: sample SDA data on the SCL low + * level.0: sample SDA data on the SCL high level. + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. 1: send + * data from the least significant bit,0: send data from the most significant bit. + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data.1: receive data from + * the least significant bit,0: receive data from the most significant bit. + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * synchronization bit + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 + +/** I2C_SR_REG register + * Describe I2C work status. + */ +#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U +#define I2C_RESP_REC_S 0 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ +#define I2C_RXFIFO_CNT 0x0000001FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000001FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; + * This field stores the amount of received data in RAM. + */ +#define I2C_TXFIFO_CNT 0x0000001FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000001FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. 0: Idle, 1: + * Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL.0: Idle, + * 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 + +/** I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APBclock + * cycles. + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU +#define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 + +/** I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ +#define I2C_RXFIFO_RADDR 0x0000000FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000000FU +#define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ +#define I2C_RXFIFO_WADDR 0x0000000FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000000FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ +#define I2C_TXFIFO_RADDR 0x0000000FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000000FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ +#define I2C_TXFIFO_WADDR 0x0000000FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000000FU +#define I2C_TXFIFO_WADDR_S 15 + +/** I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define I2C_RXFIFO_WM_THRHD 0x0000000FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000000FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 + +/** I2C_DATA_REG register + * Rx FIFO read data. + */ +#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) +/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU +#define I2C_FIFO_RDATA_S 0 + +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 + +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 + +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 + +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 + +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negativeedge + * of SCL, in I2C module clock cycles. + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU +#define I2C_SDA_HOLD_TIME_S 0 + +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_S 0 + +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL setup to high level and remains + * high in master mode, in I2C module clock cycles. + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edgeof SDA and the + * negative edge of SCL for a START condition, in I2C module clock cycles. + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_S 0 + +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positiveedge of SCL and the + * negative edge of SDA for a RESTART condition, in I2C module clock cycles. + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition,in I2C module + * clock cycles. + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edgeof SCL and the + * positive edge of SDA, in I2C module clock cycles. + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register valuein I2C + * module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU +#define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register valuein I2C + * module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 + +/** I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) +/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_NUM 0x000000FFU +#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) +#define I2C_SCLK_DIV_NUM_V 0x000000FFU +#define I2C_SCLK_DIV_NUM_S 0 +/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_A 0x0000003FU +#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) +#define I2C_SCLK_DIV_A_V 0x0000003FU +#define I2C_SCLK_DIV_A_S 8 +/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_B 0x0000003FU +#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) +#define I2C_SCLK_DIV_B_V 0x0000003FU +#define I2C_SCLK_DIV_B_S 14 +/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) +#define I2C_SCLK_SEL_V 0x00000001U +#define I2C_SCLK_SEL_S 20 +/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) +#define I2C_SCLK_ACTIVE_V 0x00000001U +#define I2C_SCLK_ACTIVE_S 21 + +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU +#define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to highlevel. + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 + +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU +#define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to highlevel. + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 + +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU +#define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to highLevel. + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 + +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU +#define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to highlevel. + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 + +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU +#define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to highlevel. + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 + +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts:op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU +#define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 + +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU +#define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 + +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU +#define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 + +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 + +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U +#define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 + +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; + * This is the the version register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU +#define I2C_DATE_S 0 + +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) +/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 + +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) +/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_i2c_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2c_struct.h new file mode 100644 index 0000000000..3ccb12bd73 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2c_struct.h @@ -0,0 +1,1027 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negativeedge + * of SCL, in I2C module clock cycles. + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL setup to high level and remains + * high in master mode, in I2C module clock cycles. + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edgeof SDA and the + * negative edge of SCL for a START condition, in I2C module clock cycles. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positiveedge of SCL and the + * negative edge of SDA for a RESTART condition, in I2C module clock cycles. + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition,in I2C module + * clock cycles. + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edgeof SCL and the + * positive edge of SDA, in I2C module clock cycles. + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode.1: sample SDA data on the SCL low + * level.0: sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ + uint32_t rx_full_ack_level:1; + uint32_t reserved_4:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. 1: send + * data from the least significant bit,0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data.1: receive data from + * the least significant bit,0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * synchronization bit + */ + uint32_t conf_upgate:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APBclock + * cycles. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:4; + uint32_t reserved_4:1; + /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:4; + uint32_t reserved_9:1; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + uint32_t reserved_11:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register valuein I2C + * module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register valuein I2C + * module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ + uint32_t resp_rec:1; + uint32_t reserved_1:2; + /** arb_lost : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + */ + uint32_t bus_busy:1; + uint32_t reserved_5:3; + /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_13:5; + /** txfifo_cnt : RO; bitpos: [22:18]; default: 0; + * This field stores the amount of received data in RAM. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_23:1; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. 0: Idle, 1: + * Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL.0: Idle, + * 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ + uint32_t rxfifo_raddr:4; + uint32_t reserved_4:1; + /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ + uint32_t rxfifo_waddr:4; + uint32_t reserved_9:1; + /** txfifo_raddr : RO; bitpos: [13:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ + uint32_t txfifo_raddr:4; + uint32_t reserved_14:1; + /** txfifo_waddr : RO; bitpos: [18:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ + uint32_t txfifo_waddr:4; + uint32_t reserved_19:13; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : RO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd0 register + * I2C command register 0 + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command0:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to highlevel. + */ + uint32_t command0_done:1; + }; + uint32_t val; +} i2c_comd0_reg_t; + +/** Type of comd1 register + * I2C command register 1 + */ +typedef union { + struct { + /** command1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command1:14; + uint32_t reserved_14:17; + /** command1_done : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to highlevel. + */ + uint32_t command1_done:1; + }; + uint32_t val; +} i2c_comd1_reg_t; + +/** Type of comd2 register + * I2C command register 2 + */ +typedef union { + struct { + /** command2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command2:14; + uint32_t reserved_14:17; + /** command2_done : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to highLevel. + */ + uint32_t command2_done:1; + }; + uint32_t val; +} i2c_comd2_reg_t; + +/** Type of comd3 register + * I2C command register 3 + */ +typedef union { + struct { + /** command3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command3:14; + uint32_t reserved_14:17; + /** command3_done : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to highlevel. + */ + uint32_t command3_done:1; + }; + uint32_t val; +} i2c_comd3_reg_t; + +/** Type of comd4 register + * I2C command register 4 + */ +typedef union { + struct { + /** command4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command4:14; + uint32_t reserved_14:17; + /** command4_done : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to highlevel. + */ + uint32_t command4_done:1; + }; + uint32_t val; +} i2c_comd4_reg_t; + +/** Type of comd5 register + * I2C command register 5 + */ +typedef union { + struct { + /** command5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts:op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command5:14; + uint32_t reserved_14:17; + /** command5_done : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command5_done:1; + }; + uint32_t val; +} i2c_comd5_reg_t; + +/** Type of comd6 register + * I2C command register 6 + */ +typedef union { + struct { + /** command6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command6:14; + uint32_t reserved_14:17; + /** command6_done : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command6_done:1; + }; + uint32_t val; +} i2c_comd6_reg_t; + +/** Type of comd7 register + * I2C command register 7 + */ +typedef union { + struct { + /** command7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: op_code is the + * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the + * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are + * used to control the ACK bit. See I2C cmd structure for moreInformation. + */ + uint32_t command7:14; + uint32_t reserved_14:17; + /** command7_done : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command7_done:1; + }; + uint32_t val; +} i2c_comd7_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 37765408; + * This is the the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + uint32_t reserved_010; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + volatile i2c_clk_conf_reg_t clk_conf; + volatile i2c_comd0_reg_t comd0; + volatile i2c_comd1_reg_t comd1; + volatile i2c_comd2_reg_t comd2; + volatile i2c_comd3_reg_t comd3; + volatile i2c_comd4_reg_t comd4; + volatile i2c_comd5_reg_t comd5; + volatile i2c_comd6_reg_t comd6; + volatile i2c_comd7_reg_t comd7; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + uint32_t reserved_084[29]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} i2c_dev_t; + +extern i2c_dev_t LP_I2C; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_reg.h new file mode 100644 index 0000000000..2eeb0b8dbf --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_reg.h @@ -0,0 +1,1057 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2S_VAD_CONF_REG register + * I2S VAD Configure register + */ +#define LP_I2S_VAD_CONF_REG (DR_REG_LP_I2S_BASE + 0x0) +/** LP_I2S_VAD_EN : R/W; bitpos: [0]; default: 0; + * VAD enable register + */ +#define LP_I2S_VAD_EN (BIT(0)) +#define LP_I2S_VAD_EN_M (LP_I2S_VAD_EN_V << LP_I2S_VAD_EN_S) +#define LP_I2S_VAD_EN_V 0x00000001U +#define LP_I2S_VAD_EN_S 0 +/** LP_I2S_VAD_RESET : WT; bitpos: [1]; default: 0; + * VAD reset register + */ +#define LP_I2S_VAD_RESET (BIT(1)) +#define LP_I2S_VAD_RESET_M (LP_I2S_VAD_RESET_V << LP_I2S_VAD_RESET_S) +#define LP_I2S_VAD_RESET_V 0x00000001U +#define LP_I2S_VAD_RESET_S 1 +/** LP_I2S_VAD_FORCE_START : WT; bitpos: [2]; default: 0; + * VAD force start register. + */ +#define LP_I2S_VAD_FORCE_START (BIT(2)) +#define LP_I2S_VAD_FORCE_START_M (LP_I2S_VAD_FORCE_START_V << LP_I2S_VAD_FORCE_START_S) +#define LP_I2S_VAD_FORCE_START_V 0x00000001U +#define LP_I2S_VAD_FORCE_START_S 2 + +/** LP_I2S_VAD_RESULT_REG register + * I2S VAD Result register + */ +#define LP_I2S_VAD_RESULT_REG (DR_REG_LP_I2S_BASE + 0x4) +/** LP_I2S_VAD_FLAG : RO; bitpos: [0]; default: 0; + * Reg vad flag observe signal + */ +#define LP_I2S_VAD_FLAG (BIT(0)) +#define LP_I2S_VAD_FLAG_M (LP_I2S_VAD_FLAG_V << LP_I2S_VAD_FLAG_S) +#define LP_I2S_VAD_FLAG_V 0x00000001U +#define LP_I2S_VAD_FLAG_S 0 +/** LP_I2S_ENERGY_ENOUGH : RO; bitpos: [1]; default: 0; + * Reg energy enough observe signal + */ +#define LP_I2S_ENERGY_ENOUGH (BIT(1)) +#define LP_I2S_ENERGY_ENOUGH_M (LP_I2S_ENERGY_ENOUGH_V << LP_I2S_ENERGY_ENOUGH_S) +#define LP_I2S_ENERGY_ENOUGH_V 0x00000001U +#define LP_I2S_ENERGY_ENOUGH_S 1 + +/** LP_I2S_RX_MEM_CONF_REG register + * I2S VAD Observe register + */ +#define LP_I2S_RX_MEM_CONF_REG (DR_REG_LP_I2S_BASE + 0x8) +/** LP_I2S_RX_MEM_FIFO_CNT : RO; bitpos: [8:0]; default: 0; + * The number of data in the rx mem + */ +#define LP_I2S_RX_MEM_FIFO_CNT 0x000001FFU +#define LP_I2S_RX_MEM_FIFO_CNT_M (LP_I2S_RX_MEM_FIFO_CNT_V << LP_I2S_RX_MEM_FIFO_CNT_S) +#define LP_I2S_RX_MEM_FIFO_CNT_V 0x000001FFU +#define LP_I2S_RX_MEM_FIFO_CNT_S 0 +/** LP_I2S_RX_MEM_THRESHOLD : R/W; bitpos: [16:9]; default: 63; + * I2S rx mem will trigger an interrupt when the data in the mem is over(not including + * equal) reg_rx_mem_threshold + */ +#define LP_I2S_RX_MEM_THRESHOLD 0x000000FFU +#define LP_I2S_RX_MEM_THRESHOLD_M (LP_I2S_RX_MEM_THRESHOLD_V << LP_I2S_RX_MEM_THRESHOLD_S) +#define LP_I2S_RX_MEM_THRESHOLD_V 0x000000FFU +#define LP_I2S_RX_MEM_THRESHOLD_S 9 + +/** LP_I2S_INT_RAW_REG register + * I2S interrupt raw register, valid in level. + */ +#define LP_I2S_INT_RAW_REG (DR_REG_LP_I2S_BASE + 0xc) +/** LP_I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ +#define LP_I2S_RX_DONE_INT_RAW (BIT(0)) +#define LP_I2S_RX_DONE_INT_RAW_M (LP_I2S_RX_DONE_INT_RAW_V << LP_I2S_RX_DONE_INT_RAW_S) +#define LP_I2S_RX_DONE_INT_RAW_V 0x00000001U +#define LP_I2S_RX_DONE_INT_RAW_S 0 +/** LP_I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define LP_I2S_RX_HUNG_INT_RAW (BIT(1)) +#define LP_I2S_RX_HUNG_INT_RAW_M (LP_I2S_RX_HUNG_INT_RAW_V << LP_I2S_RX_HUNG_INT_RAW_S) +#define LP_I2S_RX_HUNG_INT_RAW_V 0x00000001U +#define LP_I2S_RX_HUNG_INT_RAW_S 1 +/** LP_I2S_RX_FIFOMEM_UDF_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + */ +#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW (BIT(2)) +#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW_M (LP_I2S_RX_FIFOMEM_UDF_INT_RAW_V << LP_I2S_RX_FIFOMEM_UDF_INT_RAW_S) +#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW_V 0x00000001U +#define LP_I2S_RX_FIFOMEM_UDF_INT_RAW_S 2 +/** LP_I2S_VAD_DONE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the vad_done_int interrupt + */ +#define LP_I2S_VAD_DONE_INT_RAW (BIT(3)) +#define LP_I2S_VAD_DONE_INT_RAW_M (LP_I2S_VAD_DONE_INT_RAW_V << LP_I2S_VAD_DONE_INT_RAW_S) +#define LP_I2S_VAD_DONE_INT_RAW_V 0x00000001U +#define LP_I2S_VAD_DONE_INT_RAW_S 3 +/** LP_I2S_VAD_RESET_DONE_INT_RAW : RO/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status bit for the vad_reset_done_int interrupt + */ +#define LP_I2S_VAD_RESET_DONE_INT_RAW (BIT(4)) +#define LP_I2S_VAD_RESET_DONE_INT_RAW_M (LP_I2S_VAD_RESET_DONE_INT_RAW_V << LP_I2S_VAD_RESET_DONE_INT_RAW_S) +#define LP_I2S_VAD_RESET_DONE_INT_RAW_V 0x00000001U +#define LP_I2S_VAD_RESET_DONE_INT_RAW_S 4 +/** LP_I2S_RX_MEM_THRESHOLD_INT_RAW : RO/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status bit for the rx_mem_threshold_int interrupt + */ +#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW (BIT(5)) +#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW_M (LP_I2S_RX_MEM_THRESHOLD_INT_RAW_V << LP_I2S_RX_MEM_THRESHOLD_INT_RAW_S) +#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW_V 0x00000001U +#define LP_I2S_RX_MEM_THRESHOLD_INT_RAW_S 5 + +/** LP_I2S_INT_ST_REG register + * I2S interrupt status register. + */ +#define LP_I2S_INT_ST_REG (DR_REG_LP_I2S_BASE + 0x10) +/** LP_I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ +#define LP_I2S_RX_DONE_INT_ST (BIT(0)) +#define LP_I2S_RX_DONE_INT_ST_M (LP_I2S_RX_DONE_INT_ST_V << LP_I2S_RX_DONE_INT_ST_S) +#define LP_I2S_RX_DONE_INT_ST_V 0x00000001U +#define LP_I2S_RX_DONE_INT_ST_S 0 +/** LP_I2S_RX_HUNG_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ +#define LP_I2S_RX_HUNG_INT_ST (BIT(1)) +#define LP_I2S_RX_HUNG_INT_ST_M (LP_I2S_RX_HUNG_INT_ST_V << LP_I2S_RX_HUNG_INT_ST_S) +#define LP_I2S_RX_HUNG_INT_ST_V 0x00000001U +#define LP_I2S_RX_HUNG_INT_ST_S 1 +/** LP_I2S_RX_FIFOMEM_UDF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + */ +#define LP_I2S_RX_FIFOMEM_UDF_INT_ST (BIT(2)) +#define LP_I2S_RX_FIFOMEM_UDF_INT_ST_M (LP_I2S_RX_FIFOMEM_UDF_INT_ST_V << LP_I2S_RX_FIFOMEM_UDF_INT_ST_S) +#define LP_I2S_RX_FIFOMEM_UDF_INT_ST_V 0x00000001U +#define LP_I2S_RX_FIFOMEM_UDF_INT_ST_S 2 +/** LP_I2S_VAD_DONE_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the vad_done_int interrupt + */ +#define LP_I2S_VAD_DONE_INT_ST (BIT(3)) +#define LP_I2S_VAD_DONE_INT_ST_M (LP_I2S_VAD_DONE_INT_ST_V << LP_I2S_VAD_DONE_INT_ST_S) +#define LP_I2S_VAD_DONE_INT_ST_V 0x00000001U +#define LP_I2S_VAD_DONE_INT_ST_S 3 +/** LP_I2S_VAD_RESET_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the vad_reset_done_int interrupt + */ +#define LP_I2S_VAD_RESET_DONE_INT_ST (BIT(4)) +#define LP_I2S_VAD_RESET_DONE_INT_ST_M (LP_I2S_VAD_RESET_DONE_INT_ST_V << LP_I2S_VAD_RESET_DONE_INT_ST_S) +#define LP_I2S_VAD_RESET_DONE_INT_ST_V 0x00000001U +#define LP_I2S_VAD_RESET_DONE_INT_ST_S 4 +/** LP_I2S_RX_MEM_THRESHOLD_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the rx_mem_threshold_int interrupt + */ +#define LP_I2S_RX_MEM_THRESHOLD_INT_ST (BIT(5)) +#define LP_I2S_RX_MEM_THRESHOLD_INT_ST_M (LP_I2S_RX_MEM_THRESHOLD_INT_ST_V << LP_I2S_RX_MEM_THRESHOLD_INT_ST_S) +#define LP_I2S_RX_MEM_THRESHOLD_INT_ST_V 0x00000001U +#define LP_I2S_RX_MEM_THRESHOLD_INT_ST_S 5 + +/** LP_I2S_INT_ENA_REG register + * I2S interrupt enable register. + */ +#define LP_I2S_INT_ENA_REG (DR_REG_LP_I2S_BASE + 0x14) +/** LP_I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ +#define LP_I2S_RX_DONE_INT_ENA (BIT(0)) +#define LP_I2S_RX_DONE_INT_ENA_M (LP_I2S_RX_DONE_INT_ENA_V << LP_I2S_RX_DONE_INT_ENA_S) +#define LP_I2S_RX_DONE_INT_ENA_V 0x00000001U +#define LP_I2S_RX_DONE_INT_ENA_S 0 +/** LP_I2S_RX_HUNG_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ +#define LP_I2S_RX_HUNG_INT_ENA (BIT(1)) +#define LP_I2S_RX_HUNG_INT_ENA_M (LP_I2S_RX_HUNG_INT_ENA_V << LP_I2S_RX_HUNG_INT_ENA_S) +#define LP_I2S_RX_HUNG_INT_ENA_V 0x00000001U +#define LP_I2S_RX_HUNG_INT_ENA_S 1 +/** LP_I2S_RX_FIFOMEM_UDF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt + */ +#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA (BIT(2)) +#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA_M (LP_I2S_RX_FIFOMEM_UDF_INT_ENA_V << LP_I2S_RX_FIFOMEM_UDF_INT_ENA_S) +#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA_V 0x00000001U +#define LP_I2S_RX_FIFOMEM_UDF_INT_ENA_S 2 +/** LP_I2S_VAD_DONE_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the vad_done_int interrupt + */ +#define LP_I2S_VAD_DONE_INT_ENA (BIT(3)) +#define LP_I2S_VAD_DONE_INT_ENA_M (LP_I2S_VAD_DONE_INT_ENA_V << LP_I2S_VAD_DONE_INT_ENA_S) +#define LP_I2S_VAD_DONE_INT_ENA_V 0x00000001U +#define LP_I2S_VAD_DONE_INT_ENA_S 3 +/** LP_I2S_VAD_RESET_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the vad_reset_done_int interrupt + */ +#define LP_I2S_VAD_RESET_DONE_INT_ENA (BIT(4)) +#define LP_I2S_VAD_RESET_DONE_INT_ENA_M (LP_I2S_VAD_RESET_DONE_INT_ENA_V << LP_I2S_VAD_RESET_DONE_INT_ENA_S) +#define LP_I2S_VAD_RESET_DONE_INT_ENA_V 0x00000001U +#define LP_I2S_VAD_RESET_DONE_INT_ENA_S 4 +/** LP_I2S_RX_MEM_THRESHOLD_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the rx_mem_threshold_int interrupt + */ +#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA (BIT(5)) +#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA_M (LP_I2S_RX_MEM_THRESHOLD_INT_ENA_V << LP_I2S_RX_MEM_THRESHOLD_INT_ENA_S) +#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA_V 0x00000001U +#define LP_I2S_RX_MEM_THRESHOLD_INT_ENA_S 5 + +/** LP_I2S_INT_CLR_REG register + * I2S interrupt clear register. + */ +#define LP_I2S_INT_CLR_REG (DR_REG_LP_I2S_BASE + 0x18) +/** LP_I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ +#define LP_I2S_RX_DONE_INT_CLR (BIT(0)) +#define LP_I2S_RX_DONE_INT_CLR_M (LP_I2S_RX_DONE_INT_CLR_V << LP_I2S_RX_DONE_INT_CLR_S) +#define LP_I2S_RX_DONE_INT_CLR_V 0x00000001U +#define LP_I2S_RX_DONE_INT_CLR_S 0 +/** LP_I2S_RX_HUNG_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ +#define LP_I2S_RX_HUNG_INT_CLR (BIT(1)) +#define LP_I2S_RX_HUNG_INT_CLR_M (LP_I2S_RX_HUNG_INT_CLR_V << LP_I2S_RX_HUNG_INT_CLR_S) +#define LP_I2S_RX_HUNG_INT_CLR_V 0x00000001U +#define LP_I2S_RX_HUNG_INT_CLR_S 1 +/** LP_I2S_RX_FIFOMEM_UDF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_fifomem_udf_int interrupt + */ +#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR (BIT(2)) +#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR_M (LP_I2S_RX_FIFOMEM_UDF_INT_CLR_V << LP_I2S_RX_FIFOMEM_UDF_INT_CLR_S) +#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR_V 0x00000001U +#define LP_I2S_RX_FIFOMEM_UDF_INT_CLR_S 2 +/** LP_I2S_VAD_DONE_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the vad_done_int interrupt + */ +#define LP_I2S_VAD_DONE_INT_CLR (BIT(3)) +#define LP_I2S_VAD_DONE_INT_CLR_M (LP_I2S_VAD_DONE_INT_CLR_V << LP_I2S_VAD_DONE_INT_CLR_S) +#define LP_I2S_VAD_DONE_INT_CLR_V 0x00000001U +#define LP_I2S_VAD_DONE_INT_CLR_S 3 +/** LP_I2S_VAD_RESET_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the vad_reset_done_int interrupt + */ +#define LP_I2S_VAD_RESET_DONE_INT_CLR (BIT(4)) +#define LP_I2S_VAD_RESET_DONE_INT_CLR_M (LP_I2S_VAD_RESET_DONE_INT_CLR_V << LP_I2S_VAD_RESET_DONE_INT_CLR_S) +#define LP_I2S_VAD_RESET_DONE_INT_CLR_V 0x00000001U +#define LP_I2S_VAD_RESET_DONE_INT_CLR_S 4 +/** LP_I2S_RX_MEM_THRESHOLD_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the rx_mem_threshold_int interrupt + */ +#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR (BIT(5)) +#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR_M (LP_I2S_RX_MEM_THRESHOLD_INT_CLR_V << LP_I2S_RX_MEM_THRESHOLD_INT_CLR_S) +#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR_V 0x00000001U +#define LP_I2S_RX_MEM_THRESHOLD_INT_CLR_S 5 + +/** LP_I2S_RX_CONF_REG register + * I2S RX configure register + */ +#define LP_I2S_RX_CONF_REG (DR_REG_LP_I2S_BASE + 0x20) +/** LP_I2S_RX_RESET : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ +#define LP_I2S_RX_RESET (BIT(0)) +#define LP_I2S_RX_RESET_M (LP_I2S_RX_RESET_V << LP_I2S_RX_RESET_S) +#define LP_I2S_RX_RESET_V 0x00000001U +#define LP_I2S_RX_RESET_S 0 +/** LP_I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ +#define LP_I2S_RX_FIFO_RESET (BIT(1)) +#define LP_I2S_RX_FIFO_RESET_M (LP_I2S_RX_FIFO_RESET_V << LP_I2S_RX_FIFO_RESET_S) +#define LP_I2S_RX_FIFO_RESET_V 0x00000001U +#define LP_I2S_RX_FIFO_RESET_S 1 +/** LP_I2S_RX_START : R/W; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ +#define LP_I2S_RX_START (BIT(2)) +#define LP_I2S_RX_START_M (LP_I2S_RX_START_V << LP_I2S_RX_START_S) +#define LP_I2S_RX_START_V 0x00000001U +#define LP_I2S_RX_START_S 2 +/** LP_I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ +#define LP_I2S_RX_SLAVE_MOD (BIT(3)) +#define LP_I2S_RX_SLAVE_MOD_M (LP_I2S_RX_SLAVE_MOD_V << LP_I2S_RX_SLAVE_MOD_S) +#define LP_I2S_RX_SLAVE_MOD_V 0x00000001U +#define LP_I2S_RX_SLAVE_MOD_S 3 +/** LP_I2S_RX_FIFOMEM_RESET : WT; bitpos: [4]; default: 0; + * Set this bit to reset Rx Syncfifomem + */ +#define LP_I2S_RX_FIFOMEM_RESET (BIT(4)) +#define LP_I2S_RX_FIFOMEM_RESET_M (LP_I2S_RX_FIFOMEM_RESET_V << LP_I2S_RX_FIFOMEM_RESET_S) +#define LP_I2S_RX_FIFOMEM_RESET_V 0x00000001U +#define LP_I2S_RX_FIFOMEM_RESET_S 4 +/** LP_I2S_RX_MONO : R/W; bitpos: [5]; default: 0; + * Set this bit to enable receiver in mono mode + */ +#define LP_I2S_RX_MONO (BIT(5)) +#define LP_I2S_RX_MONO_M (LP_I2S_RX_MONO_V << LP_I2S_RX_MONO_S) +#define LP_I2S_RX_MONO_V 0x00000001U +#define LP_I2S_RX_MONO_S 5 +/** LP_I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ +#define LP_I2S_RX_BIG_ENDIAN (BIT(7)) +#define LP_I2S_RX_BIG_ENDIAN_M (LP_I2S_RX_BIG_ENDIAN_V << LP_I2S_RX_BIG_ENDIAN_S) +#define LP_I2S_RX_BIG_ENDIAN_V 0x00000001U +#define LP_I2S_RX_BIG_ENDIAN_S 7 +/** LP_I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ +#define LP_I2S_RX_UPDATE (BIT(8)) +#define LP_I2S_RX_UPDATE_M (LP_I2S_RX_UPDATE_V << LP_I2S_RX_UPDATE_S) +#define LP_I2S_RX_UPDATE_V 0x00000001U +#define LP_I2S_RX_UPDATE_S 8 +/** LP_I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ +#define LP_I2S_RX_MONO_FST_VLD (BIT(9)) +#define LP_I2S_RX_MONO_FST_VLD_M (LP_I2S_RX_MONO_FST_VLD_V << LP_I2S_RX_MONO_FST_VLD_S) +#define LP_I2S_RX_MONO_FST_VLD_V 0x00000001U +#define LP_I2S_RX_MONO_FST_VLD_S 9 +/** LP_I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ +#define LP_I2S_RX_PCM_CONF 0x00000003U +#define LP_I2S_RX_PCM_CONF_M (LP_I2S_RX_PCM_CONF_V << LP_I2S_RX_PCM_CONF_S) +#define LP_I2S_RX_PCM_CONF_V 0x00000003U +#define LP_I2S_RX_PCM_CONF_S 10 +/** LP_I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ +#define LP_I2S_RX_PCM_BYPASS (BIT(12)) +#define LP_I2S_RX_PCM_BYPASS_M (LP_I2S_RX_PCM_BYPASS_V << LP_I2S_RX_PCM_BYPASS_S) +#define LP_I2S_RX_PCM_BYPASS_V 0x00000001U +#define LP_I2S_RX_PCM_BYPASS_S 12 +/** LP_I2S_RX_STOP_MODE : R/W; bitpos: [14:13]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ +#define LP_I2S_RX_STOP_MODE 0x00000003U +#define LP_I2S_RX_STOP_MODE_M (LP_I2S_RX_STOP_MODE_V << LP_I2S_RX_STOP_MODE_S) +#define LP_I2S_RX_STOP_MODE_V 0x00000003U +#define LP_I2S_RX_STOP_MODE_S 13 +/** LP_I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ +#define LP_I2S_RX_LEFT_ALIGN (BIT(15)) +#define LP_I2S_RX_LEFT_ALIGN_M (LP_I2S_RX_LEFT_ALIGN_V << LP_I2S_RX_LEFT_ALIGN_S) +#define LP_I2S_RX_LEFT_ALIGN_V 0x00000001U +#define LP_I2S_RX_LEFT_ALIGN_S 15 +/** LP_I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ +#define LP_I2S_RX_24_FILL_EN (BIT(16)) +#define LP_I2S_RX_24_FILL_EN_M (LP_I2S_RX_24_FILL_EN_V << LP_I2S_RX_24_FILL_EN_S) +#define LP_I2S_RX_24_FILL_EN_V 0x00000001U +#define LP_I2S_RX_24_FILL_EN_S 16 +/** LP_I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ +#define LP_I2S_RX_WS_IDLE_POL (BIT(17)) +#define LP_I2S_RX_WS_IDLE_POL_M (LP_I2S_RX_WS_IDLE_POL_V << LP_I2S_RX_WS_IDLE_POL_S) +#define LP_I2S_RX_WS_IDLE_POL_V 0x00000001U +#define LP_I2S_RX_WS_IDLE_POL_S 17 +/** LP_I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ +#define LP_I2S_RX_BIT_ORDER (BIT(18)) +#define LP_I2S_RX_BIT_ORDER_M (LP_I2S_RX_BIT_ORDER_V << LP_I2S_RX_BIT_ORDER_S) +#define LP_I2S_RX_BIT_ORDER_V 0x00000001U +#define LP_I2S_RX_BIT_ORDER_S 18 +/** LP_I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ +#define LP_I2S_RX_TDM_EN (BIT(19)) +#define LP_I2S_RX_TDM_EN_M (LP_I2S_RX_TDM_EN_V << LP_I2S_RX_TDM_EN_S) +#define LP_I2S_RX_TDM_EN_V 0x00000001U +#define LP_I2S_RX_TDM_EN_S 19 +/** LP_I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ +#define LP_I2S_RX_PDM_EN (BIT(20)) +#define LP_I2S_RX_PDM_EN_M (LP_I2S_RX_PDM_EN_V << LP_I2S_RX_PDM_EN_S) +#define LP_I2S_RX_PDM_EN_V 0x00000001U +#define LP_I2S_RX_PDM_EN_S 20 + +/** LP_I2S_RX_CONF1_REG register + * I2S RX configure register 1 + */ +#define LP_I2S_RX_CONF1_REG (DR_REG_LP_I2S_BASE + 0x28) +/** LP_I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0; + * The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + */ +#define LP_I2S_RX_TDM_WS_WIDTH 0x0000007FU +#define LP_I2S_RX_TDM_WS_WIDTH_M (LP_I2S_RX_TDM_WS_WIDTH_V << LP_I2S_RX_TDM_WS_WIDTH_S) +#define LP_I2S_RX_TDM_WS_WIDTH_V 0x0000007FU +#define LP_I2S_RX_TDM_WS_WIDTH_S 0 +/** LP_I2S_RX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6; + * Bit clock configuration bits in receiver mode. + */ +#define LP_I2S_RX_BCK_DIV_NUM 0x0000003FU +#define LP_I2S_RX_BCK_DIV_NUM_M (LP_I2S_RX_BCK_DIV_NUM_V << LP_I2S_RX_BCK_DIV_NUM_S) +#define LP_I2S_RX_BCK_DIV_NUM_V 0x0000003FU +#define LP_I2S_RX_BCK_DIV_NUM_S 7 +/** LP_I2S_RX_BITS_MOD : R/W; bitpos: [17:13]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ +#define LP_I2S_RX_BITS_MOD 0x0000001FU +#define LP_I2S_RX_BITS_MOD_M (LP_I2S_RX_BITS_MOD_V << LP_I2S_RX_BITS_MOD_S) +#define LP_I2S_RX_BITS_MOD_V 0x0000001FU +#define LP_I2S_RX_BITS_MOD_S 13 +/** LP_I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15; + * I2S Rx half sample bits -1. + */ +#define LP_I2S_RX_HALF_SAMPLE_BITS 0x0000003FU +#define LP_I2S_RX_HALF_SAMPLE_BITS_M (LP_I2S_RX_HALF_SAMPLE_BITS_V << LP_I2S_RX_HALF_SAMPLE_BITS_S) +#define LP_I2S_RX_HALF_SAMPLE_BITS_V 0x0000003FU +#define LP_I2S_RX_HALF_SAMPLE_BITS_S 18 +/** LP_I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ +#define LP_I2S_RX_TDM_CHAN_BITS 0x0000001FU +#define LP_I2S_RX_TDM_CHAN_BITS_M (LP_I2S_RX_TDM_CHAN_BITS_V << LP_I2S_RX_TDM_CHAN_BITS_S) +#define LP_I2S_RX_TDM_CHAN_BITS_V 0x0000001FU +#define LP_I2S_RX_TDM_CHAN_BITS_S 24 +/** LP_I2S_RX_MSB_SHIFT : R/W; bitpos: [29]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ +#define LP_I2S_RX_MSB_SHIFT (BIT(29)) +#define LP_I2S_RX_MSB_SHIFT_M (LP_I2S_RX_MSB_SHIFT_V << LP_I2S_RX_MSB_SHIFT_S) +#define LP_I2S_RX_MSB_SHIFT_V 0x00000001U +#define LP_I2S_RX_MSB_SHIFT_S 29 + +/** LP_I2S_RX_TDM_CTRL_REG register + * I2S TX TDM mode control register + */ +#define LP_I2S_RX_TDM_CTRL_REG (DR_REG_LP_I2S_BASE + 0x50) +/** LP_I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define LP_I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define LP_I2S_RX_TDM_PDM_CHAN0_EN_M (LP_I2S_RX_TDM_PDM_CHAN0_EN_V << LP_I2S_RX_TDM_PDM_CHAN0_EN_S) +#define LP_I2S_RX_TDM_PDM_CHAN0_EN_V 0x00000001U +#define LP_I2S_RX_TDM_PDM_CHAN0_EN_S 0 +/** LP_I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ +#define LP_I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define LP_I2S_RX_TDM_PDM_CHAN1_EN_M (LP_I2S_RX_TDM_PDM_CHAN1_EN_V << LP_I2S_RX_TDM_PDM_CHAN1_EN_S) +#define LP_I2S_RX_TDM_PDM_CHAN1_EN_V 0x00000001U +#define LP_I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/** LP_I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ +#define LP_I2S_RX_TDM_TOT_CHAN_NUM 0x0000000FU +#define LP_I2S_RX_TDM_TOT_CHAN_NUM_M (LP_I2S_RX_TDM_TOT_CHAN_NUM_V << LP_I2S_RX_TDM_TOT_CHAN_NUM_S) +#define LP_I2S_RX_TDM_TOT_CHAN_NUM_V 0x0000000FU +#define LP_I2S_RX_TDM_TOT_CHAN_NUM_S 16 + +/** LP_I2S_RX_TIMING_REG register + * I2S RX timing control register + */ +#define LP_I2S_RX_TIMING_REG (DR_REG_LP_I2S_BASE + 0x58) +/** LP_I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define LP_I2S_RX_SD_IN_DM 0x00000003U +#define LP_I2S_RX_SD_IN_DM_M (LP_I2S_RX_SD_IN_DM_V << LP_I2S_RX_SD_IN_DM_S) +#define LP_I2S_RX_SD_IN_DM_V 0x00000003U +#define LP_I2S_RX_SD_IN_DM_S 0 +/** LP_I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define LP_I2S_RX_WS_OUT_DM 0x00000003U +#define LP_I2S_RX_WS_OUT_DM_M (LP_I2S_RX_WS_OUT_DM_V << LP_I2S_RX_WS_OUT_DM_S) +#define LP_I2S_RX_WS_OUT_DM_V 0x00000003U +#define LP_I2S_RX_WS_OUT_DM_S 16 +/** LP_I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define LP_I2S_RX_BCK_OUT_DM 0x00000003U +#define LP_I2S_RX_BCK_OUT_DM_M (LP_I2S_RX_BCK_OUT_DM_V << LP_I2S_RX_BCK_OUT_DM_S) +#define LP_I2S_RX_BCK_OUT_DM_V 0x00000003U +#define LP_I2S_RX_BCK_OUT_DM_S 20 +/** LP_I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define LP_I2S_RX_WS_IN_DM 0x00000003U +#define LP_I2S_RX_WS_IN_DM_M (LP_I2S_RX_WS_IN_DM_V << LP_I2S_RX_WS_IN_DM_S) +#define LP_I2S_RX_WS_IN_DM_V 0x00000003U +#define LP_I2S_RX_WS_IN_DM_S 24 +/** LP_I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ +#define LP_I2S_RX_BCK_IN_DM 0x00000003U +#define LP_I2S_RX_BCK_IN_DM_M (LP_I2S_RX_BCK_IN_DM_V << LP_I2S_RX_BCK_IN_DM_S) +#define LP_I2S_RX_BCK_IN_DM_V 0x00000003U +#define LP_I2S_RX_BCK_IN_DM_S 28 + +/** LP_I2S_LC_HUNG_CONF_REG register + * I2S HUNG configure register. + */ +#define LP_I2S_LC_HUNG_CONF_REG (DR_REG_LP_I2S_BASE + 0x60) +/** LP_I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ +#define LP_I2S_LC_FIFO_TIMEOUT 0x000000FFU +#define LP_I2S_LC_FIFO_TIMEOUT_M (LP_I2S_LC_FIFO_TIMEOUT_V << LP_I2S_LC_FIFO_TIMEOUT_S) +#define LP_I2S_LC_FIFO_TIMEOUT_V 0x000000FFU +#define LP_I2S_LC_FIFO_TIMEOUT_S 0 +/** LP_I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ +#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007U +#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT_M (LP_I2S_LC_FIFO_TIMEOUT_SHIFT_V << LP_I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007U +#define LP_I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/** LP_I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ +#define LP_I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define LP_I2S_LC_FIFO_TIMEOUT_ENA_M (LP_I2S_LC_FIFO_TIMEOUT_ENA_V << LP_I2S_LC_FIFO_TIMEOUT_ENA_S) +#define LP_I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U +#define LP_I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/** LP_I2S_RXEOF_NUM_REG register + * I2S RX data number control register. + */ +#define LP_I2S_RXEOF_NUM_REG (DR_REG_LP_I2S_BASE + 0x64) +/** LP_I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ +#define LP_I2S_RX_EOF_NUM 0x00000FFFU +#define LP_I2S_RX_EOF_NUM_M (LP_I2S_RX_EOF_NUM_V << LP_I2S_RX_EOF_NUM_S) +#define LP_I2S_RX_EOF_NUM_V 0x00000FFFU +#define LP_I2S_RX_EOF_NUM_S 0 + +/** LP_I2S_CONF_SIGLE_DATA_REG register + * I2S signal data register + */ +#define LP_I2S_CONF_SIGLE_DATA_REG (DR_REG_LP_I2S_BASE + 0x68) +/** LP_I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ +#define LP_I2S_SINGLE_DATA 0xFFFFFFFFU +#define LP_I2S_SINGLE_DATA_M (LP_I2S_SINGLE_DATA_V << LP_I2S_SINGLE_DATA_S) +#define LP_I2S_SINGLE_DATA_V 0xFFFFFFFFU +#define LP_I2S_SINGLE_DATA_S 0 + +/** LP_I2S_RX_PDM_CONF_REG register + * I2S RX configure register + */ +#define LP_I2S_RX_PDM_CONF_REG (DR_REG_LP_I2S_BASE + 0x70) +/** LP_I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ +#define LP_I2S_RX_PDM2PCM_EN (BIT(19)) +#define LP_I2S_RX_PDM2PCM_EN_M (LP_I2S_RX_PDM2PCM_EN_V << LP_I2S_RX_PDM2PCM_EN_S) +#define LP_I2S_RX_PDM2PCM_EN_V 0x00000001U +#define LP_I2S_RX_PDM2PCM_EN_S 19 +/** LP_I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ +#define LP_I2S_RX_PDM_SINC_DSR_16_EN (BIT(20)) +#define LP_I2S_RX_PDM_SINC_DSR_16_EN_M (LP_I2S_RX_PDM_SINC_DSR_16_EN_V << LP_I2S_RX_PDM_SINC_DSR_16_EN_S) +#define LP_I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U +#define LP_I2S_RX_PDM_SINC_DSR_16_EN_S 20 +/** LP_I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ +#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU +#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_M (LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_V << LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_S) +#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU +#define LP_I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21 +/** LP_I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ +#define LP_I2S_RX_PDM_HP_BYPASS (BIT(25)) +#define LP_I2S_RX_PDM_HP_BYPASS_M (LP_I2S_RX_PDM_HP_BYPASS_V << LP_I2S_RX_PDM_HP_BYPASS_S) +#define LP_I2S_RX_PDM_HP_BYPASS_V 0x00000001U +#define LP_I2S_RX_PDM_HP_BYPASS_S 25 +/** LP_I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ +#define LP_I2S_RX_IIR_HP_MULT12_5 0x00000007U +#define LP_I2S_RX_IIR_HP_MULT12_5_M (LP_I2S_RX_IIR_HP_MULT12_5_V << LP_I2S_RX_IIR_HP_MULT12_5_S) +#define LP_I2S_RX_IIR_HP_MULT12_5_V 0x00000007U +#define LP_I2S_RX_IIR_HP_MULT12_5_S 26 +/** LP_I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ +#define LP_I2S_RX_IIR_HP_MULT12_0 0x00000007U +#define LP_I2S_RX_IIR_HP_MULT12_0_M (LP_I2S_RX_IIR_HP_MULT12_0_V << LP_I2S_RX_IIR_HP_MULT12_0_S) +#define LP_I2S_RX_IIR_HP_MULT12_0_V 0x00000007U +#define LP_I2S_RX_IIR_HP_MULT12_0_S 29 + +/** LP_I2S_ECO_LOW_REG register + * I2S ECO register + */ +#define LP_I2S_ECO_LOW_REG (DR_REG_LP_I2S_BASE + 0x74) +/** LP_I2S_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * logic low eco registers + */ +#define LP_I2S_RDN_ECO_LOW 0xFFFFFFFFU +#define LP_I2S_RDN_ECO_LOW_M (LP_I2S_RDN_ECO_LOW_V << LP_I2S_RDN_ECO_LOW_S) +#define LP_I2S_RDN_ECO_LOW_V 0xFFFFFFFFU +#define LP_I2S_RDN_ECO_LOW_S 0 + +/** LP_I2S_ECO_HIGH_REG register + * I2S ECO register + */ +#define LP_I2S_ECO_HIGH_REG (DR_REG_LP_I2S_BASE + 0x78) +/** LP_I2S_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * logic high eco registers + */ +#define LP_I2S_RDN_ECO_HIGH 0xFFFFFFFFU +#define LP_I2S_RDN_ECO_HIGH_M (LP_I2S_RDN_ECO_HIGH_V << LP_I2S_RDN_ECO_HIGH_S) +#define LP_I2S_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define LP_I2S_RDN_ECO_HIGH_S 0 + +/** LP_I2S_ECO_CONF_REG register + * I2S ECO register + */ +#define LP_I2S_ECO_CONF_REG (DR_REG_LP_I2S_BASE + 0x7c) +/** LP_I2S_RDN_ENA : R/W; bitpos: [0]; default: 0; + * enable rdn counter bit + */ +#define LP_I2S_RDN_ENA (BIT(0)) +#define LP_I2S_RDN_ENA_M (LP_I2S_RDN_ENA_V << LP_I2S_RDN_ENA_S) +#define LP_I2S_RDN_ENA_V 0x00000001U +#define LP_I2S_RDN_ENA_S 0 +/** LP_I2S_RDN_RESULT : RO; bitpos: [1]; default: 0; + * rdn result + */ +#define LP_I2S_RDN_RESULT (BIT(1)) +#define LP_I2S_RDN_RESULT_M (LP_I2S_RDN_RESULT_V << LP_I2S_RDN_RESULT_S) +#define LP_I2S_RDN_RESULT_V 0x00000001U +#define LP_I2S_RDN_RESULT_S 1 + +/** LP_I2S_VAD_PARAM0_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM0_REG (DR_REG_LP_I2S_BASE + 0x80) +/** LP_I2S_PARAM_MIN_ENERGY : R/W; bitpos: [15:0]; default: 5000; + * VAD parameter + */ +#define LP_I2S_PARAM_MIN_ENERGY 0x0000FFFFU +#define LP_I2S_PARAM_MIN_ENERGY_M (LP_I2S_PARAM_MIN_ENERGY_V << LP_I2S_PARAM_MIN_ENERGY_S) +#define LP_I2S_PARAM_MIN_ENERGY_V 0x0000FFFFU +#define LP_I2S_PARAM_MIN_ENERGY_S 0 +/** LP_I2S_PARAM_INIT_FRAME_NUM : R/W; bitpos: [24:16]; default: 200; + * VAD parameter + */ +#define LP_I2S_PARAM_INIT_FRAME_NUM 0x000001FFU +#define LP_I2S_PARAM_INIT_FRAME_NUM_M (LP_I2S_PARAM_INIT_FRAME_NUM_V << LP_I2S_PARAM_INIT_FRAME_NUM_S) +#define LP_I2S_PARAM_INIT_FRAME_NUM_V 0x000001FFU +#define LP_I2S_PARAM_INIT_FRAME_NUM_S 16 + +/** LP_I2S_VAD_PARAM1_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM1_REG (DR_REG_LP_I2S_BASE + 0x84) +/** LP_I2S_PARAM_MIN_SPEECH_COUNT : R/W; bitpos: [3:0]; default: 3; + * VAD parameter + */ +#define LP_I2S_PARAM_MIN_SPEECH_COUNT 0x0000000FU +#define LP_I2S_PARAM_MIN_SPEECH_COUNT_M (LP_I2S_PARAM_MIN_SPEECH_COUNT_V << LP_I2S_PARAM_MIN_SPEECH_COUNT_S) +#define LP_I2S_PARAM_MIN_SPEECH_COUNT_V 0x0000000FU +#define LP_I2S_PARAM_MIN_SPEECH_COUNT_S 0 +/** LP_I2S_PARAM_MAX_SPEECH_COUNT : R/W; bitpos: [10:4]; default: 100; + * VAD parameter + */ +#define LP_I2S_PARAM_MAX_SPEECH_COUNT 0x0000007FU +#define LP_I2S_PARAM_MAX_SPEECH_COUNT_M (LP_I2S_PARAM_MAX_SPEECH_COUNT_V << LP_I2S_PARAM_MAX_SPEECH_COUNT_S) +#define LP_I2S_PARAM_MAX_SPEECH_COUNT_V 0x0000007FU +#define LP_I2S_PARAM_MAX_SPEECH_COUNT_S 4 +/** LP_I2S_PARAM_HANGOVER_SPEECH : R/W; bitpos: [15:11]; default: 3; + * VAD parameter + */ +#define LP_I2S_PARAM_HANGOVER_SPEECH 0x0000001FU +#define LP_I2S_PARAM_HANGOVER_SPEECH_M (LP_I2S_PARAM_HANGOVER_SPEECH_V << LP_I2S_PARAM_HANGOVER_SPEECH_S) +#define LP_I2S_PARAM_HANGOVER_SPEECH_V 0x0000001FU +#define LP_I2S_PARAM_HANGOVER_SPEECH_S 11 +/** LP_I2S_PARAM_HANGOVER_SILENT : R/W; bitpos: [23:16]; default: 30; + * VAD parameter + */ +#define LP_I2S_PARAM_HANGOVER_SILENT 0x000000FFU +#define LP_I2S_PARAM_HANGOVER_SILENT_M (LP_I2S_PARAM_HANGOVER_SILENT_V << LP_I2S_PARAM_HANGOVER_SILENT_S) +#define LP_I2S_PARAM_HANGOVER_SILENT_V 0x000000FFU +#define LP_I2S_PARAM_HANGOVER_SILENT_S 16 +/** LP_I2S_PARAM_MAX_OFFSET : R/W; bitpos: [30:24]; default: 40; + * VAD parameter + */ +#define LP_I2S_PARAM_MAX_OFFSET 0x0000007FU +#define LP_I2S_PARAM_MAX_OFFSET_M (LP_I2S_PARAM_MAX_OFFSET_V << LP_I2S_PARAM_MAX_OFFSET_S) +#define LP_I2S_PARAM_MAX_OFFSET_V 0x0000007FU +#define LP_I2S_PARAM_MAX_OFFSET_S 24 +/** LP_I2S_PARAM_SKIP_BAND_ENERGY : R/W; bitpos: [31]; default: 0; + * Set 1 to skip band energy check. + */ +#define LP_I2S_PARAM_SKIP_BAND_ENERGY (BIT(31)) +#define LP_I2S_PARAM_SKIP_BAND_ENERGY_M (LP_I2S_PARAM_SKIP_BAND_ENERGY_V << LP_I2S_PARAM_SKIP_BAND_ENERGY_S) +#define LP_I2S_PARAM_SKIP_BAND_ENERGY_V 0x00000001U +#define LP_I2S_PARAM_SKIP_BAND_ENERGY_S 31 + +/** LP_I2S_VAD_PARAM2_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM2_REG (DR_REG_LP_I2S_BASE + 0x88) +/** LP_I2S_PARAM_NOISE_AMP_DOWN : R/W; bitpos: [15:0]; default: 26214; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_AMP_DOWN 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_AMP_DOWN_M (LP_I2S_PARAM_NOISE_AMP_DOWN_V << LP_I2S_PARAM_NOISE_AMP_DOWN_S) +#define LP_I2S_PARAM_NOISE_AMP_DOWN_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_AMP_DOWN_S 0 +/** LP_I2S_PARAM_NOISE_AMP_UP : R/W; bitpos: [31:16]; default: 32440; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_AMP_UP 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_AMP_UP_M (LP_I2S_PARAM_NOISE_AMP_UP_V << LP_I2S_PARAM_NOISE_AMP_UP_S) +#define LP_I2S_PARAM_NOISE_AMP_UP_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_AMP_UP_S 16 + +/** LP_I2S_VAD_PARAM3_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM3_REG (DR_REG_LP_I2S_BASE + 0x8c) +/** LP_I2S_PARAM_NOISE_SPE_UP0 : R/W; bitpos: [15:0]; default: 32735; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_SPE_UP0 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_SPE_UP0_M (LP_I2S_PARAM_NOISE_SPE_UP0_V << LP_I2S_PARAM_NOISE_SPE_UP0_S) +#define LP_I2S_PARAM_NOISE_SPE_UP0_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_SPE_UP0_S 0 +/** LP_I2S_PARAM_NOISE_SPE_UP1 : R/W; bitpos: [31:16]; default: 32113; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_SPE_UP1 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_SPE_UP1_M (LP_I2S_PARAM_NOISE_SPE_UP1_V << LP_I2S_PARAM_NOISE_SPE_UP1_S) +#define LP_I2S_PARAM_NOISE_SPE_UP1_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_SPE_UP1_S 16 + +/** LP_I2S_VAD_PARAM4_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM4_REG (DR_REG_LP_I2S_BASE + 0x90) +/** LP_I2S_PARAM_NOISE_SPE_DOWN : R/W; bitpos: [15:0]; default: 26214; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_SPE_DOWN 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_SPE_DOWN_M (LP_I2S_PARAM_NOISE_SPE_DOWN_V << LP_I2S_PARAM_NOISE_SPE_DOWN_S) +#define LP_I2S_PARAM_NOISE_SPE_DOWN_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_SPE_DOWN_S 0 +/** LP_I2S_PARAM_NOISE_MEAN_DOWN : R/W; bitpos: [31:16]; default: 31130; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_MEAN_DOWN 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_MEAN_DOWN_M (LP_I2S_PARAM_NOISE_MEAN_DOWN_V << LP_I2S_PARAM_NOISE_MEAN_DOWN_S) +#define LP_I2S_PARAM_NOISE_MEAN_DOWN_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_MEAN_DOWN_S 16 + +/** LP_I2S_VAD_PARAM5_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM5_REG (DR_REG_LP_I2S_BASE + 0x94) +/** LP_I2S_PARAM_NOISE_MEAN_UP0 : R/W; bitpos: [15:0]; default: 32113; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_MEAN_UP0 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_MEAN_UP0_M (LP_I2S_PARAM_NOISE_MEAN_UP0_V << LP_I2S_PARAM_NOISE_MEAN_UP0_S) +#define LP_I2S_PARAM_NOISE_MEAN_UP0_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_MEAN_UP0_S 0 +/** LP_I2S_PARAM_NOISE_MEAN_UP1 : R/W; bitpos: [31:16]; default: 31784; + * VAD parameter + */ +#define LP_I2S_PARAM_NOISE_MEAN_UP1 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_MEAN_UP1_M (LP_I2S_PARAM_NOISE_MEAN_UP1_V << LP_I2S_PARAM_NOISE_MEAN_UP1_S) +#define LP_I2S_PARAM_NOISE_MEAN_UP1_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_MEAN_UP1_S 16 + +/** LP_I2S_VAD_PARAM6_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM6_REG (DR_REG_LP_I2S_BASE + 0x98) +/** LP_I2S_PARAM_NOISE_STD_FS_THSL : R/W; bitpos: [15:0]; default: 32000; + * Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to + * ((noise_std_max)>>11)^2*5 + */ +#define LP_I2S_PARAM_NOISE_STD_FS_THSL 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_STD_FS_THSL_M (LP_I2S_PARAM_NOISE_STD_FS_THSL_V << LP_I2S_PARAM_NOISE_STD_FS_THSL_S) +#define LP_I2S_PARAM_NOISE_STD_FS_THSL_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_STD_FS_THSL_S 0 +/** LP_I2S_PARAM_NOISE_STD_FS_THSH : R/W; bitpos: [31:16]; default: 46080; + * Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to + * ((noise_std_max)>>11)^2*5 + */ +#define LP_I2S_PARAM_NOISE_STD_FS_THSH 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_STD_FS_THSH_M (LP_I2S_PARAM_NOISE_STD_FS_THSH_V << LP_I2S_PARAM_NOISE_STD_FS_THSH_S) +#define LP_I2S_PARAM_NOISE_STD_FS_THSH_V 0x0000FFFFU +#define LP_I2S_PARAM_NOISE_STD_FS_THSH_S 16 + +/** LP_I2S_VAD_PARAM7_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM7_REG (DR_REG_LP_I2S_BASE + 0x9c) +/** LP_I2S_PARAM_THRES_UPD_BASE : R/W; bitpos: [15:0]; default: 32440; + * VAD parameter + */ +#define LP_I2S_PARAM_THRES_UPD_BASE 0x0000FFFFU +#define LP_I2S_PARAM_THRES_UPD_BASE_M (LP_I2S_PARAM_THRES_UPD_BASE_V << LP_I2S_PARAM_THRES_UPD_BASE_S) +#define LP_I2S_PARAM_THRES_UPD_BASE_V 0x0000FFFFU +#define LP_I2S_PARAM_THRES_UPD_BASE_S 0 +/** LP_I2S_PARAM_THRES_UPD_VARY : R/W; bitpos: [31:16]; default: 328; + * VAD parameter + */ +#define LP_I2S_PARAM_THRES_UPD_VARY 0x0000FFFFU +#define LP_I2S_PARAM_THRES_UPD_VARY_M (LP_I2S_PARAM_THRES_UPD_VARY_V << LP_I2S_PARAM_THRES_UPD_VARY_S) +#define LP_I2S_PARAM_THRES_UPD_VARY_V 0x0000FFFFU +#define LP_I2S_PARAM_THRES_UPD_VARY_S 16 + +/** LP_I2S_VAD_PARAM8_REG register + * I2S VAD Parameter register + */ +#define LP_I2S_VAD_PARAM8_REG (DR_REG_LP_I2S_BASE + 0xa0) +/** LP_I2S_PARAM_THRES_UPD_BDL : R/W; bitpos: [7:0]; default: 64; + * Noise_std boundary low when updating threshold. + */ +#define LP_I2S_PARAM_THRES_UPD_BDL 0x000000FFU +#define LP_I2S_PARAM_THRES_UPD_BDL_M (LP_I2S_PARAM_THRES_UPD_BDL_V << LP_I2S_PARAM_THRES_UPD_BDL_S) +#define LP_I2S_PARAM_THRES_UPD_BDL_V 0x000000FFU +#define LP_I2S_PARAM_THRES_UPD_BDL_S 0 +/** LP_I2S_PARAM_THRES_UPD_BDH : R/W; bitpos: [15:8]; default: 80; + * Noise_std boundary high when updating threshold. + */ +#define LP_I2S_PARAM_THRES_UPD_BDH 0x000000FFU +#define LP_I2S_PARAM_THRES_UPD_BDH_M (LP_I2S_PARAM_THRES_UPD_BDH_V << LP_I2S_PARAM_THRES_UPD_BDH_S) +#define LP_I2S_PARAM_THRES_UPD_BDH_V 0x000000FFU +#define LP_I2S_PARAM_THRES_UPD_BDH_S 8 +/** LP_I2S_PARAM_FEATURE_BURST : R/W; bitpos: [31:16]; default: 8192; + * VAD parameter + */ +#define LP_I2S_PARAM_FEATURE_BURST 0x0000FFFFU +#define LP_I2S_PARAM_FEATURE_BURST_M (LP_I2S_PARAM_FEATURE_BURST_V << LP_I2S_PARAM_FEATURE_BURST_S) +#define LP_I2S_PARAM_FEATURE_BURST_V 0x0000FFFFU +#define LP_I2S_PARAM_FEATURE_BURST_S 16 + +/** LP_I2S_VAD_OB0_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB0_REG (DR_REG_LP_I2S_BASE + 0xb0) +/** LP_I2S_SPEECH_COUNT_OB : RO; bitpos: [7:0]; default: 0; + * Reg silent count observe + */ +#define LP_I2S_SPEECH_COUNT_OB 0x000000FFU +#define LP_I2S_SPEECH_COUNT_OB_M (LP_I2S_SPEECH_COUNT_OB_V << LP_I2S_SPEECH_COUNT_OB_S) +#define LP_I2S_SPEECH_COUNT_OB_V 0x000000FFU +#define LP_I2S_SPEECH_COUNT_OB_S 0 +/** LP_I2S_SILENT_COUNT_OB : RO; bitpos: [15:8]; default: 0; + * Reg speech count observe + */ +#define LP_I2S_SILENT_COUNT_OB 0x000000FFU +#define LP_I2S_SILENT_COUNT_OB_M (LP_I2S_SILENT_COUNT_OB_V << LP_I2S_SILENT_COUNT_OB_S) +#define LP_I2S_SILENT_COUNT_OB_V 0x000000FFU +#define LP_I2S_SILENT_COUNT_OB_S 8 +/** LP_I2S_MAX_SIGNAL0_OB : RO; bitpos: [31:16]; default: 0; + * Reg max signal0 observe + */ +#define LP_I2S_MAX_SIGNAL0_OB 0x0000FFFFU +#define LP_I2S_MAX_SIGNAL0_OB_M (LP_I2S_MAX_SIGNAL0_OB_V << LP_I2S_MAX_SIGNAL0_OB_S) +#define LP_I2S_MAX_SIGNAL0_OB_V 0x0000FFFFU +#define LP_I2S_MAX_SIGNAL0_OB_S 16 + +/** LP_I2S_VAD_OB1_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB1_REG (DR_REG_LP_I2S_BASE + 0xb4) +/** LP_I2S_MAX_SIGNAL1_OB : RO; bitpos: [15:0]; default: 0; + * Reg max signal1 observe + */ +#define LP_I2S_MAX_SIGNAL1_OB 0x0000FFFFU +#define LP_I2S_MAX_SIGNAL1_OB_M (LP_I2S_MAX_SIGNAL1_OB_V << LP_I2S_MAX_SIGNAL1_OB_S) +#define LP_I2S_MAX_SIGNAL1_OB_V 0x0000FFFFU +#define LP_I2S_MAX_SIGNAL1_OB_S 0 +/** LP_I2S_MAX_SIGNAL2_OB : RO; bitpos: [31:16]; default: 0; + * Reg max signal2 observe + */ +#define LP_I2S_MAX_SIGNAL2_OB 0x0000FFFFU +#define LP_I2S_MAX_SIGNAL2_OB_M (LP_I2S_MAX_SIGNAL2_OB_V << LP_I2S_MAX_SIGNAL2_OB_S) +#define LP_I2S_MAX_SIGNAL2_OB_V 0x0000FFFFU +#define LP_I2S_MAX_SIGNAL2_OB_S 16 + +/** LP_I2S_VAD_OB2_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB2_REG (DR_REG_LP_I2S_BASE + 0xb8) +/** LP_I2S_NOISE_AMP_OB : RO; bitpos: [31:0]; default: 0; + * Reg noise_amp observe signal + */ +#define LP_I2S_NOISE_AMP_OB 0xFFFFFFFFU +#define LP_I2S_NOISE_AMP_OB_M (LP_I2S_NOISE_AMP_OB_V << LP_I2S_NOISE_AMP_OB_S) +#define LP_I2S_NOISE_AMP_OB_V 0xFFFFFFFFU +#define LP_I2S_NOISE_AMP_OB_S 0 + +/** LP_I2S_VAD_OB3_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB3_REG (DR_REG_LP_I2S_BASE + 0xbc) +/** LP_I2S_NOISE_MEAN_OB : RO; bitpos: [31:0]; default: 0; + * Reg noise_mean observe signal + */ +#define LP_I2S_NOISE_MEAN_OB 0xFFFFFFFFU +#define LP_I2S_NOISE_MEAN_OB_M (LP_I2S_NOISE_MEAN_OB_V << LP_I2S_NOISE_MEAN_OB_S) +#define LP_I2S_NOISE_MEAN_OB_V 0xFFFFFFFFU +#define LP_I2S_NOISE_MEAN_OB_S 0 + +/** LP_I2S_VAD_OB4_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB4_REG (DR_REG_LP_I2S_BASE + 0xc0) +/** LP_I2S_NOISE_STD_OB : RO; bitpos: [31:0]; default: 0; + * Reg noise_std observe signal + */ +#define LP_I2S_NOISE_STD_OB 0xFFFFFFFFU +#define LP_I2S_NOISE_STD_OB_M (LP_I2S_NOISE_STD_OB_V << LP_I2S_NOISE_STD_OB_S) +#define LP_I2S_NOISE_STD_OB_V 0xFFFFFFFFU +#define LP_I2S_NOISE_STD_OB_S 0 + +/** LP_I2S_VAD_OB5_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB5_REG (DR_REG_LP_I2S_BASE + 0xc4) +/** LP_I2S_OFFSET_OB : RO; bitpos: [31:0]; default: 0; + * Reg offset observe signal + */ +#define LP_I2S_OFFSET_OB 0xFFFFFFFFU +#define LP_I2S_OFFSET_OB_M (LP_I2S_OFFSET_OB_V << LP_I2S_OFFSET_OB_S) +#define LP_I2S_OFFSET_OB_V 0xFFFFFFFFU +#define LP_I2S_OFFSET_OB_S 0 + +/** LP_I2S_VAD_OB6_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB6_REG (DR_REG_LP_I2S_BASE + 0xc8) +/** LP_I2S_THRESHOLD_OB : RO; bitpos: [31:0]; default: 0; + * Reg threshold observe signal + */ +#define LP_I2S_THRESHOLD_OB 0xFFFFFFFFU +#define LP_I2S_THRESHOLD_OB_M (LP_I2S_THRESHOLD_OB_V << LP_I2S_THRESHOLD_OB_S) +#define LP_I2S_THRESHOLD_OB_V 0xFFFFFFFFU +#define LP_I2S_THRESHOLD_OB_S 0 + +/** LP_I2S_VAD_OB7_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB7_REG (DR_REG_LP_I2S_BASE + 0xcc) +/** LP_I2S_ENERGY_LOW_OB : RO; bitpos: [31:0]; default: 0; + * Reg energy bit 31~0 observe signal + */ +#define LP_I2S_ENERGY_LOW_OB 0xFFFFFFFFU +#define LP_I2S_ENERGY_LOW_OB_M (LP_I2S_ENERGY_LOW_OB_V << LP_I2S_ENERGY_LOW_OB_S) +#define LP_I2S_ENERGY_LOW_OB_V 0xFFFFFFFFU +#define LP_I2S_ENERGY_LOW_OB_S 0 + +/** LP_I2S_VAD_OB8_REG register + * I2S VAD Observe register + */ +#define LP_I2S_VAD_OB8_REG (DR_REG_LP_I2S_BASE + 0xd0) +/** LP_I2S_ENERGY_HIGH_OB : RO; bitpos: [31:0]; default: 0; + * Reg energy bit 63~32 observe signal + */ +#define LP_I2S_ENERGY_HIGH_OB 0xFFFFFFFFU +#define LP_I2S_ENERGY_HIGH_OB_M (LP_I2S_ENERGY_HIGH_OB_V << LP_I2S_ENERGY_HIGH_OB_S) +#define LP_I2S_ENERGY_HIGH_OB_V 0xFFFFFFFFU +#define LP_I2S_ENERGY_HIGH_OB_S 0 + +/** LP_I2S_CLK_GATE_REG register + * Clock gate register + */ +#define LP_I2S_CLK_GATE_REG (DR_REG_LP_I2S_BASE + 0xf8) +/** LP_I2S_CLK_EN : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ +#define LP_I2S_CLK_EN (BIT(0)) +#define LP_I2S_CLK_EN_M (LP_I2S_CLK_EN_V << LP_I2S_CLK_EN_S) +#define LP_I2S_CLK_EN_V 0x00000001U +#define LP_I2S_CLK_EN_S 0 +/** LP_I2S_VAD_CG_FORCE_ON : R/W; bitpos: [1]; default: 1; + * VAD clock gate force on register + */ +#define LP_I2S_VAD_CG_FORCE_ON (BIT(1)) +#define LP_I2S_VAD_CG_FORCE_ON_M (LP_I2S_VAD_CG_FORCE_ON_V << LP_I2S_VAD_CG_FORCE_ON_S) +#define LP_I2S_VAD_CG_FORCE_ON_V 0x00000001U +#define LP_I2S_VAD_CG_FORCE_ON_S 1 +/** LP_I2S_RX_MEM_CG_FORCE_ON : R/W; bitpos: [2]; default: 0; + * I2S rx mem clock gate force on register + */ +#define LP_I2S_RX_MEM_CG_FORCE_ON (BIT(2)) +#define LP_I2S_RX_MEM_CG_FORCE_ON_M (LP_I2S_RX_MEM_CG_FORCE_ON_V << LP_I2S_RX_MEM_CG_FORCE_ON_S) +#define LP_I2S_RX_MEM_CG_FORCE_ON_V 0x00000001U +#define LP_I2S_RX_MEM_CG_FORCE_ON_S 2 +/** LP_I2S_RX_REG_CG_FORCE_ON : R/W; bitpos: [3]; default: 1; + * I2S rx reg clock gate force on register + */ +#define LP_I2S_RX_REG_CG_FORCE_ON (BIT(3)) +#define LP_I2S_RX_REG_CG_FORCE_ON_M (LP_I2S_RX_REG_CG_FORCE_ON_V << LP_I2S_RX_REG_CG_FORCE_ON_S) +#define LP_I2S_RX_REG_CG_FORCE_ON_V 0x00000001U +#define LP_I2S_RX_REG_CG_FORCE_ON_S 3 + +/** LP_I2S_DATE_REG register + * Version control register + */ +#define LP_I2S_DATE_REG (DR_REG_LP_I2S_BASE + 0xfc) +/** LP_I2S_DATE : R/W; bitpos: [27:0]; default: 36720704; + * I2S version control register + */ +#define LP_I2S_DATE 0x0FFFFFFFU +#define LP_I2S_DATE_M (LP_I2S_DATE_V << LP_I2S_DATE_S) +#define LP_I2S_DATE_V 0x0FFFFFFFU +#define LP_I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_struct.h new file mode 100644 index 0000000000..bfc118ffeb --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_i2s_struct.h @@ -0,0 +1,949 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: VAD registers */ +/** Type of vad_conf register + * I2S VAD Configure register + */ +typedef union { + struct { + /** vad_en : R/W; bitpos: [0]; default: 0; + * VAD enable register + */ + uint32_t vad_en:1; + /** vad_reset : WT; bitpos: [1]; default: 0; + * VAD reset register + */ + uint32_t vad_reset:1; + /** vad_force_start : WT; bitpos: [2]; default: 0; + * VAD force start register. + */ + uint32_t vad_force_start:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_i2s_vad_conf_reg_t; + +/** Type of vad_result register + * I2S VAD Result register + */ +typedef union { + struct { + /** vad_flag : RO; bitpos: [0]; default: 0; + * Reg vad flag observe signal + */ + uint32_t vad_flag:1; + /** energy_enough : RO; bitpos: [1]; default: 0; + * Reg energy enough observe signal + */ + uint32_t energy_enough:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_i2s_vad_result_reg_t; + +/** Type of vad_param0 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_min_energy : R/W; bitpos: [15:0]; default: 5000; + * VAD parameter + */ + uint32_t param_min_energy:16; + /** param_init_frame_num : R/W; bitpos: [24:16]; default: 200; + * VAD parameter + */ + uint32_t param_init_frame_num:9; + uint32_t reserved_25:7; + }; + uint32_t val; +} lp_i2s_vad_param0_reg_t; + +/** Type of vad_param1 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_min_speech_count : R/W; bitpos: [3:0]; default: 3; + * VAD parameter + */ + uint32_t param_min_speech_count:4; + /** param_max_speech_count : R/W; bitpos: [10:4]; default: 100; + * VAD parameter + */ + uint32_t param_max_speech_count:7; + /** param_hangover_speech : R/W; bitpos: [15:11]; default: 3; + * VAD parameter + */ + uint32_t param_hangover_speech:5; + /** param_hangover_silent : R/W; bitpos: [23:16]; default: 30; + * VAD parameter + */ + uint32_t param_hangover_silent:8; + /** param_max_offset : R/W; bitpos: [30:24]; default: 40; + * VAD parameter + */ + uint32_t param_max_offset:7; + /** param_skip_band_energy : R/W; bitpos: [31]; default: 0; + * Set 1 to skip band energy check. + */ + uint32_t param_skip_band_energy:1; + }; + uint32_t val; +} lp_i2s_vad_param1_reg_t; + +/** Type of vad_param2 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_noise_amp_down : R/W; bitpos: [15:0]; default: 26214; + * VAD parameter + */ + uint32_t param_noise_amp_down:16; + /** param_noise_amp_up : R/W; bitpos: [31:16]; default: 32440; + * VAD parameter + */ + uint32_t param_noise_amp_up:16; + }; + uint32_t val; +} lp_i2s_vad_param2_reg_t; + +/** Type of vad_param3 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_noise_spe_up0 : R/W; bitpos: [15:0]; default: 32735; + * VAD parameter + */ + uint32_t param_noise_spe_up0:16; + /** param_noise_spe_up1 : R/W; bitpos: [31:16]; default: 32113; + * VAD parameter + */ + uint32_t param_noise_spe_up1:16; + }; + uint32_t val; +} lp_i2s_vad_param3_reg_t; + +/** Type of vad_param4 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_noise_spe_down : R/W; bitpos: [15:0]; default: 26214; + * VAD parameter + */ + uint32_t param_noise_spe_down:16; + /** param_noise_mean_down : R/W; bitpos: [31:16]; default: 31130; + * VAD parameter + */ + uint32_t param_noise_mean_down:16; + }; + uint32_t val; +} lp_i2s_vad_param4_reg_t; + +/** Type of vad_param5 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_noise_mean_up0 : R/W; bitpos: [15:0]; default: 32113; + * VAD parameter + */ + uint32_t param_noise_mean_up0:16; + /** param_noise_mean_up1 : R/W; bitpos: [31:16]; default: 31784; + * VAD parameter + */ + uint32_t param_noise_mean_up1:16; + }; + uint32_t val; +} lp_i2s_vad_param5_reg_t; + +/** Type of vad_param6 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_noise_std_fs_thsl : R/W; bitpos: [15:0]; default: 32000; + * Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to + * ((noise_std_max)>>11)^2*5 + */ + uint32_t param_noise_std_fs_thsl:16; + /** param_noise_std_fs_thsh : R/W; bitpos: [31:16]; default: 46080; + * Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to + * ((noise_std_max)>>11)^2*5 + */ + uint32_t param_noise_std_fs_thsh:16; + }; + uint32_t val; +} lp_i2s_vad_param6_reg_t; + +/** Type of vad_param7 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_thres_upd_base : R/W; bitpos: [15:0]; default: 32440; + * VAD parameter + */ + uint32_t param_thres_upd_base:16; + /** param_thres_upd_vary : R/W; bitpos: [31:16]; default: 328; + * VAD parameter + */ + uint32_t param_thres_upd_vary:16; + }; + uint32_t val; +} lp_i2s_vad_param7_reg_t; + +/** Type of vad_param8 register + * I2S VAD Parameter register + */ +typedef union { + struct { + /** param_thres_upd_bdl : R/W; bitpos: [7:0]; default: 64; + * Noise_std boundary low when updating threshold. + */ + uint32_t param_thres_upd_bdl:8; + /** param_thres_upd_bdh : R/W; bitpos: [15:8]; default: 80; + * Noise_std boundary high when updating threshold. + */ + uint32_t param_thres_upd_bdh:8; + /** param_feature_burst : R/W; bitpos: [31:16]; default: 8192; + * VAD parameter + */ + uint32_t param_feature_burst:16; + }; + uint32_t val; +} lp_i2s_vad_param8_reg_t; + +/** Type of vad_ob0 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** speech_count_ob : RO; bitpos: [7:0]; default: 0; + * Reg silent count observe + */ + uint32_t speech_count_ob:8; + /** silent_count_ob : RO; bitpos: [15:8]; default: 0; + * Reg speech count observe + */ + uint32_t silent_count_ob:8; + /** max_signal0_ob : RO; bitpos: [31:16]; default: 0; + * Reg max signal0 observe + */ + uint32_t max_signal0_ob:16; + }; + uint32_t val; +} lp_i2s_vad_ob0_reg_t; + +/** Type of vad_ob1 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** max_signal1_ob : RO; bitpos: [15:0]; default: 0; + * Reg max signal1 observe + */ + uint32_t max_signal1_ob:16; + /** max_signal2_ob : RO; bitpos: [31:16]; default: 0; + * Reg max signal2 observe + */ + uint32_t max_signal2_ob:16; + }; + uint32_t val; +} lp_i2s_vad_ob1_reg_t; + +/** Type of vad_ob2 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** noise_amp_ob : RO; bitpos: [31:0]; default: 0; + * Reg noise_amp observe signal + */ + uint32_t noise_amp_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob2_reg_t; + +/** Type of vad_ob3 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** noise_mean_ob : RO; bitpos: [31:0]; default: 0; + * Reg noise_mean observe signal + */ + uint32_t noise_mean_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob3_reg_t; + +/** Type of vad_ob4 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** noise_std_ob : RO; bitpos: [31:0]; default: 0; + * Reg noise_std observe signal + */ + uint32_t noise_std_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob4_reg_t; + +/** Type of vad_ob5 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** offset_ob : RO; bitpos: [31:0]; default: 0; + * Reg offset observe signal + */ + uint32_t offset_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob5_reg_t; + +/** Type of vad_ob6 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** threshold_ob : RO; bitpos: [31:0]; default: 0; + * Reg threshold observe signal + */ + uint32_t threshold_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob6_reg_t; + +/** Type of vad_ob7 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** energy_low_ob : RO; bitpos: [31:0]; default: 0; + * Reg energy bit 31~0 observe signal + */ + uint32_t energy_low_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob7_reg_t; + +/** Type of vad_ob8 register + * I2S VAD Observe register + */ +typedef union { + struct { + /** energy_high_ob : RO; bitpos: [31:0]; default: 0; + * Reg energy bit 63~32 observe signal + */ + uint32_t energy_high_ob:32; + }; + uint32_t val; +} lp_i2s_vad_ob8_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of rx_mem_conf register + * I2S VAD Observe register + */ +typedef union { + struct { + /** rx_mem_fifo_cnt : RO; bitpos: [8:0]; default: 0; + * The number of data in the rx mem + */ + uint32_t rx_mem_fifo_cnt:9; + /** rx_mem_threshold : R/W; bitpos: [16:9]; default: 63; + * I2S rx mem will trigger an interrupt when the data in the mem is over(not including + * equal) reg_rx_mem_threshold + */ + uint32_t rx_mem_threshold:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_i2s_rx_mem_conf_reg_t; + +/** Type of rx_conf register + * I2S RX configure register + */ +typedef union { + struct { + /** rx_reset : WT; bitpos: [0]; default: 0; + * Set this bit to reset receiver + */ + uint32_t rx_reset:1; + /** rx_fifo_reset : WT; bitpos: [1]; default: 0; + * Set this bit to reset Rx AFIFO + */ + uint32_t rx_fifo_reset:1; + /** rx_start : R/W; bitpos: [2]; default: 0; + * Set this bit to start receiving data + */ + uint32_t rx_start:1; + /** rx_slave_mod : R/W; bitpos: [3]; default: 0; + * Set this bit to enable slave receiver mode + */ + uint32_t rx_slave_mod:1; + /** rx_fifomem_reset : WT; bitpos: [4]; default: 0; + * Set this bit to reset Rx Syncfifomem + */ + uint32_t rx_fifomem_reset:1; + /** rx_mono : R/W; bitpos: [5]; default: 0; + * Set this bit to enable receiver in mono mode + */ + uint32_t rx_mono:1; + uint32_t reserved_6:1; + /** rx_big_endian : R/W; bitpos: [7]; default: 0; + * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + */ + uint32_t rx_big_endian:1; + /** rx_update : R/W/SC; bitpos: [8]; default: 0; + * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This + * bit will be cleared by hardware after update register done. + */ + uint32_t rx_update:1; + /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; + * 1: The first channel data value is valid in I2S RX mono mode. 0: The second + * channel data value is valid in I2S RX mono mode. + */ + uint32_t rx_mono_fst_vld:1; + /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; + * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 + * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + */ + uint32_t rx_pcm_conf:2; + /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + uint32_t rx_pcm_bypass:1; + /** rx_stop_mode : R/W; bitpos: [14:13]; default: 0; + * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is + * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + */ + uint32_t rx_stop_mode:2; + /** rx_left_align : R/W; bitpos: [15]; default: 1; + * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + */ + uint32_t rx_left_align:1; + /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; + * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + */ + uint32_t rx_24_fill_en:1; + /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; + * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. + * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + */ + uint32_t rx_ws_idle_pol:1; + /** rx_bit_order : R/W; bitpos: [18]; default: 0; + * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB + * is received first. + */ + uint32_t rx_bit_order:1; + /** rx_tdm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable I2S TDM Rx mode . 0: Disable. + */ + uint32_t rx_tdm_en:1; + /** rx_pdm_en : R/W; bitpos: [20]; default: 0; + * 1: Enable I2S PDM Rx mode . 0: Disable. + */ + uint32_t rx_pdm_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_i2s_rx_conf_reg_t; + +/** Type of rx_conf1 register + * I2S RX configure register 1 + */ +typedef union { + struct { + /** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0; + * The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + */ + uint32_t rx_tdm_ws_width:7; + /** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + uint32_t rx_bck_div_num:6; + /** rx_bits_mod : R/W; bitpos: [17:13]; default: 15; + * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all + * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in + * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid + * channel data is in 32-bit-mode. + */ + uint32_t rx_bits_mod:5; + /** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15; + * I2S Rx half sample bits -1. + */ + uint32_t rx_half_sample_bits:6; + /** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15; + * The Rx bit number for each channel minus 1in TDM mode. + */ + uint32_t rx_tdm_chan_bits:5; + /** rx_msb_shift : R/W; bitpos: [29]; default: 1; + * Set this bit to enable receiver in Phillips standard mode + */ + uint32_t rx_msb_shift:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_i2s_rx_conf1_reg_t; + +/** Type of rx_tdm_ctrl register + * I2S TX TDM mode control register + */ +typedef union { + struct { + /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan0_en:1; + /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; + * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just + * input 0 in this channel. + */ + uint32_t rx_tdm_pdm_chan1_en:1; + uint32_t reserved_2:14; + /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; + * The total channel number of I2S TX TDM mode. + */ + uint32_t rx_tdm_tot_chan_num:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_i2s_rx_tdm_ctrl_reg_t; + +/** Type of rxeof_num register + * I2S RX data number control register. + */ +typedef union { + struct { + /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; + * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + + * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + */ + uint32_t rx_eof_num:12; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2s_rxeof_num_reg_t; + +/** Type of rx_pdm_conf register + * I2S RX configure register + */ +typedef union { + struct { + uint32_t reserved_0:19; + /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0; + * 1: Enable PDM2PCM RX mode. 0: DIsable. + */ + uint32_t rx_pdm2pcm_en:1; + /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0; + * Configure the down sampling rate of PDM RX filter group1 module. 1: The down + * sampling rate is 128. 0: down sampling rate is 64. + */ + uint32_t rx_pdm_sinc_dsr_16_en:1; + /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1; + * Configure PDM RX amplify number. + */ + uint32_t rx_pdm2pcm_amplify_num:4; + /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0; + * I2S PDM RX bypass hp filter or not. + */ + uint32_t rx_pdm_hp_bypass:1; + /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6; + * The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + */ + uint32_t rx_iir_hp_mult12_5:3; + /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7; + * The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + * LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + */ + uint32_t rx_iir_hp_mult12_0:3; + }; + uint32_t val; +} lp_i2s_rx_pdm_conf_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * I2S interrupt raw register, valid in level. + */ +typedef union { + struct { + /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_raw:1; + /** rx_hung_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_raw:1; + /** rx_fifomem_udf_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + */ + uint32_t rx_fifomem_udf_int_raw:1; + /** vad_done_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the vad_done_int interrupt + */ + uint32_t vad_done_int_raw:1; + /** vad_reset_done_int_raw : RO/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt status bit for the vad_reset_done_int interrupt + */ + uint32_t vad_reset_done_int_raw:1; + /** rx_mem_threshold_int_raw : RO/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt status bit for the rx_mem_threshold_int interrupt + */ + uint32_t rx_mem_threshold_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2s_int_raw_reg_t; + +/** Type of int_st register + * I2S interrupt status register. + */ +typedef union { + struct { + /** rx_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_st:1; + /** rx_hung_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_st:1; + /** rx_fifomem_udf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + */ + uint32_t rx_fifomem_udf_int_st:1; + /** vad_done_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the vad_done_int interrupt + */ + uint32_t vad_done_int_st:1; + /** vad_reset_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the vad_reset_done_int interrupt + */ + uint32_t vad_reset_done_int_st:1; + /** rx_mem_threshold_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the rx_mem_threshold_int interrupt + */ + uint32_t rx_mem_threshold_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2s_int_st_reg_t; + +/** Type of int_ena register + * I2S interrupt enable register. + */ +typedef union { + struct { + /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_ena:1; + /** rx_hung_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_ena:1; + /** rx_fifomem_udf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt + */ + uint32_t rx_fifomem_udf_int_ena:1; + /** vad_done_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the vad_done_int interrupt + */ + uint32_t vad_done_int_ena:1; + /** vad_reset_done_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the vad_reset_done_int interrupt + */ + uint32_t vad_reset_done_int_ena:1; + /** rx_mem_threshold_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the rx_mem_threshold_int interrupt + */ + uint32_t rx_mem_threshold_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2s_int_ena_reg_t; + +/** Type of int_clr register + * I2S interrupt clear register. + */ +typedef union { + struct { + /** rx_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_done_int interrupt + */ + uint32_t rx_done_int_clr:1; + /** rx_hung_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + uint32_t rx_hung_int_clr:1; + /** rx_fifomem_udf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_fifomem_udf_int interrupt + */ + uint32_t rx_fifomem_udf_int_clr:1; + /** vad_done_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the vad_done_int interrupt + */ + uint32_t vad_done_int_clr:1; + /** vad_reset_done_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the vad_reset_done_int interrupt + */ + uint32_t vad_reset_done_int_clr:1; + /** rx_mem_threshold_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the rx_mem_threshold_int interrupt + */ + uint32_t rx_mem_threshold_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2s_int_clr_reg_t; + + +/** Group: RX clock and timing registers */ +/** Type of rx_timing register + * I2S RX timing control register + */ +typedef union { + struct { + /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; + * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_sd_in_dm:2; + uint32_t reserved_2:14; + /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; + * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_out_dm:2; + uint32_t reserved_18:2; + /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; + * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_out_dm:2; + uint32_t reserved_22:2; + /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; + * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_ws_in_dm:2; + uint32_t reserved_26:2; + /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; + * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: + * delay by neg edge. 3: not used. + */ + uint32_t rx_bck_in_dm:2; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_i2s_rx_timing_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of lc_hung_conf register + * I2S HUNG configure register. + */ +typedef union { + struct { + /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered + * when fifo hung counter is equal to this value + */ + uint32_t lc_fifo_timeout:8; + /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is reset when + * counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + uint32_t lc_fifo_timeout_shift:3; + /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + uint32_t lc_fifo_timeout_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2s_lc_hung_conf_reg_t; + +/** Type of conf_sigle_data register + * I2S signal data register + */ +typedef union { + struct { + /** single_data : R/W; bitpos: [31:0]; default: 0; + * The configured constant channel data to be sent out. + */ + uint32_t single_data:32; + }; + uint32_t val; +} lp_i2s_conf_sigle_data_reg_t; + + +/** Group: ECO registers */ +/** Type of eco_low register + * I2S ECO register + */ +typedef union { + struct { + /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * logic low eco registers + */ + uint32_t rdn_eco_low:32; + }; + uint32_t val; +} lp_i2s_eco_low_reg_t; + +/** Type of eco_high register + * I2S ECO register + */ +typedef union { + struct { + /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * logic high eco registers + */ + uint32_t rdn_eco_high:32; + }; + uint32_t val; +} lp_i2s_eco_high_reg_t; + +/** Type of eco_conf register + * I2S ECO register + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * enable rdn counter bit + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 0; + * rdn result + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_i2s_eco_conf_reg_t; + + +/** Group: Clock registers */ +/** Type of clk_gate register + * Clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * set this bit to enable clock gate + */ + uint32_t clk_en:1; + /** vad_cg_force_on : R/W; bitpos: [1]; default: 1; + * VAD clock gate force on register + */ + uint32_t vad_cg_force_on:1; + /** rx_mem_cg_force_on : R/W; bitpos: [2]; default: 0; + * I2S rx mem clock gate force on register + */ + uint32_t rx_mem_cg_force_on:1; + /** rx_reg_cg_force_on : R/W; bitpos: [3]; default: 1; + * I2S rx reg clock gate force on register + */ + uint32_t rx_reg_cg_force_on:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_i2s_clk_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * I2S version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_i2s_date_reg_t; + + +typedef struct lp_i2s_dev_t { + volatile lp_i2s_vad_conf_reg_t vad_conf; + volatile lp_i2s_vad_result_reg_t vad_result; + volatile lp_i2s_rx_mem_conf_reg_t rx_mem_conf; + volatile lp_i2s_int_raw_reg_t int_raw; + volatile lp_i2s_int_st_reg_t int_st; + volatile lp_i2s_int_ena_reg_t int_ena; + volatile lp_i2s_int_clr_reg_t int_clr; + uint32_t reserved_01c; + volatile lp_i2s_rx_conf_reg_t rx_conf; + uint32_t reserved_024; + volatile lp_i2s_rx_conf1_reg_t rx_conf1; + uint32_t reserved_02c[9]; + volatile lp_i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; + uint32_t reserved_054; + volatile lp_i2s_rx_timing_reg_t rx_timing; + uint32_t reserved_05c; + volatile lp_i2s_lc_hung_conf_reg_t lc_hung_conf; + volatile lp_i2s_rxeof_num_reg_t rxeof_num; + volatile lp_i2s_conf_sigle_data_reg_t conf_sigle_data; + uint32_t reserved_06c; + volatile lp_i2s_rx_pdm_conf_reg_t rx_pdm_conf; + volatile lp_i2s_eco_low_reg_t eco_low; + volatile lp_i2s_eco_high_reg_t eco_high; + volatile lp_i2s_eco_conf_reg_t eco_conf; + volatile lp_i2s_vad_param0_reg_t vad_param0; + volatile lp_i2s_vad_param1_reg_t vad_param1; + volatile lp_i2s_vad_param2_reg_t vad_param2; + volatile lp_i2s_vad_param3_reg_t vad_param3; + volatile lp_i2s_vad_param4_reg_t vad_param4; + volatile lp_i2s_vad_param5_reg_t vad_param5; + volatile lp_i2s_vad_param6_reg_t vad_param6; + volatile lp_i2s_vad_param7_reg_t vad_param7; + volatile lp_i2s_vad_param8_reg_t vad_param8; + uint32_t reserved_0a4[3]; + volatile lp_i2s_vad_ob0_reg_t vad_ob0; + volatile lp_i2s_vad_ob1_reg_t vad_ob1; + volatile lp_i2s_vad_ob2_reg_t vad_ob2; + volatile lp_i2s_vad_ob3_reg_t vad_ob3; + volatile lp_i2s_vad_ob4_reg_t vad_ob4; + volatile lp_i2s_vad_ob5_reg_t vad_ob5; + volatile lp_i2s_vad_ob6_reg_t vad_ob6; + volatile lp_i2s_vad_ob7_reg_t vad_ob7; + volatile lp_i2s_vad_ob8_reg_t vad_ob8; + uint32_t reserved_0d4[9]; + volatile lp_i2s_clk_gate_reg_t clk_gate; + volatile lp_i2s_date_reg_t date; +} lp_i2s_dev_t; + +extern lp_i2s_dev_t LP_I2S; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2s_dev_t) == 0x100, "Invalid size of lp_i2s_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_intr_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_intr_reg.h new file mode 100644 index 0000000000..f4a0e4f7c2 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_intr_reg.h @@ -0,0 +1,235 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPINTR_SW_INT_RAW_REG register + * need_des + */ +#define LPINTR_SW_INT_RAW_REG (DR_REG_LPINTR_BASE + 0x0) +/** LPINTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0; + * need_des + */ +#define LPINTR_LP_SW_INT_RAW (BIT(31)) +#define LPINTR_LP_SW_INT_RAW_M (LPINTR_LP_SW_INT_RAW_V << LPINTR_LP_SW_INT_RAW_S) +#define LPINTR_LP_SW_INT_RAW_V 0x00000001U +#define LPINTR_LP_SW_INT_RAW_S 31 + +/** LPINTR_SW_INT_ST_REG register + * need_des + */ +#define LPINTR_SW_INT_ST_REG (DR_REG_LPINTR_BASE + 0x4) +/** LPINTR_LP_SW_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LPINTR_LP_SW_INT_ST (BIT(31)) +#define LPINTR_LP_SW_INT_ST_M (LPINTR_LP_SW_INT_ST_V << LPINTR_LP_SW_INT_ST_S) +#define LPINTR_LP_SW_INT_ST_V 0x00000001U +#define LPINTR_LP_SW_INT_ST_S 31 + +/** LPINTR_SW_INT_ENA_REG register + * need_des + */ +#define LPINTR_SW_INT_ENA_REG (DR_REG_LPINTR_BASE + 0x8) +/** LPINTR_LP_SW_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPINTR_LP_SW_INT_ENA (BIT(31)) +#define LPINTR_LP_SW_INT_ENA_M (LPINTR_LP_SW_INT_ENA_V << LPINTR_LP_SW_INT_ENA_S) +#define LPINTR_LP_SW_INT_ENA_V 0x00000001U +#define LPINTR_LP_SW_INT_ENA_S 31 + +/** LPINTR_SW_INT_CLR_REG register + * need_des + */ +#define LPINTR_SW_INT_CLR_REG (DR_REG_LPINTR_BASE + 0xc) +/** LPINTR_LP_SW_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPINTR_LP_SW_INT_CLR (BIT(31)) +#define LPINTR_LP_SW_INT_CLR_M (LPINTR_LP_SW_INT_CLR_V << LPINTR_LP_SW_INT_CLR_S) +#define LPINTR_LP_SW_INT_CLR_V 0x00000001U +#define LPINTR_LP_SW_INT_CLR_S 31 + +/** LPINTR_STATUS_REG register + * need_des + */ +#define LPINTR_STATUS_REG (DR_REG_LPINTR_BASE + 0x10) +/** LPINTR_LP_HUK_INTR_ST : RO; bitpos: [10]; default: 0; + * need_des + */ +#define LPINTR_LP_HUK_INTR_ST (BIT(10)) +#define LPINTR_LP_HUK_INTR_ST_M (LPINTR_LP_HUK_INTR_ST_V << LPINTR_LP_HUK_INTR_ST_S) +#define LPINTR_LP_HUK_INTR_ST_V 0x00000001U +#define LPINTR_LP_HUK_INTR_ST_S 10 +/** LPINTR_SYSREG_INTR_ST : RO; bitpos: [11]; default: 0; + * need_des + */ +#define LPINTR_SYSREG_INTR_ST (BIT(11)) +#define LPINTR_SYSREG_INTR_ST_M (LPINTR_SYSREG_INTR_ST_V << LPINTR_SYSREG_INTR_ST_S) +#define LPINTR_SYSREG_INTR_ST_V 0x00000001U +#define LPINTR_SYSREG_INTR_ST_S 11 +/** LPINTR_LP_SW_INTR_ST : RO; bitpos: [12]; default: 0; + * need_des + */ +#define LPINTR_LP_SW_INTR_ST (BIT(12)) +#define LPINTR_LP_SW_INTR_ST_M (LPINTR_LP_SW_INTR_ST_V << LPINTR_LP_SW_INTR_ST_S) +#define LPINTR_LP_SW_INTR_ST_V 0x00000001U +#define LPINTR_LP_SW_INTR_ST_S 12 +/** LPINTR_LP_EFUSE_INTR_ST : RO; bitpos: [13]; default: 0; + * need_des + */ +#define LPINTR_LP_EFUSE_INTR_ST (BIT(13)) +#define LPINTR_LP_EFUSE_INTR_ST_M (LPINTR_LP_EFUSE_INTR_ST_V << LPINTR_LP_EFUSE_INTR_ST_S) +#define LPINTR_LP_EFUSE_INTR_ST_V 0x00000001U +#define LPINTR_LP_EFUSE_INTR_ST_S 13 +/** LPINTR_LP_UART_INTR_ST : RO; bitpos: [14]; default: 0; + * need_des + */ +#define LPINTR_LP_UART_INTR_ST (BIT(14)) +#define LPINTR_LP_UART_INTR_ST_M (LPINTR_LP_UART_INTR_ST_V << LPINTR_LP_UART_INTR_ST_S) +#define LPINTR_LP_UART_INTR_ST_V 0x00000001U +#define LPINTR_LP_UART_INTR_ST_S 14 +/** LPINTR_LP_TSENS_INTR_ST : RO; bitpos: [15]; default: 0; + * need_des + */ +#define LPINTR_LP_TSENS_INTR_ST (BIT(15)) +#define LPINTR_LP_TSENS_INTR_ST_M (LPINTR_LP_TSENS_INTR_ST_V << LPINTR_LP_TSENS_INTR_ST_S) +#define LPINTR_LP_TSENS_INTR_ST_V 0x00000001U +#define LPINTR_LP_TSENS_INTR_ST_S 15 +/** LPINTR_LP_TOUCH_INTR_ST : RO; bitpos: [16]; default: 0; + * need_des + */ +#define LPINTR_LP_TOUCH_INTR_ST (BIT(16)) +#define LPINTR_LP_TOUCH_INTR_ST_M (LPINTR_LP_TOUCH_INTR_ST_V << LPINTR_LP_TOUCH_INTR_ST_S) +#define LPINTR_LP_TOUCH_INTR_ST_V 0x00000001U +#define LPINTR_LP_TOUCH_INTR_ST_S 16 +/** LPINTR_LP_SPI_INTR_ST : RO; bitpos: [17]; default: 0; + * need_des + */ +#define LPINTR_LP_SPI_INTR_ST (BIT(17)) +#define LPINTR_LP_SPI_INTR_ST_M (LPINTR_LP_SPI_INTR_ST_V << LPINTR_LP_SPI_INTR_ST_S) +#define LPINTR_LP_SPI_INTR_ST_V 0x00000001U +#define LPINTR_LP_SPI_INTR_ST_S 17 +/** LPINTR_LP_I2S_INTR_ST : RO; bitpos: [18]; default: 0; + * need_des + */ +#define LPINTR_LP_I2S_INTR_ST (BIT(18)) +#define LPINTR_LP_I2S_INTR_ST_M (LPINTR_LP_I2S_INTR_ST_V << LPINTR_LP_I2S_INTR_ST_S) +#define LPINTR_LP_I2S_INTR_ST_V 0x00000001U +#define LPINTR_LP_I2S_INTR_ST_S 18 +/** LPINTR_LP_I2C_INTR_ST : RO; bitpos: [19]; default: 0; + * need_des + */ +#define LPINTR_LP_I2C_INTR_ST (BIT(19)) +#define LPINTR_LP_I2C_INTR_ST_M (LPINTR_LP_I2C_INTR_ST_V << LPINTR_LP_I2C_INTR_ST_S) +#define LPINTR_LP_I2C_INTR_ST_V 0x00000001U +#define LPINTR_LP_I2C_INTR_ST_S 19 +/** LPINTR_LP_GPIO_INTR_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define LPINTR_LP_GPIO_INTR_ST (BIT(20)) +#define LPINTR_LP_GPIO_INTR_ST_M (LPINTR_LP_GPIO_INTR_ST_V << LPINTR_LP_GPIO_INTR_ST_S) +#define LPINTR_LP_GPIO_INTR_ST_V 0x00000001U +#define LPINTR_LP_GPIO_INTR_ST_S 20 +/** LPINTR_LP_ADC_INTR_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define LPINTR_LP_ADC_INTR_ST (BIT(21)) +#define LPINTR_LP_ADC_INTR_ST_M (LPINTR_LP_ADC_INTR_ST_V << LPINTR_LP_ADC_INTR_ST_S) +#define LPINTR_LP_ADC_INTR_ST_V 0x00000001U +#define LPINTR_LP_ADC_INTR_ST_S 21 +/** LPINTR_ANAPERI_INTR_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define LPINTR_ANAPERI_INTR_ST (BIT(22)) +#define LPINTR_ANAPERI_INTR_ST_M (LPINTR_ANAPERI_INTR_ST_V << LPINTR_ANAPERI_INTR_ST_S) +#define LPINTR_ANAPERI_INTR_ST_V 0x00000001U +#define LPINTR_ANAPERI_INTR_ST_S 22 +/** LPINTR_PMU_REG_1_INTR_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define LPINTR_PMU_REG_1_INTR_ST (BIT(23)) +#define LPINTR_PMU_REG_1_INTR_ST_M (LPINTR_PMU_REG_1_INTR_ST_V << LPINTR_PMU_REG_1_INTR_ST_S) +#define LPINTR_PMU_REG_1_INTR_ST_V 0x00000001U +#define LPINTR_PMU_REG_1_INTR_ST_S 23 +/** LPINTR_PMU_REG_0_INTR_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define LPINTR_PMU_REG_0_INTR_ST (BIT(24)) +#define LPINTR_PMU_REG_0_INTR_ST_M (LPINTR_PMU_REG_0_INTR_ST_V << LPINTR_PMU_REG_0_INTR_ST_S) +#define LPINTR_PMU_REG_0_INTR_ST_V 0x00000001U +#define LPINTR_PMU_REG_0_INTR_ST_S 24 +/** LPINTR_MB_LP_INTR_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define LPINTR_MB_LP_INTR_ST (BIT(25)) +#define LPINTR_MB_LP_INTR_ST_M (LPINTR_MB_LP_INTR_ST_V << LPINTR_MB_LP_INTR_ST_S) +#define LPINTR_MB_LP_INTR_ST_V 0x00000001U +#define LPINTR_MB_LP_INTR_ST_S 25 +/** LPINTR_MB_HP_INTR_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define LPINTR_MB_HP_INTR_ST (BIT(26)) +#define LPINTR_MB_HP_INTR_ST_M (LPINTR_MB_HP_INTR_ST_V << LPINTR_MB_HP_INTR_ST_S) +#define LPINTR_MB_HP_INTR_ST_V 0x00000001U +#define LPINTR_MB_HP_INTR_ST_S 26 +/** LPINTR_LP_TIMER_REG_1_INTR_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define LPINTR_LP_TIMER_REG_1_INTR_ST (BIT(27)) +#define LPINTR_LP_TIMER_REG_1_INTR_ST_M (LPINTR_LP_TIMER_REG_1_INTR_ST_V << LPINTR_LP_TIMER_REG_1_INTR_ST_S) +#define LPINTR_LP_TIMER_REG_1_INTR_ST_V 0x00000001U +#define LPINTR_LP_TIMER_REG_1_INTR_ST_S 27 +/** LPINTR_LP_TIMER_REG_0_INTR_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define LPINTR_LP_TIMER_REG_0_INTR_ST (BIT(28)) +#define LPINTR_LP_TIMER_REG_0_INTR_ST_M (LPINTR_LP_TIMER_REG_0_INTR_ST_V << LPINTR_LP_TIMER_REG_0_INTR_ST_S) +#define LPINTR_LP_TIMER_REG_0_INTR_ST_V 0x00000001U +#define LPINTR_LP_TIMER_REG_0_INTR_ST_S 28 +/** LPINTR_LP_WDT_INTR_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define LPINTR_LP_WDT_INTR_ST (BIT(29)) +#define LPINTR_LP_WDT_INTR_ST_M (LPINTR_LP_WDT_INTR_ST_V << LPINTR_LP_WDT_INTR_ST_S) +#define LPINTR_LP_WDT_INTR_ST_V 0x00000001U +#define LPINTR_LP_WDT_INTR_ST_S 29 +/** LPINTR_LP_RTC_INTR_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LPINTR_LP_RTC_INTR_ST (BIT(30)) +#define LPINTR_LP_RTC_INTR_ST_M (LPINTR_LP_RTC_INTR_ST_V << LPINTR_LP_RTC_INTR_ST_S) +#define LPINTR_LP_RTC_INTR_ST_V 0x00000001U +#define LPINTR_LP_RTC_INTR_ST_S 30 +/** LPINTR_HP_INTR_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LPINTR_HP_INTR_ST (BIT(31)) +#define LPINTR_HP_INTR_ST_M (LPINTR_HP_INTR_ST_V << LPINTR_HP_INTR_ST_S) +#define LPINTR_HP_INTR_ST_V 0x00000001U +#define LPINTR_HP_INTR_ST_S 31 + +/** LPINTR_DATE_REG register + * need_des + */ +#define LPINTR_DATE_REG (DR_REG_LPINTR_BASE + 0x3fc) +/** LPINTR_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPINTR_CLK_EN (BIT(31)) +#define LPINTR_CLK_EN_M (LPINTR_CLK_EN_V << LPINTR_CLK_EN_S) +#define LPINTR_CLK_EN_V 0x00000001U +#define LPINTR_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_intr_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_intr_struct.h new file mode 100644 index 0000000000..7afbf69953 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_intr_struct.h @@ -0,0 +1,205 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of sw_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sw_int_raw : R/W/WTC; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sw_int_raw:1; + }; + uint32_t val; +} lpintr_sw_int_raw_reg_t; + +/** Type of sw_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sw_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sw_int_st:1; + }; + uint32_t val; +} lpintr_sw_int_st_reg_t; + +/** Type of sw_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sw_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sw_int_ena:1; + }; + uint32_t val; +} lpintr_sw_int_ena_reg_t; + +/** Type of sw_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sw_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sw_int_clr:1; + }; + uint32_t val; +} lpintr_sw_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** lp_huk_intr_st : RO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_huk_intr_st:1; + /** sysreg_intr_st : RO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t sysreg_intr_st:1; + /** lp_sw_intr_st : RO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t lp_sw_intr_st:1; + /** lp_efuse_intr_st : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_efuse_intr_st:1; + /** lp_uart_intr_st : RO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t lp_uart_intr_st:1; + /** lp_tsens_intr_st : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t lp_tsens_intr_st:1; + /** lp_touch_intr_st : RO; bitpos: [16]; default: 0; + * need_des + */ + uint32_t lp_touch_intr_st:1; + /** lp_spi_intr_st : RO; bitpos: [17]; default: 0; + * need_des + */ + uint32_t lp_spi_intr_st:1; + /** lp_i2s_intr_st : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_i2s_intr_st:1; + /** lp_i2c_intr_st : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_i2c_intr_st:1; + /** lp_gpio_intr_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_gpio_intr_st:1; + /** lp_adc_intr_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t lp_adc_intr_st:1; + /** anaperi_intr_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t anaperi_intr_st:1; + /** pmu_reg_1_intr_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t pmu_reg_1_intr_st:1; + /** pmu_reg_0_intr_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t pmu_reg_0_intr_st:1; + /** mb_lp_intr_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t mb_lp_intr_st:1; + /** mb_hp_intr_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t mb_hp_intr_st:1; + /** lp_timer_reg_1_intr_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_timer_reg_1_intr_st:1; + /** lp_timer_reg_0_intr_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_timer_reg_0_intr_st:1; + /** lp_wdt_intr_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_wdt_intr_st:1; + /** lp_rtc_intr_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_rtc_intr_st:1; + /** hp_intr_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_intr_st:1; + }; + uint32_t val; +} lpintr_status_reg_t; + + +/** Group: configure_register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpintr_date_reg_t; + + +typedef struct { + volatile lpintr_sw_int_raw_reg_t sw_int_raw; + volatile lpintr_sw_int_st_reg_t sw_int_st; + volatile lpintr_sw_int_ena_reg_t sw_int_ena; + volatile lpintr_sw_int_clr_reg_t sw_int_clr; + volatile lpintr_status_reg_t status; + uint32_t reserved_014[250]; + volatile lpintr_date_reg_t date; +} lpintr_dev_t; + +extern lpintr_dev_t LP_INTR; + +#ifndef __cplusplus +_Static_assert(sizeof(lpintr_dev_t) == 0x400, "Invalid size of lpintr_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_reg.h new file mode 100644 index 0000000000..de9f270b78 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_reg.h @@ -0,0 +1,1283 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_IOMUX_CLK_EN_REG register + * Reserved + */ +#define LP_IOMUX_CLK_EN_REG (DR_REG_LP_IOMUX_BASE + 0x0) +/** LP_IOMUX_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Reserved + */ +#define LP_IOMUX_REG_CLK_EN (BIT(0)) +#define LP_IOMUX_REG_CLK_EN_M (LP_IOMUX_REG_CLK_EN_V << LP_IOMUX_REG_CLK_EN_S) +#define LP_IOMUX_REG_CLK_EN_V 0x00000001U +#define LP_IOMUX_REG_CLK_EN_S 0 + +/** LP_IOMUX_VER_DATE_REG register + * Reserved + */ +#define LP_IOMUX_VER_DATE_REG (DR_REG_LP_IOMUX_BASE + 0x4) +/** LP_IOMUX_REG_VER_DATE : R/W; bitpos: [27:0]; default: 2294547; + * Reserved + */ +#define LP_IOMUX_REG_VER_DATE 0x0FFFFFFFU +#define LP_IOMUX_REG_VER_DATE_M (LP_IOMUX_REG_VER_DATE_V << LP_IOMUX_REG_VER_DATE_S) +#define LP_IOMUX_REG_VER_DATE_V 0x0FFFFFFFU +#define LP_IOMUX_REG_VER_DATE_S 0 + +/** LP_IOMUX_PAD0_REG register + * Reserved + */ +#define LP_IOMUX_PAD0_REG (DR_REG_LP_IOMUX_BASE + 0x8) +/** LP_IOMUX_REG_PAD0_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD0_DRV 0x00000003U +#define LP_IOMUX_REG_PAD0_DRV_M (LP_IOMUX_REG_PAD0_DRV_V << LP_IOMUX_REG_PAD0_DRV_S) +#define LP_IOMUX_REG_PAD0_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD0_DRV_S 0 +/** LP_IOMUX_REG_PAD0_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD0_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD0_RDE_M (LP_IOMUX_REG_PAD0_RDE_V << LP_IOMUX_REG_PAD0_RDE_S) +#define LP_IOMUX_REG_PAD0_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD0_RDE_S 2 +/** LP_IOMUX_REG_PAD0_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD0_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD0_RUE_M (LP_IOMUX_REG_PAD0_RUE_V << LP_IOMUX_REG_PAD0_RUE_S) +#define LP_IOMUX_REG_PAD0_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD0_RUE_S 3 +/** LP_IOMUX_REG_PAD0_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD0_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD0_MUX_SEL_M (LP_IOMUX_REG_PAD0_MUX_SEL_V << LP_IOMUX_REG_PAD0_MUX_SEL_S) +#define LP_IOMUX_REG_PAD0_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD0_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD0_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD0_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD0_FUN_SEL_M (LP_IOMUX_REG_PAD0_FUN_SEL_V << LP_IOMUX_REG_PAD0_FUN_SEL_S) +#define LP_IOMUX_REG_PAD0_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD0_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD0_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD0_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD0_SLP_SEL_M (LP_IOMUX_REG_PAD0_SLP_SEL_V << LP_IOMUX_REG_PAD0_SLP_SEL_S) +#define LP_IOMUX_REG_PAD0_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD0_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD0_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD0_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD0_SLP_IE_M (LP_IOMUX_REG_PAD0_SLP_IE_V << LP_IOMUX_REG_PAD0_SLP_IE_S) +#define LP_IOMUX_REG_PAD0_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD0_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD0_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD0_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD0_SLP_OE_M (LP_IOMUX_REG_PAD0_SLP_OE_V << LP_IOMUX_REG_PAD0_SLP_OE_S) +#define LP_IOMUX_REG_PAD0_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD0_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD0_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD0_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD0_FUN_IE_M (LP_IOMUX_REG_PAD0_FUN_IE_V << LP_IOMUX_REG_PAD0_FUN_IE_S) +#define LP_IOMUX_REG_PAD0_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD0_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD0_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD0_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD0_FILTER_EN_M (LP_IOMUX_REG_PAD0_FILTER_EN_V << LP_IOMUX_REG_PAD0_FILTER_EN_S) +#define LP_IOMUX_REG_PAD0_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD0_FILTER_EN_S 11 + +/** LP_IOMUX_PAD1_REG register + * Reserved + */ +#define LP_IOMUX_PAD1_REG (DR_REG_LP_IOMUX_BASE + 0xc) +/** LP_IOMUX_REG_PAD1_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD1_DRV 0x00000003U +#define LP_IOMUX_REG_PAD1_DRV_M (LP_IOMUX_REG_PAD1_DRV_V << LP_IOMUX_REG_PAD1_DRV_S) +#define LP_IOMUX_REG_PAD1_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD1_DRV_S 0 +/** LP_IOMUX_REG_PAD1_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD1_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD1_RDE_M (LP_IOMUX_REG_PAD1_RDE_V << LP_IOMUX_REG_PAD1_RDE_S) +#define LP_IOMUX_REG_PAD1_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD1_RDE_S 2 +/** LP_IOMUX_REG_PAD1_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD1_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD1_RUE_M (LP_IOMUX_REG_PAD1_RUE_V << LP_IOMUX_REG_PAD1_RUE_S) +#define LP_IOMUX_REG_PAD1_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD1_RUE_S 3 +/** LP_IOMUX_REG_PAD1_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD1_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD1_MUX_SEL_M (LP_IOMUX_REG_PAD1_MUX_SEL_V << LP_IOMUX_REG_PAD1_MUX_SEL_S) +#define LP_IOMUX_REG_PAD1_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD1_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD1_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD1_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD1_FUN_SEL_M (LP_IOMUX_REG_PAD1_FUN_SEL_V << LP_IOMUX_REG_PAD1_FUN_SEL_S) +#define LP_IOMUX_REG_PAD1_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD1_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD1_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD1_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD1_SLP_SEL_M (LP_IOMUX_REG_PAD1_SLP_SEL_V << LP_IOMUX_REG_PAD1_SLP_SEL_S) +#define LP_IOMUX_REG_PAD1_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD1_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD1_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD1_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD1_SLP_IE_M (LP_IOMUX_REG_PAD1_SLP_IE_V << LP_IOMUX_REG_PAD1_SLP_IE_S) +#define LP_IOMUX_REG_PAD1_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD1_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD1_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD1_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD1_SLP_OE_M (LP_IOMUX_REG_PAD1_SLP_OE_V << LP_IOMUX_REG_PAD1_SLP_OE_S) +#define LP_IOMUX_REG_PAD1_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD1_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD1_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD1_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD1_FUN_IE_M (LP_IOMUX_REG_PAD1_FUN_IE_V << LP_IOMUX_REG_PAD1_FUN_IE_S) +#define LP_IOMUX_REG_PAD1_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD1_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD1_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD1_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD1_FILTER_EN_M (LP_IOMUX_REG_PAD1_FILTER_EN_V << LP_IOMUX_REG_PAD1_FILTER_EN_S) +#define LP_IOMUX_REG_PAD1_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD1_FILTER_EN_S 11 + +/** LP_IOMUX_PAD2_REG register + * Reserved + */ +#define LP_IOMUX_PAD2_REG (DR_REG_LP_IOMUX_BASE + 0x10) +/** LP_IOMUX_REG_PAD2_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD2_DRV 0x00000003U +#define LP_IOMUX_REG_PAD2_DRV_M (LP_IOMUX_REG_PAD2_DRV_V << LP_IOMUX_REG_PAD2_DRV_S) +#define LP_IOMUX_REG_PAD2_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD2_DRV_S 0 +/** LP_IOMUX_REG_PAD2_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD2_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD2_RDE_M (LP_IOMUX_REG_PAD2_RDE_V << LP_IOMUX_REG_PAD2_RDE_S) +#define LP_IOMUX_REG_PAD2_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD2_RDE_S 2 +/** LP_IOMUX_REG_PAD2_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD2_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD2_RUE_M (LP_IOMUX_REG_PAD2_RUE_V << LP_IOMUX_REG_PAD2_RUE_S) +#define LP_IOMUX_REG_PAD2_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD2_RUE_S 3 +/** LP_IOMUX_REG_PAD2_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD2_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD2_MUX_SEL_M (LP_IOMUX_REG_PAD2_MUX_SEL_V << LP_IOMUX_REG_PAD2_MUX_SEL_S) +#define LP_IOMUX_REG_PAD2_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD2_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD2_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD2_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD2_FUN_SEL_M (LP_IOMUX_REG_PAD2_FUN_SEL_V << LP_IOMUX_REG_PAD2_FUN_SEL_S) +#define LP_IOMUX_REG_PAD2_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD2_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD2_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD2_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD2_SLP_SEL_M (LP_IOMUX_REG_PAD2_SLP_SEL_V << LP_IOMUX_REG_PAD2_SLP_SEL_S) +#define LP_IOMUX_REG_PAD2_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD2_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD2_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD2_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD2_SLP_IE_M (LP_IOMUX_REG_PAD2_SLP_IE_V << LP_IOMUX_REG_PAD2_SLP_IE_S) +#define LP_IOMUX_REG_PAD2_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD2_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD2_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD2_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD2_SLP_OE_M (LP_IOMUX_REG_PAD2_SLP_OE_V << LP_IOMUX_REG_PAD2_SLP_OE_S) +#define LP_IOMUX_REG_PAD2_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD2_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD2_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD2_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD2_FUN_IE_M (LP_IOMUX_REG_PAD2_FUN_IE_V << LP_IOMUX_REG_PAD2_FUN_IE_S) +#define LP_IOMUX_REG_PAD2_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD2_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD2_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD2_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD2_FILTER_EN_M (LP_IOMUX_REG_PAD2_FILTER_EN_V << LP_IOMUX_REG_PAD2_FILTER_EN_S) +#define LP_IOMUX_REG_PAD2_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD2_FILTER_EN_S 11 + +/** LP_IOMUX_PAD3_REG register + * Reserved + */ +#define LP_IOMUX_PAD3_REG (DR_REG_LP_IOMUX_BASE + 0x14) +/** LP_IOMUX_REG_PAD3_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD3_DRV 0x00000003U +#define LP_IOMUX_REG_PAD3_DRV_M (LP_IOMUX_REG_PAD3_DRV_V << LP_IOMUX_REG_PAD3_DRV_S) +#define LP_IOMUX_REG_PAD3_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD3_DRV_S 0 +/** LP_IOMUX_REG_PAD3_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD3_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD3_RDE_M (LP_IOMUX_REG_PAD3_RDE_V << LP_IOMUX_REG_PAD3_RDE_S) +#define LP_IOMUX_REG_PAD3_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD3_RDE_S 2 +/** LP_IOMUX_REG_PAD3_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD3_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD3_RUE_M (LP_IOMUX_REG_PAD3_RUE_V << LP_IOMUX_REG_PAD3_RUE_S) +#define LP_IOMUX_REG_PAD3_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD3_RUE_S 3 +/** LP_IOMUX_REG_PAD3_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD3_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD3_MUX_SEL_M (LP_IOMUX_REG_PAD3_MUX_SEL_V << LP_IOMUX_REG_PAD3_MUX_SEL_S) +#define LP_IOMUX_REG_PAD3_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD3_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD3_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD3_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD3_FUN_SEL_M (LP_IOMUX_REG_PAD3_FUN_SEL_V << LP_IOMUX_REG_PAD3_FUN_SEL_S) +#define LP_IOMUX_REG_PAD3_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD3_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD3_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD3_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD3_SLP_SEL_M (LP_IOMUX_REG_PAD3_SLP_SEL_V << LP_IOMUX_REG_PAD3_SLP_SEL_S) +#define LP_IOMUX_REG_PAD3_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD3_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD3_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD3_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD3_SLP_IE_M (LP_IOMUX_REG_PAD3_SLP_IE_V << LP_IOMUX_REG_PAD3_SLP_IE_S) +#define LP_IOMUX_REG_PAD3_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD3_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD3_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD3_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD3_SLP_OE_M (LP_IOMUX_REG_PAD3_SLP_OE_V << LP_IOMUX_REG_PAD3_SLP_OE_S) +#define LP_IOMUX_REG_PAD3_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD3_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD3_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD3_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD3_FUN_IE_M (LP_IOMUX_REG_PAD3_FUN_IE_V << LP_IOMUX_REG_PAD3_FUN_IE_S) +#define LP_IOMUX_REG_PAD3_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD3_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD3_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD3_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD3_FILTER_EN_M (LP_IOMUX_REG_PAD3_FILTER_EN_V << LP_IOMUX_REG_PAD3_FILTER_EN_S) +#define LP_IOMUX_REG_PAD3_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD3_FILTER_EN_S 11 + +/** LP_IOMUX_PAD4_REG register + * Reserved + */ +#define LP_IOMUX_PAD4_REG (DR_REG_LP_IOMUX_BASE + 0x18) +/** LP_IOMUX_REG_PAD4_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD4_DRV 0x00000003U +#define LP_IOMUX_REG_PAD4_DRV_M (LP_IOMUX_REG_PAD4_DRV_V << LP_IOMUX_REG_PAD4_DRV_S) +#define LP_IOMUX_REG_PAD4_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD4_DRV_S 0 +/** LP_IOMUX_REG_PAD4_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD4_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD4_RDE_M (LP_IOMUX_REG_PAD4_RDE_V << LP_IOMUX_REG_PAD4_RDE_S) +#define LP_IOMUX_REG_PAD4_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD4_RDE_S 2 +/** LP_IOMUX_REG_PAD4_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD4_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD4_RUE_M (LP_IOMUX_REG_PAD4_RUE_V << LP_IOMUX_REG_PAD4_RUE_S) +#define LP_IOMUX_REG_PAD4_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD4_RUE_S 3 +/** LP_IOMUX_REG_PAD4_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD4_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD4_MUX_SEL_M (LP_IOMUX_REG_PAD4_MUX_SEL_V << LP_IOMUX_REG_PAD4_MUX_SEL_S) +#define LP_IOMUX_REG_PAD4_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD4_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD4_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD4_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD4_FUN_SEL_M (LP_IOMUX_REG_PAD4_FUN_SEL_V << LP_IOMUX_REG_PAD4_FUN_SEL_S) +#define LP_IOMUX_REG_PAD4_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD4_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD4_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD4_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD4_SLP_SEL_M (LP_IOMUX_REG_PAD4_SLP_SEL_V << LP_IOMUX_REG_PAD4_SLP_SEL_S) +#define LP_IOMUX_REG_PAD4_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD4_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD4_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD4_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD4_SLP_IE_M (LP_IOMUX_REG_PAD4_SLP_IE_V << LP_IOMUX_REG_PAD4_SLP_IE_S) +#define LP_IOMUX_REG_PAD4_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD4_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD4_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD4_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD4_SLP_OE_M (LP_IOMUX_REG_PAD4_SLP_OE_V << LP_IOMUX_REG_PAD4_SLP_OE_S) +#define LP_IOMUX_REG_PAD4_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD4_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD4_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD4_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD4_FUN_IE_M (LP_IOMUX_REG_PAD4_FUN_IE_V << LP_IOMUX_REG_PAD4_FUN_IE_S) +#define LP_IOMUX_REG_PAD4_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD4_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD4_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD4_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD4_FILTER_EN_M (LP_IOMUX_REG_PAD4_FILTER_EN_V << LP_IOMUX_REG_PAD4_FILTER_EN_S) +#define LP_IOMUX_REG_PAD4_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD4_FILTER_EN_S 11 + +/** LP_IOMUX_PAD5_REG register + * Reserved + */ +#define LP_IOMUX_PAD5_REG (DR_REG_LP_IOMUX_BASE + 0x1c) +/** LP_IOMUX_REG_PAD5_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD5_DRV 0x00000003U +#define LP_IOMUX_REG_PAD5_DRV_M (LP_IOMUX_REG_PAD5_DRV_V << LP_IOMUX_REG_PAD5_DRV_S) +#define LP_IOMUX_REG_PAD5_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD5_DRV_S 0 +/** LP_IOMUX_REG_PAD5_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD5_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD5_RDE_M (LP_IOMUX_REG_PAD5_RDE_V << LP_IOMUX_REG_PAD5_RDE_S) +#define LP_IOMUX_REG_PAD5_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD5_RDE_S 2 +/** LP_IOMUX_REG_PAD5_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD5_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD5_RUE_M (LP_IOMUX_REG_PAD5_RUE_V << LP_IOMUX_REG_PAD5_RUE_S) +#define LP_IOMUX_REG_PAD5_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD5_RUE_S 3 +/** LP_IOMUX_REG_PAD5_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD5_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD5_MUX_SEL_M (LP_IOMUX_REG_PAD5_MUX_SEL_V << LP_IOMUX_REG_PAD5_MUX_SEL_S) +#define LP_IOMUX_REG_PAD5_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD5_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD5_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD5_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD5_FUN_SEL_M (LP_IOMUX_REG_PAD5_FUN_SEL_V << LP_IOMUX_REG_PAD5_FUN_SEL_S) +#define LP_IOMUX_REG_PAD5_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD5_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD5_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD5_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD5_SLP_SEL_M (LP_IOMUX_REG_PAD5_SLP_SEL_V << LP_IOMUX_REG_PAD5_SLP_SEL_S) +#define LP_IOMUX_REG_PAD5_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD5_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD5_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD5_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD5_SLP_IE_M (LP_IOMUX_REG_PAD5_SLP_IE_V << LP_IOMUX_REG_PAD5_SLP_IE_S) +#define LP_IOMUX_REG_PAD5_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD5_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD5_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD5_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD5_SLP_OE_M (LP_IOMUX_REG_PAD5_SLP_OE_V << LP_IOMUX_REG_PAD5_SLP_OE_S) +#define LP_IOMUX_REG_PAD5_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD5_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD5_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD5_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD5_FUN_IE_M (LP_IOMUX_REG_PAD5_FUN_IE_V << LP_IOMUX_REG_PAD5_FUN_IE_S) +#define LP_IOMUX_REG_PAD5_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD5_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD5_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD5_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD5_FILTER_EN_M (LP_IOMUX_REG_PAD5_FILTER_EN_V << LP_IOMUX_REG_PAD5_FILTER_EN_S) +#define LP_IOMUX_REG_PAD5_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD5_FILTER_EN_S 11 + +/** LP_IOMUX_PAD6_REG register + * Reserved + */ +#define LP_IOMUX_PAD6_REG (DR_REG_LP_IOMUX_BASE + 0x20) +/** LP_IOMUX_REG_PAD6_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD6_DRV 0x00000003U +#define LP_IOMUX_REG_PAD6_DRV_M (LP_IOMUX_REG_PAD6_DRV_V << LP_IOMUX_REG_PAD6_DRV_S) +#define LP_IOMUX_REG_PAD6_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD6_DRV_S 0 +/** LP_IOMUX_REG_PAD6_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD6_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD6_RDE_M (LP_IOMUX_REG_PAD6_RDE_V << LP_IOMUX_REG_PAD6_RDE_S) +#define LP_IOMUX_REG_PAD6_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD6_RDE_S 2 +/** LP_IOMUX_REG_PAD6_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD6_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD6_RUE_M (LP_IOMUX_REG_PAD6_RUE_V << LP_IOMUX_REG_PAD6_RUE_S) +#define LP_IOMUX_REG_PAD6_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD6_RUE_S 3 +/** LP_IOMUX_REG_PAD6_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD6_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD6_MUX_SEL_M (LP_IOMUX_REG_PAD6_MUX_SEL_V << LP_IOMUX_REG_PAD6_MUX_SEL_S) +#define LP_IOMUX_REG_PAD6_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD6_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD6_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD6_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD6_FUN_SEL_M (LP_IOMUX_REG_PAD6_FUN_SEL_V << LP_IOMUX_REG_PAD6_FUN_SEL_S) +#define LP_IOMUX_REG_PAD6_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD6_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD6_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD6_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD6_SLP_SEL_M (LP_IOMUX_REG_PAD6_SLP_SEL_V << LP_IOMUX_REG_PAD6_SLP_SEL_S) +#define LP_IOMUX_REG_PAD6_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD6_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD6_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD6_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD6_SLP_IE_M (LP_IOMUX_REG_PAD6_SLP_IE_V << LP_IOMUX_REG_PAD6_SLP_IE_S) +#define LP_IOMUX_REG_PAD6_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD6_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD6_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD6_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD6_SLP_OE_M (LP_IOMUX_REG_PAD6_SLP_OE_V << LP_IOMUX_REG_PAD6_SLP_OE_S) +#define LP_IOMUX_REG_PAD6_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD6_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD6_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD6_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD6_FUN_IE_M (LP_IOMUX_REG_PAD6_FUN_IE_V << LP_IOMUX_REG_PAD6_FUN_IE_S) +#define LP_IOMUX_REG_PAD6_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD6_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD6_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD6_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD6_FILTER_EN_M (LP_IOMUX_REG_PAD6_FILTER_EN_V << LP_IOMUX_REG_PAD6_FILTER_EN_S) +#define LP_IOMUX_REG_PAD6_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD6_FILTER_EN_S 11 + +/** LP_IOMUX_PAD7_REG register + * Reserved + */ +#define LP_IOMUX_PAD7_REG (DR_REG_LP_IOMUX_BASE + 0x24) +/** LP_IOMUX_REG_PAD7_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD7_DRV 0x00000003U +#define LP_IOMUX_REG_PAD7_DRV_M (LP_IOMUX_REG_PAD7_DRV_V << LP_IOMUX_REG_PAD7_DRV_S) +#define LP_IOMUX_REG_PAD7_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD7_DRV_S 0 +/** LP_IOMUX_REG_PAD7_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD7_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD7_RDE_M (LP_IOMUX_REG_PAD7_RDE_V << LP_IOMUX_REG_PAD7_RDE_S) +#define LP_IOMUX_REG_PAD7_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD7_RDE_S 2 +/** LP_IOMUX_REG_PAD7_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD7_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD7_RUE_M (LP_IOMUX_REG_PAD7_RUE_V << LP_IOMUX_REG_PAD7_RUE_S) +#define LP_IOMUX_REG_PAD7_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD7_RUE_S 3 +/** LP_IOMUX_REG_PAD7_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD7_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD7_MUX_SEL_M (LP_IOMUX_REG_PAD7_MUX_SEL_V << LP_IOMUX_REG_PAD7_MUX_SEL_S) +#define LP_IOMUX_REG_PAD7_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD7_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD7_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD7_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD7_FUN_SEL_M (LP_IOMUX_REG_PAD7_FUN_SEL_V << LP_IOMUX_REG_PAD7_FUN_SEL_S) +#define LP_IOMUX_REG_PAD7_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD7_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD7_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD7_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD7_SLP_SEL_M (LP_IOMUX_REG_PAD7_SLP_SEL_V << LP_IOMUX_REG_PAD7_SLP_SEL_S) +#define LP_IOMUX_REG_PAD7_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD7_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD7_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD7_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD7_SLP_IE_M (LP_IOMUX_REG_PAD7_SLP_IE_V << LP_IOMUX_REG_PAD7_SLP_IE_S) +#define LP_IOMUX_REG_PAD7_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD7_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD7_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD7_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD7_SLP_OE_M (LP_IOMUX_REG_PAD7_SLP_OE_V << LP_IOMUX_REG_PAD7_SLP_OE_S) +#define LP_IOMUX_REG_PAD7_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD7_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD7_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD7_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD7_FUN_IE_M (LP_IOMUX_REG_PAD7_FUN_IE_V << LP_IOMUX_REG_PAD7_FUN_IE_S) +#define LP_IOMUX_REG_PAD7_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD7_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD7_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD7_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD7_FILTER_EN_M (LP_IOMUX_REG_PAD7_FILTER_EN_V << LP_IOMUX_REG_PAD7_FILTER_EN_S) +#define LP_IOMUX_REG_PAD7_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD7_FILTER_EN_S 11 + +/** LP_IOMUX_PAD8_REG register + * Reserved + */ +#define LP_IOMUX_PAD8_REG (DR_REG_LP_IOMUX_BASE + 0x28) +/** LP_IOMUX_REG_PAD8_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD8_DRV 0x00000003U +#define LP_IOMUX_REG_PAD8_DRV_M (LP_IOMUX_REG_PAD8_DRV_V << LP_IOMUX_REG_PAD8_DRV_S) +#define LP_IOMUX_REG_PAD8_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD8_DRV_S 0 +/** LP_IOMUX_REG_PAD8_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD8_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD8_RDE_M (LP_IOMUX_REG_PAD8_RDE_V << LP_IOMUX_REG_PAD8_RDE_S) +#define LP_IOMUX_REG_PAD8_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD8_RDE_S 2 +/** LP_IOMUX_REG_PAD8_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD8_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD8_RUE_M (LP_IOMUX_REG_PAD8_RUE_V << LP_IOMUX_REG_PAD8_RUE_S) +#define LP_IOMUX_REG_PAD8_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD8_RUE_S 3 +/** LP_IOMUX_REG_PAD8_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD8_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD8_MUX_SEL_M (LP_IOMUX_REG_PAD8_MUX_SEL_V << LP_IOMUX_REG_PAD8_MUX_SEL_S) +#define LP_IOMUX_REG_PAD8_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD8_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD8_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD8_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD8_FUN_SEL_M (LP_IOMUX_REG_PAD8_FUN_SEL_V << LP_IOMUX_REG_PAD8_FUN_SEL_S) +#define LP_IOMUX_REG_PAD8_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD8_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD8_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD8_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD8_SLP_SEL_M (LP_IOMUX_REG_PAD8_SLP_SEL_V << LP_IOMUX_REG_PAD8_SLP_SEL_S) +#define LP_IOMUX_REG_PAD8_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD8_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD8_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD8_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD8_SLP_IE_M (LP_IOMUX_REG_PAD8_SLP_IE_V << LP_IOMUX_REG_PAD8_SLP_IE_S) +#define LP_IOMUX_REG_PAD8_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD8_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD8_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD8_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD8_SLP_OE_M (LP_IOMUX_REG_PAD8_SLP_OE_V << LP_IOMUX_REG_PAD8_SLP_OE_S) +#define LP_IOMUX_REG_PAD8_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD8_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD8_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD8_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD8_FUN_IE_M (LP_IOMUX_REG_PAD8_FUN_IE_V << LP_IOMUX_REG_PAD8_FUN_IE_S) +#define LP_IOMUX_REG_PAD8_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD8_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD8_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD8_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD8_FILTER_EN_M (LP_IOMUX_REG_PAD8_FILTER_EN_V << LP_IOMUX_REG_PAD8_FILTER_EN_S) +#define LP_IOMUX_REG_PAD8_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD8_FILTER_EN_S 11 + +/** LP_IOMUX_PAD9_REG register + * Reserved + */ +#define LP_IOMUX_PAD9_REG (DR_REG_LP_IOMUX_BASE + 0x2c) +/** LP_IOMUX_REG_PAD9_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD9_DRV 0x00000003U +#define LP_IOMUX_REG_PAD9_DRV_M (LP_IOMUX_REG_PAD9_DRV_V << LP_IOMUX_REG_PAD9_DRV_S) +#define LP_IOMUX_REG_PAD9_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD9_DRV_S 0 +/** LP_IOMUX_REG_PAD9_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD9_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD9_RDE_M (LP_IOMUX_REG_PAD9_RDE_V << LP_IOMUX_REG_PAD9_RDE_S) +#define LP_IOMUX_REG_PAD9_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD9_RDE_S 2 +/** LP_IOMUX_REG_PAD9_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD9_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD9_RUE_M (LP_IOMUX_REG_PAD9_RUE_V << LP_IOMUX_REG_PAD9_RUE_S) +#define LP_IOMUX_REG_PAD9_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD9_RUE_S 3 +/** LP_IOMUX_REG_PAD9_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD9_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD9_MUX_SEL_M (LP_IOMUX_REG_PAD9_MUX_SEL_V << LP_IOMUX_REG_PAD9_MUX_SEL_S) +#define LP_IOMUX_REG_PAD9_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD9_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD9_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD9_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD9_FUN_SEL_M (LP_IOMUX_REG_PAD9_FUN_SEL_V << LP_IOMUX_REG_PAD9_FUN_SEL_S) +#define LP_IOMUX_REG_PAD9_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD9_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD9_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD9_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD9_SLP_SEL_M (LP_IOMUX_REG_PAD9_SLP_SEL_V << LP_IOMUX_REG_PAD9_SLP_SEL_S) +#define LP_IOMUX_REG_PAD9_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD9_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD9_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD9_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD9_SLP_IE_M (LP_IOMUX_REG_PAD9_SLP_IE_V << LP_IOMUX_REG_PAD9_SLP_IE_S) +#define LP_IOMUX_REG_PAD9_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD9_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD9_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD9_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD9_SLP_OE_M (LP_IOMUX_REG_PAD9_SLP_OE_V << LP_IOMUX_REG_PAD9_SLP_OE_S) +#define LP_IOMUX_REG_PAD9_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD9_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD9_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD9_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD9_FUN_IE_M (LP_IOMUX_REG_PAD9_FUN_IE_V << LP_IOMUX_REG_PAD9_FUN_IE_S) +#define LP_IOMUX_REG_PAD9_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD9_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD9_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD9_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD9_FILTER_EN_M (LP_IOMUX_REG_PAD9_FILTER_EN_V << LP_IOMUX_REG_PAD9_FILTER_EN_S) +#define LP_IOMUX_REG_PAD9_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD9_FILTER_EN_S 11 + +/** LP_IOMUX_PAD10_REG register + * Reserved + */ +#define LP_IOMUX_PAD10_REG (DR_REG_LP_IOMUX_BASE + 0x30) +/** LP_IOMUX_REG_PAD10_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD10_DRV 0x00000003U +#define LP_IOMUX_REG_PAD10_DRV_M (LP_IOMUX_REG_PAD10_DRV_V << LP_IOMUX_REG_PAD10_DRV_S) +#define LP_IOMUX_REG_PAD10_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD10_DRV_S 0 +/** LP_IOMUX_REG_PAD10_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD10_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD10_RDE_M (LP_IOMUX_REG_PAD10_RDE_V << LP_IOMUX_REG_PAD10_RDE_S) +#define LP_IOMUX_REG_PAD10_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD10_RDE_S 2 +/** LP_IOMUX_REG_PAD10_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD10_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD10_RUE_M (LP_IOMUX_REG_PAD10_RUE_V << LP_IOMUX_REG_PAD10_RUE_S) +#define LP_IOMUX_REG_PAD10_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD10_RUE_S 3 +/** LP_IOMUX_REG_PAD10_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD10_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD10_MUX_SEL_M (LP_IOMUX_REG_PAD10_MUX_SEL_V << LP_IOMUX_REG_PAD10_MUX_SEL_S) +#define LP_IOMUX_REG_PAD10_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD10_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD10_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD10_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD10_FUN_SEL_M (LP_IOMUX_REG_PAD10_FUN_SEL_V << LP_IOMUX_REG_PAD10_FUN_SEL_S) +#define LP_IOMUX_REG_PAD10_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD10_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD10_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD10_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD10_SLP_SEL_M (LP_IOMUX_REG_PAD10_SLP_SEL_V << LP_IOMUX_REG_PAD10_SLP_SEL_S) +#define LP_IOMUX_REG_PAD10_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD10_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD10_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD10_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD10_SLP_IE_M (LP_IOMUX_REG_PAD10_SLP_IE_V << LP_IOMUX_REG_PAD10_SLP_IE_S) +#define LP_IOMUX_REG_PAD10_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD10_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD10_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD10_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD10_SLP_OE_M (LP_IOMUX_REG_PAD10_SLP_OE_V << LP_IOMUX_REG_PAD10_SLP_OE_S) +#define LP_IOMUX_REG_PAD10_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD10_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD10_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD10_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD10_FUN_IE_M (LP_IOMUX_REG_PAD10_FUN_IE_V << LP_IOMUX_REG_PAD10_FUN_IE_S) +#define LP_IOMUX_REG_PAD10_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD10_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD10_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD10_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD10_FILTER_EN_M (LP_IOMUX_REG_PAD10_FILTER_EN_V << LP_IOMUX_REG_PAD10_FILTER_EN_S) +#define LP_IOMUX_REG_PAD10_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD10_FILTER_EN_S 11 + +/** LP_IOMUX_PAD11_REG register + * Reserved + */ +#define LP_IOMUX_PAD11_REG (DR_REG_LP_IOMUX_BASE + 0x34) +/** LP_IOMUX_REG_PAD11_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD11_DRV 0x00000003U +#define LP_IOMUX_REG_PAD11_DRV_M (LP_IOMUX_REG_PAD11_DRV_V << LP_IOMUX_REG_PAD11_DRV_S) +#define LP_IOMUX_REG_PAD11_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD11_DRV_S 0 +/** LP_IOMUX_REG_PAD11_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD11_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD11_RDE_M (LP_IOMUX_REG_PAD11_RDE_V << LP_IOMUX_REG_PAD11_RDE_S) +#define LP_IOMUX_REG_PAD11_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD11_RDE_S 2 +/** LP_IOMUX_REG_PAD11_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD11_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD11_RUE_M (LP_IOMUX_REG_PAD11_RUE_V << LP_IOMUX_REG_PAD11_RUE_S) +#define LP_IOMUX_REG_PAD11_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD11_RUE_S 3 +/** LP_IOMUX_REG_PAD11_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD11_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD11_MUX_SEL_M (LP_IOMUX_REG_PAD11_MUX_SEL_V << LP_IOMUX_REG_PAD11_MUX_SEL_S) +#define LP_IOMUX_REG_PAD11_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD11_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD11_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD11_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD11_FUN_SEL_M (LP_IOMUX_REG_PAD11_FUN_SEL_V << LP_IOMUX_REG_PAD11_FUN_SEL_S) +#define LP_IOMUX_REG_PAD11_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD11_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD11_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD11_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD11_SLP_SEL_M (LP_IOMUX_REG_PAD11_SLP_SEL_V << LP_IOMUX_REG_PAD11_SLP_SEL_S) +#define LP_IOMUX_REG_PAD11_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD11_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD11_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD11_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD11_SLP_IE_M (LP_IOMUX_REG_PAD11_SLP_IE_V << LP_IOMUX_REG_PAD11_SLP_IE_S) +#define LP_IOMUX_REG_PAD11_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD11_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD11_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD11_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD11_SLP_OE_M (LP_IOMUX_REG_PAD11_SLP_OE_V << LP_IOMUX_REG_PAD11_SLP_OE_S) +#define LP_IOMUX_REG_PAD11_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD11_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD11_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD11_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD11_FUN_IE_M (LP_IOMUX_REG_PAD11_FUN_IE_V << LP_IOMUX_REG_PAD11_FUN_IE_S) +#define LP_IOMUX_REG_PAD11_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD11_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD11_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD11_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD11_FILTER_EN_M (LP_IOMUX_REG_PAD11_FILTER_EN_V << LP_IOMUX_REG_PAD11_FILTER_EN_S) +#define LP_IOMUX_REG_PAD11_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD11_FILTER_EN_S 11 + +/** LP_IOMUX_PAD120_REG register + * Reserved + */ +#define LP_IOMUX_PAD120_REG (DR_REG_LP_IOMUX_BASE + 0x38) +/** LP_IOMUX_REG_PAD12_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD12_DRV 0x00000003U +#define LP_IOMUX_REG_PAD12_DRV_M (LP_IOMUX_REG_PAD12_DRV_V << LP_IOMUX_REG_PAD12_DRV_S) +#define LP_IOMUX_REG_PAD12_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD12_DRV_S 0 +/** LP_IOMUX_REG_PAD12_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD12_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD12_RDE_M (LP_IOMUX_REG_PAD12_RDE_V << LP_IOMUX_REG_PAD12_RDE_S) +#define LP_IOMUX_REG_PAD12_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD12_RDE_S 2 +/** LP_IOMUX_REG_PAD12_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD12_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD12_RUE_M (LP_IOMUX_REG_PAD12_RUE_V << LP_IOMUX_REG_PAD12_RUE_S) +#define LP_IOMUX_REG_PAD12_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD12_RUE_S 3 +/** LP_IOMUX_REG_PAD12_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD12_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD12_MUX_SEL_M (LP_IOMUX_REG_PAD12_MUX_SEL_V << LP_IOMUX_REG_PAD12_MUX_SEL_S) +#define LP_IOMUX_REG_PAD12_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD12_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD12_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD12_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD12_FUN_SEL_M (LP_IOMUX_REG_PAD12_FUN_SEL_V << LP_IOMUX_REG_PAD12_FUN_SEL_S) +#define LP_IOMUX_REG_PAD12_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD12_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD12_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD12_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD12_SLP_SEL_M (LP_IOMUX_REG_PAD12_SLP_SEL_V << LP_IOMUX_REG_PAD12_SLP_SEL_S) +#define LP_IOMUX_REG_PAD12_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD12_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD12_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD12_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD12_SLP_IE_M (LP_IOMUX_REG_PAD12_SLP_IE_V << LP_IOMUX_REG_PAD12_SLP_IE_S) +#define LP_IOMUX_REG_PAD12_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD12_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD12_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD12_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD12_SLP_OE_M (LP_IOMUX_REG_PAD12_SLP_OE_V << LP_IOMUX_REG_PAD12_SLP_OE_S) +#define LP_IOMUX_REG_PAD12_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD12_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD12_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD12_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD12_FUN_IE_M (LP_IOMUX_REG_PAD12_FUN_IE_V << LP_IOMUX_REG_PAD12_FUN_IE_S) +#define LP_IOMUX_REG_PAD12_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD12_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD12_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD12_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD12_FILTER_EN_M (LP_IOMUX_REG_PAD12_FILTER_EN_V << LP_IOMUX_REG_PAD12_FILTER_EN_S) +#define LP_IOMUX_REG_PAD12_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD12_FILTER_EN_S 11 + +/** LP_IOMUX_PAD13_REG register + * Reserved + */ +#define LP_IOMUX_PAD13_REG (DR_REG_LP_IOMUX_BASE + 0x3c) +/** LP_IOMUX_REG_PAD13_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD13_DRV 0x00000003U +#define LP_IOMUX_REG_PAD13_DRV_M (LP_IOMUX_REG_PAD13_DRV_V << LP_IOMUX_REG_PAD13_DRV_S) +#define LP_IOMUX_REG_PAD13_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD13_DRV_S 0 +/** LP_IOMUX_REG_PAD13_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD13_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD13_RDE_M (LP_IOMUX_REG_PAD13_RDE_V << LP_IOMUX_REG_PAD13_RDE_S) +#define LP_IOMUX_REG_PAD13_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD13_RDE_S 2 +/** LP_IOMUX_REG_PAD13_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD13_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD13_RUE_M (LP_IOMUX_REG_PAD13_RUE_V << LP_IOMUX_REG_PAD13_RUE_S) +#define LP_IOMUX_REG_PAD13_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD13_RUE_S 3 +/** LP_IOMUX_REG_PAD13_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD13_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD13_MUX_SEL_M (LP_IOMUX_REG_PAD13_MUX_SEL_V << LP_IOMUX_REG_PAD13_MUX_SEL_S) +#define LP_IOMUX_REG_PAD13_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD13_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD13_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD13_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD13_FUN_SEL_M (LP_IOMUX_REG_PAD13_FUN_SEL_V << LP_IOMUX_REG_PAD13_FUN_SEL_S) +#define LP_IOMUX_REG_PAD13_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD13_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD13_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD13_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD13_SLP_SEL_M (LP_IOMUX_REG_PAD13_SLP_SEL_V << LP_IOMUX_REG_PAD13_SLP_SEL_S) +#define LP_IOMUX_REG_PAD13_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD13_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD13_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD13_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD13_SLP_IE_M (LP_IOMUX_REG_PAD13_SLP_IE_V << LP_IOMUX_REG_PAD13_SLP_IE_S) +#define LP_IOMUX_REG_PAD13_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD13_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD13_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD13_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD13_SLP_OE_M (LP_IOMUX_REG_PAD13_SLP_OE_V << LP_IOMUX_REG_PAD13_SLP_OE_S) +#define LP_IOMUX_REG_PAD13_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD13_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD13_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD13_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD13_FUN_IE_M (LP_IOMUX_REG_PAD13_FUN_IE_V << LP_IOMUX_REG_PAD13_FUN_IE_S) +#define LP_IOMUX_REG_PAD13_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD13_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD13_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD13_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD13_FILTER_EN_M (LP_IOMUX_REG_PAD13_FILTER_EN_V << LP_IOMUX_REG_PAD13_FILTER_EN_S) +#define LP_IOMUX_REG_PAD13_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD13_FILTER_EN_S 11 + +/** LP_IOMUX_PAD14_REG register + * Reserved + */ +#define LP_IOMUX_PAD14_REG (DR_REG_LP_IOMUX_BASE + 0x40) +/** LP_IOMUX_REG_PAD14_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD14_DRV 0x00000003U +#define LP_IOMUX_REG_PAD14_DRV_M (LP_IOMUX_REG_PAD14_DRV_V << LP_IOMUX_REG_PAD14_DRV_S) +#define LP_IOMUX_REG_PAD14_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD14_DRV_S 0 +/** LP_IOMUX_REG_PAD14_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD14_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD14_RDE_M (LP_IOMUX_REG_PAD14_RDE_V << LP_IOMUX_REG_PAD14_RDE_S) +#define LP_IOMUX_REG_PAD14_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD14_RDE_S 2 +/** LP_IOMUX_REG_PAD14_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD14_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD14_RUE_M (LP_IOMUX_REG_PAD14_RUE_V << LP_IOMUX_REG_PAD14_RUE_S) +#define LP_IOMUX_REG_PAD14_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD14_RUE_S 3 +/** LP_IOMUX_REG_PAD14_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD14_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD14_MUX_SEL_M (LP_IOMUX_REG_PAD14_MUX_SEL_V << LP_IOMUX_REG_PAD14_MUX_SEL_S) +#define LP_IOMUX_REG_PAD14_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD14_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD14_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD14_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD14_FUN_SEL_M (LP_IOMUX_REG_PAD14_FUN_SEL_V << LP_IOMUX_REG_PAD14_FUN_SEL_S) +#define LP_IOMUX_REG_PAD14_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD14_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD14_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD14_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD14_SLP_SEL_M (LP_IOMUX_REG_PAD14_SLP_SEL_V << LP_IOMUX_REG_PAD14_SLP_SEL_S) +#define LP_IOMUX_REG_PAD14_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD14_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD14_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD14_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD14_SLP_IE_M (LP_IOMUX_REG_PAD14_SLP_IE_V << LP_IOMUX_REG_PAD14_SLP_IE_S) +#define LP_IOMUX_REG_PAD14_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD14_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD14_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD14_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD14_SLP_OE_M (LP_IOMUX_REG_PAD14_SLP_OE_V << LP_IOMUX_REG_PAD14_SLP_OE_S) +#define LP_IOMUX_REG_PAD14_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD14_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD14_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD14_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD14_FUN_IE_M (LP_IOMUX_REG_PAD14_FUN_IE_V << LP_IOMUX_REG_PAD14_FUN_IE_S) +#define LP_IOMUX_REG_PAD14_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD14_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD14_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD14_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD14_FILTER_EN_M (LP_IOMUX_REG_PAD14_FILTER_EN_V << LP_IOMUX_REG_PAD14_FILTER_EN_S) +#define LP_IOMUX_REG_PAD14_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD14_FILTER_EN_S 11 + +/** LP_IOMUX_PAD15_REG register + * Reserved + */ +#define LP_IOMUX_PAD15_REG (DR_REG_LP_IOMUX_BASE + 0x44) +/** LP_IOMUX_REG_PAD15_DRV : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ +#define LP_IOMUX_REG_PAD15_DRV 0x00000003U +#define LP_IOMUX_REG_PAD15_DRV_M (LP_IOMUX_REG_PAD15_DRV_V << LP_IOMUX_REG_PAD15_DRV_S) +#define LP_IOMUX_REG_PAD15_DRV_V 0x00000003U +#define LP_IOMUX_REG_PAD15_DRV_S 0 +/** LP_IOMUX_REG_PAD15_RDE : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD15_RDE (BIT(2)) +#define LP_IOMUX_REG_PAD15_RDE_M (LP_IOMUX_REG_PAD15_RDE_V << LP_IOMUX_REG_PAD15_RDE_S) +#define LP_IOMUX_REG_PAD15_RDE_V 0x00000001U +#define LP_IOMUX_REG_PAD15_RDE_S 2 +/** LP_IOMUX_REG_PAD15_RUE : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_PAD15_RUE (BIT(3)) +#define LP_IOMUX_REG_PAD15_RUE_M (LP_IOMUX_REG_PAD15_RUE_V << LP_IOMUX_REG_PAD15_RUE_S) +#define LP_IOMUX_REG_PAD15_RUE_V 0x00000001U +#define LP_IOMUX_REG_PAD15_RUE_S 3 +/** LP_IOMUX_REG_PAD15_MUX_SEL : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ +#define LP_IOMUX_REG_PAD15_MUX_SEL (BIT(4)) +#define LP_IOMUX_REG_PAD15_MUX_SEL_M (LP_IOMUX_REG_PAD15_MUX_SEL_V << LP_IOMUX_REG_PAD15_MUX_SEL_S) +#define LP_IOMUX_REG_PAD15_MUX_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD15_MUX_SEL_S 4 +/** LP_IOMUX_REG_PAD15_FUN_SEL : R/W; bitpos: [6:5]; default: 0; + * function sel + */ +#define LP_IOMUX_REG_PAD15_FUN_SEL 0x00000003U +#define LP_IOMUX_REG_PAD15_FUN_SEL_M (LP_IOMUX_REG_PAD15_FUN_SEL_V << LP_IOMUX_REG_PAD15_FUN_SEL_S) +#define LP_IOMUX_REG_PAD15_FUN_SEL_V 0x00000003U +#define LP_IOMUX_REG_PAD15_FUN_SEL_S 5 +/** LP_IOMUX_REG_PAD15_SLP_SEL : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ +#define LP_IOMUX_REG_PAD15_SLP_SEL (BIT(7)) +#define LP_IOMUX_REG_PAD15_SLP_SEL_M (LP_IOMUX_REG_PAD15_SLP_SEL_V << LP_IOMUX_REG_PAD15_SLP_SEL_S) +#define LP_IOMUX_REG_PAD15_SLP_SEL_V 0x00000001U +#define LP_IOMUX_REG_PAD15_SLP_SEL_S 7 +/** LP_IOMUX_REG_PAD15_SLP_IE : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ +#define LP_IOMUX_REG_PAD15_SLP_IE (BIT(8)) +#define LP_IOMUX_REG_PAD15_SLP_IE_M (LP_IOMUX_REG_PAD15_SLP_IE_V << LP_IOMUX_REG_PAD15_SLP_IE_S) +#define LP_IOMUX_REG_PAD15_SLP_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD15_SLP_IE_S 8 +/** LP_IOMUX_REG_PAD15_SLP_OE : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ +#define LP_IOMUX_REG_PAD15_SLP_OE (BIT(9)) +#define LP_IOMUX_REG_PAD15_SLP_OE_M (LP_IOMUX_REG_PAD15_SLP_OE_V << LP_IOMUX_REG_PAD15_SLP_OE_S) +#define LP_IOMUX_REG_PAD15_SLP_OE_V 0x00000001U +#define LP_IOMUX_REG_PAD15_SLP_OE_S 9 +/** LP_IOMUX_REG_PAD15_FUN_IE : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ +#define LP_IOMUX_REG_PAD15_FUN_IE (BIT(10)) +#define LP_IOMUX_REG_PAD15_FUN_IE_M (LP_IOMUX_REG_PAD15_FUN_IE_V << LP_IOMUX_REG_PAD15_FUN_IE_S) +#define LP_IOMUX_REG_PAD15_FUN_IE_V 0x00000001U +#define LP_IOMUX_REG_PAD15_FUN_IE_S 10 +/** LP_IOMUX_REG_PAD15_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IOMUX_REG_PAD15_FILTER_EN (BIT(11)) +#define LP_IOMUX_REG_PAD15_FILTER_EN_M (LP_IOMUX_REG_PAD15_FILTER_EN_V << LP_IOMUX_REG_PAD15_FILTER_EN_S) +#define LP_IOMUX_REG_PAD15_FILTER_EN_V 0x00000001U +#define LP_IOMUX_REG_PAD15_FILTER_EN_S 11 + +/** LP_IOMUX_EXT_WAKEUP0_SEL_REG register + * Reserved + */ +#define LP_IOMUX_EXT_WAKEUP0_SEL_REG (DR_REG_LP_IOMUX_BASE + 0x48) +/** LP_IOMUX_REG_XTL_EXT_CTR_SEL : R/W; bitpos: [4:0]; default: 0; + * select LP GPIO 0 ~ 15 to control XTAL + */ +#define LP_IOMUX_REG_XTL_EXT_CTR_SEL 0x0000001FU +#define LP_IOMUX_REG_XTL_EXT_CTR_SEL_M (LP_IOMUX_REG_XTL_EXT_CTR_SEL_V << LP_IOMUX_REG_XTL_EXT_CTR_SEL_S) +#define LP_IOMUX_REG_XTL_EXT_CTR_SEL_V 0x0000001FU +#define LP_IOMUX_REG_XTL_EXT_CTR_SEL_S 0 +/** LP_IOMUX_REG_EXT_WAKEUP0_SEL : R/W; bitpos: [9:5]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_EXT_WAKEUP0_SEL 0x0000001FU +#define LP_IOMUX_REG_EXT_WAKEUP0_SEL_M (LP_IOMUX_REG_EXT_WAKEUP0_SEL_V << LP_IOMUX_REG_EXT_WAKEUP0_SEL_S) +#define LP_IOMUX_REG_EXT_WAKEUP0_SEL_V 0x0000001FU +#define LP_IOMUX_REG_EXT_WAKEUP0_SEL_S 5 + +/** LP_IOMUX_LP_PAD_HOLD_REG register + * Reserved + */ +#define LP_IOMUX_LP_PAD_HOLD_REG (DR_REG_LP_IOMUX_BASE + 0x4c) +/** LP_IOMUX_REG_LP_GPIO_HOLD : R/W; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_LP_GPIO_HOLD 0x0000FFFFU +#define LP_IOMUX_REG_LP_GPIO_HOLD_M (LP_IOMUX_REG_LP_GPIO_HOLD_V << LP_IOMUX_REG_LP_GPIO_HOLD_S) +#define LP_IOMUX_REG_LP_GPIO_HOLD_V 0x0000FFFFU +#define LP_IOMUX_REG_LP_GPIO_HOLD_S 0 + +/** LP_IOMUX_LP_PAD_HYS_REG register + * Reserved + */ +#define LP_IOMUX_LP_PAD_HYS_REG (DR_REG_LP_IOMUX_BASE + 0x50) +/** LP_IOMUX_REG_LP_GPIO_HYS : R/W; bitpos: [15:0]; default: 0; + * Reserved + */ +#define LP_IOMUX_REG_LP_GPIO_HYS 0x0000FFFFU +#define LP_IOMUX_REG_LP_GPIO_HYS_M (LP_IOMUX_REG_LP_GPIO_HYS_V << LP_IOMUX_REG_LP_GPIO_HYS_S) +#define LP_IOMUX_REG_LP_GPIO_HYS_V 0x0000FFFFU +#define LP_IOMUX_REG_LP_GPIO_HYS_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_struct.h new file mode 100644 index 0000000000..740839aecd --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_iomux_struct.h @@ -0,0 +1,166 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: clk_en */ +/** Type of clk_en register + * Reserved + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * Reserved + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_iomux_clk_en_reg_t; + + +/** Group: ver_date */ +/** Type of ver_date register + * Reserved + */ +typedef union { + struct { + /** reg_ver_date : R/W; bitpos: [27:0]; default: 2294547; + * Reserved + */ + uint32_t reg_ver_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_iomux_ver_date_reg_t; + + +/** Group: pad */ +/** Type of pad register + * Reserved + */ +typedef union { + struct { + /** drv : R/W; bitpos: [1:0]; default: 2; + * Reserved + */ + uint32_t drv:2; + /** rde : R/W; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t rde:1; + /** rue : R/W; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t rue:1; + /** mux_sel : R/W; bitpos: [4]; default: 0; + * 1:use LP GPIO,0: use digital GPIO + */ + uint32_t mux_sel:1; + /** fun_sel : R/W; bitpos: [6:5]; default: 0; + * function sel + */ + uint32_t fun_sel:2; + /** slp_sel : R/W; bitpos: [7]; default: 0; + * 1: enable sleep mode during sleep,0: no sleep mode + */ + uint32_t slp_sel:1; + /** slp_ie : R/W; bitpos: [8]; default: 0; + * input enable in sleep mode + */ + uint32_t slp_ie:1; + /** slp_oe : R/W; bitpos: [9]; default: 0; + * output enable in sleep mode + */ + uint32_t slp_oe:1; + /** fun_ie : R/W; bitpos: [10]; default: 0; + * input enable in work mode + */ + uint32_t fun_ie:1; + /** filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_iomux_pad_reg_t; + + +/** Group: ext_wakeup0_sel */ +/** Type of ext_wakeup0_sel register + * Reserved + */ +typedef union { + struct { + /** reg_xtl_ext_ctr_sel : R/W; bitpos: [4:0]; default: 0; + * select LP GPIO 0 ~ 15 to control XTAL + */ + uint32_t reg_xtl_ext_ctr_sel:5; + /** reg_ext_wakeup0_sel : R/W; bitpos: [9:5]; default: 0; + * Reserved + */ + uint32_t reg_ext_wakeup0_sel:5; + uint32_t reserved_10:22; + }; + uint32_t val; +} lp_iomux_ext_wakeup0_sel_reg_t; + + +/** Group: lp_pad_hold */ +/** Type of lp_pad_hold register + * Reserved + */ +typedef union { + struct { + /** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_lp_gpio_hold:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_iomux_lp_pad_hold_reg_t; + + +/** Group: lp_pad_hys */ +/** Type of lp_pad_hys register + * Reserved + */ +typedef union { + struct { + /** reg_lp_gpio_hys : R/W; bitpos: [15:0]; default: 0; + * Reserved + */ + uint32_t reg_lp_gpio_hys:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_iomux_lp_pad_hys_reg_t; + + +typedef struct lp_iomux_dev_t { + volatile lp_iomux_clk_en_reg_t clk_en; + volatile lp_iomux_ver_date_reg_t ver_date; + volatile lp_iomux_pad_reg_t pad[16]; + volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel; + volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold; + volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys; +} lp_iomux_dev_t; + +extern lp_iomux_dev_t LP_IOMUX; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_iomux_dev_t) == 0x54, "Invalid size of lp_iomux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_reg.h new file mode 100644 index 0000000000..07ebf89847 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_reg.h @@ -0,0 +1,1156 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MB_MASSEGE_0_REG register + * need_des + */ +#define MB_MASSEGE_0_REG (DR_REG_MB_BASE + 0x0) +/** MB_MASSEGE_0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_0 0xFFFFFFFFU +#define MB_MASSEGE_0_M (MB_MASSEGE_0_V << MB_MASSEGE_0_S) +#define MB_MASSEGE_0_V 0xFFFFFFFFU +#define MB_MASSEGE_0_S 0 + +/** MB_MASSEGE_1_REG register + * need_des + */ +#define MB_MASSEGE_1_REG (DR_REG_MB_BASE + 0x4) +/** MB_MASSEGE_1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_1 0xFFFFFFFFU +#define MB_MASSEGE_1_M (MB_MASSEGE_1_V << MB_MASSEGE_1_S) +#define MB_MASSEGE_1_V 0xFFFFFFFFU +#define MB_MASSEGE_1_S 0 + +/** MB_MASSEGE_2_REG register + * need_des + */ +#define MB_MASSEGE_2_REG (DR_REG_MB_BASE + 0x8) +/** MB_MASSEGE_2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_2 0xFFFFFFFFU +#define MB_MASSEGE_2_M (MB_MASSEGE_2_V << MB_MASSEGE_2_S) +#define MB_MASSEGE_2_V 0xFFFFFFFFU +#define MB_MASSEGE_2_S 0 + +/** MB_MASSEGE_3_REG register + * need_des + */ +#define MB_MASSEGE_3_REG (DR_REG_MB_BASE + 0xc) +/** MB_MASSEGE_3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_3 0xFFFFFFFFU +#define MB_MASSEGE_3_M (MB_MASSEGE_3_V << MB_MASSEGE_3_S) +#define MB_MASSEGE_3_V 0xFFFFFFFFU +#define MB_MASSEGE_3_S 0 + +/** MB_MASSEGE_4_REG register + * need_des + */ +#define MB_MASSEGE_4_REG (DR_REG_MB_BASE + 0x10) +/** MB_MASSEGE_4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_4 0xFFFFFFFFU +#define MB_MASSEGE_4_M (MB_MASSEGE_4_V << MB_MASSEGE_4_S) +#define MB_MASSEGE_4_V 0xFFFFFFFFU +#define MB_MASSEGE_4_S 0 + +/** MB_MASSEGE_5_REG register + * need_des + */ +#define MB_MASSEGE_5_REG (DR_REG_MB_BASE + 0x14) +/** MB_MASSEGE_5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_5 0xFFFFFFFFU +#define MB_MASSEGE_5_M (MB_MASSEGE_5_V << MB_MASSEGE_5_S) +#define MB_MASSEGE_5_V 0xFFFFFFFFU +#define MB_MASSEGE_5_S 0 + +/** MB_MASSEGE_6_REG register + * need_des + */ +#define MB_MASSEGE_6_REG (DR_REG_MB_BASE + 0x18) +/** MB_MASSEGE_6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_6 0xFFFFFFFFU +#define MB_MASSEGE_6_M (MB_MASSEGE_6_V << MB_MASSEGE_6_S) +#define MB_MASSEGE_6_V 0xFFFFFFFFU +#define MB_MASSEGE_6_S 0 + +/** MB_MASSEGE_7_REG register + * need_des + */ +#define MB_MASSEGE_7_REG (DR_REG_MB_BASE + 0x1c) +/** MB_MASSEGE_7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_7 0xFFFFFFFFU +#define MB_MASSEGE_7_M (MB_MASSEGE_7_V << MB_MASSEGE_7_S) +#define MB_MASSEGE_7_V 0xFFFFFFFFU +#define MB_MASSEGE_7_S 0 + +/** MB_MASSEGE_8_REG register + * need_des + */ +#define MB_MASSEGE_8_REG (DR_REG_MB_BASE + 0x20) +/** MB_MASSEGE_8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_8 0xFFFFFFFFU +#define MB_MASSEGE_8_M (MB_MASSEGE_8_V << MB_MASSEGE_8_S) +#define MB_MASSEGE_8_V 0xFFFFFFFFU +#define MB_MASSEGE_8_S 0 + +/** MB_MASSEGE_9_REG register + * need_des + */ +#define MB_MASSEGE_9_REG (DR_REG_MB_BASE + 0x24) +/** MB_MASSEGE_9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_9 0xFFFFFFFFU +#define MB_MASSEGE_9_M (MB_MASSEGE_9_V << MB_MASSEGE_9_S) +#define MB_MASSEGE_9_V 0xFFFFFFFFU +#define MB_MASSEGE_9_S 0 + +/** MB_MASSEGE_10_REG register + * need_des + */ +#define MB_MASSEGE_10_REG (DR_REG_MB_BASE + 0x28) +/** MB_MASSEGE_10 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_10 0xFFFFFFFFU +#define MB_MASSEGE_10_M (MB_MASSEGE_10_V << MB_MASSEGE_10_S) +#define MB_MASSEGE_10_V 0xFFFFFFFFU +#define MB_MASSEGE_10_S 0 + +/** MB_MASSEGE_11_REG register + * need_des + */ +#define MB_MASSEGE_11_REG (DR_REG_MB_BASE + 0x2c) +/** MB_MASSEGE_11 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_11 0xFFFFFFFFU +#define MB_MASSEGE_11_M (MB_MASSEGE_11_V << MB_MASSEGE_11_S) +#define MB_MASSEGE_11_V 0xFFFFFFFFU +#define MB_MASSEGE_11_S 0 + +/** MB_MASSEGE_12_REG register + * need_des + */ +#define MB_MASSEGE_12_REG (DR_REG_MB_BASE + 0x30) +/** MB_MASSEGE_12 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_12 0xFFFFFFFFU +#define MB_MASSEGE_12_M (MB_MASSEGE_12_V << MB_MASSEGE_12_S) +#define MB_MASSEGE_12_V 0xFFFFFFFFU +#define MB_MASSEGE_12_S 0 + +/** MB_MASSEGE_13_REG register + * need_des + */ +#define MB_MASSEGE_13_REG (DR_REG_MB_BASE + 0x34) +/** MB_MASSEGE_13 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_13 0xFFFFFFFFU +#define MB_MASSEGE_13_M (MB_MASSEGE_13_V << MB_MASSEGE_13_S) +#define MB_MASSEGE_13_V 0xFFFFFFFFU +#define MB_MASSEGE_13_S 0 + +/** MB_MASSEGE_14_REG register + * need_des + */ +#define MB_MASSEGE_14_REG (DR_REG_MB_BASE + 0x38) +/** MB_MASSEGE_14 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_14 0xFFFFFFFFU +#define MB_MASSEGE_14_M (MB_MASSEGE_14_V << MB_MASSEGE_14_S) +#define MB_MASSEGE_14_V 0xFFFFFFFFU +#define MB_MASSEGE_14_S 0 + +/** MB_MASSEGE_15_REG register + * need_des + */ +#define MB_MASSEGE_15_REG (DR_REG_MB_BASE + 0x3c) +/** MB_MASSEGE_15 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MB_MASSEGE_15 0xFFFFFFFFU +#define MB_MASSEGE_15_M (MB_MASSEGE_15_V << MB_MASSEGE_15_S) +#define MB_MASSEGE_15_V 0xFFFFFFFFU +#define MB_MASSEGE_15_S 0 + +/** MB_LP_INT_RAW_REG register + * need_des + */ +#define MB_LP_INT_RAW_REG (DR_REG_MB_BASE + 0x40) +/** MB_LP_0_INT_RAW : RO; bitpos: [0]; default: 0; + * need_des + */ +#define MB_LP_0_INT_RAW (BIT(0)) +#define MB_LP_0_INT_RAW_M (MB_LP_0_INT_RAW_V << MB_LP_0_INT_RAW_S) +#define MB_LP_0_INT_RAW_V 0x00000001U +#define MB_LP_0_INT_RAW_S 0 +/** MB_LP_1_INT_RAW : RO; bitpos: [1]; default: 0; + * need_des + */ +#define MB_LP_1_INT_RAW (BIT(1)) +#define MB_LP_1_INT_RAW_M (MB_LP_1_INT_RAW_V << MB_LP_1_INT_RAW_S) +#define MB_LP_1_INT_RAW_V 0x00000001U +#define MB_LP_1_INT_RAW_S 1 +/** MB_LP_2_INT_RAW : RO; bitpos: [2]; default: 0; + * need_des + */ +#define MB_LP_2_INT_RAW (BIT(2)) +#define MB_LP_2_INT_RAW_M (MB_LP_2_INT_RAW_V << MB_LP_2_INT_RAW_S) +#define MB_LP_2_INT_RAW_V 0x00000001U +#define MB_LP_2_INT_RAW_S 2 +/** MB_LP_3_INT_RAW : RO; bitpos: [3]; default: 0; + * need_des + */ +#define MB_LP_3_INT_RAW (BIT(3)) +#define MB_LP_3_INT_RAW_M (MB_LP_3_INT_RAW_V << MB_LP_3_INT_RAW_S) +#define MB_LP_3_INT_RAW_V 0x00000001U +#define MB_LP_3_INT_RAW_S 3 +/** MB_LP_4_INT_RAW : RO; bitpos: [4]; default: 0; + * need_des + */ +#define MB_LP_4_INT_RAW (BIT(4)) +#define MB_LP_4_INT_RAW_M (MB_LP_4_INT_RAW_V << MB_LP_4_INT_RAW_S) +#define MB_LP_4_INT_RAW_V 0x00000001U +#define MB_LP_4_INT_RAW_S 4 +/** MB_LP_5_INT_RAW : RO; bitpos: [5]; default: 0; + * need_des + */ +#define MB_LP_5_INT_RAW (BIT(5)) +#define MB_LP_5_INT_RAW_M (MB_LP_5_INT_RAW_V << MB_LP_5_INT_RAW_S) +#define MB_LP_5_INT_RAW_V 0x00000001U +#define MB_LP_5_INT_RAW_S 5 +/** MB_LP_6_INT_RAW : RO; bitpos: [6]; default: 0; + * need_des + */ +#define MB_LP_6_INT_RAW (BIT(6)) +#define MB_LP_6_INT_RAW_M (MB_LP_6_INT_RAW_V << MB_LP_6_INT_RAW_S) +#define MB_LP_6_INT_RAW_V 0x00000001U +#define MB_LP_6_INT_RAW_S 6 +/** MB_LP_7_INT_RAW : RO; bitpos: [7]; default: 0; + * need_des + */ +#define MB_LP_7_INT_RAW (BIT(7)) +#define MB_LP_7_INT_RAW_M (MB_LP_7_INT_RAW_V << MB_LP_7_INT_RAW_S) +#define MB_LP_7_INT_RAW_V 0x00000001U +#define MB_LP_7_INT_RAW_S 7 +/** MB_LP_8_INT_RAW : RO; bitpos: [8]; default: 0; + * need_des + */ +#define MB_LP_8_INT_RAW (BIT(8)) +#define MB_LP_8_INT_RAW_M (MB_LP_8_INT_RAW_V << MB_LP_8_INT_RAW_S) +#define MB_LP_8_INT_RAW_V 0x00000001U +#define MB_LP_8_INT_RAW_S 8 +/** MB_LP_9_INT_RAW : RO; bitpos: [9]; default: 0; + * need_des + */ +#define MB_LP_9_INT_RAW (BIT(9)) +#define MB_LP_9_INT_RAW_M (MB_LP_9_INT_RAW_V << MB_LP_9_INT_RAW_S) +#define MB_LP_9_INT_RAW_V 0x00000001U +#define MB_LP_9_INT_RAW_S 9 +/** MB_LP_10_INT_RAW : RO; bitpos: [10]; default: 0; + * need_des + */ +#define MB_LP_10_INT_RAW (BIT(10)) +#define MB_LP_10_INT_RAW_M (MB_LP_10_INT_RAW_V << MB_LP_10_INT_RAW_S) +#define MB_LP_10_INT_RAW_V 0x00000001U +#define MB_LP_10_INT_RAW_S 10 +/** MB_LP_11_INT_RAW : RO; bitpos: [11]; default: 0; + * need_des + */ +#define MB_LP_11_INT_RAW (BIT(11)) +#define MB_LP_11_INT_RAW_M (MB_LP_11_INT_RAW_V << MB_LP_11_INT_RAW_S) +#define MB_LP_11_INT_RAW_V 0x00000001U +#define MB_LP_11_INT_RAW_S 11 +/** MB_LP_12_INT_RAW : RO; bitpos: [12]; default: 0; + * need_des + */ +#define MB_LP_12_INT_RAW (BIT(12)) +#define MB_LP_12_INT_RAW_M (MB_LP_12_INT_RAW_V << MB_LP_12_INT_RAW_S) +#define MB_LP_12_INT_RAW_V 0x00000001U +#define MB_LP_12_INT_RAW_S 12 +/** MB_LP_13_INT_RAW : RO; bitpos: [13]; default: 0; + * need_des + */ +#define MB_LP_13_INT_RAW (BIT(13)) +#define MB_LP_13_INT_RAW_M (MB_LP_13_INT_RAW_V << MB_LP_13_INT_RAW_S) +#define MB_LP_13_INT_RAW_V 0x00000001U +#define MB_LP_13_INT_RAW_S 13 +/** MB_LP_14_INT_RAW : RO; bitpos: [14]; default: 0; + * need_des + */ +#define MB_LP_14_INT_RAW (BIT(14)) +#define MB_LP_14_INT_RAW_M (MB_LP_14_INT_RAW_V << MB_LP_14_INT_RAW_S) +#define MB_LP_14_INT_RAW_V 0x00000001U +#define MB_LP_14_INT_RAW_S 14 +/** MB_LP_15_INT_RAW : RO; bitpos: [15]; default: 0; + * need_des + */ +#define MB_LP_15_INT_RAW (BIT(15)) +#define MB_LP_15_INT_RAW_M (MB_LP_15_INT_RAW_V << MB_LP_15_INT_RAW_S) +#define MB_LP_15_INT_RAW_V 0x00000001U +#define MB_LP_15_INT_RAW_S 15 + +/** MB_LP_INT_ST_REG register + * need_des + */ +#define MB_LP_INT_ST_REG (DR_REG_MB_BASE + 0x44) +/** MB_LP_0_INT_ST : RO; bitpos: [0]; default: 0; + * need_des + */ +#define MB_LP_0_INT_ST (BIT(0)) +#define MB_LP_0_INT_ST_M (MB_LP_0_INT_ST_V << MB_LP_0_INT_ST_S) +#define MB_LP_0_INT_ST_V 0x00000001U +#define MB_LP_0_INT_ST_S 0 +/** MB_LP_1_INT_ST : RO; bitpos: [1]; default: 0; + * need_des + */ +#define MB_LP_1_INT_ST (BIT(1)) +#define MB_LP_1_INT_ST_M (MB_LP_1_INT_ST_V << MB_LP_1_INT_ST_S) +#define MB_LP_1_INT_ST_V 0x00000001U +#define MB_LP_1_INT_ST_S 1 +/** MB_LP_2_INT_ST : RO; bitpos: [2]; default: 0; + * need_des + */ +#define MB_LP_2_INT_ST (BIT(2)) +#define MB_LP_2_INT_ST_M (MB_LP_2_INT_ST_V << MB_LP_2_INT_ST_S) +#define MB_LP_2_INT_ST_V 0x00000001U +#define MB_LP_2_INT_ST_S 2 +/** MB_LP_3_INT_ST : RO; bitpos: [3]; default: 0; + * need_des + */ +#define MB_LP_3_INT_ST (BIT(3)) +#define MB_LP_3_INT_ST_M (MB_LP_3_INT_ST_V << MB_LP_3_INT_ST_S) +#define MB_LP_3_INT_ST_V 0x00000001U +#define MB_LP_3_INT_ST_S 3 +/** MB_LP_4_INT_ST : RO; bitpos: [4]; default: 0; + * need_des + */ +#define MB_LP_4_INT_ST (BIT(4)) +#define MB_LP_4_INT_ST_M (MB_LP_4_INT_ST_V << MB_LP_4_INT_ST_S) +#define MB_LP_4_INT_ST_V 0x00000001U +#define MB_LP_4_INT_ST_S 4 +/** MB_LP_5_INT_ST : RO; bitpos: [5]; default: 0; + * need_des + */ +#define MB_LP_5_INT_ST (BIT(5)) +#define MB_LP_5_INT_ST_M (MB_LP_5_INT_ST_V << MB_LP_5_INT_ST_S) +#define MB_LP_5_INT_ST_V 0x00000001U +#define MB_LP_5_INT_ST_S 5 +/** MB_LP_6_INT_ST : RO; bitpos: [6]; default: 0; + * need_des + */ +#define MB_LP_6_INT_ST (BIT(6)) +#define MB_LP_6_INT_ST_M (MB_LP_6_INT_ST_V << MB_LP_6_INT_ST_S) +#define MB_LP_6_INT_ST_V 0x00000001U +#define MB_LP_6_INT_ST_S 6 +/** MB_LP_7_INT_ST : RO; bitpos: [7]; default: 0; + * need_des + */ +#define MB_LP_7_INT_ST (BIT(7)) +#define MB_LP_7_INT_ST_M (MB_LP_7_INT_ST_V << MB_LP_7_INT_ST_S) +#define MB_LP_7_INT_ST_V 0x00000001U +#define MB_LP_7_INT_ST_S 7 +/** MB_LP_8_INT_ST : RO; bitpos: [8]; default: 0; + * need_des + */ +#define MB_LP_8_INT_ST (BIT(8)) +#define MB_LP_8_INT_ST_M (MB_LP_8_INT_ST_V << MB_LP_8_INT_ST_S) +#define MB_LP_8_INT_ST_V 0x00000001U +#define MB_LP_8_INT_ST_S 8 +/** MB_LP_9_INT_ST : RO; bitpos: [9]; default: 0; + * need_des + */ +#define MB_LP_9_INT_ST (BIT(9)) +#define MB_LP_9_INT_ST_M (MB_LP_9_INT_ST_V << MB_LP_9_INT_ST_S) +#define MB_LP_9_INT_ST_V 0x00000001U +#define MB_LP_9_INT_ST_S 9 +/** MB_LP_10_INT_ST : RO; bitpos: [10]; default: 0; + * need_des + */ +#define MB_LP_10_INT_ST (BIT(10)) +#define MB_LP_10_INT_ST_M (MB_LP_10_INT_ST_V << MB_LP_10_INT_ST_S) +#define MB_LP_10_INT_ST_V 0x00000001U +#define MB_LP_10_INT_ST_S 10 +/** MB_LP_11_INT_ST : RO; bitpos: [11]; default: 0; + * need_des + */ +#define MB_LP_11_INT_ST (BIT(11)) +#define MB_LP_11_INT_ST_M (MB_LP_11_INT_ST_V << MB_LP_11_INT_ST_S) +#define MB_LP_11_INT_ST_V 0x00000001U +#define MB_LP_11_INT_ST_S 11 +/** MB_LP_12_INT_ST : RO; bitpos: [12]; default: 0; + * need_des + */ +#define MB_LP_12_INT_ST (BIT(12)) +#define MB_LP_12_INT_ST_M (MB_LP_12_INT_ST_V << MB_LP_12_INT_ST_S) +#define MB_LP_12_INT_ST_V 0x00000001U +#define MB_LP_12_INT_ST_S 12 +/** MB_LP_13_INT_ST : RO; bitpos: [13]; default: 0; + * need_des + */ +#define MB_LP_13_INT_ST (BIT(13)) +#define MB_LP_13_INT_ST_M (MB_LP_13_INT_ST_V << MB_LP_13_INT_ST_S) +#define MB_LP_13_INT_ST_V 0x00000001U +#define MB_LP_13_INT_ST_S 13 +/** MB_LP_14_INT_ST : RO; bitpos: [14]; default: 0; + * need_des + */ +#define MB_LP_14_INT_ST (BIT(14)) +#define MB_LP_14_INT_ST_M (MB_LP_14_INT_ST_V << MB_LP_14_INT_ST_S) +#define MB_LP_14_INT_ST_V 0x00000001U +#define MB_LP_14_INT_ST_S 14 +/** MB_LP_15_INT_ST : RO; bitpos: [15]; default: 0; + * need_des + */ +#define MB_LP_15_INT_ST (BIT(15)) +#define MB_LP_15_INT_ST_M (MB_LP_15_INT_ST_V << MB_LP_15_INT_ST_S) +#define MB_LP_15_INT_ST_V 0x00000001U +#define MB_LP_15_INT_ST_S 15 + +/** MB_LP_INT_ENA_REG register + * need_des + */ +#define MB_LP_INT_ENA_REG (DR_REG_MB_BASE + 0x48) +/** MB_LP_0_INT_ENA : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define MB_LP_0_INT_ENA (BIT(0)) +#define MB_LP_0_INT_ENA_M (MB_LP_0_INT_ENA_V << MB_LP_0_INT_ENA_S) +#define MB_LP_0_INT_ENA_V 0x00000001U +#define MB_LP_0_INT_ENA_S 0 +/** MB_LP_1_INT_ENA : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define MB_LP_1_INT_ENA (BIT(1)) +#define MB_LP_1_INT_ENA_M (MB_LP_1_INT_ENA_V << MB_LP_1_INT_ENA_S) +#define MB_LP_1_INT_ENA_V 0x00000001U +#define MB_LP_1_INT_ENA_S 1 +/** MB_LP_2_INT_ENA : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define MB_LP_2_INT_ENA (BIT(2)) +#define MB_LP_2_INT_ENA_M (MB_LP_2_INT_ENA_V << MB_LP_2_INT_ENA_S) +#define MB_LP_2_INT_ENA_V 0x00000001U +#define MB_LP_2_INT_ENA_S 2 +/** MB_LP_3_INT_ENA : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define MB_LP_3_INT_ENA (BIT(3)) +#define MB_LP_3_INT_ENA_M (MB_LP_3_INT_ENA_V << MB_LP_3_INT_ENA_S) +#define MB_LP_3_INT_ENA_V 0x00000001U +#define MB_LP_3_INT_ENA_S 3 +/** MB_LP_4_INT_ENA : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define MB_LP_4_INT_ENA (BIT(4)) +#define MB_LP_4_INT_ENA_M (MB_LP_4_INT_ENA_V << MB_LP_4_INT_ENA_S) +#define MB_LP_4_INT_ENA_V 0x00000001U +#define MB_LP_4_INT_ENA_S 4 +/** MB_LP_5_INT_ENA : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define MB_LP_5_INT_ENA (BIT(5)) +#define MB_LP_5_INT_ENA_M (MB_LP_5_INT_ENA_V << MB_LP_5_INT_ENA_S) +#define MB_LP_5_INT_ENA_V 0x00000001U +#define MB_LP_5_INT_ENA_S 5 +/** MB_LP_6_INT_ENA : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define MB_LP_6_INT_ENA (BIT(6)) +#define MB_LP_6_INT_ENA_M (MB_LP_6_INT_ENA_V << MB_LP_6_INT_ENA_S) +#define MB_LP_6_INT_ENA_V 0x00000001U +#define MB_LP_6_INT_ENA_S 6 +/** MB_LP_7_INT_ENA : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define MB_LP_7_INT_ENA (BIT(7)) +#define MB_LP_7_INT_ENA_M (MB_LP_7_INT_ENA_V << MB_LP_7_INT_ENA_S) +#define MB_LP_7_INT_ENA_V 0x00000001U +#define MB_LP_7_INT_ENA_S 7 +/** MB_LP_8_INT_ENA : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define MB_LP_8_INT_ENA (BIT(8)) +#define MB_LP_8_INT_ENA_M (MB_LP_8_INT_ENA_V << MB_LP_8_INT_ENA_S) +#define MB_LP_8_INT_ENA_V 0x00000001U +#define MB_LP_8_INT_ENA_S 8 +/** MB_LP_9_INT_ENA : R/W; bitpos: [9]; default: 0; + * need_des + */ +#define MB_LP_9_INT_ENA (BIT(9)) +#define MB_LP_9_INT_ENA_M (MB_LP_9_INT_ENA_V << MB_LP_9_INT_ENA_S) +#define MB_LP_9_INT_ENA_V 0x00000001U +#define MB_LP_9_INT_ENA_S 9 +/** MB_LP_10_INT_ENA : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define MB_LP_10_INT_ENA (BIT(10)) +#define MB_LP_10_INT_ENA_M (MB_LP_10_INT_ENA_V << MB_LP_10_INT_ENA_S) +#define MB_LP_10_INT_ENA_V 0x00000001U +#define MB_LP_10_INT_ENA_S 10 +/** MB_LP_11_INT_ENA : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define MB_LP_11_INT_ENA (BIT(11)) +#define MB_LP_11_INT_ENA_M (MB_LP_11_INT_ENA_V << MB_LP_11_INT_ENA_S) +#define MB_LP_11_INT_ENA_V 0x00000001U +#define MB_LP_11_INT_ENA_S 11 +/** MB_LP_12_INT_ENA : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define MB_LP_12_INT_ENA (BIT(12)) +#define MB_LP_12_INT_ENA_M (MB_LP_12_INT_ENA_V << MB_LP_12_INT_ENA_S) +#define MB_LP_12_INT_ENA_V 0x00000001U +#define MB_LP_12_INT_ENA_S 12 +/** MB_LP_13_INT_ENA : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define MB_LP_13_INT_ENA (BIT(13)) +#define MB_LP_13_INT_ENA_M (MB_LP_13_INT_ENA_V << MB_LP_13_INT_ENA_S) +#define MB_LP_13_INT_ENA_V 0x00000001U +#define MB_LP_13_INT_ENA_S 13 +/** MB_LP_14_INT_ENA : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define MB_LP_14_INT_ENA (BIT(14)) +#define MB_LP_14_INT_ENA_M (MB_LP_14_INT_ENA_V << MB_LP_14_INT_ENA_S) +#define MB_LP_14_INT_ENA_V 0x00000001U +#define MB_LP_14_INT_ENA_S 14 +/** MB_LP_15_INT_ENA : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define MB_LP_15_INT_ENA (BIT(15)) +#define MB_LP_15_INT_ENA_M (MB_LP_15_INT_ENA_V << MB_LP_15_INT_ENA_S) +#define MB_LP_15_INT_ENA_V 0x00000001U +#define MB_LP_15_INT_ENA_S 15 + +/** MB_LP_INT_CLR_REG register + * need_des + */ +#define MB_LP_INT_CLR_REG (DR_REG_MB_BASE + 0x4c) +/** MB_LP_0_INT_CLR : WO; bitpos: [0]; default: 0; + * need_des + */ +#define MB_LP_0_INT_CLR (BIT(0)) +#define MB_LP_0_INT_CLR_M (MB_LP_0_INT_CLR_V << MB_LP_0_INT_CLR_S) +#define MB_LP_0_INT_CLR_V 0x00000001U +#define MB_LP_0_INT_CLR_S 0 +/** MB_LP_1_INT_CLR : WO; bitpos: [1]; default: 0; + * need_des + */ +#define MB_LP_1_INT_CLR (BIT(1)) +#define MB_LP_1_INT_CLR_M (MB_LP_1_INT_CLR_V << MB_LP_1_INT_CLR_S) +#define MB_LP_1_INT_CLR_V 0x00000001U +#define MB_LP_1_INT_CLR_S 1 +/** MB_LP_2_INT_CLR : WO; bitpos: [2]; default: 0; + * need_des + */ +#define MB_LP_2_INT_CLR (BIT(2)) +#define MB_LP_2_INT_CLR_M (MB_LP_2_INT_CLR_V << MB_LP_2_INT_CLR_S) +#define MB_LP_2_INT_CLR_V 0x00000001U +#define MB_LP_2_INT_CLR_S 2 +/** MB_LP_3_INT_CLR : WO; bitpos: [3]; default: 0; + * need_des + */ +#define MB_LP_3_INT_CLR (BIT(3)) +#define MB_LP_3_INT_CLR_M (MB_LP_3_INT_CLR_V << MB_LP_3_INT_CLR_S) +#define MB_LP_3_INT_CLR_V 0x00000001U +#define MB_LP_3_INT_CLR_S 3 +/** MB_LP_4_INT_CLR : WO; bitpos: [4]; default: 0; + * need_des + */ +#define MB_LP_4_INT_CLR (BIT(4)) +#define MB_LP_4_INT_CLR_M (MB_LP_4_INT_CLR_V << MB_LP_4_INT_CLR_S) +#define MB_LP_4_INT_CLR_V 0x00000001U +#define MB_LP_4_INT_CLR_S 4 +/** MB_LP_5_INT_CLR : WO; bitpos: [5]; default: 0; + * need_des + */ +#define MB_LP_5_INT_CLR (BIT(5)) +#define MB_LP_5_INT_CLR_M (MB_LP_5_INT_CLR_V << MB_LP_5_INT_CLR_S) +#define MB_LP_5_INT_CLR_V 0x00000001U +#define MB_LP_5_INT_CLR_S 5 +/** MB_LP_6_INT_CLR : WO; bitpos: [6]; default: 0; + * need_des + */ +#define MB_LP_6_INT_CLR (BIT(6)) +#define MB_LP_6_INT_CLR_M (MB_LP_6_INT_CLR_V << MB_LP_6_INT_CLR_S) +#define MB_LP_6_INT_CLR_V 0x00000001U +#define MB_LP_6_INT_CLR_S 6 +/** MB_LP_7_INT_CLR : WO; bitpos: [7]; default: 0; + * need_des + */ +#define MB_LP_7_INT_CLR (BIT(7)) +#define MB_LP_7_INT_CLR_M (MB_LP_7_INT_CLR_V << MB_LP_7_INT_CLR_S) +#define MB_LP_7_INT_CLR_V 0x00000001U +#define MB_LP_7_INT_CLR_S 7 +/** MB_LP_8_INT_CLR : WO; bitpos: [8]; default: 0; + * need_des + */ +#define MB_LP_8_INT_CLR (BIT(8)) +#define MB_LP_8_INT_CLR_M (MB_LP_8_INT_CLR_V << MB_LP_8_INT_CLR_S) +#define MB_LP_8_INT_CLR_V 0x00000001U +#define MB_LP_8_INT_CLR_S 8 +/** MB_LP_9_INT_CLR : WO; bitpos: [9]; default: 0; + * need_des + */ +#define MB_LP_9_INT_CLR (BIT(9)) +#define MB_LP_9_INT_CLR_M (MB_LP_9_INT_CLR_V << MB_LP_9_INT_CLR_S) +#define MB_LP_9_INT_CLR_V 0x00000001U +#define MB_LP_9_INT_CLR_S 9 +/** MB_LP_10_INT_CLR : WO; bitpos: [10]; default: 0; + * need_des + */ +#define MB_LP_10_INT_CLR (BIT(10)) +#define MB_LP_10_INT_CLR_M (MB_LP_10_INT_CLR_V << MB_LP_10_INT_CLR_S) +#define MB_LP_10_INT_CLR_V 0x00000001U +#define MB_LP_10_INT_CLR_S 10 +/** MB_LP_11_INT_CLR : WO; bitpos: [11]; default: 0; + * need_des + */ +#define MB_LP_11_INT_CLR (BIT(11)) +#define MB_LP_11_INT_CLR_M (MB_LP_11_INT_CLR_V << MB_LP_11_INT_CLR_S) +#define MB_LP_11_INT_CLR_V 0x00000001U +#define MB_LP_11_INT_CLR_S 11 +/** MB_LP_12_INT_CLR : WO; bitpos: [12]; default: 0; + * need_des + */ +#define MB_LP_12_INT_CLR (BIT(12)) +#define MB_LP_12_INT_CLR_M (MB_LP_12_INT_CLR_V << MB_LP_12_INT_CLR_S) +#define MB_LP_12_INT_CLR_V 0x00000001U +#define MB_LP_12_INT_CLR_S 12 +/** MB_LP_13_INT_CLR : WO; bitpos: [13]; default: 0; + * need_des + */ +#define MB_LP_13_INT_CLR (BIT(13)) +#define MB_LP_13_INT_CLR_M (MB_LP_13_INT_CLR_V << MB_LP_13_INT_CLR_S) +#define MB_LP_13_INT_CLR_V 0x00000001U +#define MB_LP_13_INT_CLR_S 13 +/** MB_LP_14_INT_CLR : WO; bitpos: [14]; default: 0; + * need_des + */ +#define MB_LP_14_INT_CLR (BIT(14)) +#define MB_LP_14_INT_CLR_M (MB_LP_14_INT_CLR_V << MB_LP_14_INT_CLR_S) +#define MB_LP_14_INT_CLR_V 0x00000001U +#define MB_LP_14_INT_CLR_S 14 +/** MB_LP_15_INT_CLR : WO; bitpos: [15]; default: 0; + * need_des + */ +#define MB_LP_15_INT_CLR (BIT(15)) +#define MB_LP_15_INT_CLR_M (MB_LP_15_INT_CLR_V << MB_LP_15_INT_CLR_S) +#define MB_LP_15_INT_CLR_V 0x00000001U +#define MB_LP_15_INT_CLR_S 15 + +/** MB_HP_INT_RAW_REG register + * need_des + */ +#define MB_HP_INT_RAW_REG (DR_REG_MB_BASE + 0x50) +/** MB_HP_0_INT_RAW : RO; bitpos: [0]; default: 0; + * need_des + */ +#define MB_HP_0_INT_RAW (BIT(0)) +#define MB_HP_0_INT_RAW_M (MB_HP_0_INT_RAW_V << MB_HP_0_INT_RAW_S) +#define MB_HP_0_INT_RAW_V 0x00000001U +#define MB_HP_0_INT_RAW_S 0 +/** MB_HP_1_INT_RAW : RO; bitpos: [1]; default: 0; + * need_des + */ +#define MB_HP_1_INT_RAW (BIT(1)) +#define MB_HP_1_INT_RAW_M (MB_HP_1_INT_RAW_V << MB_HP_1_INT_RAW_S) +#define MB_HP_1_INT_RAW_V 0x00000001U +#define MB_HP_1_INT_RAW_S 1 +/** MB_HP_2_INT_RAW : RO; bitpos: [2]; default: 0; + * need_des + */ +#define MB_HP_2_INT_RAW (BIT(2)) +#define MB_HP_2_INT_RAW_M (MB_HP_2_INT_RAW_V << MB_HP_2_INT_RAW_S) +#define MB_HP_2_INT_RAW_V 0x00000001U +#define MB_HP_2_INT_RAW_S 2 +/** MB_HP_3_INT_RAW : RO; bitpos: [3]; default: 0; + * need_des + */ +#define MB_HP_3_INT_RAW (BIT(3)) +#define MB_HP_3_INT_RAW_M (MB_HP_3_INT_RAW_V << MB_HP_3_INT_RAW_S) +#define MB_HP_3_INT_RAW_V 0x00000001U +#define MB_HP_3_INT_RAW_S 3 +/** MB_HP_4_INT_RAW : RO; bitpos: [4]; default: 0; + * need_des + */ +#define MB_HP_4_INT_RAW (BIT(4)) +#define MB_HP_4_INT_RAW_M (MB_HP_4_INT_RAW_V << MB_HP_4_INT_RAW_S) +#define MB_HP_4_INT_RAW_V 0x00000001U +#define MB_HP_4_INT_RAW_S 4 +/** MB_HP_5_INT_RAW : RO; bitpos: [5]; default: 0; + * need_des + */ +#define MB_HP_5_INT_RAW (BIT(5)) +#define MB_HP_5_INT_RAW_M (MB_HP_5_INT_RAW_V << MB_HP_5_INT_RAW_S) +#define MB_HP_5_INT_RAW_V 0x00000001U +#define MB_HP_5_INT_RAW_S 5 +/** MB_HP_6_INT_RAW : RO; bitpos: [6]; default: 0; + * need_des + */ +#define MB_HP_6_INT_RAW (BIT(6)) +#define MB_HP_6_INT_RAW_M (MB_HP_6_INT_RAW_V << MB_HP_6_INT_RAW_S) +#define MB_HP_6_INT_RAW_V 0x00000001U +#define MB_HP_6_INT_RAW_S 6 +/** MB_HP_7_INT_RAW : RO; bitpos: [7]; default: 0; + * need_des + */ +#define MB_HP_7_INT_RAW (BIT(7)) +#define MB_HP_7_INT_RAW_M (MB_HP_7_INT_RAW_V << MB_HP_7_INT_RAW_S) +#define MB_HP_7_INT_RAW_V 0x00000001U +#define MB_HP_7_INT_RAW_S 7 +/** MB_HP_8_INT_RAW : RO; bitpos: [8]; default: 0; + * need_des + */ +#define MB_HP_8_INT_RAW (BIT(8)) +#define MB_HP_8_INT_RAW_M (MB_HP_8_INT_RAW_V << MB_HP_8_INT_RAW_S) +#define MB_HP_8_INT_RAW_V 0x00000001U +#define MB_HP_8_INT_RAW_S 8 +/** MB_HP_9_INT_RAW : RO; bitpos: [9]; default: 0; + * need_des + */ +#define MB_HP_9_INT_RAW (BIT(9)) +#define MB_HP_9_INT_RAW_M (MB_HP_9_INT_RAW_V << MB_HP_9_INT_RAW_S) +#define MB_HP_9_INT_RAW_V 0x00000001U +#define MB_HP_9_INT_RAW_S 9 +/** MB_HP_10_INT_RAW : RO; bitpos: [10]; default: 0; + * need_des + */ +#define MB_HP_10_INT_RAW (BIT(10)) +#define MB_HP_10_INT_RAW_M (MB_HP_10_INT_RAW_V << MB_HP_10_INT_RAW_S) +#define MB_HP_10_INT_RAW_V 0x00000001U +#define MB_HP_10_INT_RAW_S 10 +/** MB_HP_11_INT_RAW : RO; bitpos: [11]; default: 0; + * need_des + */ +#define MB_HP_11_INT_RAW (BIT(11)) +#define MB_HP_11_INT_RAW_M (MB_HP_11_INT_RAW_V << MB_HP_11_INT_RAW_S) +#define MB_HP_11_INT_RAW_V 0x00000001U +#define MB_HP_11_INT_RAW_S 11 +/** MB_HP_12_INT_RAW : RO; bitpos: [12]; default: 0; + * need_des + */ +#define MB_HP_12_INT_RAW (BIT(12)) +#define MB_HP_12_INT_RAW_M (MB_HP_12_INT_RAW_V << MB_HP_12_INT_RAW_S) +#define MB_HP_12_INT_RAW_V 0x00000001U +#define MB_HP_12_INT_RAW_S 12 +/** MB_HP_13_INT_RAW : RO; bitpos: [13]; default: 0; + * need_des + */ +#define MB_HP_13_INT_RAW (BIT(13)) +#define MB_HP_13_INT_RAW_M (MB_HP_13_INT_RAW_V << MB_HP_13_INT_RAW_S) +#define MB_HP_13_INT_RAW_V 0x00000001U +#define MB_HP_13_INT_RAW_S 13 +/** MB_HP_14_INT_RAW : RO; bitpos: [14]; default: 0; + * need_des + */ +#define MB_HP_14_INT_RAW (BIT(14)) +#define MB_HP_14_INT_RAW_M (MB_HP_14_INT_RAW_V << MB_HP_14_INT_RAW_S) +#define MB_HP_14_INT_RAW_V 0x00000001U +#define MB_HP_14_INT_RAW_S 14 +/** MB_HP_15_INT_RAW : RO; bitpos: [15]; default: 0; + * need_des + */ +#define MB_HP_15_INT_RAW (BIT(15)) +#define MB_HP_15_INT_RAW_M (MB_HP_15_INT_RAW_V << MB_HP_15_INT_RAW_S) +#define MB_HP_15_INT_RAW_V 0x00000001U +#define MB_HP_15_INT_RAW_S 15 + +/** MB_HP_INT_ST_REG register + * need_des + */ +#define MB_HP_INT_ST_REG (DR_REG_MB_BASE + 0x54) +/** MB_HP_0_INT_ST : RO; bitpos: [0]; default: 0; + * need_des + */ +#define MB_HP_0_INT_ST (BIT(0)) +#define MB_HP_0_INT_ST_M (MB_HP_0_INT_ST_V << MB_HP_0_INT_ST_S) +#define MB_HP_0_INT_ST_V 0x00000001U +#define MB_HP_0_INT_ST_S 0 +/** MB_HP_1_INT_ST : RO; bitpos: [1]; default: 0; + * need_des + */ +#define MB_HP_1_INT_ST (BIT(1)) +#define MB_HP_1_INT_ST_M (MB_HP_1_INT_ST_V << MB_HP_1_INT_ST_S) +#define MB_HP_1_INT_ST_V 0x00000001U +#define MB_HP_1_INT_ST_S 1 +/** MB_HP_2_INT_ST : RO; bitpos: [2]; default: 0; + * need_des + */ +#define MB_HP_2_INT_ST (BIT(2)) +#define MB_HP_2_INT_ST_M (MB_HP_2_INT_ST_V << MB_HP_2_INT_ST_S) +#define MB_HP_2_INT_ST_V 0x00000001U +#define MB_HP_2_INT_ST_S 2 +/** MB_HP_3_INT_ST : RO; bitpos: [3]; default: 0; + * need_des + */ +#define MB_HP_3_INT_ST (BIT(3)) +#define MB_HP_3_INT_ST_M (MB_HP_3_INT_ST_V << MB_HP_3_INT_ST_S) +#define MB_HP_3_INT_ST_V 0x00000001U +#define MB_HP_3_INT_ST_S 3 +/** MB_HP_4_INT_ST : RO; bitpos: [4]; default: 0; + * need_des + */ +#define MB_HP_4_INT_ST (BIT(4)) +#define MB_HP_4_INT_ST_M (MB_HP_4_INT_ST_V << MB_HP_4_INT_ST_S) +#define MB_HP_4_INT_ST_V 0x00000001U +#define MB_HP_4_INT_ST_S 4 +/** MB_HP_5_INT_ST : RO; bitpos: [5]; default: 0; + * need_des + */ +#define MB_HP_5_INT_ST (BIT(5)) +#define MB_HP_5_INT_ST_M (MB_HP_5_INT_ST_V << MB_HP_5_INT_ST_S) +#define MB_HP_5_INT_ST_V 0x00000001U +#define MB_HP_5_INT_ST_S 5 +/** MB_HP_6_INT_ST : RO; bitpos: [6]; default: 0; + * need_des + */ +#define MB_HP_6_INT_ST (BIT(6)) +#define MB_HP_6_INT_ST_M (MB_HP_6_INT_ST_V << MB_HP_6_INT_ST_S) +#define MB_HP_6_INT_ST_V 0x00000001U +#define MB_HP_6_INT_ST_S 6 +/** MB_HP_7_INT_ST : RO; bitpos: [7]; default: 0; + * need_des + */ +#define MB_HP_7_INT_ST (BIT(7)) +#define MB_HP_7_INT_ST_M (MB_HP_7_INT_ST_V << MB_HP_7_INT_ST_S) +#define MB_HP_7_INT_ST_V 0x00000001U +#define MB_HP_7_INT_ST_S 7 +/** MB_HP_8_INT_ST : RO; bitpos: [8]; default: 0; + * need_des + */ +#define MB_HP_8_INT_ST (BIT(8)) +#define MB_HP_8_INT_ST_M (MB_HP_8_INT_ST_V << MB_HP_8_INT_ST_S) +#define MB_HP_8_INT_ST_V 0x00000001U +#define MB_HP_8_INT_ST_S 8 +/** MB_HP_9_INT_ST : RO; bitpos: [9]; default: 0; + * need_des + */ +#define MB_HP_9_INT_ST (BIT(9)) +#define MB_HP_9_INT_ST_M (MB_HP_9_INT_ST_V << MB_HP_9_INT_ST_S) +#define MB_HP_9_INT_ST_V 0x00000001U +#define MB_HP_9_INT_ST_S 9 +/** MB_HP_10_INT_ST : RO; bitpos: [10]; default: 0; + * need_des + */ +#define MB_HP_10_INT_ST (BIT(10)) +#define MB_HP_10_INT_ST_M (MB_HP_10_INT_ST_V << MB_HP_10_INT_ST_S) +#define MB_HP_10_INT_ST_V 0x00000001U +#define MB_HP_10_INT_ST_S 10 +/** MB_HP_11_INT_ST : RO; bitpos: [11]; default: 0; + * need_des + */ +#define MB_HP_11_INT_ST (BIT(11)) +#define MB_HP_11_INT_ST_M (MB_HP_11_INT_ST_V << MB_HP_11_INT_ST_S) +#define MB_HP_11_INT_ST_V 0x00000001U +#define MB_HP_11_INT_ST_S 11 +/** MB_HP_12_INT_ST : RO; bitpos: [12]; default: 0; + * need_des + */ +#define MB_HP_12_INT_ST (BIT(12)) +#define MB_HP_12_INT_ST_M (MB_HP_12_INT_ST_V << MB_HP_12_INT_ST_S) +#define MB_HP_12_INT_ST_V 0x00000001U +#define MB_HP_12_INT_ST_S 12 +/** MB_HP_13_INT_ST : RO; bitpos: [13]; default: 0; + * need_des + */ +#define MB_HP_13_INT_ST (BIT(13)) +#define MB_HP_13_INT_ST_M (MB_HP_13_INT_ST_V << MB_HP_13_INT_ST_S) +#define MB_HP_13_INT_ST_V 0x00000001U +#define MB_HP_13_INT_ST_S 13 +/** MB_HP_14_INT_ST : RO; bitpos: [14]; default: 0; + * need_des + */ +#define MB_HP_14_INT_ST (BIT(14)) +#define MB_HP_14_INT_ST_M (MB_HP_14_INT_ST_V << MB_HP_14_INT_ST_S) +#define MB_HP_14_INT_ST_V 0x00000001U +#define MB_HP_14_INT_ST_S 14 +/** MB_HP_15_INT_ST : RO; bitpos: [15]; default: 0; + * need_des + */ +#define MB_HP_15_INT_ST (BIT(15)) +#define MB_HP_15_INT_ST_M (MB_HP_15_INT_ST_V << MB_HP_15_INT_ST_S) +#define MB_HP_15_INT_ST_V 0x00000001U +#define MB_HP_15_INT_ST_S 15 + +/** MB_HP_INT_ENA_REG register + * need_des + */ +#define MB_HP_INT_ENA_REG (DR_REG_MB_BASE + 0x58) +/** MB_HP_0_INT_ENA : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define MB_HP_0_INT_ENA (BIT(0)) +#define MB_HP_0_INT_ENA_M (MB_HP_0_INT_ENA_V << MB_HP_0_INT_ENA_S) +#define MB_HP_0_INT_ENA_V 0x00000001U +#define MB_HP_0_INT_ENA_S 0 +/** MB_HP_1_INT_ENA : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define MB_HP_1_INT_ENA (BIT(1)) +#define MB_HP_1_INT_ENA_M (MB_HP_1_INT_ENA_V << MB_HP_1_INT_ENA_S) +#define MB_HP_1_INT_ENA_V 0x00000001U +#define MB_HP_1_INT_ENA_S 1 +/** MB_HP_2_INT_ENA : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define MB_HP_2_INT_ENA (BIT(2)) +#define MB_HP_2_INT_ENA_M (MB_HP_2_INT_ENA_V << MB_HP_2_INT_ENA_S) +#define MB_HP_2_INT_ENA_V 0x00000001U +#define MB_HP_2_INT_ENA_S 2 +/** MB_HP_3_INT_ENA : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define MB_HP_3_INT_ENA (BIT(3)) +#define MB_HP_3_INT_ENA_M (MB_HP_3_INT_ENA_V << MB_HP_3_INT_ENA_S) +#define MB_HP_3_INT_ENA_V 0x00000001U +#define MB_HP_3_INT_ENA_S 3 +/** MB_HP_4_INT_ENA : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define MB_HP_4_INT_ENA (BIT(4)) +#define MB_HP_4_INT_ENA_M (MB_HP_4_INT_ENA_V << MB_HP_4_INT_ENA_S) +#define MB_HP_4_INT_ENA_V 0x00000001U +#define MB_HP_4_INT_ENA_S 4 +/** MB_HP_5_INT_ENA : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define MB_HP_5_INT_ENA (BIT(5)) +#define MB_HP_5_INT_ENA_M (MB_HP_5_INT_ENA_V << MB_HP_5_INT_ENA_S) +#define MB_HP_5_INT_ENA_V 0x00000001U +#define MB_HP_5_INT_ENA_S 5 +/** MB_HP_6_INT_ENA : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define MB_HP_6_INT_ENA (BIT(6)) +#define MB_HP_6_INT_ENA_M (MB_HP_6_INT_ENA_V << MB_HP_6_INT_ENA_S) +#define MB_HP_6_INT_ENA_V 0x00000001U +#define MB_HP_6_INT_ENA_S 6 +/** MB_HP_7_INT_ENA : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define MB_HP_7_INT_ENA (BIT(7)) +#define MB_HP_7_INT_ENA_M (MB_HP_7_INT_ENA_V << MB_HP_7_INT_ENA_S) +#define MB_HP_7_INT_ENA_V 0x00000001U +#define MB_HP_7_INT_ENA_S 7 +/** MB_HP_8_INT_ENA : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define MB_HP_8_INT_ENA (BIT(8)) +#define MB_HP_8_INT_ENA_M (MB_HP_8_INT_ENA_V << MB_HP_8_INT_ENA_S) +#define MB_HP_8_INT_ENA_V 0x00000001U +#define MB_HP_8_INT_ENA_S 8 +/** MB_HP_9_INT_ENA : R/W; bitpos: [9]; default: 0; + * need_des + */ +#define MB_HP_9_INT_ENA (BIT(9)) +#define MB_HP_9_INT_ENA_M (MB_HP_9_INT_ENA_V << MB_HP_9_INT_ENA_S) +#define MB_HP_9_INT_ENA_V 0x00000001U +#define MB_HP_9_INT_ENA_S 9 +/** MB_HP_10_INT_ENA : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define MB_HP_10_INT_ENA (BIT(10)) +#define MB_HP_10_INT_ENA_M (MB_HP_10_INT_ENA_V << MB_HP_10_INT_ENA_S) +#define MB_HP_10_INT_ENA_V 0x00000001U +#define MB_HP_10_INT_ENA_S 10 +/** MB_HP_11_INT_ENA : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define MB_HP_11_INT_ENA (BIT(11)) +#define MB_HP_11_INT_ENA_M (MB_HP_11_INT_ENA_V << MB_HP_11_INT_ENA_S) +#define MB_HP_11_INT_ENA_V 0x00000001U +#define MB_HP_11_INT_ENA_S 11 +/** MB_HP_12_INT_ENA : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define MB_HP_12_INT_ENA (BIT(12)) +#define MB_HP_12_INT_ENA_M (MB_HP_12_INT_ENA_V << MB_HP_12_INT_ENA_S) +#define MB_HP_12_INT_ENA_V 0x00000001U +#define MB_HP_12_INT_ENA_S 12 +/** MB_HP_13_INT_ENA : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define MB_HP_13_INT_ENA (BIT(13)) +#define MB_HP_13_INT_ENA_M (MB_HP_13_INT_ENA_V << MB_HP_13_INT_ENA_S) +#define MB_HP_13_INT_ENA_V 0x00000001U +#define MB_HP_13_INT_ENA_S 13 +/** MB_HP_14_INT_ENA : R/W; bitpos: [14]; default: 0; + * need_des + */ +#define MB_HP_14_INT_ENA (BIT(14)) +#define MB_HP_14_INT_ENA_M (MB_HP_14_INT_ENA_V << MB_HP_14_INT_ENA_S) +#define MB_HP_14_INT_ENA_V 0x00000001U +#define MB_HP_14_INT_ENA_S 14 +/** MB_HP_15_INT_ENA : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define MB_HP_15_INT_ENA (BIT(15)) +#define MB_HP_15_INT_ENA_M (MB_HP_15_INT_ENA_V << MB_HP_15_INT_ENA_S) +#define MB_HP_15_INT_ENA_V 0x00000001U +#define MB_HP_15_INT_ENA_S 15 + +/** MB_HP_INT_CLR_REG register + * need_des + */ +#define MB_HP_INT_CLR_REG (DR_REG_MB_BASE + 0x5c) +/** MB_HP_0_INT_CLR : WO; bitpos: [0]; default: 0; + * need_des + */ +#define MB_HP_0_INT_CLR (BIT(0)) +#define MB_HP_0_INT_CLR_M (MB_HP_0_INT_CLR_V << MB_HP_0_INT_CLR_S) +#define MB_HP_0_INT_CLR_V 0x00000001U +#define MB_HP_0_INT_CLR_S 0 +/** MB_HP_1_INT_CLR : WO; bitpos: [1]; default: 0; + * need_des + */ +#define MB_HP_1_INT_CLR (BIT(1)) +#define MB_HP_1_INT_CLR_M (MB_HP_1_INT_CLR_V << MB_HP_1_INT_CLR_S) +#define MB_HP_1_INT_CLR_V 0x00000001U +#define MB_HP_1_INT_CLR_S 1 +/** MB_HP_2_INT_CLR : WO; bitpos: [2]; default: 0; + * need_des + */ +#define MB_HP_2_INT_CLR (BIT(2)) +#define MB_HP_2_INT_CLR_M (MB_HP_2_INT_CLR_V << MB_HP_2_INT_CLR_S) +#define MB_HP_2_INT_CLR_V 0x00000001U +#define MB_HP_2_INT_CLR_S 2 +/** MB_HP_3_INT_CLR : WO; bitpos: [3]; default: 0; + * need_des + */ +#define MB_HP_3_INT_CLR (BIT(3)) +#define MB_HP_3_INT_CLR_M (MB_HP_3_INT_CLR_V << MB_HP_3_INT_CLR_S) +#define MB_HP_3_INT_CLR_V 0x00000001U +#define MB_HP_3_INT_CLR_S 3 +/** MB_HP_4_INT_CLR : WO; bitpos: [4]; default: 0; + * need_des + */ +#define MB_HP_4_INT_CLR (BIT(4)) +#define MB_HP_4_INT_CLR_M (MB_HP_4_INT_CLR_V << MB_HP_4_INT_CLR_S) +#define MB_HP_4_INT_CLR_V 0x00000001U +#define MB_HP_4_INT_CLR_S 4 +/** MB_HP_5_INT_CLR : WO; bitpos: [5]; default: 0; + * need_des + */ +#define MB_HP_5_INT_CLR (BIT(5)) +#define MB_HP_5_INT_CLR_M (MB_HP_5_INT_CLR_V << MB_HP_5_INT_CLR_S) +#define MB_HP_5_INT_CLR_V 0x00000001U +#define MB_HP_5_INT_CLR_S 5 +/** MB_HP_6_INT_CLR : WO; bitpos: [6]; default: 0; + * need_des + */ +#define MB_HP_6_INT_CLR (BIT(6)) +#define MB_HP_6_INT_CLR_M (MB_HP_6_INT_CLR_V << MB_HP_6_INT_CLR_S) +#define MB_HP_6_INT_CLR_V 0x00000001U +#define MB_HP_6_INT_CLR_S 6 +/** MB_HP_7_INT_CLR : WO; bitpos: [7]; default: 0; + * need_des + */ +#define MB_HP_7_INT_CLR (BIT(7)) +#define MB_HP_7_INT_CLR_M (MB_HP_7_INT_CLR_V << MB_HP_7_INT_CLR_S) +#define MB_HP_7_INT_CLR_V 0x00000001U +#define MB_HP_7_INT_CLR_S 7 +/** MB_HP_8_INT_CLR : WO; bitpos: [8]; default: 0; + * need_des + */ +#define MB_HP_8_INT_CLR (BIT(8)) +#define MB_HP_8_INT_CLR_M (MB_HP_8_INT_CLR_V << MB_HP_8_INT_CLR_S) +#define MB_HP_8_INT_CLR_V 0x00000001U +#define MB_HP_8_INT_CLR_S 8 +/** MB_HP_9_INT_CLR : WO; bitpos: [9]; default: 0; + * need_des + */ +#define MB_HP_9_INT_CLR (BIT(9)) +#define MB_HP_9_INT_CLR_M (MB_HP_9_INT_CLR_V << MB_HP_9_INT_CLR_S) +#define MB_HP_9_INT_CLR_V 0x00000001U +#define MB_HP_9_INT_CLR_S 9 +/** MB_HP_10_INT_CLR : WO; bitpos: [10]; default: 0; + * need_des + */ +#define MB_HP_10_INT_CLR (BIT(10)) +#define MB_HP_10_INT_CLR_M (MB_HP_10_INT_CLR_V << MB_HP_10_INT_CLR_S) +#define MB_HP_10_INT_CLR_V 0x00000001U +#define MB_HP_10_INT_CLR_S 10 +/** MB_HP_11_INT_CLR : WO; bitpos: [11]; default: 0; + * need_des + */ +#define MB_HP_11_INT_CLR (BIT(11)) +#define MB_HP_11_INT_CLR_M (MB_HP_11_INT_CLR_V << MB_HP_11_INT_CLR_S) +#define MB_HP_11_INT_CLR_V 0x00000001U +#define MB_HP_11_INT_CLR_S 11 +/** MB_HP_12_INT_CLR : WO; bitpos: [12]; default: 0; + * need_des + */ +#define MB_HP_12_INT_CLR (BIT(12)) +#define MB_HP_12_INT_CLR_M (MB_HP_12_INT_CLR_V << MB_HP_12_INT_CLR_S) +#define MB_HP_12_INT_CLR_V 0x00000001U +#define MB_HP_12_INT_CLR_S 12 +/** MB_HP_13_INT_CLR : WO; bitpos: [13]; default: 0; + * need_des + */ +#define MB_HP_13_INT_CLR (BIT(13)) +#define MB_HP_13_INT_CLR_M (MB_HP_13_INT_CLR_V << MB_HP_13_INT_CLR_S) +#define MB_HP_13_INT_CLR_V 0x00000001U +#define MB_HP_13_INT_CLR_S 13 +/** MB_HP_14_INT_CLR : WO; bitpos: [14]; default: 0; + * need_des + */ +#define MB_HP_14_INT_CLR (BIT(14)) +#define MB_HP_14_INT_CLR_M (MB_HP_14_INT_CLR_V << MB_HP_14_INT_CLR_S) +#define MB_HP_14_INT_CLR_V 0x00000001U +#define MB_HP_14_INT_CLR_S 14 +/** MB_HP_15_INT_CLR : WO; bitpos: [15]; default: 0; + * need_des + */ +#define MB_HP_15_INT_CLR (BIT(15)) +#define MB_HP_15_INT_CLR_M (MB_HP_15_INT_CLR_V << MB_HP_15_INT_CLR_S) +#define MB_HP_15_INT_CLR_V 0x00000001U +#define MB_HP_15_INT_CLR_S 15 + +/** MB_REG_CLK_EN_REG register + * need_des + */ +#define MB_REG_CLK_EN_REG (DR_REG_MB_BASE + 0x60) +/** MB_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define MB_REG_CLK_EN (BIT(0)) +#define MB_REG_CLK_EN_M (MB_REG_CLK_EN_V << MB_REG_CLK_EN_S) +#define MB_REG_CLK_EN_V 0x00000001U +#define MB_REG_CLK_EN_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_struct.h new file mode 100644 index 0000000000..16e0a721e2 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_mailbox_struct.h @@ -0,0 +1,867 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of massege_0 register + * need_des + */ +typedef union { + struct { + /** massege_0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_0:32; + }; + uint32_t val; +} mb_massege_0_reg_t; + +/** Type of massege_1 register + * need_des + */ +typedef union { + struct { + /** massege_1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_1:32; + }; + uint32_t val; +} mb_massege_1_reg_t; + +/** Type of massege_2 register + * need_des + */ +typedef union { + struct { + /** massege_2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_2:32; + }; + uint32_t val; +} mb_massege_2_reg_t; + +/** Type of massege_3 register + * need_des + */ +typedef union { + struct { + /** massege_3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_3:32; + }; + uint32_t val; +} mb_massege_3_reg_t; + +/** Type of massege_4 register + * need_des + */ +typedef union { + struct { + /** massege_4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_4:32; + }; + uint32_t val; +} mb_massege_4_reg_t; + +/** Type of massege_5 register + * need_des + */ +typedef union { + struct { + /** massege_5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_5:32; + }; + uint32_t val; +} mb_massege_5_reg_t; + +/** Type of massege_6 register + * need_des + */ +typedef union { + struct { + /** massege_6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_6:32; + }; + uint32_t val; +} mb_massege_6_reg_t; + +/** Type of massege_7 register + * need_des + */ +typedef union { + struct { + /** massege_7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_7:32; + }; + uint32_t val; +} mb_massege_7_reg_t; + +/** Type of massege_8 register + * need_des + */ +typedef union { + struct { + /** massege_8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_8:32; + }; + uint32_t val; +} mb_massege_8_reg_t; + +/** Type of massege_9 register + * need_des + */ +typedef union { + struct { + /** massege_9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_9:32; + }; + uint32_t val; +} mb_massege_9_reg_t; + +/** Type of massege_10 register + * need_des + */ +typedef union { + struct { + /** massege_10 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_10:32; + }; + uint32_t val; +} mb_massege_10_reg_t; + +/** Type of massege_11 register + * need_des + */ +typedef union { + struct { + /** massege_11 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_11:32; + }; + uint32_t val; +} mb_massege_11_reg_t; + +/** Type of massege_12 register + * need_des + */ +typedef union { + struct { + /** massege_12 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_12:32; + }; + uint32_t val; +} mb_massege_12_reg_t; + +/** Type of massege_13 register + * need_des + */ +typedef union { + struct { + /** massege_13 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_13:32; + }; + uint32_t val; +} mb_massege_13_reg_t; + +/** Type of massege_14 register + * need_des + */ +typedef union { + struct { + /** massege_14 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_14:32; + }; + uint32_t val; +} mb_massege_14_reg_t; + +/** Type of massege_15 register + * need_des + */ +typedef union { + struct { + /** massege_15 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t massege_15:32; + }; + uint32_t val; +} mb_massege_15_reg_t; + +/** Type of reg_clk_en register + * need_des + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mb_reg_clk_en_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + /** lp_0_int_raw : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_0_int_raw:1; + /** lp_1_int_raw : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_1_int_raw:1; + /** lp_2_int_raw : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t lp_2_int_raw:1; + /** lp_3_int_raw : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t lp_3_int_raw:1; + /** lp_4_int_raw : RO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t lp_4_int_raw:1; + /** lp_5_int_raw : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t lp_5_int_raw:1; + /** lp_6_int_raw : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t lp_6_int_raw:1; + /** lp_7_int_raw : RO; bitpos: [7]; default: 0; + * need_des + */ + uint32_t lp_7_int_raw:1; + /** lp_8_int_raw : RO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t lp_8_int_raw:1; + /** lp_9_int_raw : RO; bitpos: [9]; default: 0; + * need_des + */ + uint32_t lp_9_int_raw:1; + /** lp_10_int_raw : RO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_10_int_raw:1; + /** lp_11_int_raw : RO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t lp_11_int_raw:1; + /** lp_12_int_raw : RO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t lp_12_int_raw:1; + /** lp_13_int_raw : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_13_int_raw:1; + /** lp_14_int_raw : RO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t lp_14_int_raw:1; + /** lp_15_int_raw : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t lp_15_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + /** lp_0_int_st : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_0_int_st:1; + /** lp_1_int_st : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_1_int_st:1; + /** lp_2_int_st : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t lp_2_int_st:1; + /** lp_3_int_st : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t lp_3_int_st:1; + /** lp_4_int_st : RO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t lp_4_int_st:1; + /** lp_5_int_st : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t lp_5_int_st:1; + /** lp_6_int_st : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t lp_6_int_st:1; + /** lp_7_int_st : RO; bitpos: [7]; default: 0; + * need_des + */ + uint32_t lp_7_int_st:1; + /** lp_8_int_st : RO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t lp_8_int_st:1; + /** lp_9_int_st : RO; bitpos: [9]; default: 0; + * need_des + */ + uint32_t lp_9_int_st:1; + /** lp_10_int_st : RO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_10_int_st:1; + /** lp_11_int_st : RO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t lp_11_int_st:1; + /** lp_12_int_st : RO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t lp_12_int_st:1; + /** lp_13_int_st : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_13_int_st:1; + /** lp_14_int_st : RO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t lp_14_int_st:1; + /** lp_15_int_st : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t lp_15_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + /** lp_0_int_ena : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t lp_0_int_ena:1; + /** lp_1_int_ena : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t lp_1_int_ena:1; + /** lp_2_int_ena : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t lp_2_int_ena:1; + /** lp_3_int_ena : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t lp_3_int_ena:1; + /** lp_4_int_ena : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t lp_4_int_ena:1; + /** lp_5_int_ena : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t lp_5_int_ena:1; + /** lp_6_int_ena : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t lp_6_int_ena:1; + /** lp_7_int_ena : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t lp_7_int_ena:1; + /** lp_8_int_ena : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t lp_8_int_ena:1; + /** lp_9_int_ena : R/W; bitpos: [9]; default: 0; + * need_des + */ + uint32_t lp_9_int_ena:1; + /** lp_10_int_ena : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_10_int_ena:1; + /** lp_11_int_ena : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t lp_11_int_ena:1; + /** lp_12_int_ena : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t lp_12_int_ena:1; + /** lp_13_int_ena : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_13_int_ena:1; + /** lp_14_int_ena : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t lp_14_int_ena:1; + /** lp_15_int_ena : R/W; bitpos: [15]; default: 0; + * need_des + */ + uint32_t lp_15_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + /** lp_0_int_clr : WO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_0_int_clr:1; + /** lp_1_int_clr : WO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_1_int_clr:1; + /** lp_2_int_clr : WO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t lp_2_int_clr:1; + /** lp_3_int_clr : WO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t lp_3_int_clr:1; + /** lp_4_int_clr : WO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t lp_4_int_clr:1; + /** lp_5_int_clr : WO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t lp_5_int_clr:1; + /** lp_6_int_clr : WO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t lp_6_int_clr:1; + /** lp_7_int_clr : WO; bitpos: [7]; default: 0; + * need_des + */ + uint32_t lp_7_int_clr:1; + /** lp_8_int_clr : WO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t lp_8_int_clr:1; + /** lp_9_int_clr : WO; bitpos: [9]; default: 0; + * need_des + */ + uint32_t lp_9_int_clr:1; + /** lp_10_int_clr : WO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t lp_10_int_clr:1; + /** lp_11_int_clr : WO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t lp_11_int_clr:1; + /** lp_12_int_clr : WO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t lp_12_int_clr:1; + /** lp_13_int_clr : WO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t lp_13_int_clr:1; + /** lp_14_int_clr : WO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t lp_14_int_clr:1; + /** lp_15_int_clr : WO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t lp_15_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_lp_int_clr_reg_t; + +/** Type of hp_int_raw register + * need_des + */ +typedef union { + struct { + /** hp_0_int_raw : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_0_int_raw:1; + /** hp_1_int_raw : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t hp_1_int_raw:1; + /** hp_2_int_raw : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t hp_2_int_raw:1; + /** hp_3_int_raw : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t hp_3_int_raw:1; + /** hp_4_int_raw : RO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t hp_4_int_raw:1; + /** hp_5_int_raw : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t hp_5_int_raw:1; + /** hp_6_int_raw : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t hp_6_int_raw:1; + /** hp_7_int_raw : RO; bitpos: [7]; default: 0; + * need_des + */ + uint32_t hp_7_int_raw:1; + /** hp_8_int_raw : RO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t hp_8_int_raw:1; + /** hp_9_int_raw : RO; bitpos: [9]; default: 0; + * need_des + */ + uint32_t hp_9_int_raw:1; + /** hp_10_int_raw : RO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_10_int_raw:1; + /** hp_11_int_raw : RO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_11_int_raw:1; + /** hp_12_int_raw : RO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_12_int_raw:1; + /** hp_13_int_raw : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_13_int_raw:1; + /** hp_14_int_raw : RO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t hp_14_int_raw:1; + /** hp_15_int_raw : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t hp_15_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_hp_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + /** hp_0_int_st : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_0_int_st:1; + /** hp_1_int_st : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t hp_1_int_st:1; + /** hp_2_int_st : RO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t hp_2_int_st:1; + /** hp_3_int_st : RO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t hp_3_int_st:1; + /** hp_4_int_st : RO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t hp_4_int_st:1; + /** hp_5_int_st : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t hp_5_int_st:1; + /** hp_6_int_st : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t hp_6_int_st:1; + /** hp_7_int_st : RO; bitpos: [7]; default: 0; + * need_des + */ + uint32_t hp_7_int_st:1; + /** hp_8_int_st : RO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t hp_8_int_st:1; + /** hp_9_int_st : RO; bitpos: [9]; default: 0; + * need_des + */ + uint32_t hp_9_int_st:1; + /** hp_10_int_st : RO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_10_int_st:1; + /** hp_11_int_st : RO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_11_int_st:1; + /** hp_12_int_st : RO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_12_int_st:1; + /** hp_13_int_st : RO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_13_int_st:1; + /** hp_14_int_st : RO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t hp_14_int_st:1; + /** hp_15_int_st : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t hp_15_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + /** hp_0_int_ena : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t hp_0_int_ena:1; + /** hp_1_int_ena : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t hp_1_int_ena:1; + /** hp_2_int_ena : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t hp_2_int_ena:1; + /** hp_3_int_ena : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t hp_3_int_ena:1; + /** hp_4_int_ena : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t hp_4_int_ena:1; + /** hp_5_int_ena : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t hp_5_int_ena:1; + /** hp_6_int_ena : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t hp_6_int_ena:1; + /** hp_7_int_ena : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t hp_7_int_ena:1; + /** hp_8_int_ena : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t hp_8_int_ena:1; + /** hp_9_int_ena : R/W; bitpos: [9]; default: 0; + * need_des + */ + uint32_t hp_9_int_ena:1; + /** hp_10_int_ena : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_10_int_ena:1; + /** hp_11_int_ena : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_11_int_ena:1; + /** hp_12_int_ena : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_12_int_ena:1; + /** hp_13_int_ena : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_13_int_ena:1; + /** hp_14_int_ena : R/W; bitpos: [14]; default: 0; + * need_des + */ + uint32_t hp_14_int_ena:1; + /** hp_15_int_ena : R/W; bitpos: [15]; default: 0; + * need_des + */ + uint32_t hp_15_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + /** hp_0_int_clr : WO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t hp_0_int_clr:1; + /** hp_1_int_clr : WO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t hp_1_int_clr:1; + /** hp_2_int_clr : WO; bitpos: [2]; default: 0; + * need_des + */ + uint32_t hp_2_int_clr:1; + /** hp_3_int_clr : WO; bitpos: [3]; default: 0; + * need_des + */ + uint32_t hp_3_int_clr:1; + /** hp_4_int_clr : WO; bitpos: [4]; default: 0; + * need_des + */ + uint32_t hp_4_int_clr:1; + /** hp_5_int_clr : WO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t hp_5_int_clr:1; + /** hp_6_int_clr : WO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t hp_6_int_clr:1; + /** hp_7_int_clr : WO; bitpos: [7]; default: 0; + * need_des + */ + uint32_t hp_7_int_clr:1; + /** hp_8_int_clr : WO; bitpos: [8]; default: 0; + * need_des + */ + uint32_t hp_8_int_clr:1; + /** hp_9_int_clr : WO; bitpos: [9]; default: 0; + * need_des + */ + uint32_t hp_9_int_clr:1; + /** hp_10_int_clr : WO; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_10_int_clr:1; + /** hp_11_int_clr : WO; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_11_int_clr:1; + /** hp_12_int_clr : WO; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_12_int_clr:1; + /** hp_13_int_clr : WO; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_13_int_clr:1; + /** hp_14_int_clr : WO; bitpos: [14]; default: 0; + * need_des + */ + uint32_t hp_14_int_clr:1; + /** hp_15_int_clr : WO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t hp_15_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} mb_hp_int_clr_reg_t; + + +typedef struct { + volatile mb_massege_0_reg_t massege_0; + volatile mb_massege_1_reg_t massege_1; + volatile mb_massege_2_reg_t massege_2; + volatile mb_massege_3_reg_t massege_3; + volatile mb_massege_4_reg_t massege_4; + volatile mb_massege_5_reg_t massege_5; + volatile mb_massege_6_reg_t massege_6; + volatile mb_massege_7_reg_t massege_7; + volatile mb_massege_8_reg_t massege_8; + volatile mb_massege_9_reg_t massege_9; + volatile mb_massege_10_reg_t massege_10; + volatile mb_massege_11_reg_t massege_11; + volatile mb_massege_12_reg_t massege_12; + volatile mb_massege_13_reg_t massege_13; + volatile mb_massege_14_reg_t massege_14; + volatile mb_massege_15_reg_t massege_15; + volatile mb_lp_int_raw_reg_t lp_int_raw; + volatile mb_lp_int_st_reg_t lp_int_st; + volatile mb_lp_int_ena_reg_t lp_int_ena; + volatile mb_lp_int_clr_reg_t lp_int_clr; + volatile mb_hp_int_raw_reg_t hp_int_raw; + volatile mb_hp_int_st_reg_t hp_int_st; + volatile mb_hp_int_ena_reg_t hp_int_ena; + volatile mb_hp_int_clr_reg_t hp_int_clr; + volatile mb_reg_clk_en_reg_t reg_clk_en; +} mb_dev_t; + +extern mb_dev_t LP_MAILBOX; + +#ifndef __cplusplus +_Static_assert(sizeof(mb_dev_t) == 0x64, "Invalid size of mb_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_eco5_reg.h new file mode 100644 index 0000000000..833e384012 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_eco5_reg.h @@ -0,0 +1,492 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_PMS_DATE_REG register + * NA + */ +#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943; + * NA + */ +#define TEE_TEE_DATE 0xFFFFFFFFU +#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S) +#define TEE_TEE_DATE_V 0xFFFFFFFFU +#define TEE_TEE_DATE_S 0 + +/** TEE_PMS_CLK_EN_REG register + * NA + */ +#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_CLK_EN (BIT(0)) +#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S) +#define TEE_REG_CLK_EN_V 0x00000001U +#define TEE_REG_CLK_EN_S 0 + +/** TEE_LP_MM_PMS_REG0_REG register + * NA + */ +#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_SYSREG_ALLOW (BIT(0)) +#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S) +#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S 0 +/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW (BIT(1)) +#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S) +#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S 1 +/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_TIMER_ALLOW (BIT(2)) +#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S) +#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S 2 +/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW (BIT(3)) +#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S) +#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S 3 +/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_PMU_ALLOW (BIT(4)) +#define TEE_REG_LP_MM_LP_PMU_ALLOW_M (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S) +#define TEE_REG_LP_MM_LP_PMU_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_PMU_ALLOW_S 4 +/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_WDT_ALLOW (BIT(5)) +#define TEE_REG_LP_MM_LP_WDT_ALLOW_M (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S) +#define TEE_REG_LP_MM_LP_WDT_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_WDT_ALLOW_S 5 +/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW (BIT(6)) +#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S) +#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S 6 +/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_RTC_ALLOW (BIT(7)) +#define TEE_REG_LP_MM_LP_RTC_ALLOW_M (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S) +#define TEE_REG_LP_MM_LP_RTC_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_RTC_ALLOW_S 7 +/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW (BIT(8)) +#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S) +#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S 8 +/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_UART_ALLOW (BIT(9)) +#define TEE_REG_LP_MM_LP_UART_ALLOW_M (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S) +#define TEE_REG_LP_MM_LP_UART_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_UART_ALLOW_S 9 +/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_I2C_ALLOW (BIT(10)) +#define TEE_REG_LP_MM_LP_I2C_ALLOW_M (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S) +#define TEE_REG_LP_MM_LP_I2C_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_I2C_ALLOW_S 10 +/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_SPI_ALLOW (BIT(11)) +#define TEE_REG_LP_MM_LP_SPI_ALLOW_M (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S) +#define TEE_REG_LP_MM_LP_SPI_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_SPI_ALLOW_S 11 +/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_I2CMST_ALLOW (BIT(12)) +#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S) +#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S 12 +/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_I2S_ALLOW (BIT(13)) +#define TEE_REG_LP_MM_LP_I2S_ALLOW_M (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S) +#define TEE_REG_LP_MM_LP_I2S_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_I2S_ALLOW_S 13 +/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_ADC_ALLOW (BIT(14)) +#define TEE_REG_LP_MM_LP_ADC_ALLOW_M (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S) +#define TEE_REG_LP_MM_LP_ADC_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_ADC_ALLOW_S 14 +/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_TOUCH_ALLOW (BIT(15)) +#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S) +#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S 15 +/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_IOMUX_ALLOW (BIT(16)) +#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S) +#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S 16 +/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_INTR_ALLOW (BIT(17)) +#define TEE_REG_LP_MM_LP_INTR_ALLOW_M (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S) +#define TEE_REG_LP_MM_LP_INTR_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_INTR_ALLOW_S 17 +/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_EFUSE_ALLOW (BIT(18)) +#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S) +#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S 18 +/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_PMS_ALLOW (BIT(19)) +#define TEE_REG_LP_MM_LP_PMS_ALLOW_M (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S) +#define TEE_REG_LP_MM_LP_PMS_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_PMS_ALLOW_S 19 +/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW (BIT(20)) +#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S) +#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S 20 +/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_TSENS_ALLOW (BIT(21)) +#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S) +#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S 21 +/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_HUK_ALLOW (BIT(22)) +#define TEE_REG_LP_MM_LP_HUK_ALLOW_M (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S) +#define TEE_REG_LP_MM_LP_HUK_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_HUK_ALLOW_S 22 +/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW (BIT(23)) +#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S) +#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S 23 +/** TEE_REG_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1; + * NA + */ +#define TEE_REG_LP_MM_LP_TRNG_ALLOW (BIT(24)) +#define TEE_REG_LP_MM_LP_TRNG_ALLOW_M (TEE_REG_LP_MM_LP_TRNG_ALLOW_V << TEE_REG_LP_MM_LP_TRNG_ALLOW_S) +#define TEE_REG_LP_MM_LP_TRNG_ALLOW_V 0x00000001U +#define TEE_REG_LP_MM_LP_TRNG_ALLOW_S 24 + +/** TEE_PERI_REGION0_LOW_REG register + * NA + */ +#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION0_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION0_LOW_M (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S) +#define TEE_REG_PERI_REGION0_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION0_LOW_S 2 + +/** TEE_PERI_REGION0_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION0_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION0_HIGH_M (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S) +#define TEE_REG_PERI_REGION0_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION0_HIGH_S 2 + +/** TEE_PERI_REGION1_LOW_REG register + * NA + */ +#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION1_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION1_LOW_M (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S) +#define TEE_REG_PERI_REGION1_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION1_LOW_S 2 + +/** TEE_PERI_REGION1_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION1_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION1_HIGH_M (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S) +#define TEE_REG_PERI_REGION1_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION1_HIGH_S 2 + +/** TEE_PERI_REGION_PMS_REG register + * NA + */ +#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3; + * NA + */ +#define TEE_REG_LP_CORE_REGION_PMS 0x00000003U +#define TEE_REG_LP_CORE_REGION_PMS_M (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S) +#define TEE_REG_LP_CORE_REGION_PMS_V 0x00000003U +#define TEE_REG_LP_CORE_REGION_PMS_S 0 +/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3; + * NA + */ +#define TEE_REG_HP_CORE0_UM_REGION_PMS 0x00000003U +#define TEE_REG_HP_CORE0_UM_REGION_PMS_M (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S) +#define TEE_REG_HP_CORE0_UM_REGION_PMS_V 0x00000003U +#define TEE_REG_HP_CORE0_UM_REGION_PMS_S 2 +/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3; + * NA + */ +#define TEE_REG_HP_CORE0_MM_REGION_PMS 0x00000003U +#define TEE_REG_HP_CORE0_MM_REGION_PMS_M (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S) +#define TEE_REG_HP_CORE0_MM_REGION_PMS_V 0x00000003U +#define TEE_REG_HP_CORE0_MM_REGION_PMS_S 4 +/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3; + * NA + */ +#define TEE_REG_HP_CORE1_UM_REGION_PMS 0x00000003U +#define TEE_REG_HP_CORE1_UM_REGION_PMS_M (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S) +#define TEE_REG_HP_CORE1_UM_REGION_PMS_V 0x00000003U +#define TEE_REG_HP_CORE1_UM_REGION_PMS_S 6 +/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3; + * NA + */ +#define TEE_REG_HP_CORE1_MM_REGION_PMS 0x00000003U +#define TEE_REG_HP_CORE1_MM_REGION_PMS_M (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S) +#define TEE_REG_HP_CORE1_MM_REGION_PMS_V 0x00000003U +#define TEE_REG_HP_CORE1_MM_REGION_PMS_S 8 + +/** TEE_PERI_REGION_2_TO_7_PMS_REG register + * NA + */ +#define TEE_PERI_REGION_2_TO_7_PMS_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_REG_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63; + * NA + */ +#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS 0x0000003FU +#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_M (TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V << TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S) +#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V 0x0000003FU +#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S 0 +/** TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63; + * NA + */ +#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS 0x0000003FU +#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S) +#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V 0x0000003FU +#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S 6 +/** TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63; + * NA + */ +#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS 0x0000003FU +#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S) +#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V 0x0000003FU +#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S 12 +/** TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63; + * NA + */ +#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS 0x0000003FU +#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S) +#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V 0x0000003FU +#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S 18 +/** TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63; + * NA + */ +#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS 0x0000003FU +#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S) +#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V 0x0000003FU +#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S 24 + +/** TEE_PERI_REGION2_LOW_REG register + * NA + */ +#define TEE_PERI_REGION2_LOW_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_REG_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION2_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION2_LOW_M (TEE_REG_PERI_REGION2_LOW_V << TEE_REG_PERI_REGION2_LOW_S) +#define TEE_REG_PERI_REGION2_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION2_LOW_S 2 + +/** TEE_PERI_REGION2_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION2_HIGH_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_REG_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION2_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION2_HIGH_M (TEE_REG_PERI_REGION2_HIGH_V << TEE_REG_PERI_REGION2_HIGH_S) +#define TEE_REG_PERI_REGION2_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION2_HIGH_S 2 + +/** TEE_PERI_REGION3_LOW_REG register + * NA + */ +#define TEE_PERI_REGION3_LOW_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_REG_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION3_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION3_LOW_M (TEE_REG_PERI_REGION3_LOW_V << TEE_REG_PERI_REGION3_LOW_S) +#define TEE_REG_PERI_REGION3_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION3_LOW_S 2 + +/** TEE_PERI_REGION3_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION3_HIGH_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_REG_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION3_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION3_HIGH_M (TEE_REG_PERI_REGION3_HIGH_V << TEE_REG_PERI_REGION3_HIGH_S) +#define TEE_REG_PERI_REGION3_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION3_HIGH_S 2 + +/** TEE_PERI_REGION4_LOW_REG register + * NA + */ +#define TEE_PERI_REGION4_LOW_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_REG_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION4_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION4_LOW_M (TEE_REG_PERI_REGION4_LOW_V << TEE_REG_PERI_REGION4_LOW_S) +#define TEE_REG_PERI_REGION4_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION4_LOW_S 2 + +/** TEE_PERI_REGION4_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION4_HIGH_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_REG_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION4_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION4_HIGH_M (TEE_REG_PERI_REGION4_HIGH_V << TEE_REG_PERI_REGION4_HIGH_S) +#define TEE_REG_PERI_REGION4_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION4_HIGH_S 2 + +/** TEE_PERI_REGION5_LOW_REG register + * NA + */ +#define TEE_PERI_REGION5_LOW_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_REG_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION5_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION5_LOW_M (TEE_REG_PERI_REGION5_LOW_V << TEE_REG_PERI_REGION5_LOW_S) +#define TEE_REG_PERI_REGION5_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION5_LOW_S 2 + +/** TEE_PERI_REGION5_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION5_HIGH_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_REG_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION5_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION5_HIGH_M (TEE_REG_PERI_REGION5_HIGH_V << TEE_REG_PERI_REGION5_HIGH_S) +#define TEE_REG_PERI_REGION5_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION5_HIGH_S 2 + +/** TEE_PERI_REGION6_LOW_REG register + * NA + */ +#define TEE_PERI_REGION6_LOW_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_REG_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION6_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION6_LOW_M (TEE_REG_PERI_REGION6_LOW_V << TEE_REG_PERI_REGION6_LOW_S) +#define TEE_REG_PERI_REGION6_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION6_LOW_S 2 + +/** TEE_PERI_REGION6_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION6_HIGH_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_REG_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION6_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION6_HIGH_M (TEE_REG_PERI_REGION6_HIGH_V << TEE_REG_PERI_REGION6_HIGH_S) +#define TEE_REG_PERI_REGION6_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION6_HIGH_S 2 + +/** TEE_PERI_REGION7_LOW_REG register + * NA + */ +#define TEE_PERI_REGION7_LOW_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_REG_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0; + * NA + */ +#define TEE_REG_PERI_REGION7_LOW 0x3FFFFFFFU +#define TEE_REG_PERI_REGION7_LOW_M (TEE_REG_PERI_REGION7_LOW_V << TEE_REG_PERI_REGION7_LOW_S) +#define TEE_REG_PERI_REGION7_LOW_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION7_LOW_S 2 + +/** TEE_PERI_REGION7_HIGH_REG register + * NA + */ +#define TEE_PERI_REGION7_HIGH_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_REG_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ +#define TEE_REG_PERI_REGION7_HIGH 0x3FFFFFFFU +#define TEE_REG_PERI_REGION7_HIGH_M (TEE_REG_PERI_REGION7_HIGH_V << TEE_REG_PERI_REGION7_HIGH_S) +#define TEE_REG_PERI_REGION7_HIGH_V 0x3FFFFFFFU +#define TEE_REG_PERI_REGION7_HIGH_S 2 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_reg.h new file mode 100644 index 0000000000..11055cc05b --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_reg.h @@ -0,0 +1,377 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMS_LP_PERI_PMS_DATE_REG register + * Version control register + */ +#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0) +/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537; + * Version control register + */ +#define PMS_LP_PERI_PMS_DATE 0xFFFFFFFFU +#define PMS_LP_PERI_PMS_DATE_M (PMS_LP_PERI_PMS_DATE_V << PMS_LP_PERI_PMS_DATE_S) +#define PMS_LP_PERI_PMS_DATE_V 0xFFFFFFFFU +#define PMS_LP_PERI_PMS_DATE_S 0 + +/** PMS_LP_PERI_PMS_CLK_EN_REG register + * Clock gating register + */ +#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_LP_PERI_PMS_BASE + 0x4) +/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on + */ +#define PMS_LP_PERI_PMS_CLK_EN (BIT(0)) +#define PMS_LP_PERI_PMS_CLK_EN_M (PMS_LP_PERI_PMS_CLK_EN_V << PMS_LP_PERI_PMS_CLK_EN_S) +#define PMS_LP_PERI_PMS_CLK_EN_V 0x00000001U +#define PMS_LP_PERI_PMS_CLK_EN_S 0 + +/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register + * Permission control register0 for LP CPU in machine mode + */ +#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_LP_PERI_PMS_BASE + 0x8) +/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP system + * registers. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_SYSREG_ALLOW (BIT(0)) +#define PMS_LP_MM_LP_SYSREG_ALLOW_M (PMS_LP_MM_LP_SYSREG_ALLOW_V << PMS_LP_MM_LP_SYSREG_ALLOW_S) +#define PMS_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_SYSREG_ALLOW_S 0 +/** PMS_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP + * always-on clock and reset). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_AONCLKRST_ALLOW (BIT(1)) +#define PMS_LP_MM_LP_AONCLKRST_ALLOW_M (PMS_LP_MM_LP_AONCLKRST_ALLOW_V << PMS_LP_MM_LP_AONCLKRST_ALLOW_S) +#define PMS_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_AONCLKRST_ALLOW_S 1 +/** PMS_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP timer. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_TIMER_ALLOW (BIT(2)) +#define PMS_LP_MM_LP_TIMER_ALLOW_M (PMS_LP_MM_LP_TIMER_ALLOW_V << PMS_LP_MM_LP_TIMER_ALLOW_S) +#define PMS_LP_MM_LP_TIMER_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_TIMER_ALLOW_S 2 +/** PMS_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP ANAPERI + * (analog peripherals). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_ANAPERI_ALLOW (BIT(3)) +#define PMS_LP_MM_LP_ANAPERI_ALLOW_M (PMS_LP_MM_LP_ANAPERI_ALLOW_V << PMS_LP_MM_LP_ANAPERI_ALLOW_S) +#define PMS_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_ANAPERI_ALLOW_S 3 +/** PMS_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP PMU (Power + * Management Unit). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_PMU_ALLOW (BIT(4)) +#define PMS_LP_MM_LP_PMU_ALLOW_M (PMS_LP_MM_LP_PMU_ALLOW_V << PMS_LP_MM_LP_PMU_ALLOW_S) +#define PMS_LP_MM_LP_PMU_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_PMU_ALLOW_S 4 +/** PMS_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog + * timer). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_WDT_ALLOW (BIT(5)) +#define PMS_LP_MM_LP_WDT_ALLOW_M (PMS_LP_MM_LP_WDT_ALLOW_V << PMS_LP_MM_LP_WDT_ALLOW_S) +#define PMS_LP_MM_LP_WDT_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_WDT_ALLOW_S 5 +/** PMS_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP Mailbox + * Controller. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_MAILBOX_ALLOW (BIT(6)) +#define PMS_LP_MM_LP_MAILBOX_ALLOW_M (PMS_LP_MM_LP_MAILBOX_ALLOW_V << PMS_LP_MM_LP_MAILBOX_ALLOW_S) +#define PMS_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_MAILBOX_ALLOW_S 6 +/** PMS_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP RTC. + * 0: Not allowed + * 1: Allow + */ +#define PMS_LP_MM_LP_RTC_ALLOW (BIT(7)) +#define PMS_LP_MM_LP_RTC_ALLOW_M (PMS_LP_MM_LP_RTC_ALLOW_V << PMS_LP_MM_LP_RTC_ALLOW_S) +#define PMS_LP_MM_LP_RTC_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_RTC_ALLOW_S 7 +/** PMS_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP PREICLKRST + * (peripheral clock and reset). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_PERICLKRST_ALLOW (BIT(8)) +#define PMS_LP_MM_LP_PERICLKRST_ALLOW_M (PMS_LP_MM_LP_PERICLKRST_ALLOW_V << PMS_LP_MM_LP_PERICLKRST_ALLOW_S) +#define PMS_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_PERICLKRST_ALLOW_S 8 +/** PMS_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP UART. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_UART_ALLOW (BIT(9)) +#define PMS_LP_MM_LP_UART_ALLOW_M (PMS_LP_MM_LP_UART_ALLOW_V << PMS_LP_MM_LP_UART_ALLOW_S) +#define PMS_LP_MM_LP_UART_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_UART_ALLOW_S 9 +/** PMS_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP I2S. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_I2C_ALLOW (BIT(10)) +#define PMS_LP_MM_LP_I2C_ALLOW_M (PMS_LP_MM_LP_I2C_ALLOW_V << PMS_LP_MM_LP_I2C_ALLOW_S) +#define PMS_LP_MM_LP_I2C_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_I2C_ALLOW_S 10 +/** PMS_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP SPI. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_SPI_ALLOW (BIT(11)) +#define PMS_LP_MM_LP_SPI_ALLOW_M (PMS_LP_MM_LP_SPI_ALLOW_V << PMS_LP_MM_LP_SPI_ALLOW_S) +#define PMS_LP_MM_LP_SPI_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_SPI_ALLOW_S 11 +/** PMS_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP I2C master. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_I2CMST_ALLOW (BIT(12)) +#define PMS_LP_MM_LP_I2CMST_ALLOW_M (PMS_LP_MM_LP_I2CMST_ALLOW_V << PMS_LP_MM_LP_I2CMST_ALLOW_S) +#define PMS_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_I2CMST_ALLOW_S 12 +/** PMS_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP I2S. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_I2S_ALLOW (BIT(13)) +#define PMS_LP_MM_LP_I2S_ALLOW_M (PMS_LP_MM_LP_I2S_ALLOW_V << PMS_LP_MM_LP_I2S_ALLOW_S) +#define PMS_LP_MM_LP_I2S_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_I2S_ALLOW_S 13 +/** PMS_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP ADC. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_ADC_ALLOW (BIT(14)) +#define PMS_LP_MM_LP_ADC_ALLOW_M (PMS_LP_MM_LP_ADC_ALLOW_V << PMS_LP_MM_LP_ADC_ALLOW_S) +#define PMS_LP_MM_LP_ADC_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_ADC_ALLOW_S 14 +/** PMS_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP touch sensor. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_TOUCH_ALLOW (BIT(15)) +#define PMS_LP_MM_LP_TOUCH_ALLOW_M (PMS_LP_MM_LP_TOUCH_ALLOW_V << PMS_LP_MM_LP_TOUCH_ALLOW_S) +#define PMS_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_TOUCH_ALLOW_S 15 +/** PMS_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP IO MUX. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_IOMUX_ALLOW (BIT(16)) +#define PMS_LP_MM_LP_IOMUX_ALLOW_M (PMS_LP_MM_LP_IOMUX_ALLOW_V << PMS_LP_MM_LP_IOMUX_ALLOW_S) +#define PMS_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_IOMUX_ALLOW_S 16 +/** PMS_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP INTR + * (interrupt). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_INTR_ALLOW (BIT(17)) +#define PMS_LP_MM_LP_INTR_ALLOW_M (PMS_LP_MM_LP_INTR_ALLOW_V << PMS_LP_MM_LP_INTR_ALLOW_S) +#define PMS_LP_MM_LP_INTR_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_INTR_ALLOW_S 17 +/** PMS_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP eFuse. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_EFUSE_ALLOW (BIT(18)) +#define PMS_LP_MM_LP_EFUSE_ALLOW_M (PMS_LP_MM_LP_EFUSE_ALLOW_V << PMS_LP_MM_LP_EFUSE_ALLOW_S) +#define PMS_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_EFUSE_ALLOW_S 18 +/** PMS_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_PMS_ALLOW (BIT(19)) +#define PMS_LP_MM_LP_PMS_ALLOW_M (PMS_LP_MM_LP_PMS_ALLOW_V << PMS_LP_MM_LP_PMS_ALLOW_S) +#define PMS_LP_MM_LP_PMS_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_PMS_ALLOW_S 19 +/** PMS_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1; + * Configures whether LP CPU in machine mode has permission to access + * HP2LP_PERI_PMS_REG. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_HP2LP_PMS_ALLOW (BIT(20)) +#define PMS_LP_MM_HP2LP_PMS_ALLOW_M (PMS_LP_MM_HP2LP_PMS_ALLOW_V << PMS_LP_MM_HP2LP_PMS_ALLOW_S) +#define PMS_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U +#define PMS_LP_MM_HP2LP_PMS_ALLOW_S 20 +/** PMS_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP temperature + * sensor. + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_TSENS_ALLOW (BIT(21)) +#define PMS_LP_MM_LP_TSENS_ALLOW_M (PMS_LP_MM_LP_TSENS_ALLOW_V << PMS_LP_MM_LP_TSENS_ALLOW_S) +#define PMS_LP_MM_LP_TSENS_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_TSENS_ALLOW_S 21 +/** PMS_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware + * Unique Key). + * 0: Not allowed + * 1: Allowed + */ +#define PMS_LP_MM_LP_HUK_ALLOW (BIT(22)) +#define PMS_LP_MM_LP_HUK_ALLOW_M (PMS_LP_MM_LP_HUK_ALLOW_V << PMS_LP_MM_LP_HUK_ALLOW_S) +#define PMS_LP_MM_LP_HUK_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_HUK_ALLOW_S 22 +/** PMS_LP_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1; + * Configures whether LP CPU in machine mode has permission to access LP SRAM. + * 0: Not allowed + * 1: Allow + */ +#define PMS_LP_MM_LP_SRAM_ALLOW (BIT(23)) +#define PMS_LP_MM_LP_SRAM_ALLOW_M (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S) +#define PMS_LP_MM_LP_SRAM_ALLOW_V 0x00000001U +#define PMS_LP_MM_LP_SRAM_ALLOW_S 23 + +/** PMS_PERI_REGION0_LOW_REG register + * Region0 start address configuration register + */ +#define PMS_PERI_REGION0_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0xc) +/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region0. + */ +#define PMS_PERI_REGION0_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION0_LOW_M (PMS_PERI_REGION0_LOW_V << PMS_PERI_REGION0_LOW_S) +#define PMS_PERI_REGION0_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION0_LOW_S 2 + +/** PMS_PERI_REGION0_HIGH_REG register + * Region0 end address configuration register + */ +#define PMS_PERI_REGION0_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x10) +/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region0. + */ +#define PMS_PERI_REGION0_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION0_HIGH_M (PMS_PERI_REGION0_HIGH_V << PMS_PERI_REGION0_HIGH_S) +#define PMS_PERI_REGION0_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION0_HIGH_S 2 + +/** PMS_PERI_REGION1_LOW_REG register + * Region1 start address configuration register + */ +#define PMS_PERI_REGION1_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x14) +/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0; + * Configures the high 30 bits of the start address of peripheral register's region1. + */ +#define PMS_PERI_REGION1_LOW 0x3FFFFFFFU +#define PMS_PERI_REGION1_LOW_M (PMS_PERI_REGION1_LOW_V << PMS_PERI_REGION1_LOW_S) +#define PMS_PERI_REGION1_LOW_V 0x3FFFFFFFU +#define PMS_PERI_REGION1_LOW_S 2 + +/** PMS_PERI_REGION1_HIGH_REG register + * Region1 end address configuration register + */ +#define PMS_PERI_REGION1_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x18) +/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823; + * Configures the high 30 bits of the end address of peripheral register's region1. + */ +#define PMS_PERI_REGION1_HIGH 0x3FFFFFFFU +#define PMS_PERI_REGION1_HIGH_M (PMS_PERI_REGION1_HIGH_V << PMS_PERI_REGION1_HIGH_S) +#define PMS_PERI_REGION1_HIGH_V 0x3FFFFFFFU +#define PMS_PERI_REGION1_HIGH_S 2 + +/** PMS_PERI_REGION_PMS_REG register + * Permission register of region + */ +#define PMS_PERI_REGION_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x1c) +/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3; + * Configures whether LP core in machine mode has permission to access address region0 + * and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1. + * 0: Not allowed + * 1: Allow + */ +#define PMS_LP_CORE_REGION_PMS 0x00000003U +#define PMS_LP_CORE_REGION_PMS_M (PMS_LP_CORE_REGION_PMS_V << PMS_LP_CORE_REGION_PMS_S) +#define PMS_LP_CORE_REGION_PMS_V 0x00000003U +#define PMS_LP_CORE_REGION_PMS_S 0 +/** PMS_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3; + * Configures whether HP CPU0 in user mode has permission to access address region0 + * and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE0_UM_REGION_PMS 0x00000003U +#define PMS_HP_CORE0_UM_REGION_PMS_M (PMS_HP_CORE0_UM_REGION_PMS_V << PMS_HP_CORE0_UM_REGION_PMS_S) +#define PMS_HP_CORE0_UM_REGION_PMS_V 0x00000003U +#define PMS_HP_CORE0_UM_REGION_PMS_S 2 +/** PMS_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3; + * Configures whether HP CPU0 in machine mode has permission to access address region0 + * and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE0_MM_REGION_PMS 0x00000003U +#define PMS_HP_CORE0_MM_REGION_PMS_M (PMS_HP_CORE0_MM_REGION_PMS_V << PMS_HP_CORE0_MM_REGION_PMS_S) +#define PMS_HP_CORE0_MM_REGION_PMS_V 0x00000003U +#define PMS_HP_CORE0_MM_REGION_PMS_S 4 +/** PMS_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3; + * Configures whether HP CPU1 in user mode has permission to access address region0 + * and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE1_UM_REGION_PMS 0x00000003U +#define PMS_HP_CORE1_UM_REGION_PMS_M (PMS_HP_CORE1_UM_REGION_PMS_V << PMS_HP_CORE1_UM_REGION_PMS_S) +#define PMS_HP_CORE1_UM_REGION_PMS_V 0x00000003U +#define PMS_HP_CORE1_UM_REGION_PMS_S 6 +/** PMS_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3; + * Configures whether HP CPU1 in machine mode has permission to access address region0 + * and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1. + * 0: Not allowed + * 1: Allow + */ +#define PMS_HP_CORE1_MM_REGION_PMS 0x00000003U +#define PMS_HP_CORE1_MM_REGION_PMS_M (PMS_HP_CORE1_MM_REGION_PMS_V << PMS_HP_CORE1_MM_REGION_PMS_S) +#define PMS_HP_CORE1_MM_REGION_PMS_V 0x00000003U +#define PMS_HP_CORE1_MM_REGION_PMS_S 8 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_struct.h new file mode 100644 index 0000000000..691228182d --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_peri_pms_struct.h @@ -0,0 +1,508 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: TEE PMS DATE REG */ +/** Type of pms_date register + * NA + */ +typedef union { + struct { + /** tee_date : R/W; bitpos: [31:0]; default: 2363943; + * NA + */ + uint32_t tee_date:32; + }; + uint32_t val; +} tee_pms_date_reg_t; + + +/** Group: TEE PMS CLK EN REG */ +/** Type of pms_clk_en register + * NA + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_pms_clk_en_reg_t; + + +/** Group: TEE LP MM PMS REG0 REG */ +/** Type of lp_mm_pms_reg0 register + * NA + */ +typedef union { + struct { + /** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_sysreg_allow:1; + /** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_aonclkrst_allow:1; + /** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_timer_allow:1; + /** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_anaperi_allow:1; + /** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_pmu_allow:1; + /** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_wdt_allow:1; + /** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_mailbox_allow:1; + /** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_rtc_allow:1; + /** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_periclkrst_allow:1; + /** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_uart_allow:1; + /** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_i2c_allow:1; + /** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_spi_allow:1; + /** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_i2cmst_allow:1; + /** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_i2s_allow:1; + /** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_adc_allow:1; + /** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_touch_allow:1; + /** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_iomux_allow:1; + /** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_intr_allow:1; + /** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_efuse_allow:1; + /** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_pms_allow:1; + /** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1; + * NA + */ + uint32_t reg_lp_mm_hp2lp_pms_allow:1; + /** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_tsens_allow:1; + /** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_huk_allow:1; + /** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_tcm_ram_allow:1; + /** reg_lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1; + * NA + */ + uint32_t reg_lp_mm_lp_trng_allow:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} tee_lp_mm_pms_reg0_reg_t; + + +/** Group: TEE PERI REGION0 LOW REG */ +/** Type of peri_region0_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region0_low:30; + }; + uint32_t val; +} tee_peri_region0_low_reg_t; + + +/** Group: TEE PERI REGION0 HIGH REG */ +/** Type of peri_region0_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region0_high:30; + }; + uint32_t val; +} tee_peri_region0_high_reg_t; + + +/** Group: TEE PERI REGION1 LOW REG */ +/** Type of peri_region1_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region1_low:30; + }; + uint32_t val; +} tee_peri_region1_low_reg_t; + + +/** Group: TEE PERI REGION1 HIGH REG */ +/** Type of peri_region1_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region1_high:30; + }; + uint32_t val; +} tee_peri_region1_high_reg_t; + + +/** Group: TEE PERI REGION PMS REG */ +/** Type of peri_region_pms register + * NA + */ +typedef union { + struct { + /** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3; + * NA + */ + uint32_t reg_lp_core_region_pms:2; + /** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3; + * NA + */ + uint32_t reg_hp_core0_um_region_pms:2; + /** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3; + * NA + */ + uint32_t reg_hp_core0_mm_region_pms:2; + /** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3; + * NA + */ + uint32_t reg_hp_core1_um_region_pms:2; + /** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3; + * NA + */ + uint32_t reg_hp_core1_mm_region_pms:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} tee_peri_region_pms_reg_t; + + +/** Group: TEE PERI REGION 2 TO 7 PMS REG */ +/** Type of peri_region_2_to_7_pms register + * NA + */ +typedef union { + struct { + /** reg_lp_core_region_2_to_7_pms : R/W; bitpos: [5:0]; default: 63; + * NA + */ + uint32_t reg_lp_core_region_2_to_7_pms:6; + /** reg_hp_core0_um_region_2_to_7_pms : R/W; bitpos: [11:6]; default: 63; + * NA + */ + uint32_t reg_hp_core0_um_region_2_to_7_pms:6; + /** reg_hp_core0_mm_region_2_to_7_pms : R/W; bitpos: [17:12]; default: 63; + * NA + */ + uint32_t reg_hp_core0_mm_region_2_to_7_pms:6; + /** reg_hp_core1_um_region_2_to_7_pms : R/W; bitpos: [23:18]; default: 63; + * NA + */ + uint32_t reg_hp_core1_um_region_2_to_7_pms:6; + /** reg_hp_core1_mm_region_2_to_7_pms : R/W; bitpos: [29:24]; default: 63; + * NA + */ + uint32_t reg_hp_core1_mm_region_2_to_7_pms:6; + uint32_t reserved_30:2; + }; + uint32_t val; +} tee_peri_region_2_to_7_pms_reg_t; + + +/** Group: TEE PERI REGION2 LOW REG */ +/** Type of peri_region2_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region2_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region2_low:30; + }; + uint32_t val; +} tee_peri_region2_low_reg_t; + + +/** Group: TEE PERI REGION2 HIGH REG */ +/** Type of peri_region2_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region2_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region2_high:30; + }; + uint32_t val; +} tee_peri_region2_high_reg_t; + + +/** Group: TEE PERI REGION3 LOW REG */ +/** Type of peri_region3_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region3_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region3_low:30; + }; + uint32_t val; +} tee_peri_region3_low_reg_t; + + +/** Group: TEE PERI REGION3 HIGH REG */ +/** Type of peri_region3_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region3_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region3_high:30; + }; + uint32_t val; +} tee_peri_region3_high_reg_t; + + +/** Group: TEE PERI REGION4 LOW REG */ +/** Type of peri_region4_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region4_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region4_low:30; + }; + uint32_t val; +} tee_peri_region4_low_reg_t; + + +/** Group: TEE PERI REGION4 HIGH REG */ +/** Type of peri_region4_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region4_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region4_high:30; + }; + uint32_t val; +} tee_peri_region4_high_reg_t; + + +/** Group: TEE PERI REGION5 LOW REG */ +/** Type of peri_region5_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region5_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region5_low:30; + }; + uint32_t val; +} tee_peri_region5_low_reg_t; + + +/** Group: TEE PERI REGION5 HIGH REG */ +/** Type of peri_region5_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region5_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region5_high:30; + }; + uint32_t val; +} tee_peri_region5_high_reg_t; + + +/** Group: TEE PERI REGION6 LOW REG */ +/** Type of peri_region6_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region6_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region6_low:30; + }; + uint32_t val; +} tee_peri_region6_low_reg_t; + + +/** Group: TEE PERI REGION6 HIGH REG */ +/** Type of peri_region6_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region6_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region6_high:30; + }; + uint32_t val; +} tee_peri_region6_high_reg_t; + + +/** Group: TEE PERI REGION7 LOW REG */ +/** Type of peri_region7_low register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region7_low : R/W; bitpos: [31:2]; default: 0; + * NA + */ + uint32_t reg_peri_region7_low:30; + }; + uint32_t val; +} tee_peri_region7_low_reg_t; + + +/** Group: TEE PERI REGION7 HIGH REG */ +/** Type of peri_region7_high register + * NA + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** reg_peri_region7_high : R/W; bitpos: [31:2]; default: 1073741823; + * NA + */ + uint32_t reg_peri_region7_high:30; + }; + uint32_t val; +} tee_peri_region7_high_reg_t; + + +typedef struct { + volatile tee_pms_date_reg_t pms_date; + volatile tee_pms_clk_en_reg_t pms_clk_en; + volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0; + volatile tee_peri_region0_low_reg_t peri_region0_low; + volatile tee_peri_region0_high_reg_t peri_region0_high; + volatile tee_peri_region1_low_reg_t peri_region1_low; + volatile tee_peri_region1_high_reg_t peri_region1_high; + volatile tee_peri_region_pms_reg_t peri_region_pms; + volatile tee_peri_region_2_to_7_pms_reg_t peri_region_2_to_7_pms; + volatile tee_peri_region2_low_reg_t peri_region2_low; + volatile tee_peri_region2_high_reg_t peri_region2_high; + volatile tee_peri_region3_low_reg_t peri_region3_low; + volatile tee_peri_region3_high_reg_t peri_region3_high; + volatile tee_peri_region4_low_reg_t peri_region4_low; + volatile tee_peri_region4_high_reg_t peri_region4_high; + volatile tee_peri_region5_low_reg_t peri_region5_low; + volatile tee_peri_region5_high_reg_t peri_region5_high; + volatile tee_peri_region6_low_reg_t peri_region6_low; + volatile tee_peri_region6_high_reg_t peri_region6_high; + volatile tee_peri_region7_low_reg_t peri_region7_low; + volatile tee_peri_region7_high_reg_t peri_region7_high; +} tee_dev_t; + +extern tee_dev_t LP_PERI_PMS; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x54, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_spi_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_spi_reg.h new file mode 100644 index 0000000000..3d6bb0371a --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_spi_reg.h @@ -0,0 +1,1375 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_SPI_CMD_REG register + * Command control register + */ +#define LP_SPI_CMD_REG (DR_REG_LP_BASE + 0x0) +/** LP_REG_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ +#define LP_REG_UPDATE (BIT(23)) +#define LP_REG_UPDATE_M (LP_REG_UPDATE_V << LP_REG_UPDATE_S) +#define LP_REG_UPDATE_V 0x00000001U +#define LP_REG_UPDATE_S 23 +/** LP_REG_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ +#define LP_REG_USR (BIT(24)) +#define LP_REG_USR_M (LP_REG_USR_V << LP_REG_USR_S) +#define LP_REG_USR_V 0x00000001U +#define LP_REG_USR_S 24 + +/** LP_SPI_ADDR_REG register + * Address value register + */ +#define LP_SPI_ADDR_REG (DR_REG_LP_BASE + 0x4) +/** LP_REG_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ +#define LP_REG_USR_ADDR_VALUE 0xFFFFFFFFU +#define LP_REG_USR_ADDR_VALUE_M (LP_REG_USR_ADDR_VALUE_V << LP_REG_USR_ADDR_VALUE_S) +#define LP_REG_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define LP_REG_USR_ADDR_VALUE_S 0 + +/** LP_SPI_CTRL_REG register + * SPI control register + */ +#define LP_SPI_CTRL_REG (DR_REG_LP_BASE + 0x8) +/** LP_REG_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * In the dummy phase the signal level of spi is output by the spi controller. Can be + * configured in CONF state. + */ +#define LP_REG_DUMMY_OUT (BIT(3)) +#define LP_REG_DUMMY_OUT_M (LP_REG_DUMMY_OUT_V << LP_REG_DUMMY_OUT_S) +#define LP_REG_DUMMY_OUT_V 0x00000001U +#define LP_REG_DUMMY_OUT_S 3 +/** LP_REG_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define LP_REG_Q_POL (BIT(18)) +#define LP_REG_Q_POL_M (LP_REG_Q_POL_V << LP_REG_Q_POL_S) +#define LP_REG_Q_POL_V 0x00000001U +#define LP_REG_Q_POL_S 18 +/** LP_REG_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ +#define LP_REG_D_POL (BIT(19)) +#define LP_REG_D_POL_M (LP_REG_D_POL_V << LP_REG_D_POL_S) +#define LP_REG_D_POL_V 0x00000001U +#define LP_REG_D_POL_S 19 +/** LP_REG_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ +#define LP_REG_RD_BIT_ORDER (BIT(25)) +#define LP_REG_RD_BIT_ORDER_M (LP_REG_RD_BIT_ORDER_V << LP_REG_RD_BIT_ORDER_S) +#define LP_REG_RD_BIT_ORDER_V 0x00000001U +#define LP_REG_RD_BIT_ORDER_S 25 +/** LP_REG_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ +#define LP_REG_WR_BIT_ORDER (BIT(26)) +#define LP_REG_WR_BIT_ORDER_M (LP_REG_WR_BIT_ORDER_V << LP_REG_WR_BIT_ORDER_S) +#define LP_REG_WR_BIT_ORDER_V 0x00000001U +#define LP_REG_WR_BIT_ORDER_S 26 + +/** LP_SPI_CLOCK_REG register + * SPI clock control register + */ +#define LP_SPI_CLOCK_REG (DR_REG_LP_BASE + 0xc) +/** LP_REG_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ +#define LP_REG_CLKCNT_L 0x0000003FU +#define LP_REG_CLKCNT_L_M (LP_REG_CLKCNT_L_V << LP_REG_CLKCNT_L_S) +#define LP_REG_CLKCNT_L_V 0x0000003FU +#define LP_REG_CLKCNT_L_S 0 +/** LP_REG_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ +#define LP_REG_CLKCNT_H 0x0000003FU +#define LP_REG_CLKCNT_H_M (LP_REG_CLKCNT_H_V << LP_REG_CLKCNT_H_S) +#define LP_REG_CLKCNT_H_V 0x0000003FU +#define LP_REG_CLKCNT_H_S 6 +/** LP_REG_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ +#define LP_REG_CLKCNT_N 0x0000003FU +#define LP_REG_CLKCNT_N_M (LP_REG_CLKCNT_N_V << LP_REG_CLKCNT_N_S) +#define LP_REG_CLKCNT_N_V 0x0000003FU +#define LP_REG_CLKCNT_N_S 12 +/** LP_REG_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ +#define LP_REG_CLKDIV_PRE 0x0000000FU +#define LP_REG_CLKDIV_PRE_M (LP_REG_CLKDIV_PRE_V << LP_REG_CLKDIV_PRE_S) +#define LP_REG_CLKDIV_PRE_V 0x0000000FU +#define LP_REG_CLKDIV_PRE_S 18 +/** LP_REG_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +#define LP_REG_CLK_EQU_SYSCLK (BIT(31)) +#define LP_REG_CLK_EQU_SYSCLK_M (LP_REG_CLK_EQU_SYSCLK_V << LP_REG_CLK_EQU_SYSCLK_S) +#define LP_REG_CLK_EQU_SYSCLK_V 0x00000001U +#define LP_REG_CLK_EQU_SYSCLK_S 31 + +/** LP_SPI_USER_REG register + * SPI USER control register + */ +#define LP_SPI_USER_REG (DR_REG_LP_BASE + 0x10) +/** LP_REG_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define LP_REG_DOUTDIN (BIT(0)) +#define LP_REG_DOUTDIN_M (LP_REG_DOUTDIN_V << LP_REG_DOUTDIN_S) +#define LP_REG_DOUTDIN_V 0x00000001U +#define LP_REG_DOUTDIN_S 0 +/** LP_REG_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ +#define LP_REG_TSCK_I_EDGE (BIT(5)) +#define LP_REG_TSCK_I_EDGE_M (LP_REG_TSCK_I_EDGE_V << LP_REG_TSCK_I_EDGE_S) +#define LP_REG_TSCK_I_EDGE_V 0x00000001U +#define LP_REG_TSCK_I_EDGE_S 5 +/** LP_REG_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define LP_REG_CS_HOLD (BIT(6)) +#define LP_REG_CS_HOLD_M (LP_REG_CS_HOLD_V << LP_REG_CS_HOLD_S) +#define LP_REG_CS_HOLD_V 0x00000001U +#define LP_REG_CS_HOLD_S 6 +/** LP_REG_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ +#define LP_REG_CS_SETUP (BIT(7)) +#define LP_REG_CS_SETUP_M (LP_REG_CS_SETUP_V << LP_REG_CS_SETUP_S) +#define LP_REG_CS_SETUP_V 0x00000001U +#define LP_REG_CS_SETUP_S 7 +/** LP_REG_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ +#define LP_REG_RSCK_I_EDGE (BIT(8)) +#define LP_REG_RSCK_I_EDGE_M (LP_REG_RSCK_I_EDGE_V << LP_REG_RSCK_I_EDGE_S) +#define LP_REG_RSCK_I_EDGE_V 0x00000001U +#define LP_REG_RSCK_I_EDGE_S 8 +/** LP_REG_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ +#define LP_REG_CK_OUT_EDGE (BIT(9)) +#define LP_REG_CK_OUT_EDGE_M (LP_REG_CK_OUT_EDGE_V << LP_REG_CK_OUT_EDGE_S) +#define LP_REG_CK_OUT_EDGE_V 0x00000001U +#define LP_REG_CK_OUT_EDGE_S 9 +/** LP_REG_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ +#define LP_REG_SIO (BIT(17)) +#define LP_REG_SIO_M (LP_REG_SIO_V << LP_REG_SIO_S) +#define LP_REG_SIO_V 0x00000001U +#define LP_REG_SIO_S 17 +/** LP_REG_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ +#define LP_REG_USR_MISO_HIGHPART (BIT(24)) +#define LP_REG_USR_MISO_HIGHPART_M (LP_REG_USR_MISO_HIGHPART_V << LP_REG_USR_MISO_HIGHPART_S) +#define LP_REG_USR_MISO_HIGHPART_V 0x00000001U +#define LP_REG_USR_MISO_HIGHPART_S 24 +/** LP_REG_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ +#define LP_REG_USR_MOSI_HIGHPART (BIT(25)) +#define LP_REG_USR_MOSI_HIGHPART_M (LP_REG_USR_MOSI_HIGHPART_V << LP_REG_USR_MOSI_HIGHPART_S) +#define LP_REG_USR_MOSI_HIGHPART_V 0x00000001U +#define LP_REG_USR_MOSI_HIGHPART_S 25 +/** LP_REG_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ +#define LP_REG_USR_DUMMY_IDLE (BIT(26)) +#define LP_REG_USR_DUMMY_IDLE_M (LP_REG_USR_DUMMY_IDLE_V << LP_REG_USR_DUMMY_IDLE_S) +#define LP_REG_USR_DUMMY_IDLE_V 0x00000001U +#define LP_REG_USR_DUMMY_IDLE_S 26 +/** LP_REG_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ +#define LP_REG_USR_MOSI (BIT(27)) +#define LP_REG_USR_MOSI_M (LP_REG_USR_MOSI_V << LP_REG_USR_MOSI_S) +#define LP_REG_USR_MOSI_V 0x00000001U +#define LP_REG_USR_MOSI_S 27 +/** LP_REG_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ +#define LP_REG_USR_MISO (BIT(28)) +#define LP_REG_USR_MISO_M (LP_REG_USR_MISO_V << LP_REG_USR_MISO_S) +#define LP_REG_USR_MISO_V 0x00000001U +#define LP_REG_USR_MISO_S 28 +/** LP_REG_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ +#define LP_REG_USR_DUMMY (BIT(29)) +#define LP_REG_USR_DUMMY_M (LP_REG_USR_DUMMY_V << LP_REG_USR_DUMMY_S) +#define LP_REG_USR_DUMMY_V 0x00000001U +#define LP_REG_USR_DUMMY_S 29 +/** LP_REG_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ +#define LP_REG_USR_ADDR (BIT(30)) +#define LP_REG_USR_ADDR_M (LP_REG_USR_ADDR_V << LP_REG_USR_ADDR_S) +#define LP_REG_USR_ADDR_V 0x00000001U +#define LP_REG_USR_ADDR_S 30 +/** LP_REG_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +#define LP_REG_USR_COMMAND (BIT(31)) +#define LP_REG_USR_COMMAND_M (LP_REG_USR_COMMAND_V << LP_REG_USR_COMMAND_S) +#define LP_REG_USR_COMMAND_V 0x00000001U +#define LP_REG_USR_COMMAND_S 31 + +/** LP_SPI_USER1_REG register + * SPI USER control register 1 + */ +#define LP_SPI_USER1_REG (DR_REG_LP_BASE + 0x14) +/** LP_REG_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ +#define LP_REG_USR_DUMMY_CYCLELEN 0x000000FFU +#define LP_REG_USR_DUMMY_CYCLELEN_M (LP_REG_USR_DUMMY_CYCLELEN_V << LP_REG_USR_DUMMY_CYCLELEN_S) +#define LP_REG_USR_DUMMY_CYCLELEN_V 0x000000FFU +#define LP_REG_USR_DUMMY_CYCLELEN_S 0 +/** LP_REG_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ +#define LP_REG_MST_WFULL_ERR_END_EN (BIT(16)) +#define LP_REG_MST_WFULL_ERR_END_EN_M (LP_REG_MST_WFULL_ERR_END_EN_V << LP_REG_MST_WFULL_ERR_END_EN_S) +#define LP_REG_MST_WFULL_ERR_END_EN_V 0x00000001U +#define LP_REG_MST_WFULL_ERR_END_EN_S 16 +/** LP_REG_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ +#define LP_REG_CS_SETUP_TIME 0x0000001FU +#define LP_REG_CS_SETUP_TIME_M (LP_REG_CS_SETUP_TIME_V << LP_REG_CS_SETUP_TIME_S) +#define LP_REG_CS_SETUP_TIME_V 0x0000001FU +#define LP_REG_CS_SETUP_TIME_S 17 +/** LP_REG_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ +#define LP_REG_CS_HOLD_TIME 0x0000001FU +#define LP_REG_CS_HOLD_TIME_M (LP_REG_CS_HOLD_TIME_V << LP_REG_CS_HOLD_TIME_S) +#define LP_REG_CS_HOLD_TIME_V 0x0000001FU +#define LP_REG_CS_HOLD_TIME_S 22 +/** LP_REG_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define LP_REG_USR_ADDR_BITLEN 0x0000001FU +#define LP_REG_USR_ADDR_BITLEN_M (LP_REG_USR_ADDR_BITLEN_V << LP_REG_USR_ADDR_BITLEN_S) +#define LP_REG_USR_ADDR_BITLEN_V 0x0000001FU +#define LP_REG_USR_ADDR_BITLEN_S 27 + +/** LP_SPI_USER2_REG register + * SPI USER control register 2 + */ +#define LP_SPI_USER2_REG (DR_REG_LP_BASE + 0x18) +/** LP_REG_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ +#define LP_REG_USR_COMMAND_VALUE 0x0000FFFFU +#define LP_REG_USR_COMMAND_VALUE_M (LP_REG_USR_COMMAND_VALUE_V << LP_REG_USR_COMMAND_VALUE_S) +#define LP_REG_USR_COMMAND_VALUE_V 0x0000FFFFU +#define LP_REG_USR_COMMAND_VALUE_S 0 +/** LP_REG_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ +#define LP_REG_MST_REMPTY_ERR_END_EN (BIT(27)) +#define LP_REG_MST_REMPTY_ERR_END_EN_M (LP_REG_MST_REMPTY_ERR_END_EN_V << LP_REG_MST_REMPTY_ERR_END_EN_S) +#define LP_REG_MST_REMPTY_ERR_END_EN_V 0x00000001U +#define LP_REG_MST_REMPTY_ERR_END_EN_S 27 +/** LP_REG_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +#define LP_REG_USR_COMMAND_BITLEN 0x0000000FU +#define LP_REG_USR_COMMAND_BITLEN_M (LP_REG_USR_COMMAND_BITLEN_V << LP_REG_USR_COMMAND_BITLEN_S) +#define LP_REG_USR_COMMAND_BITLEN_V 0x0000000FU +#define LP_REG_USR_COMMAND_BITLEN_S 28 + +/** LP_SPI_MS_DLEN_REG register + * SPI data bit length control register + */ +#define LP_SPI_MS_DLEN_REG (DR_REG_LP_BASE + 0x1c) +/** LP_REG_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ +#define LP_REG_MS_DATA_BITLEN 0x0003FFFFU +#define LP_REG_MS_DATA_BITLEN_M (LP_REG_MS_DATA_BITLEN_V << LP_REG_MS_DATA_BITLEN_S) +#define LP_REG_MS_DATA_BITLEN_V 0x0003FFFFU +#define LP_REG_MS_DATA_BITLEN_S 0 + +/** LP_SPI_MISC_REG register + * SPI misc register + */ +#define LP_SPI_MISC_REG (DR_REG_LP_BASE + 0x20) +/** LP_REG_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ +#define LP_REG_CS0_DIS (BIT(0)) +#define LP_REG_CS0_DIS_M (LP_REG_CS0_DIS_V << LP_REG_CS0_DIS_S) +#define LP_REG_CS0_DIS_V 0x00000001U +#define LP_REG_CS0_DIS_S 0 +/** LP_REG_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ +#define LP_REG_CK_DIS (BIT(6)) +#define LP_REG_CK_DIS_M (LP_REG_CK_DIS_V << LP_REG_CK_DIS_S) +#define LP_REG_CK_DIS_V 0x00000001U +#define LP_REG_CK_DIS_S 6 +/** LP_REG_MASTER_CS_POL : R/W; bitpos: [9:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ +#define LP_REG_MASTER_CS_POL 0x00000007U +#define LP_REG_MASTER_CS_POL_M (LP_REG_MASTER_CS_POL_V << LP_REG_MASTER_CS_POL_S) +#define LP_REG_MASTER_CS_POL_V 0x00000007U +#define LP_REG_MASTER_CS_POL_S 7 +/** LP_REG_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ +#define LP_REG_SLAVE_CS_POL (BIT(23)) +#define LP_REG_SLAVE_CS_POL_M (LP_REG_SLAVE_CS_POL_V << LP_REG_SLAVE_CS_POL_S) +#define LP_REG_SLAVE_CS_POL_V 0x00000001U +#define LP_REG_SLAVE_CS_POL_S 23 +/** LP_REG_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ +#define LP_REG_CK_IDLE_EDGE (BIT(29)) +#define LP_REG_CK_IDLE_EDGE_M (LP_REG_CK_IDLE_EDGE_V << LP_REG_CK_IDLE_EDGE_S) +#define LP_REG_CK_IDLE_EDGE_V 0x00000001U +#define LP_REG_CK_IDLE_EDGE_S 29 +/** LP_REG_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ +#define LP_REG_CS_KEEP_ACTIVE (BIT(30)) +#define LP_REG_CS_KEEP_ACTIVE_M (LP_REG_CS_KEEP_ACTIVE_V << LP_REG_CS_KEEP_ACTIVE_S) +#define LP_REG_CS_KEEP_ACTIVE_V 0x00000001U +#define LP_REG_CS_KEEP_ACTIVE_S 30 + +/** LP_SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ +#define LP_SPI_DIN_MODE_REG (DR_REG_LP_BASE + 0x24) +/** LP_REG_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define LP_REG_DIN0_MODE 0x00000003U +#define LP_REG_DIN0_MODE_M (LP_REG_DIN0_MODE_V << LP_REG_DIN0_MODE_S) +#define LP_REG_DIN0_MODE_V 0x00000003U +#define LP_REG_DIN0_MODE_S 0 +/** LP_REG_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define LP_REG_DIN1_MODE 0x00000003U +#define LP_REG_DIN1_MODE_M (LP_REG_DIN1_MODE_V << LP_REG_DIN1_MODE_S) +#define LP_REG_DIN1_MODE_V 0x00000003U +#define LP_REG_DIN1_MODE_S 2 +/** LP_REG_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define LP_REG_DIN2_MODE 0x00000003U +#define LP_REG_DIN2_MODE_M (LP_REG_DIN2_MODE_V << LP_REG_DIN2_MODE_S) +#define LP_REG_DIN2_MODE_V 0x00000003U +#define LP_REG_DIN2_MODE_S 4 +/** LP_REG_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ +#define LP_REG_DIN3_MODE 0x00000003U +#define LP_REG_DIN3_MODE_M (LP_REG_DIN3_MODE_V << LP_REG_DIN3_MODE_S) +#define LP_REG_DIN3_MODE_V 0x00000003U +#define LP_REG_DIN3_MODE_S 6 +/** LP_REG_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ +#define LP_REG_TIMING_HCLK_ACTIVE (BIT(16)) +#define LP_REG_TIMING_HCLK_ACTIVE_M (LP_REG_TIMING_HCLK_ACTIVE_V << LP_REG_TIMING_HCLK_ACTIVE_S) +#define LP_REG_TIMING_HCLK_ACTIVE_V 0x00000001U +#define LP_REG_TIMING_HCLK_ACTIVE_S 16 + +/** LP_SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ +#define LP_SPI_DIN_NUM_REG (DR_REG_LP_BASE + 0x28) +/** LP_REG_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define LP_REG_DIN0_NUM 0x00000003U +#define LP_REG_DIN0_NUM_M (LP_REG_DIN0_NUM_V << LP_REG_DIN0_NUM_S) +#define LP_REG_DIN0_NUM_V 0x00000003U +#define LP_REG_DIN0_NUM_S 0 +/** LP_REG_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define LP_REG_DIN1_NUM 0x00000003U +#define LP_REG_DIN1_NUM_M (LP_REG_DIN1_NUM_V << LP_REG_DIN1_NUM_S) +#define LP_REG_DIN1_NUM_V 0x00000003U +#define LP_REG_DIN1_NUM_S 2 +/** LP_REG_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define LP_REG_DIN2_NUM 0x00000003U +#define LP_REG_DIN2_NUM_M (LP_REG_DIN2_NUM_V << LP_REG_DIN2_NUM_S) +#define LP_REG_DIN2_NUM_V 0x00000003U +#define LP_REG_DIN2_NUM_S 4 +/** LP_REG_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ +#define LP_REG_DIN3_NUM 0x00000003U +#define LP_REG_DIN3_NUM_M (LP_REG_DIN3_NUM_V << LP_REG_DIN3_NUM_S) +#define LP_REG_DIN3_NUM_V 0x00000003U +#define LP_REG_DIN3_NUM_S 6 + +/** LP_SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ +#define LP_SPI_DOUT_MODE_REG (DR_REG_LP_BASE + 0x2c) +/** LP_REG_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define LP_REG_DOUT0_MODE (BIT(0)) +#define LP_REG_DOUT0_MODE_M (LP_REG_DOUT0_MODE_V << LP_REG_DOUT0_MODE_S) +#define LP_REG_DOUT0_MODE_V 0x00000001U +#define LP_REG_DOUT0_MODE_S 0 +/** LP_REG_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define LP_REG_DOUT1_MODE (BIT(1)) +#define LP_REG_DOUT1_MODE_M (LP_REG_DOUT1_MODE_V << LP_REG_DOUT1_MODE_S) +#define LP_REG_DOUT1_MODE_V 0x00000001U +#define LP_REG_DOUT1_MODE_S 1 +/** LP_REG_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define LP_REG_DOUT2_MODE (BIT(2)) +#define LP_REG_DOUT2_MODE_M (LP_REG_DOUT2_MODE_V << LP_REG_DOUT2_MODE_S) +#define LP_REG_DOUT2_MODE_V 0x00000001U +#define LP_REG_DOUT2_MODE_S 2 +/** LP_REG_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ +#define LP_REG_DOUT3_MODE (BIT(3)) +#define LP_REG_DOUT3_MODE_M (LP_REG_DOUT3_MODE_V << LP_REG_DOUT3_MODE_S) +#define LP_REG_DOUT3_MODE_V 0x00000001U +#define LP_REG_DOUT3_MODE_S 3 + +/** LP_SPI_DMA_CONF_REG register + * SPI DMA control register + */ +#define LP_SPI_DMA_CONF_REG (DR_REG_LP_BASE + 0x30) +/** LP_REG_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ +#define LP_REG_RX_AFIFO_RST (BIT(29)) +#define LP_REG_RX_AFIFO_RST_M (LP_REG_RX_AFIFO_RST_V << LP_REG_RX_AFIFO_RST_S) +#define LP_REG_RX_AFIFO_RST_V 0x00000001U +#define LP_REG_RX_AFIFO_RST_S 29 +/** LP_REG_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ +#define LP_REG_BUF_AFIFO_RST (BIT(30)) +#define LP_REG_BUF_AFIFO_RST_M (LP_REG_BUF_AFIFO_RST_V << LP_REG_BUF_AFIFO_RST_S) +#define LP_REG_BUF_AFIFO_RST_V 0x00000001U +#define LP_REG_BUF_AFIFO_RST_S 30 + +/** LP_SPI_DMA_INT_ENA_REG register + * SPI DMA interrupt enable register + */ +#define LP_SPI_DMA_INT_ENA_REG (DR_REG_LP_BASE + 0x34) +/** LP_REG_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define LP_REG_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define LP_REG_SLV_RD_BUF_DONE_INT_ENA_M (LP_REG_SLV_RD_BUF_DONE_INT_ENA_V << LP_REG_SLV_RD_BUF_DONE_INT_ENA_S) +#define LP_REG_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001U +#define LP_REG_SLV_RD_BUF_DONE_INT_ENA_S 10 +/** LP_REG_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define LP_REG_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define LP_REG_SLV_WR_BUF_DONE_INT_ENA_M (LP_REG_SLV_WR_BUF_DONE_INT_ENA_V << LP_REG_SLV_WR_BUF_DONE_INT_ENA_S) +#define LP_REG_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001U +#define LP_REG_SLV_WR_BUF_DONE_INT_ENA_S 11 +/** LP_REG_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ +#define LP_REG_TRANS_DONE_INT_ENA (BIT(12)) +#define LP_REG_TRANS_DONE_INT_ENA_M (LP_REG_TRANS_DONE_INT_ENA_V << LP_REG_TRANS_DONE_INT_ENA_S) +#define LP_REG_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_REG_TRANS_DONE_INT_ENA_S 12 +/** LP_REG_SPI_WAKEUP_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_WAKEUP_INT interrupt + */ +#define LP_REG_SPI_WAKEUP_INT_ENA (BIT(14)) +#define LP_REG_SPI_WAKEUP_INT_ENA_M (LP_REG_SPI_WAKEUP_INT_ENA_V << LP_REG_SPI_WAKEUP_INT_ENA_S) +#define LP_REG_SPI_WAKEUP_INT_ENA_V 0x00000001U +#define LP_REG_SPI_WAKEUP_INT_ENA_S 14 +/** LP_REG_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_M (LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_V << LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001U +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/** LP_REG_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define LP_REG_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define LP_REG_SLV_CMD_ERR_INT_ENA_M (LP_REG_SLV_CMD_ERR_INT_ENA_V << LP_REG_SLV_CMD_ERR_INT_ENA_S) +#define LP_REG_SLV_CMD_ERR_INT_ENA_V 0x00000001U +#define LP_REG_SLV_CMD_ERR_INT_ENA_S 16 +/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001U +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001U +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 +/** LP_REG_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ +#define LP_REG_APP2_INT_ENA (BIT(19)) +#define LP_REG_APP2_INT_ENA_M (LP_REG_APP2_INT_ENA_V << LP_REG_APP2_INT_ENA_S) +#define LP_REG_APP2_INT_ENA_V 0x00000001U +#define LP_REG_APP2_INT_ENA_S 19 +/** LP_REG_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ +#define LP_REG_APP1_INT_ENA (BIT(20)) +#define LP_REG_APP1_INT_ENA_M (LP_REG_APP1_INT_ENA_V << LP_REG_APP1_INT_ENA_S) +#define LP_REG_APP1_INT_ENA_V 0x00000001U +#define LP_REG_APP1_INT_ENA_S 20 + +/** LP_SPI_DMA_INT_CLR_REG register + * SPI DMA interrupt clear register + */ +#define LP_SPI_DMA_INT_CLR_REG (DR_REG_LP_BASE + 0x38) +/** LP_REG_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define LP_REG_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define LP_REG_SLV_RD_BUF_DONE_INT_CLR_M (LP_REG_SLV_RD_BUF_DONE_INT_CLR_V << LP_REG_SLV_RD_BUF_DONE_INT_CLR_S) +#define LP_REG_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001U +#define LP_REG_SLV_RD_BUF_DONE_INT_CLR_S 10 +/** LP_REG_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define LP_REG_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define LP_REG_SLV_WR_BUF_DONE_INT_CLR_M (LP_REG_SLV_WR_BUF_DONE_INT_CLR_V << LP_REG_SLV_WR_BUF_DONE_INT_CLR_S) +#define LP_REG_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001U +#define LP_REG_SLV_WR_BUF_DONE_INT_CLR_S 11 +/** LP_REG_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ +#define LP_REG_TRANS_DONE_INT_CLR (BIT(12)) +#define LP_REG_TRANS_DONE_INT_CLR_M (LP_REG_TRANS_DONE_INT_CLR_V << LP_REG_TRANS_DONE_INT_CLR_S) +#define LP_REG_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_REG_TRANS_DONE_INT_CLR_S 12 +/** LP_REG_SPI_WAKEUP_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_WAKEUP_INT interrupt + */ +#define LP_REG_SPI_WAKEUP_INT_CLR (BIT(14)) +#define LP_REG_SPI_WAKEUP_INT_CLR_M (LP_REG_SPI_WAKEUP_INT_CLR_V << LP_REG_SPI_WAKEUP_INT_CLR_S) +#define LP_REG_SPI_WAKEUP_INT_CLR_V 0x00000001U +#define LP_REG_SPI_WAKEUP_INT_CLR_S 14 +/** LP_REG_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_M (LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_V << LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001U +#define LP_REG_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/** LP_REG_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define LP_REG_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define LP_REG_SLV_CMD_ERR_INT_CLR_M (LP_REG_SLV_CMD_ERR_INT_CLR_V << LP_REG_SLV_CMD_ERR_INT_CLR_S) +#define LP_REG_SLV_CMD_ERR_INT_CLR_V 0x00000001U +#define LP_REG_SLV_CMD_ERR_INT_CLR_S 16 +/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001U +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001U +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 +/** LP_REG_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ +#define LP_REG_APP2_INT_CLR (BIT(19)) +#define LP_REG_APP2_INT_CLR_M (LP_REG_APP2_INT_CLR_V << LP_REG_APP2_INT_CLR_S) +#define LP_REG_APP2_INT_CLR_V 0x00000001U +#define LP_REG_APP2_INT_CLR_S 19 +/** LP_REG_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ +#define LP_REG_APP1_INT_CLR (BIT(20)) +#define LP_REG_APP1_INT_CLR_M (LP_REG_APP1_INT_CLR_V << LP_REG_APP1_INT_CLR_S) +#define LP_REG_APP1_INT_CLR_V 0x00000001U +#define LP_REG_APP1_INT_CLR_S 20 + +/** LP_SPI_DMA_INT_RAW_REG register + * SPI DMA interrupt raw register + */ +#define LP_SPI_DMA_INT_RAW_REG (DR_REG_LP_BASE + 0x3c) +/** LP_REG_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ +#define LP_REG_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define LP_REG_SLV_RD_BUF_DONE_INT_RAW_M (LP_REG_SLV_RD_BUF_DONE_INT_RAW_V << LP_REG_SLV_RD_BUF_DONE_INT_RAW_S) +#define LP_REG_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001U +#define LP_REG_SLV_RD_BUF_DONE_INT_RAW_S 10 +/** LP_REG_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ +#define LP_REG_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define LP_REG_SLV_WR_BUF_DONE_INT_RAW_M (LP_REG_SLV_WR_BUF_DONE_INT_RAW_V << LP_REG_SLV_WR_BUF_DONE_INT_RAW_S) +#define LP_REG_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001U +#define LP_REG_SLV_WR_BUF_DONE_INT_RAW_S 11 +/** LP_REG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ +#define LP_REG_TRANS_DONE_INT_RAW (BIT(12)) +#define LP_REG_TRANS_DONE_INT_RAW_M (LP_REG_TRANS_DONE_INT_RAW_V << LP_REG_TRANS_DONE_INT_RAW_S) +#define LP_REG_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_REG_TRANS_DONE_INT_RAW_S 12 +/** LP_REG_SPI_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SPI_WAKEUP_INT interrupt. 1: There is a wake up signal when + * low power mode. 0: Others. + */ +#define LP_REG_SPI_WAKEUP_INT_RAW (BIT(14)) +#define LP_REG_SPI_WAKEUP_INT_RAW_M (LP_REG_SPI_WAKEUP_INT_RAW_V << LP_REG_SPI_WAKEUP_INT_RAW_S) +#define LP_REG_SPI_WAKEUP_INT_RAW_V 0x00000001U +#define LP_REG_SPI_WAKEUP_INT_RAW_S 14 +/** LP_REG_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ +#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_M (LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_V << LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001U +#define LP_REG_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/** LP_REG_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ +#define LP_REG_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define LP_REG_SLV_CMD_ERR_INT_RAW_M (LP_REG_SLV_CMD_ERR_INT_RAW_V << LP_REG_SLV_CMD_ERR_INT_RAW_S) +#define LP_REG_SLV_CMD_ERR_INT_RAW_V 0x00000001U +#define LP_REG_SLV_CMD_ERR_INT_RAW_S 16 +/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001U +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001U +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 +/** LP_REG_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application. + */ +#define LP_REG_APP2_INT_RAW (BIT(19)) +#define LP_REG_APP2_INT_RAW_M (LP_REG_APP2_INT_RAW_V << LP_REG_APP2_INT_RAW_S) +#define LP_REG_APP2_INT_RAW_V 0x00000001U +#define LP_REG_APP2_INT_RAW_S 19 +/** LP_REG_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application. + */ +#define LP_REG_APP1_INT_RAW (BIT(20)) +#define LP_REG_APP1_INT_RAW_M (LP_REG_APP1_INT_RAW_V << LP_REG_APP1_INT_RAW_S) +#define LP_REG_APP1_INT_RAW_V 0x00000001U +#define LP_REG_APP1_INT_RAW_S 20 + +/** LP_SPI_DMA_INT_ST_REG register + * SPI DMA interrupt status register + */ +#define LP_SPI_DMA_INT_ST_REG (DR_REG_LP_BASE + 0x40) +/** LP_REG_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define LP_REG_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define LP_REG_SLV_RD_BUF_DONE_INT_ST_M (LP_REG_SLV_RD_BUF_DONE_INT_ST_V << LP_REG_SLV_RD_BUF_DONE_INT_ST_S) +#define LP_REG_SLV_RD_BUF_DONE_INT_ST_V 0x00000001U +#define LP_REG_SLV_RD_BUF_DONE_INT_ST_S 10 +/** LP_REG_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define LP_REG_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define LP_REG_SLV_WR_BUF_DONE_INT_ST_M (LP_REG_SLV_WR_BUF_DONE_INT_ST_V << LP_REG_SLV_WR_BUF_DONE_INT_ST_S) +#define LP_REG_SLV_WR_BUF_DONE_INT_ST_V 0x00000001U +#define LP_REG_SLV_WR_BUF_DONE_INT_ST_S 11 +/** LP_REG_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ +#define LP_REG_TRANS_DONE_INT_ST (BIT(12)) +#define LP_REG_TRANS_DONE_INT_ST_M (LP_REG_TRANS_DONE_INT_ST_V << LP_REG_TRANS_DONE_INT_ST_S) +#define LP_REG_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_REG_TRANS_DONE_INT_ST_S 12 +/** LP_REG_SPI_WAKEUP_INT_ST : RO; bitpos: [14]; default: 0; + * reserved + */ +#define LP_REG_SPI_WAKEUP_INT_ST (BIT(14)) +#define LP_REG_SPI_WAKEUP_INT_ST_M (LP_REG_SPI_WAKEUP_INT_ST_V << LP_REG_SPI_WAKEUP_INT_ST_S) +#define LP_REG_SPI_WAKEUP_INT_ST_V 0x00000001U +#define LP_REG_SPI_WAKEUP_INT_ST_S 14 +/** LP_REG_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST_M (LP_REG_SLV_BUF_ADDR_ERR_INT_ST_V << LP_REG_SLV_BUF_ADDR_ERR_INT_ST_S) +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001U +#define LP_REG_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/** LP_REG_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define LP_REG_SLV_CMD_ERR_INT_ST (BIT(16)) +#define LP_REG_SLV_CMD_ERR_INT_ST_M (LP_REG_SLV_CMD_ERR_INT_ST_V << LP_REG_SLV_CMD_ERR_INT_ST_S) +#define LP_REG_SLV_CMD_ERR_INT_ST_V 0x00000001U +#define LP_REG_SLV_CMD_ERR_INT_ST_S 16 +/** LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001U +#define LP_REG_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/** LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001U +#define LP_REG_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 +/** LP_REG_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ +#define LP_REG_APP2_INT_ST (BIT(19)) +#define LP_REG_APP2_INT_ST_M (LP_REG_APP2_INT_ST_V << LP_REG_APP2_INT_ST_S) +#define LP_REG_APP2_INT_ST_V 0x00000001U +#define LP_REG_APP2_INT_ST_S 19 +/** LP_REG_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ +#define LP_REG_APP1_INT_ST (BIT(20)) +#define LP_REG_APP1_INT_ST_M (LP_REG_APP1_INT_ST_V << LP_REG_APP1_INT_ST_S) +#define LP_REG_APP1_INT_ST_V 0x00000001U +#define LP_REG_APP1_INT_ST_S 20 + +/** LP_SPI_SLEEP_CONF0_REG register + * NA + */ +#define LP_SPI_SLEEP_CONF0_REG (DR_REG_LP_BASE + 0x44) +/** LP_REG_SLV_WK_CHAR0 : R/W; bitpos: [7:0]; default: 10; + * NA + */ +#define LP_REG_SLV_WK_CHAR0 0x000000FFU +#define LP_REG_SLV_WK_CHAR0_M (LP_REG_SLV_WK_CHAR0_V << LP_REG_SLV_WK_CHAR0_S) +#define LP_REG_SLV_WK_CHAR0_V 0x000000FFU +#define LP_REG_SLV_WK_CHAR0_S 0 +/** LP_REG_SLV_WK_CHAR_NUM : R/W; bitpos: [10:8]; default: 0; + * NA + */ +#define LP_REG_SLV_WK_CHAR_NUM 0x00000007U +#define LP_REG_SLV_WK_CHAR_NUM_M (LP_REG_SLV_WK_CHAR_NUM_V << LP_REG_SLV_WK_CHAR_NUM_S) +#define LP_REG_SLV_WK_CHAR_NUM_V 0x00000007U +#define LP_REG_SLV_WK_CHAR_NUM_S 8 +/** LP_REG_SLV_WK_CHAR_MASK : R/W; bitpos: [15:11]; default: 0; + * NA + */ +#define LP_REG_SLV_WK_CHAR_MASK 0x0000001FU +#define LP_REG_SLV_WK_CHAR_MASK_M (LP_REG_SLV_WK_CHAR_MASK_V << LP_REG_SLV_WK_CHAR_MASK_S) +#define LP_REG_SLV_WK_CHAR_MASK_V 0x0000001FU +#define LP_REG_SLV_WK_CHAR_MASK_S 11 +/** LP_REG_SLV_WK_MODE_SEL : R/W; bitpos: [16]; default: 0; + * NA + */ +#define LP_REG_SLV_WK_MODE_SEL (BIT(16)) +#define LP_REG_SLV_WK_MODE_SEL_M (LP_REG_SLV_WK_MODE_SEL_V << LP_REG_SLV_WK_MODE_SEL_S) +#define LP_REG_SLV_WK_MODE_SEL_V 0x00000001U +#define LP_REG_SLV_WK_MODE_SEL_S 16 +/** LP_REG_SLEEP_EN : R/W; bitpos: [17]; default: 0; + * NA + */ +#define LP_REG_SLEEP_EN (BIT(17)) +#define LP_REG_SLEEP_EN_M (LP_REG_SLEEP_EN_V << LP_REG_SLEEP_EN_S) +#define LP_REG_SLEEP_EN_V 0x00000001U +#define LP_REG_SLEEP_EN_S 17 +/** LP_REG_SLEEP_DIS_RXFIFO_WR_EN : R/W; bitpos: [18]; default: 0; + * NA + */ +#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN (BIT(18)) +#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN_M (LP_REG_SLEEP_DIS_RXFIFO_WR_EN_V << LP_REG_SLEEP_DIS_RXFIFO_WR_EN_S) +#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN_V 0x00000001U +#define LP_REG_SLEEP_DIS_RXFIFO_WR_EN_S 18 +/** LP_REG_SLEEP_WK_DATA_SEL : R/W; bitpos: [19]; default: 0; + * NA + */ +#define LP_REG_SLEEP_WK_DATA_SEL (BIT(19)) +#define LP_REG_SLEEP_WK_DATA_SEL_M (LP_REG_SLEEP_WK_DATA_SEL_V << LP_REG_SLEEP_WK_DATA_SEL_S) +#define LP_REG_SLEEP_WK_DATA_SEL_V 0x00000001U +#define LP_REG_SLEEP_WK_DATA_SEL_S 19 + +/** LP_SPI_SLEEP_CONF1_REG register + * NA + */ +#define LP_SPI_SLEEP_CONF1_REG (DR_REG_LP_BASE + 0x48) +/** LP_REG_SLV_WK_CHAR1 : R/W; bitpos: [7:0]; default: 11; + * NA + */ +#define LP_REG_SLV_WK_CHAR1 0x000000FFU +#define LP_REG_SLV_WK_CHAR1_M (LP_REG_SLV_WK_CHAR1_V << LP_REG_SLV_WK_CHAR1_S) +#define LP_REG_SLV_WK_CHAR1_V 0x000000FFU +#define LP_REG_SLV_WK_CHAR1_S 0 +/** LP_REG_SLV_WK_CHAR2 : R/W; bitpos: [15:8]; default: 12; + * NA + */ +#define LP_REG_SLV_WK_CHAR2 0x000000FFU +#define LP_REG_SLV_WK_CHAR2_M (LP_REG_SLV_WK_CHAR2_V << LP_REG_SLV_WK_CHAR2_S) +#define LP_REG_SLV_WK_CHAR2_V 0x000000FFU +#define LP_REG_SLV_WK_CHAR2_S 8 +/** LP_REG_SLV_WK_CHAR3 : R/W; bitpos: [23:16]; default: 13; + * NA + */ +#define LP_REG_SLV_WK_CHAR3 0x000000FFU +#define LP_REG_SLV_WK_CHAR3_M (LP_REG_SLV_WK_CHAR3_V << LP_REG_SLV_WK_CHAR3_S) +#define LP_REG_SLV_WK_CHAR3_V 0x000000FFU +#define LP_REG_SLV_WK_CHAR3_S 16 +/** LP_REG_SLV_WK_CHAR4 : R/W; bitpos: [31:24]; default: 14; + * NA + */ +#define LP_REG_SLV_WK_CHAR4 0x000000FFU +#define LP_REG_SLV_WK_CHAR4_M (LP_REG_SLV_WK_CHAR4_V << LP_REG_SLV_WK_CHAR4_S) +#define LP_REG_SLV_WK_CHAR4_V 0x000000FFU +#define LP_REG_SLV_WK_CHAR4_S 24 + +/** LP_SPI_DMA_INT_SET_REG register + * SPI interrupt software set register + */ +#define LP_SPI_DMA_INT_SET_REG (DR_REG_LP_BASE + 0x4c) +/** LP_SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ +#define LP_SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10)) +#define LP_SPI_SLV_RD_BUF_DONE_INT_SET_M (LP_SPI_SLV_RD_BUF_DONE_INT_SET_V << LP_SPI_SLV_RD_BUF_DONE_INT_SET_S) +#define LP_SPI_SLV_RD_BUF_DONE_INT_SET_V 0x00000001U +#define LP_SPI_SLV_RD_BUF_DONE_INT_SET_S 10 +/** LP_SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ +#define LP_SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11)) +#define LP_SPI_SLV_WR_BUF_DONE_INT_SET_M (LP_SPI_SLV_WR_BUF_DONE_INT_SET_V << LP_SPI_SLV_WR_BUF_DONE_INT_SET_S) +#define LP_SPI_SLV_WR_BUF_DONE_INT_SET_V 0x00000001U +#define LP_SPI_SLV_WR_BUF_DONE_INT_SET_S 11 +/** LP_SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ +#define LP_SPI_TRANS_DONE_INT_SET (BIT(12)) +#define LP_SPI_TRANS_DONE_INT_SET_M (LP_SPI_TRANS_DONE_INT_SET_V << LP_SPI_TRANS_DONE_INT_SET_S) +#define LP_SPI_TRANS_DONE_INT_SET_V 0x00000001U +#define LP_SPI_TRANS_DONE_INT_SET_S 12 +/** LP_SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ +#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15)) +#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_M (LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_V << LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_S) +#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x00000001U +#define LP_SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15 +/** LP_SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ +#define LP_SPI_SLV_CMD_ERR_INT_SET (BIT(16)) +#define LP_SPI_SLV_CMD_ERR_INT_SET_M (LP_SPI_SLV_CMD_ERR_INT_SET_V << LP_SPI_SLV_CMD_ERR_INT_SET_S) +#define LP_SPI_SLV_CMD_ERR_INT_SET_V 0x00000001U +#define LP_SPI_SLV_CMD_ERR_INT_SET_S 16 +/** LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ +#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17)) +#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S) +#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x00000001U +#define LP_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17 +/** LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ +#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18)) +#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S) +#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x00000001U +#define LP_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18 +/** LP_SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ +#define LP_SPI_APP2_INT_SET (BIT(19)) +#define LP_SPI_APP2_INT_SET_M (LP_SPI_APP2_INT_SET_V << LP_SPI_APP2_INT_SET_S) +#define LP_SPI_APP2_INT_SET_V 0x00000001U +#define LP_SPI_APP2_INT_SET_S 19 +/** LP_SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ +#define LP_SPI_APP1_INT_SET (BIT(20)) +#define LP_SPI_APP1_INT_SET_M (LP_SPI_APP1_INT_SET_V << LP_SPI_APP1_INT_SET_S) +#define LP_SPI_APP1_INT_SET_V 0x00000001U +#define LP_SPI_APP1_INT_SET_S 20 + +/** LP_SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ +#define LP_SPI_W0_REG (DR_REG_LP_BASE + 0x98) +/** LP_REG_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF0 0xFFFFFFFFU +#define LP_REG_BUF0_M (LP_REG_BUF0_V << LP_REG_BUF0_S) +#define LP_REG_BUF0_V 0xFFFFFFFFU +#define LP_REG_BUF0_S 0 + +/** LP_SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ +#define LP_SPI_W1_REG (DR_REG_LP_BASE + 0x9c) +/** LP_REG_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF1 0xFFFFFFFFU +#define LP_REG_BUF1_M (LP_REG_BUF1_V << LP_REG_BUF1_S) +#define LP_REG_BUF1_V 0xFFFFFFFFU +#define LP_REG_BUF1_S 0 + +/** LP_SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ +#define LP_SPI_W2_REG (DR_REG_LP_BASE + 0xa0) +/** LP_REG_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF2 0xFFFFFFFFU +#define LP_REG_BUF2_M (LP_REG_BUF2_V << LP_REG_BUF2_S) +#define LP_REG_BUF2_V 0xFFFFFFFFU +#define LP_REG_BUF2_S 0 + +/** LP_SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ +#define LP_SPI_W3_REG (DR_REG_LP_BASE + 0xa4) +/** LP_REG_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF3 0xFFFFFFFFU +#define LP_REG_BUF3_M (LP_REG_BUF3_V << LP_REG_BUF3_S) +#define LP_REG_BUF3_V 0xFFFFFFFFU +#define LP_REG_BUF3_S 0 + +/** LP_SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ +#define LP_SPI_W4_REG (DR_REG_LP_BASE + 0xa8) +/** LP_REG_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF4 0xFFFFFFFFU +#define LP_REG_BUF4_M (LP_REG_BUF4_V << LP_REG_BUF4_S) +#define LP_REG_BUF4_V 0xFFFFFFFFU +#define LP_REG_BUF4_S 0 + +/** LP_SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ +#define LP_SPI_W5_REG (DR_REG_LP_BASE + 0xac) +/** LP_REG_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF5 0xFFFFFFFFU +#define LP_REG_BUF5_M (LP_REG_BUF5_V << LP_REG_BUF5_S) +#define LP_REG_BUF5_V 0xFFFFFFFFU +#define LP_REG_BUF5_S 0 + +/** LP_SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ +#define LP_SPI_W6_REG (DR_REG_LP_BASE + 0xb0) +/** LP_REG_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF6 0xFFFFFFFFU +#define LP_REG_BUF6_M (LP_REG_BUF6_V << LP_REG_BUF6_S) +#define LP_REG_BUF6_V 0xFFFFFFFFU +#define LP_REG_BUF6_S 0 + +/** LP_SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ +#define LP_SPI_W7_REG (DR_REG_LP_BASE + 0xb4) +/** LP_REG_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF7 0xFFFFFFFFU +#define LP_REG_BUF7_M (LP_REG_BUF7_V << LP_REG_BUF7_S) +#define LP_REG_BUF7_V 0xFFFFFFFFU +#define LP_REG_BUF7_S 0 + +/** LP_SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ +#define LP_SPI_W8_REG (DR_REG_LP_BASE + 0xb8) +/** LP_REG_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF8 0xFFFFFFFFU +#define LP_REG_BUF8_M (LP_REG_BUF8_V << LP_REG_BUF8_S) +#define LP_REG_BUF8_V 0xFFFFFFFFU +#define LP_REG_BUF8_S 0 + +/** LP_SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ +#define LP_SPI_W9_REG (DR_REG_LP_BASE + 0xbc) +/** LP_REG_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF9 0xFFFFFFFFU +#define LP_REG_BUF9_M (LP_REG_BUF9_V << LP_REG_BUF9_S) +#define LP_REG_BUF9_V 0xFFFFFFFFU +#define LP_REG_BUF9_S 0 + +/** LP_SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ +#define LP_SPI_W10_REG (DR_REG_LP_BASE + 0xc0) +/** LP_REG_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF10 0xFFFFFFFFU +#define LP_REG_BUF10_M (LP_REG_BUF10_V << LP_REG_BUF10_S) +#define LP_REG_BUF10_V 0xFFFFFFFFU +#define LP_REG_BUF10_S 0 + +/** LP_SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ +#define LP_SPI_W11_REG (DR_REG_LP_BASE + 0xc4) +/** LP_REG_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF11 0xFFFFFFFFU +#define LP_REG_BUF11_M (LP_REG_BUF11_V << LP_REG_BUF11_S) +#define LP_REG_BUF11_V 0xFFFFFFFFU +#define LP_REG_BUF11_S 0 + +/** LP_SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ +#define LP_SPI_W12_REG (DR_REG_LP_BASE + 0xc8) +/** LP_REG_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF12 0xFFFFFFFFU +#define LP_REG_BUF12_M (LP_REG_BUF12_V << LP_REG_BUF12_S) +#define LP_REG_BUF12_V 0xFFFFFFFFU +#define LP_REG_BUF12_S 0 + +/** LP_SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ +#define LP_SPI_W13_REG (DR_REG_LP_BASE + 0xcc) +/** LP_REG_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF13 0xFFFFFFFFU +#define LP_REG_BUF13_M (LP_REG_BUF13_V << LP_REG_BUF13_S) +#define LP_REG_BUF13_V 0xFFFFFFFFU +#define LP_REG_BUF13_S 0 + +/** LP_SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ +#define LP_SPI_W14_REG (DR_REG_LP_BASE + 0xd0) +/** LP_REG_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF14 0xFFFFFFFFU +#define LP_REG_BUF14_M (LP_REG_BUF14_V << LP_REG_BUF14_S) +#define LP_REG_BUF14_V 0xFFFFFFFFU +#define LP_REG_BUF14_S 0 + +/** LP_SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ +#define LP_SPI_W15_REG (DR_REG_LP_BASE + 0xd4) +/** LP_REG_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define LP_REG_BUF15 0xFFFFFFFFU +#define LP_REG_BUF15_M (LP_REG_BUF15_V << LP_REG_BUF15_S) +#define LP_REG_BUF15_V 0xFFFFFFFFU +#define LP_REG_BUF15_S 0 + +/** LP_SPI_SLAVE_REG register + * SPI slave control register + */ +#define LP_SPI_SLAVE_REG (DR_REG_LP_BASE + 0xe0) +/** LP_REG_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ +#define LP_REG_CLK_MODE 0x00000003U +#define LP_REG_CLK_MODE_M (LP_REG_CLK_MODE_V << LP_REG_CLK_MODE_S) +#define LP_REG_CLK_MODE_V 0x00000003U +#define LP_REG_CLK_MODE_S 0 +/** LP_REG_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ +#define LP_REG_CLK_MODE_13 (BIT(2)) +#define LP_REG_CLK_MODE_13_M (LP_REG_CLK_MODE_13_V << LP_REG_CLK_MODE_13_S) +#define LP_REG_CLK_MODE_13_V 0x00000001U +#define LP_REG_CLK_MODE_13_S 2 +/** LP_REG_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ +#define LP_REG_RSCK_DATA_OUT (BIT(3)) +#define LP_REG_RSCK_DATA_OUT_M (LP_REG_RSCK_DATA_OUT_V << LP_REG_RSCK_DATA_OUT_S) +#define LP_REG_RSCK_DATA_OUT_V 0x00000001U +#define LP_REG_RSCK_DATA_OUT_S 3 +/** LP_REG_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ +#define LP_REG_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define LP_REG_SLV_RDBUF_BITLEN_EN_M (LP_REG_SLV_RDBUF_BITLEN_EN_V << LP_REG_SLV_RDBUF_BITLEN_EN_S) +#define LP_REG_SLV_RDBUF_BITLEN_EN_V 0x00000001U +#define LP_REG_SLV_RDBUF_BITLEN_EN_S 10 +/** LP_REG_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ +#define LP_REG_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define LP_REG_SLV_WRBUF_BITLEN_EN_M (LP_REG_SLV_WRBUF_BITLEN_EN_V << LP_REG_SLV_WRBUF_BITLEN_EN_S) +#define LP_REG_SLV_WRBUF_BITLEN_EN_V 0x00000001U +#define LP_REG_SLV_WRBUF_BITLEN_EN_S 11 +/** LP_REG_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ +#define LP_REG_SLAVE_MODE (BIT(26)) +#define LP_REG_SLAVE_MODE_M (LP_REG_SLAVE_MODE_V << LP_REG_SLAVE_MODE_S) +#define LP_REG_SLAVE_MODE_V 0x00000001U +#define LP_REG_SLAVE_MODE_S 26 +/** LP_REG_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +#define LP_REG_SOFT_RESET (BIT(27)) +#define LP_REG_SOFT_RESET_M (LP_REG_SOFT_RESET_V << LP_REG_SOFT_RESET_S) +#define LP_REG_SOFT_RESET_V 0x00000001U +#define LP_REG_SOFT_RESET_S 27 + +/** LP_SPI_SLAVE1_REG register + * SPI slave control register 1 + */ +#define LP_SPI_SLAVE1_REG (DR_REG_LP_BASE + 0xe4) +/** LP_REG_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ +#define LP_REG_SLV_DATA_BITLEN 0x0003FFFFU +#define LP_REG_SLV_DATA_BITLEN_M (LP_REG_SLV_DATA_BITLEN_V << LP_REG_SLV_DATA_BITLEN_S) +#define LP_REG_SLV_DATA_BITLEN_V 0x0003FFFFU +#define LP_REG_SLV_DATA_BITLEN_S 0 +/** LP_REG_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ +#define LP_REG_SLV_LAST_COMMAND 0x000000FFU +#define LP_REG_SLV_LAST_COMMAND_M (LP_REG_SLV_LAST_COMMAND_V << LP_REG_SLV_LAST_COMMAND_S) +#define LP_REG_SLV_LAST_COMMAND_V 0x000000FFU +#define LP_REG_SLV_LAST_COMMAND_S 18 +/** LP_REG_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ +#define LP_REG_SLV_LAST_ADDR 0x0000003FU +#define LP_REG_SLV_LAST_ADDR_M (LP_REG_SLV_LAST_ADDR_V << LP_REG_SLV_LAST_ADDR_S) +#define LP_REG_SLV_LAST_ADDR_V 0x0000003FU +#define LP_REG_SLV_LAST_ADDR_S 26 + +/** LP_SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ +#define LP_SPI_CLK_GATE_REG (DR_REG_LP_BASE + 0xe8) +/** LP_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ +#define LP_REG_CLK_EN (BIT(0)) +#define LP_REG_CLK_EN_M (LP_REG_CLK_EN_V << LP_REG_CLK_EN_S) +#define LP_REG_CLK_EN_V 0x00000001U +#define LP_REG_CLK_EN_S 0 +/** LP_REG_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ +#define LP_REG_MST_CLK_ACTIVE (BIT(1)) +#define LP_REG_MST_CLK_ACTIVE_M (LP_REG_MST_CLK_ACTIVE_V << LP_REG_MST_CLK_ACTIVE_S) +#define LP_REG_MST_CLK_ACTIVE_V 0x00000001U +#define LP_REG_MST_CLK_ACTIVE_S 1 +/** LP_REG_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ +#define LP_REG_MST_CLK_SEL (BIT(2)) +#define LP_REG_MST_CLK_SEL_M (LP_REG_MST_CLK_SEL_V << LP_REG_MST_CLK_SEL_S) +#define LP_REG_MST_CLK_SEL_V 0x00000001U +#define LP_REG_MST_CLK_SEL_S 2 + +/** LP_SPI_DATE_REG register + * Version control + */ +#define LP_SPI_DATE_REG (DR_REG_LP_BASE + 0xf0) +/** LP_REG_DATE : R/W; bitpos: [27:0]; default: 33591360; + * SPI register version. + */ +#define LP_REG_DATE 0x0FFFFFFFU +#define LP_REG_DATE_M (LP_REG_DATE_V << LP_REG_DATE_S) +#define LP_REG_DATE_V 0x0FFFFFFFU +#define LP_REG_DATE_S 0 + +/** LP_RND_ECO_CS_REG register + * NA + */ +#define LP_RND_ECO_CS_REG (DR_REG_LP_BASE + 0xf4) +/** LP_REG_RND_ECO_EN : R/W; bitpos: [0]; default: 0; + * NA + */ +#define LP_REG_RND_ECO_EN (BIT(0)) +#define LP_REG_RND_ECO_EN_M (LP_REG_RND_ECO_EN_V << LP_REG_RND_ECO_EN_S) +#define LP_REG_RND_ECO_EN_V 0x00000001U +#define LP_REG_RND_ECO_EN_S 0 +/** LP_RND_ECO_RESULT : RO; bitpos: [1]; default: 0; + * NA + */ +#define LP_RND_ECO_RESULT (BIT(1)) +#define LP_RND_ECO_RESULT_M (LP_RND_ECO_RESULT_V << LP_RND_ECO_RESULT_S) +#define LP_RND_ECO_RESULT_V 0x00000001U +#define LP_RND_ECO_RESULT_S 1 + +/** LP_RND_ECO_LOW_REG register + * NA + */ +#define LP_RND_ECO_LOW_REG (DR_REG_LP_BASE + 0xf8) +/** LP_REG_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * NA + */ +#define LP_REG_RND_ECO_LOW 0xFFFFFFFFU +#define LP_REG_RND_ECO_LOW_M (LP_REG_RND_ECO_LOW_V << LP_REG_RND_ECO_LOW_S) +#define LP_REG_RND_ECO_LOW_V 0xFFFFFFFFU +#define LP_REG_RND_ECO_LOW_S 0 + +/** LP_RND_ECO_HIGH_REG register + * NA + */ +#define LP_RND_ECO_HIGH_REG (DR_REG_LP_BASE + 0xfc) +/** LP_REG_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 65535; + * NA + */ +#define LP_REG_RND_ECO_HIGH 0xFFFFFFFFU +#define LP_REG_RND_ECO_HIGH_M (LP_REG_RND_ECO_HIGH_V << LP_REG_RND_ECO_HIGH_S) +#define LP_REG_RND_ECO_HIGH_V 0xFFFFFFFFU +#define LP_REG_RND_ECO_HIGH_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_spi_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_spi_struct.h new file mode 100644 index 0000000000..0735efd6be --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_spi_struct.h @@ -0,0 +1,1276 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: LP SPI CMD REG */ +/** Type of spi_cmd register + * Command control register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** reg_update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t reg_update:1; + /** reg_usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t reg_usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} lp_spi_cmd_reg_t; + + +/** Group: LP SPI ADDR REG */ +/** Type of spi_addr register + * Address value register + */ +typedef union { + struct { + /** reg_usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t reg_usr_addr_value:32; + }; + uint32_t val; +} lp_spi_addr_reg_t; + + +/** Group: LP SPI CTRL REG */ +/** Type of spi_ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** reg_dummy_out : R/W; bitpos: [3]; default: 0; + * In the dummy phase the signal level of spi is output by the spi controller. Can be + * configured in CONF state. + */ + uint32_t reg_dummy_out:1; + uint32_t reserved_4:14; + /** reg_q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t reg_q_pol:1; + /** reg_d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t reg_d_pol:1; + uint32_t reserved_20:5; + /** reg_rd_bit_order : R/W; bitpos: [25]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t reg_rd_bit_order:1; + /** reg_wr_bit_order : R/W; bitpos: [26]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t reg_wr_bit_order:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} lp_spi_ctrl_reg_t; + + +/** Group: LP SPI CLOCK REG */ +/** Type of spi_clock register + * SPI clock control register + */ +typedef union { + struct { + /** reg_clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t reg_clkcnt_l:6; + /** reg_clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t reg_clkcnt_h:6; + /** reg_clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t reg_clkcnt_n:6; + /** reg_clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t reg_clkdiv_pre:4; + uint32_t reserved_22:9; + /** reg_clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t reg_clk_equ_sysclk:1; + }; + uint32_t val; +} lp_spi_clock_reg_t; + + +/** Group: LP SPI USER REG */ +/** Type of spi_user register + * SPI USER control register + */ +typedef union { + struct { + /** reg_doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t reg_doutdin:1; + uint32_t reserved_1:4; + /** reg_tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t reg_tsck_i_edge:1; + /** reg_cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t reg_cs_hold:1; + /** reg_cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t reg_cs_setup:1; + /** reg_rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t reg_rsck_i_edge:1; + /** reg_ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t reg_ck_out_edge:1; + uint32_t reserved_10:7; + /** reg_sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t reg_sio:1; + uint32_t reserved_18:6; + /** reg_usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t reg_usr_miso_highpart:1; + /** reg_usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t reg_usr_mosi_highpart:1; + /** reg_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t reg_usr_dummy_idle:1; + /** reg_usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t reg_usr_mosi:1; + /** reg_usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t reg_usr_miso:1; + /** reg_usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t reg_usr_dummy:1; + /** reg_usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t reg_usr_addr:1; + /** reg_usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t reg_usr_command:1; + }; + uint32_t val; +} lp_spi_user_reg_t; + + +/** Group: LP SPI USER1 REG */ +/** Type of spi_user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** reg_usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t reg_usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** reg_mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t reg_mst_wfull_err_end_en:1; + /** reg_cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t reg_cs_setup_time:5; + /** reg_cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t reg_cs_hold_time:5; + /** reg_usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t reg_usr_addr_bitlen:5; + }; + uint32_t val; +} lp_spi_user1_reg_t; + + +/** Group: LP SPI USER2 REG */ +/** Type of spi_user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** reg_usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t reg_usr_command_value:16; + uint32_t reserved_16:11; + /** reg_mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t reg_mst_rempty_err_end_en:1; + /** reg_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t reg_usr_command_bitlen:4; + }; + uint32_t val; +} lp_spi_user2_reg_t; + + +/** Group: LP SPI MS DLEN REG */ +/** Type of spi_ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** reg_ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t reg_ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} lp_spi_ms_dlen_reg_t; + + +/** Group: LP SPI MISC REG */ +/** Type of spi_misc register + * SPI misc register + */ +typedef union { + struct { + /** reg_cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t reg_cs0_dis:1; + uint32_t reserved_1:5; + /** reg_ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t reg_ck_dis:1; + /** reg_master_cs_pol : R/W; bitpos: [9:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t reg_master_cs_pol:3; + uint32_t reserved_10:13; + /** reg_slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t reg_slave_cs_pol:1; + uint32_t reserved_24:5; + /** reg_ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t reg_ck_idle_edge:1; + /** reg_cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t reg_cs_keep_active:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_spi_misc_reg_t; + + +/** Group: LP SPI DIN MODE REG */ +/** Type of spi_din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** reg_din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t reg_din0_mode:2; + /** reg_din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t reg_din1_mode:2; + /** reg_din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t reg_din2_mode:2; + /** reg_din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t reg_din3_mode:2; + uint32_t reserved_8:8; + /** reg_timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t reg_timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_spi_din_mode_reg_t; + + +/** Group: LP SPI DIN NUM REG */ +/** Type of spi_din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** reg_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t reg_din0_num:2; + /** reg_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t reg_din1_num:2; + /** reg_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t reg_din2_num:2; + /** reg_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t reg_din3_num:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_spi_din_num_reg_t; + + +/** Group: LP SPI DOUT MODE REG */ +/** Type of spi_dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** reg_dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t reg_dout0_mode:1; + /** reg_dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t reg_dout1_mode:1; + /** reg_dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t reg_dout2_mode:1; + /** reg_dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t reg_dout3_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_spi_dout_mode_reg_t; + + +/** Group: LP SPI DMA CONF REG */ +/** Type of spi_dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** reg_rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t reg_rx_afifo_rst:1; + /** reg_buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t reg_buf_afifo_rst:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_spi_dma_conf_reg_t; + + +/** Group: LP SPI DMA INT ENA REG */ +/** Type of spi_dma_int_ena register + * SPI DMA interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** reg_slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t reg_slv_rd_buf_done_int_ena:1; + /** reg_slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t reg_slv_wr_buf_done_int_ena:1; + /** reg_trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t reg_trans_done_int_ena:1; + uint32_t reserved_13:1; + /** reg_spi_wakeup_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_WAKEUP_INT interrupt + */ + uint32_t reg_spi_wakeup_int_ena:1; + /** reg_slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t reg_slv_buf_addr_err_int_ena:1; + /** reg_slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t reg_slv_cmd_err_int_ena:1; + /** reg_mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t reg_mst_rx_afifo_wfull_err_int_ena:1; + /** reg_mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t reg_mst_tx_afifo_rempty_err_int_ena:1; + /** reg_app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t reg_app2_int_ena:1; + /** reg_app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t reg_app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_spi_dma_int_ena_reg_t; + + +/** Group: LP SPI DMA INT CLR REG */ +/** Type of spi_dma_int_clr register + * SPI DMA interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** reg_slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t reg_slv_rd_buf_done_int_clr:1; + /** reg_slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t reg_slv_wr_buf_done_int_clr:1; + /** reg_trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t reg_trans_done_int_clr:1; + uint32_t reserved_13:1; + /** reg_spi_wakeup_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_WAKEUP_INT interrupt + */ + uint32_t reg_spi_wakeup_int_clr:1; + /** reg_slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t reg_slv_buf_addr_err_int_clr:1; + /** reg_slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t reg_slv_cmd_err_int_clr:1; + /** reg_mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t reg_mst_rx_afifo_wfull_err_int_clr:1; + /** reg_mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t reg_mst_tx_afifo_rempty_err_int_clr:1; + /** reg_app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t reg_app2_int_clr:1; + /** reg_app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t reg_app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_spi_dma_int_clr_reg_t; + + +/** Group: LP SPI DMA INT RAW REG */ +/** Type of spi_dma_int_raw register + * SPI DMA interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** reg_slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t reg_slv_rd_buf_done_int_raw:1; + /** reg_slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t reg_slv_wr_buf_done_int_raw:1; + /** reg_trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t reg_trans_done_int_raw:1; + uint32_t reserved_13:1; + /** reg_spi_wakeup_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SPI_WAKEUP_INT interrupt. 1: There is a wake up signal when + * low power mode. 0: Others. + */ + uint32_t reg_spi_wakeup_int_raw:1; + /** reg_slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t reg_slv_buf_addr_err_int_raw:1; + /** reg_slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t reg_slv_cmd_err_int_raw:1; + /** reg_mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t reg_mst_rx_afifo_wfull_err_int_raw:1; + /** reg_mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t reg_mst_tx_afifo_rempty_err_int_raw:1; + /** reg_app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application. + */ + uint32_t reg_app2_int_raw:1; + /** reg_app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application. + */ + uint32_t reg_app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_spi_dma_int_raw_reg_t; + + +/** Group: LP SPI DMA INT ST REG */ +/** Type of spi_dma_int_st register + * SPI DMA interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** reg_slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t reg_slv_rd_buf_done_int_st:1; + /** reg_slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t reg_slv_wr_buf_done_int_st:1; + /** reg_trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t reg_trans_done_int_st:1; + uint32_t reserved_13:1; + /** reg_spi_wakeup_int_st : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t reg_spi_wakeup_int_st:1; + /** reg_slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t reg_slv_buf_addr_err_int_st:1; + /** reg_slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t reg_slv_cmd_err_int_st:1; + /** reg_mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t reg_mst_rx_afifo_wfull_err_int_st:1; + /** reg_mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t reg_mst_tx_afifo_rempty_err_int_st:1; + /** reg_app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t reg_app2_int_st:1; + /** reg_app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t reg_app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_spi_dma_int_st_reg_t; + + +/** Group: Interrupt registers */ +/** Type of spi_dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** spi_slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t spi_slv_rd_buf_done_int_set:1; + /** spi_slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t spi_slv_wr_buf_done_int_set:1; + /** spi_trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t spi_trans_done_int_set:1; + uint32_t reserved_13:2; + /** spi_slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t spi_slv_buf_addr_err_int_set:1; + /** spi_slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t spi_slv_cmd_err_int_set:1; + /** spi_mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t spi_mst_rx_afifo_wfull_err_int_set:1; + /** spi_mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t spi_mst_tx_afifo_rempty_err_int_set:1; + /** spi_app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t spi_app2_int_set:1; + /** spi_app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t spi_app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} lp_spi_dma_int_set_reg_t; + + +/** Group: LP SPI SLEEP CONF0 REG */ +/** Type of spi_sleep_conf0 register + * NA + */ +typedef union { + struct { + /** reg_slv_wk_char0 : R/W; bitpos: [7:0]; default: 10; + * NA + */ + uint32_t reg_slv_wk_char0:8; + /** reg_slv_wk_char_num : R/W; bitpos: [10:8]; default: 0; + * NA + */ + uint32_t reg_slv_wk_char_num:3; + /** reg_slv_wk_char_mask : R/W; bitpos: [15:11]; default: 0; + * NA + */ + uint32_t reg_slv_wk_char_mask:5; + /** reg_slv_wk_mode_sel : R/W; bitpos: [16]; default: 0; + * NA + */ + uint32_t reg_slv_wk_mode_sel:1; + /** reg_sleep_en : R/W; bitpos: [17]; default: 0; + * NA + */ + uint32_t reg_sleep_en:1; + /** reg_sleep_dis_rxfifo_wr_en : R/W; bitpos: [18]; default: 0; + * NA + */ + uint32_t reg_sleep_dis_rxfifo_wr_en:1; + /** reg_sleep_wk_data_sel : R/W; bitpos: [19]; default: 0; + * NA + */ + uint32_t reg_sleep_wk_data_sel:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_spi_sleep_conf0_reg_t; + + +/** Group: LP SPI SLEEP CONF1 REG */ +/** Type of spi_sleep_conf1 register + * NA + */ +typedef union { + struct { + /** reg_slv_wk_char1 : R/W; bitpos: [7:0]; default: 11; + * NA + */ + uint32_t reg_slv_wk_char1:8; + /** reg_slv_wk_char2 : R/W; bitpos: [15:8]; default: 12; + * NA + */ + uint32_t reg_slv_wk_char2:8; + /** reg_slv_wk_char3 : R/W; bitpos: [23:16]; default: 13; + * NA + */ + uint32_t reg_slv_wk_char3:8; + /** reg_slv_wk_char4 : R/W; bitpos: [31:24]; default: 14; + * NA + */ + uint32_t reg_slv_wk_char4:8; + }; + uint32_t val; +} lp_spi_sleep_conf1_reg_t; + + +/** Group: LP SPI W0 REG */ +/** Type of spi_w0 register + * SPI CPU-controlled buffer0 + */ +typedef union { + struct { + /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf0:32; + }; + uint32_t val; +} lp_spi_w0_reg_t; + + +/** Group: LP SPI W1 REG */ +/** Type of spi_w1 register + * SPI CPU-controlled buffer1 + */ +typedef union { + struct { + /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf1:32; + }; + uint32_t val; +} lp_spi_w1_reg_t; + + +/** Group: LP SPI W2 REG */ +/** Type of spi_w2 register + * SPI CPU-controlled buffer2 + */ +typedef union { + struct { + /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf2:32; + }; + uint32_t val; +} lp_spi_w2_reg_t; + + +/** Group: LP SPI W3 REG */ +/** Type of spi_w3 register + * SPI CPU-controlled buffer3 + */ +typedef union { + struct { + /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf3:32; + }; + uint32_t val; +} lp_spi_w3_reg_t; + + +/** Group: LP SPI W4 REG */ +/** Type of spi_w4 register + * SPI CPU-controlled buffer4 + */ +typedef union { + struct { + /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf4:32; + }; + uint32_t val; +} lp_spi_w4_reg_t; + + +/** Group: LP SPI W5 REG */ +/** Type of spi_w5 register + * SPI CPU-controlled buffer5 + */ +typedef union { + struct { + /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf5:32; + }; + uint32_t val; +} lp_spi_w5_reg_t; + + +/** Group: LP SPI W6 REG */ +/** Type of spi_w6 register + * SPI CPU-controlled buffer6 + */ +typedef union { + struct { + /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf6:32; + }; + uint32_t val; +} lp_spi_w6_reg_t; + + +/** Group: LP SPI W7 REG */ +/** Type of spi_w7 register + * SPI CPU-controlled buffer7 + */ +typedef union { + struct { + /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf7:32; + }; + uint32_t val; +} lp_spi_w7_reg_t; + + +/** Group: LP SPI W8 REG */ +/** Type of spi_w8 register + * SPI CPU-controlled buffer8 + */ +typedef union { + struct { + /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf8:32; + }; + uint32_t val; +} lp_spi_w8_reg_t; + + +/** Group: LP SPI W9 REG */ +/** Type of spi_w9 register + * SPI CPU-controlled buffer9 + */ +typedef union { + struct { + /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf9:32; + }; + uint32_t val; +} lp_spi_w9_reg_t; + + +/** Group: LP SPI W10 REG */ +/** Type of spi_w10 register + * SPI CPU-controlled buffer10 + */ +typedef union { + struct { + /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf10:32; + }; + uint32_t val; +} lp_spi_w10_reg_t; + + +/** Group: LP SPI W11 REG */ +/** Type of spi_w11 register + * SPI CPU-controlled buffer11 + */ +typedef union { + struct { + /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf11:32; + }; + uint32_t val; +} lp_spi_w11_reg_t; + + +/** Group: LP SPI W12 REG */ +/** Type of spi_w12 register + * SPI CPU-controlled buffer12 + */ +typedef union { + struct { + /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf12:32; + }; + uint32_t val; +} lp_spi_w12_reg_t; + + +/** Group: LP SPI W13 REG */ +/** Type of spi_w13 register + * SPI CPU-controlled buffer13 + */ +typedef union { + struct { + /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf13:32; + }; + uint32_t val; +} lp_spi_w13_reg_t; + + +/** Group: LP SPI W14 REG */ +/** Type of spi_w14 register + * SPI CPU-controlled buffer14 + */ +typedef union { + struct { + /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf14:32; + }; + uint32_t val; +} lp_spi_w14_reg_t; + + +/** Group: LP SPI W15 REG */ +/** Type of spi_w15 register + * SPI CPU-controlled buffer15 + */ +typedef union { + struct { + /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t reg_buf15:32; + }; + uint32_t val; +} lp_spi_w15_reg_t; + + +/** Group: LP SPI SLAVE REG */ +/** Type of spi_slave register + * SPI slave control register + */ +typedef union { + struct { + /** reg_clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t reg_clk_mode:2; + /** reg_clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t reg_clk_mode_13:1; + /** reg_rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t reg_rsck_data_out:1; + uint32_t reserved_4:6; + /** reg_slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t reg_slv_rdbuf_bitlen_en:1; + /** reg_slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t reg_slv_wrbuf_bitlen_en:1; + uint32_t reserved_12:14; + /** reg_slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t reg_slave_mode:1; + /** reg_soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t reg_soft_reset:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_spi_slave_reg_t; + + +/** Group: LP SPI SLAVE1 REG */ +/** Type of spi_slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** reg_slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t reg_slv_data_bitlen:18; + /** reg_slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t reg_slv_last_command:8; + /** reg_slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t reg_slv_last_addr:6; + }; + uint32_t val; +} lp_spi_slave1_reg_t; + + +/** Group: LP SPI CLK GATE REG */ +/** Type of spi_clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t reg_clk_en:1; + /** reg_mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t reg_mst_clk_active:1; + /** reg_mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t reg_mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_spi_clk_gate_reg_t; + + +/** Group: LP SPI DATE REG */ +/** Type of spi_date register + * Version control + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 33591360; + * SPI register version. + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_spi_date_reg_t; + + +/** Group: LP RND ECO CS REG */ +/** Type of rnd_eco_cs register + * NA + */ +typedef union { + struct { + /** reg_rnd_eco_en : R/W; bitpos: [0]; default: 0; + * NA + */ + uint32_t reg_rnd_eco_en:1; + /** rnd_eco_result : RO; bitpos: [1]; default: 0; + * NA + */ + uint32_t rnd_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_rnd_eco_cs_reg_t; + + +/** Group: LP RND ECO LOW REG */ +/** Type of rnd_eco_low register + * NA + */ +typedef union { + struct { + /** reg_rnd_eco_low : R/W; bitpos: [31:0]; default: 0; + * NA + */ + uint32_t reg_rnd_eco_low:32; + }; + uint32_t val; +} lp_rnd_eco_low_reg_t; + + +/** Group: LP RND ECO HIGH REG */ +/** Type of rnd_eco_high register + * NA + */ +typedef union { + struct { + /** reg_rnd_eco_high : R/W; bitpos: [31:0]; default: 65535; + * NA + */ + uint32_t reg_rnd_eco_high:32; + }; + uint32_t val; +} lp_rnd_eco_high_reg_t; + + +typedef struct { + volatile lp_spi_cmd_reg_t spi_cmd; + volatile lp_spi_addr_reg_t spi_addr; + volatile lp_spi_ctrl_reg_t spi_ctrl; + volatile lp_spi_clock_reg_t spi_clock; + volatile lp_spi_user_reg_t spi_user; + volatile lp_spi_user1_reg_t spi_user1; + volatile lp_spi_user2_reg_t spi_user2; + volatile lp_spi_ms_dlen_reg_t spi_ms_dlen; + volatile lp_spi_misc_reg_t spi_misc; + volatile lp_spi_din_mode_reg_t spi_din_mode; + volatile lp_spi_din_num_reg_t spi_din_num; + volatile lp_spi_dout_mode_reg_t spi_dout_mode; + volatile lp_spi_dma_conf_reg_t spi_dma_conf; + volatile lp_spi_dma_int_ena_reg_t spi_dma_int_ena; + volatile lp_spi_dma_int_clr_reg_t spi_dma_int_clr; + volatile lp_spi_dma_int_raw_reg_t spi_dma_int_raw; + volatile lp_spi_dma_int_st_reg_t spi_dma_int_st; + volatile lp_spi_sleep_conf0_reg_t spi_sleep_conf0; + volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1; + volatile lp_spi_dma_int_set_reg_t spi_dma_int_set; + uint32_t reserved_050[18]; + volatile lp_spi_w0_reg_t spi_w0; + volatile lp_spi_w1_reg_t spi_w1; + volatile lp_spi_w2_reg_t spi_w2; + volatile lp_spi_w3_reg_t spi_w3; + volatile lp_spi_w4_reg_t spi_w4; + volatile lp_spi_w5_reg_t spi_w5; + volatile lp_spi_w6_reg_t spi_w6; + volatile lp_spi_w7_reg_t spi_w7; + volatile lp_spi_w8_reg_t spi_w8; + volatile lp_spi_w9_reg_t spi_w9; + volatile lp_spi_w10_reg_t spi_w10; + volatile lp_spi_w11_reg_t spi_w11; + volatile lp_spi_w12_reg_t spi_w12; + volatile lp_spi_w13_reg_t spi_w13; + volatile lp_spi_w14_reg_t spi_w14; + volatile lp_spi_w15_reg_t spi_w15; + uint32_t reserved_0d8[2]; + volatile lp_spi_slave_reg_t spi_slave; + volatile lp_spi_slave1_reg_t spi_slave1; + volatile lp_spi_clk_gate_reg_t spi_clk_gate; + uint32_t reserved_0ec; + volatile lp_spi_date_reg_t spi_date; + volatile lp_rnd_eco_cs_reg_t rnd_eco_cs; + volatile lp_rnd_eco_low_reg_t rnd_eco_low; + volatile lp_rnd_eco_high_reg_t rnd_eco_high; +} lp_dev_t; + +extern lp_dev_t LP_SPI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_system_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_system_reg.h new file mode 100644 index 0000000000..3719697ee9 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_system_reg.h @@ -0,0 +1,1465 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_SYSTEM_REG_LP_SYSTEM_VER_DATE_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_SYSTEM_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0) +/** LP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296276; + * need_des + */ +#define LP_SYSTEM_REG_VER_DATE 0xFFFFFFFFU +#define LP_SYSTEM_REG_VER_DATE_M (LP_SYSTEM_REG_VER_DATE_V << LP_SYSTEM_REG_VER_DATE_S) +#define LP_SYSTEM_REG_VER_DATE_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_VER_DATE_S 0 + +/** LP_SYSTEM_REG_CLK_SEL_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4) +/** LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK (BIT(16)) +#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_M (LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V << LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S) +#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V 0x00000001U +#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S 16 +/** LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL (BIT(17)) +#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_M (LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V << LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S) +#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V 0x00000001U +#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S 17 + +/** LP_SYSTEM_REG_SYS_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8) +/** LP_SYSTEM_REG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0; + * lp cpu disable + */ +#define LP_SYSTEM_REG_LP_CORE_DISABLE (BIT(0)) +#define LP_SYSTEM_REG_LP_CORE_DISABLE_M (LP_SYSTEM_REG_LP_CORE_DISABLE_V << LP_SYSTEM_REG_LP_CORE_DISABLE_S) +#define LP_SYSTEM_REG_LP_CORE_DISABLE_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_DISABLE_S 0 +/** LP_SYSTEM_REG_SYS_SW_RST : WT; bitpos: [1]; default: 0; + * digital system software reset bit + */ +#define LP_SYSTEM_REG_SYS_SW_RST (BIT(1)) +#define LP_SYSTEM_REG_SYS_SW_RST_M (LP_SYSTEM_REG_SYS_SW_RST_V << LP_SYSTEM_REG_SYS_SW_RST_S) +#define LP_SYSTEM_REG_SYS_SW_RST_V 0x00000001U +#define LP_SYSTEM_REG_SYS_SW_RST_S 1 +/** LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT (BIT(2)) +#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_M (LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V << LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S) +#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S 2 +/** LP_SYSTEM_REG_DIG_FIB : R/W; bitpos: [10:3]; default: 255; + * need_des + */ +#define LP_SYSTEM_REG_DIG_FIB 0x000000FFU +#define LP_SYSTEM_REG_DIG_FIB_M (LP_SYSTEM_REG_DIG_FIB_V << LP_SYSTEM_REG_DIG_FIB_S) +#define LP_SYSTEM_REG_DIG_FIB_V 0x000000FFU +#define LP_SYSTEM_REG_DIG_FIB_S 3 +/** LP_SYSTEM_REG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0; + * reset disable bit for LP IOMUX + */ +#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE (BIT(11)) +#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_M (LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V << LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S) +#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S 11 +/** LP_SYSTEM_REG_ANA_FIB : RO; bitpos: [20:14]; default: 127; + * need_des + */ +#define LP_SYSTEM_REG_ANA_FIB 0x0000007FU +#define LP_SYSTEM_REG_ANA_FIB_M (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S) +#define LP_SYSTEM_REG_ANA_FIB_V 0x0000007FU +#define LP_SYSTEM_REG_ANA_FIB_S 14 +/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define LP_SYSTEM_REG_LP_FIB_SEL 0x000000FFU +#define LP_SYSTEM_REG_LP_FIB_SEL_M (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S) +#define LP_SYSTEM_REG_LP_FIB_SEL_V 0x000000FFU +#define LP_SYSTEM_REG_LP_FIB_SEL_S 21 +/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR (BIT(29)) +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S 29 +/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG (BIT(30)) +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_M (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S) +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S 30 +/** LP_SYSTEM_REG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0; + * 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from + * hp_core1 + */ +#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL (BIT(31)) +#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_M (LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V << LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S) +#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V 0x00000001U +#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S 31 + +/** LP_SYSTEM_REG_LP_CLK_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc) +/** LP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_SYSTEM_REG_CLK_EN (BIT(0)) +#define LP_SYSTEM_REG_CLK_EN_M (LP_SYSTEM_REG_CLK_EN_V << LP_SYSTEM_REG_CLK_EN_S) +#define LP_SYSTEM_REG_CLK_EN_V 0x00000001U +#define LP_SYSTEM_REG_CLK_EN_S 0 +/** LP_SYSTEM_REG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1; + * reserved + */ +#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN (BIT(14)) +#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_M (LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V << LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S) +#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V 0x00000001U +#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S 14 + +/** LP_SYSTEM_REG_LP_RST_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10) +/** LP_SYSTEM_REG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1; + * analog source reset bypass : wdt,brown out,super wdt,glitch + */ +#define LP_SYSTEM_REG_ANA_RST_BYPASS (BIT(0)) +#define LP_SYSTEM_REG_ANA_RST_BYPASS_M (LP_SYSTEM_REG_ANA_RST_BYPASS_V << LP_SYSTEM_REG_ANA_RST_BYPASS_S) +#define LP_SYSTEM_REG_ANA_RST_BYPASS_V 0x00000001U +#define LP_SYSTEM_REG_ANA_RST_BYPASS_S 0 +/** LP_SYSTEM_REG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1; + * system source reset bypass : software reset,hp wdt,lp wdt,efuse + */ +#define LP_SYSTEM_REG_SYS_RST_BYPASS (BIT(1)) +#define LP_SYSTEM_REG_SYS_RST_BYPASS_M (LP_SYSTEM_REG_SYS_RST_BYPASS_V << LP_SYSTEM_REG_SYS_RST_BYPASS_S) +#define LP_SYSTEM_REG_SYS_RST_BYPASS_V 0x00000001U +#define LP_SYSTEM_REG_SYS_RST_BYPASS_S 1 +/** LP_SYSTEM_REG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0; + * efuse force no reset control + */ +#define LP_SYSTEM_REG_EFUSE_FORCE_NORST (BIT(2)) +#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_M (LP_SYSTEM_REG_EFUSE_FORCE_NORST_V << LP_SYSTEM_REG_EFUSE_FORCE_NORST_S) +#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_V 0x00000001U +#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_S 2 + +/** LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18) +/** LP_SYSTEM_REG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856; + * need_des + */ +#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_M (LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V << LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S) +#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S 0 + +/** LP_SYSTEM_REG_EXT_WAKEUP1_REG register + * need_des + */ +#define LP_SYSTEM_REG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c) +/** LP_SYSTEM_REG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0; + * Bitmap to select RTC pads for ext wakeup1 + */ +#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL 0x0000FFFFU +#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_M (LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V << LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S) +#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V 0x0000FFFFU +#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S 0 +/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0; + * clear ext wakeup1 status + */ +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR (BIT(16)) +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_M (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S) +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V 0x00000001U +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S 16 + +/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG register + * need_des + */ +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20) +/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0; + * ext wakeup1 status + */ +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS 0x0000FFFFU +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_M (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S) +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V 0x0000FFFFU +#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S 0 + +/** LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24) +/** LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON (BIT(5)) +#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_M (LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S) +#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V 0x00000001U +#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S 5 +/** LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON (BIT(7)) +#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_M (LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S) +#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V 0x00000001U +#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S 7 + +/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG register + * need_des + */ +#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28) +/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP 0xFFFFFFFFU +#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_M (LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V << LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S) +#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S 0 + +/** LP_SYSTEM_REG_LP_STORE0_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c) +/** LP_SYSTEM_REG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH0 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH0_M (LP_SYSTEM_REG_LP_SCRATCH0_V << LP_SYSTEM_REG_LP_SCRATCH0_S) +#define LP_SYSTEM_REG_LP_SCRATCH0_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH0_S 0 + +/** LP_SYSTEM_REG_LP_STORE1_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30) +/** LP_SYSTEM_REG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH1 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH1_M (LP_SYSTEM_REG_LP_SCRATCH1_V << LP_SYSTEM_REG_LP_SCRATCH1_S) +#define LP_SYSTEM_REG_LP_SCRATCH1_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH1_S 0 + +/** LP_SYSTEM_REG_LP_STORE2_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34) +/** LP_SYSTEM_REG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH2 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH2_M (LP_SYSTEM_REG_LP_SCRATCH2_V << LP_SYSTEM_REG_LP_SCRATCH2_S) +#define LP_SYSTEM_REG_LP_SCRATCH2_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH2_S 0 + +/** LP_SYSTEM_REG_LP_STORE3_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38) +/** LP_SYSTEM_REG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH3 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH3_M (LP_SYSTEM_REG_LP_SCRATCH3_V << LP_SYSTEM_REG_LP_SCRATCH3_S) +#define LP_SYSTEM_REG_LP_SCRATCH3_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH3_S 0 + +/** LP_SYSTEM_REG_LP_STORE4_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c) +/** LP_SYSTEM_REG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH4 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH4_M (LP_SYSTEM_REG_LP_SCRATCH4_V << LP_SYSTEM_REG_LP_SCRATCH4_S) +#define LP_SYSTEM_REG_LP_SCRATCH4_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH4_S 0 + +/** LP_SYSTEM_REG_LP_STORE5_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40) +/** LP_SYSTEM_REG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH5 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH5_M (LP_SYSTEM_REG_LP_SCRATCH5_V << LP_SYSTEM_REG_LP_SCRATCH5_S) +#define LP_SYSTEM_REG_LP_SCRATCH5_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH5_S 0 + +/** LP_SYSTEM_REG_LP_STORE6_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44) +/** LP_SYSTEM_REG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH6 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH6_M (LP_SYSTEM_REG_LP_SCRATCH6_V << LP_SYSTEM_REG_LP_SCRATCH6_S) +#define LP_SYSTEM_REG_LP_SCRATCH6_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH6_S 0 + +/** LP_SYSTEM_REG_LP_STORE7_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48) +/** LP_SYSTEM_REG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH7 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH7_M (LP_SYSTEM_REG_LP_SCRATCH7_V << LP_SYSTEM_REG_LP_SCRATCH7_S) +#define LP_SYSTEM_REG_LP_SCRATCH7_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH7_S 0 + +/** LP_SYSTEM_REG_LP_STORE8_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c) +/** LP_SYSTEM_REG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH8 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH8_M (LP_SYSTEM_REG_LP_SCRATCH8_V << LP_SYSTEM_REG_LP_SCRATCH8_S) +#define LP_SYSTEM_REG_LP_SCRATCH8_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH8_S 0 + +/** LP_SYSTEM_REG_LP_STORE9_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50) +/** LP_SYSTEM_REG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH9 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH9_M (LP_SYSTEM_REG_LP_SCRATCH9_V << LP_SYSTEM_REG_LP_SCRATCH9_S) +#define LP_SYSTEM_REG_LP_SCRATCH9_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH9_S 0 + +/** LP_SYSTEM_REG_LP_STORE10_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54) +/** LP_SYSTEM_REG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH10 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH10_M (LP_SYSTEM_REG_LP_SCRATCH10_V << LP_SYSTEM_REG_LP_SCRATCH10_S) +#define LP_SYSTEM_REG_LP_SCRATCH10_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH10_S 0 + +/** LP_SYSTEM_REG_LP_STORE11_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58) +/** LP_SYSTEM_REG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH11 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH11_M (LP_SYSTEM_REG_LP_SCRATCH11_V << LP_SYSTEM_REG_LP_SCRATCH11_S) +#define LP_SYSTEM_REG_LP_SCRATCH11_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH11_S 0 + +/** LP_SYSTEM_REG_LP_STORE12_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c) +/** LP_SYSTEM_REG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH12 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH12_M (LP_SYSTEM_REG_LP_SCRATCH12_V << LP_SYSTEM_REG_LP_SCRATCH12_S) +#define LP_SYSTEM_REG_LP_SCRATCH12_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH12_S 0 + +/** LP_SYSTEM_REG_LP_STORE13_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60) +/** LP_SYSTEM_REG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH13 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH13_M (LP_SYSTEM_REG_LP_SCRATCH13_V << LP_SYSTEM_REG_LP_SCRATCH13_S) +#define LP_SYSTEM_REG_LP_SCRATCH13_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH13_S 0 + +/** LP_SYSTEM_REG_LP_STORE14_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64) +/** LP_SYSTEM_REG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH14 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH14_M (LP_SYSTEM_REG_LP_SCRATCH14_V << LP_SYSTEM_REG_LP_SCRATCH14_S) +#define LP_SYSTEM_REG_LP_SCRATCH14_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH14_S 0 + +/** LP_SYSTEM_REG_LP_STORE15_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68) +/** LP_SYSTEM_REG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_SCRATCH15 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH15_M (LP_SYSTEM_REG_LP_SCRATCH15_V << LP_SYSTEM_REG_LP_SCRATCH15_S) +#define LP_SYSTEM_REG_LP_SCRATCH15_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_SCRATCH15_S 0 + +/** LP_SYSTEM_REG_LP_PROBEA_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c) +/** LP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_A_MOD_SEL 0x0000FFFFU +#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_M (LP_SYSTEM_REG_PROBE_A_MOD_SEL_V << LP_SYSTEM_REG_PROBE_A_MOD_SEL_S) +#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_V 0x0000FFFFU +#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_S 0 +/** LP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_A_TOP_SEL 0x000000FFU +#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_M (LP_SYSTEM_REG_PROBE_A_TOP_SEL_V << LP_SYSTEM_REG_PROBE_A_TOP_SEL_S) +#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_V 0x000000FFU +#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_S 16 +/** LP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_L_SEL 0x00000003U +#define LP_SYSTEM_REG_PROBE_L_SEL_M (LP_SYSTEM_REG_PROBE_L_SEL_V << LP_SYSTEM_REG_PROBE_L_SEL_S) +#define LP_SYSTEM_REG_PROBE_L_SEL_V 0x00000003U +#define LP_SYSTEM_REG_PROBE_L_SEL_S 24 +/** LP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_H_SEL 0x00000003U +#define LP_SYSTEM_REG_PROBE_H_SEL_M (LP_SYSTEM_REG_PROBE_H_SEL_V << LP_SYSTEM_REG_PROBE_H_SEL_S) +#define LP_SYSTEM_REG_PROBE_H_SEL_V 0x00000003U +#define LP_SYSTEM_REG_PROBE_H_SEL_S 26 +/** LP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_GLOBAL_EN (BIT(28)) +#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_M (LP_SYSTEM_REG_PROBE_GLOBAL_EN_V << LP_SYSTEM_REG_PROBE_GLOBAL_EN_S) +#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_V 0x00000001U +#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_S 28 + +/** LP_SYSTEM_REG_LP_PROBEB_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70) +/** LP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_B_MOD_SEL 0x0000FFFFU +#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_M (LP_SYSTEM_REG_PROBE_B_MOD_SEL_V << LP_SYSTEM_REG_PROBE_B_MOD_SEL_S) +#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_V 0x0000FFFFU +#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_S 0 +/** LP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_B_TOP_SEL 0x000000FFU +#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_M (LP_SYSTEM_REG_PROBE_B_TOP_SEL_V << LP_SYSTEM_REG_PROBE_B_TOP_SEL_S) +#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_V 0x000000FFU +#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_S 16 +/** LP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_B_EN (BIT(24)) +#define LP_SYSTEM_REG_PROBE_B_EN_M (LP_SYSTEM_REG_PROBE_B_EN_V << LP_SYSTEM_REG_PROBE_B_EN_S) +#define LP_SYSTEM_REG_PROBE_B_EN_V 0x00000001U +#define LP_SYSTEM_REG_PROBE_B_EN_S 24 + +/** LP_SYSTEM_REG_LP_PROBE_OUT_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74) +/** LP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PROBE_TOP_OUT 0xFFFFFFFFU +#define LP_SYSTEM_REG_PROBE_TOP_OUT_M (LP_SYSTEM_REG_PROBE_TOP_OUT_V << LP_SYSTEM_REG_PROBE_TOP_OUT_S) +#define LP_SYSTEM_REG_PROBE_TOP_OUT_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_PROBE_TOP_OUT_S 0 + +/** LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG register + * need_des + */ +#define LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c) +/** LP_SYSTEM_REG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define LP_SYSTEM_REG_F2S_APB_POSTW_EN (BIT(0)) +#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_M (LP_SYSTEM_REG_F2S_APB_POSTW_EN_V << LP_SYSTEM_REG_F2S_APB_POSTW_EN_S) +#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_V 0x00000001U +#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_S 0 + +/** LP_SYSTEM_REG_USB_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100) +/** LP_SYSTEM_REG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL (BIT(0)) +#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_M (LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S) +#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V 0x00000001U +#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S 0 +/** LP_SYSTEM_REG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_SW_USB_PHY_SEL (BIT(1)) +#define LP_SYSTEM_REG_SW_USB_PHY_SEL_M (LP_SYSTEM_REG_SW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_USB_PHY_SEL_S) +#define LP_SYSTEM_REG_SW_USB_PHY_SEL_V 0x00000001U +#define LP_SYSTEM_REG_SW_USB_PHY_SEL_S 1 +/** LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0; + * clear usb wakeup to PMU. + */ +#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR (BIT(2)) +#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_M (LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V << LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S) +#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V 0x00000001U +#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S 2 +/** LP_SYSTEM_REG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0; + * indicate usb otg2.0 is in suspend state. + */ +#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND (BIT(3)) +#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_M (LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V << LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S) +#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V 0x00000001U +#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S 3 +/** LP_SYSTEM_REG_USBOTG20_LS_MODE : R/W; bitpos: [4]; default: 0; + * indicate current mode of usb otg2.0. + */ +#define LP_SYSTEM_REG_USBOTG20_LS_MODE (BIT(4)) +#define LP_SYSTEM_REG_USBOTG20_LS_MODE_M (LP_SYSTEM_REG_USBOTG20_LS_MODE_V << LP_SYSTEM_REG_USBOTG20_LS_MODE_S) +#define LP_SYSTEM_REG_USBOTG20_LS_MODE_V 0x00000001U +#define LP_SYSTEM_REG_USBOTG20_LS_MODE_S 4 + +/** LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG register + * need_des + */ +#define LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c) +/** LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255; + * Set 1 to power up pad group + */ +#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP 0x000000FFU +#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_M (LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V << LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S) +#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V 0x000000FFU +#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S 0 + +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110) +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN (BIT(0)) +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S) +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S 0 +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT (BIT(1)) +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S) +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V 0x00000001U +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S 1 + +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114) +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S) +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S 0 + +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118) +/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_M (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S) +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S 0 + +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c) +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN (BIT(0)) +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S) +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S 0 +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT (BIT(1)) +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S) +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V 0x00000001U +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S 1 + +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120) +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S) +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S 0 + +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124) +/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_M (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S) +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S 0 + +/** LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130) +/** LP_SYSTEM_REG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1; + * clock gate enable for hp cpu root 400M clk + */ +#define LP_SYSTEM_REG_CPU_CLK_EN (BIT(0)) +#define LP_SYSTEM_REG_CPU_CLK_EN_M (LP_SYSTEM_REG_CPU_CLK_EN_V << LP_SYSTEM_REG_CPU_CLK_EN_S) +#define LP_SYSTEM_REG_CPU_CLK_EN_V 0x00000001U +#define LP_SYSTEM_REG_CPU_CLK_EN_S 0 +/** LP_SYSTEM_REG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1; + * clock gate enable for hp sys root 480M clk + */ +#define LP_SYSTEM_REG_SYS_CLK_EN (BIT(1)) +#define LP_SYSTEM_REG_SYS_CLK_EN_M (LP_SYSTEM_REG_SYS_CLK_EN_V << LP_SYSTEM_REG_SYS_CLK_EN_S) +#define LP_SYSTEM_REG_SYS_CLK_EN_V 0x00000001U +#define LP_SYSTEM_REG_SYS_CLK_EN_S 1 + +/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138) +/** LP_SYSTEM_REG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW 0xFFFFFFFFU +#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_M (LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V << LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S) +#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S 0 + +/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c) +/** LP_SYSTEM_REG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH 0xFFFFFFFFU +#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_M (LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V << LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S) +#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S 0 + +/** LP_SYSTEM_REG_PAD_COMP0_REG register + * need_des + */ +#define LP_SYSTEM_REG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148) +/** LP_SYSTEM_REG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0; + * pad comp dref + */ +#define LP_SYSTEM_REG_DREF_COMP0 0x00000007U +#define LP_SYSTEM_REG_DREF_COMP0_M (LP_SYSTEM_REG_DREF_COMP0_V << LP_SYSTEM_REG_DREF_COMP0_S) +#define LP_SYSTEM_REG_DREF_COMP0_V 0x00000007U +#define LP_SYSTEM_REG_DREF_COMP0_S 0 +/** LP_SYSTEM_REG_MODE_COMP0 : R/W; bitpos: [3]; default: 0; + * pad comp mode + */ +#define LP_SYSTEM_REG_MODE_COMP0 (BIT(3)) +#define LP_SYSTEM_REG_MODE_COMP0_M (LP_SYSTEM_REG_MODE_COMP0_V << LP_SYSTEM_REG_MODE_COMP0_S) +#define LP_SYSTEM_REG_MODE_COMP0_V 0x00000001U +#define LP_SYSTEM_REG_MODE_COMP0_S 3 +/** LP_SYSTEM_REG_XPD_COMP0 : R/W; bitpos: [4]; default: 0; + * pad comp xpd + */ +#define LP_SYSTEM_REG_XPD_COMP0 (BIT(4)) +#define LP_SYSTEM_REG_XPD_COMP0_M (LP_SYSTEM_REG_XPD_COMP0_V << LP_SYSTEM_REG_XPD_COMP0_S) +#define LP_SYSTEM_REG_XPD_COMP0_V 0x00000001U +#define LP_SYSTEM_REG_XPD_COMP0_S 4 + +/** LP_SYSTEM_REG_PAD_COMP1_REG register + * need_des + */ +#define LP_SYSTEM_REG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c) +/** LP_SYSTEM_REG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0; + * pad comp dref + */ +#define LP_SYSTEM_REG_DREF_COMP1 0x00000007U +#define LP_SYSTEM_REG_DREF_COMP1_M (LP_SYSTEM_REG_DREF_COMP1_V << LP_SYSTEM_REG_DREF_COMP1_S) +#define LP_SYSTEM_REG_DREF_COMP1_V 0x00000007U +#define LP_SYSTEM_REG_DREF_COMP1_S 0 +/** LP_SYSTEM_REG_MODE_COMP1 : R/W; bitpos: [3]; default: 0; + * pad comp mode + */ +#define LP_SYSTEM_REG_MODE_COMP1 (BIT(3)) +#define LP_SYSTEM_REG_MODE_COMP1_M (LP_SYSTEM_REG_MODE_COMP1_V << LP_SYSTEM_REG_MODE_COMP1_S) +#define LP_SYSTEM_REG_MODE_COMP1_V 0x00000001U +#define LP_SYSTEM_REG_MODE_COMP1_S 3 +/** LP_SYSTEM_REG_XPD_COMP1 : R/W; bitpos: [4]; default: 0; + * pad comp xpd + */ +#define LP_SYSTEM_REG_XPD_COMP1 (BIT(4)) +#define LP_SYSTEM_REG_XPD_COMP1_M (LP_SYSTEM_REG_XPD_COMP1_V << LP_SYSTEM_REG_XPD_COMP1_S) +#define LP_SYSTEM_REG_XPD_COMP1_V 0x00000001U +#define LP_SYSTEM_REG_XPD_COMP1_S 4 + +/** LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG register + * need_des + */ +#define LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154) +/** LP_SYSTEM_REG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10; + * need_des + */ +#define LP_SYSTEM_REG_BURST_LIMIT_AON 0x0000001FU +#define LP_SYSTEM_REG_BURST_LIMIT_AON_M (LP_SYSTEM_REG_BURST_LIMIT_AON_V << LP_SYSTEM_REG_BURST_LIMIT_AON_S) +#define LP_SYSTEM_REG_BURST_LIMIT_AON_V 0x0000001FU +#define LP_SYSTEM_REG_BURST_LIMIT_AON_S 0 +/** LP_SYSTEM_REG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10; + * need_des + */ +#define LP_SYSTEM_REG_READ_INTERVAL_AON 0x0000007FU +#define LP_SYSTEM_REG_READ_INTERVAL_AON_M (LP_SYSTEM_REG_READ_INTERVAL_AON_V << LP_SYSTEM_REG_READ_INTERVAL_AON_S) +#define LP_SYSTEM_REG_READ_INTERVAL_AON_V 0x0000007FU +#define LP_SYSTEM_REG_READ_INTERVAL_AON_S 5 +/** LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100; + * need_des + */ +#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU +#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_M (LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S) +#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU +#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S 12 +/** LP_SYSTEM_REG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100; + * need_des + */ +#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON 0x000003FFU +#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_M (LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S) +#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V 0x000003FFU +#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S 22 + +/** LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG register + * need_des + */ +#define LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158) +/** LP_SYSTEM_REG_AON_BYPASS : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_AON_BYPASS (BIT(31)) +#define LP_SYSTEM_REG_AON_BYPASS_M (LP_SYSTEM_REG_AON_BYPASS_V << LP_SYSTEM_REG_AON_BYPASS_S) +#define LP_SYSTEM_REG_AON_BYPASS_V 0x00000001U +#define LP_SYSTEM_REG_AON_BYPASS_S 31 + +/** LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG register + * need_des + */ +#define LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c) +/** LP_SYSTEM_REG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LINK_ADDR_AON 0xFFFFFFFFU +#define LP_SYSTEM_REG_LINK_ADDR_AON_M (LP_SYSTEM_REG_LINK_ADDR_AON_V << LP_SYSTEM_REG_LINK_ADDR_AON_S) +#define LP_SYSTEM_REG_LINK_ADDR_AON_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LINK_ADDR_AON_S 0 + +/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG register + * need_des + */ +#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164) +/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 0xFFFFFFFFU +#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_M (LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V << LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S) +#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S 0 + +/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168) +/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_M (LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S 0 + +/** LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c) +/** LP_SYSTEM_REG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0; + * master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: + * regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha + * tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_ID 0x0000001FU +#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_M (LP_SYSTEM_REG_LP_ADDRHOLE_ID_V << LP_SYSTEM_REG_LP_ADDRHOLE_ID_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_V 0x0000001FU +#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_S 0 +/** LP_SYSTEM_REG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0; + * 1:write trans, 0: read trans. + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_WR (BIT(5)) +#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_M (LP_SYSTEM_REG_LP_ADDRHOLE_WR_V << LP_SYSTEM_REG_LP_ADDRHOLE_WR_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_V 0x00000001U +#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_S 5 +/** LP_SYSTEM_REG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0; + * 1: illegal address access, 0: access without permission + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE (BIT(6)) +#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_M (LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V 0x00000001U +#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S 6 + +/** LP_SYSTEM_REG_INT_RAW_REG register + * raw interrupt register + */ +#define LP_SYSTEM_REG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170) +/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp + * matrix default slave) + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW (BIT(0)) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S 0 +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW (BIT(1)) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S 1 +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * the raw interrupt status of lp core ahb bus timeout + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW (BIT(2)) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S 2 +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * the raw interrupt status of lp core ibus timeout + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW (BIT(3)) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S 3 +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * the raw interrupt status of lp core dbus timeout + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW (BIT(4)) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S 4 +/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * the raw interrupt status of etm task ulp + */ +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW (BIT(5)) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S 5 +/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * the raw interrupt status of slow_clk_tick + */ +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW (BIT(6)) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V 0x00000001U +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S 6 + +/** LP_SYSTEM_REG_INT_ST_REG register + * masked interrupt register + */ +#define LP_SYSTEM_REG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174) +/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0; + * the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp + * matrix default slave) + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST (BIT(0)) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S 0 +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0; + * the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST (BIT(1)) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S 1 +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0; + * the masked interrupt status of lp core ahb bus timeout + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST (BIT(2)) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S 2 +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0; + * the masked interrupt status of lp core ibus timeout + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST (BIT(3)) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S 3 +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0; + * the masked interrupt status of lp core dbus timeout + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST (BIT(4)) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S 4 +/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0; + * the masked interrupt status of etm task ulp + */ +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST (BIT(5)) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S 5 +/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0; + * the masked interrupt status of slow_clk_tick + */ +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST (BIT(6)) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V 0x00000001U +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S 6 + +/** LP_SYSTEM_REG_INT_ENA_REG register + * masked interrupt register + */ +#define LP_SYSTEM_REG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178) +/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable lp addrhole int + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA (BIT(0)) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S 0 +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable idbus addrhole int + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA (BIT(1)) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S 1 +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to enable lp_core_ahb_timeout int + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA (BIT(2)) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S 2 +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to enable lp_core_ibus_timeout int + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA (BIT(3)) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S 3 +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to enable lp_core_dbus_timeout int + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA (BIT(4)) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S 4 +/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to enable etm task ulp int + */ +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA (BIT(5)) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S 5 +/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable slow_clk_tick int + */ +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA (BIT(6)) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V 0x00000001U +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S 6 + +/** LP_SYSTEM_REG_INT_CLR_REG register + * interrupt clear register + */ +#define LP_SYSTEM_REG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c) +/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0; + * write 1 to clear lp addrhole int + */ +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR (BIT(0)) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_M (LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S) +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S 0 +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0; + * write 1 to clear idbus addrhole int + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR (BIT(1)) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S 1 +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear lp_core_ahb_timeout int + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR (BIT(2)) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S 2 +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear lp_core_ibus_timeout int + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR (BIT(3)) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S 3 +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear lp_core_dbus_timeout int + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR (BIT(4)) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S 4 +/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear etm tasl ulp int + */ +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR (BIT(5)) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_M (LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S) +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S 5 +/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear slow_clk_tick int + */ +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR (BIT(6)) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_M (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S) +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V 0x00000001U +#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S 6 + +/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180) +/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_M (LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S) +#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S 0 + +/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184) +/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_M (LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S) +#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S 0 + +/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188) +/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; + * need_des + */ +#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL 0xFFFFFFFFU +#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_M (LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S) +#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S 0 + +/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c) +/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; + * need_des + */ +#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_M (LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S) +#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S 0 + +/** LP_SYSTEM_REG_LP_CPU_DBG_PC_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190) +/** LP_SYSTEM_REG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_CPU_DBG_PC 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_CPU_DBG_PC_M (LP_SYSTEM_REG_LP_CPU_DBG_PC_V << LP_SYSTEM_REG_LP_CPU_DBG_PC_S) +#define LP_SYSTEM_REG_LP_CPU_DBG_PC_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_CPU_DBG_PC_S 0 + +/** LP_SYSTEM_REG_LP_CPU_EXC_PC_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194) +/** LP_SYSTEM_REG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_LP_CPU_EXC_PC 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_CPU_EXC_PC_M (LP_SYSTEM_REG_LP_CPU_EXC_PC_V << LP_SYSTEM_REG_LP_CPU_EXC_PC_S) +#define LP_SYSTEM_REG_LP_CPU_EXC_PC_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_LP_CPU_EXC_PC_S 0 + +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG register + * need_des + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198) +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR 0xFFFFFFFFU +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S 0 + +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG register + * need_des + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c) +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID 0x0000001FU +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V 0x0000001FU +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S 0 +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR (BIT(5)) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V 0x00000001U +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S 5 +/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0; + * need_des + */ +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE (BIT(6)) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_M (LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S) +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V 0x00000001U +#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S 6 + +/** LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG register + * need_des + */ +#define LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0) +/** LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255; + * [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn + * [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn + * [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn + * [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn + * [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst + * [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst + * [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn + * [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn + */ +#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL 0x000000FFU +#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M (LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S) +#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V 0x000000FFU +#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S 8 +/** LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255; + * [31] 1'b1: po_rstn bypass sys_sw_rstn + * [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn + * [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn + * [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn + * [27] 1'b1: po_rstn bypass usb_jtag_chip_rst + * [26] 1'b1: po_rstn bypass usb_uart_chip_rst + * [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn + * [24] 1'b1: po_rstn bypass efuse_err_rstn + */ +#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL 0x000000FFU +#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_M (LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S) +#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V 0x000000FFU +#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S 24 + +/** LP_SYSTEM_REG_RNG_DATA_REG register + * rng data register + */ +#define LP_SYSTEM_REG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4) +/** LP_SYSTEM_REG_RND_DATA : RO; bitpos: [31:0]; default: 0; + * result of rng output + */ +#define LP_SYSTEM_REG_RND_DATA 0xFFFFFFFFU +#define LP_SYSTEM_REG_RND_DATA_M (LP_SYSTEM_REG_RND_DATA_V << LP_SYSTEM_REG_RND_DATA_S) +#define LP_SYSTEM_REG_RND_DATA_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_RND_DATA_S 0 + +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0) +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1; + * set this field to 1 to enable lp core ahb timeout handle + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN (BIT(0)) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S 0 +/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535; + * This field used to set lp core ahb bus timeout threshold + */ +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES 0x0000FFFFU +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S) +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V 0x0000FFFFU +#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S 1 +/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1; + * set this field to 1 to enable lp2hp ahb timeout handle + */ +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN (BIT(17)) +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_M (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S) +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S 17 +/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31; + * This field used to set lp2hp ahb bus timeout threshold + */ +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES 0x0000001FU +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S) +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V 0x0000001FU +#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S 18 + +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4) +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1; + * set this field to 1 to enable lp core ibus timeout handle + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN (BIT(0)) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S 0 +/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535; + * This field used to set lp core ibus timeout threshold + */ +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES 0x0000FFFFU +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S) +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V 0x0000FFFFU +#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S 1 + +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8) +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1; + * set this field to 1 to enable lp core dbus timeout handle + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN (BIT(0)) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S 0 +/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535; + * This field used to set lp core dbus timeout threshold + */ +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES 0x0000FFFFU +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_M (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S) +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V 0x0000FFFFU +#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S 1 + +/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG register + * need_des + */ +#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc) +/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0; + * Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to + * disable ahb err resp. + */ +#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS 0x00000007U +#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_M (LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V << LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S) +#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V 0x00000007U +#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S 0 + +/** LP_SYSTEM_REG_RNG_CFG_REG register + * rng cfg register + */ +#define LP_SYSTEM_REG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0) +/** LP_SYSTEM_REG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1; + * enable rng timer + */ +#define LP_SYSTEM_REG_RNG_TIMER_EN (BIT(0)) +#define LP_SYSTEM_REG_RNG_TIMER_EN_M (LP_SYSTEM_REG_RNG_TIMER_EN_V << LP_SYSTEM_REG_RNG_TIMER_EN_S) +#define LP_SYSTEM_REG_RNG_TIMER_EN_V 0x00000001U +#define LP_SYSTEM_REG_RNG_TIMER_EN_S 0 +/** LP_SYSTEM_REG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1; + * configure ng timer pscale + */ +#define LP_SYSTEM_REG_RNG_TIMER_PSCALE 0x000000FFU +#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_M (LP_SYSTEM_REG_RNG_TIMER_PSCALE_V << LP_SYSTEM_REG_RNG_TIMER_PSCALE_S) +#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_V 0x000000FFU +#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_S 1 +/** LP_SYSTEM_REG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0; + * enable rng_saradc + */ +#define LP_SYSTEM_REG_RNG_SAR_ENABLE (BIT(9)) +#define LP_SYSTEM_REG_RNG_SAR_ENABLE_M (LP_SYSTEM_REG_RNG_SAR_ENABLE_V << LP_SYSTEM_REG_RNG_SAR_ENABLE_S) +#define LP_SYSTEM_REG_RNG_SAR_ENABLE_V 0x00000001U +#define LP_SYSTEM_REG_RNG_SAR_ENABLE_S 9 +/** LP_SYSTEM_REG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0; + * debug rng sar sample cnt + */ +#define LP_SYSTEM_REG_RNG_SAR_DATA 0x00001FFFU +#define LP_SYSTEM_REG_RNG_SAR_DATA_M (LP_SYSTEM_REG_RNG_SAR_DATA_V << LP_SYSTEM_REG_RNG_SAR_DATA_S) +#define LP_SYSTEM_REG_RNG_SAR_DATA_V 0x00001FFFU +#define LP_SYSTEM_REG_RNG_SAR_DATA_S 16 + +/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_REG register + * enable pad hold ctrl + */ +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_REG (DR_REG_LP_SYS_BASE + 0x1c4) +/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0 : R/W; bitpos: [31:0]; default: 0; + * Set 1 to hold pad 0-31 status + */ +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0 0xFFFFFFFFU +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_M (LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_V << LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_S) +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_V 0xFFFFFFFFU +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL0_S 0 + +/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_REG register + * enable pad hold ctrl + */ +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_REG (DR_REG_LP_SYS_BASE + 0x1c8) +/** LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1 : R/W; bitpos: [24:0]; default: 0; + * Set 1 to hold pad 32-56 status + */ +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1 0x01FFFFFFU +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_M (LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_V << LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_S) +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_V 0x01FFFFFFU +#define LP_SYSTEM_REG_PAD_RTC_HOLD_CTRL1_S 0 + +/** LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_REG register + * enable pad hold ctrl + */ +#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1cc) +/** LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL : R/W; bitpos: [25:0]; default: 0; + * Set bit0-5 to hold flash pad status. Set bit6-25 to hold psram pad status. + */ +#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL 0x03FFFFFFU +#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_M (LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_V << LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_S) +#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_V 0x03FFFFFFU +#define LP_SYSTEM_REG_DED_PAD_RTC_HOLD_CTRL_S 0 + +/** LP_SYSTEM_REG_DISCHARGE_REG register + * pufmem / ldo flash power discharge control + */ +#define LP_SYSTEM_REG_DISCHARGE_REG (DR_REG_LP_SYS_BASE + 0x200) +/** LP_SYSTEM_REG_LDO_FLASH_DISCHARGE : R/W; bitpos: [0]; default: 0; + * Set this bit to discharge ldo flash. + */ +#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE (BIT(0)) +#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_M (LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_V << LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_S) +#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_V 0x00000001U +#define LP_SYSTEM_REG_LDO_FLASH_DISCHARGE_S 0 +/** LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to discharge lp puf mem. + */ +#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN (BIT(1)) +#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_M (LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_V << LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_S) +#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_V 0x00000001U +#define LP_SYSTEM_REG_LP_PUF_MEM_ISO_EN_S 1 +/** LP_SYSTEM_REG_LP_PUF_MEM_XPD : R/W; bitpos: [2]; default: 1; + * Set this bit to discharge lp puf mem. + */ +#define LP_SYSTEM_REG_LP_PUF_MEM_XPD (BIT(2)) +#define LP_SYSTEM_REG_LP_PUF_MEM_XPD_M (LP_SYSTEM_REG_LP_PUF_MEM_XPD_V << LP_SYSTEM_REG_LP_PUF_MEM_XPD_S) +#define LP_SYSTEM_REG_LP_PUF_MEM_XPD_V 0x00000001U +#define LP_SYSTEM_REG_LP_PUF_MEM_XPD_S 2 +/** LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE : R/W; bitpos: [3]; default: 0; + * Set this bit to discharge lp puf mem. + */ +#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE (BIT(3)) +#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_M (LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_V << LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_S) +#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_V 0x00000001U +#define LP_SYSTEM_REG_LP_PUF_MEM_DISCHARGE_S 3 + +/** LP_SYSTEM_REG_HP_USB_OTGHS_PHY_CTRL_REG register + * Usb otg2.0 PHY control register + */ +#define LP_SYSTEM_REG_HP_USB_OTGHS_PHY_CTRL_REG (DR_REG_LP_SYS_BASE + 0x204) +/** LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP : R/W; bitpos: [0]; default: 1; + * Set this bit to pull up USB OTG2.0 PHY id + */ +#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP (BIT(0)) +#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_M (LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_V << LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_S) +#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_V 0x00000001U +#define LP_SYSTEM_REG_HP_UTMIOTG_IDPULLUP_S 0 +/** LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN : R/W; bitpos: [1]; default: 1; + * Set this bit to pull down USB OTG2.0 PHY dp + */ +#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN (BIT(1)) +#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_M (LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_V << LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_S) +#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_V 0x00000001U +#define LP_SYSTEM_REG_HP_UTMIOTG_DPPULLDOWN_S 1 +/** LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN : R/W; bitpos: [2]; default: 1; + * Set this bit to pull down USB OTG2.0 PHY dm + */ +#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN (BIT(2)) +#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_M (LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_V << LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_S) +#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_V 0x00000001U +#define LP_SYSTEM_REG_HP_UTMIOTG_DMPULLDOWN_S 2 +/** LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS : R/W; bitpos: [3]; default: 0; + * Set this bit to charge USB OTG2.0 PHY vbus + */ +#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS (BIT(3)) +#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_M (LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_V << LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_S) +#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_V 0x00000001U +#define LP_SYSTEM_REG_HP_UTMISRP_CHRGVBUS_S 3 +/** LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS : R/W; bitpos: [4]; default: 0; + * Set this bit to discharge USB OTG2.0 PHY vbus + */ +#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS (BIT(4)) +#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_M (LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_V << LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_S) +#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_V 0x00000001U +#define LP_SYSTEM_REG_HP_UTMISRP_DISCHRGVBUS_S 4 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_system_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_system_struct.h new file mode 100644 index 0000000000..56af2b70c0 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_system_struct.h @@ -0,0 +1,1418 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_sys_ver_date register + * need_des + */ +typedef union { + struct { + /** ver_date : R/W; bitpos: [31:0]; default: 539296276; + * need_des + */ + uint32_t ver_date:32; + }; + uint32_t val; +} lp_system_reg_lp_sys_ver_date_reg_t; + +/** Type of clk_sel_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ena_sw_sel_sys_clk : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t ena_sw_sel_sys_clk:1; + /** sw_sys_clk_src_sel : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t sw_sys_clk_src_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} lp_system_reg_clk_sel_ctrl_reg_t; + +/** Type of sys_ctrl register + * need_des + */ +typedef union { + struct { + /** lp_core_disable : R/W; bitpos: [0]; default: 0; + * lp cpu disable + */ + uint32_t lp_core_disable:1; + /** sys_sw_rst : WT; bitpos: [1]; default: 0; + * digital system software reset bit + */ + uint32_t sys_sw_rst:1; + /** force_download_boot : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t force_download_boot:1; + /** dig_fib : R/W; bitpos: [10:3]; default: 255; + * need_des + */ + uint32_t dig_fib:8; + /** io_mux_reset_disable : R/W; bitpos: [11]; default: 0; + * reset disable bit for LP IOMUX + */ + uint32_t io_mux_reset_disable:1; + uint32_t reserved_12:2; + /** ana_fib : RO; bitpos: [20:14]; default: 127; + * need_des + */ + uint32_t ana_fib:7; + /** lp_fib_sel : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_fib_sel:8; + /** lp_core_etm_wakeup_flag_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_core_etm_wakeup_flag_clr:1; + /** lp_core_etm_wakeup_flag : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_core_etm_wakeup_flag:1; + /** systimer_stall_sel : R/W; bitpos: [31]; default: 0; + * 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from + * hp_core1 + */ + uint32_t systimer_stall_sel:1; + }; + uint32_t val; +} lp_system_reg_sys_ctrl_reg_t; + +/** Type of lp_clk_ctrl register + * need_des + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t clk_en:1; + uint32_t reserved_1:13; + /** lp_fosc_hp_cken : R/W; bitpos: [14]; default: 1; + * reserved + */ + uint32_t lp_fosc_hp_cken:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_system_reg_lp_clk_ctrl_reg_t; + +/** Type of lp_rst_ctrl register + * need_des + */ +typedef union { + struct { + /** ana_rst_bypass : R/W; bitpos: [0]; default: 1; + * analog source reset bypass : wdt,brown out,super wdt,glitch + */ + uint32_t ana_rst_bypass:1; + /** sys_rst_bypass : R/W; bitpos: [1]; default: 1; + * system source reset bypass : software reset,hp wdt,lp wdt,efuse + */ + uint32_t sys_rst_bypass:1; + /** efuse_force_norst : R/W; bitpos: [2]; default: 0; + * efuse force no reset control + */ + uint32_t efuse_force_norst:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_system_reg_lp_rst_ctrl_reg_t; + +/** Type of lp_core_boot_addr register + * need_des + */ +typedef union { + struct { + /** lp_cpu_boot_addr : R/W; bitpos: [31:0]; default: 1343225856; + * need_des + */ + uint32_t lp_cpu_boot_addr:32; + }; + uint32_t val; +} lp_system_reg_lp_core_boot_addr_reg_t; + +/** Type of ext_wakeup1 register + * need_des + */ +typedef union { + struct { + /** ext_wakeup1_sel : R/W; bitpos: [15:0]; default: 0; + * Bitmap to select RTC pads for ext wakeup1 + */ + uint32_t ext_wakeup1_sel:16; + /** ext_wakeup1_status_clr : WT; bitpos: [16]; default: 0; + * clear ext wakeup1 status + */ + uint32_t ext_wakeup1_status_clr:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_system_reg_ext_wakeup1_reg_t; + +/** Type of ext_wakeup1_status register + * need_des + */ +typedef union { + struct { + /** ext_wakeup1_status : RO; bitpos: [15:0]; default: 0; + * ext wakeup1 status + */ + uint32_t ext_wakeup1_status:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_system_reg_ext_wakeup1_status_reg_t; + +/** Type of lp_tcm_pwr_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** lp_tcm_rom_clk_force_on : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t lp_tcm_rom_clk_force_on:1; + uint32_t reserved_6:1; + /** lp_tcm_ram_clk_force_on : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t lp_tcm_ram_clk_force_on:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_system_reg_lp_tcm_pwr_ctrl_reg_t; + +/** Type of boot_addr_hp_lp_reg register + * need_des + */ +typedef union { + struct { + /** boot_addr_hp_lp : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t boot_addr_hp_lp:32; + }; + uint32_t val; +} lp_system_reg_boot_addr_hp_lp_reg_reg_t; + +/** Type of lp_store0 register + * need_des + */ +typedef union { + struct { + /** lp_scratch0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch0:32; + }; + uint32_t val; +} lp_system_reg_lp_store0_reg_t; + +/** Type of lp_store1 register + * need_des + */ +typedef union { + struct { + /** lp_scratch1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch1:32; + }; + uint32_t val; +} lp_system_reg_lp_store1_reg_t; + +/** Type of lp_store2 register + * need_des + */ +typedef union { + struct { + /** lp_scratch2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch2:32; + }; + uint32_t val; +} lp_system_reg_lp_store2_reg_t; + +/** Type of lp_store3 register + * need_des + */ +typedef union { + struct { + /** lp_scratch3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch3:32; + }; + uint32_t val; +} lp_system_reg_lp_store3_reg_t; + +/** Type of lp_store4 register + * need_des + */ +typedef union { + struct { + /** lp_scratch4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch4:32; + }; + uint32_t val; +} lp_system_reg_lp_store4_reg_t; + +/** Type of lp_store5 register + * need_des + */ +typedef union { + struct { + /** lp_scratch5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch5:32; + }; + uint32_t val; +} lp_system_reg_lp_store5_reg_t; + +/** Type of lp_store6 register + * need_des + */ +typedef union { + struct { + /** lp_scratch6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch6:32; + }; + uint32_t val; +} lp_system_reg_lp_store6_reg_t; + +/** Type of lp_store7 register + * need_des + */ +typedef union { + struct { + /** lp_scratch7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch7:32; + }; + uint32_t val; +} lp_system_reg_lp_store7_reg_t; + +/** Type of lp_store8 register + * need_des + */ +typedef union { + struct { + /** lp_scratch8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch8:32; + }; + uint32_t val; +} lp_system_reg_lp_store8_reg_t; + +/** Type of lp_store9 register + * need_des + */ +typedef union { + struct { + /** lp_scratch9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch9:32; + }; + uint32_t val; +} lp_system_reg_lp_store9_reg_t; + +/** Type of lp_store10 register + * need_des + */ +typedef union { + struct { + /** lp_scratch10 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch10:32; + }; + uint32_t val; +} lp_system_reg_lp_store10_reg_t; + +/** Type of lp_store11 register + * need_des + */ +typedef union { + struct { + /** lp_scratch11 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch11:32; + }; + uint32_t val; +} lp_system_reg_lp_store11_reg_t; + +/** Type of lp_store12 register + * need_des + */ +typedef union { + struct { + /** lp_scratch12 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch12:32; + }; + uint32_t val; +} lp_system_reg_lp_store12_reg_t; + +/** Type of lp_store13 register + * need_des + */ +typedef union { + struct { + /** lp_scratch13 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch13:32; + }; + uint32_t val; +} lp_system_reg_lp_store13_reg_t; + +/** Type of lp_store14 register + * need_des + */ +typedef union { + struct { + /** lp_scratch14 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch14:32; + }; + uint32_t val; +} lp_system_reg_lp_store14_reg_t; + +/** Type of lp_store15 register + * need_des + */ +typedef union { + struct { + /** lp_scratch15 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_scratch15:32; + }; + uint32_t val; +} lp_system_reg_lp_store15_reg_t; + +/** Type of lp_probea_ctrl register + * need_des + */ +typedef union { + struct { + /** probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t probe_a_mod_sel:16; + /** probe_a_top_sel : R/W; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t probe_a_top_sel:8; + /** probe_l_sel : R/W; bitpos: [25:24]; default: 0; + * need_des + */ + uint32_t probe_l_sel:2; + /** probe_h_sel : R/W; bitpos: [27:26]; default: 0; + * need_des + */ + uint32_t probe_h_sel:2; + /** probe_global_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t probe_global_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_system_reg_lp_probea_ctrl_reg_t; + +/** Type of lp_probeb_ctrl register + * need_des + */ +typedef union { + struct { + /** probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t probe_b_mod_sel:16; + /** probe_b_top_sel : R/W; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t probe_b_top_sel:8; + /** probe_b_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t probe_b_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} lp_system_reg_lp_probeb_ctrl_reg_t; + +/** Type of lp_probe_out register + * need_des + */ +typedef union { + struct { + /** probe_top_out : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t probe_top_out:32; + }; + uint32_t val; +} lp_system_reg_lp_probe_out_reg_t; + +/** Type of f2s_apb_brg_cntl register + * need_des + */ +typedef union { + struct { + /** f2s_apb_postw_en : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t f2s_apb_postw_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_system_reg_f2s_apb_brg_cntl_reg_t; + +/** Type of usb_ctrl register + * need_des + */ +typedef union { + struct { + /** sw_hw_usb_phy_sel : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t sw_hw_usb_phy_sel:1; + /** sw_usb_phy_sel : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t sw_usb_phy_sel:1; + /** usbotg20_wakeup_clr : WT; bitpos: [2]; default: 0; + * clear usb wakeup to PMU. + */ + uint32_t usbotg20_wakeup_clr:1; + /** usbotg20_in_suspend : R/W; bitpos: [3]; default: 0; + * indicate usb otg2.0 is in suspend state. + */ + uint32_t usbotg20_in_suspend:1; + /** usbotg20_ls_mode : R/W; bitpos: [4]; default: 0; + * indicate current mode of usb otg2.0. + */ + uint32_t usbotg20_ls_mode:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_system_reg_usb_ctrl_reg_t; + +/** Type of ana_xpd_pad_group register + * need_des + */ +typedef union { + struct { + /** ana_reg_xpd_pad_group : R/W; bitpos: [7:0]; default: 255; + * Set 1 to power up pad group + */ + uint32_t ana_reg_xpd_pad_group:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_system_reg_ana_xpd_pad_group_reg_t; + +/** Type of lp_tcm_ram_rdn_eco_cs register + * need_des + */ +typedef union { + struct { + /** lp_tcm_ram_rdn_eco_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_tcm_ram_rdn_eco_en:1; + /** lp_tcm_ram_rdn_eco_result : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_tcm_ram_rdn_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t; + +/** Type of lp_tcm_ram_rdn_eco_low register + * need_des + */ +typedef union { + struct { + /** lp_tcm_ram_rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_tcm_ram_rdn_eco_low:32; + }; + uint32_t val; +} lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t; + +/** Type of lp_tcm_ram_rdn_eco_high register + * need_des + */ +typedef union { + struct { + /** lp_tcm_ram_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t lp_tcm_ram_rdn_eco_high:32; + }; + uint32_t val; +} lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t; + +/** Type of lp_tcm_rom_rdn_eco_cs register + * need_des + */ +typedef union { + struct { + /** lp_tcm_rom_rdn_eco_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_tcm_rom_rdn_eco_en:1; + /** lp_tcm_rom_rdn_eco_result : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_tcm_rom_rdn_eco_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t; + +/** Type of lp_tcm_rom_rdn_eco_low register + * need_des + */ +typedef union { + struct { + /** lp_tcm_rom_rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_tcm_rom_rdn_eco_low:32; + }; + uint32_t val; +} lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t; + +/** Type of lp_tcm_rom_rdn_eco_high register + * need_des + */ +typedef union { + struct { + /** lp_tcm_rom_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t lp_tcm_rom_rdn_eco_high:32; + }; + uint32_t val; +} lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t; + +/** Type of hp_root_clk_ctrl register + * need_des + */ +typedef union { + struct { + /** cpu_clk_en : R/W; bitpos: [0]; default: 1; + * clock gate enable for hp cpu root 400M clk + */ + uint32_t cpu_clk_en:1; + /** sys_clk_en : R/W; bitpos: [1]; default: 1; + * clock gate enable for hp sys root 480M clk + */ + uint32_t sys_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_system_reg_hp_root_clk_ctrl_reg_t; + +/** Type of lp_pmu_rdn_eco_low register + * need_des + */ +typedef union { + struct { + /** pmu_rdn_eco_low : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t pmu_rdn_eco_low:32; + }; + uint32_t val; +} lp_system_reg_lp_pmu_rdn_eco_low_reg_t; + +/** Type of lp_pmu_rdn_eco_high register + * need_des + */ +typedef union { + struct { + /** pmu_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t pmu_rdn_eco_high:32; + }; + uint32_t val; +} lp_system_reg_lp_pmu_rdn_eco_high_reg_t; + +/** Type of pad_comp0 register + * need_des + */ +typedef union { + struct { + /** dref_comp0 : R/W; bitpos: [2:0]; default: 0; + * pad comp dref + */ + uint32_t dref_comp0:3; + /** mode_comp0 : R/W; bitpos: [3]; default: 0; + * pad comp mode + */ + uint32_t mode_comp0:1; + /** xpd_comp0 : R/W; bitpos: [4]; default: 0; + * pad comp xpd + */ + uint32_t xpd_comp0:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_system_reg_pad_comp_reg_t; + +/** Type of backup_dma_cfg0 register + * need_des + */ +typedef union { + struct { + /** burst_limit_aon : R/W; bitpos: [4:0]; default: 10; + * need_des + */ + uint32_t burst_limit_aon:5; + /** read_interval_aon : R/W; bitpos: [11:5]; default: 10; + * need_des + */ + uint32_t read_interval_aon:7; + /** link_backup_tout_thres_aon : R/W; bitpos: [21:12]; default: 100; + * need_des + */ + uint32_t link_backup_tout_thres_aon:10; + /** link_tout_thres_aon : R/W; bitpos: [31:22]; default: 100; + * need_des + */ + uint32_t link_tout_thres_aon:10; + }; + uint32_t val; +} lp_system_reg_backup_dma_cfg0_reg_t; + +/** Type of backup_dma_cfg1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** aon_bypass : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_bypass:1; + }; + uint32_t val; +} lp_system_reg_backup_dma_cfg1_reg_t; + +/** Type of backup_dma_cfg2 register + * need_des + */ +typedef union { + struct { + /** link_addr_aon : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t link_addr_aon:32; + }; + uint32_t val; +} lp_system_reg_backup_dma_cfg2_reg_t; + +/** Type of boot_addr_hp_core1 register + * need_des + */ +typedef union { + struct { + /** boot_addr_hp_core1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t boot_addr_hp_core1:32; + }; + uint32_t val; +} lp_system_reg_boot_addr_hp_core1_reg_t; + +/** Type of hp_mem_aux_ctrl register + * need_des + */ +typedef union { + struct { + /** hp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t hp_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_system_reg_hp_mem_aux_ctrl_reg_t; + +/** Type of lp_mem_aux_ctrl register + * need_des + */ +typedef union { + struct { + /** lp_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t lp_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_system_reg_lp_mem_aux_ctrl_reg_t; + +/** Type of hp_rom_aux_ctrl register + * need_des + */ +typedef union { + struct { + /** hp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + * need_des + */ + uint32_t hp_rom_aux_ctrl:32; + }; + uint32_t val; +} lp_system_reg_hp_rom_aux_ctrl_reg_t; + +/** Type of lp_rom_aux_ctrl register + * need_des + */ +typedef union { + struct { + /** lp_rom_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + * need_des + */ + uint32_t lp_rom_aux_ctrl:32; + }; + uint32_t val; +} lp_system_reg_lp_rom_aux_ctrl_reg_t; + +/** Type of hp_por_rst_bypass_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_po_cnnt_rstn_bypass_ctrl : R/W; bitpos: [15:8]; default: 255; + * [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn + * [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn + * [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn + * [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn + * [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst + * [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst + * [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn + * [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn + */ + uint32_t hp_po_cnnt_rstn_bypass_ctrl:8; + uint32_t reserved_16:8; + /** hp_po_rstn_bypass_ctrl : R/W; bitpos: [31:24]; default: 255; + * [31] 1'b1: po_rstn bypass sys_sw_rstn + * [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn + * [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn + * [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn + * [27] 1'b1: po_rstn bypass usb_jtag_chip_rst + * [26] 1'b1: po_rstn bypass usb_uart_chip_rst + * [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn + * [24] 1'b1: po_rstn bypass efuse_err_rstn + */ + uint32_t hp_po_rstn_bypass_ctrl:8; + }; + uint32_t val; +} lp_system_reg_hp_por_rst_bypass_ctrl_reg_t; + +/** Type of lp_core_ahb_timeout register + * need_des + */ +typedef union { + struct { + /** lp_core_ahb_timeout_en : R/W; bitpos: [0]; default: 1; + * set this field to 1 to enable lp core ahb timeout handle + */ + uint32_t lp_core_ahb_timeout_en:1; + /** lp_core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535; + * This field used to set lp core ahb bus timeout threshold + */ + uint32_t lp_core_ahb_timeout_thres:16; + /** lp2hp_ahb_timeout_en : R/W; bitpos: [17]; default: 1; + * set this field to 1 to enable lp2hp ahb timeout handle + */ + uint32_t lp2hp_ahb_timeout_en:1; + /** lp2hp_ahb_timeout_thres : R/W; bitpos: [22:18]; default: 31; + * This field used to set lp2hp ahb bus timeout threshold + */ + uint32_t lp2hp_ahb_timeout_thres:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_system_reg_lp_core_ahb_timeout_reg_t; + +/** Type of lp_core_ibus_timeout register + * need_des + */ +typedef union { + struct { + /** lp_core_ibus_timeout_en : R/W; bitpos: [0]; default: 1; + * set this field to 1 to enable lp core ibus timeout handle + */ + uint32_t lp_core_ibus_timeout_en:1; + /** lp_core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535; + * This field used to set lp core ibus timeout threshold + */ + uint32_t lp_core_ibus_timeout_thres:16; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_system_reg_lp_core_ibus_timeout_reg_t; + +/** Type of lp_core_dbus_timeout register + * need_des + */ +typedef union { + struct { + /** lp_core_dbus_timeout_en : R/W; bitpos: [0]; default: 1; + * set this field to 1 to enable lp core dbus timeout handle + */ + uint32_t lp_core_dbus_timeout_en:1; + /** lp_core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535; + * This field used to set lp core dbus timeout threshold + */ + uint32_t lp_core_dbus_timeout_thres:16; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_system_reg_lp_core_dbus_timeout_reg_t; + + +/** Group: status_register */ +/** Type of lp_addrhole_addr register + * need_des + */ +typedef union { + struct { + /** lp_addrhole_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_addrhole_addr:32; + }; + uint32_t val; +} lp_system_reg_lp_addrhole_addr_reg_t; + +/** Type of lp_addrhole_info register + * need_des + */ +typedef union { + struct { + /** lp_addrhole_id : RO; bitpos: [4:0]; default: 0; + * master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: + * regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha + * tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. + */ + uint32_t lp_addrhole_id:5; + /** lp_addrhole_wr : RO; bitpos: [5]; default: 0; + * 1:write trans, 0: read trans. + */ + uint32_t lp_addrhole_wr:1; + /** lp_addrhole_secure : RO; bitpos: [6]; default: 0; + * 1: illegal address access, 0: access without permission + */ + uint32_t lp_addrhole_secure:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_system_reg_lp_addrhole_info_reg_t; + +/** Type of lp_cpu_dbg_pc register + * need_des + */ +typedef union { + struct { + /** lp_cpu_dbg_pc : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_dbg_pc:32; + }; + uint32_t val; +} lp_system_reg_lp_cpu_dbg_pc_reg_t; + +/** Type of lp_cpu_exc_pc register + * need_des + */ +typedef union { + struct { + /** lp_cpu_exc_pc : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_pc:32; + }; + uint32_t val; +} lp_system_reg_lp_cpu_exc_pc_reg_t; + +/** Type of idbus_addrhole_addr register + * need_des + */ +typedef union { + struct { + /** idbus_addrhole_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t idbus_addrhole_addr:32; + }; + uint32_t val; +} lp_system_reg_idbus_addrhole_addr_reg_t; + +/** Type of idbus_addrhole_info register + * need_des + */ +typedef union { + struct { + /** idbus_addrhole_id : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t idbus_addrhole_id:5; + /** idbus_addrhole_wr : RO; bitpos: [5]; default: 0; + * need_des + */ + uint32_t idbus_addrhole_wr:1; + /** idbus_addrhole_secure : RO; bitpos: [6]; default: 0; + * need_des + */ + uint32_t idbus_addrhole_secure:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_system_reg_idbus_addrhole_info_reg_t; + +/** Type of rng_data register + * rng data register + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * result of rng output + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lp_system_reg_rng_data_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * raw interrupt register + */ +typedef union { + struct { + /** lp_addrhole_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp + * matrix default slave) + */ + uint32_t lp_addrhole_int_raw:1; + /** idbus_addrhole_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + */ + uint32_t idbus_addrhole_int_raw:1; + /** lp_core_ahb_timeout_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * the raw interrupt status of lp core ahb bus timeout + */ + uint32_t lp_core_ahb_timeout_int_raw:1; + /** lp_core_ibus_timeout_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * the raw interrupt status of lp core ibus timeout + */ + uint32_t lp_core_ibus_timeout_int_raw:1; + /** lp_core_dbus_timeout_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * the raw interrupt status of lp core dbus timeout + */ + uint32_t lp_core_dbus_timeout_int_raw:1; + /** etm_task_ulp_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * the raw interrupt status of etm task ulp + */ + uint32_t etm_task_ulp_int_raw:1; + /** slow_clk_tick_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * the raw interrupt status of slow_clk_tick + */ + uint32_t slow_clk_tick_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_system_reg_int_raw_reg_t; + +/** Type of int_st register + * masked interrupt register + */ +typedef union { + struct { + /** lp_addrhole_int_st : RO; bitpos: [0]; default: 0; + * the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp + * matrix default slave) + */ + uint32_t lp_addrhole_int_st:1; + /** idbus_addrhole_int_st : RO; bitpos: [1]; default: 0; + * the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + */ + uint32_t idbus_addrhole_int_st:1; + /** lp_core_ahb_timeout_int_st : RO; bitpos: [2]; default: 0; + * the masked interrupt status of lp core ahb bus timeout + */ + uint32_t lp_core_ahb_timeout_int_st:1; + /** lp_core_ibus_timeout_int_st : RO; bitpos: [3]; default: 0; + * the masked interrupt status of lp core ibus timeout + */ + uint32_t lp_core_ibus_timeout_int_st:1; + /** lp_core_dbus_timeout_int_st : RO; bitpos: [4]; default: 0; + * the masked interrupt status of lp core dbus timeout + */ + uint32_t lp_core_dbus_timeout_int_st:1; + /** etm_task_ulp_int_st : RO; bitpos: [5]; default: 0; + * the masked interrupt status of etm task ulp + */ + uint32_t etm_task_ulp_int_st:1; + /** slow_clk_tick_int_st : RO; bitpos: [6]; default: 0; + * the masked interrupt status of slow_clk_tick + */ + uint32_t slow_clk_tick_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_system_reg_int_st_reg_t; + +/** Type of int_ena register + * masked interrupt register + */ +typedef union { + struct { + /** lp_addrhole_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable lp addrhole int + */ + uint32_t lp_addrhole_int_ena:1; + /** idbus_addrhole_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable idbus addrhole int + */ + uint32_t idbus_addrhole_int_ena:1; + /** lp_core_ahb_timeout_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to enable lp_core_ahb_timeout int + */ + uint32_t lp_core_ahb_timeout_int_ena:1; + /** lp_core_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to enable lp_core_ibus_timeout int + */ + uint32_t lp_core_ibus_timeout_int_ena:1; + /** lp_core_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to enable lp_core_dbus_timeout int + */ + uint32_t lp_core_dbus_timeout_int_ena:1; + /** etm_task_ulp_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to enable etm task ulp int + */ + uint32_t etm_task_ulp_int_ena:1; + /** slow_clk_tick_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable slow_clk_tick int + */ + uint32_t slow_clk_tick_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_system_reg_int_ena_reg_t; + +/** Type of int_clr register + * interrupt clear register + */ +typedef union { + struct { + /** lp_addrhole_int_clr : WT; bitpos: [0]; default: 0; + * write 1 to clear lp addrhole int + */ + uint32_t lp_addrhole_int_clr:1; + /** idbus_addrhole_int_clr : WT; bitpos: [1]; default: 0; + * write 1 to clear idbus addrhole int + */ + uint32_t idbus_addrhole_int_clr:1; + /** lp_core_ahb_timeout_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear lp_core_ahb_timeout int + */ + uint32_t lp_core_ahb_timeout_int_clr:1; + /** lp_core_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear lp_core_ibus_timeout int + */ + uint32_t lp_core_ibus_timeout_int_clr:1; + /** lp_core_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear lp_core_dbus_timeout int + */ + uint32_t lp_core_dbus_timeout_int_clr:1; + /** etm_task_ulp_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear etm tasl ulp int + */ + uint32_t etm_task_ulp_int_clr:1; + /** slow_clk_tick_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear slow_clk_tick int + */ + uint32_t slow_clk_tick_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_system_reg_int_clr_reg_t; + + +/** Group: control registers */ +/** Type of lp_core_err_resp_dis register + * need_des + */ +typedef union { + struct { + /** lp_core_err_resp_dis : R/W; bitpos: [2:0]; default: 0; + * Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to + * disable ahb err resp. + */ + uint32_t lp_core_err_resp_dis:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_system_reg_lp_core_err_resp_dis_reg_t; + +/** Type of rng_cfg register + * rng cfg register + */ +typedef union { + struct { + /** rng_timer_en : R/W; bitpos: [0]; default: 1; + * enable rng timer + */ + uint32_t rng_timer_en:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 1; + * configure ng timer pscale + */ + uint32_t rng_timer_pscale:8; + /** rng_sar_enable : R/W; bitpos: [9]; default: 0; + * enable rng_saradc + */ + uint32_t rng_sar_enable:1; + uint32_t reserved_10:6; + /** rng_sar_data : RO; bitpos: [28:16]; default: 0; + * debug rng sar sample cnt + */ + uint32_t rng_sar_data:13; + uint32_t reserved_29:3; + }; + uint32_t val; +} lp_system_reg_rng_cfg_reg_t; + +/** Type of pad_rtc_hold_ctrl0 register + * enable pad hold ctrl + */ +typedef union { + struct { + /** pad_rtc_hold_ctrl0 : R/W; bitpos: [31:0]; default: 0; + * Set 1 to hold pad 0-31 status + */ + uint32_t pad_rtc_hold_ctrl0:32; + }; + uint32_t val; +} lp_system_reg_pad_rtc_hold_ctrl0_reg_t; + +/** Type of pad_rtc_hold_ctrl1 register + * enable pad hold ctrl + */ +typedef union { + struct { + /** pad_rtc_hold_ctrl1 : R/W; bitpos: [24:0]; default: 0; + * Set 1 to hold pad 32-56 status + */ + uint32_t pad_rtc_hold_ctrl1:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} lp_system_reg_pad_rtc_hold_ctrl1_reg_t; + +/** Type of ded_pad_rtc_hold_ctrl register + * enable pad hold ctrl + */ +typedef union { + struct { + /** ded_pad_rtc_hold_ctrl : R/W; bitpos: [25:0]; default: 0; + * Set bit0-5 to hold flash pad status. Set bit6-25 to hold psram pad status. + */ + uint32_t ded_pad_rtc_hold_ctrl:26; + uint32_t reserved_26:6; + }; + uint32_t val; +} lp_system_reg_ded_pad_rtc_hold_ctrl_reg_t; + +/** Type of discharge register + * pufmem / ldo flash power discharge control + */ +typedef union { + struct { + /** ldo_flash_discharge : R/W; bitpos: [0]; default: 0; + * Set this bit to discharge ldo flash. + */ + uint32_t ldo_flash_discharge:1; + /** lp_puf_mem_iso_en : R/W; bitpos: [1]; default: 0; + * Set this bit to discharge lp puf mem. + */ + uint32_t lp_puf_mem_iso_en:1; + /** lp_puf_mem_xpd : R/W; bitpos: [2]; default: 1; + * Set this bit to discharge lp puf mem. + */ + uint32_t lp_puf_mem_xpd:1; + /** lp_puf_mem_discharge : R/W; bitpos: [3]; default: 0; + * Set this bit to discharge lp puf mem. + */ + uint32_t lp_puf_mem_discharge:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_system_reg_discharge_reg_t; + +/** Type of hp_usb_otghs_phy_ctrl register + * Usb otg2.0 PHY control register + */ +typedef union { + struct { + /** hp_utmiotg_idpullup : R/W; bitpos: [0]; default: 1; + * Set this bit to pull up USB OTG2.0 PHY id + */ + uint32_t hp_utmiotg_idpullup:1; + /** hp_utmiotg_dppulldown : R/W; bitpos: [1]; default: 1; + * Set this bit to pull down USB OTG2.0 PHY dp + */ + uint32_t hp_utmiotg_dppulldown:1; + /** hp_utmiotg_dmpulldown : R/W; bitpos: [2]; default: 1; + * Set this bit to pull down USB OTG2.0 PHY dm + */ + uint32_t hp_utmiotg_dmpulldown:1; + /** hp_utmisrp_chrgvbus : R/W; bitpos: [3]; default: 0; + * Set this bit to charge USB OTG2.0 PHY vbus + */ + uint32_t hp_utmisrp_chrgvbus:1; + /** hp_utmisrp_dischrgvbus : R/W; bitpos: [4]; default: 0; + * Set this bit to discharge USB OTG2.0 PHY vbus + */ + uint32_t hp_utmisrp_dischrgvbus:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_system_reg_hp_usb_otghs_phy_ctrl_reg_t; + + +typedef struct { + volatile lp_system_reg_lp_sys_ver_date_reg_t lp_sys_ver_date; + volatile lp_system_reg_clk_sel_ctrl_reg_t clk_sel_ctrl; + volatile lp_system_reg_sys_ctrl_reg_t sys_ctrl; + volatile lp_system_reg_lp_clk_ctrl_reg_t lp_clk_ctrl; + volatile lp_system_reg_lp_rst_ctrl_reg_t lp_rst_ctrl; + uint32_t reserved_014; + volatile lp_system_reg_lp_core_boot_addr_reg_t lp_core_boot_addr; + volatile lp_system_reg_ext_wakeup1_reg_t ext_wakeup1; + volatile lp_system_reg_ext_wakeup1_status_reg_t ext_wakeup1_status; + volatile lp_system_reg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl; + volatile lp_system_reg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg; + volatile lp_system_reg_lp_store0_reg_t lp_store0; + volatile lp_system_reg_lp_store1_reg_t lp_store1; + volatile lp_system_reg_lp_store2_reg_t lp_store2; + volatile lp_system_reg_lp_store3_reg_t lp_store3; + volatile lp_system_reg_lp_store4_reg_t lp_store4; + volatile lp_system_reg_lp_store5_reg_t lp_store5; + volatile lp_system_reg_lp_store6_reg_t lp_store6; + volatile lp_system_reg_lp_store7_reg_t lp_store7; + volatile lp_system_reg_lp_store8_reg_t lp_store8; + volatile lp_system_reg_lp_store9_reg_t lp_store9; + volatile lp_system_reg_lp_store10_reg_t lp_store10; + volatile lp_system_reg_lp_store11_reg_t lp_store11; + volatile lp_system_reg_lp_store12_reg_t lp_store12; + volatile lp_system_reg_lp_store13_reg_t lp_store13; + volatile lp_system_reg_lp_store14_reg_t lp_store14; + volatile lp_system_reg_lp_store15_reg_t lp_store15; + volatile lp_system_reg_lp_probea_ctrl_reg_t lp_probea_ctrl; + volatile lp_system_reg_lp_probeb_ctrl_reg_t lp_probeb_ctrl; + volatile lp_system_reg_lp_probe_out_reg_t lp_probe_out; + uint32_t reserved_078[9]; + volatile lp_system_reg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl; + uint32_t reserved_0a0[24]; + volatile lp_system_reg_usb_ctrl_reg_t usb_ctrl; + uint32_t reserved_104[2]; + volatile lp_system_reg_ana_xpd_pad_group_reg_t ana_xpd_pad_group; + volatile lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs; + volatile lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low; + volatile lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high; + volatile lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs; + volatile lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low; + volatile lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high; + uint32_t reserved_128[2]; + volatile lp_system_reg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl; + uint32_t reserved_134; + volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low; + volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high; + uint32_t reserved_140[2]; + volatile lp_system_reg_pad_comp_reg_t pad_comp[2]; + uint32_t reserved_150; + volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0; + volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1; + volatile lp_system_reg_backup_dma_cfg2_reg_t backup_dma_cfg2; + uint32_t reserved_160; + volatile lp_system_reg_boot_addr_hp_core1_reg_t boot_addr_hp_core1; + volatile lp_system_reg_lp_addrhole_addr_reg_t lp_addrhole_addr; + volatile lp_system_reg_lp_addrhole_info_reg_t lp_addrhole_info; + volatile lp_system_reg_int_raw_reg_t int_raw; + volatile lp_system_reg_int_st_reg_t int_st; + volatile lp_system_reg_int_ena_reg_t int_ena; + volatile lp_system_reg_int_clr_reg_t int_clr; + volatile lp_system_reg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl; + volatile lp_system_reg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl; + volatile lp_system_reg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl; + volatile lp_system_reg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl; + volatile lp_system_reg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc; + volatile lp_system_reg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc; + volatile lp_system_reg_idbus_addrhole_addr_reg_t idbus_addrhole_addr; + volatile lp_system_reg_idbus_addrhole_info_reg_t idbus_addrhole_info; + volatile lp_system_reg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl; + volatile lp_system_reg_rng_data_reg_t rng_data; + uint32_t reserved_1a8[2]; + volatile lp_system_reg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout; + volatile lp_system_reg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout; + volatile lp_system_reg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout; + volatile lp_system_reg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis; + volatile lp_system_reg_rng_cfg_reg_t rng_cfg; + volatile lp_system_reg_pad_rtc_hold_ctrl0_reg_t pad_rtc_hold_ctrl0; + volatile lp_system_reg_pad_rtc_hold_ctrl1_reg_t pad_rtc_hold_ctrl1; + volatile lp_system_reg_ded_pad_rtc_hold_ctrl_reg_t ded_pad_rtc_hold_ctrl; + uint32_t reserved_1d0[12]; + volatile lp_system_reg_discharge_reg_t discharge; + volatile lp_system_reg_hp_usb_otghs_phy_ctrl_reg_t hp_usb_otghs_phy_ctrl; +} lp_system_reg_dev_t; + +extern lp_system_reg_dev_t LP_SYS; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_system_reg_dev_t) == 0x208, "Invalid size of lp_system_reg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_eco5_struct.h new file mode 100644 index 0000000000..ad41a52b3f --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_eco5_struct.h @@ -0,0 +1,363 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of tar0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of tar0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of tar1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low1:32; + }; + uint32_t val; +} lp_timer_tar1_low_reg_t; + +/** Type of tar1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high1:16; + uint32_t reserved_16:15; + /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en1:1; + }; + uint32_t val; +} lp_timer_tar1_high_reg_t; + +/** Type of update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** main_timer_update : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t main_timer_update:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of main_buf0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of main_buf0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of main_buf1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of main_buf1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_raw:1; + /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_st:1; + /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_ena:1; + /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_clr:1; + /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t tar0_low; + volatile lp_timer_tar0_high_reg_t tar0_high; + volatile lp_timer_tar1_low_reg_t tar1_low; + volatile lp_timer_tar1_high_reg_t tar1_high; + volatile lp_timer_update_reg_t update; + volatile lp_timer_main_buf0_low_reg_t main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t main_buf1_high; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_reg.h new file mode 100644 index 0000000000..683e3596ac --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_reg.h @@ -0,0 +1,342 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RTC_TIMER_TAR0_LOW_REG register + * need_des + */ +#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0) +/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** RTC_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4) +/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S) +#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** RTC_TIMER_TAR1_LOW_REG register + * need_des + */ +#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8) +/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** RTC_TIMER_TAR1_HIGH_REG register + * need_des + */ +#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc) +/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S) +#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** RTC_TIMER_UPDATE_REG register + * need_des + */ +#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10) +/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S) +#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28 +/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S) +#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S) +#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** RTC_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14) +/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** RTC_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18) +/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** RTC_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c) +/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** RTC_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20) +/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** RTC_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24) +/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** RTC_TIMER_INT_RAW_REG register + * need_des + */ +#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28) +/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_OVERFLOW_RAW (BIT(30)) +#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S) +#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U +#define RTC_TIMER_OVERFLOW_RAW_S 30 +/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S) +#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** RTC_TIMER_INT_ST_REG register + * need_des + */ +#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c) +/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_OVERFLOW_ST (BIT(30)) +#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S) +#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U +#define RTC_TIMER_OVERFLOW_ST_S 30 +/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S) +#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** RTC_TIMER_INT_ENA_REG register + * need_des + */ +#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30) +/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_OVERFLOW_ENA (BIT(30)) +#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S) +#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U +#define RTC_TIMER_OVERFLOW_ENA_S 30 +/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S) +#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** RTC_TIMER_INT_CLR_REG register + * need_des + */ +#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34) +/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_OVERFLOW_CLR (BIT(30)) +#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S) +#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U +#define RTC_TIMER_OVERFLOW_CLR_S 30 +/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S) +#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** RTC_TIMER_LP_INT_RAW_REG register + * need_des + */ +#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38) +/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** RTC_TIMER_LP_INT_ST_REG register + * need_des + */ +#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c) +/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** RTC_TIMER_LP_INT_ENA_REG register + * need_des + */ +#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40) +/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** RTC_TIMER_LP_INT_CLR_REG register + * need_des + */ +#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44) +/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** RTC_TIMER_DATE_REG register + * need_des + */ +#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc) +/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ +#define RTC_TIMER_DATE 0x7FFFFFFFU +#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S) +#define RTC_TIMER_DATE_V 0x7FFFFFFFU +#define RTC_TIMER_DATE_S 0 +/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define RTC_TIMER_CLK_EN (BIT(31)) +#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S) +#define RTC_TIMER_CLK_EN_V 0x00000001U +#define RTC_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_struct.h new file mode 100644 index 0000000000..09dd169f13 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_timer_struct.h @@ -0,0 +1,274 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + union { + struct { + uint32_t target_lo: 32; + }; + uint32_t val; + } lo; + union { + struct { + uint32_t target_hi: 16; + uint32_t reserved0: 15; + uint32_t enable : 1; + }; + uint32_t val; + } hi; +} lp_timer_target_reg_t; + +/** Type of update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** main_timer_update : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t main_timer_update:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +typedef struct { + union { + struct { + uint32_t counter_lo: 32; + }; + uint32_t val; + } lo; + union { + struct { + uint32_t counter_hi: 16; + uint32_t reserved0 : 16; + }; + uint32_t val; + } hi; +} lp_timer_counter_reg_t; + + +/** Type of main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_raw:1; + /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_st:1; + /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_ena:1; + /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_clr:1; + /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_target_reg_t target[2]; + volatile lp_timer_update_reg_t update; + volatile lp_timer_counter_reg_t counter[2]; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_uart_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_uart_reg.h new file mode 100644 index 0000000000..2a494b5d0c --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_uart_reg.h @@ -0,0 +1,1339 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_UART_FIFO_REG register + * FIFO data register + */ +#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0) +/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define LP_UART_RXFIFO_RD_BYTE 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_M (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S) +#define LP_UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_S 0 + +/** LP_UART_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4) +/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define LP_UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_RAW_M (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S) +#define LP_UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_RAW_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define LP_UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_M (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define LP_UART_PARITY_ERR_INT_RAW (BIT(2)) +#define LP_UART_PARITY_ERR_INT_RAW_M (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S) +#define LP_UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_RAW_S 2 +/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define LP_UART_FRM_ERR_INT_RAW (BIT(3)) +#define LP_UART_FRM_ERR_INT_RAW_M (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S) +#define LP_UART_FRM_ERR_INT_RAW_V 0x00000001U +#define LP_UART_FRM_ERR_INT_RAW_S 3 +/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define LP_UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_RAW_M (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S) +#define LP_UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_RAW_S 4 +/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define LP_UART_DSR_CHG_INT_RAW (BIT(5)) +#define LP_UART_DSR_CHG_INT_RAW_M (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S) +#define LP_UART_DSR_CHG_INT_RAW_V 0x00000001U +#define LP_UART_DSR_CHG_INT_RAW_S 5 +/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define LP_UART_CTS_CHG_INT_RAW (BIT(6)) +#define LP_UART_CTS_CHG_INT_RAW_M (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S) +#define LP_UART_CTS_CHG_INT_RAW_V 0x00000001U +#define LP_UART_CTS_CHG_INT_RAW_S 6 +/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define LP_UART_BRK_DET_INT_RAW (BIT(7)) +#define LP_UART_BRK_DET_INT_RAW_M (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S) +#define LP_UART_BRK_DET_INT_RAW_V 0x00000001U +#define LP_UART_BRK_DET_INT_RAW_S 7 +/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define LP_UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_RAW_M (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S) +#define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 +/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XON_INT_RAW (BIT(9)) +#define LP_UART_SW_XON_INT_RAW_M (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S) +#define LP_UART_SW_XON_INT_RAW_V 0x00000001U +#define LP_UART_SW_XON_INT_RAW_S 9 +/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XOFF_INT_RAW (BIT(10)) +#define LP_UART_SW_XOFF_INT_RAW_M (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S) +#define LP_UART_SW_XOFF_INT_RAW_V 0x00000001U +#define LP_UART_SW_XOFF_INT_RAW_S 10 +/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define LP_UART_GLITCH_DET_INT_RAW (BIT(11)) +#define LP_UART_GLITCH_DET_INT_RAW_M (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S) +#define LP_UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_RAW_S 11 +/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define LP_UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_RAW_M (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_RAW_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define LP_UART_TX_DONE_INT_RAW (BIT(14)) +#define LP_UART_TX_DONE_INT_RAW_M (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S) +#define LP_UART_TX_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_DONE_INT_RAW_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define LP_UART_WAKEUP_INT_RAW (BIT(19)) +#define LP_UART_WAKEUP_INT_RAW_M (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S) +#define LP_UART_WAKEUP_INT_RAW_V 0x00000001U +#define LP_UART_WAKEUP_INT_RAW_S 19 + +/** LP_UART_INT_ST_REG register + * Masked interrupt status + */ +#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8) +/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ST_M (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S) +#define LP_UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ST_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ST_M (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S) +#define LP_UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ST_S 1 +/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define LP_UART_PARITY_ERR_INT_ST (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ST_M (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S) +#define LP_UART_PARITY_ERR_INT_ST_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ST_S 2 +/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define LP_UART_FRM_ERR_INT_ST (BIT(3)) +#define LP_UART_FRM_ERR_INT_ST_M (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S) +#define LP_UART_FRM_ERR_INT_ST_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ST_S 3 +/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ST_M (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S) +#define LP_UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ST_S 4 +/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define LP_UART_DSR_CHG_INT_ST (BIT(5)) +#define LP_UART_DSR_CHG_INT_ST_M (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S) +#define LP_UART_DSR_CHG_INT_ST_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ST_S 5 +/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define LP_UART_CTS_CHG_INT_ST (BIT(6)) +#define LP_UART_CTS_CHG_INT_ST_M (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S) +#define LP_UART_CTS_CHG_INT_ST_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ST_S 6 +/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define LP_UART_BRK_DET_INT_ST (BIT(7)) +#define LP_UART_BRK_DET_INT_ST_M (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S) +#define LP_UART_BRK_DET_INT_ST_V 0x00000001U +#define LP_UART_BRK_DET_INT_ST_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ST_M (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S) +#define LP_UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ST_S 8 +/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define LP_UART_SW_XON_INT_ST (BIT(9)) +#define LP_UART_SW_XON_INT_ST_M (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S) +#define LP_UART_SW_XON_INT_ST_V 0x00000001U +#define LP_UART_SW_XON_INT_ST_S 9 +/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define LP_UART_SW_XOFF_INT_ST (BIT(10)) +#define LP_UART_SW_XOFF_INT_ST_M (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S) +#define LP_UART_SW_XOFF_INT_ST_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ST_S 10 +/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define LP_UART_GLITCH_DET_INT_ST (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ST_M (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S) +#define LP_UART_GLITCH_DET_INT_ST_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ST_S 11 +/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define LP_UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ST_M (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S) +#define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ST_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define LP_UART_TX_DONE_INT_ST (BIT(14)) +#define LP_UART_TX_DONE_INT_ST_M (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S) +#define LP_UART_TX_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_DONE_INT_ST_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define LP_UART_WAKEUP_INT_ST (BIT(19)) +#define LP_UART_WAKEUP_INT_ST_M (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S) +#define LP_UART_WAKEUP_INT_ST_V 0x00000001U +#define LP_UART_WAKEUP_INT_ST_S 19 + +/** LP_UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc) +/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define LP_UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ENA_M (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S) +#define LP_UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ENA_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_M (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define LP_UART_PARITY_ERR_INT_ENA (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ENA_M (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S) +#define LP_UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ENA_S 2 +/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define LP_UART_FRM_ERR_INT_ENA (BIT(3)) +#define LP_UART_FRM_ERR_INT_ENA_M (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S) +#define LP_UART_FRM_ERR_INT_ENA_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ENA_S 3 +/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define LP_UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ENA_M (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S) +#define LP_UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ENA_S 4 +/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define LP_UART_DSR_CHG_INT_ENA (BIT(5)) +#define LP_UART_DSR_CHG_INT_ENA_M (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S) +#define LP_UART_DSR_CHG_INT_ENA_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ENA_S 5 +/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define LP_UART_CTS_CHG_INT_ENA (BIT(6)) +#define LP_UART_CTS_CHG_INT_ENA_M (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S) +#define LP_UART_CTS_CHG_INT_ENA_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ENA_S 6 +/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define LP_UART_BRK_DET_INT_ENA (BIT(7)) +#define LP_UART_BRK_DET_INT_ENA_M (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S) +#define LP_UART_BRK_DET_INT_ENA_V 0x00000001U +#define LP_UART_BRK_DET_INT_ENA_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define LP_UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ENA_M (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S) +#define LP_UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ENA_S 8 +/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define LP_UART_SW_XON_INT_ENA (BIT(9)) +#define LP_UART_SW_XON_INT_ENA_M (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S) +#define LP_UART_SW_XON_INT_ENA_V 0x00000001U +#define LP_UART_SW_XON_INT_ENA_S 9 +/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define LP_UART_SW_XOFF_INT_ENA (BIT(10)) +#define LP_UART_SW_XOFF_INT_ENA_M (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S) +#define LP_UART_SW_XOFF_INT_ENA_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ENA_S 10 +/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define LP_UART_GLITCH_DET_INT_ENA (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ENA_M (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S) +#define LP_UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ENA_S 11 +/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define LP_UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ENA_M (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ENA_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define LP_UART_TX_DONE_INT_ENA (BIT(14)) +#define LP_UART_TX_DONE_INT_ENA_M (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S) +#define LP_UART_TX_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_DONE_INT_ENA_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define LP_UART_WAKEUP_INT_ENA (BIT(19)) +#define LP_UART_WAKEUP_INT_ENA_M (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S) +#define LP_UART_WAKEUP_INT_ENA_V 0x00000001U +#define LP_UART_WAKEUP_INT_ENA_S 19 + +/** LP_UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10) +/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define LP_UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_CLR_M (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S) +#define LP_UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_CLR_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define LP_UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_M (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define LP_UART_PARITY_ERR_INT_CLR (BIT(2)) +#define LP_UART_PARITY_ERR_INT_CLR_M (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S) +#define LP_UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_CLR_S 2 +/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define LP_UART_FRM_ERR_INT_CLR (BIT(3)) +#define LP_UART_FRM_ERR_INT_CLR_M (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S) +#define LP_UART_FRM_ERR_INT_CLR_V 0x00000001U +#define LP_UART_FRM_ERR_INT_CLR_S 3 +/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define LP_UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_CLR_M (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S) +#define LP_UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_CLR_S 4 +/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define LP_UART_DSR_CHG_INT_CLR (BIT(5)) +#define LP_UART_DSR_CHG_INT_CLR_M (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S) +#define LP_UART_DSR_CHG_INT_CLR_V 0x00000001U +#define LP_UART_DSR_CHG_INT_CLR_S 5 +/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define LP_UART_CTS_CHG_INT_CLR (BIT(6)) +#define LP_UART_CTS_CHG_INT_CLR_M (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S) +#define LP_UART_CTS_CHG_INT_CLR_V 0x00000001U +#define LP_UART_CTS_CHG_INT_CLR_S 6 +/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define LP_UART_BRK_DET_INT_CLR (BIT(7)) +#define LP_UART_BRK_DET_INT_CLR_M (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S) +#define LP_UART_BRK_DET_INT_CLR_V 0x00000001U +#define LP_UART_BRK_DET_INT_CLR_S 7 +/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define LP_UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_CLR_M (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S) +#define LP_UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_CLR_S 8 +/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define LP_UART_SW_XON_INT_CLR (BIT(9)) +#define LP_UART_SW_XON_INT_CLR_M (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S) +#define LP_UART_SW_XON_INT_CLR_V 0x00000001U +#define LP_UART_SW_XON_INT_CLR_S 9 +/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define LP_UART_SW_XOFF_INT_CLR (BIT(10)) +#define LP_UART_SW_XOFF_INT_CLR_M (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S) +#define LP_UART_SW_XOFF_INT_CLR_V 0x00000001U +#define LP_UART_SW_XOFF_INT_CLR_S 10 +/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define LP_UART_GLITCH_DET_INT_CLR (BIT(11)) +#define LP_UART_GLITCH_DET_INT_CLR_M (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S) +#define LP_UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_CLR_S 11 +/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define LP_UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_CLR_M (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_CLR_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define LP_UART_TX_DONE_INT_CLR (BIT(14)) +#define LP_UART_TX_DONE_INT_CLR_M (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S) +#define LP_UART_TX_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_DONE_INT_CLR_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define LP_UART_WAKEUP_INT_CLR (BIT(19)) +#define LP_UART_WAKEUP_INT_CLR_M (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S) +#define LP_UART_WAKEUP_INT_CLR_V 0x00000001U +#define LP_UART_WAKEUP_INT_CLR_S 19 + +/** LP_UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14) +/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define LP_UART_CLKDIV 0x00000FFFU +#define LP_UART_CLKDIV_M (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S) +#define LP_UART_CLKDIV_V 0x00000FFFU +#define LP_UART_CLKDIV_S 0 +/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define LP_UART_CLKDIV_FRAG 0x0000000FU +#define LP_UART_CLKDIV_FRAG_M (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S) +#define LP_UART_CLKDIV_FRAG_V 0x0000000FU +#define LP_UART_CLKDIV_FRAG_S 20 + +/** LP_UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18) +/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define LP_UART_GLITCH_FILT 0x000000FFU +#define LP_UART_GLITCH_FILT_M (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S) +#define LP_UART_GLITCH_FILT_V 0x000000FFU +#define LP_UART_GLITCH_FILT_S 0 +/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define LP_UART_GLITCH_FILT_EN (BIT(8)) +#define LP_UART_GLITCH_FILT_EN_M (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S) +#define LP_UART_GLITCH_FILT_EN_V 0x00000001U +#define LP_UART_GLITCH_FILT_EN_S 8 + +/** LP_UART_STATUS_REG register + * UART status register + */ +#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c) +/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define LP_UART_RXFIFO_CNT 0x0000001FU +#define LP_UART_RXFIFO_CNT_M (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S) +#define LP_UART_RXFIFO_CNT_V 0x0000001FU +#define LP_UART_RXFIFO_CNT_S 3 +/** LP_UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define LP_UART_DSRN (BIT(13)) +#define LP_UART_DSRN_M (LP_UART_DSRN_V << LP_UART_DSRN_S) +#define LP_UART_DSRN_V 0x00000001U +#define LP_UART_DSRN_S 13 +/** LP_UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define LP_UART_CTSN (BIT(14)) +#define LP_UART_CTSN_M (LP_UART_CTSN_V << LP_UART_CTSN_S) +#define LP_UART_CTSN_V 0x00000001U +#define LP_UART_CTSN_S 14 +/** LP_UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define LP_UART_RXD (BIT(15)) +#define LP_UART_RXD_M (LP_UART_RXD_V << LP_UART_RXD_S) +#define LP_UART_RXD_V 0x00000001U +#define LP_UART_RXD_S 15 +/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define LP_UART_TXFIFO_CNT 0x0000001FU +#define LP_UART_TXFIFO_CNT_M (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S) +#define LP_UART_TXFIFO_CNT_V 0x0000001FU +#define LP_UART_TXFIFO_CNT_S 19 +/** LP_UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define LP_UART_DTRN (BIT(29)) +#define LP_UART_DTRN_M (LP_UART_DTRN_V << LP_UART_DTRN_S) +#define LP_UART_DTRN_V 0x00000001U +#define LP_UART_DTRN_S 29 +/** LP_UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define LP_UART_RTSN (BIT(30)) +#define LP_UART_RTSN_M (LP_UART_RTSN_V << LP_UART_RTSN_S) +#define LP_UART_RTSN_V 0x00000001U +#define LP_UART_RTSN_S 30 +/** LP_UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define LP_UART_TXD (BIT(31)) +#define LP_UART_TXD_M (LP_UART_TXD_V << LP_UART_TXD_S) +#define LP_UART_TXD_V 0x00000001U +#define LP_UART_TXD_S 31 + +/** LP_UART_CONF0_SYNC_REG register + * Configuration register 0 + */ +#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20) +/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define LP_UART_PARITY (BIT(0)) +#define LP_UART_PARITY_M (LP_UART_PARITY_V << LP_UART_PARITY_S) +#define LP_UART_PARITY_V 0x00000001U +#define LP_UART_PARITY_S 0 +/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define LP_UART_PARITY_EN (BIT(1)) +#define LP_UART_PARITY_EN_M (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S) +#define LP_UART_PARITY_EN_V 0x00000001U +#define LP_UART_PARITY_EN_S 1 +/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define LP_UART_BIT_NUM 0x00000003U +#define LP_UART_BIT_NUM_M (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S) +#define LP_UART_BIT_NUM_V 0x00000003U +#define LP_UART_BIT_NUM_S 2 +/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define LP_UART_STOP_BIT_NUM 0x00000003U +#define LP_UART_STOP_BIT_NUM_M (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S) +#define LP_UART_STOP_BIT_NUM_V 0x00000003U +#define LP_UART_STOP_BIT_NUM_S 4 +/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of sending data + * is done. + */ +#define LP_UART_TXD_BRK (BIT(6)) +#define LP_UART_TXD_BRK_M (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S) +#define LP_UART_TXD_BRK_V 0x00000001U +#define LP_UART_TXD_BRK_S 6 +/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define LP_UART_LOOPBACK (BIT(12)) +#define LP_UART_LOOPBACK_M (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S) +#define LP_UART_LOOPBACK_V 0x00000001U +#define LP_UART_LOOPBACK_S 12 +/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define LP_UART_TX_FLOW_EN (BIT(13)) +#define LP_UART_TX_FLOW_EN_M (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S) +#define LP_UART_TX_FLOW_EN_V 0x00000001U +#define LP_UART_TX_FLOW_EN_S 13 +/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define LP_UART_RXD_INV (BIT(15)) +#define LP_UART_RXD_INV_M (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S) +#define LP_UART_RXD_INV_V 0x00000001U +#define LP_UART_RXD_INV_S 15 +/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define LP_UART_TXD_INV (BIT(16)) +#define LP_UART_TXD_INV_M (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S) +#define LP_UART_TXD_INV_V 0x00000001U +#define LP_UART_TXD_INV_S 16 +/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define LP_UART_DIS_RX_DAT_OVF (BIT(17)) +#define LP_UART_DIS_RX_DAT_OVF_M (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S) +#define LP_UART_DIS_RX_DAT_OVF_V 0x00000001U +#define LP_UART_DIS_RX_DAT_OVF_S 17 +/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define LP_UART_ERR_WR_MASK (BIT(18)) +#define LP_UART_ERR_WR_MASK_M (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S) +#define LP_UART_ERR_WR_MASK_V 0x00000001U +#define LP_UART_ERR_WR_MASK_S 18 +/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ +#define LP_UART_MEM_CLK_EN (BIT(20)) +#define LP_UART_MEM_CLK_EN_M (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S) +#define LP_UART_MEM_CLK_EN_V 0x00000001U +#define LP_UART_MEM_CLK_EN_S 20 +/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define LP_UART_SW_RTS (BIT(21)) +#define LP_UART_SW_RTS_M (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S) +#define LP_UART_SW_RTS_V 0x00000001U +#define LP_UART_SW_RTS_S 21 +/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define LP_UART_RXFIFO_RST (BIT(22)) +#define LP_UART_RXFIFO_RST_M (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S) +#define LP_UART_RXFIFO_RST_V 0x00000001U +#define LP_UART_RXFIFO_RST_S 22 +/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define LP_UART_TXFIFO_RST (BIT(23)) +#define LP_UART_TXFIFO_RST_M (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S) +#define LP_UART_TXFIFO_RST_V 0x00000001U +#define LP_UART_TXFIFO_RST_S 23 + +/** LP_UART_CONF1_REG register + * Configuration register 1 + */ +#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24) +/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define LP_UART_RXFIFO_FULL_THRHD 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_M (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S) +#define LP_UART_RXFIFO_FULL_THRHD_V 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_S 3 +/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define LP_UART_TXFIFO_EMPTY_THRHD 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_M (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S) +#define LP_UART_TXFIFO_EMPTY_THRHD_V 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_S 11 +/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define LP_UART_CTS_INV (BIT(16)) +#define LP_UART_CTS_INV_M (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S) +#define LP_UART_CTS_INV_V 0x00000001U +#define LP_UART_CTS_INV_S 16 +/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define LP_UART_DSR_INV (BIT(17)) +#define LP_UART_DSR_INV_M (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S) +#define LP_UART_DSR_INV_V 0x00000001U +#define LP_UART_DSR_INV_S 17 +/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define LP_UART_RTS_INV (BIT(18)) +#define LP_UART_RTS_INV_M (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S) +#define LP_UART_RTS_INV_V 0x00000001U +#define LP_UART_RTS_INV_S 18 +/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define LP_UART_DTR_INV (BIT(19)) +#define LP_UART_DTR_INV_M (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S) +#define LP_UART_DTR_INV_V 0x00000001U +#define LP_UART_DTR_INV_S 19 +/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define LP_UART_SW_DTR (BIT(20)) +#define LP_UART_SW_DTR_M (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S) +#define LP_UART_SW_DTR_V 0x00000001U +#define LP_UART_SW_DTR_S 20 +/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define LP_UART_CLK_EN (BIT(21)) +#define LP_UART_CLK_EN_M (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S) +#define LP_UART_CLK_EN_V 0x00000001U +#define LP_UART_CLK_EN_S 21 + +/** LP_UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c) +/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define LP_UART_RX_FLOW_THRHD 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_M (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S) +#define LP_UART_RX_FLOW_THRHD_V 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_S 3 +/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define LP_UART_RX_FLOW_EN (BIT(8)) +#define LP_UART_RX_FLOW_EN_M (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S) +#define LP_UART_RX_FLOW_EN_V 0x00000001U +#define LP_UART_RX_FLOW_EN_S 8 + +/** LP_UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30) +/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define LP_UART_WK_CHAR1 0x000000FFU +#define LP_UART_WK_CHAR1_M (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S) +#define LP_UART_WK_CHAR1_V 0x000000FFU +#define LP_UART_WK_CHAR1_S 0 +/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define LP_UART_WK_CHAR2 0x000000FFU +#define LP_UART_WK_CHAR2_M (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S) +#define LP_UART_WK_CHAR2_V 0x000000FFU +#define LP_UART_WK_CHAR2_S 8 +/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define LP_UART_WK_CHAR3 0x000000FFU +#define LP_UART_WK_CHAR3_M (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S) +#define LP_UART_WK_CHAR3_V 0x000000FFU +#define LP_UART_WK_CHAR3_S 16 +/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define LP_UART_WK_CHAR4 0x000000FFU +#define LP_UART_WK_CHAR4_M (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S) +#define LP_UART_WK_CHAR4_V 0x000000FFU +#define LP_UART_WK_CHAR4_S 24 + +/** LP_UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34) +/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define LP_UART_WK_CHAR0 0x000000FFU +#define LP_UART_WK_CHAR0_M (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S) +#define LP_UART_WK_CHAR0_V 0x000000FFU +#define LP_UART_WK_CHAR0_S 0 + +/** LP_UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38) +/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define LP_UART_ACTIVE_THRESHOLD 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_M (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S) +#define LP_UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_S 0 +/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define LP_UART_RX_WAKE_UP_THRHD 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_M (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S) +#define LP_UART_RX_WAKE_UP_THRHD_V 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_S 13 +/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define LP_UART_WK_CHAR_NUM 0x00000007U +#define LP_UART_WK_CHAR_NUM_M (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S) +#define LP_UART_WK_CHAR_NUM_V 0x00000007U +#define LP_UART_WK_CHAR_NUM_S 18 +/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define LP_UART_WK_CHAR_MASK 0x0000001FU +#define LP_UART_WK_CHAR_MASK_M (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S) +#define LP_UART_WK_CHAR_MASK_V 0x0000001FU +#define LP_UART_WK_CHAR_MASK_S 21 +/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define LP_UART_WK_MODE_SEL 0x00000003U +#define LP_UART_WK_MODE_SEL_M (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S) +#define LP_UART_WK_MODE_SEL_V 0x00000003U +#define LP_UART_WK_MODE_SEL_S 26 + +/** LP_UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c) +/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define LP_UART_XON_CHAR 0x000000FFU +#define LP_UART_XON_CHAR_M (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S) +#define LP_UART_XON_CHAR_V 0x000000FFU +#define LP_UART_XON_CHAR_S 0 +/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define LP_UART_XOFF_CHAR 0x000000FFU +#define LP_UART_XOFF_CHAR_M (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S) +#define LP_UART_XOFF_CHAR_V 0x000000FFU +#define LP_UART_XOFF_CHAR_S 8 +/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define LP_UART_XON_XOFF_STILL_SEND (BIT(16)) +#define LP_UART_XON_XOFF_STILL_SEND_M (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S) +#define LP_UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define LP_UART_XON_XOFF_STILL_SEND_S 16 +/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define LP_UART_SW_FLOW_CON_EN (BIT(17)) +#define LP_UART_SW_FLOW_CON_EN_M (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S) +#define LP_UART_SW_FLOW_CON_EN_V 0x00000001U +#define LP_UART_SW_FLOW_CON_EN_S 17 +/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define LP_UART_XONOFF_DEL (BIT(18)) +#define LP_UART_XONOFF_DEL_M (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S) +#define LP_UART_XONOFF_DEL_V 0x00000001U +#define LP_UART_XONOFF_DEL_S 18 +/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define LP_UART_FORCE_XON (BIT(19)) +#define LP_UART_FORCE_XON_M (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S) +#define LP_UART_FORCE_XON_V 0x00000001U +#define LP_UART_FORCE_XON_S 19 +/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define LP_UART_FORCE_XOFF (BIT(20)) +#define LP_UART_FORCE_XOFF_M (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S) +#define LP_UART_FORCE_XOFF_V 0x00000001U +#define LP_UART_FORCE_XOFF_S 20 +/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XON (BIT(21)) +#define LP_UART_SEND_XON_M (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S) +#define LP_UART_SEND_XON_V 0x00000001U +#define LP_UART_SEND_XON_S 21 +/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XOFF (BIT(22)) +#define LP_UART_SEND_XOFF_M (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S) +#define LP_UART_SEND_XOFF_V 0x00000001U +#define LP_UART_SEND_XOFF_S 22 + +/** LP_UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40) +/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define LP_UART_XON_THRESHOLD 0x0000001FU +#define LP_UART_XON_THRESHOLD_M (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S) +#define LP_UART_XON_THRESHOLD_V 0x0000001FU +#define LP_UART_XON_THRESHOLD_S 3 +/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define LP_UART_XOFF_THRESHOLD 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_M (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S) +#define LP_UART_XOFF_THRESHOLD_V 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_S 11 + +/** LP_UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44) +/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define LP_UART_TX_BRK_NUM 0x000000FFU +#define LP_UART_TX_BRK_NUM_M (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S) +#define LP_UART_TX_BRK_NUM_V 0x000000FFU +#define LP_UART_TX_BRK_NUM_S 0 + +/** LP_UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48) +/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define LP_UART_RX_IDLE_THRHD 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_M (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S) +#define LP_UART_RX_IDLE_THRHD_V 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_S 0 +/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define LP_UART_TX_IDLE_NUM 0x000003FFU +#define LP_UART_TX_IDLE_NUM_M (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S) +#define LP_UART_TX_IDLE_NUM_V 0x000003FFU +#define LP_UART_TX_IDLE_NUM_S 10 + +/** LP_UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c) +/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL0_EN (BIT(1)) +#define LP_UART_DL0_EN_M (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S) +#define LP_UART_DL0_EN_V 0x00000001U +#define LP_UART_DL0_EN_S 1 +/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL1_EN (BIT(2)) +#define LP_UART_DL1_EN_M (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S) +#define LP_UART_DL1_EN_V 0x00000001U +#define LP_UART_DL1_EN_S 2 + +/** LP_UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50) +/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define LP_UART_PRE_IDLE_NUM 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_M (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S) +#define LP_UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54) +/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define LP_UART_POST_IDLE_NUM 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_M (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S) +#define LP_UART_POST_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58) +/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define LP_UART_RX_GAP_TOUT 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_M (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S) +#define LP_UART_RX_GAP_TOUT_V 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_S 0 + +/** LP_UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c) +/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR 0x000000FFU +#define LP_UART_AT_CMD_CHAR_M (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S) +#define LP_UART_AT_CMD_CHAR_V 0x000000FFU +#define LP_UART_AT_CMD_CHAR_S 0 +/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define LP_UART_CHAR_NUM 0x000000FFU +#define LP_UART_CHAR_NUM_M (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S) +#define LP_UART_CHAR_NUM_V 0x000000FFU +#define LP_UART_CHAR_NUM_S 8 + +/** LP_UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60) +/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define LP_UART_MEM_FORCE_PD (BIT(25)) +#define LP_UART_MEM_FORCE_PD_M (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S) +#define LP_UART_MEM_FORCE_PD_V 0x00000001U +#define LP_UART_MEM_FORCE_PD_S 25 +/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define LP_UART_MEM_FORCE_PU (BIT(26)) +#define LP_UART_MEM_FORCE_PU_M (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S) +#define LP_UART_MEM_FORCE_PU_V 0x00000001U +#define LP_UART_MEM_FORCE_PU_S 26 + +/** LP_UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) +/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enable bit for uart receiver's timeout function. + */ +#define LP_UART_RX_TOUT_EN (BIT(0)) +#define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) +#define LP_UART_RX_TOUT_EN_V 0x00000001U +#define LP_UART_RX_TOUT_EN_S 0 +/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define LP_UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define LP_UART_RX_TOUT_FLOW_DIS_M (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S) +#define LP_UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define LP_UART_RX_TOUT_FLOW_DIS_S 1 +/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define LP_UART_RX_TOUT_THRHD 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_M (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S) +#define LP_UART_RX_TOUT_THRHD_V 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_S 2 + +/** LP_UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68) +/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_WADDR 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_M (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S) +#define LP_UART_TX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_S 3 +/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_RADDR 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_M (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S) +#define LP_UART_TX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_S 12 + +/** LP_UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c) +/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ +#define LP_UART_RX_SRAM_RADDR 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_M (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S) +#define LP_UART_RX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_S 3 +/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ +#define LP_UART_RX_SRAM_WADDR 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_M (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S) +#define LP_UART_RX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_S 12 + +/** LP_UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70) +/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define LP_UART_ST_URX_OUT 0x0000000FU +#define LP_UART_ST_URX_OUT_M (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S) +#define LP_UART_ST_URX_OUT_V 0x0000000FU +#define LP_UART_ST_URX_OUT_S 0 +/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define LP_UART_ST_UTX_OUT 0x0000000FU +#define LP_UART_ST_UTX_OUT_M (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S) +#define LP_UART_ST_UTX_OUT_V 0x0000000FU +#define LP_UART_ST_UTX_OUT_S 4 + +/** LP_UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88) +/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define LP_UART_TX_SCLK_EN (BIT(24)) +#define LP_UART_TX_SCLK_EN_M (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S) +#define LP_UART_TX_SCLK_EN_V 0x00000001U +#define LP_UART_TX_SCLK_EN_S 24 +/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define LP_UART_RX_SCLK_EN (BIT(25)) +#define LP_UART_RX_SCLK_EN_M (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S) +#define LP_UART_RX_SCLK_EN_V 0x00000001U +#define LP_UART_RX_SCLK_EN_S 25 +/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define LP_UART_TX_RST_CORE (BIT(26)) +#define LP_UART_TX_RST_CORE_M (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S) +#define LP_UART_TX_RST_CORE_V 0x00000001U +#define LP_UART_TX_RST_CORE_S 26 +/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define LP_UART_RX_RST_CORE (BIT(27)) +#define LP_UART_RX_RST_CORE_M (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S) +#define LP_UART_RX_RST_CORE_V 0x00000001U +#define LP_UART_RX_RST_CORE_S 27 + +/** LP_UART_DATE_REG register + * UART Version register + */ +#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c) +/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ +#define LP_UART_DATE 0xFFFFFFFFU +#define LP_UART_DATE_M (LP_UART_DATE_V << LP_UART_DATE_S) +#define LP_UART_DATE_V 0xFFFFFFFFU +#define LP_UART_DATE_S 0 + +/** LP_UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90) +/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_FULL (BIT(0)) +#define LP_UART_TX_AFIFO_FULL_M (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S) +#define LP_UART_TX_AFIFO_FULL_V 0x00000001U +#define LP_UART_TX_AFIFO_FULL_S 0 +/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_EMPTY (BIT(1)) +#define LP_UART_TX_AFIFO_EMPTY_M (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S) +#define LP_UART_TX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_TX_AFIFO_EMPTY_S 1 +/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_FULL (BIT(2)) +#define LP_UART_RX_AFIFO_FULL_M (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S) +#define LP_UART_RX_AFIFO_FULL_V 0x00000001U +#define LP_UART_RX_AFIFO_FULL_S 2 +/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_EMPTY (BIT(3)) +#define LP_UART_RX_AFIFO_EMPTY_M (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S) +#define LP_UART_RX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_RX_AFIFO_EMPTY_S 3 + +/** LP_UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98) +/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define LP_UART_REG_UPDATE (BIT(0)) +#define LP_UART_REG_UPDATE_M (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S) +#define LP_UART_REG_UPDATE_V 0x00000001U +#define LP_UART_REG_UPDATE_S 0 + +/** LP_UART_ID_REG register + * UART ID register + */ +#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c) +/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define LP_UART_ID 0xFFFFFFFFU +#define LP_UART_ID_M (LP_UART_ID_V << LP_UART_ID_S) +#define LP_UART_ID_V 0xFFFFFFFFU +#define LP_UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_uart_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_uart_struct.h new file mode 100644 index 0000000000..d7043fc5ed --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_uart_struct.h @@ -0,0 +1,1102 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} lp_uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enable bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * Configuration register 0 + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + uint32_t reserved_7:5; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + uint32_t reserved_14:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + uint32_t reserved_19:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 0; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:5; + uint32_t reserved_8:3; + /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:5; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:5; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} lp_uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + uint32_t reserved_10:3; + /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:5; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** xon_threshold : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:5; + uint32_t reserved_8:3; + /** xoff_threshold : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:5; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + uint32_t reserved_16:3; + /** txfifo_cnt : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} lp_uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:5; + uint32_t reserved_8:4; + /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:5; + uint32_t reserved_8:4; + /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_char_sync_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36720720; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} lp_uart_id_reg_t; + + +typedef struct { + volatile lp_uart_fifo_reg_t fifo; + volatile lp_uart_int_raw_reg_t int_raw; + volatile lp_uart_int_st_reg_t int_st; + volatile lp_uart_int_ena_reg_t int_ena; + volatile lp_uart_int_clr_reg_t int_clr; + volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync; + volatile lp_uart_rx_filt_reg_t rx_filt; + volatile lp_uart_status_reg_t status; + volatile lp_uart_conf0_sync_reg_t conf0_sync; + volatile lp_uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile lp_uart_sleep_conf0_reg_t sleep_conf0; + volatile lp_uart_sleep_conf1_reg_t sleep_conf1; + volatile lp_uart_sleep_conf2_reg_t sleep_conf2; + volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile lp_uart_swfc_conf1_reg_t swfc_conf1; + volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync; + volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile lp_uart_mem_conf_reg_t mem_conf; + volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync; + volatile lp_uart_mem_tx_status_reg_t mem_tx_status; + volatile lp_uart_mem_rx_status_reg_t mem_rx_status; + volatile lp_uart_fsm_status_reg_t fsm_status; + uint32_t reserved_074[5]; + volatile lp_uart_clk_conf_reg_t clk_conf; + volatile lp_uart_date_reg_t date; + volatile lp_uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile lp_uart_reg_update_reg_t reg_update; + volatile lp_uart_id_reg_t id; +} lp_uart_dev_t; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..1c215bdfa3 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_reg.h @@ -0,0 +1,324 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_FEED (BIT(31)) +#define LP_WDT_FEED_M (LP_WDT_FEED_V << LP_WDT_FEED_S) +#define LP_WDT_FEED_V 0x00000001U +#define LP_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 35725408; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..10cfad4386 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lp_wdt_struct.h @@ -0,0 +1,310 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of config0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} rtc_wdt_config0_reg_t; + +/** Type of config1 register + * need_des + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} rtc_wdt_config1_reg_t; + +/** Type of config2 register + * need_des + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} rtc_wdt_config2_reg_t; + +/** Type of config3 register + * need_des + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} rtc_wdt_config3_reg_t; + +/** Type of config4 register + * need_des + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} rtc_wdt_config4_reg_t; + +/** Type of feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t feed:1; + }; + uint32_t val; +} rtc_wdt_feed_reg_t; + +/** Type of wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} rtc_wdt_wprotect_reg_t; + +/** Type of swd_config register + * need_des + */ +typedef union { + struct { + /** swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t swd_reset_flag:1; + uint32_t reserved_1:17; + /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t swd_auto_feed_en:1; + /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t swd_rst_flag_clr:1; + /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t swd_signal_width:10; + /** swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t swd_disable:1; + /** swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t swd_feed:1; + }; + uint32_t val; +} rtc_wdt_swd_config_reg_t; + +/** Type of swd_wprotect register + * need_des + */ +typedef union { + struct { + /** swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t swd_wkey:32; + }; + uint32_t val; +} rtc_wdt_swd_wprotect_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_raw:1; + /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_raw:1; + }; + uint32_t val; +} rtc_wdt_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} rtc_wdt_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} rtc_wdt_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} rtc_wdt_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_wdt_date : R/W; bitpos: [30:0]; default: 35725408; + * need_des + */ + uint32_t lp_wdt_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rtc_wdt_date_reg_t; + + +typedef struct { + volatile rtc_wdt_config0_reg_t config0; + volatile rtc_wdt_config1_reg_t config1; + volatile rtc_wdt_config2_reg_t config2; + volatile rtc_wdt_config3_reg_t config3; + volatile rtc_wdt_config4_reg_t config4; + volatile rtc_wdt_feed_reg_t feed; + volatile rtc_wdt_wprotect_reg_t wprotect; + volatile rtc_wdt_swd_config_reg_t swd_config; + volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect; + volatile rtc_wdt_int_raw_reg_t int_raw; + volatile rtc_wdt_int_st_reg_t int_st; + volatile rtc_wdt_int_ena_reg_t int_ena; + volatile rtc_wdt_int_clr_reg_t int_clr; + uint32_t reserved_034[242]; + volatile rtc_wdt_date_reg_t date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lpperi_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/lpperi_reg.h new file mode 100644 index 0000000000..338134fe92 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lpperi_reg.h @@ -0,0 +1,470 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_CK_EN_RNG : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_RNG (BIT(16)) +#define LPPERI_CK_EN_RNG_M (LPPERI_CK_EN_RNG_V << LPPERI_CK_EN_RNG_S) +#define LPPERI_CK_EN_RNG_V 0x00000001U +#define LPPERI_CK_EN_RNG_S 16 +/** LPPERI_CK_EN_LP_TSENS : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_TSENS (BIT(17)) +#define LPPERI_CK_EN_LP_TSENS_M (LPPERI_CK_EN_LP_TSENS_V << LPPERI_CK_EN_LP_TSENS_S) +#define LPPERI_CK_EN_LP_TSENS_V 0x00000001U +#define LPPERI_CK_EN_LP_TSENS_S 17 +/** LPPERI_CK_EN_LP_PMS : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_PMS (BIT(18)) +#define LPPERI_CK_EN_LP_PMS_M (LPPERI_CK_EN_LP_PMS_V << LPPERI_CK_EN_LP_PMS_S) +#define LPPERI_CK_EN_LP_PMS_V 0x00000001U +#define LPPERI_CK_EN_LP_PMS_S 18 +/** LPPERI_CK_EN_LP_EFUSE : R/W; bitpos: [19]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_EFUSE (BIT(19)) +#define LPPERI_CK_EN_LP_EFUSE_M (LPPERI_CK_EN_LP_EFUSE_V << LPPERI_CK_EN_LP_EFUSE_S) +#define LPPERI_CK_EN_LP_EFUSE_V 0x00000001U +#define LPPERI_CK_EN_LP_EFUSE_S 19 +/** LPPERI_CK_EN_LP_IOMUX : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_IOMUX (BIT(20)) +#define LPPERI_CK_EN_LP_IOMUX_M (LPPERI_CK_EN_LP_IOMUX_V << LPPERI_CK_EN_LP_IOMUX_S) +#define LPPERI_CK_EN_LP_IOMUX_V 0x00000001U +#define LPPERI_CK_EN_LP_IOMUX_S 20 +/** LPPERI_CK_EN_LP_TOUCH : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_TOUCH (BIT(21)) +#define LPPERI_CK_EN_LP_TOUCH_M (LPPERI_CK_EN_LP_TOUCH_V << LPPERI_CK_EN_LP_TOUCH_S) +#define LPPERI_CK_EN_LP_TOUCH_V 0x00000001U +#define LPPERI_CK_EN_LP_TOUCH_S 21 +/** LPPERI_CK_EN_LP_SPI : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_SPI (BIT(22)) +#define LPPERI_CK_EN_LP_SPI_M (LPPERI_CK_EN_LP_SPI_V << LPPERI_CK_EN_LP_SPI_S) +#define LPPERI_CK_EN_LP_SPI_V 0x00000001U +#define LPPERI_CK_EN_LP_SPI_S 22 +/** LPPERI_CK_EN_LP_ADC : R/W; bitpos: [23]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_ADC (BIT(23)) +#define LPPERI_CK_EN_LP_ADC_M (LPPERI_CK_EN_LP_ADC_V << LPPERI_CK_EN_LP_ADC_S) +#define LPPERI_CK_EN_LP_ADC_V 0x00000001U +#define LPPERI_CK_EN_LP_ADC_S 23 +/** LPPERI_CK_EN_LP_I2S_TX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_I2S_TX (BIT(24)) +#define LPPERI_CK_EN_LP_I2S_TX_M (LPPERI_CK_EN_LP_I2S_TX_V << LPPERI_CK_EN_LP_I2S_TX_S) +#define LPPERI_CK_EN_LP_I2S_TX_V 0x00000001U +#define LPPERI_CK_EN_LP_I2S_TX_S 24 +/** LPPERI_CK_EN_LP_I2S_RX : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_I2S_RX (BIT(25)) +#define LPPERI_CK_EN_LP_I2S_RX_M (LPPERI_CK_EN_LP_I2S_RX_V << LPPERI_CK_EN_LP_I2S_RX_S) +#define LPPERI_CK_EN_LP_I2S_RX_V 0x00000001U +#define LPPERI_CK_EN_LP_I2S_RX_S 25 +/** LPPERI_CK_EN_LP_I2S : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_I2S (BIT(26)) +#define LPPERI_CK_EN_LP_I2S_M (LPPERI_CK_EN_LP_I2S_V << LPPERI_CK_EN_LP_I2S_S) +#define LPPERI_CK_EN_LP_I2S_V 0x00000001U +#define LPPERI_CK_EN_LP_I2S_S 26 +/** LPPERI_CK_EN_LP_I2CMST : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_I2CMST (BIT(27)) +#define LPPERI_CK_EN_LP_I2CMST_M (LPPERI_CK_EN_LP_I2CMST_V << LPPERI_CK_EN_LP_I2CMST_S) +#define LPPERI_CK_EN_LP_I2CMST_V 0x00000001U +#define LPPERI_CK_EN_LP_I2CMST_S 27 +/** LPPERI_CK_EN_LP_I2C : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_I2C (BIT(28)) +#define LPPERI_CK_EN_LP_I2C_M (LPPERI_CK_EN_LP_I2C_V << LPPERI_CK_EN_LP_I2C_S) +#define LPPERI_CK_EN_LP_I2C_V 0x00000001U +#define LPPERI_CK_EN_LP_I2C_S 28 +/** LPPERI_CK_EN_LP_UART : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_UART (BIT(29)) +#define LPPERI_CK_EN_LP_UART_M (LPPERI_CK_EN_LP_UART_V << LPPERI_CK_EN_LP_UART_S) +#define LPPERI_CK_EN_LP_UART_V 0x00000001U +#define LPPERI_CK_EN_LP_UART_S 29 +/** LPPERI_CK_EN_LP_INTR : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_CK_EN_LP_INTR (BIT(30)) +#define LPPERI_CK_EN_LP_INTR_M (LPPERI_CK_EN_LP_INTR_V << LPPERI_CK_EN_LP_INTR_S) +#define LPPERI_CK_EN_LP_INTR_V 0x00000001U +#define LPPERI_CK_EN_LP_INTR_S 30 +/** LPPERI_CK_EN_LP_CORE : R/W; bitpos: [31]; default: 0; + * write 1 to force on lp_core clk + */ +#define LPPERI_CK_EN_LP_CORE (BIT(31)) +#define LPPERI_CK_EN_LP_CORE_M (LPPERI_CK_EN_LP_CORE_V << LPPERI_CK_EN_LP_CORE_S) +#define LPPERI_CK_EN_LP_CORE_V 0x00000001U +#define LPPERI_CK_EN_LP_CORE_S 31 + +/** LPPERI_CORE_CLK_SEL_REG register + * need_des + */ +#define LPPERI_CORE_CLK_SEL_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_LP_I2S_TX_CLK_SEL : R/W; bitpos: [25:24]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_TX_CLK_SEL 0x00000003U +#define LPPERI_LP_I2S_TX_CLK_SEL_M (LPPERI_LP_I2S_TX_CLK_SEL_V << LPPERI_LP_I2S_TX_CLK_SEL_S) +#define LPPERI_LP_I2S_TX_CLK_SEL_V 0x00000003U +#define LPPERI_LP_I2S_TX_CLK_SEL_S 24 +/** LPPERI_LP_I2S_RX_CLK_SEL : R/W; bitpos: [27:26]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_RX_CLK_SEL 0x00000003U +#define LPPERI_LP_I2S_RX_CLK_SEL_M (LPPERI_LP_I2S_RX_CLK_SEL_V << LPPERI_LP_I2S_RX_CLK_SEL_S) +#define LPPERI_LP_I2S_RX_CLK_SEL_V 0x00000003U +#define LPPERI_LP_I2S_RX_CLK_SEL_S 26 +/** LPPERI_LP_I2C_CLK_SEL : R/W; bitpos: [29:28]; default: 0; + * need_des + */ +#define LPPERI_LP_I2C_CLK_SEL 0x00000003U +#define LPPERI_LP_I2C_CLK_SEL_M (LPPERI_LP_I2C_CLK_SEL_V << LPPERI_LP_I2C_CLK_SEL_S) +#define LPPERI_LP_I2C_CLK_SEL_V 0x00000003U +#define LPPERI_LP_I2C_CLK_SEL_S 28 +/** LPPERI_LP_UART_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_CLK_SEL 0x00000003U +#define LPPERI_LP_UART_CLK_SEL_M (LPPERI_LP_UART_CLK_SEL_V << LPPERI_LP_UART_CLK_SEL_S) +#define LPPERI_LP_UART_CLK_SEL_V 0x00000003U +#define LPPERI_LP_UART_CLK_SEL_S 30 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RST_EN_LP_RNG : R/W; bitpos: [17]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_RNG (BIT(17)) +#define LPPERI_RST_EN_LP_RNG_M (LPPERI_RST_EN_LP_RNG_V << LPPERI_RST_EN_LP_RNG_S) +#define LPPERI_RST_EN_LP_RNG_V 0x00000001U +#define LPPERI_RST_EN_LP_RNG_S 17 +/** LPPERI_RST_EN_LP_TSENS : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_TSENS (BIT(18)) +#define LPPERI_RST_EN_LP_TSENS_M (LPPERI_RST_EN_LP_TSENS_V << LPPERI_RST_EN_LP_TSENS_S) +#define LPPERI_RST_EN_LP_TSENS_V 0x00000001U +#define LPPERI_RST_EN_LP_TSENS_S 18 +/** LPPERI_RST_EN_LP_PMS : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_PMS (BIT(19)) +#define LPPERI_RST_EN_LP_PMS_M (LPPERI_RST_EN_LP_PMS_V << LPPERI_RST_EN_LP_PMS_S) +#define LPPERI_RST_EN_LP_PMS_V 0x00000001U +#define LPPERI_RST_EN_LP_PMS_S 19 +/** LPPERI_RST_EN_LP_EFUSE : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_EFUSE (BIT(20)) +#define LPPERI_RST_EN_LP_EFUSE_M (LPPERI_RST_EN_LP_EFUSE_V << LPPERI_RST_EN_LP_EFUSE_S) +#define LPPERI_RST_EN_LP_EFUSE_V 0x00000001U +#define LPPERI_RST_EN_LP_EFUSE_S 20 +/** LPPERI_RST_EN_LP_IOMUX : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_IOMUX (BIT(21)) +#define LPPERI_RST_EN_LP_IOMUX_M (LPPERI_RST_EN_LP_IOMUX_V << LPPERI_RST_EN_LP_IOMUX_S) +#define LPPERI_RST_EN_LP_IOMUX_V 0x00000001U +#define LPPERI_RST_EN_LP_IOMUX_S 21 +/** LPPERI_RST_EN_LP_TOUCH : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_TOUCH (BIT(22)) +#define LPPERI_RST_EN_LP_TOUCH_M (LPPERI_RST_EN_LP_TOUCH_V << LPPERI_RST_EN_LP_TOUCH_S) +#define LPPERI_RST_EN_LP_TOUCH_V 0x00000001U +#define LPPERI_RST_EN_LP_TOUCH_S 22 +/** LPPERI_RST_EN_LP_SPI : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_SPI (BIT(23)) +#define LPPERI_RST_EN_LP_SPI_M (LPPERI_RST_EN_LP_SPI_V << LPPERI_RST_EN_LP_SPI_S) +#define LPPERI_RST_EN_LP_SPI_V 0x00000001U +#define LPPERI_RST_EN_LP_SPI_S 23 +/** LPPERI_RST_EN_LP_ADC : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_ADC (BIT(24)) +#define LPPERI_RST_EN_LP_ADC_M (LPPERI_RST_EN_LP_ADC_V << LPPERI_RST_EN_LP_ADC_S) +#define LPPERI_RST_EN_LP_ADC_V 0x00000001U +#define LPPERI_RST_EN_LP_ADC_S 24 +/** LPPERI_RST_EN_LP_I2S : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_I2S (BIT(25)) +#define LPPERI_RST_EN_LP_I2S_M (LPPERI_RST_EN_LP_I2S_V << LPPERI_RST_EN_LP_I2S_S) +#define LPPERI_RST_EN_LP_I2S_V 0x00000001U +#define LPPERI_RST_EN_LP_I2S_S 25 +/** LPPERI_RST_EN_LP_I2CMST : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_I2CMST (BIT(26)) +#define LPPERI_RST_EN_LP_I2CMST_M (LPPERI_RST_EN_LP_I2CMST_V << LPPERI_RST_EN_LP_I2CMST_S) +#define LPPERI_RST_EN_LP_I2CMST_V 0x00000001U +#define LPPERI_RST_EN_LP_I2CMST_S 26 +/** LPPERI_RST_EN_LP_I2C : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_I2C (BIT(27)) +#define LPPERI_RST_EN_LP_I2C_M (LPPERI_RST_EN_LP_I2C_V << LPPERI_RST_EN_LP_I2C_S) +#define LPPERI_RST_EN_LP_I2C_V 0x00000001U +#define LPPERI_RST_EN_LP_I2C_S 27 +/** LPPERI_RST_EN_LP_UART : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_UART (BIT(28)) +#define LPPERI_RST_EN_LP_UART_M (LPPERI_RST_EN_LP_UART_V << LPPERI_RST_EN_LP_UART_S) +#define LPPERI_RST_EN_LP_UART_V 0x00000001U +#define LPPERI_RST_EN_LP_UART_S 28 +/** LPPERI_RST_EN_LP_INTR : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_INTR (BIT(29)) +#define LPPERI_RST_EN_LP_INTR_M (LPPERI_RST_EN_LP_INTR_V << LPPERI_RST_EN_LP_INTR_S) +#define LPPERI_RST_EN_LP_INTR_V 0x00000001U +#define LPPERI_RST_EN_LP_INTR_S 29 +/** LPPERI_RST_EN_LP_ROM : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_ROM (BIT(30)) +#define LPPERI_RST_EN_LP_ROM_M (LPPERI_RST_EN_LP_ROM_V << LPPERI_RST_EN_LP_ROM_S) +#define LPPERI_RST_EN_LP_ROM_V 0x00000001U +#define LPPERI_RST_EN_LP_ROM_S 30 +/** LPPERI_RST_EN_LP_CORE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_RST_EN_LP_CORE (BIT(31)) +#define LPPERI_RST_EN_LP_CORE_M (LPPERI_RST_EN_LP_CORE_V << LPPERI_RST_EN_LP_CORE_S) +#define LPPERI_RST_EN_LP_CORE_V 0x00000001U +#define LPPERI_RST_EN_LP_CORE_S 31 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_LPCORE_DBGM_UNAVAILABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVAILABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVAILABLE_M (LPPERI_LPCORE_DBGM_UNAVAILABLE_V << LPPERI_LPCORE_DBGM_UNAVAILABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVAILABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVAILABLE_S 31 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_LP_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_M (LPPERI_LP_UART_WAKEUP_FLAG_CLR_V << LPPERI_LP_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_LP_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_LP_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_LP_UART_WAKEUP_FLAG_M (LPPERI_LP_UART_WAKEUP_FLAG_V << LPPERI_LP_UART_WAKEUP_FLAG_S) +#define LPPERI_LP_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_LP_UART_WAKEUP_FLAG_S 1 +/** LPPERI_LP_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_LP_UART_WAKEUP_EN_M (LPPERI_LP_UART_WAKEUP_EN_V << LPPERI_LP_UART_WAKEUP_EN_S) +#define LPPERI_LP_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_LP_UART_WAKEUP_EN_S 29 +/** LPPERI_LP_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_LP_UART_MEM_FORCE_PD_M (LPPERI_LP_UART_MEM_FORCE_PD_V << LPPERI_LP_UART_MEM_FORCE_PD_S) +#define LPPERI_LP_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_LP_UART_MEM_FORCE_PD_S 30 +/** LPPERI_LP_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_LP_UART_MEM_FORCE_PU_M (LPPERI_LP_UART_MEM_FORCE_PU_V << LPPERI_LP_UART_MEM_FORCE_PU_S) +#define LPPERI_LP_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_LP_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_ADC_CTRL_REG register + * need_des + */ +#define LPPERI_ADC_CTRL_REG (DR_REG_LPPERI_BASE + 0x2c) +/** LPPERI_SAR2_CLK_FORCE_ON : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LPPERI_SAR2_CLK_FORCE_ON (BIT(6)) +#define LPPERI_SAR2_CLK_FORCE_ON_M (LPPERI_SAR2_CLK_FORCE_ON_V << LPPERI_SAR2_CLK_FORCE_ON_S) +#define LPPERI_SAR2_CLK_FORCE_ON_V 0x00000001U +#define LPPERI_SAR2_CLK_FORCE_ON_S 6 +/** LPPERI_SAR1_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LPPERI_SAR1_CLK_FORCE_ON (BIT(7)) +#define LPPERI_SAR1_CLK_FORCE_ON_M (LPPERI_SAR1_CLK_FORCE_ON_V << LPPERI_SAR1_CLK_FORCE_ON_S) +#define LPPERI_SAR1_CLK_FORCE_ON_V 0x00000001U +#define LPPERI_SAR1_CLK_FORCE_ON_S 7 +/** LPPERI_LPADC_FUNC_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * need_des + */ +#define LPPERI_LPADC_FUNC_DIV_NUM 0x000000FFU +#define LPPERI_LPADC_FUNC_DIV_NUM_M (LPPERI_LPADC_FUNC_DIV_NUM_V << LPPERI_LPADC_FUNC_DIV_NUM_S) +#define LPPERI_LPADC_FUNC_DIV_NUM_V 0x000000FFU +#define LPPERI_LPADC_FUNC_DIV_NUM_S 8 +/** LPPERI_LPADC_SAR2_DIV_NUM : R/W; bitpos: [23:16]; default: 4; + * need_des + */ +#define LPPERI_LPADC_SAR2_DIV_NUM 0x000000FFU +#define LPPERI_LPADC_SAR2_DIV_NUM_M (LPPERI_LPADC_SAR2_DIV_NUM_V << LPPERI_LPADC_SAR2_DIV_NUM_S) +#define LPPERI_LPADC_SAR2_DIV_NUM_V 0x000000FFU +#define LPPERI_LPADC_SAR2_DIV_NUM_S 16 +/** LPPERI_LPADC_SAR1_DIV_NUM : R/W; bitpos: [31:24]; default: 4; + * need_des + */ +#define LPPERI_LPADC_SAR1_DIV_NUM 0x000000FFU +#define LPPERI_LPADC_SAR1_DIV_NUM_M (LPPERI_LPADC_SAR1_DIV_NUM_V << LPPERI_LPADC_SAR1_DIV_NUM_S) +#define LPPERI_LPADC_SAR1_DIV_NUM_V 0x000000FFU +#define LPPERI_LPADC_SAR1_DIV_NUM_S 24 + +/** LPPERI_LP_I2S_RXCLK_DIV_NUM_REG register + * need_des + */ +#define LPPERI_LP_I2S_RXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x30) +/** LPPERI_LP_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2; + * need_des + */ +#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_M (LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S) +#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_NUM_S 24 + +/** LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG register + * need_des + */ +#define LPPERI_LP_I2S_RXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x34) +/** LPPERI_LP_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1 (BIT(4)) +#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_M (LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S) +#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define LPPERI_LP_I2S_RX_CLKM_DIV_YN1_S 4 +/** LPPERI_LP_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_M (LPPERI_LP_I2S_RX_CLKM_DIV_Z_V << LPPERI_LP_I2S_RX_CLKM_DIV_Z_S) +#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_Z_S 5 +/** LPPERI_LP_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1; + * need_des + */ +#define LPPERI_LP_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_M (LPPERI_LP_I2S_RX_CLKM_DIV_Y_V << LPPERI_LP_I2S_RX_CLKM_DIV_Y_S) +#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_Y_S 14 +/** LPPERI_LP_I2S_RX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_RX_CLKM_DIV_X 0x000001FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_X_M (LPPERI_LP_I2S_RX_CLKM_DIV_X_V << LPPERI_LP_I2S_RX_CLKM_DIV_X_S) +#define LPPERI_LP_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define LPPERI_LP_I2S_RX_CLKM_DIV_X_S 23 + +/** LPPERI_LP_I2S_TXCLK_DIV_NUM_REG register + * need_des + */ +#define LPPERI_LP_I2S_TXCLK_DIV_NUM_REG (DR_REG_LPPERI_BASE + 0x38) +/** LPPERI_LP_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [31:24]; default: 2; + * need_des + */ +#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_M (LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V << LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S) +#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_NUM_S 24 + +/** LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG register + * need_des + */ +#define LPPERI_LP_I2S_TXCLK_DIV_XYZ_REG (DR_REG_LPPERI_BASE + 0x3c) +/** LPPERI_LP_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1 (BIT(4)) +#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_M (LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V << LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S) +#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define LPPERI_LP_I2S_TX_CLKM_DIV_YN1_S 4 +/** LPPERI_LP_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [13:5]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_M (LPPERI_LP_I2S_TX_CLKM_DIV_Z_V << LPPERI_LP_I2S_TX_CLKM_DIV_Z_S) +#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_Z_S 5 +/** LPPERI_LP_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [22:14]; default: 1; + * need_des + */ +#define LPPERI_LP_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_M (LPPERI_LP_I2S_TX_CLKM_DIV_Y_V << LPPERI_LP_I2S_TX_CLKM_DIV_Y_S) +#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_Y_S 14 +/** LPPERI_LP_I2S_TX_CLKM_DIV_X : R/W; bitpos: [31:23]; default: 0; + * need_des + */ +#define LPPERI_LP_I2S_TX_CLKM_DIV_X 0x000001FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_X_M (LPPERI_LP_I2S_TX_CLKM_DIV_X_V << LPPERI_LP_I2S_TX_CLKM_DIV_X_S) +#define LPPERI_LP_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define LPPERI_LP_I2S_TX_CLKM_DIV_X_S 23 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/lpperi_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/lpperi_struct.h new file mode 100644 index 0000000000..98148b4e55 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/lpperi_struct.h @@ -0,0 +1,379 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ck_en_rng : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t ck_en_rng:1; + /** ck_en_lp_tsens : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t ck_en_lp_tsens:1; + /** ck_en_lp_pms : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t ck_en_lp_pms:1; + /** ck_en_lp_efuse : R/W; bitpos: [19]; default: 1; + * need_des + */ + uint32_t ck_en_lp_efuse:1; + /** ck_en_lp_iomux : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t ck_en_lp_iomux:1; + /** ck_en_lp_touch : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t ck_en_lp_touch:1; + /** ck_en_lp_spi : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t ck_en_lp_spi:1; + /** ck_en_lp_adc : R/W; bitpos: [23]; default: 1; + * need_des + */ + uint32_t ck_en_lp_adc:1; + /** ck_en_lp_i2s_tx : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t ck_en_lp_i2s_tx:1; + /** ck_en_lp_i2s_rx : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t ck_en_lp_i2s_rx:1; + /** ck_en_lp_i2s : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t ck_en_lp_i2s:1; + /** ck_en_lp_i2cmst : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t ck_en_lp_i2cmst:1; + /** ck_en_lp_i2c : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t ck_en_lp_i2c:1; + /** ck_en_lp_uart : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t ck_en_lp_uart:1; + /** ck_en_lp_intr : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t ck_en_lp_intr:1; + /** ck_en_lp_core : R/W; bitpos: [31]; default: 0; + * write 1 to force on lp_core clk + */ + uint32_t ck_en_lp_core:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of core_clk_sel register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** lp_i2s_tx_clk_sel : R/W; bitpos: [25:24]; default: 0; + * need_des + */ + uint32_t lp_i2s_tx_clk_sel:2; + /** lp_i2s_rx_clk_sel : R/W; bitpos: [27:26]; default: 0; + * need_des + */ + uint32_t lp_i2s_rx_clk_sel:2; + /** lp_i2c_clk_sel : R/W; bitpos: [29:28]; default: 0; + * need_des + */ + uint32_t lp_i2c_clk_sel:2; + /** lp_uart_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t lp_uart_clk_sel:2; + }; + uint32_t val; +} lpperi_core_clk_sel_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** rst_en_lp_rng : R/W; bitpos: [17]; default: 0; + * need_des + */ + uint32_t rst_en_lp_rng:1; + /** rst_en_lp_tsens : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t rst_en_lp_tsens:1; + /** rst_en_lp_pms : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t rst_en_lp_pms:1; + /** rst_en_lp_efuse : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t rst_en_lp_efuse:1; + /** rst_en_lp_iomux : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t rst_en_lp_iomux:1; + /** rst_en_lp_touch : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t rst_en_lp_touch:1; + /** rst_en_lp_spi : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t rst_en_lp_spi:1; + /** rst_en_lp_adc : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t rst_en_lp_adc:1; + /** rst_en_lp_i2s : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t rst_en_lp_i2s:1; + /** rst_en_lp_i2cmst : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t rst_en_lp_i2cmst:1; + /** rst_en_lp_i2c : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t rst_en_lp_i2c:1; + /** rst_en_lp_uart : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t rst_en_lp_uart:1; + /** rst_en_lp_intr : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t rst_en_lp_intr:1; + /** rst_en_lp_rom : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t rst_en_lp_rom:1; + /** rst_en_lp_core : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t rst_en_lp_core:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavailable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavailable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** lp_uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_uart_wakeup_flag_clr:1; + /** lp_uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** lp_uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_uart_wakeup_en:1; + /** lp_uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_uart_mem_force_pd:1; + /** lp_uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of adc_ctrl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** sar2_clk_force_on : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t sar2_clk_force_on:1; + /** sar1_clk_force_on : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t sar1_clk_force_on:1; + /** lpadc_func_div_num : R/W; bitpos: [15:8]; default: 4; + * need_des + */ + uint32_t lpadc_func_div_num:8; + /** lpadc_sar2_div_num : R/W; bitpos: [23:16]; default: 4; + * need_des + */ + uint32_t lpadc_sar2_div_num:8; + /** lpadc_sar1_div_num : R/W; bitpos: [31:24]; default: 4; + * need_des + */ + uint32_t lpadc_sar1_div_num:8; + }; + uint32_t val; +} lpperi_adc_ctrl_reg_t; + +/** Type of lp_i2s_rxclk_div_num register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** lp_i2s_rx_clkm_div_num : R/W; bitpos: [31:24]; default: 2; + * need_des + */ + uint32_t lp_i2s_rx_clkm_div_num:8; + }; + uint32_t val; +} lpperi_lp_i2s_rxclk_div_num_reg_t; + +/** Type of lp_i2s_rxclk_div_xyz register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lp_i2s_rx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t lp_i2s_rx_clkm_div_yn1:1; + /** lp_i2s_rx_clkm_div_z : R/W; bitpos: [13:5]; default: 0; + * need_des + */ + uint32_t lp_i2s_rx_clkm_div_z:9; + /** lp_i2s_rx_clkm_div_y : R/W; bitpos: [22:14]; default: 1; + * need_des + */ + uint32_t lp_i2s_rx_clkm_div_y:9; + /** lp_i2s_rx_clkm_div_x : R/W; bitpos: [31:23]; default: 0; + * need_des + */ + uint32_t lp_i2s_rx_clkm_div_x:9; + }; + uint32_t val; +} lpperi_lp_i2s_rxclk_div_xyz_reg_t; + +/** Type of lp_i2s_txclk_div_num register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** lp_i2s_tx_clkm_div_num : R/W; bitpos: [31:24]; default: 2; + * need_des + */ + uint32_t lp_i2s_tx_clkm_div_num:8; + }; + uint32_t val; +} lpperi_lp_i2s_txclk_div_num_reg_t; + +/** Type of lp_i2s_txclk_div_xyz register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lp_i2s_tx_clkm_div_yn1 : R/W; bitpos: [4]; default: 0; + * need_des + */ + uint32_t lp_i2s_tx_clkm_div_yn1:1; + /** lp_i2s_tx_clkm_div_z : R/W; bitpos: [13:5]; default: 0; + * need_des + */ + uint32_t lp_i2s_tx_clkm_div_z:9; + /** lp_i2s_tx_clkm_div_y : R/W; bitpos: [22:14]; default: 1; + * need_des + */ + uint32_t lp_i2s_tx_clkm_div_y:9; + /** lp_i2s_tx_clkm_div_x : R/W; bitpos: [31:23]; default: 0; + * need_des + */ + uint32_t lp_i2s_tx_clkm_div_x:9; + }; + uint32_t val; +} lpperi_lp_i2s_txclk_div_xyz_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_core_clk_sel_reg_t core_clk_sel; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_cpu_reg_t cpu; + uint32_t reserved_010[6]; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_adc_ctrl_reg_t adc_ctrl; + volatile lpperi_lp_i2s_rxclk_div_num_reg_t lp_i2s_rxclk_div_num; + volatile lpperi_lp_i2s_rxclk_div_xyz_reg_t lp_i2s_rxclk_div_xyz; + volatile lpperi_lp_i2s_txclk_div_num_reg_t lp_i2s_txclk_div_num; + volatile lpperi_lp_i2s_txclk_div_xyz_reg_t lp_i2s_txclk_div_xyz; + uint32_t reserved_040[239]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_eco5_struct.h new file mode 100644 index 0000000000..2ee5ebb57c --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_eco5_struct.h @@ -0,0 +1,2347 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration register */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ + uint32_t clk_prescale:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + +/** Type of timern_cfg0 register + * PWM timern period and update method configuration register. + */ +typedef union { + struct { + /** timern_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timern, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMERn_PRESCALE + 1) + */ + uint32_t timern_prescale:8; + /** timern_period : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timern + */ + uint32_t timern_period:16; + /** timern_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timern period. + * 0: Immediate + * 1: TEZ + * 2: Sync + * 3: TEZ or sync + * TEZ here and below means timer equal zero event + */ + uint32_t timern_period_upmethod:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} mcpwm_timern_cfg0_reg_t; + +/** Type of timern_cfg1 register + * PWM timern working mode and start/stop control register. + */ +typedef union { + struct { + /** timern_start : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timern. + * 0: If PWM timern starts, then stops at TEZ + * 1: If timern starts, then stops at TEP + * 2: PWM timern starts and runs on + * 3: Timern starts and stops at the next TEZ + * 4: Timer0 starts and stops at the next TEP. + * TEP here and below means the event that happens when the timer equals to period + */ + uint32_t timern_start:3; + /** timern_mod : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timern. + * 0: Freeze + * 1: Increase mode + * 2: Decrease mode + * 3: Up-down mode + */ + uint32_t timern_mod:2; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_timern_cfg1_reg_t; + +/** Type of timern_sync register + * PWM timern sync function configuration register. + */ +typedef union { + struct { + /** timern_synci_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timern reloading with phase on sync input event + * is enabled. + * 0: Disable + * 1: Enable + */ + uint32_t timern_synci_en:1; + /** timern_sync_sw : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ + uint32_t timern_sync_sw:1; + /** timern_synco_sel : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timern sync_out. + * 0: Sync_in + * 1: TEZ + * 2: TEP + * 3: Invalid, sync_out selects noting + */ + uint32_t timern_synco_sel:2; + /** timern_phase : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timern reload on sync event. + */ + uint32_t timern_phase:16; + /** timern_phase_direction : R/W; bitpos: [20]; default: 0; + * Configures the PWM timern's direction when timern mode is up-down mode. + * 0: Increase + * 1: Decrease + */ + uint32_t timern_phase_direction:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} mcpwm_timern_sync_reg_t; + +/** Type of timer_synci_cfg register + * Synchronization input selection register for PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0. + * 1: PWM timer0 sync_out + * 2: PWM timer1 sync_out + * 3: PWM timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * Other values: No sync input selected + */ + uint32_t timer0_syncisel:3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1. + * 1: PWM timer0 sync_out + * 2: PWM timer1 sync_out + * 3: PWM timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * Other values: No sync input selected + */ + uint32_t timer1_syncisel:3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2. + * 1: PWM timer0 sync_out + * 2: PWM timer1 sync_out + * 3: PWM timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * Other values: No sync input selected + */ + uint32_t timer2_syncisel:3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix. + * 0: Not invert + * 1: Invert + */ + uint32_t external_synci0_invert:1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix. + * 0: Not invert + * 1: Invert + */ + uint32_t external_synci1_invert:1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix. + * 0: Not invert + * 1: Invert + */ + uint32_t external_synci2_invert:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + +/** Type of operator_timersel register + * PWM operator's timer select register + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0. + * 0: Timer0 + * 1: Timer1 + * 2: Timer2 + * 3: Invalid, will select timer2 + */ + uint32_t operator0_timersel:2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1. + * 0: Timer0 + * 1: Timer1 + * 2: Timer2 + * 3: Invalid, will select timer2 + */ + uint32_t operator1_timersel:2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2. + * 0: Timer0 + * 1: Timer1 + * 2: Timer2 + * 3: Invalid, will select timer2 + */ + uint32_t operator2_timersel:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + +/** Type of genn_stmp_cfg register + * Generatorn time stamp registers A and B transfer status and update method register + */ +typedef union { + struct { + /** cmprn_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator n time stamp A's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ + uint32_t cmprn_a_upmethod:4; + /** cmprn_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator n time stamp B's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ + uint32_t cmprn_b_upmethod:4; + /** cmprn_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generatorn time stamp A's shadow reg is transferred. + * 0: A's active reg has been updated with shadow register latest value. + * 1: A's shadow reg is filled and waiting to be transferred to A's active reg + */ + uint32_t cmprn_a_shdw_full:1; + /** cmprn_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generatorn time stamp B's shadow reg is transferred. + * 0: B's active reg has been updated with shadow register latest value. + * 1: B's shadow reg is filled and waiting to be transferred to B's active reg + */ + uint32_t cmprn_b_shdw_full:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_genn_stmp_cfg_reg_t; + +/** Type of genn_tstmp_a register + * Generatorn time stamp A's shadow register + */ +typedef union { + struct { + /** cmprn_a : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator n time stamp A's shadow register. + */ + uint32_t cmprn_a:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_tstmp_a_reg_t; + +/** Type of genn_tstmp_b register + * Generatorn time stamp B's shadow register + */ +typedef union { + struct { + /** cmprn_b : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator n time stamp B's shadow register. + */ + uint32_t cmprn_b:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_tstmp_b_reg_t; + +/** Type of genn_cfg0 register + * Generatorn fault event T0 and T1 configuration register + */ +typedef union { + struct { + /** genn_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator n's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ + uint32_t genn_cfg_upmethod:4; + /** genn_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator n event_t0, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ + uint32_t genn_t0_sel:3; + /** genn_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator n event_t1, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ + uint32_t genn_t1_sel:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_genn_cfg0_reg_t; + +/** Type of genn_force register + * Generatorn output signal force mode register. + */ +typedef union { + struct { + /** genn_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generatorn. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: TEA + * Bit3 is set to 1: TEB + * Bit4 is set to 1: Sync + * Bit5 is set to 1: Disable update. TEA/B here and below means an event generated + * when the timer's value equals to that of register A/B. + */ + uint32_t genn_cntuforce_upmethod:6; + /** genn_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWMn A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ + uint32_t genn_a_cntuforce_mode:2; + /** genn_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWMn B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ + uint32_t genn_b_cntuforce_mode:2; + /** genn_a_nciforce : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWMn + * A, a toggle will trigger a force event. + */ + uint32_t genn_a_nciforce:1; + /** genn_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWMn A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ + uint32_t genn_a_nciforce_mode:2; + /** genn_b_nciforce : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWMn + * B, a toggle will trigger a force event. + */ + uint32_t genn_b_nciforce:1; + /** genn_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWMn B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ + uint32_t genn_b_nciforce_mode:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_genn_force_reg_t; + +/** Type of genn_a register + * PWMn output signal A actions configuration register + */ +typedef union { + struct { + /** genn_a_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWMn A triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_utez:2; + /** genn_a_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWMn A triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_utep:2; + /** genn_a_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWMn A triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_utea:2; + /** genn_a_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWMn A triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_uteb:2; + /** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWMn A triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_ut0:2; + /** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWMn A triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_ut1:2; + /** genn_a_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWMn A triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_dtez:2; + /** genn_a_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWMn A triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_dtep:2; + /** genn_a_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWMn A triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_dtea:2; + /** genn_a_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWMn A triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_dteb:2; + /** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWMn A triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_dt0:2; + /** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWMn A triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_a_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_genn_a_reg_t; + +/** Type of genn_b register + * PWMn output signal B actions configuration register + */ +typedef union { + struct { + /** genn_b_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWMn B triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_utez:2; + /** genn_b_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWMn B triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_utep:2; + /** genn_b_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWMn B triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_utea:2; + /** genn_b_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWMn B triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_uteb:2; + /** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWMn B triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_ut0:2; + /** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWMn B triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_ut1:2; + /** genn_b_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWMn B triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_dtez:2; + /** genn_b_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWMn B triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_dtep:2; + /** genn_b_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWMn B triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_dtea:2; + /** genn_b_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWMn B triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_dteb:2; + /** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWMn B triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_dt0:2; + /** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWMn B triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ + uint32_t genn_b_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_genn_b_reg_t; + +/** Type of dtn_cfg register + * Dead time configuration register + */ +typedef union { + struct { + /** dbn_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ + uint32_t dbn_fed_upmethod:4; + /** dbn_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ + uint32_t dbn_red_upmethod:4; + /** dbn_deb_mode : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode. + * 0: fed/red take effect on different path separately + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t dbn_deb_mode:1; + /** dbn_a_outswap : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ + uint32_t dbn_a_outswap:1; + /** dbn_b_outswap : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ + uint32_t dbn_b_outswap:1; + /** dbn_red_insel : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ + uint32_t dbn_red_insel:1; + /** dbn_fed_insel : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ + uint32_t dbn_fed_insel:1; + /** dbn_red_outinvert : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ + uint32_t dbn_red_outinvert:1; + /** dbn_fed_outinvert : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ + uint32_t dbn_fed_outinvert:1; + /** dbn_a_outbypass : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ + uint32_t dbn_a_outbypass:1; + /** dbn_b_outbypass : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ + uint32_t dbn_b_outbypass:1; + /** dbn_clk_sel : R/W; bitpos: [17]; default: 0; + * Configures dead time generator n clock selection. + * 0: PWM_clk + * 1: PT_clk + */ + uint32_t dbn_clk_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} mcpwm_dtn_cfg_reg_t; + +/** Type of dtn_fed_cfg register + * Falling edge delay (FED) shadow register + */ +typedef union { + struct { + /** dbn_fed : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ + uint32_t dbn_fed:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dtn_fed_cfg_reg_t; + +/** Type of dtn_red_cfg register + * Rising edge delay (RED) shadow register + */ +typedef union { + struct { + /** dbn_red : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ + uint32_t dbn_red:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dtn_red_cfg_reg_t; + +/** Type of carriern_cfg register + * Carriern configuration register + */ +typedef union { + struct { + /** choppern_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carriern. + * 0: Bypassed + * 1: Enabled + */ + uint32_t choppern_en:1; + /** choppern_prescale : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carriern clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1) + */ + uint32_t choppern_prescale:4; + /** choppern_duty : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8 + */ + uint32_t choppern_duty:3; + /** choppern_oshtwth : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ + uint32_t choppern_oshtwth:4; + /** choppern_out_invert : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWMn A and PWMn B for this + * submodule. + * 0: Normal + * 1: Invert + */ + uint32_t choppern_out_invert:1; + /** choppern_in_invert : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWMn A and PWMn B for this + * submodule. + * 0: Normal + * 1: Invert + */ + uint32_t choppern_in_invert:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} mcpwm_carriern_cfg_reg_t; + +/** Type of fhn_cfg0 register + * PWMn A and PWMn B trip events actions configuration register + */ +typedef union { + struct { + /** tzn_sw_cbc : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_sw_cbc:1; + /** tzn_f2_cbc : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_f2_cbc:1; + /** tzn_f1_cbc : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_f1_cbc:1; + /** tzn_f0_cbc : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_f0_cbc:1; + /** tzn_sw_ost : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_sw_ost:1; + /** tzn_f2_ost : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_f2_ost:1; + /** tzn_f1_ost : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_f1_ost:1; + /** tzn_f0_ost : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ + uint32_t tzn_f0_ost:1; + /** tzn_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_a_cbc_d:2; + /** tzn_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_a_cbc_u:2; + /** tzn_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWMn A when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_a_ost_d:2; + /** tzn_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWMn A when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_a_ost_u:2; + /** tzn_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_b_cbc_d:2; + /** tzn_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_b_cbc_u:2; + /** tzn_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWMn B when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_b_ost_d:2; + /** tzn_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWMn B when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ + uint32_t tzn_b_ost_u:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_fhn_cfg0_reg_t; + +/** Type of fhn_cfg1 register + * Software triggers for fault handler actions configuration register + */ +typedef union { + struct { + /** tzn_clr_ost : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ + uint32_t tzn_clr_ost:1; + /** tzn_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action. + * 0: Select nothing, will not refresh + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + */ + uint32_t tzn_cbcpulse:2; + /** tzn_force_cbc : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ + uint32_t tzn_force_cbc:1; + /** tzn_force_ost : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ + uint32_t tzn_force_ost:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_fhn_cfg1_reg_t; + +/** Type of fault_detect register + * Fault detection configuration and status register + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation. + * 0: Disable + * 1: Enable + */ + uint32_t f0_en:1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation. + * 0: Disable + * 1: Enable + */ + uint32_t f1_en:1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation. + * 0: Disable + * 1: Enable + */ + uint32_t f2_en:1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix. + * 0: Level low + * 1: Level high + */ + uint32_t f0_pole:1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix. + * 0: Level low + * 1: Level high + */ + uint32_t f1_pole:1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix. + * 0: Level low + * 1: Level high + */ + uint32_t f2_pole:1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going. + * 0: No action + * 1: On going + */ + uint32_t event_f0:1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going. + * 0: No action + * 1: On going + */ + uint32_t event_f1:1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going. + * 0: No action + * 1: On going + */ + uint32_t event_f2:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + +/** Type of cap_timer_cfg register + * Capture timer configuration register + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment. + * 0: Disable + * 1: Enable + */ + uint32_t cap_timer_en:1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync. + * 0: Disable + * 1: Enable + */ + uint32_t cap_synci_en:1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input. + * 0: None + * 1: Timer0 sync_out + * 2: Timer1 sync_out + * 3: Timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * 7: None + */ + uint32_t cap_synci_sel:3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1. + * 0: Invalid, No effect + * 1: Trigger a capture timer sync, capture timer is loaded with value in phase + * register + */ + uint32_t cap_sync_sw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + +/** Type of cap_timer_phase register + * Capture timer sync phase register + */ +typedef union { + struct { + /** cap_phase : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ + uint32_t cap_phase:32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + +/** Type of cap_chn_cfg register + * Capture channel n configuration register + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel n. + * 0: Disable + * 1: Enable + */ + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel n after prescaling is used. + * 0: None + * Bit0 is set to 1: Rnable capture on the negative edge + * Bit1 is set to 1: Enable capture on the positive edge + */ + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on positive edge of CAPn. Prescale value = + * PWM_CAPn_PRESCALE + 1 + */ + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAPn from GPIO matrix before prescale. + * 0: Normal + * 1: Invert + */ + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture. + * 0: Invalid, No effect + * 1: Trigger a software forced capture on channel n + */ + uint32_t capn_sw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + +/** Type of update_cfg register + * Generator Update configuration register + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module. + * 0: Disable + * 1: Enable + */ + uint32_t global_up_en:1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ + uint32_t global_force_up:1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator0. + * Valid only when PWM_GLOBAL_UP_EN is set to 1. + * 0: Disable + * 1: Enable + */ + uint32_t op0_up_en:1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ + uint32_t op0_force_up:1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator1. + * Valid only when PWM_GLOBAL_UP_EN is set to 1. + * 0: Disable + * 1: Enable + */ + uint32_t op1_up_en:1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ + uint32_t op1_force_up:1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator2. + * Valid only when PWM_GLOBAL_UP_EN is set to 1. + * 0: Disable + * 1: Enable + */ + uint32_t op2_up_en:1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ + uint32_t op2_force_up:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + +/** Type of evt_en register + * Event enable register + */ +typedef union { + struct { + /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer0_stop_en:1; + /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer1_stop_en:1; + /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer2_stop_en:1; + /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer0_tez_en:1; + /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer1_tez_en:1; + /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer2_tez_en:1; + /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer0_tep_en:1; + /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer1_tep_en:1; + /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_timer2_tep_en:1; + /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op0_tea_en:1; + /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op1_tea_en:1; + /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op2_tea_en:1; + /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op0_teb_en:1; + /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op1_teb_en:1; + /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op2_teb_en:1; + /** evt_f0_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_f0_en:1; + /** evt_f1_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_f1_en:1; + /** evt_f2_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_f2_en:1; + /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_f0_clr_en:1; + /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_f1_clr_en:1; + /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_f2_clr_en:1; + /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_tz0_cbc_en:1; + /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_tz1_cbc_en:1; + /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_tz2_cbc_en:1; + /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_tz0_ost_en:1; + /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_tz1_ost_en:1; + /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_tz2_ost_en:1; + /** evt_cap0_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_cap0_en:1; + /** evt_cap1_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_cap1_en:1; + /** evt_cap2_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_cap2_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_evt_en_reg_t; + +/** Type of task_en register + * Task enable register + */ +typedef union { + struct { + /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cmpr0_a_up_en:1; + /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cmpr1_a_up_en:1; + /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cmpr2_a_up_en:1; + /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cmpr0_b_up_en:1; + /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cmpr1_b_up_en:1; + /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cmpr2_b_up_en:1; + /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_gen_stop_en:1; + /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_sync_en:1; + /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_sync_en:1; + /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_sync_en:1; + /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer0_period_up_en:1; + /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer1_period_up_en:1; + /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_timer2_period_up_en:1; + /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_tz0_ost_en:1; + /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_tz1_ost_en:1; + /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_tz2_ost_en:1; + /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_clr0_ost_en:1; + /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_clr1_ost_en:1; + /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_clr2_ost_en:1; + /** task_cap0_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cap0_en:1; + /** task_cap1_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cap1_en:1; + /** task_cap2_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive. + * 0: Disable + * 1: Enable + */ + uint32_t task_cap2_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} mcpwm_task_en_reg_t; + +/** Type of evt_en2 register + * Event enable register2 + */ +typedef union { + struct { + /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op0_tee1_en:1; + /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op1_tee1_en:1; + /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op2_tee1_en:1; + /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op0_tee2_en:1; + /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op1_tee2_en:1; + /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate. + * 0: Disable + * 1: Enable + */ + uint32_t evt_op2_tee2_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_evt_en2_reg_t; + +/** Type of opn_tstmp_e1 register + * Generatorn timer stamp E1 value register + */ +typedef union { + struct { + /** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E1 value register + */ + uint32_t opn_tstmp_e1:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_opn_tstmp_e1_reg_t; + +/** Type of opn_tstmp_e2 register + * Generatorn timer stamp E2 value register + */ +typedef union { + struct { + /** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E2 value register + */ + uint32_t opn_tstmp_e2:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_opn_tstmp_e2_reg_t; + +/** Type of clk register + * Global configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Status register */ +/** Type of timern_status register + * PWM timern status register. + */ +typedef union { + struct { + /** timern_value : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timern counter value. + */ + uint32_t timern_value:16; + /** timern_direction : RO; bitpos: [16]; default: 0; + * Represents current PWM timern counter direction. + * 0: Increment + * 1: Decrement + */ + uint32_t timern_direction:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} mcpwm_timern_status_reg_t; + +/** Type of fhn_status register + * Fault events status register + */ +typedef union { + struct { + /** tzn_cbc_on : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going. + * 0:No action + * 1: On going + */ + uint32_t tzn_cbc_on:1; + /** tzn_ost_on : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going. + * 0:No action + * 1: On going + */ + uint32_t tzn_ost_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mcpwm_fhn_status_reg_t; + +/** Type of cap_chn register + * CAPn capture value register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAPn + */ + uint32_t capn_value:32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + +/** Type of cap_status register + * Last capture trigger edge information register + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0. + * 0: Posedge + * 1: Negedge + */ + uint32_t cap0_edge:1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1. + * 0: Posedge + * 1: Negedge + */ + uint32_t cap1_edge:1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2. + * 0: Posedge + * 1: Negedge + */ + uint32_t cap2_edge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: Interrupt register */ +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena:1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena:1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena:1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena:1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena:1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena:1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena:1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena:1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena:1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_ena:1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_ena:1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_ena:1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_ena:1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_ena:1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_ena:1; + /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ + uint32_t cmpr0_tea_int_ena:1; + /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ + uint32_t cmpr1_tea_int_ena:1; + /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ + uint32_t cmpr2_tea_int_ena:1; + /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ + uint32_t cmpr0_teb_int_ena:1; + /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ + uint32_t cmpr1_teb_int_ena:1; + /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ + uint32_t cmpr2_teb_int_ena:1; + /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ + uint32_t tz0_cbc_int_ena:1; + /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ + uint32_t tz1_cbc_int_ena:1; + /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ + uint32_t tz2_cbc_int_ena:1; + /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_ena:1; + /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_ena:1; + /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_ena:1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_ena:1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_ena:1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ + uint32_t timer0_stop_int_raw:1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ + uint32_t timer1_stop_int_raw:1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ + uint32_t timer2_stop_int_raw:1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ + uint32_t timer0_tez_int_raw:1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ + uint32_t timer1_tez_int_raw:1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ + uint32_t timer2_tez_int_raw:1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ + uint32_t timer0_tep_int_raw:1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ + uint32_t timer1_tep_int_raw:1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ + uint32_t timer2_tep_int_raw:1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ + uint32_t fault0_int_raw:1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ + uint32_t fault1_int_raw:1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ + uint32_t fault2_int_raw:1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ + uint32_t fault0_clr_int_raw:1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ + uint32_t fault1_clr_int_raw:1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ + uint32_t fault2_clr_int_raw:1; + /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_raw:1; + /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_raw:1; + /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_raw:1; + /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_raw:1; + /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_raw:1; + /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_raw:1; + /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_raw:1; + /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_raw:1; + /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_raw:1; + /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ + uint32_t tz0_ost_int_raw:1; + /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ + uint32_t tz1_ost_int_raw:1; + /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ + uint32_t tz2_ost_int_raw:1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ + uint32_t cap0_int_raw:1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ + uint32_t cap1_int_raw:1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ + uint32_t cap2_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ + uint32_t timer0_stop_int_st:1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ + uint32_t timer1_stop_int_st:1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ + uint32_t timer2_stop_int_st:1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st:1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st:1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st:1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ + uint32_t timer0_tep_int_st:1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ + uint32_t timer1_tep_int_st:1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ + uint32_t timer2_tep_int_st:1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ + uint32_t fault0_int_st:1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ + uint32_t fault1_int_st:1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ + uint32_t fault2_int_st:1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ + uint32_t fault0_clr_int_st:1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ + uint32_t fault1_clr_int_st:1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ + uint32_t fault2_clr_int_st:1; + /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_st:1; + /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_st:1; + /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_st:1; + /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_st:1; + /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_st:1; + /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_st:1; + /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_st:1; + /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_st:1; + /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_st:1; + /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_st:1; + /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_st:1; + /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_st:1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ + uint32_t cap0_int_st:1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ + uint32_t cap1_int_st:1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ + uint32_t cap2_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr:1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr:1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr:1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr:1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr:1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr:1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr:1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr:1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr:1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_clr:1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_clr:1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_clr:1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_clr:1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_clr:1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_clr:1; + /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_clr:1; + /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_clr:1; + /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_clr:1; + /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_clr:1; + /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_clr:1; + /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_clr:1; + /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t tz0_cbc_int_clr:1; + /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t tz1_cbc_int_clr:1; + /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t tz2_cbc_int_clr:1; + /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_clr:1; + /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_clr:1; + /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_clr:1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_clr:1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_clr:1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: Version register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mcpwm_version_reg_t; + + +typedef struct { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timern_cfg0_reg_t timer0_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer0_cfg1; + volatile mcpwm_timern_sync_reg_t timer0_sync; + volatile mcpwm_timern_status_reg_t timer0_status; + volatile mcpwm_timern_cfg0_reg_t timer1_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer1_cfg1; + volatile mcpwm_timern_sync_reg_t timer1_sync; + volatile mcpwm_timern_status_reg_t timer1_status; + volatile mcpwm_timern_cfg0_reg_t timer2_cfg0; + volatile mcpwm_timern_cfg1_reg_t timer2_cfg1; + volatile mcpwm_timern_sync_reg_t timer2_sync; + volatile mcpwm_timern_status_reg_t timer2_status; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen0_cfg0; + volatile mcpwm_genn_force_reg_t gen0_force; + volatile mcpwm_genn_a_reg_t gen0_a; + volatile mcpwm_genn_b_reg_t gen0_b; + volatile mcpwm_dtn_cfg_reg_t dt0_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier0_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1; + volatile mcpwm_fhn_status_reg_t fh0_status; + volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen1_cfg0; + volatile mcpwm_genn_force_reg_t gen1_force; + volatile mcpwm_genn_a_reg_t gen1_a; + volatile mcpwm_genn_b_reg_t gen1_b; + volatile mcpwm_dtn_cfg_reg_t dt1_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier1_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1; + volatile mcpwm_fhn_status_reg_t fh1_status; + volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg; + volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a; + volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b; + volatile mcpwm_genn_cfg0_reg_t gen2_cfg0; + volatile mcpwm_genn_force_reg_t gen2_force; + volatile mcpwm_genn_a_reg_t gen2_a; + volatile mcpwm_genn_b_reg_t gen2_b; + volatile mcpwm_dtn_cfg_reg_t dt2_cfg; + volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg; + volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg; + volatile mcpwm_carriern_cfg_reg_t carrier2_cfg; + volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0; + volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1; + volatile mcpwm_fhn_status_reg_t fh2_status; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_evt_en_reg_t evt_en; + volatile mcpwm_task_en_reg_t task_en; + volatile mcpwm_evt_en2_reg_t evt_en2; + volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2; + volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2; + volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1; + volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM0; +extern mcpwm_dev_t MCPWM1; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_reg.h new file mode 100644 index 0000000000..c1e2197dbf --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_reg.h @@ -0,0 +1,5213 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MCPWM_CLK_CFG_REG register + * PWM clock prescaler register. + */ +#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0) +/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ +#define MCPWM_CLK_PRESCALE 0x000000FFU +#define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) +#define MCPWM_CLK_PRESCALE_V 0x000000FFU +#define MCPWM_CLK_PRESCALE_S 0 + +/** MCPWM_TIMER0_CFG0_REG register + * PWM timer0 period and update method configuration register. + */ +#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4) +/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer0, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER0_PRESCALE + 1) + */ +#define MCPWM_TIMER0_PRESCALE 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) +#define MCPWM_TIMER0_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER0_PRESCALE_S 0 +/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer0 + */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) +#define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER0_PERIOD_S 8 +/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer0 period. + * 0: Immediate + * 1: TEZ + * 2: Sync + * 3: TEZ or sync + * TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER0_CFG1_REG register + * PWM timer0 working mode and start/stop control register. + */ +#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8) +/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer0. + * 0: If PWM timer0 starts, then stops at TEZ + * 1: If timer0 starts, then stops at TEP + * 2: PWM timer0 starts and runs on + * 3: Timer0 starts and stops at the next TEZ + * 4: Timer0 starts and stops at the next TEP. + * TEP here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER0_START 0x00000007U +#define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) +#define MCPWM_TIMER0_START_V 0x00000007U +#define MCPWM_TIMER0_START_S 0 +/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer0. + * 0: Freeze + * 1: Increase mode + * 2: Decrease mode + * 3: Up-down mode + */ +#define MCPWM_TIMER0_MOD 0x00000003U +#define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) +#define MCPWM_TIMER0_MOD_V 0x00000003U +#define MCPWM_TIMER0_MOD_S 3 + +/** MCPWM_TIMER0_SYNC_REG register + * PWM timer0 sync function configuration register. + */ +#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc) +/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 reloading with phase on sync input event + * is enabled. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) +#define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER0_SYNCI_EN_S 0 +/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) +#define MCPWM_TIMER0_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER0_SYNC_SW_S 1 +/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer0 sync_out. + * 0: Sync_in + * 1: TEZ + * 2: TEP + * 3: Invalid, sync_out selects noting + */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer0 reload on sync event. + */ +#define MCPWM_TIMER0_PHASE 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) +#define MCPWM_TIMER0_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER0_PHASE_S 4 +/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer0's direction when timer0 mode is up-down mode. + * 0: Increase + * 1: Decrease + */ +#define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) +#define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER0_STATUS_REG register + * PWM timer0 status register. + */ +#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10) +/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer0 counter value. + */ +#define MCPWM_TIMER0_VALUE 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) +#define MCPWM_TIMER0_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER0_VALUE_S 0 +/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer0 counter direction. + * 0: Increment + * 1: Decrement + */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) +#define MCPWM_TIMER0_DIRECTION_V 0x00000001U +#define MCPWM_TIMER0_DIRECTION_S 16 + +/** MCPWM_TIMER1_CFG0_REG register + * PWM timer1 period and update method configuration register. + */ +#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14) +/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer1, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER1_PRESCALE + 1) + */ +#define MCPWM_TIMER1_PRESCALE 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) +#define MCPWM_TIMER1_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER1_PRESCALE_S 0 +/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer1 + */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) +#define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER1_PERIOD_S 8 +/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer1 period. + * 0: Immediate + * 1: TEZ + * 2: Sync + * 3: TEZ or sync + * TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER1_CFG1_REG register + * PWM timer1 working mode and start/stop control register. + */ +#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18) +/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer1. + * 0: If PWM timer1 starts, then stops at TEZ + * 1: If timer1 starts, then stops at TEP + * 2: PWM timer1 starts and runs on + * 3: Timer1 starts and stops at the next TEZ + * 4: Timer0 starts and stops at the next TEP. + * TEP here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER1_START 0x00000007U +#define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) +#define MCPWM_TIMER1_START_V 0x00000007U +#define MCPWM_TIMER1_START_S 0 +/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer1. + * 0: Freeze + * 1: Increase mode + * 2: Decrease mode + * 3: Up-down mode + */ +#define MCPWM_TIMER1_MOD 0x00000003U +#define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) +#define MCPWM_TIMER1_MOD_V 0x00000003U +#define MCPWM_TIMER1_MOD_S 3 + +/** MCPWM_TIMER1_SYNC_REG register + * PWM timer1 sync function configuration register. + */ +#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c) +/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer1 reloading with phase on sync input event + * is enabled. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) +#define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER1_SYNCI_EN_S 0 +/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) +#define MCPWM_TIMER1_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER1_SYNC_SW_S 1 +/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer1 sync_out. + * 0: Sync_in + * 1: TEZ + * 2: TEP + * 3: Invalid, sync_out selects noting + */ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer1 reload on sync event. + */ +#define MCPWM_TIMER1_PHASE 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) +#define MCPWM_TIMER1_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER1_PHASE_S 4 +/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer1's direction when timer1 mode is up-down mode. + * 0: Increase + * 1: Decrease + */ +#define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) +#define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER1_STATUS_REG register + * PWM timer1 status register. + */ +#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20) +/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer1 counter value. + */ +#define MCPWM_TIMER1_VALUE 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) +#define MCPWM_TIMER1_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER1_VALUE_S 0 +/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer1 counter direction. + * 0: Increment + * 1: Decrement + */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) +#define MCPWM_TIMER1_DIRECTION_V 0x00000001U +#define MCPWM_TIMER1_DIRECTION_S 16 + +/** MCPWM_TIMER2_CFG0_REG register + * PWM timer2 period and update method configuration register. + */ +#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24) +/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timer2, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMER2_PRESCALE + 1) + */ +#define MCPWM_TIMER2_PRESCALE 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) +#define MCPWM_TIMER2_PRESCALE_V 0x000000FFU +#define MCPWM_TIMER2_PRESCALE_S 0 +/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timer2 + */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) +#define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU +#define MCPWM_TIMER2_PERIOD_S 8 +/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timer2 period. + * 0: Immediate + * 1: TEZ + * 2: Sync + * 3: TEZ or sync + * TEZ here and below means timer equal zero event + */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 + +/** MCPWM_TIMER2_CFG1_REG register + * PWM timer2 working mode and start/stop control register. + */ +#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28) +/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer2. + * 0: If PWM timer2 starts, then stops at TEZ + * 1: If timer2 starts, then stops at TEP + * 2: PWM timer2 starts and runs on + * 3: Timer2 starts and stops at the next TEZ + * 4: Timer0 starts and stops at the next TEP. + * TEP here and below means the event that happens when the timer equals to period + */ +#define MCPWM_TIMER2_START 0x00000007U +#define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) +#define MCPWM_TIMER2_START_V 0x00000007U +#define MCPWM_TIMER2_START_S 0 +/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer2. + * 0: Freeze + * 1: Increase mode + * 2: Decrease mode + * 3: Up-down mode + */ +#define MCPWM_TIMER2_MOD 0x00000003U +#define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) +#define MCPWM_TIMER2_MOD_V 0x00000003U +#define MCPWM_TIMER2_MOD_S 3 + +/** MCPWM_TIMER2_SYNC_REG register + * PWM timer2 sync function configuration register. + */ +#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c) +/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer2 reloading with phase on sync input event + * is enabled. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) +#define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U +#define MCPWM_TIMER2_SYNCI_EN_S 0 +/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) +#define MCPWM_TIMER2_SYNC_SW_V 0x00000001U +#define MCPWM_TIMER2_SYNC_SW_S 1 +/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer2 sync_out. + * 0: Sync_in + * 1: TEZ + * 2: TEP + * 3: Invalid, sync_out selects noting + */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer2 reload on sync event. + */ +#define MCPWM_TIMER2_PHASE 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) +#define MCPWM_TIMER2_PHASE_V 0x0000FFFFU +#define MCPWM_TIMER2_PHASE_S 4 +/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer2's direction when timer2 mode is up-down mode. + * 0: Increase + * 1: Decrease + */ +#define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) +#define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) +#define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_PHASE_DIRECTION_S 20 + +/** MCPWM_TIMER2_STATUS_REG register + * PWM timer2 status register. + */ +#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30) +/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer2 counter value. + */ +#define MCPWM_TIMER2_VALUE 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) +#define MCPWM_TIMER2_VALUE_V 0x0000FFFFU +#define MCPWM_TIMER2_VALUE_S 0 +/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; + * Represents current PWM timer2 counter direction. + * 0: Increment + * 1: Decrement + */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) +#define MCPWM_TIMER2_DIRECTION_V 0x00000001U +#define MCPWM_TIMER2_DIRECTION_S 16 + +/** MCPWM_TIMER_SYNCI_CFG_REG register + * Synchronization input selection register for PWM timers. + */ +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34) +/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0. + * 1: PWM timer0 sync_out + * 2: PWM timer1 sync_out + * 3: PWM timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * Other values: No sync input selected + */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) +#define MCPWM_TIMER0_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER0_SYNCISEL_S 0 +/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1. + * 1: PWM timer0 sync_out + * 2: PWM timer1 sync_out + * 3: PWM timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * Other values: No sync input selected + */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) +#define MCPWM_TIMER1_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER1_SYNCISEL_S 3 +/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2. + * 1: PWM timer0 sync_out + * 2: PWM timer1 sync_out + * 3: PWM timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * Other values: No sync input selected + */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) +#define MCPWM_TIMER2_SYNCISEL_V 0x00000007U +#define MCPWM_TIMER2_SYNCISEL_S 6 +/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix. + * 0: Not invert + * 1: Invert + */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix. + * 0: Not invert + * 1: Invert + */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix. + * 0: Not invert + * 1: Invert + */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 + +/** MCPWM_OPERATOR_TIMERSEL_REG register + * PWM operator's timer select register + */ +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38) +/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0. + * 0: Timer0 + * 1: Timer1 + * 2: Timer2 + * 3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR0_TIMERSEL_S 0 +/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1. + * 0: Timer0 + * 1: Timer1 + * 2: Timer2 + * 3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2. + * 0: Timer0 + * 1: Timer1 + * 2: Timer2 + * 3: Invalid, will select timer2 + */ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U +#define MCPWM_OPERATOR2_TIMERSEL_S 4 + +/** MCPWM_GEN0_STMP_CFG_REG register + * Generator0 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c) +/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 0 time stamp A's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) +#define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR0_A_UPMETHOD_S 0 +/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 0 time stamp B's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) +#define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR0_B_UPMETHOD_S 4 +/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator0 time stamp A's shadow reg is transferred. + * 0: A's active reg has been updated with shadow register latest value. + * 1: A's shadow reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) +#define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR0_A_SHDW_FULL_S 8 +/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator0 time stamp B's shadow reg is transferred. + * 0: B's active reg has been updated with shadow register latest value. + * 1: B's shadow reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) +#define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR0_B_SHDW_FULL_S 9 + +/** MCPWM_GEN0_TSTMP_A_REG register + * Generator0 time stamp A's shadow register + */ +#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40) +/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 0 time stamp A's shadow register. + */ +#define MCPWM_CMPR0_A 0x0000FFFFU +#define MCPWM_CMPR0_A_M (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S) +#define MCPWM_CMPR0_A_V 0x0000FFFFU +#define MCPWM_CMPR0_A_S 0 + +/** MCPWM_GEN0_TSTMP_B_REG register + * Generator0 time stamp B's shadow register + */ +#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44) +/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 0 time stamp B's shadow register. + */ +#define MCPWM_CMPR0_B 0x0000FFFFU +#define MCPWM_CMPR0_B_M (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S) +#define MCPWM_CMPR0_B_V 0x0000FFFFU +#define MCPWM_CMPR0_B_S 0 + +/** MCPWM_GEN0_CFG0_REG register + * Generator0 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48) +/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 0's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 +/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 0 event_t0, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ +#define MCPWM_GEN0_T0_SEL 0x00000007U +#define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) +#define MCPWM_GEN0_T0_SEL_V 0x00000007U +#define MCPWM_GEN0_T0_SEL_S 4 +/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 0 event_t1, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ +#define MCPWM_GEN0_T1_SEL 0x00000007U +#define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) +#define MCPWM_GEN0_T1_SEL_V 0x00000007U +#define MCPWM_GEN0_T1_SEL_S 7 + +/** MCPWM_GEN0_FORCE_REG register + * Generator0 output signal force mode register. + */ +#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c) +/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator0. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: TEA + * Bit3 is set to 1: TEB + * Bit4 is set to 1: Sync + * Bit5 is set to 1: Disable update. TEA/B here and below means an event generated + * when the timer's value equals to that of register A/B. + */ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM0 A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM0 B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM0 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) +#define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM0 A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM0 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) +#define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM0 B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN0_A_REG register + * PWM0 output signal A actions configuration register + */ +#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50) +/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM0 A triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_UTEZ 0x00000003U +#define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) +#define MCPWM_GEN0_A_UTEZ_V 0x00000003U +#define MCPWM_GEN0_A_UTEZ_S 0 +/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM0 A triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_UTEP 0x00000003U +#define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) +#define MCPWM_GEN0_A_UTEP_V 0x00000003U +#define MCPWM_GEN0_A_UTEP_S 2 +/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM0 A triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_UTEA 0x00000003U +#define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) +#define MCPWM_GEN0_A_UTEA_V 0x00000003U +#define MCPWM_GEN0_A_UTEA_S 4 +/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM0 A triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_UTEB 0x00000003U +#define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) +#define MCPWM_GEN0_A_UTEB_V 0x00000003U +#define MCPWM_GEN0_A_UTEB_S 6 +/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM0 A triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_UT0 0x00000003U +#define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) +#define MCPWM_GEN0_A_UT0_V 0x00000003U +#define MCPWM_GEN0_A_UT0_S 8 +/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM0 A triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_UT1 0x00000003U +#define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) +#define MCPWM_GEN0_A_UT1_V 0x00000003U +#define MCPWM_GEN0_A_UT1_S 10 +/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM0 A triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_DTEZ 0x00000003U +#define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) +#define MCPWM_GEN0_A_DTEZ_V 0x00000003U +#define MCPWM_GEN0_A_DTEZ_S 12 +/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM0 A triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_DTEP 0x00000003U +#define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) +#define MCPWM_GEN0_A_DTEP_V 0x00000003U +#define MCPWM_GEN0_A_DTEP_S 14 +/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM0 A triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_DTEA 0x00000003U +#define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) +#define MCPWM_GEN0_A_DTEA_V 0x00000003U +#define MCPWM_GEN0_A_DTEA_S 16 +/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM0 A triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_DTEB 0x00000003U +#define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) +#define MCPWM_GEN0_A_DTEB_V 0x00000003U +#define MCPWM_GEN0_A_DTEB_S 18 +/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM0 A triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_DT0 0x00000003U +#define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) +#define MCPWM_GEN0_A_DT0_V 0x00000003U +#define MCPWM_GEN0_A_DT0_S 20 +/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM0 A triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_A_DT1 0x00000003U +#define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) +#define MCPWM_GEN0_A_DT1_V 0x00000003U +#define MCPWM_GEN0_A_DT1_S 22 + +/** MCPWM_GEN0_B_REG register + * PWM0 output signal B actions configuration register + */ +#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54) +/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM0 B triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_UTEZ 0x00000003U +#define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) +#define MCPWM_GEN0_B_UTEZ_V 0x00000003U +#define MCPWM_GEN0_B_UTEZ_S 0 +/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM0 B triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_UTEP 0x00000003U +#define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) +#define MCPWM_GEN0_B_UTEP_V 0x00000003U +#define MCPWM_GEN0_B_UTEP_S 2 +/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM0 B triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_UTEA 0x00000003U +#define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) +#define MCPWM_GEN0_B_UTEA_V 0x00000003U +#define MCPWM_GEN0_B_UTEA_S 4 +/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM0 B triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_UTEB 0x00000003U +#define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) +#define MCPWM_GEN0_B_UTEB_V 0x00000003U +#define MCPWM_GEN0_B_UTEB_S 6 +/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM0 B triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_UT0 0x00000003U +#define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) +#define MCPWM_GEN0_B_UT0_V 0x00000003U +#define MCPWM_GEN0_B_UT0_S 8 +/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM0 B triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_UT1 0x00000003U +#define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) +#define MCPWM_GEN0_B_UT1_V 0x00000003U +#define MCPWM_GEN0_B_UT1_S 10 +/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM0 B triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_DTEZ 0x00000003U +#define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) +#define MCPWM_GEN0_B_DTEZ_V 0x00000003U +#define MCPWM_GEN0_B_DTEZ_S 12 +/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM0 B triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_DTEP 0x00000003U +#define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) +#define MCPWM_GEN0_B_DTEP_V 0x00000003U +#define MCPWM_GEN0_B_DTEP_S 14 +/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM0 B triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_DTEA 0x00000003U +#define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) +#define MCPWM_GEN0_B_DTEA_V 0x00000003U +#define MCPWM_GEN0_B_DTEA_S 16 +/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM0 B triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_DTEB 0x00000003U +#define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) +#define MCPWM_GEN0_B_DTEB_V 0x00000003U +#define MCPWM_GEN0_B_DTEB_S 18 +/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM0 B triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_DT0 0x00000003U +#define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) +#define MCPWM_GEN0_B_DT0_V 0x00000003U +#define MCPWM_GEN0_B_DT0_S 20 +/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM0 B triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN0_B_DT1 0x00000003U +#define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) +#define MCPWM_GEN0_B_DT1_V 0x00000003U +#define MCPWM_GEN0_B_DT1_S 22 + +/** MCPWM_DT0_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58) +/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_DB0_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB0_FED_UPMETHOD_M (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S) +#define MCPWM_DB0_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB0_FED_UPMETHOD_S 0 +/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_DB0_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB0_RED_UPMETHOD_M (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S) +#define MCPWM_DB0_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB0_RED_UPMETHOD_S 4 +/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode. + * 0: fed/red take effect on different path separately + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB0_DEB_MODE (BIT(8)) +#define MCPWM_DB0_DEB_MODE_M (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S) +#define MCPWM_DB0_DEB_MODE_V 0x00000001U +#define MCPWM_DB0_DEB_MODE_S 8 +/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DB0_A_OUTSWAP (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_M (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S) +#define MCPWM_DB0_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB0_A_OUTSWAP_S 9 +/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DB0_B_OUTSWAP (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_M (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S) +#define MCPWM_DB0_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB0_B_OUTSWAP_S 10 +/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DB0_RED_INSEL (BIT(11)) +#define MCPWM_DB0_RED_INSEL_M (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S) +#define MCPWM_DB0_RED_INSEL_V 0x00000001U +#define MCPWM_DB0_RED_INSEL_S 11 +/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DB0_FED_INSEL (BIT(12)) +#define MCPWM_DB0_FED_INSEL_M (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S) +#define MCPWM_DB0_FED_INSEL_V 0x00000001U +#define MCPWM_DB0_FED_INSEL_S 12 +/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_M (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S) +#define MCPWM_DB0_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB0_RED_OUTINVERT_S 13 +/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_M (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S) +#define MCPWM_DB0_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB0_FED_OUTINVERT_S 14 +/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_M (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S) +#define MCPWM_DB0_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB0_A_OUTBYPASS_S 15 +/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_M (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S) +#define MCPWM_DB0_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB0_B_OUTBYPASS_S 16 +/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 0 clock selection. + * 0: PWM_clk + * 1: PT_clk + */ +#define MCPWM_DB0_CLK_SEL (BIT(17)) +#define MCPWM_DB0_CLK_SEL_M (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S) +#define MCPWM_DB0_CLK_SEL_V 0x00000001U +#define MCPWM_DB0_CLK_SEL_S 17 + +/** MCPWM_DT0_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c) +/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DB0_FED 0x0000FFFFU +#define MCPWM_DB0_FED_M (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S) +#define MCPWM_DB0_FED_V 0x0000FFFFU +#define MCPWM_DB0_FED_S 0 + +/** MCPWM_DT0_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60) +/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DB0_RED 0x0000FFFFU +#define MCPWM_DB0_RED_M (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S) +#define MCPWM_DB0_RED_V 0x0000FFFFU +#define MCPWM_DB0_RED_S 0 + +/** MCPWM_CARRIER0_CFG_REG register + * Carrier0 configuration register + */ +#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64) +/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier0. + * 0: Bypassed + * 1: Enabled + */ +#define MCPWM_CHOPPER0_EN (BIT(0)) +#define MCPWM_CHOPPER0_EN_M (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S) +#define MCPWM_CHOPPER0_EN_V 0x00000001U +#define MCPWM_CHOPPER0_EN_S 0 +/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier0 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + */ +#define MCPWM_CHOPPER0_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER0_PRESCALE_M (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S) +#define MCPWM_CHOPPER0_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER0_PRESCALE_S 1 +/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER0_DUTY / 8 + */ +#define MCPWM_CHOPPER0_DUTY 0x00000007U +#define MCPWM_CHOPPER0_DUTY_M (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S) +#define MCPWM_CHOPPER0_DUTY_V 0x00000007U +#define MCPWM_CHOPPER0_DUTY_S 5 +/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CHOPPER0_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER0_OSHTWTH_M (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S) +#define MCPWM_CHOPPER0_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER0_OSHTWTH_S 8 +/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM0 A and PWM0 B for this + * submodule. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_M (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S) +#define MCPWM_CHOPPER0_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER0_OUT_INVERT_S 12 +/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM0 A and PWM0 B for this + * submodule. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_M (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S) +#define MCPWM_CHOPPER0_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER0_IN_INVERT_S 13 + +/** MCPWM_FH0_CFG0_REG register + * PWM0 A and PWM0 B trip events actions configuration register + */ +#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68) +/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_SW_CBC (BIT(0)) +#define MCPWM_TZ0_SW_CBC_M (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S) +#define MCPWM_TZ0_SW_CBC_V 0x00000001U +#define MCPWM_TZ0_SW_CBC_S 0 +/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_F2_CBC (BIT(1)) +#define MCPWM_TZ0_F2_CBC_M (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S) +#define MCPWM_TZ0_F2_CBC_V 0x00000001U +#define MCPWM_TZ0_F2_CBC_S 1 +/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_F1_CBC (BIT(2)) +#define MCPWM_TZ0_F1_CBC_M (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S) +#define MCPWM_TZ0_F1_CBC_V 0x00000001U +#define MCPWM_TZ0_F1_CBC_S 2 +/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_F0_CBC (BIT(3)) +#define MCPWM_TZ0_F0_CBC_M (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S) +#define MCPWM_TZ0_F0_CBC_V 0x00000001U +#define MCPWM_TZ0_F0_CBC_S 3 +/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_SW_OST (BIT(4)) +#define MCPWM_TZ0_SW_OST_M (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S) +#define MCPWM_TZ0_SW_OST_V 0x00000001U +#define MCPWM_TZ0_SW_OST_S 4 +/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_F2_OST (BIT(5)) +#define MCPWM_TZ0_F2_OST_M (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S) +#define MCPWM_TZ0_F2_OST_V 0x00000001U +#define MCPWM_TZ0_F2_OST_S 5 +/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_F1_OST (BIT(6)) +#define MCPWM_TZ0_F1_OST_M (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S) +#define MCPWM_TZ0_F1_OST_V 0x00000001U +#define MCPWM_TZ0_F1_OST_S 6 +/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ0_F0_OST (BIT(7)) +#define MCPWM_TZ0_F0_OST_M (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S) +#define MCPWM_TZ0_F0_OST_V 0x00000001U +#define MCPWM_TZ0_F0_OST_S 7 +/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_A_CBC_D 0x00000003U +#define MCPWM_TZ0_A_CBC_D_M (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S) +#define MCPWM_TZ0_A_CBC_D_V 0x00000003U +#define MCPWM_TZ0_A_CBC_D_S 8 +/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_A_CBC_U 0x00000003U +#define MCPWM_TZ0_A_CBC_U_M (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S) +#define MCPWM_TZ0_A_CBC_U_V 0x00000003U +#define MCPWM_TZ0_A_CBC_U_S 10 +/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM0 A when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_A_OST_D 0x00000003U +#define MCPWM_TZ0_A_OST_D_M (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S) +#define MCPWM_TZ0_A_OST_D_V 0x00000003U +#define MCPWM_TZ0_A_OST_D_S 12 +/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM0 A when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_A_OST_U 0x00000003U +#define MCPWM_TZ0_A_OST_U_M (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S) +#define MCPWM_TZ0_A_OST_U_V 0x00000003U +#define MCPWM_TZ0_A_OST_U_S 14 +/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_B_CBC_D 0x00000003U +#define MCPWM_TZ0_B_CBC_D_M (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S) +#define MCPWM_TZ0_B_CBC_D_V 0x00000003U +#define MCPWM_TZ0_B_CBC_D_S 16 +/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_B_CBC_U 0x00000003U +#define MCPWM_TZ0_B_CBC_U_M (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S) +#define MCPWM_TZ0_B_CBC_U_V 0x00000003U +#define MCPWM_TZ0_B_CBC_U_S 18 +/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM0 B when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_B_OST_D 0x00000003U +#define MCPWM_TZ0_B_OST_D_M (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S) +#define MCPWM_TZ0_B_OST_D_V 0x00000003U +#define MCPWM_TZ0_B_OST_D_S 20 +/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM0 B when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ0_B_OST_U 0x00000003U +#define MCPWM_TZ0_B_OST_U_M (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S) +#define MCPWM_TZ0_B_OST_U_V 0x00000003U +#define MCPWM_TZ0_B_OST_U_S 22 + +/** MCPWM_FH0_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c) +/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_TZ0_CLR_OST (BIT(0)) +#define MCPWM_TZ0_CLR_OST_M (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S) +#define MCPWM_TZ0_CLR_OST_V 0x00000001U +#define MCPWM_TZ0_CLR_OST_S 0 +/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action. + * 0: Select nothing, will not refresh + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + */ +#define MCPWM_TZ0_CBCPULSE 0x00000003U +#define MCPWM_TZ0_CBCPULSE_M (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S) +#define MCPWM_TZ0_CBCPULSE_V 0x00000003U +#define MCPWM_TZ0_CBCPULSE_S 1 +/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_TZ0_FORCE_CBC (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_M (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S) +#define MCPWM_TZ0_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ0_FORCE_CBC_S 3 +/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_TZ0_FORCE_OST (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_M (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S) +#define MCPWM_TZ0_FORCE_OST_V 0x00000001U +#define MCPWM_TZ0_FORCE_OST_S 4 + +/** MCPWM_FH0_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70) +/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going. + * 0:No action + * 1: On going + */ +#define MCPWM_TZ0_CBC_ON (BIT(0)) +#define MCPWM_TZ0_CBC_ON_M (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S) +#define MCPWM_TZ0_CBC_ON_V 0x00000001U +#define MCPWM_TZ0_CBC_ON_S 0 +/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going. + * 0:No action + * 1: On going + */ +#define MCPWM_TZ0_OST_ON (BIT(1)) +#define MCPWM_TZ0_OST_ON_M (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S) +#define MCPWM_TZ0_OST_ON_V 0x00000001U +#define MCPWM_TZ0_OST_ON_S 1 + +/** MCPWM_GEN1_STMP_CFG_REG register + * Generator1 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74) +/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 1 time stamp A's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_CMPR1_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR1_A_UPMETHOD_M (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S) +#define MCPWM_CMPR1_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR1_A_UPMETHOD_S 0 +/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 1 time stamp B's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_CMPR1_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR1_B_UPMETHOD_M (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S) +#define MCPWM_CMPR1_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR1_B_UPMETHOD_S 4 +/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator1 time stamp A's shadow reg is transferred. + * 0: A's active reg has been updated with shadow register latest value. + * 1: A's shadow reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_M (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S) +#define MCPWM_CMPR1_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR1_A_SHDW_FULL_S 8 +/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator1 time stamp B's shadow reg is transferred. + * 0: B's active reg has been updated with shadow register latest value. + * 1: B's shadow reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_M (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S) +#define MCPWM_CMPR1_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR1_B_SHDW_FULL_S 9 + +/** MCPWM_GEN1_TSTMP_A_REG register + * Generator1 time stamp A's shadow register + */ +#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78) +/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 1 time stamp A's shadow register. + */ +#define MCPWM_CMPR1_A 0x0000FFFFU +#define MCPWM_CMPR1_A_M (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S) +#define MCPWM_CMPR1_A_V 0x0000FFFFU +#define MCPWM_CMPR1_A_S 0 + +/** MCPWM_GEN1_TSTMP_B_REG register + * Generator1 time stamp B's shadow register + */ +#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c) +/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 1 time stamp B's shadow register. + */ +#define MCPWM_CMPR1_B 0x0000FFFFU +#define MCPWM_CMPR1_B_M (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S) +#define MCPWM_CMPR1_B_V 0x0000FFFFU +#define MCPWM_CMPR1_B_S 0 + +/** MCPWM_GEN1_CFG0_REG register + * Generator1 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80) +/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 1's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 +/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 1 event_t0, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ +#define MCPWM_GEN1_T0_SEL 0x00000007U +#define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) +#define MCPWM_GEN1_T0_SEL_V 0x00000007U +#define MCPWM_GEN1_T0_SEL_S 4 +/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 1 event_t1, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ +#define MCPWM_GEN1_T1_SEL 0x00000007U +#define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) +#define MCPWM_GEN1_T1_SEL_V 0x00000007U +#define MCPWM_GEN1_T1_SEL_S 7 + +/** MCPWM_GEN1_FORCE_REG register + * Generator1 output signal force mode register. + */ +#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84) +/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator1. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: TEA + * Bit3 is set to 1: TEB + * Bit4 is set to 1: Sync + * Bit5 is set to 1: Disable update. TEA/B here and below means an event generated + * when the timer's value equals to that of register A/B. + */ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM1 A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM1 B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM1 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) +#define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM1 A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM1 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) +#define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM1 B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN1_A_REG register + * PWM1 output signal A actions configuration register + */ +#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88) +/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM1 A triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_UTEZ 0x00000003U +#define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) +#define MCPWM_GEN1_A_UTEZ_V 0x00000003U +#define MCPWM_GEN1_A_UTEZ_S 0 +/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM1 A triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_UTEP 0x00000003U +#define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) +#define MCPWM_GEN1_A_UTEP_V 0x00000003U +#define MCPWM_GEN1_A_UTEP_S 2 +/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM1 A triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_UTEA 0x00000003U +#define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) +#define MCPWM_GEN1_A_UTEA_V 0x00000003U +#define MCPWM_GEN1_A_UTEA_S 4 +/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM1 A triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_UTEB 0x00000003U +#define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) +#define MCPWM_GEN1_A_UTEB_V 0x00000003U +#define MCPWM_GEN1_A_UTEB_S 6 +/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM1 A triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_UT0 0x00000003U +#define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) +#define MCPWM_GEN1_A_UT0_V 0x00000003U +#define MCPWM_GEN1_A_UT0_S 8 +/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM1 A triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_UT1 0x00000003U +#define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) +#define MCPWM_GEN1_A_UT1_V 0x00000003U +#define MCPWM_GEN1_A_UT1_S 10 +/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM1 A triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_DTEZ 0x00000003U +#define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) +#define MCPWM_GEN1_A_DTEZ_V 0x00000003U +#define MCPWM_GEN1_A_DTEZ_S 12 +/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM1 A triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_DTEP 0x00000003U +#define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) +#define MCPWM_GEN1_A_DTEP_V 0x00000003U +#define MCPWM_GEN1_A_DTEP_S 14 +/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM1 A triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_DTEA 0x00000003U +#define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) +#define MCPWM_GEN1_A_DTEA_V 0x00000003U +#define MCPWM_GEN1_A_DTEA_S 16 +/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM1 A triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_DTEB 0x00000003U +#define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) +#define MCPWM_GEN1_A_DTEB_V 0x00000003U +#define MCPWM_GEN1_A_DTEB_S 18 +/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM1 A triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_DT0 0x00000003U +#define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) +#define MCPWM_GEN1_A_DT0_V 0x00000003U +#define MCPWM_GEN1_A_DT0_S 20 +/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM1 A triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_A_DT1 0x00000003U +#define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) +#define MCPWM_GEN1_A_DT1_V 0x00000003U +#define MCPWM_GEN1_A_DT1_S 22 + +/** MCPWM_GEN1_B_REG register + * PWM1 output signal B actions configuration register + */ +#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c) +/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM1 B triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_UTEZ 0x00000003U +#define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) +#define MCPWM_GEN1_B_UTEZ_V 0x00000003U +#define MCPWM_GEN1_B_UTEZ_S 0 +/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM1 B triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_UTEP 0x00000003U +#define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) +#define MCPWM_GEN1_B_UTEP_V 0x00000003U +#define MCPWM_GEN1_B_UTEP_S 2 +/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM1 B triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_UTEA 0x00000003U +#define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) +#define MCPWM_GEN1_B_UTEA_V 0x00000003U +#define MCPWM_GEN1_B_UTEA_S 4 +/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM1 B triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_UTEB 0x00000003U +#define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) +#define MCPWM_GEN1_B_UTEB_V 0x00000003U +#define MCPWM_GEN1_B_UTEB_S 6 +/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM1 B triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_UT0 0x00000003U +#define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) +#define MCPWM_GEN1_B_UT0_V 0x00000003U +#define MCPWM_GEN1_B_UT0_S 8 +/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM1 B triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_UT1 0x00000003U +#define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) +#define MCPWM_GEN1_B_UT1_V 0x00000003U +#define MCPWM_GEN1_B_UT1_S 10 +/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM1 B triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_DTEZ 0x00000003U +#define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) +#define MCPWM_GEN1_B_DTEZ_V 0x00000003U +#define MCPWM_GEN1_B_DTEZ_S 12 +/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM1 B triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_DTEP 0x00000003U +#define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) +#define MCPWM_GEN1_B_DTEP_V 0x00000003U +#define MCPWM_GEN1_B_DTEP_S 14 +/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM1 B triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_DTEA 0x00000003U +#define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) +#define MCPWM_GEN1_B_DTEA_V 0x00000003U +#define MCPWM_GEN1_B_DTEA_S 16 +/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM1 B triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_DTEB 0x00000003U +#define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) +#define MCPWM_GEN1_B_DTEB_V 0x00000003U +#define MCPWM_GEN1_B_DTEB_S 18 +/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM1 B triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_DT0 0x00000003U +#define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) +#define MCPWM_GEN1_B_DT0_V 0x00000003U +#define MCPWM_GEN1_B_DT0_S 20 +/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM1 B triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN1_B_DT1 0x00000003U +#define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) +#define MCPWM_GEN1_B_DT1_V 0x00000003U +#define MCPWM_GEN1_B_DT1_S 22 + +/** MCPWM_DT1_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90) +/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_DB1_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB1_FED_UPMETHOD_M (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S) +#define MCPWM_DB1_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB1_FED_UPMETHOD_S 0 +/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_DB1_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB1_RED_UPMETHOD_M (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S) +#define MCPWM_DB1_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB1_RED_UPMETHOD_S 4 +/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode. + * 0: fed/red take effect on different path separately + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB1_DEB_MODE (BIT(8)) +#define MCPWM_DB1_DEB_MODE_M (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S) +#define MCPWM_DB1_DEB_MODE_V 0x00000001U +#define MCPWM_DB1_DEB_MODE_S 8 +/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DB1_A_OUTSWAP (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_M (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S) +#define MCPWM_DB1_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB1_A_OUTSWAP_S 9 +/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DB1_B_OUTSWAP (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_M (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S) +#define MCPWM_DB1_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB1_B_OUTSWAP_S 10 +/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DB1_RED_INSEL (BIT(11)) +#define MCPWM_DB1_RED_INSEL_M (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S) +#define MCPWM_DB1_RED_INSEL_V 0x00000001U +#define MCPWM_DB1_RED_INSEL_S 11 +/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DB1_FED_INSEL (BIT(12)) +#define MCPWM_DB1_FED_INSEL_M (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S) +#define MCPWM_DB1_FED_INSEL_V 0x00000001U +#define MCPWM_DB1_FED_INSEL_S 12 +/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_M (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S) +#define MCPWM_DB1_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB1_RED_OUTINVERT_S 13 +/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_M (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S) +#define MCPWM_DB1_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB1_FED_OUTINVERT_S 14 +/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_M (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S) +#define MCPWM_DB1_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB1_A_OUTBYPASS_S 15 +/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_M (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S) +#define MCPWM_DB1_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB1_B_OUTBYPASS_S 16 +/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 1 clock selection. + * 0: PWM_clk + * 1: PT_clk + */ +#define MCPWM_DB1_CLK_SEL (BIT(17)) +#define MCPWM_DB1_CLK_SEL_M (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S) +#define MCPWM_DB1_CLK_SEL_V 0x00000001U +#define MCPWM_DB1_CLK_SEL_S 17 + +/** MCPWM_DT1_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94) +/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DB1_FED 0x0000FFFFU +#define MCPWM_DB1_FED_M (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S) +#define MCPWM_DB1_FED_V 0x0000FFFFU +#define MCPWM_DB1_FED_S 0 + +/** MCPWM_DT1_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98) +/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DB1_RED 0x0000FFFFU +#define MCPWM_DB1_RED_M (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S) +#define MCPWM_DB1_RED_V 0x0000FFFFU +#define MCPWM_DB1_RED_S 0 + +/** MCPWM_CARRIER1_CFG_REG register + * Carrier1 configuration register + */ +#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c) +/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier1. + * 0: Bypassed + * 1: Enabled + */ +#define MCPWM_CHOPPER1_EN (BIT(0)) +#define MCPWM_CHOPPER1_EN_M (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S) +#define MCPWM_CHOPPER1_EN_V 0x00000001U +#define MCPWM_CHOPPER1_EN_S 0 +/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier1 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1) + */ +#define MCPWM_CHOPPER1_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER1_PRESCALE_M (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S) +#define MCPWM_CHOPPER1_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER1_PRESCALE_S 1 +/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER1_DUTY / 8 + */ +#define MCPWM_CHOPPER1_DUTY 0x00000007U +#define MCPWM_CHOPPER1_DUTY_M (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S) +#define MCPWM_CHOPPER1_DUTY_V 0x00000007U +#define MCPWM_CHOPPER1_DUTY_S 5 +/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CHOPPER1_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER1_OSHTWTH_M (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S) +#define MCPWM_CHOPPER1_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER1_OSHTWTH_S 8 +/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM1 A and PWM1 B for this + * submodule. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_M (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S) +#define MCPWM_CHOPPER1_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER1_OUT_INVERT_S 12 +/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM1 A and PWM1 B for this + * submodule. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_M (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S) +#define MCPWM_CHOPPER1_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER1_IN_INVERT_S 13 + +/** MCPWM_FH1_CFG0_REG register + * PWM1 A and PWM1 B trip events actions configuration register + */ +#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0) +/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_SW_CBC (BIT(0)) +#define MCPWM_TZ1_SW_CBC_M (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S) +#define MCPWM_TZ1_SW_CBC_V 0x00000001U +#define MCPWM_TZ1_SW_CBC_S 0 +/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_F2_CBC (BIT(1)) +#define MCPWM_TZ1_F2_CBC_M (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S) +#define MCPWM_TZ1_F2_CBC_V 0x00000001U +#define MCPWM_TZ1_F2_CBC_S 1 +/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_F1_CBC (BIT(2)) +#define MCPWM_TZ1_F1_CBC_M (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S) +#define MCPWM_TZ1_F1_CBC_V 0x00000001U +#define MCPWM_TZ1_F1_CBC_S 2 +/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_F0_CBC (BIT(3)) +#define MCPWM_TZ1_F0_CBC_M (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S) +#define MCPWM_TZ1_F0_CBC_V 0x00000001U +#define MCPWM_TZ1_F0_CBC_S 3 +/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_SW_OST (BIT(4)) +#define MCPWM_TZ1_SW_OST_M (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S) +#define MCPWM_TZ1_SW_OST_V 0x00000001U +#define MCPWM_TZ1_SW_OST_S 4 +/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_F2_OST (BIT(5)) +#define MCPWM_TZ1_F2_OST_M (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S) +#define MCPWM_TZ1_F2_OST_V 0x00000001U +#define MCPWM_TZ1_F2_OST_S 5 +/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_F1_OST (BIT(6)) +#define MCPWM_TZ1_F1_OST_M (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S) +#define MCPWM_TZ1_F1_OST_V 0x00000001U +#define MCPWM_TZ1_F1_OST_S 6 +/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ1_F0_OST (BIT(7)) +#define MCPWM_TZ1_F0_OST_M (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S) +#define MCPWM_TZ1_F0_OST_V 0x00000001U +#define MCPWM_TZ1_F0_OST_S 7 +/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_A_CBC_D 0x00000003U +#define MCPWM_TZ1_A_CBC_D_M (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S) +#define MCPWM_TZ1_A_CBC_D_V 0x00000003U +#define MCPWM_TZ1_A_CBC_D_S 8 +/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_A_CBC_U 0x00000003U +#define MCPWM_TZ1_A_CBC_U_M (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S) +#define MCPWM_TZ1_A_CBC_U_V 0x00000003U +#define MCPWM_TZ1_A_CBC_U_S 10 +/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM1 A when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_A_OST_D 0x00000003U +#define MCPWM_TZ1_A_OST_D_M (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S) +#define MCPWM_TZ1_A_OST_D_V 0x00000003U +#define MCPWM_TZ1_A_OST_D_S 12 +/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM1 A when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_A_OST_U 0x00000003U +#define MCPWM_TZ1_A_OST_U_M (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S) +#define MCPWM_TZ1_A_OST_U_V 0x00000003U +#define MCPWM_TZ1_A_OST_U_S 14 +/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_B_CBC_D 0x00000003U +#define MCPWM_TZ1_B_CBC_D_M (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S) +#define MCPWM_TZ1_B_CBC_D_V 0x00000003U +#define MCPWM_TZ1_B_CBC_D_S 16 +/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_B_CBC_U 0x00000003U +#define MCPWM_TZ1_B_CBC_U_M (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S) +#define MCPWM_TZ1_B_CBC_U_V 0x00000003U +#define MCPWM_TZ1_B_CBC_U_S 18 +/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM1 B when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_B_OST_D 0x00000003U +#define MCPWM_TZ1_B_OST_D_M (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S) +#define MCPWM_TZ1_B_OST_D_V 0x00000003U +#define MCPWM_TZ1_B_OST_D_S 20 +/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM1 B when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ1_B_OST_U 0x00000003U +#define MCPWM_TZ1_B_OST_U_M (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S) +#define MCPWM_TZ1_B_OST_U_V 0x00000003U +#define MCPWM_TZ1_B_OST_U_S 22 + +/** MCPWM_FH1_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4) +/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_TZ1_CLR_OST (BIT(0)) +#define MCPWM_TZ1_CLR_OST_M (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S) +#define MCPWM_TZ1_CLR_OST_V 0x00000001U +#define MCPWM_TZ1_CLR_OST_S 0 +/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action. + * 0: Select nothing, will not refresh + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + */ +#define MCPWM_TZ1_CBCPULSE 0x00000003U +#define MCPWM_TZ1_CBCPULSE_M (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S) +#define MCPWM_TZ1_CBCPULSE_V 0x00000003U +#define MCPWM_TZ1_CBCPULSE_S 1 +/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_TZ1_FORCE_CBC (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_M (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S) +#define MCPWM_TZ1_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ1_FORCE_CBC_S 3 +/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_TZ1_FORCE_OST (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_M (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S) +#define MCPWM_TZ1_FORCE_OST_V 0x00000001U +#define MCPWM_TZ1_FORCE_OST_S 4 + +/** MCPWM_FH1_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8) +/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going. + * 0:No action + * 1: On going + */ +#define MCPWM_TZ1_CBC_ON (BIT(0)) +#define MCPWM_TZ1_CBC_ON_M (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S) +#define MCPWM_TZ1_CBC_ON_V 0x00000001U +#define MCPWM_TZ1_CBC_ON_S 0 +/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going. + * 0:No action + * 1: On going + */ +#define MCPWM_TZ1_OST_ON (BIT(1)) +#define MCPWM_TZ1_OST_ON_M (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S) +#define MCPWM_TZ1_OST_ON_V 0x00000001U +#define MCPWM_TZ1_OST_ON_S 1 + +/** MCPWM_GEN2_STMP_CFG_REG register + * Generator2 time stamp registers A and B transfer status and update method register + */ +#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac) +/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator 2 time stamp A's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_CMPR2_A_UPMETHOD 0x0000000FU +#define MCPWM_CMPR2_A_UPMETHOD_M (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S) +#define MCPWM_CMPR2_A_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR2_A_UPMETHOD_S 0 +/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator 2 time stamp B's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_CMPR2_B_UPMETHOD 0x0000000FU +#define MCPWM_CMPR2_B_UPMETHOD_M (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S) +#define MCPWM_CMPR2_B_UPMETHOD_V 0x0000000FU +#define MCPWM_CMPR2_B_UPMETHOD_S 4 +/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generator2 time stamp A's shadow reg is transferred. + * 0: A's active reg has been updated with shadow register latest value. + * 1: A's shadow reg is filled and waiting to be transferred to A's active reg + */ +#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_M (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S) +#define MCPWM_CMPR2_A_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR2_A_SHDW_FULL_S 8 +/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generator2 time stamp B's shadow reg is transferred. + * 0: B's active reg has been updated with shadow register latest value. + * 1: B's shadow reg is filled and waiting to be transferred to B's active reg + */ +#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_M (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S) +#define MCPWM_CMPR2_B_SHDW_FULL_V 0x00000001U +#define MCPWM_CMPR2_B_SHDW_FULL_S 9 + +/** MCPWM_GEN2_TSTMP_A_REG register + * Generator2 time stamp A's shadow register + */ +#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0) +/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 2 time stamp A's shadow register. + */ +#define MCPWM_CMPR2_A 0x0000FFFFU +#define MCPWM_CMPR2_A_M (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S) +#define MCPWM_CMPR2_A_V 0x0000FFFFU +#define MCPWM_CMPR2_A_S 0 + +/** MCPWM_GEN2_TSTMP_B_REG register + * Generator2 time stamp B's shadow register + */ +#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4) +/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator 2 time stamp B's shadow register. + */ +#define MCPWM_CMPR2_B 0x0000FFFFU +#define MCPWM_CMPR2_B_M (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S) +#define MCPWM_CMPR2_B_V 0x0000FFFFU +#define MCPWM_CMPR2_B_S 0 + +/** MCPWM_GEN2_CFG0_REG register + * Generator2 fault event T0 and T1 configuration register + */ +#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8) +/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator 2's active register. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 +/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator 2 event_t0, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ +#define MCPWM_GEN2_T0_SEL 0x00000007U +#define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) +#define MCPWM_GEN2_T0_SEL_V 0x00000007U +#define MCPWM_GEN2_T0_SEL_S 4 +/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator 2 event_t1, take effect immediately. + * 0: fault_event0 + * 1: fault_event1 + * 2: fault_event2 + * 3: sync_taken + * 4: Invalid, Select nothing + */ +#define MCPWM_GEN2_T1_SEL 0x00000007U +#define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) +#define MCPWM_GEN2_T1_SEL_V 0x00000007U +#define MCPWM_GEN2_T1_SEL_S 7 + +/** MCPWM_GEN2_FORCE_REG register + * Generator2 output signal force mode register. + */ +#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc) +/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator2. + * 0: Immediately + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: TEA + * Bit3 is set to 1: TEB + * Bit4 is set to 1: Sync + * Bit5 is set to 1: Disable update. TEA/B here and below means an event generated + * when the timer's value equals to that of register A/B. + */ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 +/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM2 A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM2 B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM2 + * A, a toggle will trigger a force event. + */ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) +#define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM2 A. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for PWM2 + * B, a toggle will trigger a force event. + */ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) +#define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM2 B. + * 0: Disabled + * 1: Low + * 2: High + * 3: Disabled + */ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 + +/** MCPWM_GEN2_A_REG register + * PWM2 output signal A actions configuration register + */ +#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0) +/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM2 A triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_UTEZ 0x00000003U +#define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) +#define MCPWM_GEN2_A_UTEZ_V 0x00000003U +#define MCPWM_GEN2_A_UTEZ_S 0 +/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM2 A triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_UTEP 0x00000003U +#define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) +#define MCPWM_GEN2_A_UTEP_V 0x00000003U +#define MCPWM_GEN2_A_UTEP_S 2 +/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM2 A triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_UTEA 0x00000003U +#define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) +#define MCPWM_GEN2_A_UTEA_V 0x00000003U +#define MCPWM_GEN2_A_UTEA_S 4 +/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM2 A triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_UTEB 0x00000003U +#define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) +#define MCPWM_GEN2_A_UTEB_V 0x00000003U +#define MCPWM_GEN2_A_UTEB_S 6 +/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM2 A triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_UT0 0x00000003U +#define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) +#define MCPWM_GEN2_A_UT0_V 0x00000003U +#define MCPWM_GEN2_A_UT0_S 8 +/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM2 A triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_UT1 0x00000003U +#define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) +#define MCPWM_GEN2_A_UT1_V 0x00000003U +#define MCPWM_GEN2_A_UT1_S 10 +/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM2 A triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_DTEZ 0x00000003U +#define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) +#define MCPWM_GEN2_A_DTEZ_V 0x00000003U +#define MCPWM_GEN2_A_DTEZ_S 12 +/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM2 A triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_DTEP 0x00000003U +#define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) +#define MCPWM_GEN2_A_DTEP_V 0x00000003U +#define MCPWM_GEN2_A_DTEP_S 14 +/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM2 A triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_DTEA 0x00000003U +#define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) +#define MCPWM_GEN2_A_DTEA_V 0x00000003U +#define MCPWM_GEN2_A_DTEA_S 16 +/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM2 A triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_DTEB 0x00000003U +#define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) +#define MCPWM_GEN2_A_DTEB_V 0x00000003U +#define MCPWM_GEN2_A_DTEB_S 18 +/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM2 A triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_DT0 0x00000003U +#define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) +#define MCPWM_GEN2_A_DT0_V 0x00000003U +#define MCPWM_GEN2_A_DT0_S 20 +/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM2 A triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_A_DT1 0x00000003U +#define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) +#define MCPWM_GEN2_A_DT1_V 0x00000003U +#define MCPWM_GEN2_A_DT1_S 22 + +/** MCPWM_GEN2_B_REG register + * PWM2 output signal B actions configuration register + */ +#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4) +/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM2 B triggered by event TEZ when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_UTEZ 0x00000003U +#define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) +#define MCPWM_GEN2_B_UTEZ_V 0x00000003U +#define MCPWM_GEN2_B_UTEZ_S 0 +/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM2 B triggered by event TEP when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_UTEP 0x00000003U +#define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) +#define MCPWM_GEN2_B_UTEP_V 0x00000003U +#define MCPWM_GEN2_B_UTEP_S 2 +/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM2 B triggered by event TEA when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_UTEA 0x00000003U +#define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) +#define MCPWM_GEN2_B_UTEA_V 0x00000003U +#define MCPWM_GEN2_B_UTEA_S 4 +/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM2 B triggered by event TEB when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_UTEB 0x00000003U +#define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) +#define MCPWM_GEN2_B_UTEB_V 0x00000003U +#define MCPWM_GEN2_B_UTEB_S 6 +/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM2 B triggered by event_t0 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_UT0 0x00000003U +#define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) +#define MCPWM_GEN2_B_UT0_V 0x00000003U +#define MCPWM_GEN2_B_UT0_S 8 +/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM2 B triggered by event_t1 when timer increasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_UT1 0x00000003U +#define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) +#define MCPWM_GEN2_B_UT1_V 0x00000003U +#define MCPWM_GEN2_B_UT1_S 10 +/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM2 B triggered by event TEZ when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_DTEZ 0x00000003U +#define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) +#define MCPWM_GEN2_B_DTEZ_V 0x00000003U +#define MCPWM_GEN2_B_DTEZ_S 12 +/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM2 B triggered by event TEP when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_DTEP 0x00000003U +#define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) +#define MCPWM_GEN2_B_DTEP_V 0x00000003U +#define MCPWM_GEN2_B_DTEP_S 14 +/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM2 B triggered by event TEA when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_DTEA 0x00000003U +#define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) +#define MCPWM_GEN2_B_DTEA_V 0x00000003U +#define MCPWM_GEN2_B_DTEA_S 16 +/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM2 B triggered by event TEB when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_DTEB 0x00000003U +#define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) +#define MCPWM_GEN2_B_DTEB_V 0x00000003U +#define MCPWM_GEN2_B_DTEB_S 18 +/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM2 B triggered by event_t0 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_DT0 0x00000003U +#define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) +#define MCPWM_GEN2_B_DT0_V 0x00000003U +#define MCPWM_GEN2_B_DT0_S 20 +/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM2 B triggered by event_t1 when timer decreasing. + * 0: No change + * 1: Low + * 2: High + * 3: Toggle + */ +#define MCPWM_GEN2_B_DT1 0x00000003U +#define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) +#define MCPWM_GEN2_B_DT1_V 0x00000003U +#define MCPWM_GEN2_B_DT1_S 22 + +/** MCPWM_DT2_CFG_REG register + * Dead time configuration register + */ +#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8) +/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_DB2_FED_UPMETHOD 0x0000000FU +#define MCPWM_DB2_FED_UPMETHOD_M (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S) +#define MCPWM_DB2_FED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB2_FED_UPMETHOD_S 0 +/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register. + * 0: Immediate + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + * Bit2 is set to 1: Sync + * Bit3 is set to 1: Disable the update + */ +#define MCPWM_DB2_RED_UPMETHOD 0x0000000FU +#define MCPWM_DB2_RED_UPMETHOD_M (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S) +#define MCPWM_DB2_RED_UPMETHOD_V 0x0000000FU +#define MCPWM_DB2_RED_UPMETHOD_S 4 +/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode. + * 0: fed/red take effect on different path separately + * 1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ +#define MCPWM_DB2_DEB_MODE (BIT(8)) +#define MCPWM_DB2_DEB_MODE_M (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S) +#define MCPWM_DB2_DEB_MODE_V 0x00000001U +#define MCPWM_DB2_DEB_MODE_S 8 +/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ +#define MCPWM_DB2_A_OUTSWAP (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_M (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S) +#define MCPWM_DB2_A_OUTSWAP_V 0x00000001U +#define MCPWM_DB2_A_OUTSWAP_S 9 +/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ +#define MCPWM_DB2_B_OUTSWAP (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_M (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S) +#define MCPWM_DB2_B_OUTSWAP_V 0x00000001U +#define MCPWM_DB2_B_OUTSWAP_S 10 +/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ +#define MCPWM_DB2_RED_INSEL (BIT(11)) +#define MCPWM_DB2_RED_INSEL_M (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S) +#define MCPWM_DB2_RED_INSEL_V 0x00000001U +#define MCPWM_DB2_RED_INSEL_S 11 +/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ +#define MCPWM_DB2_FED_INSEL (BIT(12)) +#define MCPWM_DB2_FED_INSEL_M (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S) +#define MCPWM_DB2_FED_INSEL_V 0x00000001U +#define MCPWM_DB2_FED_INSEL_S 12 +/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ +#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_M (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S) +#define MCPWM_DB2_RED_OUTINVERT_V 0x00000001U +#define MCPWM_DB2_RED_OUTINVERT_S 13 +/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ +#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_M (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S) +#define MCPWM_DB2_FED_OUTINVERT_V 0x00000001U +#define MCPWM_DB2_FED_OUTINVERT_S 14 +/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ +#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_M (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S) +#define MCPWM_DB2_A_OUTBYPASS_V 0x00000001U +#define MCPWM_DB2_A_OUTBYPASS_S 15 +/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ +#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_M (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S) +#define MCPWM_DB2_B_OUTBYPASS_V 0x00000001U +#define MCPWM_DB2_B_OUTBYPASS_S 16 +/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0; + * Configures dead time generator 2 clock selection. + * 0: PWM_clk + * 1: PT_clk + */ +#define MCPWM_DB2_CLK_SEL (BIT(17)) +#define MCPWM_DB2_CLK_SEL_M (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S) +#define MCPWM_DB2_CLK_SEL_V 0x00000001U +#define MCPWM_DB2_CLK_SEL_S 17 + +/** MCPWM_DT2_FED_CFG_REG register + * Falling edge delay (FED) shadow register + */ +#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc) +/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ +#define MCPWM_DB2_FED 0x0000FFFFU +#define MCPWM_DB2_FED_M (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S) +#define MCPWM_DB2_FED_V 0x0000FFFFU +#define MCPWM_DB2_FED_S 0 + +/** MCPWM_DT2_RED_CFG_REG register + * Rising edge delay (RED) shadow register + */ +#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0) +/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ +#define MCPWM_DB2_RED 0x0000FFFFU +#define MCPWM_DB2_RED_M (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S) +#define MCPWM_DB2_RED_V 0x0000FFFFU +#define MCPWM_DB2_RED_S 0 + +/** MCPWM_CARRIER2_CFG_REG register + * Carrier2 configuration register + */ +#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4) +/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier2. + * 0: Bypassed + * 1: Enabled + */ +#define MCPWM_CHOPPER2_EN (BIT(0)) +#define MCPWM_CHOPPER2_EN_M (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S) +#define MCPWM_CHOPPER2_EN_V 0x00000001U +#define MCPWM_CHOPPER2_EN_S 0 +/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier2 clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1) + */ +#define MCPWM_CHOPPER2_PRESCALE 0x0000000FU +#define MCPWM_CHOPPER2_PRESCALE_M (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S) +#define MCPWM_CHOPPER2_PRESCALE_V 0x0000000FU +#define MCPWM_CHOPPER2_PRESCALE_S 1 +/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER2_DUTY / 8 + */ +#define MCPWM_CHOPPER2_DUTY 0x00000007U +#define MCPWM_CHOPPER2_DUTY_M (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S) +#define MCPWM_CHOPPER2_DUTY_V 0x00000007U +#define MCPWM_CHOPPER2_DUTY_S 5 +/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ +#define MCPWM_CHOPPER2_OSHTWTH 0x0000000FU +#define MCPWM_CHOPPER2_OSHTWTH_M (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S) +#define MCPWM_CHOPPER2_OSHTWTH_V 0x0000000FU +#define MCPWM_CHOPPER2_OSHTWTH_S 8 +/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM2 A and PWM2 B for this + * submodule. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_M (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S) +#define MCPWM_CHOPPER2_OUT_INVERT_V 0x00000001U +#define MCPWM_CHOPPER2_OUT_INVERT_S 12 +/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM2 A and PWM2 B for this + * submodule. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_M (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S) +#define MCPWM_CHOPPER2_IN_INVERT_V 0x00000001U +#define MCPWM_CHOPPER2_IN_INVERT_S 13 + +/** MCPWM_FH2_CFG0_REG register + * PWM2 A and PWM2 B trip events actions configuration register + */ +#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8) +/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_SW_CBC (BIT(0)) +#define MCPWM_TZ2_SW_CBC_M (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S) +#define MCPWM_TZ2_SW_CBC_V 0x00000001U +#define MCPWM_TZ2_SW_CBC_S 0 +/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_F2_CBC (BIT(1)) +#define MCPWM_TZ2_F2_CBC_M (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S) +#define MCPWM_TZ2_F2_CBC_V 0x00000001U +#define MCPWM_TZ2_F2_CBC_S 1 +/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_F1_CBC (BIT(2)) +#define MCPWM_TZ2_F1_CBC_M (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S) +#define MCPWM_TZ2_F1_CBC_V 0x00000001U +#define MCPWM_TZ2_F1_CBC_S 2 +/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_F0_CBC (BIT(3)) +#define MCPWM_TZ2_F0_CBC_M (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S) +#define MCPWM_TZ2_F0_CBC_V 0x00000001U +#define MCPWM_TZ2_F0_CBC_S 3 +/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_SW_OST (BIT(4)) +#define MCPWM_TZ2_SW_OST_M (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S) +#define MCPWM_TZ2_SW_OST_V 0x00000001U +#define MCPWM_TZ2_SW_OST_S 4 +/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_F2_OST (BIT(5)) +#define MCPWM_TZ2_F2_OST_M (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S) +#define MCPWM_TZ2_F2_OST_V 0x00000001U +#define MCPWM_TZ2_F2_OST_S 5 +/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_F1_OST (BIT(6)) +#define MCPWM_TZ2_F1_OST_M (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S) +#define MCPWM_TZ2_F1_OST_V 0x00000001U +#define MCPWM_TZ2_F1_OST_S 6 +/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TZ2_F0_OST (BIT(7)) +#define MCPWM_TZ2_F0_OST_M (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S) +#define MCPWM_TZ2_F0_OST_V 0x00000001U +#define MCPWM_TZ2_F0_OST_S 7 +/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_A_CBC_D 0x00000003U +#define MCPWM_TZ2_A_CBC_D_M (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S) +#define MCPWM_TZ2_A_CBC_D_V 0x00000003U +#define MCPWM_TZ2_A_CBC_D_S 8 +/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_A_CBC_U 0x00000003U +#define MCPWM_TZ2_A_CBC_U_M (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S) +#define MCPWM_TZ2_A_CBC_U_V 0x00000003U +#define MCPWM_TZ2_A_CBC_U_S 10 +/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM2 A when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_A_OST_D 0x00000003U +#define MCPWM_TZ2_A_OST_D_M (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S) +#define MCPWM_TZ2_A_OST_D_V 0x00000003U +#define MCPWM_TZ2_A_OST_D_S 12 +/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM2 A when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_A_OST_U 0x00000003U +#define MCPWM_TZ2_A_OST_U_M (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S) +#define MCPWM_TZ2_A_OST_U_V 0x00000003U +#define MCPWM_TZ2_A_OST_U_S 14 +/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer + * is decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_B_CBC_D 0x00000003U +#define MCPWM_TZ2_B_CBC_D_M (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S) +#define MCPWM_TZ2_B_CBC_D_V 0x00000003U +#define MCPWM_TZ2_B_CBC_D_S 16 +/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer + * is increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_B_CBC_U 0x00000003U +#define MCPWM_TZ2_B_CBC_U_M (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S) +#define MCPWM_TZ2_B_CBC_U_V 0x00000003U +#define MCPWM_TZ2_B_CBC_U_S 18 +/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM2 B when fault event occurs and timer is + * decreasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_B_OST_D 0x00000003U +#define MCPWM_TZ2_B_OST_D_M (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S) +#define MCPWM_TZ2_B_OST_D_V 0x00000003U +#define MCPWM_TZ2_B_OST_D_S 20 +/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM2 B when fault event occurs and timer is + * increasing. + * 0: Do nothing + * 1: Force low + * 2: Force high + * 3: Toggle + */ +#define MCPWM_TZ2_B_OST_U 0x00000003U +#define MCPWM_TZ2_B_OST_U_M (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S) +#define MCPWM_TZ2_B_OST_U_V 0x00000003U +#define MCPWM_TZ2_B_OST_U_S 22 + +/** MCPWM_FH2_CFG1_REG register + * Software triggers for fault handler actions configuration register + */ +#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc) +/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ +#define MCPWM_TZ2_CLR_OST (BIT(0)) +#define MCPWM_TZ2_CLR_OST_M (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S) +#define MCPWM_TZ2_CLR_OST_V 0x00000001U +#define MCPWM_TZ2_CLR_OST_S 0 +/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action. + * 0: Select nothing, will not refresh + * Bit0 is set to 1: TEZ + * Bit1 is set to 1: TEP + */ +#define MCPWM_TZ2_CBCPULSE 0x00000003U +#define MCPWM_TZ2_CBCPULSE_M (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S) +#define MCPWM_TZ2_CBCPULSE_V 0x00000003U +#define MCPWM_TZ2_CBCPULSE_S 1 +/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ +#define MCPWM_TZ2_FORCE_CBC (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_M (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S) +#define MCPWM_TZ2_FORCE_CBC_V 0x00000001U +#define MCPWM_TZ2_FORCE_CBC_S 3 +/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ +#define MCPWM_TZ2_FORCE_OST (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_M (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S) +#define MCPWM_TZ2_FORCE_OST_V 0x00000001U +#define MCPWM_TZ2_FORCE_OST_S 4 + +/** MCPWM_FH2_STATUS_REG register + * Fault events status register + */ +#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0) +/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going. + * 0:No action + * 1: On going + */ +#define MCPWM_TZ2_CBC_ON (BIT(0)) +#define MCPWM_TZ2_CBC_ON_M (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S) +#define MCPWM_TZ2_CBC_ON_V 0x00000001U +#define MCPWM_TZ2_CBC_ON_S 0 +/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going. + * 0:No action + * 1: On going + */ +#define MCPWM_TZ2_OST_ON (BIT(1)) +#define MCPWM_TZ2_OST_ON_M (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S) +#define MCPWM_TZ2_OST_ON_V 0x00000001U +#define MCPWM_TZ2_OST_ON_S 1 + +/** MCPWM_FAULT_DETECT_REG register + * Fault detection configuration and status register + */ +#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4) +/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation. + * 0: Disable + * 1: Enable + */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) +#define MCPWM_F0_EN_V 0x00000001U +#define MCPWM_F0_EN_S 0 +/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation. + * 0: Disable + * 1: Enable + */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) +#define MCPWM_F1_EN_V 0x00000001U +#define MCPWM_F1_EN_S 1 +/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation. + * 0: Disable + * 1: Enable + */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) +#define MCPWM_F2_EN_V 0x00000001U +#define MCPWM_F2_EN_S 2 +/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix. + * 0: Level low + * 1: Level high + */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) +#define MCPWM_F0_POLE_V 0x00000001U +#define MCPWM_F0_POLE_S 3 +/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix. + * 0: Level low + * 1: Level high + */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) +#define MCPWM_F1_POLE_V 0x00000001U +#define MCPWM_F1_POLE_S 4 +/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix. + * 0: Level low + * 1: Level high + */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) +#define MCPWM_F2_POLE_V 0x00000001U +#define MCPWM_F2_POLE_S 5 +/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going. + * 0: No action + * 1: On going + */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) +#define MCPWM_EVENT_F0_V 0x00000001U +#define MCPWM_EVENT_F0_S 6 +/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going. + * 0: No action + * 1: On going + */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) +#define MCPWM_EVENT_F1_V 0x00000001U +#define MCPWM_EVENT_F1_S 7 +/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going. + * 0: No action + * 1: On going + */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) +#define MCPWM_EVENT_F2_V 0x00000001U +#define MCPWM_EVENT_F2_S 8 + +/** MCPWM_CAP_TIMER_CFG_REG register + * Capture timer configuration register + */ +#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8) +/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment. + * 0: Disable + * 1: Enable + */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) +#define MCPWM_CAP_TIMER_EN_V 0x00000001U +#define MCPWM_CAP_TIMER_EN_S 0 +/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync. + * 0: Disable + * 1: Enable + */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) +#define MCPWM_CAP_SYNCI_EN_V 0x00000001U +#define MCPWM_CAP_SYNCI_EN_S 1 +/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input. + * 0: None + * 1: Timer0 sync_out + * 2: Timer1 sync_out + * 3: Timer2 sync_out + * 4: SYNC0 from GPIO matrix + * 5: SYNC1 from GPIO matrix + * 6: SYNC2 from GPIO matrix + * 7: None + */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) +#define MCPWM_CAP_SYNCI_SEL_V 0x00000007U +#define MCPWM_CAP_SYNCI_SEL_S 2 +/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1. + * 0: Invalid, No effect + * 1: Trigger a capture timer sync, capture timer is loaded with value in phase + * register + */ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) +#define MCPWM_CAP_SYNC_SW_V 0x00000001U +#define MCPWM_CAP_SYNC_SW_S 5 + +/** MCPWM_CAP_TIMER_PHASE_REG register + * Capture timer sync phase register + */ +#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec) +/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ +#define MCPWM_CAP_PHASE 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFFU +#define MCPWM_CAP_PHASE_S 0 + +/** MCPWM_CAP_CH0_CFG_REG register + * Capture channel 0 configuration register + */ +#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0) +/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 0. + * 0: Disable + * 1: Enable + */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) +#define MCPWM_CAP0_EN_V 0x00000001U +#define MCPWM_CAP0_EN_S 0 +/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 0 after prescaling is used. + * 0: None + * Bit0 is set to 1: Rnable capture on the negative edge + * Bit1 is set to 1: Enable capture on the positive edge + */ +#define MCPWM_CAP0_MODE 0x00000003U +#define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) +#define MCPWM_CAP0_MODE_V 0x00000003U +#define MCPWM_CAP0_MODE_S 1 +/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on positive edge of CAP0. Prescale value = + * PWM_CAP0_PRESCALE + 1 + */ +#define MCPWM_CAP0_PRESCALE 0x000000FFU +#define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) +#define MCPWM_CAP0_PRESCALE_V 0x000000FFU +#define MCPWM_CAP0_PRESCALE_S 3 +/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP0 from GPIO matrix before prescale. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) +#define MCPWM_CAP0_IN_INVERT_V 0x00000001U +#define MCPWM_CAP0_IN_INVERT_S 11 +/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture. + * 0: Invalid, No effect + * 1: Trigger a software forced capture on channel 0 + */ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) +#define MCPWM_CAP0_SW_V 0x00000001U +#define MCPWM_CAP0_SW_S 12 + +/** MCPWM_CAP_CH1_CFG_REG register + * Capture channel 1 configuration register + */ +#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4) +/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 1. + * 0: Disable + * 1: Enable + */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) +#define MCPWM_CAP1_EN_V 0x00000001U +#define MCPWM_CAP1_EN_S 0 +/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 1 after prescaling is used. + * 0: None + * Bit0 is set to 1: Rnable capture on the negative edge + * Bit1 is set to 1: Enable capture on the positive edge + */ +#define MCPWM_CAP1_MODE 0x00000003U +#define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) +#define MCPWM_CAP1_MODE_V 0x00000003U +#define MCPWM_CAP1_MODE_S 1 +/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on positive edge of CAP1. Prescale value = + * PWM_CAP1_PRESCALE + 1 + */ +#define MCPWM_CAP1_PRESCALE 0x000000FFU +#define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) +#define MCPWM_CAP1_PRESCALE_V 0x000000FFU +#define MCPWM_CAP1_PRESCALE_S 3 +/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP1 from GPIO matrix before prescale. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) +#define MCPWM_CAP1_IN_INVERT_V 0x00000001U +#define MCPWM_CAP1_IN_INVERT_S 11 +/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture. + * 0: Invalid, No effect + * 1: Trigger a software forced capture on channel 1 + */ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) +#define MCPWM_CAP1_SW_V 0x00000001U +#define MCPWM_CAP1_SW_S 12 + +/** MCPWM_CAP_CH2_CFG_REG register + * Capture channel 2 configuration register + */ +#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8) +/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel 2. + * 0: Disable + * 1: Enable + */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) +#define MCPWM_CAP2_EN_V 0x00000001U +#define MCPWM_CAP2_EN_S 0 +/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel 2 after prescaling is used. + * 0: None + * Bit0 is set to 1: Rnable capture on the negative edge + * Bit1 is set to 1: Enable capture on the positive edge + */ +#define MCPWM_CAP2_MODE 0x00000003U +#define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) +#define MCPWM_CAP2_MODE_V 0x00000003U +#define MCPWM_CAP2_MODE_S 1 +/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on positive edge of CAP2. Prescale value = + * PWM_CAP2_PRESCALE + 1 + */ +#define MCPWM_CAP2_PRESCALE 0x000000FFU +#define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) +#define MCPWM_CAP2_PRESCALE_V 0x000000FFU +#define MCPWM_CAP2_PRESCALE_S 3 +/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAP2 from GPIO matrix before prescale. + * 0: Normal + * 1: Invert + */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) +#define MCPWM_CAP2_IN_INVERT_V 0x00000001U +#define MCPWM_CAP2_IN_INVERT_S 11 +/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture. + * 0: Invalid, No effect + * 1: Trigger a software forced capture on channel 2 + */ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) +#define MCPWM_CAP2_SW_V 0x00000001U +#define MCPWM_CAP2_SW_S 12 + +/** MCPWM_CAP_CH0_REG register + * CAP0 capture value register + */ +#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc) +/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP0 + */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP0_VALUE_S 0 + +/** MCPWM_CAP_CH1_REG register + * CAP1 capture value register + */ +#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100) +/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP1 + */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP1_VALUE_S 0 + +/** MCPWM_CAP_CH2_REG register + * CAP2 capture value register + */ +#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104) +/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAP2 + */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU +#define MCPWM_CAP2_VALUE_S 0 + +/** MCPWM_CAP_STATUS_REG register + * Last capture trigger edge information register + */ +#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108) +/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0. + * 0: Posedge + * 1: Negedge + */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) +#define MCPWM_CAP0_EDGE_V 0x00000001U +#define MCPWM_CAP0_EDGE_S 0 +/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1. + * 0: Posedge + * 1: Negedge + */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) +#define MCPWM_CAP1_EDGE_V 0x00000001U +#define MCPWM_CAP1_EDGE_S 1 +/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2. + * 0: Posedge + * 1: Negedge + */ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) +#define MCPWM_CAP2_EDGE_V 0x00000001U +#define MCPWM_CAP2_EDGE_S 2 + +/** MCPWM_UPDATE_CFG_REG register + * Generator Update configuration register + */ +#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c) +/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module. + * 0: Disable + * 1: Enable + */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) +#define MCPWM_GLOBAL_UP_EN_V 0x00000001U +#define MCPWM_GLOBAL_UP_EN_S 0 +/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) +#define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator0. + * Valid only when PWM_GLOBAL_UP_EN is set to 1. + * 0: Disable + * 1: Enable + */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) +#define MCPWM_OP0_UP_EN_V 0x00000001U +#define MCPWM_OP0_UP_EN_S 2 +/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) +#define MCPWM_OP0_FORCE_UP_V 0x00000001U +#define MCPWM_OP0_FORCE_UP_S 3 +/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator1. + * Valid only when PWM_GLOBAL_UP_EN is set to 1. + * 0: Disable + * 1: Enable + */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) +#define MCPWM_OP1_UP_EN_V 0x00000001U +#define MCPWM_OP1_UP_EN_S 4 +/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) +#define MCPWM_OP1_FORCE_UP_V 0x00000001U +#define MCPWM_OP1_FORCE_UP_S 5 +/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator2. + * Valid only when PWM_GLOBAL_UP_EN is set to 1. + * 0: Disable + * 1: Enable + */ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) +#define MCPWM_OP2_UP_EN_V 0x00000001U +#define MCPWM_OP2_UP_EN_S 6 +/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) +#define MCPWM_OP2_FORCE_UP_V 0x00000001U +#define MCPWM_OP2_FORCE_UP_S 7 + +/** MCPWM_INT_ENA_REG register + * Interrupt enable register + */ +#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110) +/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 +/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) +#define MCPWM_FAULT0_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_INT_ENA_S 9 +/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) +#define MCPWM_FAULT1_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_INT_ENA_S 10 +/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) +#define MCPWM_FAULT2_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_INT_ENA_S 11 +/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) +#define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ENA_S 24 +/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) +#define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ENA_S 25 +/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) +#define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ENA_S 26 +/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) +#define MCPWM_CAP0_INT_ENA_V 0x00000001U +#define MCPWM_CAP0_INT_ENA_S 27 +/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) +#define MCPWM_CAP1_INT_ENA_V 0x00000001U +#define MCPWM_CAP1_INT_ENA_S 28 +/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) +#define MCPWM_CAP2_INT_ENA_V 0x00000001U +#define MCPWM_CAP2_INT_ENA_S 29 + +/** MCPWM_INT_RAW_REG register + * Interrupt raw status register + */ +#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114) +/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 +/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) +#define MCPWM_FAULT0_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_INT_RAW_S 9 +/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) +#define MCPWM_FAULT1_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_INT_RAW_S 10 +/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) +#define MCPWM_FAULT2_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_INT_RAW_S 11 +/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) +#define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ0_OST_INT_RAW_S 24 +/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) +#define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ1_OST_INT_RAW_S 25 +/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) +#define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U +#define MCPWM_TZ2_OST_INT_RAW_S 26 +/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) +#define MCPWM_CAP0_INT_RAW_V 0x00000001U +#define MCPWM_CAP0_INT_RAW_S 27 +/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) +#define MCPWM_CAP1_INT_RAW_V 0x00000001U +#define MCPWM_CAP1_INT_RAW_S 28 +/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) +#define MCPWM_CAP2_INT_RAW_V 0x00000001U +#define MCPWM_CAP2_INT_RAW_S 29 + +/** MCPWM_INT_ST_REG register + * Interrupt masked status register + */ +#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118) +/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_ST_S 0 +/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) +#define MCPWM_FAULT0_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_INT_ST_S 9 +/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) +#define MCPWM_FAULT1_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_INT_ST_S 10 +/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) +#define MCPWM_FAULT2_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_INT_ST_S 11 +/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) +#define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_ST_S 21 +/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) +#define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_ST_S 22 +/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) +#define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_ST_S 23 +/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) +#define MCPWM_TZ0_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ0_OST_INT_ST_S 24 +/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) +#define MCPWM_TZ1_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ1_OST_INT_ST_S 25 +/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) +#define MCPWM_TZ2_OST_INT_ST_V 0x00000001U +#define MCPWM_TZ2_OST_INT_ST_S 26 +/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) +#define MCPWM_CAP0_INT_ST_V 0x00000001U +#define MCPWM_CAP0_INT_ST_S 27 +/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) +#define MCPWM_CAP1_INT_ST_V 0x00000001U +#define MCPWM_CAP1_INT_ST_S 28 +/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) +#define MCPWM_CAP2_INT_ST_V 0x00000001U +#define MCPWM_CAP2_INT_ST_S 29 + +/** MCPWM_INT_CLR_REG register + * Interrupt clear register + */ +#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c) +/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 +/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) +#define MCPWM_FAULT0_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_INT_CLR_S 9 +/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) +#define MCPWM_FAULT1_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_INT_CLR_S 10 +/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) +#define MCPWM_FAULT2_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_INT_CLR_S 11 +/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) +#define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ0_OST_INT_CLR_S 24 +/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) +#define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ1_OST_INT_CLR_S 25 +/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) +#define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U +#define MCPWM_TZ2_OST_INT_CLR_S 26 +/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) +#define MCPWM_CAP0_INT_CLR_V 0x00000001U +#define MCPWM_CAP0_INT_CLR_S 27 +/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) +#define MCPWM_CAP1_INT_CLR_V 0x00000001U +#define MCPWM_CAP1_INT_CLR_S 28 +/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) +#define MCPWM_CAP2_INT_CLR_V 0x00000001U +#define MCPWM_CAP2_INT_CLR_S 29 + +/** MCPWM_EVT_EN_REG register + * Event enable register + */ +#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120) +/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) +#define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) +#define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_STOP_EN_S 0 +/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) +#define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) +#define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_STOP_EN_S 1 +/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) +#define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) +#define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_STOP_EN_S 2 +/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) +#define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) +#define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEZ_EN_S 3 +/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) +#define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) +#define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEZ_EN_S 4 +/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) +#define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) +#define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEZ_EN_S 5 +/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) +#define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) +#define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER0_TEP_EN_S 6 +/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) +#define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) +#define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER1_TEP_EN_S 7 +/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) +#define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) +#define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U +#define MCPWM_EVT_TIMER2_TEP_EN_S 8 +/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP0_TEA_EN (BIT(9)) +#define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) +#define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEA_EN_S 9 +/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP1_TEA_EN (BIT(10)) +#define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) +#define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEA_EN_S 10 +/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP2_TEA_EN (BIT(11)) +#define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) +#define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEA_EN_S 11 +/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP0_TEB_EN (BIT(12)) +#define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) +#define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEB_EN_S 12 +/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP1_TEB_EN (BIT(13)) +#define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) +#define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEB_EN_S 13 +/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP2_TEB_EN (BIT(14)) +#define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) +#define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEB_EN_S 14 +/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_F0_EN (BIT(15)) +#define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) +#define MCPWM_EVT_F0_EN_V 0x00000001U +#define MCPWM_EVT_F0_EN_S 15 +/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_F1_EN (BIT(16)) +#define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) +#define MCPWM_EVT_F1_EN_V 0x00000001U +#define MCPWM_EVT_F1_EN_S 16 +/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_F2_EN (BIT(17)) +#define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) +#define MCPWM_EVT_F2_EN_V 0x00000001U +#define MCPWM_EVT_F2_EN_S 17 +/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_F0_CLR_EN (BIT(18)) +#define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) +#define MCPWM_EVT_F0_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F0_CLR_EN_S 18 +/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_F1_CLR_EN (BIT(19)) +#define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) +#define MCPWM_EVT_F1_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F1_CLR_EN_S 19 +/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_F2_CLR_EN (BIT(20)) +#define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) +#define MCPWM_EVT_F2_CLR_EN_V 0x00000001U +#define MCPWM_EVT_F2_CLR_EN_S 20 +/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) +#define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) +#define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_CBC_EN_S 21 +/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) +#define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) +#define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_CBC_EN_S 22 +/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) +#define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) +#define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_CBC_EN_S 23 +/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TZ0_OST_EN (BIT(24)) +#define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) +#define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ0_OST_EN_S 24 +/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TZ1_OST_EN (BIT(25)) +#define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) +#define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ1_OST_EN_S 25 +/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_TZ2_OST_EN (BIT(26)) +#define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) +#define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U +#define MCPWM_EVT_TZ2_OST_EN_S 26 +/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_CAP0_EN (BIT(27)) +#define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) +#define MCPWM_EVT_CAP0_EN_V 0x00000001U +#define MCPWM_EVT_CAP0_EN_S 27 +/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_CAP1_EN (BIT(28)) +#define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) +#define MCPWM_EVT_CAP1_EN_V 0x00000001U +#define MCPWM_EVT_CAP1_EN_S 28 +/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_CAP2_EN (BIT(29)) +#define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) +#define MCPWM_EVT_CAP2_EN_V 0x00000001U +#define MCPWM_EVT_CAP2_EN_S 29 + +/** MCPWM_TASK_EN_REG register + * Task enable register + */ +#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124) +/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) +#define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) +#define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_A_UP_EN_S 0 +/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) +#define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) +#define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_A_UP_EN_S 1 +/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) +#define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) +#define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_A_UP_EN_S 2 +/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) +#define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) +#define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR0_B_UP_EN_S 3 +/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) +#define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) +#define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR1_B_UP_EN_S 4 +/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) +#define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) +#define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U +#define MCPWM_TASK_CMPR2_B_UP_EN_S 5 +/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_GEN_STOP_EN (BIT(6)) +#define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) +#define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U +#define MCPWM_TASK_GEN_STOP_EN_S 6 +/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) +#define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) +#define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_SYNC_EN_S 7 +/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) +#define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) +#define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_SYNC_EN_S 8 +/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) +#define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) +#define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_SYNC_EN_S 9 +/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 +/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 +/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U +#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 +/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TZ0_OST_EN (BIT(13)) +#define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) +#define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ0_OST_EN_S 13 +/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TZ1_OST_EN (BIT(14)) +#define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) +#define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ1_OST_EN_S 14 +/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_TZ2_OST_EN (BIT(15)) +#define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) +#define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U +#define MCPWM_TASK_TZ2_OST_EN_S 15 +/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CLR0_OST_EN (BIT(16)) +#define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) +#define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR0_OST_EN_S 16 +/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CLR1_OST_EN (BIT(17)) +#define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) +#define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR1_OST_EN_S 17 +/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CLR2_OST_EN (BIT(18)) +#define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) +#define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U +#define MCPWM_TASK_CLR2_OST_EN_S 18 +/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CAP0_EN (BIT(19)) +#define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) +#define MCPWM_TASK_CAP0_EN_V 0x00000001U +#define MCPWM_TASK_CAP0_EN_S 19 +/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CAP1_EN (BIT(20)) +#define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) +#define MCPWM_TASK_CAP1_EN_V 0x00000001U +#define MCPWM_TASK_CAP1_EN_S 20 +/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive. + * 0: Disable + * 1: Enable + */ +#define MCPWM_TASK_CAP2_EN (BIT(21)) +#define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) +#define MCPWM_TASK_CAP2_EN_V 0x00000001U +#define MCPWM_TASK_CAP2_EN_S 21 + +/** MCPWM_EVT_EN2_REG register + * Event enable register2 + */ +#define MCPWM_EVT_EN2_REG(i) (REG_MCPWM_BASE(i) + 0x128) +/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP0_TEE1_EN (BIT(0)) +#define MCPWM_EVT_OP0_TEE1_EN_M (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S) +#define MCPWM_EVT_OP0_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEE1_EN_S 0 +/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP1_TEE1_EN (BIT(1)) +#define MCPWM_EVT_OP1_TEE1_EN_M (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S) +#define MCPWM_EVT_OP1_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEE1_EN_S 1 +/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP2_TEE1_EN (BIT(2)) +#define MCPWM_EVT_OP2_TEE1_EN_M (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S) +#define MCPWM_EVT_OP2_TEE1_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEE1_EN_S 2 +/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP0_TEE2_EN (BIT(3)) +#define MCPWM_EVT_OP0_TEE2_EN_M (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S) +#define MCPWM_EVT_OP0_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP0_TEE2_EN_S 3 +/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP1_TEE2_EN (BIT(4)) +#define MCPWM_EVT_OP1_TEE2_EN_M (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S) +#define MCPWM_EVT_OP1_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP1_TEE2_EN_S 4 +/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate. + * 0: Disable + * 1: Enable + */ +#define MCPWM_EVT_OP2_TEE2_EN (BIT(5)) +#define MCPWM_EVT_OP2_TEE2_EN_M (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S) +#define MCPWM_EVT_OP2_TEE2_EN_V 0x00000001U +#define MCPWM_EVT_OP2_TEE2_EN_S 5 + +/** MCPWM_OP0_TSTMP_E1_REG register + * Generator0 timer stamp E1 value register + */ +#define MCPWM_OP0_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x12c) +/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator0 timer stamp E1 value register + */ +#define MCPWM_OP0_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E1_M (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S) +#define MCPWM_OP0_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E1_S 0 + +/** MCPWM_OP0_TSTMP_E2_REG register + * Generator0 timer stamp E2 value register + */ +#define MCPWM_OP0_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x130) +/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator0 timer stamp E2 value register + */ +#define MCPWM_OP0_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E2_M (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S) +#define MCPWM_OP0_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP0_TSTMP_E2_S 0 + +/** MCPWM_OP1_TSTMP_E1_REG register + * Generator1 timer stamp E1 value register + */ +#define MCPWM_OP1_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x134) +/** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator1 timer stamp E1 value register + */ +#define MCPWM_OP1_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E1_M (MCPWM_OP1_TSTMP_E1_V << MCPWM_OP1_TSTMP_E1_S) +#define MCPWM_OP1_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E1_S 0 + +/** MCPWM_OP1_TSTMP_E2_REG register + * Generator1 timer stamp E2 value register + */ +#define MCPWM_OP1_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x138) +/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator1 timer stamp E2 value register + */ +#define MCPWM_OP1_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E2_M (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S) +#define MCPWM_OP1_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP1_TSTMP_E2_S 0 + +/** MCPWM_OP2_TSTMP_E1_REG register + * Generator2 timer stamp E1 value register + */ +#define MCPWM_OP2_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x13c) +/** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0; + * Configures generator2 timer stamp E1 value register + */ +#define MCPWM_OP2_TSTMP_E1 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E1_M (MCPWM_OP2_TSTMP_E1_V << MCPWM_OP2_TSTMP_E1_S) +#define MCPWM_OP2_TSTMP_E1_V 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E1_S 0 + +/** MCPWM_OP2_TSTMP_E2_REG register + * Generator2 timer stamp E2 value register + */ +#define MCPWM_OP2_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x140) +/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0; + * Configures generator2 timer stamp E2 value register + */ +#define MCPWM_OP2_TSTMP_E2 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E2_M (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S) +#define MCPWM_OP2_TSTMP_E2_V 0x0000FFFFU +#define MCPWM_OP2_TSTMP_E2_S 0 + +/** MCPWM_CLK_REG register + * Global configuration register + */ +#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x144) +/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate. + * 0: Open the clock gate only when application writes registers + * 1: Force open the clock gate for register + */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) +#define MCPWM_CLK_EN_V 0x00000001U +#define MCPWM_CLK_EN_S 0 + +/** MCPWM_VERSION_REG register + * Version register. + */ +#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x148) +/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ +#define MCPWM_DATE 0x0FFFFFFFU +#define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) +#define MCPWM_DATE_V 0x0FFFFFFFU +#define MCPWM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_struct.h new file mode 100644 index 0000000000..e917dc7b3c --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mcpwm_struct.h @@ -0,0 +1,1918 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: clk_cfg */ +/** Type of clk_cfg register + * PWM clock prescaler register. + */ +typedef union { + struct { + /** clk_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * + * (PWM_CLK_PRESCALE + 1). + */ + uint32_t clk_prescale:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_clk_cfg_reg_t; + + +/** Group: timer */ +/** Type of timern_cfg0 register + * PWM timern period and update method configuration register. + */ +typedef union { + struct { + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; + * Configures the prescaler value of timern, so that the period of PT0_clk = Period of + * PWM_clk * (PWM_TIMERn_PRESCALE + 1) + */ + uint32_t timer_prescale:8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; + * Configures the period shadow of PWM timern + */ + uint32_t timer_period:16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; + * Configures the update method for active register of PWM timern period.\\0: + * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal + * zero event + */ + uint32_t timer_period_upmethod:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} mcpwm_timer_cfg0_reg_t; + +/** Type of timer0_cfg1 register + * PWM timer$n working mode and start/stop control register. + */ +typedef union { + struct { + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; + * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, + * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts + * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and + * stops at the next TEP.\\TEP here and below means the event that happens when the + * timer equals to period + */ + uint32_t timer_start:3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; + * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: + * Decrease mode\\3: Up-down mode + */ + uint32_t timer_mod:2; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_timer_cfg1_reg_t; + +/** Type of timer0_sync register + * PWM timer$n sync function configuration register. + */ +typedef union { + struct { + /** timer_synci_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer$n reloading with phase on sync input + * event is enabled.\\0: Disable\\1: Enable + */ + uint32_t timer_synci_en:1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; + * Configures the generation of software sync. Toggling this bit will trigger a + * software sync. + */ + uint32_t timer_sync_sw:1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; + * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: + * Invalid, sync_out selects noting + */ + uint32_t timer_synco_sel:2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; + * Configures the phase for timer$n reload on sync event. + */ + uint32_t timer_phase:16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; + * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: + * Increase\\1: Decrease + */ + uint32_t timer_phase_direction:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} mcpwm_timer_sync_reg_t; + +/** Type of timer_status register + * PWM timer$n status register. + */ +typedef union { + struct { + /** timer_value : RO; bitpos: [15:0]; default: 0; + * Represents current PWM timer$n counter value. + */ + uint32_t timer_value:16; + /** timer_direction : RO; bitpos: [16]; default: 0; + * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement + */ + uint32_t timer_direction:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} mcpwm_timer_status_reg_t; + + +/** Group: timer_synci_cfg */ +/** Type of timer_synci_cfg register + * Synchronization input selection register for PWM timers. + */ +typedef union { + struct { + /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0; + * Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer0_syncisel:3; + /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0; + * Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer1_syncisel:3; + /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0; + * Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: + * PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 + * from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + */ + uint32_t timer2_syncisel:3; + /** external_synci0_invert : R/W; bitpos: [9]; default: 0; + * Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci0_invert:1; + /** external_synci1_invert : R/W; bitpos: [10]; default: 0; + * Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci1_invert:1; + /** external_synci2_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: + * Invert + */ + uint32_t external_synci2_invert:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} mcpwm_timer_synci_cfg_reg_t; + + +/** Group: operator_timersel */ +/** Type of operator_timersel register + * PWM operator's timer select register + */ +typedef union { + struct { + /** operator0_timersel : R/W; bitpos: [1:0]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator0.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator0_timersel:2; + /** operator1_timersel : R/W; bitpos: [3:2]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator1.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator1_timersel:2; + /** operator2_timersel : R/W; bitpos: [5:4]; default: 0; + * Configures which PWM timer will be the timing reference for PWM operator2.\\0: + * Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + */ + uint32_t operator2_timersel:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_operator_timersel_reg_t; + + +/** Group: operators */ +/** Type of genn_stmp_cfg register + * Generatorn time stamp registers A and B transfer status and update method register + */ +typedef union { + struct { + /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures the update method for PWM generator n time stamp A's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t cmpr_a_upmethod:4; + /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures the update method for PWM generator n time stamp B's active + * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is + * set to 1: Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t cmpr_b_upmethod:4; + /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + * Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0: + * A's active reg has been updated with shadow register latest value.\\1: A's shadow + * reg is filled and waiting to be transferred to A's active reg + */ + uint32_t cmpr_a_shdw_full:1; + /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + * Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0: + * B's active reg has been updated with shadow register latest value.\\1: B's shadow + * reg is filled and waiting to be transferred to B's active reg + */ + uint32_t cmpr_b_shdw_full:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_gen_stmp_cfg_reg_t; + +/** Type of gen_tstmp_a register + * Generator$n time stamp A's shadow register + */ +typedef union { + struct { + /** cmpr : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator $n time stamp 's shadow register. + */ + uint32_t cmpr:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_gen_tstmp_reg_t; + + +/** Type of gen_cfg0 register + * Generator$n fault event T0 and T1 configuration register + */ +typedef union { + struct { + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for PWM generator $n's active register.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t gen_cfg_upmethod:4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; + * Configures source selection for PWM generator $n event_t0, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ + uint32_t gen_t0_sel:3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; + * Configures source selection for PWM generator $n event_t1, take effect + * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: + * Invalid, Select nothing + */ + uint32_t gen_t1_sel:3; + uint32_t reserved_10:22; + }; + uint32_t val; +} mcpwm_gen_cfg0_reg_t; + +/** Type of gen_force register + * Generator$n output signal force mode register. + */ +typedef union { + struct { + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + * Configures update method for continuous software force of PWM generator$n.\\0: + * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable + * update. TEA/B here and below means an event generated when the timer's value equals + * to that of register A/B. + */ + uint32_t gen_cntuforce_upmethod:6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + * Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ + uint32_t gen_a_cntuforce_mode:2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + * Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2: + * High\\3: Disabled + */ + uint32_t gen_b_cntuforce_mode:2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; + * Configures the generation of non-continuous immediate software-force event for + * PWM$n A, a toggle will trigger a force event. + */ + uint32_t gen_a_nciforce:1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + * Configures non-continuous immediate software force mode for PWM$n A.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ + uint32_t gen_a_nciforce_mode:2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; + * Configures the generation of non-continuous immediate software-force event for + * PWM$n B, a toggle will trigger a force event. + */ + uint32_t gen_b_nciforce:1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + * Configures non-continuous immediate software force mode for PWM$n B.\\0: + * Disabled\\1: Low\\2: High\\3: Disabled + */ + uint32_t gen_b_nciforce_mode:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_gen_force_reg_t; + +/** Type of gen register + * PWM$n output signal A actions configuration register + */ +typedef union { + struct { + /** gen_a_utez : R/W; bitpos: [1:0]; default: 0; + * Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_utez:2; + /** gen_a_utep : R/W; bitpos: [3:2]; default: 0; + * Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_utep:2; + /** gen_a_utea : R/W; bitpos: [5:4]; default: 0; + * Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_utea:2; + /** gen_a_uteb : R/W; bitpos: [7:6]; default: 0; + * Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_uteb:2; + /** gen_a_ut0 : R/W; bitpos: [9:8]; default: 0; + * Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_ut0:2; + /** gen_a_ut1 : R/W; bitpos: [11:10]; default: 0; + * Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_ut1:2; + /** gen_a_dtez : R/W; bitpos: [13:12]; default: 0; + * Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_dtez:2; + /** gen_a_dtep : R/W; bitpos: [15:14]; default: 0; + * Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_dtep:2; + /** gen_a_dtea : R/W; bitpos: [17:16]; default: 0; + * Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_dtea:2; + /** gen_a_dteb : R/W; bitpos: [19:18]; default: 0; + * Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_dteb:2; + /** gen_a_dt0 : R/W; bitpos: [21:20]; default: 0; + * Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_dt0:2; + /** gen_a_dt1 : R/W; bitpos: [23:22]; default: 0; + * Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No + * change\\1: Low\\2: High\\3: Toggle + */ + uint32_t gen_dt1:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_gen_reg_t; + +/** Type of dt0_cfg register + * Dead time configuration register + */ +typedef union { + struct { + /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + * Configures update method for FED (Falling edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t db_fed_upmethod:4; + /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0; + * Configures update method for RED (rising edge delay) active register.\\0: + * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: + * Sync\\Bit3 is set to 1: Disable the update + */ + uint32_t db_red_upmethod:4; + /** db_deb_mode : R/W; bitpos: [8]; default: 0; + * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path + * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + */ + uint32_t db_deb_mode:1; + /** db_a_outswap : R/W; bitpos: [9]; default: 0; + * Configures S6 in table. + */ + uint32_t db_a_outswap:1; + /** db_b_outswap : R/W; bitpos: [10]; default: 0; + * Configures S7 in table. + */ + uint32_t db_b_outswap:1; + /** db_red_insel : R/W; bitpos: [11]; default: 0; + * Configures S4 in table. + */ + uint32_t db_red_insel:1; + /** db_fed_insel : R/W; bitpos: [12]; default: 0; + * Configures S5 in table. + */ + uint32_t db_fed_insel:1; + /** db_red_outinvert : R/W; bitpos: [13]; default: 0; + * Configures S2 in table. + */ + uint32_t db_red_outinvert:1; + /** db_fed_outinvert : R/W; bitpos: [14]; default: 0; + * Configures S3 in table. + */ + uint32_t db_fed_outinvert:1; + /** db_a_outbypass : R/W; bitpos: [15]; default: 1; + * Configures S1 in table. + */ + uint32_t db_a_outbypass:1; + /** db_b_outbypass : R/W; bitpos: [16]; default: 1; + * Configures S0 in table. + */ + uint32_t db_b_outbypass:1; + /** db_clk_sel : R/W; bitpos: [17]; default: 0; + * Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk + */ + uint32_t db_clk_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} mcpwm_dt_cfg_reg_t; + +/** Type of dt0_fed_cfg register + * Falling edge delay (FED) shadow register + */ +typedef union { + struct { + /** db_fed : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for FED. + */ + uint32_t db_fed:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dt_fed_cfg_reg_t; + +/** Type of dt0_red_cfg register + * Rising edge delay (RED) shadow register + */ +typedef union { + struct { + /** db_red : R/W; bitpos: [15:0]; default: 0; + * Configures shadow register for RED. + */ + uint32_t db_red:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_dt_red_cfg_reg_t; + +/** Type of carrier0_cfg register + * Carrier$n configuration register + */ +typedef union { + struct { + /** chopper_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled + */ + uint32_t chopper_en:1; + /** chopper_prescale : R/W; bitpos: [4:1]; default: 0; + * Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of + * PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1) + */ + uint32_t chopper_prescale:4; + /** chopper_duty : R/W; bitpos: [7:5]; default: 0; + * Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8 + */ + uint32_t chopper_duty:3; + /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0; + * Configures width of the first pulse. Measurement unit: Periods of the carrier. + */ + uint32_t chopper_oshtwth:4; + /** chopper_out_invert : R/W; bitpos: [12]; default: 0; + * Configures whether or not to invert the output of PWM$n A and PWM$n B for this + * submodule.\\0: Normal\\1: Invert + */ + uint32_t chopper_out_invert:1; + /** chopper_in_invert : R/W; bitpos: [13]; default: 0; + * Configures whether or not to invert the input of PWM$n A and PWM$n B for this + * submodule.\\0: Normal\\1: Invert + */ + uint32_t chopper_in_invert:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} mcpwm_carrier_cfg_reg_t; + +/** Type of fh0_cfg0 register + * PWM$n A and PWM$n B trip events actions configuration register + */ +typedef union { + struct { + /** tz_sw_cbc : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_sw_cbc:1; + /** tz_f2_cbc : R/W; bitpos: [1]; default: 0; + * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_f2_cbc:1; + /** tz_f1_cbc : R/W; bitpos: [2]; default: 0; + * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_f1_cbc:1; + /** tz_f0_cbc : R/W; bitpos: [3]; default: 0; + * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_f0_cbc:1; + /** tz_sw_ost : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable software force one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_sw_ost:1; + /** tz_f2_ost : R/W; bitpos: [5]; default: 0; + * Configures whether or not event_f2 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_f2_ost:1; + /** tz_f1_ost : R/W; bitpos: [6]; default: 0; + * Configures whether or not event_f1 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_f1_ost:1; + /** tz_f0_ost : R/W; bitpos: [7]; default: 0; + * Configures whether or not event_f0 will trigger one-shot mode action.\\0: + * Disable\\1: Enable + */ + uint32_t tz_f0_ost:1; + /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_a_cbc_d:2; + /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_a_cbc_u:2; + /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0; + * Configures one-shot mode action on PWM$n A when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_a_ost_d:2; + /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0; + * Configures one-shot mode action on PWM$n A when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_a_ost_u:2; + /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer + * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_b_cbc_d:2; + /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer + * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_b_cbc_u:2; + /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0; + * Configures one-shot mode action on PWM$n B when fault event occurs and timer is + * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_b_ost_d:2; + /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0; + * Configures one-shot mode action on PWM$n B when fault event occurs and timer is + * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + */ + uint32_t tz_b_ost_u:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} mcpwm_fh_cfg0_reg_t; + +/** Type of fh0_cfg1 register + * Software triggers for fault handler actions configuration register + */ +typedef union { + struct { + /** tz_clr_ost : R/W; bitpos: [0]; default: 0; + * Configures the generation of software one-shot mode action clear. A toggle + * (software negate its value) triggers a clear for on going one-shot mode action. + */ + uint32_t tz_clr_ost:1; + /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0; + * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select + * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + */ + uint32_t tz_cbcpulse:2; + /** tz_force_cbc : R/W; bitpos: [3]; default: 0; + * Configures the generation of software cycle-by-cycle mode action. A toggle + * (software negate its value) triggers a cycle-by-cycle mode action. + */ + uint32_t tz_force_cbc:1; + /** tz_force_ost : R/W; bitpos: [4]; default: 0; + * Configures the generation of software one-shot mode action. A toggle (software + * negate its value) triggers a one-shot mode action. + */ + uint32_t tz_force_ost:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} mcpwm_fh_cfg1_reg_t; + +/** Type of fh0_status register + * Fault events status register + */ +typedef union { + struct { + /** tz_cbc_on : RO; bitpos: [0]; default: 0; + * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No + * action\\1: On going + */ + uint32_t tz_cbc_on:1; + /** tz_ost_on : RO; bitpos: [1]; default: 0; + * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On + * going + */ + uint32_t tz_ost_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mcpwm_fh_status_reg_t; + +/** Group: fault_detect */ +/** Type of fault_detect register + * Fault detection configuration and status register + */ +typedef union { + struct { + /** f0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + */ + uint32_t f0_en:1; + /** f1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + */ + uint32_t f1_en:1; + /** f2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + */ + uint32_t f2_en:1; + /** f0_pole : R/W; bitpos: [3]; default: 0; + * Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f0_pole:1; + /** f1_pole : R/W; bitpos: [4]; default: 0; + * Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f1_pole:1; + /** f2_pole : R/W; bitpos: [5]; default: 0; + * Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level + * low\\1: Level high + */ + uint32_t f2_pole:1; + /** event_f0 : RO; bitpos: [6]; default: 0; + * Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + */ + uint32_t event_f0:1; + /** event_f1 : RO; bitpos: [7]; default: 0; + * Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + */ + uint32_t event_f1:1; + /** event_f2 : RO; bitpos: [8]; default: 0; + * Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + */ + uint32_t event_f2:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} mcpwm_fault_detect_reg_t; + + +/** Group: cap_timer_cfg */ +/** Type of cap_timer_cfg register + * Capture timer configuration register + */ +typedef union { + struct { + /** cap_timer_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + */ + uint32_t cap_timer_en:1; + /** cap_synci_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + */ + uint32_t cap_synci_en:1; + /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0; + * Configures the selection of capture module sync input.\\0: None\\1: Timer0 + * sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: + * SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + */ + uint32_t cap_synci_sel:3; + /** cap_sync_sw : WT; bitpos: [5]; default: 0; + * Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: + * Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with + * value in phase register + */ + uint32_t cap_sync_sw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_cap_timer_cfg_reg_t; + + +/** Group: cap_timer_phase */ +/** Type of cap_timer_phase register + * Capture timer sync phase register + */ +typedef union { + struct { + /** cap_phase : R/W; bitpos: [31:0]; default: 0; + * Configures phase value for capture timer sync operation. + */ + uint32_t cap_phase:32; + }; + uint32_t val; +} mcpwm_cap_timer_phase_reg_t; + + +/** Group: cap_chn_cfg */ +/** Type of cap_chn_cfg register + * Capture channel n configuration register + */ +typedef union { + struct { + /** capn_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable + */ + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; + * Configures which edge of capture on channel n after prescaling is used.\\0: + * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: + * Enable capture on the positive edge + */ + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; + * Configures prescale value on positive edge of CAPn. Prescale value = + * PWM_CAPn_PRESCALE + 1 + */ + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; + * Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0: + * Normal\\1: Invert + */ + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; + * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a + * software forced capture on channel n + */ + uint32_t capn_sw:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} mcpwm_cap_chn_cfg_reg_t; + + +/** Group: cap_chn */ +/** Type of cap_chn register + * CAPn capture value register + */ +typedef union { + struct { + /** capn_value : RO; bitpos: [31:0]; default: 0; + * Represents value of last capture on CAPn + */ + uint32_t capn_value:32; + }; + uint32_t val; +} mcpwm_cap_chn_reg_t; + + +/** Group: cap_status */ +/** Type of cap_status register + * Last capture trigger edge information register + */ +typedef union { + struct { + /** cap0_edge : RO; bitpos: [0]; default: 0; + * Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + */ + uint32_t cap0_edge:1; + /** cap1_edge : RO; bitpos: [1]; default: 0; + * Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + */ + uint32_t cap1_edge:1; + /** cap2_edge : RO; bitpos: [2]; default: 0; + * Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + */ + uint32_t cap2_edge:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} mcpwm_cap_status_reg_t; + + +/** Group: update_cfg */ +/** Type of update_cfg register + * Generator Update configuration register + */ +typedef union { + struct { + /** global_up_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable global update for all active registers in MCPWM + * module.\\0: Disable\\1: Enable + */ + uint32_t global_up_en:1; + /** global_force_up : R/W; bitpos: [1]; default: 0; + * Configures the generation of global forced update for all active registers in MCPWM + * module. A toggle (software invert its value) will trigger a global forced update. + * Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + */ + uint32_t global_force_up:1; + /** op0_up_en : R/W; bitpos: [2]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op0_up_en:1; + /** op0_force_up : R/W; bitpos: [3]; default: 0; + * Configures the generation of forced update for active registers in PWM operator0. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + */ + uint32_t op0_force_up:1; + /** op1_up_en : R/W; bitpos: [4]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op1_up_en:1; + /** op1_force_up : R/W; bitpos: [5]; default: 0; + * Configures the generation of forced update for active registers in PWM operator1. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + */ + uint32_t op1_force_up:1; + /** op2_up_en : R/W; bitpos: [6]; default: 1; + * Configures whether or not to enable update of active registers in PWM operator$n. + * Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + */ + uint32_t op2_up_en:1; + /** op2_force_up : R/W; bitpos: [7]; default: 0; + * Configures the generation of forced update for active registers in PWM operator2. A + * toggle (software invert its value) will trigger a forced update. Valid only when + * MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + */ + uint32_t op2_force_up:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mcpwm_update_cfg_reg_t; + + +/** Group: int_ena */ +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_ena:1; + /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_ena:1; + /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_ena:1; + /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_ena:1; + /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_ena:1; + /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_ena:1; + /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_ena:1; + /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_ena:1; + /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_ena:1; + /** fault0_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_ena:1; + /** fault1_int_ena : R/W; bitpos: [10]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_ena:1; + /** fault2_int_ena : R/W; bitpos: [11]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_ena:1; + /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_ena:1; + /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_ena:1; + /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_ena:1; + /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + */ + uint32_t cmpr0_tea_int_ena:1; + /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + */ + uint32_t cmpr1_tea_int_ena:1; + /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + */ + uint32_t cmpr2_tea_int_ena:1; + /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + */ + uint32_t cmpr0_teb_int_ena:1; + /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + */ + uint32_t cmpr1_teb_int_ena:1; + /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + */ + uint32_t cmpr2_teb_int_ena:1; + /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM0. + */ + uint32_t tz0_cbc_int_ena:1; + /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM1. + */ + uint32_t tz1_cbc_int_ena:1; + /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode + * action on PWM2. + */ + uint32_t tz2_cbc_int_ena:1; + /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_ena:1; + /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_ena:1; + /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_ena:1; + /** cap0_int_ena : R/W; bitpos: [27]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_ena:1; + /** cap1_int_ena : R/W; bitpos: [28]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_ena:1; + /** cap2_int_ena : R/W; bitpos: [29]; default: 0; + * Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_ena:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_ena_reg_t; + + +/** Group: int_raw */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 0 stops. + */ + uint32_t timer0_stop_int_raw:1; + /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 1 stops. + */ + uint32_t timer1_stop_int_raw:1; + /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when the timer + * 2 stops. + */ + uint32_t timer2_stop_int_raw:1; + /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEZ event. + */ + uint32_t timer0_tez_int_raw:1; + /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEZ event. + */ + uint32_t timer1_tez_int_raw:1; + /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEZ event. + */ + uint32_t timer2_tez_int_raw:1; + /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 0 TEP event. + */ + uint32_t timer0_tep_int_raw:1; + /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 1 TEP event. + */ + uint32_t timer1_tep_int_raw:1; + /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer + * 2 TEP event. + */ + uint32_t timer2_tep_int_raw:1; + /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * starts. + */ + uint32_t fault0_int_raw:1; + /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * starts. + */ + uint32_t fault1_int_raw:1; + /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * starts. + */ + uint32_t fault2_int_raw:1; + /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 + * clears. + */ + uint32_t fault0_clr_int_raw:1; + /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 + * clears. + */ + uint32_t fault1_clr_int_raw:1; + /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 + * clears. + */ + uint32_t fault2_clr_int_raw:1; + /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_raw:1; + /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_raw:1; + /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_raw:1; + /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_raw:1; + /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_raw:1; + /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_raw:1; + /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_raw:1; + /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_raw:1; + /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_raw:1; + /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM0. + */ + uint32_t tz0_ost_int_raw:1; + /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM1. + */ + uint32_t tz1_ost_int_raw:1; + /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot + * mode action on PWM2. + */ + uint32_t tz2_ost_int_raw:1; + /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP0. + */ + uint32_t cap0_int_raw:1; + /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP1. + */ + uint32_t cap1_int_raw:1; + /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * Raw status bit: The raw interrupt status of the interrupt triggered by capture on + * CAP2. + */ + uint32_t cap2_int_raw:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_raw_reg_t; + + +/** Group: int_st */ +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_stop_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 0 stops. + */ + uint32_t timer0_stop_int_st:1; + /** timer1_stop_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 1 stops. + */ + uint32_t timer1_stop_int_st:1; + /** timer2_stop_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when the + * timer 2 stops. + */ + uint32_t timer2_stop_int_st:1; + /** timer0_tez_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEZ event. + */ + uint32_t timer0_tez_int_st:1; + /** timer1_tez_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEZ event. + */ + uint32_t timer1_tez_int_st:1; + /** timer2_tez_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEZ event. + */ + uint32_t timer2_tez_int_st:1; + /** timer0_tep_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 0 TEP event. + */ + uint32_t timer0_tep_int_st:1; + /** timer1_tep_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 1 TEP event. + */ + uint32_t timer1_tep_int_st:1; + /** timer2_tep_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * timer 2 TEP event. + */ + uint32_t timer2_tep_int_st:1; + /** fault0_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 starts. + */ + uint32_t fault0_int_st:1; + /** fault1_int_st : RO; bitpos: [10]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 starts. + */ + uint32_t fault1_int_st:1; + /** fault2_int_st : RO; bitpos: [11]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 starts. + */ + uint32_t fault2_int_st:1; + /** fault0_clr_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f0 clears. + */ + uint32_t fault0_clr_int_st:1; + /** fault1_clr_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f1 clears. + */ + uint32_t fault1_clr_int_st:1; + /** fault2_clr_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered when + * event_f2 clears. + */ + uint32_t fault2_clr_int_st:1; + /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEA event + */ + uint32_t cmpr0_tea_int_st:1; + /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEA event + */ + uint32_t cmpr1_tea_int_st:1; + /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEA event + */ + uint32_t cmpr2_tea_int_st:1; + /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 0 TEB event + */ + uint32_t cmpr0_teb_int_st:1; + /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 1 TEB event + */ + uint32_t cmpr1_teb_int_st:1; + /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a PWM + * operator 2 TEB event + */ + uint32_t cmpr2_teb_int_st:1; + /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM0. + */ + uint32_t tz0_cbc_int_st:1; + /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM1. + */ + uint32_t tz1_cbc_int_st:1; + /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * cycle-by-cycle mode action on PWM2. + */ + uint32_t tz2_cbc_int_st:1; + /** tz0_ost_int_st : RO; bitpos: [24]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM0. + */ + uint32_t tz0_ost_int_st:1; + /** tz1_ost_int_st : RO; bitpos: [25]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM1. + */ + uint32_t tz1_ost_int_st:1; + /** tz2_ost_int_st : RO; bitpos: [26]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by a + * one-shot mode action on PWM2. + */ + uint32_t tz2_ost_int_st:1; + /** cap0_int_st : RO; bitpos: [27]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP0. + */ + uint32_t cap0_int_st:1; + /** cap1_int_st : RO; bitpos: [28]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP1. + */ + uint32_t cap1_int_st:1; + /** cap2_int_st : RO; bitpos: [29]; default: 0; + * Masked status bit: The masked interrupt status of the interrupt triggered by + * capture on CAP2. + */ + uint32_t cap2_int_st:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_st_reg_t; + + +/** Group: int_clr */ +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + */ + uint32_t timer0_stop_int_clr:1; + /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + */ + uint32_t timer1_stop_int_clr:1; + /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + */ + uint32_t timer2_stop_int_clr:1; + /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + */ + uint32_t timer0_tez_int_clr:1; + /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + */ + uint32_t timer1_tez_int_clr:1; + /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + */ + uint32_t timer2_tez_int_clr:1; + /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + */ + uint32_t timer0_tep_int_clr:1; + /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + */ + uint32_t timer1_tep_int_clr:1; + /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + */ + uint32_t timer2_tep_int_clr:1; + /** fault0_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + */ + uint32_t fault0_int_clr:1; + /** fault1_int_clr : WT; bitpos: [10]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + */ + uint32_t fault1_int_clr:1; + /** fault2_int_clr : WT; bitpos: [11]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + */ + uint32_t fault2_int_clr:1; + /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + */ + uint32_t fault0_clr_int_clr:1; + /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + */ + uint32_t fault1_clr_int_clr:1; + /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + */ + uint32_t fault2_clr_int_clr:1; + /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + */ + uint32_t cmpr0_tea_int_clr:1; + /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + */ + uint32_t cmpr1_tea_int_clr:1; + /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + */ + uint32_t cmpr2_tea_int_clr:1; + /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + */ + uint32_t cmpr0_teb_int_clr:1; + /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + */ + uint32_t cmpr1_teb_int_clr:1; + /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + */ + uint32_t cmpr2_teb_int_clr:1; + /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM0. + */ + uint32_t tz0_cbc_int_clr:1; + /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM1. + */ + uint32_t tz1_cbc_int_clr:1; + /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action + * on PWM2. + */ + uint32_t tz2_cbc_int_clr:1; + /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM0. + */ + uint32_t tz0_ost_int_clr:1; + /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM1. + */ + uint32_t tz1_ost_int_clr:1; + /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on + * PWM2. + */ + uint32_t tz2_ost_int_clr:1; + /** cap0_int_clr : WT; bitpos: [27]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + */ + uint32_t cap0_int_clr:1; + /** cap1_int_clr : WT; bitpos: [28]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + */ + uint32_t cap1_int_clr:1; + /** cap2_int_clr : WT; bitpos: [29]; default: 0; + * Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + */ + uint32_t cap2_int_clr:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_int_clr_reg_t; + + +/** Group: evt_en */ +/** Type of evt_en register + * Event enable register + */ +typedef union { + struct { + /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer0_stop_en:1; + /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer1_stop_en:1; + /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_timer2_stop_en:1; + /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable timer0 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer0_tez_en:1; + /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable timer1 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer1_tez_en:1; + /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable timer2 equal zero event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer2_tez_en:1; + /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable timer0 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer0_tep_en:1; + /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer1 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer1_tep_en:1; + /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer2 equal period event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_timer2_tep_en:1; + /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tea_en:1; + /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tea_en:1; + /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal a event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tea_en:1; + /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_teb_en:1; + /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_teb_en:1; + /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal b event + * generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_teb_en:1; + /** evt_f0_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f0_en:1; + /** evt_f1_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f1_en:1; + /** evt_f2_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_f2_en:1; + /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f0_clr_en:1; + /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f1_clr_en:1; + /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_f2_clr_en:1; + /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz0_cbc_en:1; + /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz1_cbc_en:1; + /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: + * Disable\\1: Enable + */ + uint32_t evt_tz2_cbc_en:1; + /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz0_ost_en:1; + /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz1_ost_en:1; + /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: + * Enable + */ + uint32_t evt_tz2_ost_en:1; + /** evt_cap0_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap0_en:1; + /** evt_cap1_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap1_en:1; + /** evt_cap2_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_cap2_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} mcpwm_evt_en_reg_t; + + +/** Group: task_en */ +/** Type of task_en register + * Task enable register + */ +typedef union { + struct { + /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr0_a_up_en:1; + /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr1_a_up_en:1; + /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp A's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr2_a_up_en:1; + /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr0_b_up_en:1; + /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr1_b_up_en:1; + /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer stamp B's shadow register + * update task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cmpr2_b_up_en:1; + /** task_gen_stop_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable all PWM generate stop task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_gen_stop_en:1; + /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_sync_en:1; + /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_sync_en:1; + /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_sync_en:1; + /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable timer0 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer0_period_up_en:1; + /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable timer1 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer1_period_up_en:1; + /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable timer2 period update task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_timer2_period_up_en:1; + /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz0_ost_en:1; + /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0; + * Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz1_ost_en:1; + /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: + * Enable + */ + uint32_t task_tz2_ost_en:1; + /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable one shot trip0 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr0_ost_en:1; + /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable one shot trip1 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr1_ost_en:1; + /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable one shot trip2 clear task receive.\\0: + * Disable\\1: Enable + */ + uint32_t task_clr2_ost_en:1; + /** task_cap0_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap0_en:1; + /** task_cap1_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap1_en:1; + /** task_cap2_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + */ + uint32_t task_cap2_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} mcpwm_task_en_reg_t; + + +/** Group: evt_en2 */ +/** Type of evt_en2 register + * Event enable register2 + */ +typedef union { + struct { + /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tee1_en:1; + /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tee1_en:1; + /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tee1_en:1; + /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op0_tee2_en:1; + /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op1_tee2_en:1; + /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG + * event generate.\\0: Disable\\1: Enable + */ + uint32_t evt_op2_tee2_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} mcpwm_evt_en2_reg_t; + + +/** Group: Configuration register */ +/** Type of opn_tstmp_e1 register + * Generatorn timer stamp E1 value register + */ +typedef union { + struct { + /** op_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; + * Configures generatorn timer stamp E1 value register + */ + uint32_t op_tstmp_e:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} mcpwm_op_tstmp_reg_t; + +/** Type of clk register + * Global configuration register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mcpwm_clk_reg_t; + + +/** Group: Version register */ +/** Type of version register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725968; + * Configures the version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mcpwm_version_reg_t; + +typedef struct { + volatile mcpwm_timer_cfg0_reg_t timer_cfg0; + volatile mcpwm_timer_cfg1_reg_t timer_cfg1; + volatile mcpwm_timer_sync_reg_t timer_sync; + volatile mcpwm_timer_status_reg_t timer_status; +} mcpwm_timer_regs_t; + +typedef struct { + volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; + volatile mcpwm_gen_tstmp_reg_t timestamp[2]; + volatile mcpwm_gen_cfg0_reg_t gen_cfg0; + volatile mcpwm_gen_force_reg_t gen_force; + volatile mcpwm_gen_reg_t generator[2]; + volatile mcpwm_dt_cfg_reg_t dt_cfg; + volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; + volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg; + volatile mcpwm_carrier_cfg_reg_t carrier_cfg; + volatile mcpwm_fh_cfg0_reg_t fh_cfg0; + volatile mcpwm_fh_cfg1_reg_t fh_cfg1; + volatile mcpwm_fh_status_reg_t fh_status; +} mcpwm_operator_reg_t; + +typedef struct { + volatile mcpwm_op_tstmp_reg_t timestamp[2]; +} mcpwm_operator_tstmp_reg_t; + +typedef struct mcpwm_dev_t { + volatile mcpwm_clk_cfg_reg_t clk_cfg; + volatile mcpwm_timer_regs_t timer[3]; + volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg; + volatile mcpwm_operator_timersel_reg_t operator_timersel; + volatile mcpwm_operator_reg_t operators[3]; + volatile mcpwm_fault_detect_reg_t fault_detect; + volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg; + volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase; + volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3]; + volatile mcpwm_cap_chn_reg_t cap_chn[3]; + volatile mcpwm_cap_status_reg_t cap_status; + volatile mcpwm_update_cfg_reg_t update_cfg; + volatile mcpwm_int_ena_reg_t int_ena; + volatile mcpwm_int_raw_reg_t int_raw; + volatile mcpwm_int_st_reg_t int_st; + volatile mcpwm_int_clr_reg_t int_clr; + volatile mcpwm_evt_en_reg_t evt_en; + volatile mcpwm_task_en_reg_t task_en; + volatile mcpwm_evt_en2_reg_t evt_en2; + volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3]; + volatile mcpwm_clk_reg_t clk; + volatile mcpwm_version_reg_t version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM0; +extern mcpwm_dev_t MCPWM1; + +#ifndef __cplusplus +_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_reg.h new file mode 100644 index 0000000000..104e4c06f1 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_reg.h @@ -0,0 +1,217 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MEM_MONITOR_LOG_SETTING_REG register + * log config register + */ +#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) +/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0; + * Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE + * monitor + */ +#define MEM_MONITOR_LOG_MODE 0x0000000FU +#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) +#define MEM_MONITOR_LOG_MODE_V 0x0000000FU +#define MEM_MONITOR_LOG_MODE_S 0 +/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4)) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4 +/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0; + * enable core log + */ +#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU +#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S) +#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_CORE_ENA_S 8 +/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0; + * enable dma_0 log + */ +#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S) +#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_0_ENA_S 16 +/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0; + * enable dma_1 log + */ +#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S) +#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_1_ENA_S 24 + +/** MEM_MONITOR_LOG_SETTING1_REG register + * log config register + */ +#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4) +/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0; + * enable dma_2 log + */ +#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S) +#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_2_ENA_S 0 +/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0; + * enable dma_3 log + */ +#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU +#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S) +#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU +#define MEM_MONITOR_LOG_DMA_3_ENA_S 8 + +/** MEM_MONITOR_LOG_CHECK_DATA_REG register + * check data register + */ +#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8) +/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ +#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S) +#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_S 0 + +/** MEM_MONITOR_LOG_DATA_MASK_REG register + * check data mask register + */ +#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc) +/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ +#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) +#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_S 0 + +/** MEM_MONITOR_LOG_MIN_REG register + * log boundary register + */ +#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10) +/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ +#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S) +#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_S 0 + +/** MEM_MONITOR_LOG_MAX_REG register + * log boundary register + */ +#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14) +/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ +#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S) +#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_S 0 + +/** MEM_MONITOR_LOG_MEM_START_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18) +/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S) +#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_S 0 + +/** MEM_MONITOR_LOG_MEM_END_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) +/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S) +#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_S 0 + +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register + * current writing address. + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20) +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S) +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 + +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register + * writing address update + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24) +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 + +/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register + * full flag status register + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28) +/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 +/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 + +/** MEM_MONITOR_CLOCK_GATE_REG register + * clock gate force on register + */ +#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c) +/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ +#define MEM_MONITOR_CLK_EN (BIT(0)) +#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) +#define MEM_MONITOR_CLK_EN_V 0x00000001U +#define MEM_MONITOR_CLK_EN_S 0 + +/** MEM_MONITOR_DATE_REG register + * version register + */ +#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc) +/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36708896; + * version register + */ +#define MEM_MONITOR_DATE 0x0FFFFFFFU +#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S) +#define MEM_MONITOR_DATE_V 0x0FFFFFFFU +#define MEM_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_struct.h new file mode 100644 index 0000000000..18fe8db503 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mem_monitor_struct.h @@ -0,0 +1,247 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of log_setting register + * log config register + */ +typedef union { + struct { + /** log_mode : R/W; bitpos: [3:0]; default: 0; + * Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE + * monitor + */ + uint32_t log_mode:4; + /** log_mem_loop_enable : R/W; bitpos: [4]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ + uint32_t log_mem_loop_enable:1; + uint32_t reserved_5:3; + /** log_core_ena : R/W; bitpos: [15:8]; default: 0; + * enable core log + */ + uint32_t log_core_ena:8; + /** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0; + * enable dma_0 log + */ + uint32_t log_dma_0_ena:8; + /** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0; + * enable dma_1 log + */ + uint32_t log_dma_1_ena:8; + }; + uint32_t val; +} mem_monitor_log_setting_reg_t; + +/** Type of log_setting1 register + * log config register + */ +typedef union { + struct { + /** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0; + * enable dma_2 log + */ + uint32_t log_dma_2_ena:8; + /** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0; + * enable dma_3 log + */ + uint32_t log_dma_3_ena:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} mem_monitor_log_setting1_reg_t; + +/** Type of log_check_data register + * check data register + */ +typedef union { + struct { + /** log_check_data : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ + uint32_t log_check_data:32; + }; + uint32_t val; +} mem_monitor_log_check_data_reg_t; + +/** Type of log_data_mask register + * check data mask register + */ +typedef union { + struct { + /** log_data_mask : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ + uint32_t log_data_mask:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} mem_monitor_log_data_mask_reg_t; + +/** Type of log_min register + * log boundary register + */ +typedef union { + struct { + /** log_min : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ + uint32_t log_min:32; + }; + uint32_t val; +} mem_monitor_log_min_reg_t; + +/** Type of log_max register + * log boundary register + */ +typedef union { + struct { + /** log_max : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ + uint32_t log_max:32; + }; + uint32_t val; +} mem_monitor_log_max_reg_t; + +/** Type of log_mem_start register + * log message store range register + */ +typedef union { + struct { + /** log_mem_start : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ + uint32_t log_mem_start:32; + }; + uint32_t val; +} mem_monitor_log_mem_start_reg_t; + +/** Type of log_mem_end register + * log message store range register + */ +typedef union { + struct { + /** log_mem_end : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ + uint32_t log_mem_end:32; + }; + uint32_t val; +} mem_monitor_log_mem_end_reg_t; + +/** Type of log_mem_current_addr register + * current writing address. + */ +typedef union { + struct { + /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ + uint32_t log_mem_current_addr:32; + }; + uint32_t val; +} mem_monitor_log_mem_current_addr_reg_t; + +/** Type of log_mem_addr_update register + * writing address update + */ +typedef union { + struct { + /** log_mem_addr_update : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ + uint32_t log_mem_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_log_mem_addr_update_reg_t; + +/** Type of log_mem_full_flag register + * full flag status register + */ +typedef union { + struct { + /** log_mem_full_flag : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ + uint32_t log_mem_full_flag:1; + /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ + uint32_t clr_log_mem_full_flag:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mem_monitor_log_mem_full_flag_reg_t; + + +/** Group: clk register */ +/** Type of clock_gate register + * clock gate force on register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_clock_gate_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36708896; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mem_monitor_date_reg_t; + + +typedef struct { + volatile mem_monitor_log_setting_reg_t log_setting; + volatile mem_monitor_log_setting1_reg_t log_setting1; + volatile mem_monitor_log_check_data_reg_t log_check_data; + volatile mem_monitor_log_data_mask_reg_t log_data_mask; + volatile mem_monitor_log_min_reg_t log_min; + volatile mem_monitor_log_max_reg_t log_max; + volatile mem_monitor_log_mem_start_reg_t log_mem_start; + volatile mem_monitor_log_mem_end_reg_t log_mem_end; + volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr; + volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update; + volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag; + volatile mem_monitor_clock_gate_reg_t clock_gate; + uint32_t reserved_030[243]; + volatile mem_monitor_date_reg_t date; +} mem_monitor_dev_t; + +extern mem_monitor_dev_t MEM_MONITOR; + +#ifndef __cplusplus +_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_eco5_struct.h new file mode 100644 index 0000000000..c94e6559ab --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_eco5_struct.h @@ -0,0 +1,452 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: csi bridge regbank clock gating control register. */ +/** Type of clk_en register + * csi bridge register mapping unit clock gating. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 0: enable clock gating. 1: disable clock gating, clock always on. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_brg_clk_en_reg_t; + + +/** Group: csi bridge control registers. */ +/** Type of csi_en register + * csi bridge enable. + */ +typedef union { + struct { + /** csi_brg_en : R/W; bitpos: [0]; default: 0; + * 0: disable csi bridge. 1: enable csi bridge. + */ + uint32_t csi_brg_en:1; + /** csi_brg_rst : R/W; bitpos: [1]; default: 0; + * 0: release csi bridge reset. 1: enable csi bridge reset. + */ + uint32_t csi_brg_rst:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_brg_csi_en_reg_t; + +/** Type of buf_flow_ctl register + * csi bridge buffer control. + */ +typedef union { + struct { + /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040; + * buffer almost full threshold. + */ + uint32_t csi_buf_afull_thrd:14; + uint32_t reserved_14:2; + /** csi_buf_depth : RO; bitpos: [29:16]; default: 0; + * buffer data count. + */ + uint32_t csi_buf_depth:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} csi_brg_buf_flow_ctl_reg_t; + + +/** Group: csi bridge dma control registers. */ +/** Type of dma_req_cfg register + * dma request configuration. + */ +typedef union { + struct { + /** dma_burst_len : R/W; bitpos: [11:0]; default: 128; + * DMA burst length. + */ + uint32_t dma_burst_len:12; + /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0; + * 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: + * updated by frame. + */ + uint32_t dma_cfg_upd_by_blk:1; + uint32_t reserved_13:3; + /** dma_force_rd_status : R/W; bitpos: [16]; default: 0; + * 1: mask dma request when reading frame info. 0: disable mask. + */ + uint32_t dma_force_rd_status:1; + /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1; + * 0: dma as flow controller. 1: csi_bridge as flow controller + */ + uint32_t csi_dma_flow_controller:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} csi_brg_dma_req_cfg_reg_t; + +/** Type of dma_req_interval register + * DMA interval configuration. + */ +typedef union { + struct { + /** dma_req_interval : R/W; bitpos: [15:0]; default: 1; + * 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + */ + uint32_t dma_req_interval:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_brg_dma_req_interval_reg_t; + +/** Type of dmablk_size register + * DMA block size configuration. + */ +typedef union { + struct { + /** dmablk_size : R/W; bitpos: [12:0]; default: 8191; + * the number of reg_dma_burst_len in a block + */ + uint32_t dmablk_size:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} csi_brg_dmablk_size_reg_t; + + +/** Group: csi bridge frame format configuration registers. */ +/** Type of data_type_cfg register + * pixel data type configuration. + */ +typedef union { + struct { + /** data_type_min : R/W; bitpos: [5:0]; default: 24; + * the min value of data type used for pixel filter. + */ + uint32_t data_type_min:6; + uint32_t reserved_6:2; + /** data_type_max : R/W; bitpos: [13:8]; default: 47; + * the max value of data type used for pixel filter. + */ + uint32_t data_type_max:6; + uint32_t reserved_14:18; + }; + uint32_t val; +} csi_brg_data_type_cfg_reg_t; + +/** Type of frame_cfg register + * frame configuration. + */ +typedef union { + struct { + /** vadr_num : R/W; bitpos: [11:0]; default: 480; + * vadr of frame data. + */ + uint32_t vadr_num:12; + /** hadr_num : R/W; bitpos: [23:12]; default: 480; + * hadr of frame data. + */ + uint32_t hadr_num:12; + /** has_hsync_e : R/W; bitpos: [24]; default: 1; + * 0: frame data doesn't contain hsync. 1: frame data contains hsync. + */ + uint32_t has_hsync_e:1; + /** vadr_num_check : R/W; bitpos: [25]; default: 0; + * 0: disable vadr check. 1: enable vadr check. + */ + uint32_t vadr_num_check:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} csi_brg_frame_cfg_reg_t; + +/** Type of endian_mode register + * data endianness order configuration. + */ +typedef union { + struct { + /** byte_endian_order : R/W; bitpos: [0]; default: 0; + * endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) + * when isp is bapassed. + */ + uint32_t byte_endian_order:1; + /** bit_endian_order : R/W; bitpos: [1]; default: 0; + * N/A + */ + uint32_t bit_endian_order:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_brg_endian_mode_reg_t; + + +/** Group: csi bridge interrupt registers. */ +/** Type of int_raw register + * csi bridge interrupt raw. + */ +typedef union { + struct { + /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt raw. + */ + uint32_t vadr_num_gt_int_raw:1; + /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt raw. + */ + uint32_t vadr_num_lt_int_raw:1; + /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt raw. + */ + uint32_t discard_int_raw:1; + /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * buffer overrun interrupt raw. + */ + uint32_t csi_buf_overrun_int_raw:1; + /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * buffer overflow interrupt raw. + */ + uint32_t csi_async_fifo_ovf_int_raw:1; + /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * dma configuration update complete interrupt raw. + */ + uint32_t dma_cfg_has_updated_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_raw_reg_t; + +/** Type of int_clr register + * csi bridge interrupt clr. + */ +typedef union { + struct { + /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt clr. + */ + uint32_t vadr_num_gt_real_int_clr:1; + /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt clr. + */ + uint32_t vadr_num_lt_real_int_clr:1; + /** discard_int_clr : WT; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt clr. + */ + uint32_t discard_int_clr:1; + /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0; + * buffer overrun interrupt clr. + */ + uint32_t csi_buf_overrun_int_clr:1; + /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * buffer overflow interrupt clr. + */ + uint32_t csi_async_fifo_ovf_int_clr:1; + /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0; + * dma configuration update complete interrupt clr. + */ + uint32_t dma_cfg_has_updated_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_clr_reg_t; + +/** Type of int_st register + * csi bridge interrupt st. + */ +typedef union { + struct { + /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt st. + */ + uint32_t vadr_num_gt_int_st:1; + /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt st. + */ + uint32_t vadr_num_lt_int_st:1; + /** discard_int_st : RO; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt st. + */ + uint32_t discard_int_st:1; + /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0; + * buffer overrun interrupt st. + */ + uint32_t csi_buf_overrun_int_st:1; + /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * buffer overflow interrupt st. + */ + uint32_t csi_async_fifo_ovf_int_st:1; + /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0; + * dma configuration update complete interrupt st. + */ + uint32_t dma_cfg_has_updated_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_st_reg_t; + +/** Type of int_ena register + * csi bridge interrupt enable. + */ +typedef union { + struct { + /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt enable. + */ + uint32_t vadr_num_gt_int_ena:1; + /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt enable. + */ + uint32_t vadr_num_lt_int_ena:1; + /** discard_int_ena : R/W; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt enable. + */ + uint32_t discard_int_ena:1; + /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * buffer overrun interrupt enable. + */ + uint32_t csi_buf_overrun_int_ena:1; + /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * buffer overflow interrupt enable. + */ + uint32_t csi_async_fifo_ovf_int_ena:1; + /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0; + * dma configuration update complete interrupt enable. + */ + uint32_t dma_cfg_has_updated_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_ena_reg_t; + + +/** Group: csi-host control registers from csi bridge regbank. */ +/** Type of host_ctrl register + * csi host control by csi bridge. + */ +typedef union { + struct { + /** csi_enableclk : R/W; bitpos: [0]; default: 1; + * enable clock lane module of csi phy. + */ + uint32_t csi_enableclk:1; + /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1; + * enable cfg_clk of csi host module. + */ + uint32_t csi_cfg_clk_en:1; + /** loopbk_test_en : R/W; bitpos: [2]; default: 0; + * for phy test by loopback dsi phy to csi phy. + */ + uint32_t loopbk_test_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} csi_brg_host_ctrl_reg_t; + + +/** Group: csi host color mode control registers. */ +/** Type of host_cm_ctrl register + * CSI HOST color mode convert configuration. + */ +typedef union { + struct { + /** csi_host_cm_en : R/W; bitpos: [0]; default: 1; + * Configures whether to enable cm output + */ + uint32_t csi_host_cm_en:1; + /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_bypass:1; + /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_rx:2; + /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_rx_rgb_format:3; + /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_rx_yuv422_format:2; + /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_tx:2; + /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1; + * Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1: + * 2-lane + */ + uint32_t csi_host_cm_lane_num:1; + /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0; + * Configures whether to swap idi32 high and low 16-bit + */ + uint32_t csi_host_cm_16bit_swap:1; + /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0; + * Configures whether to swap idi32 high and low 8-bit + */ + uint32_t csi_host_cm_8bit_swap:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} csi_brg_host_cm_ctrl_reg_t; + +/** Type of host_size_ctrl register + * CSI HOST color mode convert configuration. + */ +typedef union { + struct { + /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0; + * Configures idi32 image size in y-direction, row_num - 1, valid only when + * yuv422_to_yuv420_en = 1 + */ + uint32_t csi_host_cm_vnum:12; + /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0; + * Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid + * only when yuv422_to_yuv420_en = 1 + */ + uint32_t csi_host_cm_hnum:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} csi_brg_host_size_ctrl_reg_t; + + +typedef struct { + volatile csi_brg_clk_en_reg_t clk_en; + volatile csi_brg_csi_en_reg_t csi_en; + volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg; + volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl; + volatile csi_brg_data_type_cfg_reg_t data_type_cfg; + volatile csi_brg_frame_cfg_reg_t frame_cfg; + volatile csi_brg_endian_mode_reg_t endian_mode; + volatile csi_brg_int_raw_reg_t int_raw; + volatile csi_brg_int_clr_reg_t int_clr; + volatile csi_brg_int_st_reg_t int_st; + volatile csi_brg_int_ena_reg_t int_ena; + volatile csi_brg_dma_req_interval_reg_t dma_req_interval; + volatile csi_brg_dmablk_size_reg_t dmablk_size; + uint32_t reserved_034[3]; + volatile csi_brg_host_ctrl_reg_t host_ctrl; + uint32_t reserved_044; + volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl; + volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl; +} csi_brg_dev_t; + +extern csi_brg_dev_t MIPI_CSI_BRIDGE; + +#ifndef __cplusplus +_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_reg.h new file mode 100644 index 0000000000..370f31c723 --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_reg.h @@ -0,0 +1,500 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CSI_BRIG_CLK_EN_REG register + * csi bridge register mapping unit clock gating. + */ +#define CSI_BRIG_CLK_EN_REG (DR_REG_CSI_BRIG_BASE + 0x0) +/** CSI_BRIG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 0: enable clock gating. 1: disable clock gating, clock always on. + */ +#define CSI_BRIG_CLK_EN (BIT(0)) +#define CSI_BRIG_CLK_EN_M (CSI_BRIG_CLK_EN_V << CSI_BRIG_CLK_EN_S) +#define CSI_BRIG_CLK_EN_V 0x00000001U +#define CSI_BRIG_CLK_EN_S 0 + +/** CSI_BRIG_CSI_EN_REG register + * csi bridge enable. + */ +#define CSI_BRIG_CSI_EN_REG (DR_REG_CSI_BRIG_BASE + 0x4) +/** CSI_BRIG_CSI_BRIG_EN : R/W; bitpos: [0]; default: 0; + * 0: disable csi bridge. 1: enable csi bridge. + */ +#define CSI_BRIG_CSI_BRIG_EN (BIT(0)) +#define CSI_BRIG_CSI_BRIG_EN_M (CSI_BRIG_CSI_BRIG_EN_V << CSI_BRIG_CSI_BRIG_EN_S) +#define CSI_BRIG_CSI_BRIG_EN_V 0x00000001U +#define CSI_BRIG_CSI_BRIG_EN_S 0 +/** CSI_BRIG_CSI_BRIG_RST : R/W; bitpos: [1]; default: 0; + * 0: release csi bridge reset. 1: enable csi bridge reset. + */ +#define CSI_BRIG_CSI_BRIG_RST (BIT(1)) +#define CSI_BRIG_CSI_BRIG_RST_M (CSI_BRIG_CSI_BRIG_RST_V << CSI_BRIG_CSI_BRIG_RST_S) +#define CSI_BRIG_CSI_BRIG_RST_V 0x00000001U +#define CSI_BRIG_CSI_BRIG_RST_S 1 + +/** CSI_BRIG_DMA_REQ_CFG_REG register + * dma request configuration. + */ +#define CSI_BRIG_DMA_REQ_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x8) +/** CSI_BRIG_DMA_BURST_LEN : R/W; bitpos: [11:0]; default: 128; + * DMA burst length. + */ +#define CSI_BRIG_DMA_BURST_LEN 0x00000FFFU +#define CSI_BRIG_DMA_BURST_LEN_M (CSI_BRIG_DMA_BURST_LEN_V << CSI_BRIG_DMA_BURST_LEN_S) +#define CSI_BRIG_DMA_BURST_LEN_V 0x00000FFFU +#define CSI_BRIG_DMA_BURST_LEN_S 0 +/** CSI_BRIG_DMA_CFG_UPD_BY_BLK : R/W; bitpos: [12]; default: 0; + * 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: + * updated by frame. + */ +#define CSI_BRIG_DMA_CFG_UPD_BY_BLK (BIT(12)) +#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_M (CSI_BRIG_DMA_CFG_UPD_BY_BLK_V << CSI_BRIG_DMA_CFG_UPD_BY_BLK_S) +#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_V 0x00000001U +#define CSI_BRIG_DMA_CFG_UPD_BY_BLK_S 12 +/** CSI_BRIG_DMA_FORCE_RD_STATUS : R/W; bitpos: [16]; default: 0; + * 1: mask dma request when reading frame info. 0: disable mask. + */ +#define CSI_BRIG_DMA_FORCE_RD_STATUS (BIT(16)) +#define CSI_BRIG_DMA_FORCE_RD_STATUS_M (CSI_BRIG_DMA_FORCE_RD_STATUS_V << CSI_BRIG_DMA_FORCE_RD_STATUS_S) +#define CSI_BRIG_DMA_FORCE_RD_STATUS_V 0x00000001U +#define CSI_BRIG_DMA_FORCE_RD_STATUS_S 16 +/** CSI_BRIG_CSI_DMA_FLOW_CONTROLLER : R/W; bitpos: [17]; default: 1; + * 0: dma as flow controller. 1: csi_bridge as flow controller + */ +#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER (BIT(17)) +#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_M (CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_V << CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_S) +#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_V 0x00000001U +#define CSI_BRIG_CSI_DMA_FLOW_CONTROLLER_S 17 + +/** CSI_BRIG_BUF_FLOW_CTL_REG register + * csi bridge buffer control. + */ +#define CSI_BRIG_BUF_FLOW_CTL_REG (DR_REG_CSI_BRIG_BASE + 0xc) +/** CSI_BRIG_CSI_BUF_AFULL_THRD : R/W; bitpos: [13:0]; default: 2040; + * buffer almost full threshold. + */ +#define CSI_BRIG_CSI_BUF_AFULL_THRD 0x00003FFFU +#define CSI_BRIG_CSI_BUF_AFULL_THRD_M (CSI_BRIG_CSI_BUF_AFULL_THRD_V << CSI_BRIG_CSI_BUF_AFULL_THRD_S) +#define CSI_BRIG_CSI_BUF_AFULL_THRD_V 0x00003FFFU +#define CSI_BRIG_CSI_BUF_AFULL_THRD_S 0 +/** CSI_BRIG_CSI_BUF_DEPTH : RO; bitpos: [29:16]; default: 0; + * buffer data count. + */ +#define CSI_BRIG_CSI_BUF_DEPTH 0x00003FFFU +#define CSI_BRIG_CSI_BUF_DEPTH_M (CSI_BRIG_CSI_BUF_DEPTH_V << CSI_BRIG_CSI_BUF_DEPTH_S) +#define CSI_BRIG_CSI_BUF_DEPTH_V 0x00003FFFU +#define CSI_BRIG_CSI_BUF_DEPTH_S 16 + +/** CSI_BRIG_DATA_TYPE_CFG_REG register + * pixel data type configuration. + */ +#define CSI_BRIG_DATA_TYPE_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x10) +/** CSI_BRIG_DATA_TYPE_MIN : R/W; bitpos: [5:0]; default: 24; + * the min value of data type used for pixel filter. + */ +#define CSI_BRIG_DATA_TYPE_MIN 0x0000003FU +#define CSI_BRIG_DATA_TYPE_MIN_M (CSI_BRIG_DATA_TYPE_MIN_V << CSI_BRIG_DATA_TYPE_MIN_S) +#define CSI_BRIG_DATA_TYPE_MIN_V 0x0000003FU +#define CSI_BRIG_DATA_TYPE_MIN_S 0 +/** CSI_BRIG_DATA_TYPE_MAX : R/W; bitpos: [13:8]; default: 47; + * the max value of data type used for pixel filter. + */ +#define CSI_BRIG_DATA_TYPE_MAX 0x0000003FU +#define CSI_BRIG_DATA_TYPE_MAX_M (CSI_BRIG_DATA_TYPE_MAX_V << CSI_BRIG_DATA_TYPE_MAX_S) +#define CSI_BRIG_DATA_TYPE_MAX_V 0x0000003FU +#define CSI_BRIG_DATA_TYPE_MAX_S 8 + +/** CSI_BRIG_FRAME_CFG_REG register + * frame configuration. + */ +#define CSI_BRIG_FRAME_CFG_REG (DR_REG_CSI_BRIG_BASE + 0x14) +/** CSI_BRIG_VADR_NUM : R/W; bitpos: [11:0]; default: 480; + * vadr of frame data. + */ +#define CSI_BRIG_VADR_NUM 0x00000FFFU +#define CSI_BRIG_VADR_NUM_M (CSI_BRIG_VADR_NUM_V << CSI_BRIG_VADR_NUM_S) +#define CSI_BRIG_VADR_NUM_V 0x00000FFFU +#define CSI_BRIG_VADR_NUM_S 0 +/** CSI_BRIG_HADR_NUM : R/W; bitpos: [23:12]; default: 480; + * hadr of frame data. + */ +#define CSI_BRIG_HADR_NUM 0x00000FFFU +#define CSI_BRIG_HADR_NUM_M (CSI_BRIG_HADR_NUM_V << CSI_BRIG_HADR_NUM_S) +#define CSI_BRIG_HADR_NUM_V 0x00000FFFU +#define CSI_BRIG_HADR_NUM_S 12 +/** CSI_BRIG_HAS_HSYNC_E : R/W; bitpos: [24]; default: 1; + * 0: frame data doesn't contain hsync. 1: frame data contains hsync. + */ +#define CSI_BRIG_HAS_HSYNC_E (BIT(24)) +#define CSI_BRIG_HAS_HSYNC_E_M (CSI_BRIG_HAS_HSYNC_E_V << CSI_BRIG_HAS_HSYNC_E_S) +#define CSI_BRIG_HAS_HSYNC_E_V 0x00000001U +#define CSI_BRIG_HAS_HSYNC_E_S 24 +/** CSI_BRIG_VADR_NUM_CHECK : R/W; bitpos: [25]; default: 0; + * 0: disable vadr check. 1: enable vadr check. + */ +#define CSI_BRIG_VADR_NUM_CHECK (BIT(25)) +#define CSI_BRIG_VADR_NUM_CHECK_M (CSI_BRIG_VADR_NUM_CHECK_V << CSI_BRIG_VADR_NUM_CHECK_S) +#define CSI_BRIG_VADR_NUM_CHECK_V 0x00000001U +#define CSI_BRIG_VADR_NUM_CHECK_S 25 + +/** CSI_BRIG_ENDIAN_MODE_REG register + * data endianness order configuration. + */ +#define CSI_BRIG_ENDIAN_MODE_REG (DR_REG_CSI_BRIG_BASE + 0x18) +/** CSI_BRIG_BYTE_ENDIAN_ORDER : R/W; bitpos: [0]; default: 0; + * endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) + * when isp is bapassed. + */ +#define CSI_BRIG_BYTE_ENDIAN_ORDER (BIT(0)) +#define CSI_BRIG_BYTE_ENDIAN_ORDER_M (CSI_BRIG_BYTE_ENDIAN_ORDER_V << CSI_BRIG_BYTE_ENDIAN_ORDER_S) +#define CSI_BRIG_BYTE_ENDIAN_ORDER_V 0x00000001U +#define CSI_BRIG_BYTE_ENDIAN_ORDER_S 0 +/** CSI_BRIG_BIT_ENDIAN_ORDER : R/W; bitpos: [1]; default: 0; + * N/A + */ +#define CSI_BRIG_BIT_ENDIAN_ORDER (BIT(1)) +#define CSI_BRIG_BIT_ENDIAN_ORDER_M (CSI_BRIG_BIT_ENDIAN_ORDER_V << CSI_BRIG_BIT_ENDIAN_ORDER_S) +#define CSI_BRIG_BIT_ENDIAN_ORDER_V 0x00000001U +#define CSI_BRIG_BIT_ENDIAN_ORDER_S 1 + +/** CSI_BRIG_INT_RAW_REG register + * csi bridge interrupt raw. + */ +#define CSI_BRIG_INT_RAW_REG (DR_REG_CSI_BRIG_BASE + 0x1c) +/** CSI_BRIG_VADR_NUM_GT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt raw. + */ +#define CSI_BRIG_VADR_NUM_GT_INT_RAW (BIT(0)) +#define CSI_BRIG_VADR_NUM_GT_INT_RAW_M (CSI_BRIG_VADR_NUM_GT_INT_RAW_V << CSI_BRIG_VADR_NUM_GT_INT_RAW_S) +#define CSI_BRIG_VADR_NUM_GT_INT_RAW_V 0x00000001U +#define CSI_BRIG_VADR_NUM_GT_INT_RAW_S 0 +/** CSI_BRIG_VADR_NUM_LT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt raw. + */ +#define CSI_BRIG_VADR_NUM_LT_INT_RAW (BIT(1)) +#define CSI_BRIG_VADR_NUM_LT_INT_RAW_M (CSI_BRIG_VADR_NUM_LT_INT_RAW_V << CSI_BRIG_VADR_NUM_LT_INT_RAW_S) +#define CSI_BRIG_VADR_NUM_LT_INT_RAW_V 0x00000001U +#define CSI_BRIG_VADR_NUM_LT_INT_RAW_S 1 +/** CSI_BRIG_DISCARD_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt raw. + */ +#define CSI_BRIG_DISCARD_INT_RAW (BIT(2)) +#define CSI_BRIG_DISCARD_INT_RAW_M (CSI_BRIG_DISCARD_INT_RAW_V << CSI_BRIG_DISCARD_INT_RAW_S) +#define CSI_BRIG_DISCARD_INT_RAW_V 0x00000001U +#define CSI_BRIG_DISCARD_INT_RAW_S 2 +/** CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * buffer overrun interrupt raw. + */ +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW (BIT(3)) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_V 0x00000001U +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_RAW_S 3 +/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * buffer overflow interrupt raw. + */ +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW (BIT(4)) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_V 0x00000001U +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_RAW_S 4 +/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * dma configuration update complete interrupt raw. + */ +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW (BIT(5)) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_V 0x00000001U +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_RAW_S 5 + +/** CSI_BRIG_INT_CLR_REG register + * csi bridge interrupt clr. + */ +#define CSI_BRIG_INT_CLR_REG (DR_REG_CSI_BRIG_BASE + 0x20) +/** CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR : WT; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt clr. + */ +#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR (BIT(0)) +#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_M (CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S) +#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_V 0x00000001U +#define CSI_BRIG_VADR_NUM_GT_REAL_INT_CLR_S 0 +/** CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR : WT; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt clr. + */ +#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR (BIT(1)) +#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_M (CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V << CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S) +#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_V 0x00000001U +#define CSI_BRIG_VADR_NUM_LT_REAL_INT_CLR_S 1 +/** CSI_BRIG_DISCARD_INT_CLR : WT; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt clr. + */ +#define CSI_BRIG_DISCARD_INT_CLR (BIT(2)) +#define CSI_BRIG_DISCARD_INT_CLR_M (CSI_BRIG_DISCARD_INT_CLR_V << CSI_BRIG_DISCARD_INT_CLR_S) +#define CSI_BRIG_DISCARD_INT_CLR_V 0x00000001U +#define CSI_BRIG_DISCARD_INT_CLR_S 2 +/** CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR : WT; bitpos: [3]; default: 0; + * buffer overrun interrupt clr. + */ +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR (BIT(3)) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_V 0x00000001U +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_CLR_S 3 +/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * buffer overflow interrupt clr. + */ +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR (BIT(4)) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_V 0x00000001U +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_CLR_S 4 +/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR : WT; bitpos: [5]; default: 0; + * dma configuration update complete interrupt clr. + */ +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR (BIT(5)) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_V 0x00000001U +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_CLR_S 5 + +/** CSI_BRIG_INT_ST_REG register + * csi bridge interrupt st. + */ +#define CSI_BRIG_INT_ST_REG (DR_REG_CSI_BRIG_BASE + 0x24) +/** CSI_BRIG_VADR_NUM_GT_INT_ST : RO; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt st. + */ +#define CSI_BRIG_VADR_NUM_GT_INT_ST (BIT(0)) +#define CSI_BRIG_VADR_NUM_GT_INT_ST_M (CSI_BRIG_VADR_NUM_GT_INT_ST_V << CSI_BRIG_VADR_NUM_GT_INT_ST_S) +#define CSI_BRIG_VADR_NUM_GT_INT_ST_V 0x00000001U +#define CSI_BRIG_VADR_NUM_GT_INT_ST_S 0 +/** CSI_BRIG_VADR_NUM_LT_INT_ST : RO; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt st. + */ +#define CSI_BRIG_VADR_NUM_LT_INT_ST (BIT(1)) +#define CSI_BRIG_VADR_NUM_LT_INT_ST_M (CSI_BRIG_VADR_NUM_LT_INT_ST_V << CSI_BRIG_VADR_NUM_LT_INT_ST_S) +#define CSI_BRIG_VADR_NUM_LT_INT_ST_V 0x00000001U +#define CSI_BRIG_VADR_NUM_LT_INT_ST_S 1 +/** CSI_BRIG_DISCARD_INT_ST : RO; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt st. + */ +#define CSI_BRIG_DISCARD_INT_ST (BIT(2)) +#define CSI_BRIG_DISCARD_INT_ST_M (CSI_BRIG_DISCARD_INT_ST_V << CSI_BRIG_DISCARD_INT_ST_S) +#define CSI_BRIG_DISCARD_INT_ST_V 0x00000001U +#define CSI_BRIG_DISCARD_INT_ST_S 2 +/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * buffer overrun interrupt st. + */ +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST (BIT(3)) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_V 0x00000001U +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ST_S 3 +/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * buffer overflow interrupt st. + */ +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST (BIT(4)) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_V 0x00000001U +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ST_S 4 +/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST : RO; bitpos: [5]; default: 0; + * dma configuration update complete interrupt st. + */ +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST (BIT(5)) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_V 0x00000001U +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ST_S 5 + +/** CSI_BRIG_INT_ENA_REG register + * csi bridge interrupt enable. + */ +#define CSI_BRIG_INT_ENA_REG (DR_REG_CSI_BRIG_BASE + 0x28) +/** CSI_BRIG_VADR_NUM_GT_INT_ENA : R/W; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt enable. + */ +#define CSI_BRIG_VADR_NUM_GT_INT_ENA (BIT(0)) +#define CSI_BRIG_VADR_NUM_GT_INT_ENA_M (CSI_BRIG_VADR_NUM_GT_INT_ENA_V << CSI_BRIG_VADR_NUM_GT_INT_ENA_S) +#define CSI_BRIG_VADR_NUM_GT_INT_ENA_V 0x00000001U +#define CSI_BRIG_VADR_NUM_GT_INT_ENA_S 0 +/** CSI_BRIG_VADR_NUM_LT_INT_ENA : R/W; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt enable. + */ +#define CSI_BRIG_VADR_NUM_LT_INT_ENA (BIT(1)) +#define CSI_BRIG_VADR_NUM_LT_INT_ENA_M (CSI_BRIG_VADR_NUM_LT_INT_ENA_V << CSI_BRIG_VADR_NUM_LT_INT_ENA_S) +#define CSI_BRIG_VADR_NUM_LT_INT_ENA_V 0x00000001U +#define CSI_BRIG_VADR_NUM_LT_INT_ENA_S 1 +/** CSI_BRIG_DISCARD_INT_ENA : R/W; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt enable. + */ +#define CSI_BRIG_DISCARD_INT_ENA (BIT(2)) +#define CSI_BRIG_DISCARD_INT_ENA_M (CSI_BRIG_DISCARD_INT_ENA_V << CSI_BRIG_DISCARD_INT_ENA_S) +#define CSI_BRIG_DISCARD_INT_ENA_V 0x00000001U +#define CSI_BRIG_DISCARD_INT_ENA_S 2 +/** CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * buffer overrun interrupt enable. + */ +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA (BIT(3)) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_M (CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V << CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S) +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_V 0x00000001U +#define CSI_BRIG_CSI_BUF_OVERRUN_INT_ENA_S 3 +/** CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * buffer overflow interrupt enable. + */ +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA (BIT(4)) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_M (CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V << CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S) +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_V 0x00000001U +#define CSI_BRIG_CSI_ASYNC_FIFO_OVF_INT_ENA_S 4 +/** CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA : R/W; bitpos: [5]; default: 0; + * dma configuration update complete interrupt enable. + */ +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA (BIT(5)) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_M (CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V << CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S) +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_V 0x00000001U +#define CSI_BRIG_DMA_CFG_HAS_UPDATED_INT_ENA_S 5 + +/** CSI_BRIG_DMA_REQ_INTERVAL_REG register + * DMA interval configuration. + */ +#define CSI_BRIG_DMA_REQ_INTERVAL_REG (DR_REG_CSI_BRIG_BASE + 0x2c) +/** CSI_BRIG_DMA_REQ_INTERVAL : R/W; bitpos: [15:0]; default: 1; + * 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + */ +#define CSI_BRIG_DMA_REQ_INTERVAL 0x0000FFFFU +#define CSI_BRIG_DMA_REQ_INTERVAL_M (CSI_BRIG_DMA_REQ_INTERVAL_V << CSI_BRIG_DMA_REQ_INTERVAL_S) +#define CSI_BRIG_DMA_REQ_INTERVAL_V 0x0000FFFFU +#define CSI_BRIG_DMA_REQ_INTERVAL_S 0 + +/** CSI_BRIG_DMABLK_SIZE_REG register + * DMA block size configuration. + */ +#define CSI_BRIG_DMABLK_SIZE_REG (DR_REG_CSI_BRIG_BASE + 0x30) +/** CSI_BRIG_DMABLK_SIZE : R/W; bitpos: [12:0]; default: 8191; + * the number of reg_dma_burst_len in a block + */ +#define CSI_BRIG_DMABLK_SIZE 0x00001FFFU +#define CSI_BRIG_DMABLK_SIZE_M (CSI_BRIG_DMABLK_SIZE_V << CSI_BRIG_DMABLK_SIZE_S) +#define CSI_BRIG_DMABLK_SIZE_V 0x00001FFFU +#define CSI_BRIG_DMABLK_SIZE_S 0 + +/** CSI_BRIG_HOST_CTRL_REG register + * csi host control by csi bridge. + */ +#define CSI_BRIG_HOST_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x40) +/** CSI_BRIG_CSI_ENABLECLK : R/W; bitpos: [0]; default: 1; + * enable clock lane module of csi phy. + */ +#define CSI_BRIG_CSI_ENABLECLK (BIT(0)) +#define CSI_BRIG_CSI_ENABLECLK_M (CSI_BRIG_CSI_ENABLECLK_V << CSI_BRIG_CSI_ENABLECLK_S) +#define CSI_BRIG_CSI_ENABLECLK_V 0x00000001U +#define CSI_BRIG_CSI_ENABLECLK_S 0 +/** CSI_BRIG_CSI_CFG_CLK_EN : R/W; bitpos: [1]; default: 1; + * enable cfg_clk of csi host module. + */ +#define CSI_BRIG_CSI_CFG_CLK_EN (BIT(1)) +#define CSI_BRIG_CSI_CFG_CLK_EN_M (CSI_BRIG_CSI_CFG_CLK_EN_V << CSI_BRIG_CSI_CFG_CLK_EN_S) +#define CSI_BRIG_CSI_CFG_CLK_EN_V 0x00000001U +#define CSI_BRIG_CSI_CFG_CLK_EN_S 1 +/** CSI_BRIG_LOOPBK_TEST_EN : R/W; bitpos: [2]; default: 0; + * for phy test by loopback dsi phy to csi phy. + */ +#define CSI_BRIG_LOOPBK_TEST_EN (BIT(2)) +#define CSI_BRIG_LOOPBK_TEST_EN_M (CSI_BRIG_LOOPBK_TEST_EN_V << CSI_BRIG_LOOPBK_TEST_EN_S) +#define CSI_BRIG_LOOPBK_TEST_EN_V 0x00000001U +#define CSI_BRIG_LOOPBK_TEST_EN_S 2 + +/** CSI_BRIG_HOST_CM_CTRL_REG register + * CSI HOST color mode convert configuration. + */ +#define CSI_BRIG_HOST_CM_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x48) +/** CSI_BRIG_CSI_HOST_CM_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to enable cm output + */ +#define CSI_BRIG_CSI_HOST_CM_EN (BIT(0)) +#define CSI_BRIG_CSI_HOST_CM_EN_M (CSI_BRIG_CSI_HOST_CM_EN_V << CSI_BRIG_CSI_HOST_CM_EN_S) +#define CSI_BRIG_CSI_HOST_CM_EN_V 0x00000001U +#define CSI_BRIG_CSI_HOST_CM_EN_S 0 +/** CSI_BRIG_CSI_HOST_CM_BYPASS : R/W; bitpos: [1]; default: 1; + * Configures whether to bypass cm + */ +#define CSI_BRIG_CSI_HOST_CM_BYPASS (BIT(1)) +#define CSI_BRIG_CSI_HOST_CM_BYPASS_M (CSI_BRIG_CSI_HOST_CM_BYPASS_V << CSI_BRIG_CSI_HOST_CM_BYPASS_S) +#define CSI_BRIG_CSI_HOST_CM_BYPASS_V 0x00000001U +#define CSI_BRIG_CSI_HOST_CM_BYPASS_S 1 +/** CSI_BRIG_CSI_HOST_CM_RX : R/W; bitpos: [3:2]; default: 0; + * Configures whether to bypass cm + */ +#define CSI_BRIG_CSI_HOST_CM_RX 0x00000003U +#define CSI_BRIG_CSI_HOST_CM_RX_M (CSI_BRIG_CSI_HOST_CM_RX_V << CSI_BRIG_CSI_HOST_CM_RX_S) +#define CSI_BRIG_CSI_HOST_CM_RX_V 0x00000003U +#define CSI_BRIG_CSI_HOST_CM_RX_S 2 +/** CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT : R/W; bitpos: [6:4]; default: 0; + * Configures whether to bypass cm + */ +#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT 0x00000007U +#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_M (CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_V << CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_S) +#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_V 0x00000007U +#define CSI_BRIG_CSI_HOST_CM_RX_RGB_FORMAT_S 4 +/** CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT : R/W; bitpos: [8:7]; default: 0; + * Configures whether to bypass cm + */ +#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT 0x00000003U +#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_M (CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_V << CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_S) +#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_V 0x00000003U +#define CSI_BRIG_CSI_HOST_CM_RX_YUV422_FORMAT_S 7 +/** CSI_BRIG_CSI_HOST_CM_TX : R/W; bitpos: [10:9]; default: 0; + * Configures whether to bypass cm + */ +#define CSI_BRIG_CSI_HOST_CM_TX 0x00000003U +#define CSI_BRIG_CSI_HOST_CM_TX_M (CSI_BRIG_CSI_HOST_CM_TX_V << CSI_BRIG_CSI_HOST_CM_TX_S) +#define CSI_BRIG_CSI_HOST_CM_TX_V 0x00000003U +#define CSI_BRIG_CSI_HOST_CM_TX_S 9 +/** CSI_BRIG_CSI_HOST_CM_LANE_NUM : R/W; bitpos: [11]; default: 1; + * Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1: + * 2-lane + */ +#define CSI_BRIG_CSI_HOST_CM_LANE_NUM (BIT(11)) +#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_M (CSI_BRIG_CSI_HOST_CM_LANE_NUM_V << CSI_BRIG_CSI_HOST_CM_LANE_NUM_S) +#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_V 0x00000001U +#define CSI_BRIG_CSI_HOST_CM_LANE_NUM_S 11 +/** CSI_BRIG_CSI_HOST_CM_16BIT_SWAP : R/W; bitpos: [12]; default: 0; + * Configures whether to swap idi32 high and low 16-bit + */ +#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP (BIT(12)) +#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_M (CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_V << CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_S) +#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_V 0x00000001U +#define CSI_BRIG_CSI_HOST_CM_16BIT_SWAP_S 12 +/** CSI_BRIG_CSI_HOST_CM_8BIT_SWAP : R/W; bitpos: [13]; default: 0; + * Configures whether to swap idi32 high and low 8-bit + */ +#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP (BIT(13)) +#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_M (CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_V << CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_S) +#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_V 0x00000001U +#define CSI_BRIG_CSI_HOST_CM_8BIT_SWAP_S 13 + +/** CSI_BRIG_HOST_SIZE_CTRL_REG register + * CSI HOST color mode convert configuration. + */ +#define CSI_BRIG_HOST_SIZE_CTRL_REG (DR_REG_CSI_BRIG_BASE + 0x4c) +/** CSI_BRIG_CSI_HOST_CM_VNUM : R/W; bitpos: [11:0]; default: 0; + * Configures idi32 image size in y-direction, row_num - 1, valid only when + * yuv422_to_yuv420_en = 1 + */ +#define CSI_BRIG_CSI_HOST_CM_VNUM 0x00000FFFU +#define CSI_BRIG_CSI_HOST_CM_VNUM_M (CSI_BRIG_CSI_HOST_CM_VNUM_V << CSI_BRIG_CSI_HOST_CM_VNUM_S) +#define CSI_BRIG_CSI_HOST_CM_VNUM_V 0x00000FFFU +#define CSI_BRIG_CSI_HOST_CM_VNUM_S 0 +/** CSI_BRIG_CSI_HOST_CM_HNUM : R/W; bitpos: [23:12]; default: 0; + * Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid + * only when yuv422_to_yuv420_en = 1 + */ +#define CSI_BRIG_CSI_HOST_CM_HNUM 0x00000FFFU +#define CSI_BRIG_CSI_HOST_CM_HNUM_M (CSI_BRIG_CSI_HOST_CM_HNUM_V << CSI_BRIG_CSI_HOST_CM_HNUM_S) +#define CSI_BRIG_CSI_HOST_CM_HNUM_V 0x00000FFFU +#define CSI_BRIG_CSI_HOST_CM_HNUM_S 12 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_struct.h new file mode 100644 index 0000000000..20b393afdb --- /dev/null +++ b/components/soc/esp32p4/register/hw_ver2/soc/mipi_csi_bridge_struct.h @@ -0,0 +1,372 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: csi bridge regbank clock gating control register. */ +/** Type of clk_en register + * csi bridge register mapping unit clock gating. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 0: enable clock gating. 1: disable clock gating, clock always on. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_brg_clk_en_reg_t; + + +/** Group: csi bridge control registers. */ +/** Type of csi_en register + * csi bridge enable. + */ +typedef union { + struct { + /** csi_brg_en : R/W; bitpos: [0]; default: 0; + * 0: disable csi bridge. 1: enable csi bridge. + */ + uint32_t csi_brg_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} csi_brg_csi_en_reg_t; + +/** Type of buf_flow_ctl register + * csi bridge buffer control. + */ +typedef union { + struct { + /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040; + * buffer almost full threshold. + */ + uint32_t csi_buf_afull_thrd:14; + uint32_t reserved_14:2; + /** csi_buf_depth : RO; bitpos: [29:16]; default: 0; + * buffer data count. + */ + uint32_t csi_buf_depth:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} csi_brg_buf_flow_ctl_reg_t; + + +/** Group: csi bridge dma control registers. */ +/** Type of dma_req_cfg register + * dma request configuration. + */ +typedef union { + struct { + /** dma_burst_len : R/W; bitpos: [11:0]; default: 128; + * DMA burst length. + */ + uint32_t dma_burst_len:12; + /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0; + * 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: + * updated by frame. + */ + uint32_t dma_cfg_upd_by_blk:1; + uint32_t reserved_13:3; + /** dma_force_rd_status : R/W; bitpos: [16]; default: 0; + * 1: mask dma request when reading frame info. 0: disable mask. + */ + uint32_t dma_force_rd_status:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} csi_brg_dma_req_cfg_reg_t; + +/** Type of dma_req_interval register + * DMA interval configuration. + */ +typedef union { + struct { + /** dma_req_interval : R/W; bitpos: [15:0]; default: 1; + * 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + */ + uint32_t dma_req_interval:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} csi_brg_dma_req_interval_reg_t; + +/** Type of dmablk_size register + * DMA block size configuration. + */ +typedef union { + struct { + /** dmablk_size : R/W; bitpos: [12:0]; default: 8191; + * the number of reg_dma_burst_len in a block + */ + uint32_t dmablk_size:13; + uint32_t reserved_13:19; + }; + uint32_t val; +} csi_brg_dmablk_size_reg_t; + + +/** Group: csi bridge frame format configuration registers. */ +/** Type of data_type_cfg register + * pixel data type configuration. + */ +typedef union { + struct { + /** data_type_min : R/W; bitpos: [5:0]; default: 24; + * the min value of data type used for pixel filter. + */ + uint32_t data_type_min:6; + uint32_t reserved_6:2; + /** data_type_max : R/W; bitpos: [13:8]; default: 47; + * the max value of data type used for pixel filter. + */ + uint32_t data_type_max:6; + uint32_t reserved_14:18; + }; + uint32_t val; +} csi_brg_data_type_cfg_reg_t; + +/** Type of frame_cfg register + * frame configuration. + */ +typedef union { + struct { + /** vadr_num : R/W; bitpos: [11:0]; default: 480; + * vadr of frame data. + */ + uint32_t vadr_num:12; + /** hadr_num : R/W; bitpos: [23:12]; default: 480; + * hadr of frame data. + */ + uint32_t hadr_num:12; + /** has_hsync_e : R/W; bitpos: [24]; default: 1; + * 0: frame data doesn't contain hsync. 1: frame data contains hsync. + */ + uint32_t has_hsync_e:1; + /** vadr_num_check : R/W; bitpos: [25]; default: 0; + * 0: disable vadr check. 1: enable vadr check. + */ + uint32_t vadr_num_check:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} csi_brg_frame_cfg_reg_t; + +/** Type of endian_mode register + * data endianness order configuration. + */ +typedef union { + struct { + /** byte_endian_order : R/W; bitpos: [0]; default: 0; + * endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) + * when isp is bapassed. + */ + uint32_t byte_endian_order:1; //byte_swap_en + /** bit_endian_order : R/W; bitpos: [1]; default: 0; + * N/A + */ + uint32_t bit_endian_order:1; //reserved + uint32_t reserved_2:30; + }; + uint32_t val; +} csi_brg_endian_mode_reg_t; + + +/** Group: csi bridge interrupt registers. */ +/** Type of int_raw register + * csi bridge interrupt raw. + */ +typedef union { + struct { + /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt raw. + */ + uint32_t vadr_num_gt_int_raw:1; + /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt raw. + */ + uint32_t vadr_num_lt_int_raw:1; + /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt raw. + */ + uint32_t discard_int_raw:1; + /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * buffer overrun interrupt raw. + */ + uint32_t csi_buf_overrun_int_raw:1; + /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * buffer overflow interrupt raw. + */ + uint32_t csi_async_fifo_ovf_int_raw:1; + /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * dma configuration update complete interrupt raw. + */ + uint32_t dma_cfg_has_updated_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_raw_reg_t; + +/** Type of int_clr register + * csi bridge interrupt clr. + */ +typedef union { + struct { + /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt clr. + */ + uint32_t vadr_num_gt_real_int_clr:1; + /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt clr. + */ + uint32_t vadr_num_lt_real_int_clr:1; + /** discard_int_clr : WT; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt clr. + */ + uint32_t discard_int_clr:1; + /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0; + * buffer overrun interrupt clr. + */ + uint32_t csi_buf_overrun_int_clr:1; + /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * buffer overflow interrupt clr. + */ + uint32_t csi_async_fifo_ovf_int_clr:1; + /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0; + * dma configuration update complete interrupt clr. + */ + uint32_t dma_cfg_has_updated_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_clr_reg_t; + +/** Type of int_st register + * csi bridge interrupt st. + */ +typedef union { + struct { + /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt st. + */ + uint32_t vadr_num_gt_int_st:1; + /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt st. + */ + uint32_t vadr_num_lt_int_st:1; + /** discard_int_st : RO; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt st. + */ + uint32_t discard_int_st:1; + /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0; + * buffer overrun interrupt st. + */ + uint32_t csi_buf_overrun_int_st:1; + /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * buffer overflow interrupt st. + */ + uint32_t csi_async_fifo_ovf_int_st:1; + /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0; + * dma configuration update complete interrupt st. + */ + uint32_t dma_cfg_has_updated_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_st_reg_t; + +/** Type of int_ena register + * csi bridge interrupt enable. + */ +typedef union { + struct { + /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0; + * reg_vadr_num is greater than real interrupt enable. + */ + uint32_t vadr_num_gt_int_ena:1; + /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0; + * reg_vadr_num is less than real interrupt enable. + */ + uint32_t vadr_num_lt_int_ena:1; + /** discard_int_ena : R/W; bitpos: [2]; default: 0; + * an incomplete frame of data was sent interrupt enable. + */ + uint32_t discard_int_ena:1; + /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * buffer overrun interrupt enable. + */ + uint32_t csi_buf_overrun_int_ena:1; + /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * buffer overflow interrupt enable. + */ + uint32_t csi_async_fifo_ovf_int_ena:1; + /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0; + * dma configuration update complete interrupt enable. + */ + uint32_t dma_cfg_has_updated_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} csi_brg_int_ena_reg_t; + + +/** Group: csi-host control registers from csi bridge regbank. */ +/** Type of host_ctrl register + * csi host control by csi bridge. + */ +typedef union { + struct { + /** csi_enableclk : R/W; bitpos: [0]; default: 1; + * enable clock lane module of csi phy. + */ + uint32_t csi_enableclk:1; + /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1; + * enable cfg_clk of csi host module. + */ + uint32_t csi_cfg_clk_en:1; + /** loopbk_test_en : R/W; bitpos: [2]; default: 0; + * for phy test by loopback dsi phy to csi phy. + */ + uint32_t loopbk_test_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} csi_brg_host_ctrl_reg_t; + + +typedef struct csi_brg_dev_t { + volatile csi_brg_clk_en_reg_t clk_en; + volatile csi_brg_csi_en_reg_t csi_en; + volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg; + volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl; + volatile csi_brg_data_type_cfg_reg_t data_type_cfg; + volatile csi_brg_frame_cfg_reg_t frame_cfg; + volatile csi_brg_endian_mode_reg_t endian_mode; + volatile csi_brg_int_raw_reg_t int_raw; + volatile csi_brg_int_clr_reg_t int_clr; + volatile csi_brg_int_st_reg_t int_st; + volatile csi_brg_int_ena_reg_t int_ena; + volatile csi_brg_dma_req_interval_reg_t dma_req_interval; + volatile csi_brg_dmablk_size_reg_t dmablk_size; + uint32_t reserved_034[3]; + volatile csi_brg_host_ctrl_reg_t host_ctrl; +} csi_brg_dev_t; + +extern csi_brg_dev_t MIPI_CSI_BRIDGE; + +#ifndef __cplusplus +_Static_assert(sizeof(csi_brg_dev_t) == 0x44, "Invalid size of csi_brg_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif