From 24486dd06908ea6339ca72cc37e3e01e57193a7b Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Tue, 16 May 2023 16:21:11 +0800 Subject: [PATCH] Power Management: support PAU REGDMA feature for esp32h2 --- .../include/esp_private/esp_pau.h | 20 +++ .../esp_hw_support/port/esp32h2/pmu_sleep.c | 11 +- components/esp_hw_support/port/pau_regdma.c | 23 +++- .../hal/esp32h2/include/hal/clk_gate_ll.h | 8 ++ components/hal/esp32h2/include/hal/pau_ll.h | 125 ++++++++++++++++++ components/hal/esp32h2/pau_hal.c | 59 +++++++++ components/hal/include/hal/pau_hal.h | 26 ++++ .../esp32h2/include/soc/Kconfig.soc_caps.in | 12 ++ .../soc/esp32h2/include/soc/pau_struct.h | 4 +- .../soc/esp32h2/include/soc/periph_defs.h | 1 + components/soc/esp32h2/include/soc/soc_caps.h | 3 + 11 files changed, 283 insertions(+), 9 deletions(-) create mode 100644 components/hal/esp32h2/include/hal/pau_ll.h create mode 100644 components/hal/esp32h2/pau_hal.c diff --git a/components/esp_hw_support/include/esp_private/esp_pau.h b/components/esp_hw_support/include/esp_private/esp_pau.h index 66c5e6ab3a..db6b059d27 100644 --- a/components/esp_hw_support/include/esp_private/esp_pau.h +++ b/components/esp_hw_support/include/esp_private/esp_pau.h @@ -25,6 +25,7 @@ extern "C" { */ void pau_regdma_set_entry_link_addr(pau_regdma_link_addr_t *link_entries); +#if SOC_PM_SUPPORT_PMU_MODEM_STATE /** * @brief Set the address of WiFi MAC REGDMA Link in modem state * @param link_addr linked lists address @@ -40,6 +41,25 @@ void pau_regdma_trigger_modem_link_backup(void); * @brief Software trigger regdma to perform modem link restore */ void pau_regdma_trigger_modem_link_restore(void); +#endif + +#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +/** + * @brief Set the address of system REGDMA Link in active state + * @param link_addr linked lists address + */ +void pau_regdma_set_system_link_addr(void *link_addr); + +/** + * @brief Software trigger regdma to perform system link backup + */ +void pau_regdma_trigger_system_link_backup(void); + +/** + * @brief Software trigger regdma to perform system link restore + */ +void pau_regdma_trigger_system_link_restore(void); +#endif /** * @brief Set the address of extra REGDMA Link in active state diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c index d1e9b51723..117ff51adb 100644 --- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c @@ -22,16 +22,15 @@ void pmu_sleep_enable_regdma_backup(void) { - assert(PMU_instance()->hal); - /* entry 0 is used by pmu HP_SLEEP and HP_ACTIVE states switching. - * entry 1, 2, 3 is reserved, not used yet! */ - pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal); + /* ESP32H2 does not have PMU HP_AON power domain. because the registers + * of PAU REGDMA is included to PMU TOP power domain, cause the contents + * of PAU REGDMA registers will be lost when the TOP domain is powered down + * during light sleep, so we does not need to enable REGDMA backup here. + * We will use the software to trigger REGDMA to backup or restore. */ } void pmu_sleep_disable_regdma_backup(void) { - assert(PMU_instance()->hal); - pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal); } uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period) diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c index 5d340c1b0a..6e8e4c8970 100644 --- a/components/esp_hw_support/port/pau_regdma.c +++ b/components/esp_hw_support/port/pau_regdma.c @@ -21,7 +21,7 @@ typedef struct { pau_hal_context_t *hal; } pau_context_t; -pau_context_t * __attribute__((weak)) PAU_instance(void) +pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void) { static pau_hal_context_t pau_hal = { .dev = NULL }; static pau_context_t pau_context = { .hal = &pau_hal }; @@ -40,6 +40,7 @@ void pau_regdma_set_entry_link_addr(pau_regdma_link_addr_t *link_entries) pau_hal_set_regdma_entry_link_addr(PAU_instance()->hal, link_entries); } +#if SOC_PM_SUPPORT_PMU_MODEM_STATE void pau_regdma_set_modem_link_addr(void *link_addr) { pau_hal_set_regdma_modem_link_addr(PAU_instance()->hal, link_addr); @@ -56,6 +57,26 @@ void pau_regdma_trigger_modem_link_restore(void) pau_hal_start_regdma_modem_link(PAU_instance()->hal, false); pau_hal_stop_regdma_modem_link(PAU_instance()->hal); } +#endif + +#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +void IRAM_ATTR pau_regdma_set_system_link_addr(void *link_addr) +{ + pau_hal_set_regdma_system_link_addr(PAU_instance()->hal, link_addr); +} + +void IRAM_ATTR pau_regdma_trigger_system_link_backup(void) +{ + pau_hal_start_regdma_system_link(PAU_instance()->hal, true); + pau_hal_stop_regdma_system_link(PAU_instance()->hal); +} + +void IRAM_ATTR pau_regdma_trigger_system_link_restore(void) +{ + pau_hal_start_regdma_system_link(PAU_instance()->hal, false); + pau_hal_stop_regdma_system_link(PAU_instance()->hal); +} +#endif void pau_regdma_set_extra_link_addr(void *link_addr) { diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h index 08b7894c55..7a8cf3b84d 100644 --- a/components/hal/esp32h2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h @@ -75,6 +75,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return PCR_ECDSA_CLK_EN; case PERIPH_TEMPSENSOR_MODULE: return PCR_TSENS_CLK_EN; + case PERIPH_REGDMA_MODULE: + return PCR_REGDMA_CLK_EN; // case PERIPH_RNG_MODULE: // return PCR_WIFI_CLK_RNG_EN; // case PERIPH_WIFI_MODULE: @@ -146,6 +148,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en CLEAR_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN); } return PCR_ECC_RST_EN; + case PERIPH_REGDMA_MODULE: + return PCR_REGDMA_RST_EN; case PERIPH_AES_MODULE: if (enable == true) { // Clear reset on digital signature, otherwise AES unit is held in reset @@ -257,6 +261,8 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) return PCR_ECDSA_CONF_REG; case PERIPH_TEMPSENSOR_MODULE: return PCR_TSENS_CLK_CONF_REG; + case PERIPH_REGDMA_MODULE: + return PCR_REGDMA_CONF_REG; default: return 0; } @@ -322,6 +328,8 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) return PCR_ECDSA_CONF_REG; case PERIPH_TEMPSENSOR_MODULE: return PCR_TSENS_CLK_CONF_REG; + case PERIPH_REGDMA_MODULE: + return PCR_REGDMA_CONF_REG; default: return 0; } diff --git a/components/hal/esp32h2/include/hal/pau_ll.h b/components/hal/esp32h2/include/hal/pau_ll.h new file mode 100644 index 0000000000..98f730ff25 --- /dev/null +++ b/components/hal/esp32h2/include/hal/pau_ll.h @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H2 PAU(Power Assist Unit) register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/pau_reg.h" +#include "soc/pau_struct.h" +#include "hal/pau_types.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) +{ + return dev->regdma_conf.flow_err; +} + +static inline __attribute__((always_inline)) void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) +{ + dev->regdma_conf.link_sel = link; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem = to_mem ? 1 : 0; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +{ + dev->regdma_conf.start = 1; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) +{ + dev->regdma_conf.start = 0; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr) +{ + dev->regdma_link_0_addr.val = (uint32_t)link_addr; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr) +{ + dev->regdma_link_1_addr.val = (uint32_t)link_addr; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr) +{ + dev->regdma_link_2_addr.val = (uint32_t)link_addr; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr) +{ + dev->regdma_link_3_addr.val = (uint32_t)link_addr; +} + +static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) +{ + return dev->regdma_current_link_addr.val; +} + +static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) +{ + return dev->regdma_backup_addr.val; +} + +static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) +{ + return dev->regdma_mem_addr.val; +} + +static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) +{ + return dev->int_raw.val; +} + +static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) +{ + return dev->int_st.val; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +{ + dev->int_ena.done_int_ena = 1; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) +{ + dev->int_ena.done_int_ena = 0; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) +{ + dev->int_ena.error_int_ena = 1; +} + +static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) +{ + dev->int_ena.error_int_ena = 0; +} + +static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) +{ + dev->int_clr.done_int_clr = 1; +} + +static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) +{ + dev->int_clr.error_int_clr = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/pau_hal.c b/components/hal/esp32h2/pau_hal.c new file mode 100644 index 0000000000..3f7ba1aab2 --- /dev/null +++ b/components/hal/esp32h2/pau_hal.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for PAU (ESP32-H2 specific part) + +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/pau_hal.h" +#include "hal/pau_types.h" + +void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) +{ + /* ESP32H2 does not have PMU HP_AON power domain. because the registers + * of PAU REGDMA is included to PMU TOP power domain, cause the contents + * of PAU REGDMA registers will be lost when the TOP domain is powered down + * during light sleep, so we does not need to enable REGDMA backup here. + * We will use the software to trigger REGDMA to backup or restore. */ +} + +void IRAM_ATTR pau_hal_start_regdma_system_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + + pau_ll_select_regdma_entry_link(hal->dev, 0); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_system_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +void pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + /* The link 3 of REGDMA is reserved, we use it as an extra linked list to + * provide backup and restore services for BLE, IEEE802.15.4 and possibly + * other modules */ + pau_ll_select_regdma_entry_link(hal->dev, 3); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} diff --git a/components/hal/include/hal/pau_hal.h b/components/hal/include/hal/pau_hal.h index 403765eef6..5b28a957d2 100644 --- a/components/hal/include/hal/pau_hal.h +++ b/components/hal/include/hal/pau_hal.h @@ -28,6 +28,7 @@ typedef struct { */ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr); +#if SOC_PM_SUPPORT_PMU_MODEM_STATE /** * @brief Set regdma modem link address * @@ -50,6 +51,31 @@ void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_rest * @param hal regdma hal context */ void pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal); +#endif + +#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG +/** + * @brief Set regdma system link address + * + * @param hal regdma hal context + * @param link_addr main link address value + */ +#define pau_hal_set_regdma_system_link_addr(hal, addr) pau_ll_set_regdma_link0_addr(hal->dev, (addr)) + +/** + * @brief Start transmission on regdma system link + * + * @param hal regdma hal context + * @param backup_or_restore false:restore true:backup + */ +void pau_hal_start_regdma_system_link(pau_hal_context_t *hal, bool backup_or_restore); +/** + * @brief Stop transmission on regdma system link + * + * @param hal regdma hal context + */ +void pau_hal_stop_regdma_system_link(pau_hal_context_t *hal); +#endif /** * @brief Set regdma extra link address diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index e00e6bd072..b1c8cc1a05 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -171,6 +171,10 @@ config SOC_LP_TIMER_SUPPORTED bool default y +config SOC_PAU_SUPPORTED + bool + default y + config SOC_CLK_TREE_SUPPORTED bool default y @@ -1079,6 +1083,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD bool default y +config SOC_PM_PAU_LINK_NUM + int + default 4 + config SOC_PM_CPU_RETENTION_BY_SW bool default y @@ -1087,6 +1095,10 @@ config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY bool default y +config SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG + bool + default y + config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool default y diff --git a/components/soc/esp32h2/include/soc/pau_struct.h b/components/soc/esp32h2/include/soc/pau_struct.h index 610b0e4e07..9fd6347265 100644 --- a/components/soc/esp32h2/include/soc/pau_struct.h +++ b/components/soc/esp32h2/include/soc/pau_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -334,7 +334,7 @@ typedef union { } pau_date_reg_t; -typedef struct { +typedef struct pau_dev_t { volatile pau_regdma_conf_reg_t regdma_conf; volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h index 5a954b200d..b4f30cd754 100644 --- a/components/soc/esp32h2/include/soc/periph_defs.h +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -41,6 +41,7 @@ typedef enum { PERIPH_SYSTIMER_MODULE, PERIPH_SARADC_MODULE, PERIPH_TEMPSENSOR_MODULE, + PERIPH_REGDMA_MODULE, /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ PERIPH_BT_MODULE, PERIPH_IEEE802154_MODULE, diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 5cbb9e1f32..7e8d80ae80 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -68,6 +68,7 @@ #define SOC_APM_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 +#define SOC_PAU_SUPPORTED 1 #define SOC_CLK_TREE_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ @@ -453,8 +454,10 @@ #define SOC_PM_SUPPORT_RC32K_PD (1) #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) +#define SOC_PM_PAU_LINK_NUM (4) #define SOC_PM_CPU_RETENTION_BY_SW (1) #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!