espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-12-01 06:39:27 +01:00
Code Issues Packages Projects Releases Wiki Activity

rtc: support access internal i2c register

Browse Source
This commit is contained in:
fuzhibo
2020-08-06 20:46:45 +08:00
parent b07a60c0b8
commit 247789bb2e
7 changed files with 286 additions and 99 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
components/soc/src/esp32s2/CMakeLists.txt
View File

@@ -1,5 +1,6 @@
set(srcs
"rtc_clk.c"
"i2c_rtc_clk.c"
"rtc_clk_init.c"
"rtc_init.c"
"rtc_pm.c"

169
components/soc/src/esp32s2/i2c_rtc_clk.c Normal file
View File

@@ -0,0 +1,169 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_err.h"
#include "soc/soc.h"
#include "soc/apb_ctrl_reg.h"
#include "i2c_rtc_clk.h"
#include "i2c_brownout.h"
#include "esp_log.h"
#define I2C_RTC_WIFI_CLK_EN (APB_CTRL_WIFI_CLK_EN_REG)
#define I2C_RTC_CLK_GATE_EN (BIT(18))
#define I2C_RTC_CLK_GATE_EN_M (BIT(18))
#define I2C_RTC_CLK_GATE_EN_V 0x1
#define I2C_RTC_CLK_GATE_EN_S 18
#define I2C_RTC_CONFIG0 0x6000e048
#define I2C_RTC_MAGIC_CTRL 0x00001FFF
#define I2C_RTC_MAGIC_CTRL_M ((I2C_RTC_MAGIC_CTRL_V)<<(I2C_RTC_MAGIC_CTRL_S))
#define I2C_RTC_MAGIC_CTRL_V 0x1FFF
#define I2C_RTC_MAGIC_CTRL_S 4
#define I2C_RTC_CONFIG1 0x6000e044
#define I2C_RTC_BOD_MASK (BIT(22))
#define I2C_RTC_BOD_MASK_M (BIT(22))
#define I2C_RTC_BOD_MASK_V 0x1
#define I2C_RTC_BOD_MASK_S 22
#define I2C_RTC_SAR_MASK (BIT(18))
#define I2C_RTC_SAR_MASK_M (BIT(18))
#define I2C_RTC_SAR_MASK_V 0x1
#define I2C_RTC_SAR_MASK_S 18
#define I2C_RTC_BBPLL_MASK (BIT(17))
#define I2C_RTC_BBPLL_MASK_M (BIT(17))
#define I2C_RTC_BBPLL_MASK_V 0x1
#define I2C_RTC_BBPLL_MASK_S 17
#define I2C_RTC_APLL_MASK (BIT(14))
#define I2C_RTC_APLL_MASK_M (BIT(14))
#define I2C_RTC_APLL_MASK_V 0x1
#define I2C_RTC_APLL_MASK_S 14
#define I2C_RTC_ALL_MASK 0x00007FFF
#define I2C_RTC_ALL_MASK_M ((I2C_RTC_ALL_MASK_V)<<(I2C_RTC_ALL_MASK_S))
#define I2C_RTC_ALL_MASK_V 0x7FFF
#define I2C_RTC_ALL_MASK_S 8
#define I2C_RTC_CONFIG2 0x6000e000
#define I2C_RTC_BUSY (BIT(25))
#define I2C_RTC_BUSY_M (BIT(25))
#define I2C_RTC_BUSY_V 0x1
#define I2C_RTC_BUSY_S 25
#define I2C_RTC_WR_CNTL (BIT(24))
#define I2C_RTC_WR_CNTL_M (BIT(24))
#define I2C_RTC_WR_CNTL_V 0x1
#define I2C_RTC_WR_CNTL_S 24
#define I2C_RTC_DATA 0x000000FF
#define I2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
#define I2C_RTC_DATA_V 0xFF
#define I2C_RTC_DATA_S 16
#define I2C_RTC_ADDR 0x000000FF
#define I2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
#define I2C_RTC_ADDR_V 0xFF
#define I2C_RTC_ADDR_S 8
#define I2C_RTC_SLAVE_ID 0x000000FF
#define I2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
#define I2C_RTC_SLAVE_ID_V 0xFF
#define I2C_RTC_SLAVE_ID_S 0
#define I2C_RTC_MAGIC_DEFAULT (0x1c40)
static void i2c_rtc_enable_block(uint8_t block)
{
REG_SET_FIELD(I2C_RTC_CONFIG0, I2C_RTC_MAGIC_CTRL, I2C_RTC_MAGIC_DEFAULT);
REG_SET_FIELD(I2C_RTC_CONFIG1, I2C_RTC_ALL_MASK, I2C_RTC_ALL_MASK_V);
REG_SET_BIT(I2C_RTC_WIFI_CLK_EN, I2C_RTC_CLK_GATE_EN);
switch (block) {
case I2C_APLL:
REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_APLL_MASK);
break;
case I2C_BBPLL:
REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BBPLL_MASK);
break;
case I2C_SAR_ADC:
REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_SAR_MASK);
break;
case I2C_BOD:
REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BOD_MASK);
break;
}
}
uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
{
i2c_rtc_enable_block(block);
uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
| (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
REG_WRITE(I2C_RTC_CONFIG2, temp);
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
}
uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
{
assert(msb - lsb < 8);
i2c_rtc_enable_block(block);
uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
| (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
REG_WRITE(I2C_RTC_CONFIG2, temp);
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
uint32_t data = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
}
void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
{
i2c_rtc_enable_block(block);
uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
| ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
| ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
| (((uint32_t)data & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
REG_WRITE(I2C_RTC_CONFIG2, temp);
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
}
void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
{
assert(msb - lsb < 8);
i2c_rtc_enable_block(block);
/*Read the i2c bus register*/
uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
| (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
REG_WRITE(I2C_RTC_CONFIG2, temp);
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
temp = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
/*Write the i2c bus register*/
temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
| ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
| ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
| ((temp & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
REG_WRITE(I2C_RTC_CONFIG2, temp);
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
}

20
components/soc/src/esp32s2/i2c_rtc_clk.h
View File

@@ -17,6 +17,7 @@
#include "i2c_apll.h"
#include "i2c_bbpll.h"
#include "i2c_ulp.h"
#include "i2c_saradc.h"
#ifdef __cplusplus
extern "C" {
@@ -31,26 +32,27 @@ extern "C" {
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
/* Read/Write internal control bus */
uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
void i2c_rtc_init(void);
/* Convenience macros for the above functions, these use register definitions
* from i2c_apll.h/i2c_bbpll.h header files.
*/
#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
i2c_rtc_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define I2C_READREG_MASK_RTC(block, reg_add) \
rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
i2c_rtc_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define I2C_WRITEREG_RTC(block, reg_add, indata) \
rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
i2c_rtc_write_reg(block, block##_HOSTID, reg_add, indata)
#define I2C_READREG_RTC(block, reg_add) \
rom_i2c_readReg(block, block##_HOSTID, reg_add)
i2c_rtc_read_reg(block, block##_HOSTID, reg_add)
#ifdef __cplusplus
}

3
components/soc/src/esp32s2/rtc_clk.c
View File

@@ -289,7 +289,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
abort();
}
}
s_cur_pll_freq = pll_freq;
s_cur_pll_freq = pll_freq;
}
/**