refactor(dedic_gpio): clean up dedic gpio soc caps

components/esp_driver_gpio/src/dedic_gpio.c

@@ -15,7 +15,7 @@
 #include "esp_log.h"
 #include "esp_check.h"
 #include "esp_cpu.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 #include "soc/io_mux_reg.h"
 #include "hal/dedic_gpio_cpu_ll.h"
 #include "esp_private/gpio.h"
@@ -25,10 +25,10 @@
 #include "driver/dedic_gpio.h"
 #include "soc/dedic_gpio_periph.h"
 
-#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
 #include "soc/dedic_gpio_struct.h"
 #endif
-#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
 #include "hal/dedic_gpio_ll.h"
 #endif
 
@@ -50,11 +50,11 @@ struct dedic_gpio_platform_t {
     uint32_t in_occupied_mask;  // mask of input channels that already occupied
 #if SOC_DEDIC_GPIO_HAS_INTERRUPT
     intr_handle_t intr_hdl;     // interrupt handle
-    dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_IN_CHANNELS_NUM];   // array of callback function for input channel
+    dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)];   // array of callback function for input channel
-    void *cb_args[SOC_DEDIC_GPIO_IN_CHANNELS_NUM];                   // array of callback arguments for input channel
+    void *cb_args[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)];                   // array of callback arguments for input channel
-    dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // which bundle belongs to for input channel
+    dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)]; // which bundle belongs to for input channel
 #endif
-#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
     dedic_dev_t *dev;
 #endif
 };
@@ -81,18 +81,18 @@ static esp_err_t dedic_gpio_build_platform(int core_id)
                 // initialize platform members
                 s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
                 // initial occupy_mask: 1111...100...0
-                s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1);
+                s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1);
-                s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);
+                s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1);
-#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
                 s_platform[core_id]->dev = &DEDIC_GPIO;
-#endif // SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
+#endif // DEDIC_GPIO_LL_ALLOW_REG_ACCESS
-#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
                 // enable dedicated GPIO register clock
                 PERIPH_RCC_ATOMIC() {
                     dedic_gpio_ll_enable_bus_clock(true);
                     dedic_gpio_ll_reset_register();
                 }
-#endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
             }
         }
         _lock_release(&s_platform_mutexlock[core_id]);
@@ -113,12 +113,12 @@ static void dedic_gpio_break_platform(int core_id)
         if (s_platform[core_id]) {
             free(s_platform[core_id]);
             s_platform[core_id] = NULL;
-#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+#if !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
             // disable the register clock if no GPIO channel is in use
             PERIPH_RCC_ATOMIC() {
                 dedic_gpio_ll_enable_bus_clock(false);
             }
-#endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
+#endif // !DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE
         }
         _lock_release(&s_platform_mutexlock[core_id]);
     }
@@ -222,11 +222,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
     // configure outwards channels
     uint32_t out_offset = 0;
     if (config->flags.out_en) {
-        ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM, ESP_ERR_INVALID_ARG, err, TAG,
+        ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG,
-                          "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM);
+                          "array size(%d) exceeds maximum supported out channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU));
         // prevent install bundle concurrently
         portENTER_CRITICAL(&s_platform[core_id]->spinlock);
-        for (size_t i = 0; i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size; i++) {
+        for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) - config->array_size; i++) {
             if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) {
                 out_mask = pattern << i;
                 out_offset = i;
@@ -235,7 +235,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
         }
         if (out_mask) {
             s_platform[core_id]->out_occupied_mask |= out_mask;
-#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
+#if DEDIC_GPIO_LL_ALLOW_REG_ACCESS
             // always enable instruction to access output GPIO, which has better performance than register access
             dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true);
 #endif
@@ -248,11 +248,11 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
     // configure inwards channels
     uint32_t in_offset = 0;
     if (config->flags.in_en) {
-        ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM, ESP_ERR_INVALID_ARG, err, TAG,
+        ESP_GOTO_ON_FALSE(config->array_size <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU), ESP_ERR_INVALID_ARG, err, TAG,
-                          "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM);
+                          "array size(%d) exceeds maximum supported in channels(%d)", config->array_size, SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU));
         // prevent install bundle concurrently
         portENTER_CRITICAL(&s_platform[core_id]->spinlock);
-        for (size_t i = 0; i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size; i++) {
+        for (size_t i = 0; i <= SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU) - config->array_size; i++) {
             if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) {
                 in_mask = pattern << i;
                 in_offset = i;
@@ -280,9 +280,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
             gpio_func_sel(config->gpio_array[i], PIN_FUNC_GPIO);
             esp_rom_gpio_connect_out_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].out_sig_per_channel[out_offset + i], config->flags.out_invert, false);
         }
-#if !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
         dedic_gpio_cpu_ll_enable_output(s_platform[core_id]->out_occupied_mask);
-#endif // !SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
     }
 
     // it's safe to initialize bundle members without locks here
@@ -322,8 +320,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
     portENTER_CRITICAL(&s_platform[core_id]->spinlock);
     s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask);
     s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask);
-    if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1)) &&
+    if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)) - 1)) &&
-            s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1))) {
+            s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)) - 1))) {
         recycle_all = true;
     }
     portEXIT_CRITICAL(&s_platform[core_id]->spinlock);

components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,16 +11,17 @@
 #include "unity.h"
 #include "unity_test_utils.h"
 #include "esp_rom_sys.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
+#include "soc/dedic_gpio_periph.h"
 #include "hal/dedic_gpio_cpu_ll.h"
 #include "driver/gpio.h"
 #include "driver/dedic_gpio.h"
 
 TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]")
 {
-    const int test_gpios[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM / 2] = {0};
+    const int test_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2] = {0};
-    const int test2_gpios[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM / 2 + 1] = {0};
+    const int test2_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2 + 1] = {0};
-    const int test3_gpios[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + 1] = {0};
+    const int test3_gpios[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) + 1] = {0};
     dedic_gpio_bundle_handle_t test_bundle, test_bundle2, test_bundle3 = NULL;
     dedic_gpio_bundle_config_t bundle_config = {
         .gpio_array = test_gpios,
@@ -47,7 +48,7 @@ TEST_CASE("Dedicated_GPIO_bundle_install/uninstall", "[dedic_gpio]")
     TEST_ASSERT_EQUAL_MESSAGE(ESP_OK, dedic_gpio_new_bundle(&bundle_config, &test_bundle), "create bundle with half channels failed");
     uint32_t mask = 0;
     TEST_ESP_OK(dedic_gpio_get_out_mask(test_bundle, &mask));
-    TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_OUT_CHANNELS_NUM / 2)) - 1, mask, "wrong out mask");
+    TEST_ASSERT_EQUAL_MESSAGE((1 << (SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU) / 2)) - 1, mask, "wrong out mask");
     TEST_ESP_OK(dedic_gpio_get_in_mask(test_bundle, &mask));
     TEST_ASSERT_EQUAL_MESSAGE(0, mask, "wrong in mask");
 

components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,7 +12,7 @@
 #include "unity.h"
 #include "driver/gpio_filter.h"
 #include "driver/dedic_gpio.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 
 #if CONFIG_IDF_TARGET_ESP32P4
 #define TEST_FILTER_GPIO 20
@@ -79,7 +79,7 @@ TEST_CASE("GPIO flex glitch filter life cycle", "[gpio_filter]")
  * @note Because the CPU instruction / CSR register is not compatible in all ESP chips,
  *       at the moment, this test only works for Espressif's RISC-V core (e.g. ESP32C6)
  */
-#if SOC_DEDICATED_GPIO_SUPPORTED
+#if SOC_HAS(DEDICATED_GPIO)
 
 #include "hal/dedic_gpio_cpu_ll.h"
 
@@ -182,5 +182,5 @@ TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]")
     vSemaphoreDelete(sem);
 }
 
-#endif // SOC_DEDICATED_GPIO_SUPPORTED
+#endif // SOC_HAS(DEDICATED_GPIO)
 #endif // SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0

components/hal/esp32c2/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32c3/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32c5/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32c6/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32c61/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32h2/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32p4/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,14 +9,17 @@
 #include <stdint.h>
 #include "riscv/csr.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*fast gpio*/
 #define CSR_GPIO_OEN_USER   0x803
 #define CSR_GPIO_IN_USER    0x804
 #define CSR_GPIO_OUT_USER   0x805
 
-#ifdef __cplusplus
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-extern "C" {
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
-#endif
 
 __attribute__((always_inline))
 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)

components/hal/esp32s2/include/hal/dedic_gpio_cpu_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,12 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
+{
+    // Dedicated GPIO output attribution is enabled automatically on the target
+}
+
 __attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {

components/hal/esp32s2/include/hal/dedic_gpio_ll.h

@@ -5,16 +5,18 @@
  */
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #include <stdint.h>
 #include <stdbool.h>
 #include "hal/misc.h"
 #include "soc/dedic_gpio_struct.h"
 #include "soc/system_reg.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DEDIC_GPIO_LL_ALLOW_REG_ACCESS  1 /*!< Allow access dedicated GPIO channel by register */
+
 static inline void _dedic_gpio_ll_enable_bus_clock(bool enable)
 {
     uint32_t reg_val = READ_PERI_REG(DPORT_CPU_PERI_CLK_EN_REG);

components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h

@@ -12,6 +12,12 @@
 extern "C" {
 #endif
 
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
+{
+    // Dedicated GPIO output attribution is enabled automatically on the target
+}
+
 __attribute__((always_inline))
 static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
 {

components/hal/esp32s3/include/hal/dedic_gpio_ll.h

@@ -5,14 +5,14 @@
  */
 #pragma once
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/system_struct.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 static inline void _dedic_gpio_ll_enable_bus_clock(bool enable)
 {
     SYSTEM.cpu_peri_clk_en.clk_en_dedicated_gpio = enable;

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -335,18 +335,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_I2C_NUM
     int
     default 1

components/soc/esp32c2/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -154,11 +154,6 @@
 // "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
 #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32-C2 has 1 I2C
 #define SOC_I2C_NUM                 (1U)

components/soc/esp32c2/include/soc/soc_caps_full.h

@@ -19,3 +19,7 @@
 
 /*--------------------------- Watch Dog ------------------------------------------*/
 #define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
+
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -431,18 +431,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_I2C_NUM
     int
     default 1

components/soc/esp32c3/include/soc/soc_caps.h

@@ -193,11 +193,6 @@
 // "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
 #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32-C3 has 1 I2C
 #define SOC_I2C_NUM                 (1U)

components/soc/esp32c3/include/soc/soc_caps_full.h

@@ -23,3 +23,7 @@
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              4  // Number of channels in each SDM instance
+
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -623,18 +623,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_SDM_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -257,12 +257,10 @@
 #define SOC_RTCIO_WAKE_SUPPORTED            1
 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED       1
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
+
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*------------------------- Analog Comparator CAPS ---------------------------*/

components/soc/esp32c5/include/soc/soc_caps_full.h

@@ -20,6 +20,10 @@
 /*--------------------------- Watch Dog ------------------------------------------*/
 #define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              4  // Number of channels in each SDM instance

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -559,18 +559,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_SDM_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -237,12 +237,10 @@
 #define SOC_RTCIO_WAKE_SUPPORTED            1
 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED       1
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
+
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- I2C CAPS ----------------------------------------*/

components/soc/esp32c6/include/soc/soc_caps_full.h

@@ -20,6 +20,10 @@
 /*--------------------------- Watch Dog ------------------------------------------*/
 #define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              4  // Number of channels in each SDM instance

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -503,18 +503,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_ANA_CMPR_NUM
     int
     default 1

components/soc/esp32c61/include/soc/soc_caps.h

@@ -161,6 +161,7 @@
 #define SOC_AHB_GDMA_SUPPORT_PSRAM 1
 #define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION   1
 
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
@@ -216,11 +217,6 @@
 #define SOC_RTCIO_WAKE_SUPPORTED            1
 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED       1
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 /*------------------------- Analog Comparator CAPS ---------------------------*/
 #define SOC_ANA_CMPR_NUM                       (1U)
 #define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE      (1)  // Support positive/negative/any cross interrupt

components/soc/esp32c61/include/soc/soc_caps_full.h

@@ -20,6 +20,10 @@
 /*--------------------------- Watch Dog ------------------------------------------*/
 #define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- ETM (Event Task Matrix) ----------------------------*/
 #define _SOC_CAPS_ETM_INST_NUM                    1  // Number of ETM instances
 #define _SOC_CAPS_ETM_CHANS_PER_INST              50 // Number of channels in each ETM instance

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -563,18 +563,6 @@ config SOC_RTCIO_HOLD_SUPPORTED
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_SDM_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -257,12 +257,10 @@
 #define SOC_RTCIO_PIN_COUNT         (8U)
 #define SOC_RTCIO_HOLD_SUPPORTED    (1)
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
+
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*------------------------- Analog Comparator CAPS ---------------------------*/

components/soc/esp32h2/include/soc/soc_caps_full.h

@@ -20,6 +20,10 @@
 /*--------------------------- Watch Dog ------------------------------------------*/
 #define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              4  // Number of channels in each SDM instance

components/soc/esp32h21/include/soc/Kconfig.soc_caps.in

@@ -399,18 +399,6 @@ config SOC_RTCIO_HOLD_SUPPORTED
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_ANA_CMPR_NUM
     int
     default 1

components/soc/esp32h21/include/soc/soc_caps.h

@@ -233,7 +233,10 @@
 // #define SOC_CLOCKOUT_HAS_SOURCE_GATE        (1)
 // #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
+
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
@@ -242,11 +245,6 @@
 #define SOC_RTCIO_PIN_COUNT         (7U)
 #define SOC_RTCIO_HOLD_SUPPORTED    (1)
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 /*------------------------- Analog Comparator CAPS ---------------------------*/
 #define SOC_ANA_CMPR_NUM                    (1U)
 #define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO   (1)

components/soc/esp32h4/include/soc/soc_caps.h

@@ -240,12 +240,10 @@
 #define SOC_RTCIO_WAKE_SUPPORTED            1
 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED       1
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
+
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- I2C CAPS ----------------------------------------*/

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -747,18 +747,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
-    bool
-    default y
-
 config SOC_SDM_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -289,12 +289,10 @@
 #define SOC_RTCIO_WAKE_SUPPORTED            1
 #define SOC_RTCIO_EDGE_WAKE_SUPPORTED       1
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
 #define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
+
+/*-------------------------- ETM CAPS -----------------------------------*/
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*------------------------- Analog Comparator CAPS ---------------------------*/

components/soc/esp32p4/include/soc/soc_caps_full.h

@@ -20,6 +20,10 @@
 /*--------------------------- Watch Dog ------------------------------------------*/
 #define _SOC_CAPS_WDT_MWDTS_PER_TIMG              1  // Number of main watchdog timers in each Timer Group
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              8  // Number of channels in each SDM instance

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -411,26 +411,10 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
-    bool
-    default y
-
 config SOC_DEDIC_GPIO_HAS_INTERRUPT
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
-    bool
-    default y
-
 config SOC_I2C_NUM
     int
     default 2

components/soc/esp32s2/include/soc/soc_caps.h

@@ -192,11 +192,7 @@
 #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 
 /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */
 #define SOC_DEDIC_GPIO_HAS_INTERRUPT    (1) /*!< Dedicated GPIO has its own interrupt source */
-#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE  (1) /*!< Dedicated GPIO output attribution is enabled automatically */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32-S2 has 2 I2C

components/soc/esp32s2/include/soc/soc_caps_full.h

@@ -29,3 +29,7 @@
 #define _SOC_CAPS_PCNT_UNITS_PER_INST             4  // Number of units in each PCNT instance
 #define _SOC_CAPS_PCNT_CHANS_PER_UNIT             2  // Number of channels in each PCNT unit
 #define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT       2  // Number of threshold points in each PCNT unit
+
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -495,18 +495,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
     bool
     default y
 
-config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
-    int
-    default 8
-
-config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
-    bool
-    default y
-
 config SOC_I2C_NUM
     int
     default 2

components/soc/esp32s3/include/soc/soc_caps.h

@@ -207,11 +207,6 @@
 // RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
 #define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
 
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE  (1) /*!< Dedicated GPIO output attribution is enabled automatically */
-
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32-S3 has 2 I2C
 #define SOC_I2C_NUM                 (2U)

components/soc/esp32s3/include/soc/soc_caps_full.h

@@ -29,3 +29,7 @@
 #define _SOC_CAPS_PCNT_UNITS_PER_INST             4  // Number of units in each PCNT instance
 #define _SOC_CAPS_PCNT_CHANS_PER_UNIT             2  // Number of channels in each PCNT unit
 #define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT       2  // Number of threshold points in each PCNT unit
+
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */

components/soc/include/soc/dedic_gpio_periph.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,25 +7,27 @@
 #pragma once
 
 #include <stdint.h>
-#include "soc/soc.h"
+#include "soc/interrupts.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
-#include "soc/periph_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#if SOC_DEDICATED_GPIO_SUPPORTED
+#if SOC_HAS(DEDICATED_GPIO)
+// helper macros to access module attributes
+#define SOC_DEDIC_GPIO_ATTR(_attr)    SOC_MODULE_ATTR(DEDIC_GPIO, _attr)
+
 typedef struct {
     const int irq;                // Interrupt resource (-1 means no interrupt supported)
     struct {
-        const int in_sig_per_channel[SOC_DEDIC_GPIO_IN_CHANNELS_NUM];
+        const int in_sig_per_channel[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)];
-        const int out_sig_per_channel[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM];
+        const int out_sig_per_channel[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)];
     } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix
 } dedic_gpio_signal_conn_t;
 
 extern const dedic_gpio_signal_conn_t dedic_gpio_periph_signals;
-#endif // SOC_DEDICATED_GPIO_SUPPORTED
+#endif // SOC_HAS(DEDICATED_GPIO)
 
 #ifdef __cplusplus
 }