From 24acdf23ee6af374067183c5c0493b289b1c3ae3 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 5 Jan 2022 16:14:03 +0800 Subject: [PATCH] soc: move peripheral base address into reg_base.h --- components/soc/CMakeLists.txt | 1 - .../soc/esp32/include/soc/periph_defs.h | 7 +- components/soc/esp32/include/soc/reg_base.h | 59 +++++++++++ components/soc/esp32/include/soc/soc.h | 77 ++------------ .../soc/esp32c3/include/soc/periph_defs.h | 18 +--- components/soc/esp32c3/include/soc/reg_base.h | 48 +++++++++ components/soc/esp32c3/include/soc/soc.h | 56 +--------- components/soc/esp32h2/include/soc/reg_base.h | 74 +++++++++++++ components/soc/esp32h2/include/soc/soc.h | 84 +-------------- .../soc/esp32s2/include/soc/periph_defs.h | 8 +- components/soc/esp32s2/include/soc/reg_base.h | 63 +++++++++++ components/soc/esp32s2/include/soc/soc.h | 87 ++------------- components/soc/esp32s3/include/soc/reg_base.h | 64 +++++++++++ components/soc/esp32s3/include/soc/soc.h | 100 ++---------------- components/soc/esp8684/include/soc/reg_base.h | 42 ++++++++ components/soc/esp8684/include/soc/soc.h | 49 +-------- components/soc/soc_include_legacy_warn.c | 5 - tools/ci/check_copyright_ignore.txt | 4 - 18 files changed, 394 insertions(+), 452 deletions(-) create mode 100644 components/soc/esp32/include/soc/reg_base.h create mode 100644 components/soc/esp32c3/include/soc/reg_base.h create mode 100644 components/soc/esp32h2/include/soc/reg_base.h create mode 100644 components/soc/esp32s2/include/soc/reg_base.h create mode 100644 components/soc/esp32s3/include/soc/reg_base.h create mode 100644 components/soc/esp8684/include/soc/reg_base.h delete mode 100644 components/soc/soc_include_legacy_warn.c diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 461f45fd40..cd7e118e51 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -1,5 +1,4 @@ idf_component_register(SRCS "lldesc.c" - "soc_include_legacy_warn.c" INCLUDE_DIRS include LDFRAGMENTS "linker.lf") diff --git a/components/soc/esp32/include/soc/periph_defs.h b/components/soc/esp32/include/soc/periph_defs.h index d6e7f8cf00..da81a70d59 100644 --- a/components/soc/esp32/include/soc/periph_defs.h +++ b/components/soc/esp32/include/soc/periph_defs.h @@ -1,11 +1,10 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_PERIPH_DEFS_H_ -#define _SOC_PERIPH_DEFS_H_ +#pragma once #ifdef __cplusplus extern "C" { @@ -53,5 +52,3 @@ typedef enum { #ifdef __cplusplus } #endif - -#endif /* _SOC_PERIPH_DEFS_H_ */ diff --git a/components/soc/esp32/include/soc/reg_base.h b/components/soc/esp32/include/soc/reg_base.h new file mode 100644 index 0000000000..7205809a95 --- /dev/null +++ b/components/soc/esp32/include/soc/reg_base.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_AES_BASE 0x3ff01000 +#define DR_REG_RSA_BASE 0x3ff02000 +#define DR_REG_SHA_BASE 0x3ff03000 +#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 +#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 +#define DR_REG_DPORT_END 0x3ff13FFC +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_FRC_TIMER_BASE 0x3ff47000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SENS_BASE 0x3ff48800 +#define DR_REG_RTC_I2C_BASE 0x3ff48C00 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_NRX_BASE 0x3ff5CC00 +#define DR_REG_BB_BASE 0x3ff5D000 +#define DR_REG_PWM0_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_SYSCON_BASE 0x3ff66000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_CAN_BASE 0x3ff6B000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index f9e3e87593..ffa1043176 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -1,16 +1,8 @@ -// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -19,7 +11,8 @@ #include "esp_assert.h" #endif -#include +#include "esp_bit_defs.h" +#include "reg_base.h" #define PRO_CPU_NUM (0) #define APP_CPU_NUM (1) @@ -27,62 +20,6 @@ #define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space - -#define DR_REG_DPORT_BASE 0x3ff00000 -#define DR_REG_AES_BASE 0x3ff01000 -#define DR_REG_RSA_BASE 0x3ff02000 -#define DR_REG_SHA_BASE 0x3ff03000 -#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 -#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 -#define DR_REG_DPORT_END 0x3ff13FFC -#define DR_REG_UART_BASE 0x3ff40000 -#define DR_REG_SPI1_BASE 0x3ff42000 -#define DR_REG_SPI0_BASE 0x3ff43000 -#define DR_REG_GPIO_BASE 0x3ff44000 -#define DR_REG_GPIO_SD_BASE 0x3ff44f00 -#define DR_REG_FE2_BASE 0x3ff45000 -#define DR_REG_FE_BASE 0x3ff46000 -#define DR_REG_FRC_TIMER_BASE 0x3ff47000 -#define DR_REG_RTCCNTL_BASE 0x3ff48000 -#define DR_REG_RTCIO_BASE 0x3ff48400 -#define DR_REG_SENS_BASE 0x3ff48800 -#define DR_REG_RTC_I2C_BASE 0x3ff48C00 -#define DR_REG_IO_MUX_BASE 0x3ff49000 -#define DR_REG_HINF_BASE 0x3ff4B000 -#define DR_REG_UHCI1_BASE 0x3ff4C000 -#define DR_REG_I2S_BASE 0x3ff4F000 -#define DR_REG_UART1_BASE 0x3ff50000 -#define DR_REG_BT_BASE 0x3ff51000 -#define DR_REG_I2C_EXT_BASE 0x3ff53000 -#define DR_REG_UHCI0_BASE 0x3ff54000 -#define DR_REG_SLCHOST_BASE 0x3ff55000 -#define DR_REG_RMT_BASE 0x3ff56000 -#define DR_REG_PCNT_BASE 0x3ff57000 -#define DR_REG_SLC_BASE 0x3ff58000 -#define DR_REG_LEDC_BASE 0x3ff59000 -#define DR_REG_EFUSE_BASE 0x3ff5A000 -#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 -#define DR_REG_NRX_BASE 0x3ff5CC00 -#define DR_REG_BB_BASE 0x3ff5D000 -#define DR_REG_PWM0_BASE 0x3ff5E000 -#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 -#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 -#define DR_REG_RTCMEM0_BASE 0x3ff61000 -#define DR_REG_RTCMEM1_BASE 0x3ff62000 -#define DR_REG_RTCMEM2_BASE 0x3ff63000 -#define DR_REG_SPI2_BASE 0x3ff64000 -#define DR_REG_SPI3_BASE 0x3ff65000 -#define DR_REG_SYSCON_BASE 0x3ff66000 -#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x3ff67000 -#define DR_REG_SDMMC_BASE 0x3ff68000 -#define DR_REG_EMAC_BASE 0x3ff69000 -#define DR_REG_CAN_BASE 0x3ff6B000 -#define DR_REG_PWM1_BASE 0x3ff6C000 -#define DR_REG_I2S1_BASE 0x3ff6D000 -#define DR_REG_UART2_BASE 0x3ff6E000 -#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE - //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32c3/include/soc/periph_defs.h b/components/soc/esp32c3/include/soc/periph_defs.h index 73c9935273..5fa1af8bf8 100644 --- a/components/soc/esp32c3/include/soc/periph_defs.h +++ b/components/soc/esp32c3/include/soc/periph_defs.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once diff --git a/components/soc/esp32c3/include/soc/reg_base.h b/components/soc/esp32c3/include/soc/reg_base.h new file mode 100644 index 0000000000..ba44a7b2de --- /dev/null +++ b/components/soc/esp32c3/include/soc/reg_base.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_GDMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_I2S0_BASE 0x6002D000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 +#define DR_REG_AES_XTS_BASE 0x600CC000 diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index bd2d552514..365d6b7452 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,54 +9,12 @@ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif -#define PRO_CPU_NUM (0) +#include "esp_bit_defs.h" +#include "reg_base.h" -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 -#define DR_REG_MMU_TABLE 0x600c5000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_GDMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_DPORT_END 0x600d3FFC -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_RTC_I2C_BASE 0x6000e000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x60008800 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_I2S0_BASE 0x6002D000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 -#define DR_REG_AES_XTS_BASE 0x600CC000 +#define PRO_CPU_NUM (0) #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) @@ -71,12 +29,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ //write value to register diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h new file mode 100644 index 0000000000..95ce211072 --- /dev/null +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 + +#define DR_REG_ITAG_TABLE 0x600c6000 +#define DR_REG_DTAG_TABLE 0x600c8000 +#define DR_REG_ECC_MULT_BASE 0x60039000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_GDMA_BASE 0x6003f000 + +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_GPIO_SD_BASE 0x60004f00 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_FRC_TIMER_BASE 0x60007000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_RTCIO_BASE 0x60008400 +#define DR_REG_SENS_BASE 0x60008800 +#define DR_REG_RTC_I2C_BASE 0x60008C00 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_HINF_BASE 0x6002B000 +#define DR_REG_UHCI1_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000F000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_BT_BASE 0x60011000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_SLCHOST_BASE 0x60019000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_SLC_BASE 0x6002D000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x6001A000 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_PWM_BASE 0x6001E000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 +#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SPI3_BASE 0x60025000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_I2C1_EXT_BASE 0x60027000 +#define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_PWM1_BASE 0x6002C000 +#define DR_REG_I2S1_BASE 0x6002D000 +#define DR_REG_UART2_BASE 0x6002E000 +#define DR_REG_PWM2_BASE 0x6002F000 +#define DR_REG_PWM3_BASE 0x60030000 +#define DR_REG_SPI4_BASE 0x60037000 +#define DR_REG_USB_WRAP_BASE 0x60039000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_LCD_CAM_BASE 0x60041000 +#define DR_REG_AES_XTS_BASE 0x600CC000 +#define DR_REG_USB_DEVICE_BASE 0x60043000 +#define DR_REG_CLKRST_BASE 0x6004B000 diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 69a3fa0b9f..970853d758 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,83 +9,13 @@ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 -#define DR_REG_MMU_TABLE 0x600c5000 - -#define DR_REG_ITAG_TABLE 0x600c6000 -#define DR_REG_DTAG_TABLE 0x600c8000 -#define DR_REG_ECC_MULT_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_GDMA_BASE 0x6003f000 - -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -// #define DR_REG_DPORT_END 0x600d3FFC -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_FRC_TIMER_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_HINF_BASE 0x6002B000 -#define DR_REG_UHCI1_BASE 0x6000C000 -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_BT_BASE 0x60011000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 -#define DR_REG_SLCHOST_BASE 0x60019000 -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_SLC_BASE 0x6002D000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x6001A000 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_PWM_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 -#define DR_REG_PWM2_BASE 0x6002F000 -#define DR_REG_PWM3_BASE 0x60030000 -#define DR_REG_SPI4_BASE 0x60037000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 -#define DR_REG_AES_XTS_BASE 0x600CC000 -#define DR_REG_USB_DEVICE_BASE 0x60043000 -#define DR_REG_CLKRST_BASE 0x6004B000 - - #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) @@ -99,12 +29,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ //write value to register diff --git a/components/soc/esp32s2/include/soc/periph_defs.h b/components/soc/esp32s2/include/soc/periph_defs.h index 56d19dd110..8d85bd0ab5 100644 --- a/components/soc/esp32s2/include/soc/periph_defs.h +++ b/components/soc/esp32s2/include/soc/periph_defs.h @@ -1,11 +1,10 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_PERIPH_DEFS_H_ -#define _SOC_PERIPH_DEFS_H_ +#pragma once #ifdef __cplusplus extern "C" { @@ -143,11 +142,8 @@ typedef enum { ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ - } periph_interrput_t; #ifdef __cplusplus } #endif - -#endif /* _SOC_PERIPH_DEFS_H_ */ diff --git a/components/soc/esp32s2/include/soc/reg_base.h b/components/soc/esp32s2/include/soc/reg_base.h new file mode 100644 index 0000000000..fae80bec8b --- /dev/null +++ b/components/soc/esp32s2/include/soc/reg_base.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x3f4c0000 +#define DR_REG_SENSITIVE_BASE 0x3f4c1000 +#define DR_REG_INTERRUPT_BASE 0x3f4c2000 +#define DR_REG_DMA_COPY_BASE 0x3f4c3000 +#define DR_REG_EXTMEM_BASE 0x61800000 +#define DR_REG_MMU_TABLE 0x61801000 +#define DR_REG_ITAG_TABLE 0x61802000 +#define DR_REG_DTAG_TABLE 0x61803000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 +#define DR_REG_INTRUSION_BASE 0x3f4d0000 +#define DR_REG_DPORT_END 0x3f4d3FFC +#define DR_REG_UART_BASE 0x3f400000 +#define DR_REG_SPI1_BASE 0x3f402000 +#define DR_REG_SPI0_BASE 0x3f403000 +#define DR_REG_GPIO_BASE 0x3f404000 +#define DR_REG_GPIO_SD_BASE 0x3f404f00 +#define DR_REG_FE2_BASE 0x3f405000 +#define DR_REG_FE_BASE 0x3f406000 +#define DR_REG_FRC_TIMER_BASE 0x3f407000 +#define DR_REG_RTCCNTL_BASE 0x3f408000 +#define DR_REG_RTCIO_BASE 0x3f408400 +#define DR_REG_SENS_BASE 0x3f408800 +#define DR_REG_RTC_I2C_BASE 0x3f408C00 +#define DR_REG_IO_MUX_BASE 0x3f409000 +#define DR_REG_HINF_BASE 0x3f40B000 +#define DR_REG_I2S_BASE 0x3f40F000 +#define DR_REG_UART1_BASE 0x3f410000 +#define DR_REG_I2C_EXT_BASE 0x3f413000 +#define DR_REG_UHCI0_BASE 0x3f414000 +#define DR_REG_SLCHOST_BASE 0x3f415000 +#define DR_REG_RMT_BASE 0x3f416000 +#define DR_REG_PCNT_BASE 0x3f417000 +#define DR_REG_SLC_BASE 0x3f418000 +#define DR_REG_LEDC_BASE 0x3f419000 +#define DR_REG_CP_BASE 0x3f4c3000 +#define DR_REG_EFUSE_BASE 0x3f41A000 +#define DR_REG_NRX_BASE 0x3f41CC00 +#define DR_REG_BB_BASE 0x3f41D000 +#define DR_REG_TIMERGROUP0_BASE 0x3f41F000 +#define DR_REG_TIMERGROUP1_BASE 0x3f420000 +#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 +#define DR_REG_SYSTIMER_BASE 0x3f423000 +#define DR_REG_SPI2_BASE 0x3f424000 +#define DR_REG_SPI3_BASE 0x3f425000 +#define DR_REG_SYSCON_BASE 0x3f426000 +#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3f427000 +#define DR_REG_SPI4_BASE 0x3f437000 +#define DR_REG_USB_WRAP_BASE 0x3f439000 +#define DR_REG_APB_SARADC_BASE 0x3f440000 +#define DR_REG_USB_BASE 0x60080000 diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index ae4cf0103a..d06c820cf5 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -1,88 +1,23 @@ -// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space -#define DR_REG_SYSTEM_BASE 0x3f4c0000 -#define DR_REG_SENSITIVE_BASE 0x3f4c1000 -#define DR_REG_INTERRUPT_BASE 0x3f4c2000 -#define DR_REG_DMA_COPY_BASE 0x3f4c3000 -#define DR_REG_EXTMEM_BASE 0x61800000 -#define DR_REG_MMU_TABLE 0x61801000 -#define DR_REG_ITAG_TABLE 0x61802000 -#define DR_REG_DTAG_TABLE 0x61803000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 -#define DR_REG_INTRUSION_BASE 0x3f4d0000 -#define DR_REG_DPORT_END 0x3f4d3FFC -#define DR_REG_UART_BASE 0x3f400000 -#define DR_REG_SPI1_BASE 0x3f402000 -#define DR_REG_SPI0_BASE 0x3f403000 -#define DR_REG_GPIO_BASE 0x3f404000 -#define DR_REG_GPIO_SD_BASE 0x3f404f00 -#define DR_REG_FE2_BASE 0x3f405000 -#define DR_REG_FE_BASE 0x3f406000 -#define DR_REG_FRC_TIMER_BASE 0x3f407000 -#define DR_REG_RTCCNTL_BASE 0x3f408000 -#define DR_REG_RTCIO_BASE 0x3f408400 -#define DR_REG_SENS_BASE 0x3f408800 -#define DR_REG_RTC_I2C_BASE 0x3f408C00 -#define DR_REG_IO_MUX_BASE 0x3f409000 -#define DR_REG_HINF_BASE 0x3f40B000 -#define DR_REG_I2S_BASE 0x3f40F000 -#define DR_REG_UART1_BASE 0x3f410000 -#define DR_REG_I2C_EXT_BASE 0x3f413000 -#define DR_REG_UHCI0_BASE 0x3f414000 -#define DR_REG_SLCHOST_BASE 0x3f415000 -#define DR_REG_RMT_BASE 0x3f416000 -#define DR_REG_PCNT_BASE 0x3f417000 -#define DR_REG_SLC_BASE 0x3f418000 -#define DR_REG_LEDC_BASE 0x3f419000 -#define DR_REG_CP_BASE 0x3f4c3000 -#define DR_REG_EFUSE_BASE 0x3f41A000 -#define DR_REG_NRX_BASE 0x3f41CC00 -#define DR_REG_BB_BASE 0x3f41D000 -#define DR_REG_TIMERGROUP0_BASE 0x3f41F000 -#define DR_REG_TIMERGROUP1_BASE 0x3f420000 -#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 -#define DR_REG_SYSTIMER_BASE 0x3f423000 -#define DR_REG_SPI2_BASE 0x3f424000 -#define DR_REG_SPI3_BASE 0x3f425000 -#define DR_REG_SYSCON_BASE 0x3f426000 -#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x3f427000 -#define DR_REG_SPI4_BASE 0x3f437000 -#define DR_REG_USB_WRAP_BASE 0x3f439000 -#define DR_REG_APB_SARADC_BASE 0x3f440000 -#define DR_REG_USB_BASE 0x60080000 - #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) @@ -100,12 +35,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/include/soc/reg_base.h new file mode 100644 index 0000000000..c0fcb9c2a0 --- /dev/null +++ b/components/soc/esp32s3/include/soc/reg_base.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_GPIO_SD_BASE 0x60004f00 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_EFUSE_BASE 0x60007000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_RTCIO_BASE 0x60008400 +#define DR_REG_SENS_BASE 0x60008800 +#define DR_REG_RTC_I2C_BASE 0x60008C00 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_HINF_BASE 0x6000B000 +#define DR_REG_UHCI1_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000F000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_BT_BASE 0x60011000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_SLCHOST_BASE 0x60015000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_PCNT_BASE 0x60017000 +#define DR_REG_SLC_BASE 0x60018000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_PWM0_BASE 0x6001E000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SPI3_BASE 0x60025000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x60027000 +#define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_PERI_BACKUP_BASE 0x6002A000 +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_PWM1_BASE 0x6002C000 +#define DR_REG_I2S1_BASE 0x6002D000 +#define DR_REG_UART2_BASE 0x6002E000 +#define DR_REG_USB_DEVICE_BASE 0x60038000 +#define DR_REG_USB_WRAP_BASE 0x60039000 +#define DR_REG_AES_BASE 0x6003A000 +#define DR_REG_SHA_BASE 0x6003B000 +#define DR_REG_RSA_BASE 0x6003C000 +#define DR_REG_HMAC_BASE 0x6003E000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 +#define DR_REG_GDMA_BASE 0x6003F000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_LCD_CAM_BASE 0x60041000 +#define DR_REG_SYSTEM_BASE 0x600C0000 +#define DR_REG_SENSITIVE_BASE 0x600C1000 +#define DR_REG_INTERRUPT_BASE 0x600C2000 +#define DR_REG_EXTMEM_BASE 0x600C4000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 +#define DR_REG_WORLD_CNTL_BASE 0x600D0000 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 001f5fe853..69b524a1a0 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -1,114 +1,30 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) #define APP_CPU_NUM (1) #define PRO_CPUID (0xcdcd) #define APP_CPUID (0xabab) -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 - -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 - -#define DR_REG_EFUSE_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 - -#define DR_REG_HINF_BASE 0x6000B000 -#define DR_REG_UHCI1_BASE 0x6000C000 - -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 - -#define DR_REG_BT_BASE 0x60011000 - -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 - -#define DR_REG_SLCHOST_BASE 0x60015000 - -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_PCNT_BASE 0x60017000 - -#define DR_REG_SLC_BASE 0x60018000 - -#define DR_REG_LEDC_BASE 0x60019000 - -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 - -#define DR_REG_PWM0_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 - -#define DR_REG_PERI_BACKUP_BASE 0x6002A000 - -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 - -#define DR_REG_USB_DEVICE_BASE 0x60038000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003A000 -#define DR_REG_SHA_BASE 0x6003B000 -#define DR_REG_RSA_BASE 0x6003C000 -#define DR_REG_HMAC_BASE 0x6003E000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 -#define DR_REG_GDMA_BASE 0x6003F000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 - -#define DR_REG_SYSTEM_BASE 0x600C0000 -#define DR_REG_SENSITIVE_BASE 0x600C1000 -#define DR_REG_INTERRUPT_BASE 0x600C2000 - /* Cache configuration */ -#define DR_REG_EXTMEM_BASE 0x600C4000 #define DR_REG_MMU_TABLE 0x600C5000 #define DR_REG_ITAG_TABLE 0x600C6000 #define DR_REG_DTAG_TABLE 0x600C8000 - #define DR_REG_EXT_MEM_ENC 0x600CC000 - -#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 -#define DR_REG_WORLD_CNTL_BASE 0x600D0000 #define DR_REG_DPORT_END 0x600D3FFC diff --git a/components/soc/esp8684/include/soc/reg_base.h b/components/soc/esp8684/include/soc/reg_base.h new file mode 100644 index 0000000000..dede05420a --- /dev/null +++ b/components/soc/esp8684/include/soc/reg_base.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_GDMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_RTC_I2C_BASE 0x6000e000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x60008800 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_SYSTIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_WDEVLE_BASE 0x60045000 +#define DR_REG_ETM_BIT_BASE 0x6004B000 +#define DR_REG_BLE_TIMER_BASE 0x6004B800 +#define DR_REG_BLE_SEC_BASE 0x6004C000 +#define DR_REG_COEX_BIT_BASE 0x6004C400 +#define DR_REG_I2C_MST_BASE 0x6004E800 diff --git a/components/soc/esp8684/include/soc/soc.h b/components/soc/esp8684/include/soc/soc.h index 1a28265110..b67e82aa71 100644 --- a/components/soc/esp8684/include/soc/soc.h +++ b/components/soc/esp8684/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,47 +9,12 @@ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" -#include "esp_bit_defs.h" #endif +#include "esp_bit_defs.h" +#include "reg_base.h" + #define PRO_CPU_NUM (0) -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG -#define DR_REG_MMU_TABLE 0x600c5000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_GDMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_DPORT_END 0x600d3FFC -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_RTC_I2C_BASE 0x6000e000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x60008800 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_WDEVLE_BASE 0x60045000 -#define DR_REG_ETM_BIT_BASE 0x6004B000 -#define DR_REG_BLE_TIMER_BASE 0x6004B800 -#define DR_REG_BLE_SEC_BASE 0x6004C000 -#define DR_REG_COEX_BIT_BASE 0x6004C400 -#define DR_REG_I2C_MST_BASE 0x6004E800 #define DR_REG_RTC_BLE_TIMER_BASE( i ) ( \ ( (i) == 0 ) ? ( 0x6004E000 ) : \ @@ -71,12 +36,6 @@ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) -#ifndef __ASSEMBLER__ -#define BIT(nr) (1UL << (nr)) -#else -#define BIT(nr) (1 << (nr)) -#endif - #ifndef __ASSEMBLER__ //write value to register diff --git a/components/soc/soc_include_legacy_warn.c b/components/soc/soc_include_legacy_warn.c deleted file mode 100644 index 375ba11654..0000000000 --- a/components/soc/soc_include_legacy_warn.c +++ /dev/null @@ -1,5 +0,0 @@ -#include "sdkconfig.h" - -#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS -#warning Legacy including is enabled. This will be deprecated in the future. You can disable this option in the menuconfig. If there are some including errors, please try to include: "soc/soc.h", "soc/soc_memory_layout.h", "driver/gpio.h", or "esp_sleep.h". -#endif diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 6bd985ace1..db5b6e4de5 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1626,7 +1626,6 @@ components/soc/esp32/include/soc/sens_reg.h components/soc/esp32/include/soc/sens_struct.h components/soc/esp32/include/soc/slc_reg.h components/soc/esp32/include/soc/slc_struct.h -components/soc/esp32/include/soc/soc.h components/soc/esp32/include/soc/soc_pins.h components/soc/esp32/include/soc/soc_ulp.h components/soc/esp32/include/soc/spi_pins.h @@ -1689,7 +1688,6 @@ components/soc/esp32c3/include/soc/interrupt_reg.h components/soc/esp32c3/include/soc/ledc_reg.h components/soc/esp32c3/include/soc/mmu.h components/soc/esp32c3/include/soc/nrx_reg.h -components/soc/esp32c3/include/soc/periph_defs.h components/soc/esp32c3/include/soc/reset_reasons.h components/soc/esp32c3/include/soc/rmt_reg.h components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -1839,7 +1837,6 @@ components/soc/esp32s2/include/soc/sdmmc_pins.h components/soc/esp32s2/include/soc/sens_reg.h components/soc/esp32s2/include/soc/sens_struct.h components/soc/esp32s2/include/soc/sensitive_reg.h -components/soc/esp32s2/include/soc/soc.h components/soc/esp32s2/include/soc/soc_pins.h components/soc/esp32s2/include/soc/soc_ulp.h components/soc/esp32s2/include/soc/spi_mem_reg.h @@ -1945,7 +1942,6 @@ components/soc/esp32s3/include/soc/sdmmc_struct.h components/soc/esp32s3/include/soc/sens_reg.h components/soc/esp32s3/include/soc/sensitive_reg.h components/soc/esp32s3/include/soc/sensitive_struct.h -components/soc/esp32s3/include/soc/soc.h components/soc/esp32s3/include/soc/soc_ulp.h components/soc/esp32s3/include/soc/spi_mem_reg.h components/soc/esp32s3/include/soc/spi_mem_struct.h