feat(esp32c5mp): add system related components

components/bootloader_support/src/bootloader_clock_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -66,7 +66,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
         }
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
         // TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
         // Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
         clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
@@ -81,14 +81,6 @@ __attribute__((weak)) void bootloader_clock_configure(void)
         rtc_clk_init(clk_cfg);
     }
 
-#if CONFIG_IDF_TARGET_ESP32C5
-    /* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
-       need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
-       and we need to check flash freq before restart as well */
-    clk_ll_mspi_fast_set_divider(1);
-    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
-#endif
-
     /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
      * it here. Usually it needs some time to start up, so we amortize at least
      * part of the start up time by enabling 32k XTAL early.

components/bootloader_support/src/bootloader_console.c

@@ -25,6 +25,9 @@
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_caps.h"
+#if CONFIG_IDF_TARGET_ESP32C5
+#include "soc/pcr_reg.h"
+#endif
 
 #ifdef CONFIG_ESP_CONSOLE_NONE
 void bootloader_console_init(void)
@@ -85,6 +88,13 @@ void bootloader_console_init(void)
 #if ESP_ROM_UART_CLK_IS_XTAL
     clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
 #endif
+#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#if CONFIG_IDF_ENV_FPGA
+    clock_hz = CONFIG_XTAL_FREQ * MHZ;
+#else
+    clock_hz = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_CLK_XTAL_FREQ) * MHZ;
+#endif  // CONFIG_IDF_ENV_FPGA
+#endif  // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 }
 #endif // CONFIG_ESP_CONSOLE_UART

components/bootloader_support/src/bootloader_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/bootloader_support/src/bootloader_mem.c

@@ -16,7 +16,7 @@
 #include "hal/apm_hal.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5!
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-8615 Remove the workaround when APM supported on C5!
 #include "soc/hp_apm_reg.h"
 #include "soc/lp_apm_reg.h"
 #include "soc/lp_apm0_reg.h"
@@ -36,7 +36,7 @@ void bootloader_init_mem(void)
     apm_hal_apm_ctrl_filter_enable_all(false);
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-8615 Remove the workaround when APM supported on C5!
+#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-8615 Remove the workaround when APM supported on C5!
     // disable apm filter
     REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
     REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
@@ -45,6 +45,6 @@ void bootloader_init_mem(void)
 
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
     // protect memory region
-    esp_cpu_configure_region_protection();
+    esp_cpu_configure_region_protection();  // TODO: [ESP32C5] IDF-8833 PSRAM support write
 #endif
 }

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -12,12 +12,12 @@
 
 void bootloader_random_enable(void)
 {
-    // TODO: [ESP32C5] IDF-8626
+// TODO: [ESP32C5] IDF-8626, IDF-9197
     ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
 }
 
 void bootloader_random_disable(void)
 {
-    // TODO: [ESP32C5] IDF-8626
+// TODO: [ESP32C5] IDF-8626, IDF-9197
     ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
 }

components/bootloader_support/src/bootloader_utility.c

@@ -645,6 +645,12 @@ static void load_image(const esp_image_metadata_t *image_data)
 #endif // CONFIG_SECURE_BOOT_FLASH_ENC_KEYS_BURN_TOGETHER
 
     if (!flash_encryption_enabled) {
+#if CONFIG_IDF_TARGET_ESP32C5
+        // TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
+        REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+        REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+        REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+#endif
         err = esp_flash_encrypt_contents();
         if (err != ESP_OK) {
             ESP_LOGE(TAG, "Encryption flash contents failed (%d)", err);

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -13,6 +13,7 @@
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_spiflash.h"
+#include "soc/soc_caps.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/io_mux_reg.h"
 #include "soc/assist_debug_reg.h"
@@ -41,7 +42,9 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
+#if SOC_MODEM_CLOCK_SUPPORTED
 #include "modem/modem_lpcon_reg.h"
+#endif
 
 static const char *TAG = "boot.esp32c5";
 
@@ -85,12 +88,15 @@ static void bootloader_super_wdt_auto_feed(void)
 static inline void bootloader_hardware_init(void)
 {
     /* Enable analog i2c master clock */
+#if SOC_MODEM_CLOCK_SUPPORTED
     SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
     SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+#endif
 }
 
 static inline void bootloader_ana_reset_config(void)
 {
+// TODO: IDF-9197
     // TODO: [ESP32C5] IDF-8650
     //Enable super WDT reset.
     // bootloader_ana_super_wdt_reset_config(true);

components/bootloader_support/src/flash_encrypt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */