diff --git a/components/esp_driver_i2s/CMakeLists.txt b/components/esp_driver_i2s/CMakeLists.txt index 2498fa6126..f8bcfb91dc 100644 --- a/components/esp_driver_i2s/CMakeLists.txt +++ b/components/esp_driver_i2s/CMakeLists.txt @@ -37,4 +37,5 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${include} PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm + LDFRAGMENTS linker.lf ) diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index 48b88f2f1e..e4178cad53 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -575,7 +575,7 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz) } #if SOC_GDMA_SUPPORTED -static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +static bool i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data; BaseType_t need_yield1 = 0; @@ -606,7 +606,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e return need_yield1 | need_yield2 | user_need_yield; } -static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +static bool i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) { i2s_chan_handle_t handle = (i2s_chan_handle_t)user_data; BaseType_t need_yield1 = 0; @@ -653,7 +653,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e #else -static void IRAM_ATTR i2s_dma_rx_callback(void *arg) +static void i2s_dma_rx_callback(void *arg) { BaseType_t need_yield1 = 0; BaseType_t need_yield2 = 0; @@ -691,7 +691,7 @@ static void IRAM_ATTR i2s_dma_rx_callback(void *arg) } } -static void IRAM_ATTR i2s_dma_tx_callback(void *arg) +static void i2s_dma_tx_callback(void *arg) { BaseType_t need_yield1 = 0; BaseType_t need_yield2 = 0; @@ -1485,7 +1485,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle) } #endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT -#if SOC_I2S_SUPPORTS_ETM_SYNC +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC uint32_t i2s_sync_get_fifo_sync_diff_count(i2s_chan_handle_t tx_handle) { return i2s_ll_tx_get_fifo_sync_diff_count(tx_handle->controller->hal.dev); diff --git a/components/esp_driver_i2s/i2s_etm.c b/components/esp_driver_i2s/i2s_etm.c index 725775dd31..cdecd3e2b0 100644 --- a/components/esp_driver_i2s/i2s_etm.c +++ b/components/esp_driver_i2s/i2s_etm.c @@ -84,9 +84,9 @@ esp_err_t i2s_new_etm_task(i2s_chan_handle_t handle, const i2s_etm_task_config_t { ESP_RETURN_ON_FALSE(handle && config && out_task, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(config->task_type < I2S_ETM_TASK_MAX, ESP_ERR_INVALID_ARG, TAG, "invalid task type"); -#if SOC_I2S_SUPPORTS_ETM_SYNC - ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_CHECK || handle->dir == I2S_DIR_TX, - ESP_ERR_NOT_SUPPORTED, TAG, "rx is not supported"); +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC + ESP_RETURN_ON_FALSE(config->task_type != I2S_ETM_TASK_SYNC_FIFO || handle->dir == I2S_DIR_TX, + ESP_ERR_NOT_SUPPORTED, TAG, "rx does not support sync check"); #endif i2s_etm_task_t *task = heap_caps_calloc(1, sizeof(i2s_etm_task_t), ETM_MEM_ALLOC_CAPS); diff --git a/components/esp_driver_i2s/include/esp_private/i2s_sync.h b/components/esp_driver_i2s/include/esp_private/i2s_sync.h index 68660ad7ab..f066bf0ea8 100644 --- a/components/esp_driver_i2s/include/esp_private/i2s_sync.h +++ b/components/esp_driver_i2s/include/esp_private/i2s_sync.h @@ -21,6 +21,7 @@ #include #include "driver/i2s_types.h" +#include "esp_err.h" #ifdef __cplusplus extern "C" { @@ -31,7 +32,7 @@ extern "C" { /** * @brief Get the counter number of BCLK ticks * @note The BCLK tick count reflects the real data that have sent on line - * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered + * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered * * @param[in] tx_handle The I2S tx channel handle * @return @@ -44,7 +45,7 @@ uint32_t i2s_sync_get_bclk_count(i2s_chan_handle_t tx_handle); * @note The FIFO count reflects how many slots have processed * Normally, fifo_cnt = slot_bit_width * bclk_cnt * If fifo_cnt < slot_bit_width * bclk_cnt, that means some data are still stuck in the I2S controller - * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_CHECK` is triggered + * @note It will be reset automatically when `I2S_ETM_TASK_SYNC_FIFO` is triggered * * @param[in] tx_handle The I2S tx channel handle * @return @@ -68,7 +69,7 @@ void i2s_sync_reset_fifo_count(i2s_chan_handle_t tx_handle); #endif // SOC_I2S_SUPPORTS_TX_SYNC_CNT -#if SOC_I2S_SUPPORTS_ETM_SYNC +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC /** * @brief I2S hardware FIFO synchronization supplement mode * @note When the FIFO sync difference count is out of threshold, the hardware will supplement data automatically diff --git a/components/esp_driver_i2s/linker.lf b/components/esp_driver_i2s/linker.lf index 9bb2330d24..ed2ae42edf 100644 --- a/components/esp_driver_i2s/linker.lf +++ b/components/esp_driver_i2s/linker.lf @@ -1,13 +1,16 @@ [mapping:i2s_driver] archive: libesp_driver_i2s.a entries: + if I2S_ISR_IRAM_SAFE = y: + i2s_common: i2s_dma_rx_callback (noflash) + i2s_common: i2s_dma_tx_callback (noflash) if I2S_CTRL_FUNC_IN_IRAM = y: if SOC_I2S_SUPPORTS_TX_SYNC_CNT = y: i2s_common: i2s_sync_get_bclk_count (noflash) i2s_common: i2s_sync_get_fifo_count (noflash) i2s_common: i2s_sync_reset_bclk_count (noflash) i2s_common: i2s_sync_reset_fifo_count (noflash) - if SOC_I2S_SUPPORTS_ETM_SYNC = y: + if SOC_I2S_SUPPORTS_TX_FIFO_SYNC = y: i2s_common: i2s_sync_get_fifo_sync_diff_count (noflash) i2s_common: i2s_sync_reset_fifo_sync_diff_count (noflash) i2s_common: i2s_sync_enable_hw_fifo_sync (noflash) diff --git a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe index 0128347673..8351f4355c 100644 --- a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe +++ b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.iram_safe @@ -1,5 +1,6 @@ CONFIG_COMPILER_DUMP_RTL_FILES=y CONFIG_I2S_ISR_IRAM_SAFE=y +CONFIG_I2S_CTRL_FUNC_IN_IRAM=y CONFIG_COMPILER_OPTIMIZATION_NONE=y # silent the error check, as the error string are stored in rodata, causing RTL check failure CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y diff --git a/components/hal/esp32h4/include/hal/i2s_ll.h b/components/hal/esp32h4/include/hal/i2s_ll.h index 9197e0d2b4..d1a97be56a 100644 --- a/components/hal/esp32h4/include/hal/i2s_ll.h +++ b/components/hal/esp32h4/include/hal/i2s_ll.h @@ -60,12 +60,12 @@ extern "C" { [I2S_DIR_RX - 1] = { \ [I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \ [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \ - [I2S_ETM_TASK_SYNC_CHECK] = -1, \ + [I2S_ETM_TASK_SYNC_FIFO] = -1, \ }, \ [I2S_DIR_TX - 1] = { \ [I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \ [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_TX, \ - [I2S_ETM_TASK_SYNC_CHECK] = I2S0_TASK_SYNC_CHECK, \ + [I2S_ETM_TASK_SYNC_FIFO] = I2S0_TASK_SYNC_CHECK, \ }}}[i2s_port][(chan_dir) - 1][task] #define I2S_LL_ETM_MAX_THRESH_NUM (0x3FFFUL) @@ -1344,7 +1344,7 @@ static inline void i2s_ll_tx_set_hw_fifo_sync_static_suppl_data(i2s_dev_t *hw, u * @brief Set the TX ETM synchronization ideal count * * @param hw Peripheral I2S hardware instance address. - * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_CHECK triggered. + * @param ideal_cnt The ideal FIFO count when I2S_ETM_TASK_SYNC_FIFO triggered. */ __attribute__((always_inline)) static inline void i2s_ll_tx_set_etm_sync_ideal_cnt(i2s_dev_t *hw, uint32_t ideal_cnt) diff --git a/components/hal/include/hal/i2s_types.h b/components/hal/include/hal/i2s_types.h index 90c0d7a213..8709b3f062 100644 --- a/components/hal/include/hal/i2s_types.h +++ b/components/hal/include/hal/i2s_types.h @@ -233,8 +233,8 @@ typedef enum { typedef enum { I2S_ETM_TASK_START, /*!< Start the I2S channel */ I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */ -#if SOC_I2S_SUPPORTS_ETM_SYNC - I2S_ETM_TASK_SYNC_CHECK, /*!< Check the I2S TX channel sync status */ +#if SOC_I2S_SUPPORTS_TX_FIFO_SYNC + I2S_ETM_TASK_SYNC_FIFO, /*!< Check the I2S TX channel sync status */ #endif I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */ } i2s_etm_task_type_t; diff --git a/components/soc/esp32/register/soc/i2s_reg.h b/components/soc/esp32/register/soc/i2s_reg.h index 12dc09a677..1af259d79d 100644 --- a/components/soc/esp32/register/soc/i2s_reg.h +++ b/components/soc/esp32/register/soc/i2s_reg.h @@ -1,15 +1,17 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ +#pragma once #include "soc/soc.h" -#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) +#ifdef __cplusplus +extern "C" { +#endif +#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000)) #define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) /* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */ @@ -1511,7 +1513,6 @@ #define I2S_I2SDATE_V 0xFFFFFFFF #define I2S_I2SDATE_S 0 - - - -#endif /*_SOC_I2S_REG_H_ */ +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index da0dbb8a84..82cdcb061b 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI diff --git a/components/soc/esp32c3/register/soc/i2s_reg.h b/components/soc/esp32c3/register/soc/i2s_reg.h index 7412fe1a13..576392baef 100644 --- a/components/soc/esp32c3/register/soc/i2s_reg.h +++ b/components/soc/esp32c3/register/soc/i2s_reg.h @@ -1,16 +1,18 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ +#pragma once +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc/soc.h" + +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C3 + #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ @@ -1037,7 +1039,3 @@ T12_5[2:0]).*/ #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index 3413beeeba..a5b205e9bb 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -18,7 +18,6 @@ #define REG_UHCI_BASE(i) (DR_REG_UHCI_BASE) // only one UHCI on C5 #define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 #define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5 diff --git a/components/soc/esp32c5/register/soc/i2s_reg.h b/components/soc/esp32c5/register/soc/i2s_reg.h index 62199e9d66..0c54601fdb 100644 --- a/components/soc/esp32c5/register/soc/i2s_reg.h +++ b/components/soc/esp32c5/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C5 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index af3ed6c919..f38495b1c0 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6 diff --git a/components/soc/esp32c6/register/soc/i2s_reg.h b/components/soc/esp32c6/register/soc/i2s_reg.h index 4f259c1131..d7dd6b6ab6 100644 --- a/components/soc/esp32c6/register/soc/i2s_reg.h +++ b/components/soc/esp32c6/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index 838fd98a68..fa4b36f2fd 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -19,7 +19,6 @@ #define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 #define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61 diff --git a/components/soc/esp32c61/register/soc/i2s_reg.h b/components/soc/esp32c61/register/soc/i2s_reg.h index 9c999162fa..934ac15e72 100644 --- a/components/soc/esp32c61/register/soc/i2s_reg.h +++ b/components/soc/esp32c61/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index df2b8f2a01..d7f5cddd5e 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -20,7 +20,6 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI diff --git a/components/soc/esp32h2/register/soc/i2s_reg.h b/components/soc/esp32h2/register/soc/i2s_reg.h index 95b982407e..e1e4477442 100644 --- a/components/soc/esp32h2/register/soc/i2s_reg.h +++ b/components/soc/esp32h2/register/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H2 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32h4/etm_periph.c b/components/soc/esp32h4/etm_periph.c index d54078bd9f..82e5ac6ffb 100644 --- a/components/soc/esp32h4/etm_periph.c +++ b/components/soc/esp32h4/etm_periph.c @@ -7,4 +7,38 @@ #include "soc/etm_periph.h" #include "soc/soc_etm_reg.h" -// TODO: [ESP32H4] IDF-12356 Support sleep retention +/** + * ETM Registers to be saved during sleep retention + * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG +*/ +#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1) + +static const regdma_entries_config_t etm_regdma_entries[] = { + // backup stage: save the status of enabled channels + // restore stage: store the enabled channels + [0] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00), + SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + [1] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01), + SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [2] = { + .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02), + SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0), + .owner = ENTRY(0) | ENTRY(2), + }, +}; + +const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = { + [0] = { + .module = SLEEP_RETENTION_MODULE_ETM0, + .regdma_entry_array = etm_regdma_entries, + .array_size = ARRAY_SIZE(etm_regdma_entries) + }, +}; diff --git a/components/soc/esp32h4/i2s_periph.c b/components/soc/esp32h4/i2s_periph.c index b3b72dc12d..2e3b4d82b4 100644 --- a/components/soc/esp32h4/i2s_periph.c +++ b/components/soc/esp32h4/i2s_periph.c @@ -32,3 +32,46 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { .irq = ETS_I2S_INTR_SOURCE, } }; + +/** + * I2S Registers to be saved during sleep retention + * - I2S_INT_ENA_REG + * - I2S_RX_CONF_REG + * - I2S_TX_CONF_REG + * - I2S_RX_CONF1_REG + * - I2S_TX_CONF1_REG + * - I2S_TX_PCM2PDM_CONF_REG + * - I2S_TX_PCM2PDM_CONF1_REG + * - I2S_RX_TDM_CTRL_REG + * - I2S_TX_TDM_CTRL_REG + * - I2S_RXEOF_NUM_REG + * - I2S_ETM_CONF_REG + * - I2S_IDEAL_CNT_REG + * - I2S_SYNC_SW_THRES_REG + * - I2S_SYNC_HW_THRES_REG + * - I2S_HW_SYNC_CONF_REG + * - I2S_HW_SYNC_DATA_REG +*/ + +#define I2S_RETENTION_REGS_CNT 16 +#define I2S_RETENTION_REGS_BASE(i) (I2S_INT_ENA_REG(i)) +static const uint32_t i2s_regs_map[4] = {0xf191b079, 0x0, 0x0, 0x0}; +#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) { \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \ + REGDMA_I2S_LINK(0x00), \ + I2S_RETENTION_REGS_BASE(i2s_port), \ + I2S_RETENTION_REGS_BASE(i2s_port), \ + I2S_RETENTION_REGS_CNT, 0, 0, \ + i2s_regs_map[0], i2s_regs_map[1], \ + i2s_regs_map[2], i2s_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) }, \ +}; +static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0); + +const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = { + [0] = { + .retention_module = SLEEP_RETENTION_MODULE_I2S0, + .entry_array = i2s0_regs_retention, + .array_size = ARRAY_SIZE(i2s0_regs_retention) + }, +}; diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 720f4839f0..63bcc7ae6c 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -227,6 +227,10 @@ config SOC_ETM_CHANNELS_PER_GROUP int default 50 +config SOC_ETM_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GPIO_PORT int default 1 @@ -335,10 +339,6 @@ config SOC_I2S_SUPPORTS_ETM bool default y -config SOC_I2S_SUPPORTS_ETM_SYNC - bool - default y - config SOC_I2S_SUPPORTS_XTAL bool default y @@ -375,6 +375,10 @@ config SOC_I2S_SUPPORTS_TX_SYNC_CNT bool default y +config SOC_I2S_SUPPORTS_TX_FIFO_SYNC + bool + default y + config SOC_I2S_PDM_MAX_TX_LINES int default 2 @@ -391,6 +395,10 @@ config SOC_I2S_TDM_FULL_DATA_WIDTH bool default y +config SOC_I2S_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_LEDC_CHANNEL_NUM int default 6 @@ -503,10 +511,6 @@ config SOC_LP_TIMER_BIT_WIDTH_HI int default 16 -config SOC_SYSTIMER_SUPPORT_ETM - bool - default y - config SOC_TIMER_SUPPORT_ETM bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 4ec809c29f..1004c6da4c 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -198,7 +198,7 @@ /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group -// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12356 Support sleep retention +#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-H4 has 1 GPIO peripheral @@ -272,7 +272,6 @@ #define SOC_I2S_NUM (1U) #define SOC_I2S_HW_VERSION_2 (1) #define SOC_I2S_SUPPORTS_ETM (1) -#define SOC_I2S_SUPPORTS_ETM_SYNC (1) #define SOC_I2S_SUPPORTS_XTAL (1) #define SOC_I2S_SUPPORTS_PLL_F96M (1) #define SOC_I2S_SUPPORTS_PLL_F64M (1) @@ -282,13 +281,13 @@ #define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter #define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data #define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1) +#define SOC_I2S_SUPPORTS_TX_FIFO_SYNC (1) #define SOC_I2S_PDM_MAX_TX_LINES (2) #define SOC_I2S_PDM_MAX_RX_LINES (1U) #define SOC_I2S_SUPPORTS_TDM (1) #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ -// TODO: [ESP32H4] IDF-12386 -// #define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */ +#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */ /*-------------------------- LEDC CAPS ---------------------------------------*/ // #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) diff --git a/components/soc/esp32h4/register/soc/i2s_reg.h b/components/soc/esp32h4/register/soc/i2s_reg.h index dfbf964bd6..009cc75002 100644 --- a/components/soc/esp32h4/register/soc/i2s_reg.h +++ b/components/soc/esp32h4/register/soc/i2s_reg.h @@ -11,10 +11,12 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S0_BASE) // only one I2S on H4 + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ -#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc) /** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt status bit for the i2s_rx_done_int interrupt */ @@ -54,7 +56,7 @@ extern "C" { /** I2S_INT_ST_REG register * I2S interrupt status register. */ -#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10) /** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status bit for the i2s_rx_done_int interrupt */ @@ -94,7 +96,7 @@ extern "C" { /** I2S_INT_ENA_REG register * I2S interrupt enable register. */ -#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14) /** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the i2s_rx_done_int interrupt */ @@ -134,7 +136,7 @@ extern "C" { /** I2S_INT_CLR_REG register * I2S interrupt clear register. */ -#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18) /** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the i2s_rx_done_int interrupt */ @@ -174,7 +176,7 @@ extern "C" { /** I2S_RX_CONF_REG register * I2S RX configure register */ -#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20) +#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20) /** I2S_RX_RESET : WT; bitpos: [0]; default: 0; * Set this bit to reset receiver */ @@ -326,7 +328,7 @@ extern "C" { /** I2S_TX_CONF_REG register * I2S TX configure register */ -#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24) +#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24) /** I2S_TX_RESET : WT; bitpos: [0]; default: 0; * Set this bit to reset transmitter */ @@ -502,7 +504,7 @@ extern "C" { /** I2S_RX_CONF1_REG register * I2S RX configure register 1 */ -#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28) +#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28) /** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * * T_bck @@ -539,7 +541,7 @@ extern "C" { /** I2S_TX_CONF1_REG register * I2S TX configure register 1 */ -#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c) +#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c) /** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0; * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * * T_bck @@ -576,7 +578,7 @@ extern "C" { /** I2S_TX_PCM2PDM_CONF_REG register * I2S TX PCM2PDM configuration register */ -#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x44) +#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x44) /** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2; * I2S TX PDM OSR2 value */ @@ -658,7 +660,7 @@ extern "C" { /** I2S_TX_PCM2PDM_CONF1_REG register * I2S TX PCM2PDM configuration register */ -#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x48) +#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x48) /** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960; * I2S TX PDM Fp */ @@ -693,7 +695,7 @@ extern "C" { /** I2S_RX_TDM_CTRL_REG register * I2S TX TDM mode control register */ -#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50) +#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50) /** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just * input 0 in this channel. @@ -833,7 +835,7 @@ extern "C" { /** I2S_TX_TDM_CTRL_REG register * I2S TX TDM mode control register */ -#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54) +#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54) /** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1; * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output * 0 in this channel. @@ -982,7 +984,7 @@ extern "C" { /** I2S_RX_TIMING_REG register * I2S RX timing control register */ -#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58) +#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58) /** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0; * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: * delay by neg edge. 3: not used. @@ -1051,7 +1053,7 @@ extern "C" { /** I2S_TX_TIMING_REG register * I2S TX timing control register */ -#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c) +#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c) /** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0; * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: * delay by neg edge. 3: not used. @@ -1104,7 +1106,7 @@ extern "C" { /** I2S_LC_HUNG_CONF_REG register * I2S HUNG configure register. */ -#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60) +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60) /** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered * when fifo hung counter is equal to this value @@ -1132,7 +1134,7 @@ extern "C" { /** I2S_RXEOF_NUM_REG register * I2S RX data number control register. */ -#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64) +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64) /** I2S_RX_EOF_NUM : R/W; bitpos: [15:0]; default: 64; * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0]) * . It will trigger in_suc_eof interrupt in the configured DMA RX channel. @@ -1145,7 +1147,7 @@ extern "C" { /** I2S_CONF_SIGLE_DATA_REG register * I2S signal data register */ -#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68) +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68) /** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0; * The configured constant channel data to be sent out. */ @@ -1157,7 +1159,7 @@ extern "C" { /** I2S_STATE_REG register * I2S TX status register */ -#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c) +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c) /** I2S_TX_IDLE : RO; bitpos: [0]; default: 1; * 1: i2s_tx is idle state. 0: i2s_tx is working. */ @@ -1169,7 +1171,7 @@ extern "C" { /** I2S_ETM_CONF_REG register * I2S ETM configure register */ -#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70) +#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70) /** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [13:0]; default: 64; * I2S ETM send x words event. When sending word number of * reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event. @@ -1190,7 +1192,7 @@ extern "C" { /** I2S_IDEAL_CNT_REG register * I2S sync counter register */ -#define I2S_IDEAL_CNT_REG (DR_REG_I2S_BASE + 0x74) +#define I2S_IDEAL_CNT_REG(i) (REG_I2S_BASE(i) + 0x74) /** I2S_TX_IDEAL_CNT : R/W; bitpos: [30:0]; default: 0; * tx fifo counter ideal value. */ @@ -1202,7 +1204,7 @@ extern "C" { /** I2S_FIFO_CNT_REG register * I2S sync counter register */ -#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x78) +#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x78) /** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0; * tx fifo counter value. */ @@ -1221,7 +1223,7 @@ extern "C" { /** I2S_BCK_CNT_REG register * I2S sync counter register */ -#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x7c) +#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x7c) /** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0; * tx bck counter value. */ @@ -1240,7 +1242,7 @@ extern "C" { /** I2S_CNT_DIFF_REG register * I2S sync counter register */ -#define I2S_CNT_DIFF_REG (DR_REG_I2S_BASE + 0x80) +#define I2S_CNT_DIFF_REG(i) (REG_I2S_BASE(i) + 0x80) /** I2S_TX_CNT_DIFF : RO; bitpos: [30:0]; default: 0; * tx bck counter value. */ @@ -1259,7 +1261,7 @@ extern "C" { /** I2S_SYNC_SW_THRES_REG register * I2S sync counter register */ -#define I2S_SYNC_SW_THRES_REG (DR_REG_I2S_BASE + 0x84) +#define I2S_SYNC_SW_THRES_REG(i) (REG_I2S_BASE(i) + 0x84) /** I2S_TX_CNT_DIFF_SW_THRES : R/W; bitpos: [30:0]; default: 0; * tx fifo counter difference software threshold value, when difference larger than * this threshold, interrupt will occur and hardware sync will not be executed. @@ -1272,7 +1274,7 @@ extern "C" { /** I2S_SYNC_HW_THRES_REG register * I2S sync counter register */ -#define I2S_SYNC_HW_THRES_REG (DR_REG_I2S_BASE + 0x88) +#define I2S_SYNC_HW_THRES_REG(i) (REG_I2S_BASE(i) + 0x88) /** I2S_TX_CNT_DIFF_HW_THRES : R/W; bitpos: [30:0]; default: 0; * tx fifo counter difference hardware threshold value, which means that only when * difference larger than this threshold will hardware start hardware sync. @@ -1285,7 +1287,7 @@ extern "C" { /** I2S_HW_SYNC_CONF_REG register * I2S TX hardware sync function configuration register */ -#define I2S_HW_SYNC_CONF_REG (DR_REG_I2S_BASE + 0x8c) +#define I2S_HW_SYNC_CONF_REG(i) (REG_I2S_BASE(i) + 0x8c) /** I2S_TX_HW_SYNC_EN : R/W; bitpos: [0]; default: 0; * Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable */ @@ -1305,7 +1307,7 @@ extern "C" { /** I2S_HW_SYNC_DATA_REG register * I2S TX hardware sync function configuration register */ -#define I2S_HW_SYNC_DATA_REG (DR_REG_I2S_BASE + 0x90) +#define I2S_HW_SYNC_DATA_REG(i) (REG_I2S_BASE(i) + 0x90) /** I2S_TX_HW_SYNC_SUPPL_DATA : R/W; bitpos: [31:0]; default: 0; * Configure the i2s tx hardware sync supplementation data when * I2S_TX_HW_SYNC_SUPPL_MODE is 1. @@ -1318,7 +1320,7 @@ extern "C" { /** I2S_CLK_GATE_REG register * Clock gate register */ -#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0xf8) +#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0xf8) /** I2S_CLK_EN : R/W; bitpos: [0]; default: 0; * set this bit to enable clock gate */ @@ -1330,7 +1332,7 @@ extern "C" { /** I2S_DATE_REG register * Version control register */ -#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc) +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0xfc) /** I2S_DATE : R/W; bitpos: [27:0]; default: 37818432; * I2S version control register */ diff --git a/components/soc/esp32h4/register/soc/soc_etm_reg.h b/components/soc/esp32h4/register/soc/soc_etm_reg.h index 30e259bef9..ac8a7ed36a 100644 --- a/components/soc/esp32h4/register/soc/soc_etm_reg.h +++ b/components/soc/esp32h4/register/soc/soc_etm_reg.h @@ -14,7 +14,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD0_REG register * Channel enable status register */ -#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_BASE + 0x0) +#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) /** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; * Represents ch0 enable status. * 0: Disable @@ -307,7 +307,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD0_SET_REG register * Channel enable set register */ -#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_BASE + 0x4) +#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) /** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; * Configures whether or not to enable ch0. * 0: Invalid, No effect @@ -600,7 +600,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD0_CLR_REG register * Channel enable clear register */ -#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_BASE + 0x8) +#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) /** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ch0 enable. * 0: Invalid, No effect @@ -893,7 +893,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD1_REG register * Channel enable status register */ -#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_BASE + 0xc) +#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) /** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; * Represents ch32 enable status. * 0: Disable @@ -1060,7 +1060,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD1_SET_REG register * Channel enable set register */ -#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_BASE + 0x10) +#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) /** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; * Configures whether or not to enable ch32. * 0: Invalid, No effect @@ -1227,7 +1227,7 @@ extern "C" { /** SOC_ETM_CH_ENA_AD1_CLR_REG register * Channel enable clear register */ -#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_BASE + 0x14) +#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) /** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ch32 enable. * 0: Invalid, No effect @@ -1394,7 +1394,7 @@ extern "C" { /** SOC_ETM_CH0_EVT_ID_REG register * Channel0 event id register */ -#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_BASE + 0x18) +#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) /** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch0_evt_id */ @@ -1406,7 +1406,7 @@ extern "C" { /** SOC_ETM_CH0_TASK_ID_REG register * Channel0 task id register */ -#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_BASE + 0x1c) +#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) /** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch0_task_id */ @@ -1418,7 +1418,7 @@ extern "C" { /** SOC_ETM_CH1_EVT_ID_REG register * Channel1 event id register */ -#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_BASE + 0x20) +#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) /** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch1_evt_id */ @@ -1430,7 +1430,7 @@ extern "C" { /** SOC_ETM_CH1_TASK_ID_REG register * Channel1 task id register */ -#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_BASE + 0x24) +#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) /** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch1_task_id */ @@ -1442,7 +1442,7 @@ extern "C" { /** SOC_ETM_CH2_EVT_ID_REG register * Channel2 event id register */ -#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_BASE + 0x28) +#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) /** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch2_evt_id */ @@ -1454,7 +1454,7 @@ extern "C" { /** SOC_ETM_CH2_TASK_ID_REG register * Channel2 task id register */ -#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_BASE + 0x2c) +#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) /** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch2_task_id */ @@ -1466,7 +1466,7 @@ extern "C" { /** SOC_ETM_CH3_EVT_ID_REG register * Channel3 event id register */ -#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_BASE + 0x30) +#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) /** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch3_evt_id */ @@ -1478,7 +1478,7 @@ extern "C" { /** SOC_ETM_CH3_TASK_ID_REG register * Channel3 task id register */ -#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_BASE + 0x34) +#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) /** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch3_task_id */ @@ -1490,7 +1490,7 @@ extern "C" { /** SOC_ETM_CH4_EVT_ID_REG register * Channel4 event id register */ -#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_BASE + 0x38) +#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) /** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch4_evt_id */ @@ -1502,7 +1502,7 @@ extern "C" { /** SOC_ETM_CH4_TASK_ID_REG register * Channel4 task id register */ -#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_BASE + 0x3c) +#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) /** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch4_task_id */ @@ -1514,7 +1514,7 @@ extern "C" { /** SOC_ETM_CH5_EVT_ID_REG register * Channel5 event id register */ -#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_BASE + 0x40) +#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) /** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch5_evt_id */ @@ -1526,7 +1526,7 @@ extern "C" { /** SOC_ETM_CH5_TASK_ID_REG register * Channel5 task id register */ -#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_BASE + 0x44) +#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) /** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch5_task_id */ @@ -1538,7 +1538,7 @@ extern "C" { /** SOC_ETM_CH6_EVT_ID_REG register * Channel6 event id register */ -#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_BASE + 0x48) +#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) /** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch6_evt_id */ @@ -1550,7 +1550,7 @@ extern "C" { /** SOC_ETM_CH6_TASK_ID_REG register * Channel6 task id register */ -#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_BASE + 0x4c) +#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) /** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch6_task_id */ @@ -1562,7 +1562,7 @@ extern "C" { /** SOC_ETM_CH7_EVT_ID_REG register * Channel7 event id register */ -#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_BASE + 0x50) +#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) /** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch7_evt_id */ @@ -1574,7 +1574,7 @@ extern "C" { /** SOC_ETM_CH7_TASK_ID_REG register * Channel7 task id register */ -#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_BASE + 0x54) +#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) /** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch7_task_id */ @@ -1586,7 +1586,7 @@ extern "C" { /** SOC_ETM_CH8_EVT_ID_REG register * Channel8 event id register */ -#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_BASE + 0x58) +#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) /** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch8_evt_id */ @@ -1598,7 +1598,7 @@ extern "C" { /** SOC_ETM_CH8_TASK_ID_REG register * Channel8 task id register */ -#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_BASE + 0x5c) +#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) /** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch8_task_id */ @@ -1610,7 +1610,7 @@ extern "C" { /** SOC_ETM_CH9_EVT_ID_REG register * Channel9 event id register */ -#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_BASE + 0x60) +#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) /** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch9_evt_id */ @@ -1622,7 +1622,7 @@ extern "C" { /** SOC_ETM_CH9_TASK_ID_REG register * Channel9 task id register */ -#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_BASE + 0x64) +#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) /** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch9_task_id */ @@ -1634,7 +1634,7 @@ extern "C" { /** SOC_ETM_CH10_EVT_ID_REG register * Channel10 event id register */ -#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_BASE + 0x68) +#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) /** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch10_evt_id */ @@ -1646,7 +1646,7 @@ extern "C" { /** SOC_ETM_CH10_TASK_ID_REG register * Channel10 task id register */ -#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_BASE + 0x6c) +#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) /** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch10_task_id */ @@ -1658,7 +1658,7 @@ extern "C" { /** SOC_ETM_CH11_EVT_ID_REG register * Channel11 event id register */ -#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_BASE + 0x70) +#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) /** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch11_evt_id */ @@ -1670,7 +1670,7 @@ extern "C" { /** SOC_ETM_CH11_TASK_ID_REG register * Channel11 task id register */ -#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_BASE + 0x74) +#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) /** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch11_task_id */ @@ -1682,7 +1682,7 @@ extern "C" { /** SOC_ETM_CH12_EVT_ID_REG register * Channel12 event id register */ -#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_BASE + 0x78) +#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) /** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch12_evt_id */ @@ -1694,7 +1694,7 @@ extern "C" { /** SOC_ETM_CH12_TASK_ID_REG register * Channel12 task id register */ -#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_BASE + 0x7c) +#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) /** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch12_task_id */ @@ -1706,7 +1706,7 @@ extern "C" { /** SOC_ETM_CH13_EVT_ID_REG register * Channel13 event id register */ -#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_BASE + 0x80) +#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) /** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch13_evt_id */ @@ -1718,7 +1718,7 @@ extern "C" { /** SOC_ETM_CH13_TASK_ID_REG register * Channel13 task id register */ -#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_BASE + 0x84) +#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) /** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch13_task_id */ @@ -1730,7 +1730,7 @@ extern "C" { /** SOC_ETM_CH14_EVT_ID_REG register * Channel14 event id register */ -#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_BASE + 0x88) +#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) /** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch14_evt_id */ @@ -1742,7 +1742,7 @@ extern "C" { /** SOC_ETM_CH14_TASK_ID_REG register * Channel14 task id register */ -#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_BASE + 0x8c) +#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) /** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch14_task_id */ @@ -1754,7 +1754,7 @@ extern "C" { /** SOC_ETM_CH15_EVT_ID_REG register * Channel15 event id register */ -#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_BASE + 0x90) +#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) /** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch15_evt_id */ @@ -1766,7 +1766,7 @@ extern "C" { /** SOC_ETM_CH15_TASK_ID_REG register * Channel15 task id register */ -#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_BASE + 0x94) +#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) /** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch15_task_id */ @@ -1778,7 +1778,7 @@ extern "C" { /** SOC_ETM_CH16_EVT_ID_REG register * Channel16 event id register */ -#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_BASE + 0x98) +#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) /** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch16_evt_id */ @@ -1790,7 +1790,7 @@ extern "C" { /** SOC_ETM_CH16_TASK_ID_REG register * Channel16 task id register */ -#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_BASE + 0x9c) +#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) /** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch16_task_id */ @@ -1802,7 +1802,7 @@ extern "C" { /** SOC_ETM_CH17_EVT_ID_REG register * Channel17 event id register */ -#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_BASE + 0xa0) +#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) /** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch17_evt_id */ @@ -1814,7 +1814,7 @@ extern "C" { /** SOC_ETM_CH17_TASK_ID_REG register * Channel17 task id register */ -#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_BASE + 0xa4) +#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) /** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch17_task_id */ @@ -1826,7 +1826,7 @@ extern "C" { /** SOC_ETM_CH18_EVT_ID_REG register * Channel18 event id register */ -#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_BASE + 0xa8) +#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) /** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch18_evt_id */ @@ -1838,7 +1838,7 @@ extern "C" { /** SOC_ETM_CH18_TASK_ID_REG register * Channel18 task id register */ -#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_BASE + 0xac) +#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) /** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch18_task_id */ @@ -1850,7 +1850,7 @@ extern "C" { /** SOC_ETM_CH19_EVT_ID_REG register * Channel19 event id register */ -#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_BASE + 0xb0) +#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) /** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch19_evt_id */ @@ -1862,7 +1862,7 @@ extern "C" { /** SOC_ETM_CH19_TASK_ID_REG register * Channel19 task id register */ -#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_BASE + 0xb4) +#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) /** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch19_task_id */ @@ -1874,7 +1874,7 @@ extern "C" { /** SOC_ETM_CH20_EVT_ID_REG register * Channel20 event id register */ -#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_BASE + 0xb8) +#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) /** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch20_evt_id */ @@ -1886,7 +1886,7 @@ extern "C" { /** SOC_ETM_CH20_TASK_ID_REG register * Channel20 task id register */ -#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_BASE + 0xbc) +#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) /** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch20_task_id */ @@ -1898,7 +1898,7 @@ extern "C" { /** SOC_ETM_CH21_EVT_ID_REG register * Channel21 event id register */ -#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_BASE + 0xc0) +#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) /** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch21_evt_id */ @@ -1910,7 +1910,7 @@ extern "C" { /** SOC_ETM_CH21_TASK_ID_REG register * Channel21 task id register */ -#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_BASE + 0xc4) +#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) /** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch21_task_id */ @@ -1922,7 +1922,7 @@ extern "C" { /** SOC_ETM_CH22_EVT_ID_REG register * Channel22 event id register */ -#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_BASE + 0xc8) +#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) /** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch22_evt_id */ @@ -1934,7 +1934,7 @@ extern "C" { /** SOC_ETM_CH22_TASK_ID_REG register * Channel22 task id register */ -#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_BASE + 0xcc) +#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) /** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch22_task_id */ @@ -1946,7 +1946,7 @@ extern "C" { /** SOC_ETM_CH23_EVT_ID_REG register * Channel23 event id register */ -#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_BASE + 0xd0) +#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) /** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch23_evt_id */ @@ -1958,7 +1958,7 @@ extern "C" { /** SOC_ETM_CH23_TASK_ID_REG register * Channel23 task id register */ -#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_BASE + 0xd4) +#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) /** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch23_task_id */ @@ -1970,7 +1970,7 @@ extern "C" { /** SOC_ETM_CH24_EVT_ID_REG register * Channel24 event id register */ -#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_BASE + 0xd8) +#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) /** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch24_evt_id */ @@ -1982,7 +1982,7 @@ extern "C" { /** SOC_ETM_CH24_TASK_ID_REG register * Channel24 task id register */ -#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_BASE + 0xdc) +#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) /** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch24_task_id */ @@ -1994,7 +1994,7 @@ extern "C" { /** SOC_ETM_CH25_EVT_ID_REG register * Channel25 event id register */ -#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_BASE + 0xe0) +#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) /** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch25_evt_id */ @@ -2006,7 +2006,7 @@ extern "C" { /** SOC_ETM_CH25_TASK_ID_REG register * Channel25 task id register */ -#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_BASE + 0xe4) +#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) /** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch25_task_id */ @@ -2018,7 +2018,7 @@ extern "C" { /** SOC_ETM_CH26_EVT_ID_REG register * Channel26 event id register */ -#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_BASE + 0xe8) +#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) /** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch26_evt_id */ @@ -2030,7 +2030,7 @@ extern "C" { /** SOC_ETM_CH26_TASK_ID_REG register * Channel26 task id register */ -#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_BASE + 0xec) +#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) /** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch26_task_id */ @@ -2042,7 +2042,7 @@ extern "C" { /** SOC_ETM_CH27_EVT_ID_REG register * Channel27 event id register */ -#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_BASE + 0xf0) +#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) /** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch27_evt_id */ @@ -2054,7 +2054,7 @@ extern "C" { /** SOC_ETM_CH27_TASK_ID_REG register * Channel27 task id register */ -#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_BASE + 0xf4) +#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) /** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch27_task_id */ @@ -2066,7 +2066,7 @@ extern "C" { /** SOC_ETM_CH28_EVT_ID_REG register * Channel28 event id register */ -#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_BASE + 0xf8) +#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) /** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch28_evt_id */ @@ -2078,7 +2078,7 @@ extern "C" { /** SOC_ETM_CH28_TASK_ID_REG register * Channel28 task id register */ -#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_BASE + 0xfc) +#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) /** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch28_task_id */ @@ -2090,7 +2090,7 @@ extern "C" { /** SOC_ETM_CH29_EVT_ID_REG register * Channel29 event id register */ -#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_BASE + 0x100) +#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) /** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch29_evt_id */ @@ -2102,7 +2102,7 @@ extern "C" { /** SOC_ETM_CH29_TASK_ID_REG register * Channel29 task id register */ -#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_BASE + 0x104) +#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) /** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch29_task_id */ @@ -2114,7 +2114,7 @@ extern "C" { /** SOC_ETM_CH30_EVT_ID_REG register * Channel30 event id register */ -#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_BASE + 0x108) +#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) /** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch30_evt_id */ @@ -2126,7 +2126,7 @@ extern "C" { /** SOC_ETM_CH30_TASK_ID_REG register * Channel30 task id register */ -#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_BASE + 0x10c) +#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) /** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch30_task_id */ @@ -2138,7 +2138,7 @@ extern "C" { /** SOC_ETM_CH31_EVT_ID_REG register * Channel31 event id register */ -#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_BASE + 0x110) +#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) /** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch31_evt_id */ @@ -2150,7 +2150,7 @@ extern "C" { /** SOC_ETM_CH31_TASK_ID_REG register * Channel31 task id register */ -#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_BASE + 0x114) +#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) /** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch31_task_id */ @@ -2162,7 +2162,7 @@ extern "C" { /** SOC_ETM_CH32_EVT_ID_REG register * Channel32 event id register */ -#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_BASE + 0x118) +#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) /** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch32_evt_id */ @@ -2174,7 +2174,7 @@ extern "C" { /** SOC_ETM_CH32_TASK_ID_REG register * Channel32 task id register */ -#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_BASE + 0x11c) +#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) /** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch32_task_id */ @@ -2186,7 +2186,7 @@ extern "C" { /** SOC_ETM_CH33_EVT_ID_REG register * Channel33 event id register */ -#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_BASE + 0x120) +#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) /** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch33_evt_id */ @@ -2198,7 +2198,7 @@ extern "C" { /** SOC_ETM_CH33_TASK_ID_REG register * Channel33 task id register */ -#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_BASE + 0x124) +#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) /** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch33_task_id */ @@ -2210,7 +2210,7 @@ extern "C" { /** SOC_ETM_CH34_EVT_ID_REG register * Channel34 event id register */ -#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_BASE + 0x128) +#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) /** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch34_evt_id */ @@ -2222,7 +2222,7 @@ extern "C" { /** SOC_ETM_CH34_TASK_ID_REG register * Channel34 task id register */ -#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_BASE + 0x12c) +#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) /** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch34_task_id */ @@ -2234,7 +2234,7 @@ extern "C" { /** SOC_ETM_CH35_EVT_ID_REG register * Channel35 event id register */ -#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_BASE + 0x130) +#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) /** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch35_evt_id */ @@ -2246,7 +2246,7 @@ extern "C" { /** SOC_ETM_CH35_TASK_ID_REG register * Channel35 task id register */ -#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_BASE + 0x134) +#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) /** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch35_task_id */ @@ -2258,7 +2258,7 @@ extern "C" { /** SOC_ETM_CH36_EVT_ID_REG register * Channel36 event id register */ -#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_BASE + 0x138) +#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) /** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch36_evt_id */ @@ -2270,7 +2270,7 @@ extern "C" { /** SOC_ETM_CH36_TASK_ID_REG register * Channel36 task id register */ -#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_BASE + 0x13c) +#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) /** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch36_task_id */ @@ -2282,7 +2282,7 @@ extern "C" { /** SOC_ETM_CH37_EVT_ID_REG register * Channel37 event id register */ -#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_BASE + 0x140) +#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) /** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch37_evt_id */ @@ -2294,7 +2294,7 @@ extern "C" { /** SOC_ETM_CH37_TASK_ID_REG register * Channel37 task id register */ -#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_BASE + 0x144) +#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) /** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch37_task_id */ @@ -2306,7 +2306,7 @@ extern "C" { /** SOC_ETM_CH38_EVT_ID_REG register * Channel38 event id register */ -#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_BASE + 0x148) +#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) /** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch38_evt_id */ @@ -2318,7 +2318,7 @@ extern "C" { /** SOC_ETM_CH38_TASK_ID_REG register * Channel38 task id register */ -#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_BASE + 0x14c) +#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) /** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch38_task_id */ @@ -2330,7 +2330,7 @@ extern "C" { /** SOC_ETM_CH39_EVT_ID_REG register * Channel39 event id register */ -#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_BASE + 0x150) +#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) /** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch39_evt_id */ @@ -2342,7 +2342,7 @@ extern "C" { /** SOC_ETM_CH39_TASK_ID_REG register * Channel39 task id register */ -#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_BASE + 0x154) +#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) /** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch39_task_id */ @@ -2354,7 +2354,7 @@ extern "C" { /** SOC_ETM_CH40_EVT_ID_REG register * Channel40 event id register */ -#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_BASE + 0x158) +#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) /** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch40_evt_id */ @@ -2366,7 +2366,7 @@ extern "C" { /** SOC_ETM_CH40_TASK_ID_REG register * Channel40 task id register */ -#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_BASE + 0x15c) +#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) /** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch40_task_id */ @@ -2378,7 +2378,7 @@ extern "C" { /** SOC_ETM_CH41_EVT_ID_REG register * Channel41 event id register */ -#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_BASE + 0x160) +#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) /** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch41_evt_id */ @@ -2390,7 +2390,7 @@ extern "C" { /** SOC_ETM_CH41_TASK_ID_REG register * Channel41 task id register */ -#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_BASE + 0x164) +#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) /** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch41_task_id */ @@ -2402,7 +2402,7 @@ extern "C" { /** SOC_ETM_CH42_EVT_ID_REG register * Channel42 event id register */ -#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_BASE + 0x168) +#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) /** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch42_evt_id */ @@ -2414,7 +2414,7 @@ extern "C" { /** SOC_ETM_CH42_TASK_ID_REG register * Channel42 task id register */ -#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_BASE + 0x16c) +#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) /** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch42_task_id */ @@ -2426,7 +2426,7 @@ extern "C" { /** SOC_ETM_CH43_EVT_ID_REG register * Channel43 event id register */ -#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_BASE + 0x170) +#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) /** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch43_evt_id */ @@ -2438,7 +2438,7 @@ extern "C" { /** SOC_ETM_CH43_TASK_ID_REG register * Channel43 task id register */ -#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_BASE + 0x174) +#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) /** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch43_task_id */ @@ -2450,7 +2450,7 @@ extern "C" { /** SOC_ETM_CH44_EVT_ID_REG register * Channel44 event id register */ -#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_BASE + 0x178) +#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) /** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch44_evt_id */ @@ -2462,7 +2462,7 @@ extern "C" { /** SOC_ETM_CH44_TASK_ID_REG register * Channel44 task id register */ -#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_BASE + 0x17c) +#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) /** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch44_task_id */ @@ -2474,7 +2474,7 @@ extern "C" { /** SOC_ETM_CH45_EVT_ID_REG register * Channel45 event id register */ -#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_BASE + 0x180) +#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) /** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch45_evt_id */ @@ -2486,7 +2486,7 @@ extern "C" { /** SOC_ETM_CH45_TASK_ID_REG register * Channel45 task id register */ -#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_BASE + 0x184) +#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) /** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch45_task_id */ @@ -2498,7 +2498,7 @@ extern "C" { /** SOC_ETM_CH46_EVT_ID_REG register * Channel46 event id register */ -#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_BASE + 0x188) +#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) /** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch46_evt_id */ @@ -2510,7 +2510,7 @@ extern "C" { /** SOC_ETM_CH46_TASK_ID_REG register * Channel46 task id register */ -#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_BASE + 0x18c) +#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) /** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch46_task_id */ @@ -2522,7 +2522,7 @@ extern "C" { /** SOC_ETM_CH47_EVT_ID_REG register * Channel47 event id register */ -#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_BASE + 0x190) +#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) /** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch47_evt_id */ @@ -2534,7 +2534,7 @@ extern "C" { /** SOC_ETM_CH47_TASK_ID_REG register * Channel47 task id register */ -#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_BASE + 0x194) +#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) /** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch47_task_id */ @@ -2546,7 +2546,7 @@ extern "C" { /** SOC_ETM_CH48_EVT_ID_REG register * Channel48 event id register */ -#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_BASE + 0x198) +#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) /** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch48_evt_id */ @@ -2558,7 +2558,7 @@ extern "C" { /** SOC_ETM_CH48_TASK_ID_REG register * Channel48 task id register */ -#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_BASE + 0x19c) +#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) /** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch48_task_id */ @@ -2570,7 +2570,7 @@ extern "C" { /** SOC_ETM_CH49_EVT_ID_REG register * Channel49 event id register */ -#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_BASE + 0x1a0) +#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) /** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch49_evt_id */ @@ -2582,7 +2582,7 @@ extern "C" { /** SOC_ETM_CH49_TASK_ID_REG register * Channel49 task id register */ -#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_BASE + 0x1a4) +#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) /** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; * Configures ch49_task_id */ @@ -2594,7 +2594,7 @@ extern "C" { /** SOC_ETM_EVT_ST0_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_BASE + 0x1a8) +#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GPIO_evt_ch0_rise_edge trigger status. * 0: Not triggered @@ -2887,7 +2887,7 @@ extern "C" { /** SOC_ETM_EVT_ST0_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_BASE + 0x1ac) +#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. * 0: Invalid, No effect @@ -3180,7 +3180,7 @@ extern "C" { /** SOC_ETM_EVT_ST1_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_BASE + 0x1b0) +#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_evt_duty_chng_end_ch6 trigger status. * 0: Not triggered @@ -3473,7 +3473,7 @@ extern "C" { /** SOC_ETM_EVT_ST1_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_BASE + 0x1b4) +#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status. * 0: Invalid, No effect @@ -3766,7 +3766,7 @@ extern "C" { /** SOC_ETM_EVT_ST2_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_BASE + 0x1b8) +#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) /** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM0_evt_op0_tea trigger status. * 0: Not triggered @@ -4059,7 +4059,7 @@ extern "C" { /** SOC_ETM_EVT_ST2_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_BASE + 0x1bc) +#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) /** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear MCPWM0_evt_op0_tea trigger status. * 0: Invalid, No effect @@ -4352,7 +4352,7 @@ extern "C" { /** SOC_ETM_EVT_ST3_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_BASE + 0x1c0) +#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) /** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM1_evt_timer2_tez trigger status. * 0: Not triggered @@ -4645,7 +4645,7 @@ extern "C" { /** SOC_ETM_EVT_ST3_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_BASE + 0x1c4) +#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) /** SOC_ETM_MCPWM1_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status. * 0: Invalid, No effect @@ -4938,7 +4938,7 @@ extern "C" { /** SOC_ETM_EVT_ST4_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_BASE + 0x1c8) +#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8) /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents ADC_evt_eq_above_thresh0 trigger status. * 0: Not triggered @@ -5231,7 +5231,7 @@ extern "C" { /** SOC_ETM_EVT_ST4_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_BASE + 0x1cc) +#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. * 0: Invalid, No effect @@ -5524,7 +5524,7 @@ extern "C" { /** SOC_ETM_EVT_ST5_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST5_REG (DR_REG_SOC_BASE + 0x1d0) +#define SOC_ETM_EVT_ST5_REG (DR_REG_SOC_ETM_BASE + 0x1d0) /** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GDMA_evt_in_suc_eof_ch1 trigger status. * 0: Not triggered @@ -5817,7 +5817,7 @@ extern "C" { /** SOC_ETM_EVT_ST5_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST5_CLR_REG (DR_REG_SOC_BASE + 0x1d4) +#define SOC_ETM_EVT_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) /** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status. * 0: Invalid, No effect @@ -6110,7 +6110,7 @@ extern "C" { /** SOC_ETM_EVT_ST6_REG register * Events trigger status register */ -#define SOC_ETM_EVT_ST6_REG (DR_REG_SOC_BASE + 0x1d8) +#define SOC_ETM_EVT_ST6_REG (DR_REG_SOC_ETM_BASE + 0x1d8) /** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH3_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GDMA_evt_out_fifo_empty_ch3 trigger status. * 0: Not triggered @@ -6277,7 +6277,7 @@ extern "C" { /** SOC_ETM_EVT_ST6_CLR_REG register * Events trigger status clear register */ -#define SOC_ETM_EVT_ST6_CLR_REG (DR_REG_SOC_BASE + 0x1dc) +#define SOC_ETM_EVT_ST6_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) /** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH3_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GDMA_evt_out_fifo_empty_ch3 trigger status. * 0: Invalid, No effect @@ -6444,7 +6444,7 @@ extern "C" { /** SOC_ETM_TASK_ST0_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_BASE + 0x1e0) +#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1e0) /** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents GPIO_task_ch0_set trigger status. * 0: Not triggered @@ -6737,7 +6737,7 @@ extern "C" { /** SOC_ETM_TASK_ST0_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_BASE + 0x1e4) +#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) /** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear GPIO_task_ch0_set trigger status. * 0: Invalid, No effect @@ -7030,7 +7030,7 @@ extern "C" { /** SOC_ETM_TASK_ST1_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_BASE + 0x1e8) +#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1e8) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_task_duty_scale_update_ch4 trigger status. * 0: Not triggered @@ -7323,7 +7323,7 @@ extern "C" { /** SOC_ETM_TASK_ST1_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_BASE + 0x1ec) +#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. * 0: Invalid, No effect @@ -7616,7 +7616,7 @@ extern "C" { /** SOC_ETM_TASK_ST2_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_BASE + 0x1f0) +#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1f0) /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents LEDC_task_timer0_pause trigger status. * 0: Not triggered @@ -7909,7 +7909,7 @@ extern "C" { /** SOC_ETM_TASK_ST2_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_BASE + 0x1f4) +#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4) /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear LEDC_task_timer0_pause trigger status. * 0: Invalid, No effect @@ -8202,7 +8202,7 @@ extern "C" { /** SOC_ETM_TASK_ST3_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_BASE + 0x1f8) +#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1f8) /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents TG0_task_cnt_cap_timer0 trigger status. * 0: Not triggered @@ -8495,7 +8495,7 @@ extern "C" { /** SOC_ETM_TASK_ST3_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_BASE + 0x1fc) +#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1fc) /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. * 0: Invalid, No effect @@ -8788,7 +8788,7 @@ extern "C" { /** SOC_ETM_TASK_ST4_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_BASE + 0x200) +#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x200) /** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents MCPWM1_task_cmpr1_b_up trigger status. * 0: Not triggered @@ -9081,7 +9081,7 @@ extern "C" { /** SOC_ETM_TASK_ST4_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_BASE + 0x204) +#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x204) /** SOC_ETM_MCPWM1_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status. * 0: Invalid, No effect @@ -9374,7 +9374,7 @@ extern "C" { /** SOC_ETM_TASK_ST5_REG register * Tasks trigger status register */ -#define SOC_ETM_TASK_ST5_REG (DR_REG_SOC_BASE + 0x208) +#define SOC_ETM_TASK_ST5_REG (DR_REG_SOC_ETM_BASE + 0x208) /** SOC_ETM_I2S0_TASK_SYNC_CHECK_ST : R/WTC/SS; bitpos: [0]; default: 0; * Represents I2S0_task_sync_check trigger status. * 0: Not triggered @@ -9586,7 +9586,7 @@ extern "C" { /** SOC_ETM_TASK_ST5_CLR_REG register * Tasks trigger status clear register */ -#define SOC_ETM_TASK_ST5_CLR_REG (DR_REG_SOC_BASE + 0x20c) +#define SOC_ETM_TASK_ST5_CLR_REG (DR_REG_SOC_ETM_BASE + 0x20c) /** SOC_ETM_I2S0_TASK_SYNC_CHECK_ST_CLR : WT; bitpos: [0]; default: 0; * Configures whether or not to clear I2S0_task_sync_check trigger status. * 0: Invalid, No effect @@ -9798,7 +9798,7 @@ extern "C" { /** SOC_ETM_CLK_EN_REG register * ETM clock enable register */ -#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_BASE + 0x210) +#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x210) /** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0; * Configures whether or not to open register clock gate. * 0: Open the clock gate only when application writes registers @@ -9812,7 +9812,7 @@ extern "C" { /** SOC_ETM_DATE_REG register * ETM date register */ -#define SOC_ETM_DATE_REG (DR_REG_SOC_BASE + 0x214) +#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x214) /** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 37777745; * Configures the version. */ diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 05bc87b136..2e8bc781fd 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -19,7 +19,6 @@ #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6 #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1 #define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 diff --git a/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h index 88ada789e7..228e289ac0 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000) + /** I2S_INT_RAW_REG register * I2S interrupt raw register, valid in level. */ diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 08601b2574..604ac9d078 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -22,7 +22,6 @@ #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 diff --git a/components/soc/esp32s2/register/soc/i2s_reg.h b/components/soc/esp32s2/register/soc/i2s_reg.h index b19e25a604..7f2f7d0721 100644 --- a/components/soc/esp32s2/register/soc/i2s_reg.h +++ b/components/soc/esp32s2/register/soc/i2s_reg.h @@ -1,16 +1,18 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ +#pragma once +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc/soc.h" + +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) + #define I2S_CONF_REG(i) (REG_I2S_BASE(i) + 0x0008) /* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ /*description: */ @@ -1378,7 +1380,3 @@ extern "C" { #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index b9468b90fb..0d26f1eba1 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -30,7 +30,6 @@ #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 diff --git a/components/soc/esp32s3/register/soc/i2s_reg.h b/components/soc/esp32s3/register/soc/i2s_reg.h index 1629384434..872469a066 100644 --- a/components/soc/esp32s3/register/soc/i2s_reg.h +++ b/components/soc/esp32s3/register/soc/i2s_reg.h @@ -1,17 +1,18 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ - +#pragma once #include "soc/soc.h" + #ifdef __cplusplus extern "C" { #endif +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) + #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xC) /* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/ @@ -1092,7 +1093,3 @@ when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/ #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2S_REG_H_ */