diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 8dd466030a..afd71f345e 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -1,9 +1,6 @@ idf_build_get_property(target IDF_TARGET) set(srcs - "adc_common.c" - "dac_common.c" - "dedic_gpio.c" "gpio.c" "i2c.c" "i2s.c" @@ -22,44 +19,62 @@ set(srcs "spi_slave.c" "spi_bus_lock.c" "timer.c" - "touch_sensor_common.c" - "twai.c" "uart.c") set(includes "include" "${target}/include") if(${target} STREQUAL "esp32") # SDMMC and MCPWM are in ESP32 only. - list(APPEND srcs "mcpwm.c" + list(APPEND srcs "adc_common.c" + "dac_common.c" + "dedic_gpio.c" + "mcpwm.c" "sdio_slave.c" "sdmmc_host.c" "sdmmc_transaction.c" + "touch_sensor_common.c" + "twai.c" "esp32/touch_sensor.c" "esp32/adc.c" "esp32/dac.c") list(APPEND includes "esp32/include") endif() -if(${target} STREQUAL "esp32s2") - list(APPEND srcs "esp32s2/rtc_tempsensor.c" +if(IDF_TARGET STREQUAL "esp32s2") + list(APPEND srcs "adc_common.c" + "dac_common.c" + "dedic_gpio.c" + "spi_slave_hd.c" + "touch_sensor_common.c" + "twai.c" + "esp32s2/rtc_tempsensor.c" "esp32s2/touch_sensor.c" "esp32s2/adc.c" "esp32s2/adc2_init_cal.c" - "spi_slave_hd.c" "esp32s2/dac.c") list(APPEND includes "esp32s2/include") endif() if(${target} STREQUAL "esp32s3") - list(APPEND srcs "spi_slave_hd.c" + list(APPEND srcs "adc_common.c" + "dac_common.c" + "dedic_gpio.c" + "spi_slave_hd.c" + "touch_sensor_common.c" + "twai.c" ) endif() +if(IDF_TARGET STREQUAL "esp32c3") + list(APPEND srcs "spi_slave_hd.c" + "esp32c3/rtc_tempsensor.c") +endif() + idf_component_register(SRCS "${srcs}" INCLUDE_DIRS ${includes} PRIV_INCLUDE_DIRS "include/driver" PRIV_REQUIRES efuse esp_pm esp_timer esp_ipc - REQUIRES esp_ringbuf freertos soc hal) + REQUIRES esp_ringbuf freertos soc hal esp_hw_support) # (REQUIRES cannot hide soc headers, since many arguments in the driver headers are chip-dependent) # uses C11 atomic feature diff --git a/components/driver/include/driver/spi_master.h b/components/driver/include/driver/spi_master.h index 06060c37af..717287a62d 100644 --- a/components/driver/include/driver/spi_master.h +++ b/components/driver/include/driver/spi_master.h @@ -22,7 +22,6 @@ /** SPI master clock is divided by 80MHz apb clock. Below defines are example frequencies, and are accurate. Be free to specify a random frequency, it will be rounded to closest frequency (to macros below if above 8MHz). * 8MHz */ -#if APB_CLK_FREQ==80*1000*1000 #define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10) #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) ///< 8.89MHz #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) ///< 10MHz @@ -33,14 +32,6 @@ #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) ///< 26.67MHz #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) ///< 40MHz #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) ///< 80MHz -#elif APB_CLK_FREQ==40*1000*1000 -#define SPI_MASTER_FREQ_7M (APB_CLK_FREQ/6) ///< 13.33MHz -#define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/5) ///< 16MHz -#define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/4) ///< 20MHz -#define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/3) ///< 26.67MHz -#define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/2) ///< 40MHz -#define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/1) ///< 80MHz -#endif #ifdef __cplusplus extern "C" { diff --git a/components/driver/ledc.c b/components/driver/ledc.c index 69eae2c1ea..b5a6bcde0c 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -19,10 +19,12 @@ #include "soc/gpio_periph.h" #include "soc/ledc_periph.h" #include "soc/rtc.h" +#include "soc/soc_caps.h" #include "hal/ledc_hal.h" #include "driver/ledc.h" #include "esp_rom_gpio.h" #include "esp_rom_sys.h" +#include "soc/clk_ctrl_os.h" static const char* LEDC_TAG = "ledc"; @@ -93,23 +95,13 @@ static IRAM_ATTR void ledc_ls_channel_update(ledc_mode_t speed_mode, ledc_channe //We know that CLK8M is about 8M, but don't know the actual value. So we need to do a calibration. static bool ledc_slow_clk_calibrate(void) { -#ifdef CONFIG_IDF_TARGET_ESP32 - //Enable CLK8M for LEDC - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); - //Waiting for CLK8M to turn on - esp_rom_delay_us(DELAY_CLK8M_CLK_SWITCH); - uint32_t cal_val = rtc_clk_cal(RTC_CAL_8MD256, SLOW_CLK_CYC_CALIBRATE); - if(cal_val == 0) { - ESP_LOGE(LEDC_TAG, "CLK8M_CLK calibration failed"); - return false; + if (periph_rtc_dig_clk8m_enable()) { + s_ledc_slow_clk_8M = periph_rtc_dig_clk8m_get_freq(); + ESP_LOGD(LEDC_TAG, "Calibrate CLK8M_CLK : %d Hz", s_ledc_slow_clk_8M); + return true; } - s_ledc_slow_clk_8M = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / cal_val; - ESP_LOGD(LEDC_TAG, "Calibrate CLK8M_CLK : %d Hz", s_ledc_slow_clk_8M); - return true; -#else - ESP_LOGE(LEDC_TAG, "CLK8M source currently only supported on ESP32"); + ESP_LOGE(LEDC_TAG, "Calibrate CLK8M_CLK failed"); return false; -#endif } static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg) @@ -121,7 +113,7 @@ static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg) src_clk_freq = LEDC_REF_CLK_HZ; } else if (clk_cfg == LEDC_USE_RTC8M_CLK) { src_clk_freq = s_ledc_slow_clk_8M; -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if SOC_LEDC_SUPPORT_XTAL_CLOCK } else if (clk_cfg == LEDC_USE_XTAL_CLK) { src_clk_freq = rtc_clk_xtal_freq_get() * 1000000; #endif @@ -349,6 +341,9 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t* timer_conf) if(p_ledc_obj[speed_mode] == NULL) { p_ledc_obj[speed_mode] = (ledc_obj_t *) heap_caps_calloc(1, sizeof(ledc_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + if (p_ledc_obj[speed_mode] == NULL) { + return ESP_ERR_NO_MEM; + } ledc_hal_init(&(p_ledc_obj[speed_mode]->ledc_hal), speed_mode); } @@ -380,11 +375,16 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf) LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "gpio_num"); LEDC_ARG_CHECK(timer_select < LEDC_TIMER_MAX, "timer_select"); + LEDC_ARG_CHECK(intr_type < LEDC_INTR_MAX, "intr_type"); + periph_module_enable(PERIPH_LEDC_MODULE); esp_err_t ret = ESP_OK; if(p_ledc_obj[speed_mode] == NULL) { p_ledc_obj[speed_mode] = (ledc_obj_t *) heap_caps_calloc(1, sizeof(ledc_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + if (p_ledc_obj[speed_mode] == NULL) { + return ESP_ERR_NO_MEM; + } ledc_hal_init(&(p_ledc_obj[speed_mode]->ledc_hal), speed_mode); } diff --git a/components/driver/spi_bus_lock.c b/components/driver/spi_bus_lock.c index bb4f18444c..a32f27bb5b 100644 --- a/components/driver/spi_bus_lock.c +++ b/components/driver/spi_bus_lock.c @@ -22,6 +22,7 @@ #include "stdatomic.h" #include "esp_log.h" #include +#include "esp_heap_caps.h" /* diff --git a/components/driver/test/include/test/test_common_spi.h b/components/driver/test/include/test/test_common_spi.h index f2cf965265..6b46d304a2 100644 --- a/components/driver/test/include/test/test_common_spi.h +++ b/components/driver/test/include/test/test_common_spi.h @@ -85,6 +85,41 @@ #define ESP_SPI_SLAVE_TV 0 #define WIRE_DELAY 12.5 +#elif CONFIG_IDF_TARGET_ESP32C3 + +#define TEST_SPI_HOST FSPI_HOST +#define TEST_SLAVE_HOST FSPI_HOST + +#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO +#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI +#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK +#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS + +#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP +#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD + +#define SLAVE_PIN_NUM_MISO -1 +#define SLAVE_PIN_NUM_MOSI -1 +#define SLAVE_PIN_NUM_CLK -1 +#define SLAVE_PIN_NUM_CS -1 +#define SLAVE_PIN_NUM_WP -1 +#define SLAVE_PIN_NUM_HD -1 + +//NOTE: On esp32c3, there is only 1 GPSPI controller, so master-slave test on single board should be disabled +#define SLAVE_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO +#define SLAVE_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI +#define SLAVE_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK +#define SLAVE_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS + +#define MASTER_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO +#define MASTER_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI +#define MASTER_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK +#define MASTER_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS + +#define GPIO_DELAY 0 +#define ESP_SPI_SLAVE_TV 0 +#define WIRE_DELAY 12.5 + #endif #define GET_DMA_CHAN(HOST) (HOST) diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c index b8bf98934a..792421838b 100644 --- a/components/driver/test/test_gpio.c +++ b/components/driver/test/test_gpio.c @@ -16,7 +16,6 @@ #include "esp_rom_uart.h" #include "esp_rom_sys.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) #define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated. @@ -35,8 +34,23 @@ #define TEST_GPIO_OUTPUT_PIN 12 #define TEST_GPIO_INPUT_ONLY_PIN 46 #define TEST_GPIO_OUTPUT_MAX GPIO_NUM_46 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define TEST_GPIO_EXT_OUT_IO 19 // default output GPIO +#define TEST_GPIO_EXT_IN_IO 20 // default input GPIO +#define TEST_GPIO_OUTPUT_PIN 12 +#define TEST_GPIO_INPUT_ONLY_PIN 46 +#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_47 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define TEST_GPIO_EXT_OUT_IO 2 // default output GPIO +#define TEST_GPIO_EXT_IN_IO 3 // default input GPIO +#define TEST_GPIO_OUTPUT_PIN 1 +#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_21 #endif +// define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3) +#define TEST_IO_9 GPIO_NUM_9 +#define TEST_IO_10 GPIO_NUM_10 + static volatile int disable_intr_times = 0; // use this to calculate how many times it go into interrupt static volatile int level_intr_times = 0; // use this to get how many times the level interrupt happened static volatile int edge_intr_times = 0; // use this to get how many times the edge interrupt happened @@ -62,7 +76,7 @@ static gpio_config_t init_io(gpio_num_t num) return io_conf; } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) //No runners // edge interrupt event static void gpio_isr_edge_handler(void* arg) @@ -95,7 +109,7 @@ static void gpio_isr_level_handler2(void* arg) esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", TEST_GPIO_EXT_OUT_IO, gpio_get_level(TEST_GPIO_EXT_OUT_IO), level_intr_times); esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times); } -#endif +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) #if !WAKE_UP_IGNORE // get result of waking up or not @@ -120,7 +134,7 @@ static void trigger_wake_up(void *arg) gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1); vTaskDelay(100 / portTICK_RATE_MS); } -#endif +#endif //!WAKE_UP_IGNORE static void prompt_to_continue(const char* str) { @@ -169,16 +183,18 @@ TEST_CASE("GPIO config parameters test", "[gpio]") io_config.pin_bit_mask = ((uint64_t)1< 1 + &I2C1, +#endif +}; + + static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, size_t size) { @@ -248,7 +266,7 @@ TEST_CASE("I2C driver memory leaking check", "[i2c]") TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size()); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) // print the reading buffer static void disp_buf(uint8_t *buf, int len) @@ -378,7 +396,7 @@ static void slave_write_buffer_test(void) TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test); -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32, ESP32C3) static void i2c_master_write_read_test(void) { uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH); @@ -519,8 +537,8 @@ static void i2c_slave_repeat_read(void) TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read); -#endif //DISABLED_FOR_TARGET(ESP32S2, ESP32) -#endif //DISABLED_FOR_TARGET(ESP32S2) +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) static volatile bool exit_flag; static bool test_read_func; @@ -629,7 +647,7 @@ TEST_CASE("I2C general API test", "[i2c]") } } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) //Init uart baud rate detection static void uart_aut_baud_det_init(int rxd_io_num) { @@ -693,4 +711,4 @@ TEST_CASE("I2C SCL freq test (local test)", "[i2c][ignore]") TEST_ESP_OK(i2c_driver_delete(i2c_num)); } -#endif +#endif // TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) diff --git a/components/driver/test/test_i2s.c b/components/driver/test/test_i2s.c index e008166591..1a0291b122 100644 --- a/components/driver/test/test_i2s.c +++ b/components/driver/test/test_i2s.c @@ -15,7 +15,7 @@ #include "math.h" #include "esp_rom_gpio.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) #define SAMPLE_RATE (36000) #define SAMPLE_BITS (16) diff --git a/components/driver/test/test_ledc.c b/components/driver/test/test_ledc.c index 9bb55e62ea..d17f1d475c 100644 --- a/components/driver/test/test_ledc.c +++ b/components/driver/test/test_ledc.c @@ -17,23 +17,88 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "freertos/queue.h" -#include "freertos/xtensa_api.h" #include "unity.h" #include "soc/ledc_periph.h" #include "esp_system.h" -#include "driver/pcnt.h" #include "driver/ledc.h" #include "driver/gpio.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) - #define PULSE_IO 18 #define PCNT_INPUT_IO 4 #define PCNT_CTRL_FLOATING_IO 5 #define HIGHEST_LIMIT 10000 #define LOWEST_LIMIT -10000 -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if SOC_LEDC_SUPPORT_HS_MODE +#define TEST_SPEED_MODE LEDC_HIGH_SPEED_MODE +#define SPEED_MODE_LIST {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE} +#else +#define TEST_SPEED_MODE LEDC_LOW_SPEED_MODE +#define SPEED_MODE_LIST {LEDC_LOW_SPEED_MODE} +#endif + +static ledc_channel_config_t initialize_channel_config(void) +{ + ledc_channel_config_t config; + memset(&config, 0, sizeof(ledc_channel_config_t)); + config.gpio_num = PULSE_IO; + config.speed_mode = TEST_SPEED_MODE; + config.channel = LEDC_CHANNEL_0; + config.intr_type = LEDC_INTR_DISABLE; + config.timer_sel = LEDC_TIMER_0; + config.duty = 4000; + config.hpoint = 0; + return config; +} + +static ledc_timer_config_t create_default_timer_config(void) +{ + ledc_timer_config_t ledc_time_config; + memset(&ledc_time_config, 0, sizeof(ledc_timer_config_t)); + ledc_time_config.speed_mode = TEST_SPEED_MODE; + ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT; + ledc_time_config.timer_num = LEDC_TIMER_0; + ledc_time_config.freq_hz = 2000; + ledc_time_config.clk_cfg = LEDC_USE_APB_CLK; + return ledc_time_config; +} + +static void timer_duty_set_get(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty) +{ + TEST_ESP_OK(ledc_set_duty(speed_mode, channel, duty)); + TEST_ESP_OK(ledc_update_duty(speed_mode, channel)); + vTaskDelay(1000 / portTICK_RATE_MS); + TEST_ASSERT_EQUAL_INT32(ledc_get_duty(speed_mode, channel), duty); +} + +// use logic analyzer to view +static void timer_duty_test(ledc_channel_t channel, ledc_timer_bit_t timer_bit, ledc_timer_t timer, ledc_mode_t speed_mode) +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + ledc_ch_config.speed_mode = speed_mode; + ledc_ch_config.channel = channel; + ledc_ch_config.timer_sel = timer; + + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + ledc_time_config.speed_mode = speed_mode; + ledc_time_config.duty_resolution = timer_bit; + ledc_time_config.timer_num = timer; + + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); + TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); + + // duty ratio: (2^duty)/(2^timer_bit) + timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 0); + timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 1); + timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 1 << 12); // 50% duty + timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, (1 << 13) - 1); + timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, (1 << 13) - 2); +} + +#if SOC_PCNT_SUPPORTED +#include "driver/pcnt.h" // TODO: C3 doesn't have PCNT peripheral + +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) //no runners // use PCNT to test the waveform of LEDC @@ -101,182 +166,135 @@ static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_ frequency_set_get(ledc_ch_config.speed_mode, ledc_ch_config.timer_sel, 9000, 9025, 5); } -static void timer_duty_set_get(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty) +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) + +#endif // SOC_PCNT_SUPPORTED + +TEST_CASE("LEDC channel config wrong gpio", "[ledc]") { - TEST_ESP_OK(ledc_set_duty(speed_mode, channel, duty)); - TEST_ESP_OK(ledc_update_duty(speed_mode, channel)); - vTaskDelay(1000 / portTICK_RATE_MS); - TEST_ASSERT_EQUAL_INT32(ledc_get_duty(speed_mode, channel), duty); -} - -// use logic analyzer to view -static void timer_duty_test(ledc_channel_t channel, ledc_timer_bit_t timer_bit, ledc_timer_t timer, ledc_mode_t speed_mode) -{ - ledc_channel_config_t ledc_ch_config = { - .gpio_num = PULSE_IO, - .speed_mode = speed_mode, - .channel = channel, - .intr_type = LEDC_INTR_DISABLE, - .timer_sel = timer, - .duty = 4000, - .hpoint = 0, - }; - ledc_timer_config_t ledc_time_config = { - .speed_mode = speed_mode, - .duty_resolution = timer_bit, - .timer_num = timer, - .freq_hz = 5000, - .clk_cfg = LEDC_USE_APB_CLK, - }; - TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); - TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); - - // duty ratio: (2^duty)/(2^timer_bit) - timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 0); - timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 1); - timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, 1 << 12); // 50% duty - timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, (1 << 13) - 1); - timer_duty_set_get(ledc_ch_config.speed_mode, ledc_ch_config.channel, (1 << 13) - 2); -} - -TEST_CASE("LEDC error log channel and timer config", "[ledc][test_env=UT_T1_LEDC]") -{ -#ifdef CONFIG_IDF_TARGET_ESP32 - const ledc_mode_t test_speed_mode = LEDC_HIGH_SPEED_MODE; -#elif defined CONFIG_IDF_TARGET_ESP32S2 - const ledc_mode_t test_speed_mode = LEDC_LOW_SPEED_MODE; -#endif - //channel configuration test - ledc_channel_config_t ledc_ch_config = { - .gpio_num = PULSE_IO, - .speed_mode = test_speed_mode, - .channel = LEDC_CHANNEL_0, - .intr_type = LEDC_INTR_DISABLE, - .timer_sel = LEDC_TIMER_0, - .duty = 4000, - .hpoint = 0, - }; - - // basic right parameter test - ledc_channel_config_t temp_ch_config = ledc_ch_config; - TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); - - // with wrong GPIO using + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); ledc_ch_config.gpio_num = GPIO_NUM_MAX; TEST_ASSERT(ledc_channel_config(&ledc_ch_config) == ESP_ERR_INVALID_ARG); - // with wrong speed - ledc_ch_config = temp_ch_config; +} + +TEST_CASE("LEDC channel config wrong speed", "[ledc]") +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); ledc_ch_config.speed_mode = LEDC_SPEED_MODE_MAX; TEST_ASSERT(ledc_channel_config(&ledc_ch_config) == ESP_ERR_INVALID_ARG); +} - // with wrong channel - ledc_ch_config = temp_ch_config; +TEST_CASE("LEDC channel config wrong channel", "[ledc]") +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); ledc_ch_config.channel = LEDC_CHANNEL_MAX; TEST_ASSERT(ledc_channel_config(&ledc_ch_config) == ESP_ERR_INVALID_ARG); +} - // with wrong interruption type - ledc_ch_config = temp_ch_config; +TEST_CASE("LEDC channel config wrong interrupt type", "[ledc]") +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); ledc_ch_config.intr_type = 2; - TEST_ASSERT_FALSE((void *)ledc_channel_config(&ledc_ch_config)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, ledc_channel_config(&ledc_ch_config)); +} - // with wrong timer - ledc_ch_config = temp_ch_config; - ledc_ch_config.timer_sel = 4; - TEST_ASSERT(ledc_channel_config(&ledc_ch_config) == ESP_ERR_INVALID_ARG); +TEST_CASE("LEDC wrong timer", "[ledc]") +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + ledc_ch_config.timer_sel = LEDC_TIMER_MAX; + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, ledc_channel_config(&ledc_ch_config)); +} - ledc_ch_config = temp_ch_config; - ledc_ch_config.duty = 12000; - TEST_ASSERT_FALSE((void *)ledc_channel_config(&ledc_ch_config)); +TEST_CASE("LEDC channel config basic parameter test", "[ledc]") +{ + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + TEST_ASSERT_EQUAL(ESP_OK, ledc_channel_config(&ledc_ch_config)); +} - // timer configuration test - ledc_timer_config_t ledc_time_config; - ledc_time_config.speed_mode = test_speed_mode; - ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT; - ledc_time_config.timer_num = LEDC_TIMER_0; - ledc_time_config.freq_hz = 5000; - ledc_time_config.clk_cfg = LEDC_USE_APB_CLK; - - ledc_timer_config_t temp_timer_config = ledc_time_config; - TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); - - ledc_time_config.speed_mode = LEDC_SPEED_MODE_MAX; - TEST_ASSERT(ledc_timer_config(&ledc_time_config) == ESP_ERR_INVALID_ARG); - - // wrong duty_resolution - ledc_time_config = temp_timer_config; +TEST_CASE("LEDC wrong duty resolution", "[ledc]") +{ + ledc_timer_config_t ledc_time_config = create_default_timer_config(); ledc_time_config.duty_resolution = LEDC_TIMER_BIT_MAX; - TEST_ASSERT(ledc_timer_config(&ledc_time_config) == ESP_ERR_INVALID_ARG); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, ledc_timer_config(&ledc_time_config)); +} - // wrong timer - ledc_time_config = temp_timer_config; - ledc_time_config.timer_num = 4; - TEST_ASSERT(ledc_timer_config(&ledc_time_config) == ESP_ERR_INVALID_ARG); +TEST_CASE("LEDC timer config wrong timer", "[ledc]") +{ + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + ledc_time_config.timer_num = LEDC_TIMER_MAX; + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, ledc_timer_config(&ledc_time_config)); +} + +TEST_CASE("LEDC timer config wrong speed mode", "[ledc]") +{ + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + ledc_time_config.speed_mode = LEDC_SPEED_MODE_MAX; + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, ledc_timer_config(&ledc_time_config)); +} + +TEST_CASE("LEDC timer config basic parameter test", "[ledc]") +{ + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); +} + +TEST_CASE("LEDC error log channel and timer config", "[ledc]") +{ + const ledc_mode_t test_speed_mode = TEST_SPEED_MODE; + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); uint32_t current_level = LEDC.channel_group[test_speed_mode].channel[LEDC_CHANNEL_0].conf0.idle_lv; TEST_ESP_OK(ledc_stop(test_speed_mode, LEDC_CHANNEL_0, !current_level)); vTaskDelay(1000 / portTICK_RATE_MS); - TEST_ASSERT_EQUAL_INT32( LEDC.channel_group[test_speed_mode].channel[LEDC_CHANNEL_0].conf0.idle_lv, !current_level); + TEST_ASSERT_EQUAL_INT32(LEDC.channel_group[test_speed_mode].channel[LEDC_CHANNEL_0].conf0.idle_lv, !current_level); } -TEST_CASE("LEDC normal channel and timer config", "[ledc][test_env=UT_T1_LEDC]") +TEST_CASE("LEDC iterate over all channel and timer configs", "[ledc]") { - ledc_channel_config_t ledc_ch_config = { - .gpio_num = PULSE_IO, - .channel = LEDC_CHANNEL_0, - .intr_type = LEDC_INTR_DISABLE, - .timer_sel = LEDC_TIMER_0, - .duty = 4000, - .hpoint = 0, - }; - ledc_channel_config_t temp_ch_config = ledc_ch_config; - - ledc_timer_config_t ledc_time_config = { - .duty_resolution = LEDC_TIMER_13_BIT, - .timer_num = LEDC_TIMER_0, - .freq_hz = 5000, - .clk_cfg = LEDC_USE_APB_CLK, - }; - ledc_timer_config_t temp_time_config = ledc_time_config; + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + ledc_timer_config_t ledc_time_config = create_default_timer_config(); // use all kinds of speed mode, channel, timer combination to test all of possible configuration -#ifdef CONFIG_IDF_TARGET_ESP32 - ledc_mode_t speed_mode[LEDC_SPEED_MODE_MAX] = {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE}; -#elif defined CONFIG_IDF_TARGET_ESP32S2 - ledc_mode_t speed_mode[LEDC_SPEED_MODE_MAX] = {LEDC_LOW_SPEED_MODE}; -#endif - ledc_channel_t channel_type[8] = {LEDC_CHANNEL_0, LEDC_CHANNEL_1, LEDC_CHANNEL_2, LEDC_CHANNEL_3, LEDC_CHANNEL_4, LEDC_CHANNEL_5, LEDC_CHANNEL_6, LEDC_CHANNEL_7}; + ledc_mode_t speed_mode[LEDC_SPEED_MODE_MAX] = SPEED_MODE_LIST; + ledc_channel_t channels[8] = {LEDC_CHANNEL_0, LEDC_CHANNEL_1, LEDC_CHANNEL_2, LEDC_CHANNEL_3, LEDC_CHANNEL_4, LEDC_CHANNEL_5}; ledc_timer_t timer_select[4] = {LEDC_TIMER_0, LEDC_TIMER_1, LEDC_TIMER_2, LEDC_TIMER_3}; for (int i = 0; i < LEDC_SPEED_MODE_MAX; i++) { ledc_ch_config.speed_mode = speed_mode[i]; ledc_time_config.speed_mode = speed_mode[i]; for (int j = 0; j < 8; j++) { - ledc_ch_config.channel = channel_type[j]; + ledc_ch_config.channel = channels[j]; for (int k = 0; k < 4; k++) { ledc_ch_config.timer_sel = timer_select[k]; ledc_time_config.timer_num = timer_select[k]; TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); - ledc_ch_config = temp_ch_config; - ledc_time_config = temp_time_config; } } } } -// set it ignore: need to debug -TEST_CASE("LEDC set and get frequency", "[ledc][test_env=UT_T1_LEDC][timeout=60][ignore]") +TEST_CASE("LEDC memory leak test", "[ledc]") { -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_0, LEDC_HIGH_SPEED_MODE); - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_1, LEDC_HIGH_SPEED_MODE); - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_2, LEDC_HIGH_SPEED_MODE); - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_3, LEDC_HIGH_SPEED_MODE); -#endif - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_0, LEDC_LOW_SPEED_MODE); - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_1, LEDC_LOW_SPEED_MODE); - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_2, LEDC_LOW_SPEED_MODE); - timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_3, LEDC_LOW_SPEED_MODE); + ledc_channel_config_t ledc_ch_config = initialize_channel_config(); + TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); + + ledc_timer_config_t ledc_time_config = create_default_timer_config(); + TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); + + uint32_t size = esp_get_free_heap_size(); + uint32_t i; + + // install and uninstall for 1000 times to test whether memory leaking exists + for (i = 0; i <= 1000; i++) { + TEST_ESP_OK(ledc_fade_func_install(0)); + ledc_fade_func_uninstall(); + } + TEST_ASSERT_INT32_WITHIN(100, size, esp_get_free_heap_size()); + TEST_ESP_OK(ledc_stop(ledc_time_config.speed_mode, LEDC_CHANNEL_0, 0)); } // the duty need to be detected by waveform given by the logic analyzer @@ -284,11 +302,7 @@ TEST_CASE("LEDC set and get frequency", "[ledc][test_env=UT_T1_LEDC][timeout=60] TEST_CASE("LEDC set and get dut(with logic analyzer)", "[ledc][ignore]") { ledc_timer_t timer_list[4] = {LEDC_TIMER_0, LEDC_TIMER_1, LEDC_TIMER_2, LEDC_TIMER_3}; -#ifdef CONFIG_IDF_TARGET_ESP32 - ledc_mode_t speed_mode_list[LEDC_SPEED_MODE_MAX] = {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE}; -#elif defined CONFIG_IDF_TARGET_ESP32S2 - ledc_mode_t speed_mode_list[LEDC_SPEED_MODE_MAX] = {LEDC_LOW_SPEED_MODE}; -#endif + ledc_mode_t speed_mode_list[LEDC_SPEED_MODE_MAX] = SPEED_MODE_LIST; for(int i=0; i #include "esp_system.h" -#include "driver/pcnt.h" #include "unity.h" #include "test_utils.h" #include "freertos/FreeRTOS.h" @@ -25,10 +24,10 @@ #include "soc/rtc.h" #include "soc/soc_caps.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) - #if SOC_MCPWM_SUPPORTED +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #include "soc/mcpwm_periph.h" +#include "driver/pcnt.h" #include "driver/mcpwm.h" @@ -788,6 +787,5 @@ TEST_CASE("MCPWM unit1, timer2 capture test", "[mcpwm][test_env=UT_T1_MCPWM][tim capture_test(MCPWM_UNIT_1, MCPWM_TIMER_2, MCPWM_POS_EDGE); } -#endif - -#endif +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#endif // SOC_MCPWM_SUPPORTED diff --git a/components/driver/test/test_rmt.c b/components/driver/test/test_rmt.c index 1cc4600ef4..a9fad4dfb8 100644 --- a/components/driver/test/test_rmt.c +++ b/components/driver/test/test_rmt.c @@ -1,5 +1,4 @@ // RMT driver unit test is based on extended NEC protocol -// Please don't use channel number: SOC_RMT_CHANNELS_NUM - 1 #include #include #include "sdkconfig.h" @@ -16,7 +15,7 @@ #define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CHANNELS_NUM-1) // CI ONLY: Don't connect any other signals to this GPIO -#define RMT_DATA_IO (12) // bind signal RMT_SIG_OUT0_IDX and RMT_SIG_IN0_IDX on the same GPIO +#define RMT_DATA_IO (4) // bind signal RMT_SIG_OUT0_IDX and RMT_SIG_IN0_IDX on the same GPIO #define RMT_TESTBENCH_FLAGS_ALWAYS_ON (1<<0) #define RMT_TESTBENCH_FLAGS_CARRIER_ON (1<<1) @@ -103,7 +102,7 @@ static void rmt_clean_testbench(int tx_channel, int rx_channel) } } -TEST_CASE("RMT wrong configuration", "[rmt][error]") +TEST_CASE("RMT wrong configuration", "[rmt]") { rmt_config_t correct_config = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, 0); rmt_config_t wrong_config = correct_config; @@ -179,25 +178,30 @@ TEST_CASE("RMT miscellaneous functions", "[rmt]") TEST_CASE("RMT multiple channels", "[rmt]") { - rmt_config_t tx_cfg1 = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, 0); + rmt_config_t tx_cfg = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, 0); + for (int i = 0; i < SOC_RMT_TX_CHANNELS_NUM; i++) { + tx_cfg.channel = i; + TEST_ESP_OK(rmt_config(&tx_cfg)); + TEST_ESP_OK(rmt_driver_install(tx_cfg.channel, 0, 0)); + } - TEST_ESP_OK(rmt_config(&tx_cfg1)); - TEST_ESP_OK(rmt_driver_install(tx_cfg1.channel, 0, 0)); + for (int i = 0; i < SOC_RMT_TX_CHANNELS_NUM; i++) { + TEST_ESP_OK(rmt_driver_uninstall(i)); + } - rmt_config_t tx_cfg2 = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, 1); - TEST_ESP_OK(rmt_config(&tx_cfg2)); - TEST_ESP_OK(rmt_driver_install(tx_cfg2.channel, 0, 0)); + rmt_config_t rx_cfg = RMT_DEFAULT_CONFIG_RX(RMT_DATA_IO, RMT_RX_CHANNEL_ENCODING_START); + for (int i = RMT_RX_CHANNEL_ENCODING_START; i < SOC_RMT_CHANNELS_NUM; i++) { + rx_cfg.channel = i; + TEST_ESP_OK(rmt_config(&rx_cfg)); + TEST_ESP_OK(rmt_driver_install(rx_cfg.channel, 0, 0)); + } - rmt_config_t tx_cfg3 = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, 2); - TEST_ESP_OK(rmt_config(&tx_cfg3)); - TEST_ESP_OK(rmt_driver_install(tx_cfg3.channel, 0, 0)); - - TEST_ESP_OK(rmt_driver_uninstall(2)); - TEST_ESP_OK(rmt_driver_uninstall(1)); - TEST_ESP_OK(rmt_driver_uninstall(0)); + for (int i = RMT_RX_CHANNEL_ENCODING_START; i < SOC_RMT_CHANNELS_NUM; i++) { + TEST_ESP_OK(rmt_driver_uninstall(i)); + } } -TEST_CASE("RMT install/uninstall test", "[rmt][pressure]") +TEST_CASE("RMT install/uninstall test", "[rmt]") { rmt_config_t tx_cfg = RMT_DEFAULT_CONFIG_TX(RMT_DATA_IO, RMT_TX_CHANNEL_ENCODING_END); TEST_ESP_OK(rmt_config(&tx_cfg)); @@ -449,8 +453,8 @@ TEST_CASE("RMT TX simultaneously", "[rmt]") frames[i].level1 = 0; frames[i].duration1 = 0; - rmt_config_t tx_config0 = RMT_DEFAULT_CONFIG_TX(12, channel0); - rmt_config_t tx_config1 = RMT_DEFAULT_CONFIG_TX(13, channel1); + rmt_config_t tx_config0 = RMT_DEFAULT_CONFIG_TX(4, channel0); + rmt_config_t tx_config1 = RMT_DEFAULT_CONFIG_TX(5, channel1); TEST_ESP_OK(rmt_config(&tx_config0)); TEST_ESP_OK(rmt_config(&tx_config1)); diff --git a/components/driver/test/test_rs485.c b/components/driver/test/test_rs485.c index cc42fe4401..9a503309ab 100644 --- a/components/driver/test/test_rs485.c +++ b/components/driver/test/test_rs485.c @@ -9,8 +9,6 @@ #include "esp_log.h" #include "esp_system.h" // for uint32_t esp_random() -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) - #define UART_TAG "Uart" #define UART_NUM1 (UART_NUM_1) #define BUF_SIZE (100) @@ -31,7 +29,7 @@ // Wait timeout for uart driver #define PACKET_READ_TICS (1000 / portTICK_RATE_MS) -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) //No runners // The table for fast CRC16 calculation @@ -289,6 +287,4 @@ static void rs485_master(void) */ TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave); -#endif - -#endif +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) diff --git a/components/driver/test/test_rtcio.c b/components/driver/test/test_rtcio.c index 02d02514ef..2e4fdbab3c 100644 --- a/components/driver/test/test_rtcio.c +++ b/components/driver/test/test_rtcio.c @@ -16,7 +16,7 @@ #include "esp_log.h" #include "soc/rtc_io_periph.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) #define RTCIO_CHECK(condition) TEST_ASSERT_MESSAGE((condition == ESP_OK), "ret is not ESP_OK") #define RTCIO_VERIFY(condition, msg) TEST_ASSERT_MESSAGE((condition), msg) diff --git a/components/driver/test/test_sigmadelta.c b/components/driver/test/test_sigmadelta.c index d0a1856ac3..d702511ba9 100644 --- a/components/driver/test/test_sigmadelta.c +++ b/components/driver/test/test_sigmadelta.c @@ -5,7 +5,7 @@ #include "soc/soc_caps.h" #include "driver/sigmadelta.h" -TEST_CASE("Sigma-Delta config test", "[sigma_delta]") +TEST_CASE("SigmaDelta config test", "[sigma_delta]") { sigmadelta_config_t sigmadelta_cfg = { .sigmadelta_prescale = 80, diff --git a/components/driver/test/test_spi_bus_lock.c b/components/driver/test/test_spi_bus_lock.c index 7a165682c0..469b43bce6 100644 --- a/components/driver/test/test_spi_bus_lock.c +++ b/components/driver/test/test_spi_bus_lock.c @@ -7,7 +7,7 @@ #include "test/test_common_spi.h" #include "unity.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) #if CONFIG_IDF_TARGET_ESP32 // The VSPI pins on UT_T1_ESP_FLASH are connected to a external flash @@ -345,6 +345,6 @@ TEST_CASE("spi master can be used on SPI1", "[spi]") //TODO: add a case when a non-polling transaction happened in the bus-acquiring time and then release the bus then queue a new trans -#endif +#endif //!CONFIG_ESP32_SPIRAM_SUPPORT -#endif +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 1846097676..ffca8d2522 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -264,6 +264,7 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") { TEST_ASSERT(success); } +#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs) { esp_err_t ret; @@ -322,6 +323,9 @@ TEST_CASE("spi placed on input-only pins", "[spi]") TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN)); } +//There is no input-only pin on esp32c3, so this test could be ignored. +#endif //#if !DISABLED_FOR_TARGETS(ESP32C3) + TEST_CASE("spi bus setting with different pin configs", "[spi]") { spi_bus_config_t cfg; @@ -366,6 +370,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); +#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, @@ -394,6 +399,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); +#endif ESP_LOGI(TAG, "check native flag for 6 output pins..."); flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; @@ -411,6 +417,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); +#if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, @@ -432,6 +439,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); +#endif ESP_LOGI(TAG, "check sclk flag..."); flags_expected = SPICOMMON_BUSFLAG_SCLK; @@ -552,20 +560,23 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") TEST_ASSERT(esp_ptr_in_dram(data_malloc)); #endif TEST_ASSERT(data_malloc != NULL); + TEST_ASSERT(esp_ptr_in_dram(data_dram)); + TEST_ASSERT(esp_ptr_in_drom(data_drom)); + ESP_LOGI(TAG, "dram: %p", data_dram); + ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc); - //refer to soc_memory_layout.c +#ifndef CONFIG_ESP32C3_MEMPROT_FEATURE uint32_t* data_iram = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_EXEC); TEST_ASSERT(data_iram != NULL); - - ESP_LOGI(TAG, "iram: %p, dram: %p", data_iram, data_dram); - ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc); - TEST_ASSERT(esp_ptr_in_dram(data_dram)); TEST_ASSERT(esp_ptr_executable(data_iram) || esp_ptr_in_iram(data_iram) || esp_ptr_in_diram_iram(data_iram)); - TEST_ASSERT(esp_ptr_in_drom(data_drom)); + ESP_LOGI(TAG, "iram: %p", data_iram); +#endif srand(52); for (int i = 0; i < 320/4; i++) { +#ifndef CONFIG_ESP32C3_MEMPROT_FEATURE data_iram[i] = rand(); +#endif data_dram[i] = rand(); data_malloc[i] = rand(); } @@ -588,10 +599,9 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") #define TEST_REGION_SIZE 5 static spi_transaction_t trans[TEST_REGION_SIZE]; int x; - - memset(trans, 0, sizeof(trans)); +#ifndef CONFIG_ESP32C3_MEMPROT_FEATURE trans[0].length = 320*8, trans[0].tx_buffer = data_iram; trans[0].rx_buffer = data_malloc+1; @@ -601,12 +611,13 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") trans[1].rx_buffer = data_iram; trans[2].length = 320*8, - trans[2].tx_buffer = data_malloc+2; - trans[2].rx_buffer = data_dram; + trans[2].tx_buffer = data_drom; + trans[2].rx_buffer = data_iram; +#endif trans[3].length = 320*8, - trans[3].tx_buffer = data_drom; - trans[3].rx_buffer = data_iram; + trans[3].tx_buffer = data_malloc+2; + trans[3].rx_buffer = data_dram; trans[4].length = 4*8, trans[4].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA; @@ -616,7 +627,11 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") *ptr = 0xbc124960; //Queue all transactions. +#ifndef CONFIG_ESP32C3_MEMPROT_FEATURE for (x=0; x (b)? (b): (a)) @@ -613,7 +616,7 @@ TEST_CASE("Slave receive correct data", "[spi]") } } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) //These tests are ESP32 only due to lack of runners /******************************************************************************** * Test By Master & Slave (2 boards) @@ -1163,4 +1166,6 @@ spitest_param_set_t mode_conf[] = { }; TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "") -#endif +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3) + +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3) diff --git a/components/driver/test/test_spi_sio.c b/components/driver/test/test_spi_sio.c index 92aef5b4f1..cdb95a6b3c 100644 --- a/components/driver/test/test_spi_sio.c +++ b/components/driver/test/test_spi_sio.c @@ -24,7 +24,7 @@ #include "hal/spi_ll.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) /******************************************************************************** * Test SIO @@ -102,7 +102,7 @@ TEST_CASE("local test sio", "[spi]") master_free_device_bus(spi); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) //These tests are ESP32 only due to lack of runners /******************************************************************************** * Test SIO Master & Slave @@ -220,6 +220,6 @@ void test_sio_slave(void) } TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave); -#endif +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) -#endif +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3, ESP32C3) diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/test_spi_slave.c index eb2d0b29e4..ba1975f267 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -3,15 +3,18 @@ */ #include +#include "sdkconfig.h" #include "unity.h" +#include "test/test_common_spi.h" #include "driver/spi_master.h" #include "driver/spi_slave.h" #include "driver/gpio.h" #include "esp_log.h" -#include "sdkconfig.h" -#include "test/test_common_spi.h" #include "esp_rom_gpio.h" +//There is only one GPSPI controller, so single-board test is disabled. +#if !DISABLED_FOR_TARGETS(ESP32C3) + #ifndef CONFIG_SPIRAM //This test should be removed once the timing test is merged. @@ -142,3 +145,5 @@ TEST_CASE("test slave send unaligned","[spi]") } #endif // !CONFIG_SPIRAM + +#endif // !TEMPORARY_DISABLED_FOR_TARGETS diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index c7b6b07991..63941a2a92 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -6,11 +6,15 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" +#include "unity.h" #include "soc/spi_periph.h" #include "driver/spi_master.h" #include "esp_serial_slave_link/essl_spi.h" +#if !DISABLED_FOR_TARGETS(ESP32C3) +//There is only one GPSPI controller on ESP32C3, so single-board test is disabled. + #if SOC_SPI_SUPPORT_SLAVE_HD_VER2 #include "driver/spi_slave_hd.h" #include "esp_rom_gpio.h" @@ -490,7 +494,7 @@ TEST_SPI_HD(HD, hd_conf); * * This test checks that the previous trans will not influence the data slave prepared for the next transaction. */ -TEST_CASE("test spi slave hd continuous mode, master too long", "[spi][spi_slv_hd]") +TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]") { spi_device_handle_t spi; spitest_param_set_t *cfg = &hd_conf[0]; @@ -583,4 +587,6 @@ TEST_CASE("test spi slave hd continuous mode, master too long", "[spi][spi_slv_h master_free_device_bus(spi); } -#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 +#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2 + +#endif //#if !DISABLED_FOR_TARGETS(ESP32C3) diff --git a/components/driver/test/test_timer.c b/components/driver/test/test_timer.c index 867f7bd2eb..e52569a05b 100644 --- a/components/driver/test/test_timer.c +++ b/components/driver/test/test_timer.c @@ -30,11 +30,16 @@ typedef struct { #define TIMER_INFO_INIT(TG, TID) {.timer_group = (TG), .timer_idx = (TID),} -static timer_info_t timer_info[4] = { +static timer_info_t timer_info[] = { +#if !CONFIG_IDF_TARGET_ESP32C3 TIMER_INFO_INIT(TIMER_GROUP_0, TIMER_0), TIMER_INFO_INIT(TIMER_GROUP_0, TIMER_1), TIMER_INFO_INIT(TIMER_GROUP_1, TIMER_0), TIMER_INFO_INIT(TIMER_GROUP_1, TIMER_1), +#else + TIMER_INFO_INIT(TIMER_GROUP_0, TIMER_0), + TIMER_INFO_INIT(TIMER_GROUP_1, TIMER_0), +#endif }; static intr_handle_t timer_isr_handles[SOC_TIMER_GROUP_TOTAL_TIMERS]; @@ -236,6 +241,7 @@ static void timer_intr_enable_and_start(int timer_group, int timer_idx, double a TEST_ESP_OK(timer_pause(timer_group, timer_idx)); TEST_ESP_OK(timer_set_counter_value(timer_group, timer_idx, 0x0)); TEST_ESP_OK(timer_set_alarm_value(timer_group, timer_idx, alarm_time * TIMER_SCALE)); + TEST_ESP_OK(timer_set_alarm(timer_group, timer_idx, TIMER_ALARM_EN)); TEST_ESP_OK(timer_enable_intr(timer_group, timer_idx)); TEST_ESP_OK(timer_start(timer_group, timer_idx)); } @@ -507,8 +513,8 @@ TEST_CASE("Timer divider", "[hw_timer]") .intr_type = TIMER_INTR_LEVEL }; uint64_t set_timer_val = 0; - uint64_t time_val[4]; - uint64_t comp_time_val[4]; + uint64_t time_val[TIMER_GROUP_MAX * TIMER_MAX]; + uint64_t comp_time_val[TIMER_GROUP_MAX * TIMER_MAX]; all_timer_init(&config, true); all_timer_pause(); @@ -526,7 +532,7 @@ TEST_CASE("Timer divider", "[hw_timer]") all_timer_start(); vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time all_timer_get_counter_value(set_timer_val, false, comp_time_val); - for (i = 0; i < 4; i++) { + for (i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) { TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); TEST_ASSERT_INT_WITHIN(10000, 10000000, comp_time_val[i]); } @@ -538,7 +544,7 @@ TEST_CASE("Timer divider", "[hw_timer]") all_timer_start(); vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time all_timer_get_counter_value(set_timer_val, false, comp_time_val); - for (i = 0; i < 4; i++) { + for (i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) { TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); TEST_ASSERT_INT_WITHIN(3126, 312500, comp_time_val[i]); } @@ -550,7 +556,7 @@ TEST_CASE("Timer divider", "[hw_timer]") all_timer_start(); vTaskDelay(1000 / portTICK_PERIOD_MS); all_timer_get_counter_value(set_timer_val, false, comp_time_val); - for (i = 0; i < 4; i++) { + for (i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) { TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); TEST_ASSERT_INT_WITHIN(40000, 40000000, comp_time_val[i]); } @@ -561,7 +567,7 @@ TEST_CASE("Timer divider", "[hw_timer]") all_timer_start(); vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time all_timer_get_counter_value(set_timer_val, false, comp_time_val); - for (i = 0; i < 4; i++) { + for (i = 0; i < TIMER_GROUP_MAX * TIMER_MAX; i++) { TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); TEST_ASSERT_INT_WITHIN(2, 1220, comp_time_val[i]); } @@ -604,8 +610,8 @@ TEST_CASE("Timer enable alarm", "[hw_timer]") // disable alarm of tg0_timer1 alarm_flag = false; - TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_DIS)); timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.2); + TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_DIS)); vTaskDelay(2000 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL(false, alarm_flag); @@ -618,8 +624,8 @@ TEST_CASE("Timer enable alarm", "[hw_timer]") // disable alarm of tg1_timer0 alarm_flag = false; - TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_DIS)); timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.2); + TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_DIS)); vTaskDelay(2000 / portTICK_PERIOD_MS); TEST_ASSERT_EQUAL(false, alarm_flag); all_timer_isr_unreg(); @@ -682,8 +688,13 @@ TEST_CASE("Timer auto reload", "[hw_timer]") // test disable auto_reload timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.14); timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 1.14 * TIMER_SCALE); + timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.14); + timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, 1.14 * TIMER_SCALE); //test enable auto_reload + TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_EN)); + timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.4); + timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_EN, 0); TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN)); timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.4); timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN, 0); diff --git a/components/driver/test/touch_sensor_test/test_esp32.c b/components/driver/test/touch_sensor_test/test_esp32.c index f68b5a4966..0a1d4e2796 100644 --- a/components/driver/test/touch_sensor_test/test_esp32.c +++ b/components/driver/test/touch_sensor_test/test_esp32.c @@ -13,8 +13,11 @@ // limitations under the License. /* - Tests for the touch sensor device driver + Tests for the touch sensor device driver for ESP32 */ +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 + #include "esp_system.h" #include "driver/touch_pad.h" #include "unity.h" @@ -34,8 +37,6 @@ #include "soc/rtc_io_struct.h" #include "esp_rom_sys.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2, ESP32S3) // This testcase for ESP32 - static const char *TAG = "test_touch"; #define TOUCH_READ_INVALID_VAL (0) @@ -374,4 +375,4 @@ TEST_CASE("Touch Sensor interrupt test", "[touch]") TEST_ESP_OK( test_touch_interrupt() ); } -#endif // !DISABLED_FOR_TARGETS(ESP8266, ESP32) +#endif // CONFIG_IDF_TARGET_ESP32 diff --git a/components/driver/test/touch_sensor_test/test_esp32s2.c b/components/driver/test/touch_sensor_test/test_esp32s2.c index ca02e5bd4f..787360bf76 100644 --- a/components/driver/test/touch_sensor_test/test_esp32s2.c +++ b/components/driver/test/touch_sensor_test/test_esp32s2.c @@ -13,8 +13,11 @@ // limitations under the License. /* - Tests for the touch sensor device driver + Tests for the touch sensor device driver for ESP32-S2 only */ +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32S2 + #include #include "esp_system.h" #include "driver/touch_pad.h" @@ -38,8 +41,6 @@ #include "driver/rtc_io.h" #include "esp_rom_sys.h" -#if !DISABLED_FOR_TARGETS(ESP8266, ESP32, ESP32S3) // This testcase for ESP32S2 - static const char *TAG = "test_touch"; #define PLATFORM_SELECT (1) //0: pxp; 1: chip @@ -2122,4 +2123,4 @@ void test_touch_slope_debug(int pad_num) TEST_ESP_OK( touch_pad_deinit() ); } -#endif // !DISABLED_FOR_TARGETS(ESP8266, ESP32) +#endif // CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/driver/touch_sensor_common.c b/components/driver/touch_sensor_common.c index a59ad928c8..9504fcfd58 100644 --- a/components/driver/touch_sensor_common.c +++ b/components/driver/touch_sensor_common.c @@ -20,7 +20,6 @@ #include "sys/lock.h" #include "soc/soc_pins.h" #include "freertos/FreeRTOS.h" -#include "freertos/xtensa_api.h" #include "freertos/semphr.h" #include "freertos/timers.h" #include "esp_intr_alloc.h" @@ -28,7 +27,6 @@ #include "driver/touch_pad.h" #include "driver/rtc_cntl.h" #include "driver/gpio.h" - #include "hal/touch_sensor_types.h" #include "hal/touch_sensor_hal.h" @@ -43,12 +41,12 @@ static const char *TOUCH_TAG = "TOUCH_SENSOR"; #define TOUCH_CHANNEL_CHECK(channel) do { \ TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \ } while (0); -#elif defined CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#else // !CONFIG_IDF_TARGET_ESP32 #define TOUCH_CHANNEL_CHECK(channel) do { \ TOUCH_CHECK(channel < SOC_TOUCH_SENSOR_NUM && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \ TOUCH_CHECK(channel != SOC_TOUCH_DENOISE_CHANNEL, "TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG); \ } while (0); -#endif +#endif // CONFIG_IDF_TARGET_ESP32 #define TOUCH_GET_IO_NUM(channel) (touch_sensor_channel_io_map[channel]) @@ -195,7 +193,7 @@ esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint16_t threshold) TOUCH_EXIT_CRITICAL(); return ESP_OK; } -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#else // !CONFIG_IDF_TARGET_ESP32 esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold) { TOUCH_CHANNEL_CHECK(touch_num); @@ -206,7 +204,7 @@ esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold) TOUCH_EXIT_CRITICAL(); return ESP_OK; } -#endif +#endif // CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32 esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold) @@ -215,7 +213,7 @@ esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold) touch_hal_get_threshold(touch_num, threshold); return ESP_OK; } -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#else // !CONFIG_IDF_TARGET_ESP32 esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold) { TOUCH_CHANNEL_CHECK(touch_num); @@ -224,7 +222,7 @@ esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold) touch_hal_get_threshold(touch_num, threshold); return ESP_OK; } -#endif +#endif // CONFIG_IDF_TARGET_ESP32 esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num) { diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index a0680a8b36..a2973e3f1b 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -154,7 +154,7 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) } /** - * Reset SPI CPU FIFO + * Reset SPI CPU TX FIFO * * @param hw Beginning address of the peripheral registers. */ diff --git a/components/hal/esp32c3/brownout_hal.c b/components/hal/esp32c3/brownout_hal.c index 95d77a3974..1fc22420b1 100644 --- a/components/hal/esp32c3/brownout_hal.c +++ b/components/hal/esp32c3/brownout_hal.c @@ -16,8 +16,8 @@ #include "hal/brownout_hal.h" #include "soc/rtc_cntl_struct.h" #include "soc/rtc_cntl_reg.h" -#include "i2c_rtc_clk.h" -#include "i2c_brownout.h" +#include "regi2c_ctrl.h" +#include "regi2c_brownout.h" void brownout_hal_config(const brownout_hal_config_t *cfg) diff --git a/components/hal/esp32c3/include/hal/clk_gate_ll.h b/components/hal/esp32c3/include/hal/clk_gate_ll.h index db3ce2c4b1..9a4cace824 100644 --- a/components/hal/esp32c3/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c3/include/hal/clk_gate_ll.h @@ -28,6 +28,8 @@ extern "C" { static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) { switch (periph) { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_CLK_EN; case PERIPH_RMT_MODULE: return SYSTEM_RMT_CLK_EN; case PERIPH_LEDC_MODULE: @@ -89,6 +91,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en (void)enable; // unused switch (periph) { + case PERIPH_SARADC_MODULE: + return SYSTEM_APB_SARADC_RST; case PERIPH_RMT_MODULE: return SYSTEM_RMT_RST; case PERIPH_LEDC_MODULE: diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index 38c81eca1c..4fd25d7c27 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -18,7 +18,7 @@ * See readme.md in soc/include/hal/readme.md ******************************************************************************/ -// The LL layer for ESP32-S3 GPIO register operations +// The LL layer for ESP32-C3 GPIO register operations #pragma once @@ -34,6 +34,8 @@ extern "C" { // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) +#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) /** * @brief Enable pull-up on GPIO. * @@ -133,7 +135,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) */ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) { - // hw->status1_w1tc.intr_st = mask; + // Not supported on C3 } /** @@ -146,7 +148,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num) { if (core_id == 0) { - GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr + GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr } else { // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr } @@ -193,12 +195,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num) */ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) { - if (gpio_num < 32) { - hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); - } else { - // hw->enable1_w1tc.data = (0x1 << (gpio_num - 32)); - } - + hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); // Ensure no other output signal is routed via GPIO matrix to this pin REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), SIG_GPIO_OUT_IDX); @@ -212,11 +209,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) */ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { - if (gpio_num < 32) { - hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); - } else { - // hw->enable1_w1ts.data = (0x1 << (gpio_num - 32)); - } + hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); } /** @@ -251,17 +244,9 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num) static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level) { if (level) { - if (gpio_num < 32) { - hw->out_w1ts.out_w1ts = (1 << gpio_num); - } else { - // hw->out1_w1ts.data = (1 << (gpio_num - 32)); - } + hw->out_w1ts.out_w1ts = (1 << gpio_num); } else { - if (gpio_num < 32) { - hw->out_w1tc.out_w1tc = (1 << gpio_num); - } else { - // hw->out1_w1tc.data = (1 << (gpio_num - 32)); - } + hw->out_w1tc.out_w1tc = (1 << gpio_num); } } @@ -279,11 +264,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32 */ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) { - if (gpio_num < 32) { - return (hw->in.data >> gpio_num) & 0x1; - } else { - return 0; // Less than 32 GPIOs in ESP32-C3 - } + return (hw->in.data >> gpio_num) & 0x1; } /** diff --git a/components/hal/esp32c3/include/hal/sha_ll.h b/components/hal/esp32c3/include/hal/sha_ll.h index 4cd0ad9134..a7bc493252 100644 --- a/components/hal/esp32c3/include/hal/sha_ll.h +++ b/components/hal/esp32c3/include/hal/sha_ll.h @@ -15,7 +15,6 @@ #include #include "soc/hwcrypto_reg.h" -#include "soc/dport_access.h" #include "hal/sha_types.h" #ifdef __cplusplus @@ -127,8 +126,12 @@ static inline void sha_ll_fill_text_block(const void *input_text, size_t block_w static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) { uint32_t *digest_state_words = (uint32_t *)digest_state; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < digest_word_len; i++) { + digest_state_words[i] = REG_READ(SHA_H_BASE + (i * REG_WIDTH)); + } - esp_dport_access_read_buffer(digest_state_words, SHA_H_BASE, digest_word_len); } /** diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/hal/esp32c3/include/hal/timer_ll.h index 8b31074fa3..edadee14e3 100644 --- a/components/hal/esp32c3/include/hal/timer_ll.h +++ b/components/hal/esp32c3/include/hal/timer_ll.h @@ -325,13 +325,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uin */ static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool level_int_en) { - switch (timer_num) { - case 0: - hw->int_ena.t0 = level_int_en; - break; - default: - break; - } + // Only "level" interrupts are supported on this target } /** @@ -346,15 +340,8 @@ static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t tim */ static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num) { - bool enable = false; - switch (timer_num) { - case 0: - enable = hw->int_ena.t0; - break; - default: - break; - } - return enable; + // Only "level" interrupts are supported on this target + return true; } /** diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index d2cd96b724..31a5ed108f 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -26,8 +26,6 @@ typedef enum { GPIO_PORT_MAX, } gpio_port_t; -/** @cond */ //Doxy command to hide preprocessor definitions from docs */ - #define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */ #define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */ #define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */ @@ -108,12 +106,10 @@ typedef enum { #define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG #define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG #define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG -#if CONFIG_IDF_TARGET_ESP32S2 #define GPIO_PIN_REG_28 IO_MUX_GPIO28_REG #define GPIO_PIN_REG_29 IO_MUX_GPIO29_REG #define GPIO_PIN_REG_30 IO_MUX_GPIO30_REG #define GPIO_PIN_REG_31 IO_MUX_GPIO31_REG -#endif #define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG #define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG #define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG @@ -122,7 +118,6 @@ typedef enum { #define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG #define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG #define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG -#if SOC_GPIO_PIN_COUNT > 40 #define GPIO_PIN_REG_40 IO_MUX_GPIO40_REG #define GPIO_PIN_REG_41 IO_MUX_GPIO41_REG #define GPIO_PIN_REG_42 IO_MUX_GPIO42_REG @@ -130,10 +125,8 @@ typedef enum { #define GPIO_PIN_REG_44 IO_MUX_GPIO44_REG #define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG #define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG -#endif - -/** @endcond */ +#if CONFIG_IDF_TARGET_ESP32 typedef enum { GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ @@ -158,14 +151,9 @@ typedef enum { GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ -#if SOC_GPIO_PIN_COUNT > 22 -#if CONFIG_IDF_TARGET_ESP32 GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ - GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ -#endif // CONFIG_IDF_TARGET_ESP32 - /* Note: The missing IO is because it is used inside the chip. */ GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ @@ -174,14 +162,54 @@ typedef enum { GPIO_NUM_31 = 31, /*!< GPIO31, input and output */ GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ - GPIO_NUM_34 = 34, /*!< GPIO34, input mode only(ESP32) / input and output(ESP32-S2) */ - GPIO_NUM_35 = 35, /*!< GPIO35, input mode only(ESP32) / input and output(ESP32-S2) */ - GPIO_NUM_36 = 36, /*!< GPIO36, input mode only(ESP32) / input and output(ESP32-S2) */ - GPIO_NUM_37 = 37, /*!< GPIO37, input mode only(ESP32) / input and output(ESP32-S2) */ - GPIO_NUM_38 = 38, /*!< GPIO38, input mode only(ESP32) / input and output(ESP32-S2) */ - GPIO_NUM_39 = 39, /*!< GPIO39, input mode only(ESP32) / input and output(ESP32-S2) */ -#endif // SOC_GPIO_PIN_COUNT > 22 -#if SOC_GPIO_PIN_COUNT > 40 + GPIO_NUM_34 = 34, /*!< GPIO34, input mode only */ + GPIO_NUM_35 = 35, /*!< GPIO35, input mode only */ + GPIO_NUM_36 = 36, /*!< GPIO36, input mode only */ + GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */ + GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */ + GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */ + GPIO_NUM_MAX, +/** @endcond */ +} gpio_num_t; +#elif CONFIG_IDF_TARGET_ESP32S2 +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ + GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ + GPIO_NUM_31 = 31, /*!< GPIO31, input and output */ + GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ + GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ + GPIO_NUM_34 = 34, /*!< GPIO34, input and output */ + GPIO_NUM_35 = 35, /*!< GPIO35, input and output */ + GPIO_NUM_36 = 36, /*!< GPIO36, input and output */ + GPIO_NUM_37 = 37, /*!< GPIO37, input and output */ + GPIO_NUM_38 = 38, /*!< GPIO38, input and output */ + GPIO_NUM_39 = 39, /*!< GPIO39, input and output */ GPIO_NUM_40 = 40, /*!< GPIO40, input and output */ GPIO_NUM_41 = 41, /*!< GPIO41, input and output */ GPIO_NUM_42 = 42, /*!< GPIO42, input and output */ @@ -189,10 +217,89 @@ typedef enum { GPIO_NUM_44 = 44, /*!< GPIO44, input and output */ GPIO_NUM_45 = 45, /*!< GPIO45, input and output */ GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */ -#endif // GPIO_PIN_COUNT > 40 GPIO_NUM_MAX, /** @endcond */ } gpio_num_t; +#elif CONFIG_IDF_TARGET_ESP32S3 +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ + GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ + GPIO_NUM_31 = 31, /*!< GPIO31, input and output */ + GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ + GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ + GPIO_NUM_34 = 34, /*!< GPIO34, input and output */ + GPIO_NUM_35 = 35, /*!< GPIO35, input and output */ + GPIO_NUM_36 = 36, /*!< GPIO36, input and output */ + GPIO_NUM_37 = 37, /*!< GPIO37, input and output */ + GPIO_NUM_38 = 38, /*!< GPIO38, input and output */ + GPIO_NUM_39 = 39, /*!< GPIO39, input and output */ + GPIO_NUM_40 = 40, /*!< GPIO40, input and output */ + GPIO_NUM_41 = 41, /*!< GPIO41, input and output */ + GPIO_NUM_42 = 42, /*!< GPIO42, input and output */ + GPIO_NUM_43 = 43, /*!< GPIO43, input and output */ + GPIO_NUM_44 = 44, /*!< GPIO44, input and output */ + GPIO_NUM_45 = 45, /*!< GPIO45, input and output */ + GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */ + GPIO_NUM_47 = 47, /*!< GPIO47, input and output */ + GPIO_NUM_MAX, +/** @endcond */ +} gpio_num_t; +#elif CONFIG_IDF_TARGET_ESP32C3 +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + // TODO: ESP32C3 IDF-2463 + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_MAX, +/** @endcond */ +} gpio_num_t; +#endif typedef enum { GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ diff --git a/components/hal/sha_hal.c b/components/hal/sha_hal.c index ac9323be8b..d8d9189fda 100644 --- a/components/hal/sha_hal.c +++ b/components/hal/sha_hal.c @@ -60,12 +60,20 @@ inline static size_t state_length(esp_sha_type type) case SHA2_224: case SHA2_256: return SHA256_STATE_LEN_WORDS; +#if SOC_SHA_SUPPORT_SHA384 case SHA2_384: + return SHA512_STATE_LEN_WORDS; +#endif +#if SOC_SHA_SUPPORT_SHA512 case SHA2_512: + return SHA512_STATE_LEN_WORDS; +#endif +#if SOC_SHA_SUPPORT_SHA512_T case SHA2_512224: case SHA2_512256: case SHA2_512T: return SHA512_STATE_LEN_WORDS; +#endif default: return 0; } diff --git a/components/hal/test/test_mpu.c b/components/hal/test/test_mpu.c index 9f85b9963f..8dc3abdbd7 100644 --- a/components/hal/test/test_mpu.c +++ b/components/hal/test/test_mpu.c @@ -6,6 +6,11 @@ #include "hal/mpu_hal.h" +// TODO ESP32-C3 IDF-2375 +// LL still not implemented + +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3) + volatile static int RTC_NOINIT_ATTR access = 0; static void trigger_illegal_access(void) @@ -41,3 +46,5 @@ void check_access(void) TEST_CASE_MULTIPLE_STAGES("Can set illegal access regions", "[soc][mpu]", trigger_illegal_access, check_access); + +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3) diff --git a/components/soc/esp32c3/include/soc/clkout_channel.h b/components/soc/esp32c3/include/soc/clkout_channel.h new file mode 100644 index 0000000000..c9e9a0c245 --- /dev/null +++ b/components/soc/esp32c3/include/soc/clkout_channel.h @@ -0,0 +1,26 @@ +// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_CLKOUT_CHANNEL_H +#define _SOC_CLKOUT_CHANNEL_H + +//CLKOUT channels +#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 +#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 +#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 +#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 +#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 +#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 + +#endif diff --git a/components/soc/esp32c3/include/soc/gpio_caps.h b/components/soc/esp32c3/include/soc/gpio_caps.h index ec0ff52cca..ebbc15d885 100644 --- a/components/soc/esp32c3/include/soc/gpio_caps.h +++ b/components/soc/esp32c3/include/soc/gpio_caps.h @@ -18,23 +18,21 @@ extern "C" { #endif +// ESP32-C3 has 1 GPIO peripheral #define SOC_GPIO_PORT (1) #define SOC_GPIO_PIN_COUNT (22) // Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC +// On ESP32-C3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. #define GPIO_SUPPORTS_RTC_INDEPENDENT (1) - +// Force hold is a new function of ESP32-C3 #define GPIO_SUPPORTS_FORCE_HOLD (1) -#define GPIO_PRO_CPU_INTR_ENA (BIT(0)) -#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1)) - #define GPIO_MODE_DEF_DISABLE (0) #define GPIO_MODE_DEF_INPUT (BIT0) #define GPIO_MODE_DEF_OUTPUT (BIT1) #define GPIO_MODE_DEF_OD (BIT2) -// TODO ESP32-C3 IDF-2119 - check if any IOs are not full featured GPIO #define SOC_GPIO_VALID_GPIO_MASK ((1U< #ifdef __cplusplus extern "C" { #endif diff --git a/components/soc/esp32s3/include/soc/gpio_caps.h b/components/soc/esp32s3/include/soc/gpio_caps.h index e3a5a10a61..e4cfb898c7 100644 --- a/components/soc/esp32s3/include/soc/gpio_caps.h +++ b/components/soc/esp32s3/include/soc/gpio_caps.h @@ -27,10 +27,10 @@ extern "C" { // Force hold is a new function of ESP32-S3 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// 0~47 except from 22~25, 47 are valid -#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47)) -// GPIO 46, 47 are input only -#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47)) +// 0~47 except from 22~25 are valid +#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) +// GPIO 46 is input only +#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46)) #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/i2s_caps.h b/components/soc/esp32s3/include/soc/i2s_caps.h index a0d476b1ad..cd21be8893 100644 --- a/components/soc/esp32s3/include/soc/i2s_caps.h +++ b/components/soc/esp32s3/include/soc/i2s_caps.h @@ -21,5 +21,3 @@ // ESP32-S3 have 1 I2S #define SOC_I2S_NUM (1) - -#define SOC_I2S_SUPPORT_PDM (0) // ESP32-S3 do not support PDM diff --git a/tools/ci/config/target-test.yml b/tools/ci/config/target-test.yml index dd479ae896..12df7a4822 100644 --- a/tools/ci/config/target-test.yml +++ b/tools/ci/config/target-test.yml @@ -359,7 +359,7 @@ component_ut_test_001: UT_001: extends: .unit_test_32_template - parallel: 45 + parallel: 47 tags: - ESP32_IDF - UT_T1_1 @@ -506,7 +506,7 @@ UT_034: UT_035: extends: .unit_test_s2_template - parallel: 47 + parallel: 48 tags: - ESP32S2_IDF - UT_T1_1