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modify voltage param to fit all mode of S3

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This commit is contained in:
chaijie
2022-05-20 19:29:20 +08:00
committed by Michael (XIAO Xufeng)
parent a2e1b6756e
commit 2a1002b4a4
3 changed files with 37 additions and 41 deletions
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2
components/esp_hw_support/port/esp32s3/rtc_pm.c
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@ -45,9 +45,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
switch (sleep_mode) { switch (sleep_mode) {
case PM_LIGHT_SLEEP: case PM_LIGHT_SLEEP:
cfg.wifi_pd_en = 1; cfg.wifi_pd_en = 1;
cfg.dig_dbias_wak = 4;
cfg.dig_dbias_slp = 0; cfg.dig_dbias_slp = 0;
cfg.rtc_dbias_wak = 0;
cfg.rtc_dbias_slp = 0; cfg.rtc_dbias_slp = 0;
rtc_sleep_init(cfg); rtc_sleep_init(cfg);
break; break;

68
components/esp_hw_support/port/esp32s3/rtc_sleep.c
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@ -71,46 +71,50 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
.vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0,
.xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1,
.deep_slp_reject = 1, .deep_slp_reject = 1,
.light_slp_reject = 1 .light_slp_reject = 1,
.dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT,
.rtc_dbias_slp = RTC_CNTL_DBIAS_1V10
}; };
out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
if (sleep_flags & RTC_SLEEP_PD_DIG) { if (sleep_flags & RTC_SLEEP_PD_DIG) {
assert(sleep_flags & RTC_SLEEP_PD_XTAL); assert(sleep_flags & RTC_SLEEP_PD_XTAL);
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; out_config->dig_dbias_slp = 0; //not used
//rtc voltage from high to low
//voltage from high to low
if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) {
/* /*
* Voltage for all features: * rtc voltage in sleep mode >= 1.1v
* - ADC/Temperature sensor in monitor mode (ULP) * Support all features:
* - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monotor = 0)
* - RTC IO as input * - RTC IO as input
* - RTC Memory at high temperature * - RTC Memory at high temperature
* - ULP * - ULP
* - Touch sensor * - Touch sensor
* - 8MD256 as RTC slow clock src * - 8MD256 as RTC slow clock src
*/ */
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; out_config->rtc_regulator_fpu = 1;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
} else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
//default mode, can't use ADC/Temperature sensor in monitor mode /*
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; * rtc voltage in sleep need stable and not less than 0.7v (default mode):
* can't use ADC/Temperature sensor in monitor mode
*/
out_config->rtc_regulator_fpu = 1;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
} else { } else {
//ultra low power, also can't use RTC IO as input, RTC memory can't work under high temperature /*
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power):
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; also can't use RTC IO as input, RTC memory can't work under high temperature
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; */
out_config->rtc_regulator_fpu = 0;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW;
} }
} else { } else {
out_config->rtc_regulator_fpu = 1;
//voltage from high to low //voltage from high to low
if (!(sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) {
/* /*
* Voltage for all features: * digital voltage not less than 1.1v, rtc voltage not less than 1.1v to keep system stable
* Support all features:
* - XTAL * - XTAL
* - RC 8M used by digital system * - RC 8M used by digital system
* - ADC/Temperature sensor in monitor mode (ULP) * - ADC/Temperature sensor in monitor mode (ULP)
@ -118,22 +122,17 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
* - Touch sensor * - Touch sensor
* - 8MD256 as RTC slow clock src * - 8MD256 as RTC slow clock src
*/ */
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10;
} else if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) {
//can't use XTAL, or RC 8M in digital system
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
} else { } else {
//also can't use ADC/Temperature sensor in monitor mode /*
out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; * digital voltage not less than 0.6v
* if use RTC_SLEEP_USE_ADC_TESEN_MONITOR, rtc voltage need to be >= 0.9v(default voltage), others just use default rtc voltage.
* - not support XTAL
* - not support RC 8M in digital system
*/
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
} }
} }
@ -199,9 +198,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor);
assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor);
@ -211,7 +208,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
if (cfg.deep_slp) { if (cfg.deep_slp) {
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
@ -219,12 +215,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else { } else {
REG_SET_FIELD(RTC_CNTL_REGULATOR_DRV_CTRL_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); REG_SET_FIELD(RTC_CNTL_REGULATOR_DRV_CTRL_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
} }
/* mem pd */ /* mem pd */
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
if (!cfg.int_8m_pd_en) { if (!cfg.int_8m_pd_en) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else { } else {

8
components/soc/esp32s3/include/soc/rtc.h
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@ -115,7 +115,9 @@ set sleep_init default param
*/ */
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 14
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_ON 0 #define RTC_CNTL_BIASSLP_MONITOR_ON 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1
@ -127,6 +129,7 @@ set sleep_init default param
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf
/** /**
* @brief Possible main XTAL frequency values. * @brief Possible main XTAL frequency values.
* *
@ -652,9 +655,7 @@ typedef struct {
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
@ -664,6 +665,7 @@ typedef struct {
uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep
uint32_t deep_slp_reject : 1; uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1; uint32_t light_slp_reject : 1;
} rtc_sleep_config_t; } rtc_sleep_config_t;