From 2a28ec3522434bbd6c1c6ed0ebc9dfd85ecf9a02 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Mon, 22 Nov 2021 13:45:36 +0800 Subject: [PATCH] crypto: also apply cache writeback/invalidate for SPIRAM_USE_MEMMAP Closes https://github.com/espressif/esp-idf/issues/7944 --- components/mbedtls/port/aes/dma/esp_aes.c | 18 ++++++-- components/mbedtls/port/sha/dma/sha.c | 2 +- components/mbedtls/test/test_aes.c | 41 +++++++++++-------- components/soc/esp32s2/include/soc/soc_caps.h | 1 + components/soc/esp32s3/include/soc/soc_caps.h | 1 + 5 files changed, 42 insertions(+), 21 deletions(-) diff --git a/components/mbedtls/port/aes/dma/esp_aes.c b/components/mbedtls/port/aes/dma/esp_aes.c index 063d28123c..3a9f2d4411 100644 --- a/components/mbedtls/port/aes/dma/esp_aes.c +++ b/components/mbedtls/port/aes/dma/esp_aes.c @@ -80,6 +80,18 @@ static esp_pm_lock_handle_t s_pm_sleep_lock; #endif #endif +#if SOC_PSRAM_DMA_CAPABLE + +#if (CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B) +#define DCACHE_LINE_SIZE 16 +#elif (CONFIG_ESP32S2_DATA_CACHE_LINE_32B || CONFIG_ESP32S3_DATA_CACHE_LINE_32B) +#define DCACHE_LINE_SIZE 32 +#elif CONFIG_ESP32S3_DATA_CACHE_LINE_64B +#define DCACHE_LINE_SIZE 64 +#endif //(CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B) + +#endif //SOC_PSRAM_DMA_CAPABLE + static const char *TAG = "esp-aes"; /* These are static due to: @@ -325,12 +337,12 @@ static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, if (block_bytes > 0) { /* Flush cache if input in external ram */ -#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) +#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE) if (esp_ptr_external_ram(input)) { Cache_WriteBack_Addr((uint32_t)input, len); } if (esp_ptr_external_ram(output)) { - if (((intptr_t)(output) & 0xF) != 0) { + if ((((intptr_t)(output) & (DCACHE_LINE_SIZE - 1)) != 0) || (block_bytes % DCACHE_LINE_SIZE != 0)) { // Non aligned ext-mem buffer output_needs_realloc = true; } @@ -421,7 +433,7 @@ static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, aes_hal_transform_dma_start(blocks); esp_aes_dma_wait_complete(use_intr, out_desc_tail); -#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) +#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE) if (block_bytes > 0) { if (esp_ptr_external_ram(output)) { Cache_Invalidate_Addr((uint32_t)output, block_bytes); diff --git a/components/mbedtls/port/sha/dma/sha.c b/components/mbedtls/port/sha/dma/sha.c index e774adcce2..9f390c41d5 100644 --- a/components/mbedtls/port/sha/dma/sha.c +++ b/components/mbedtls/port/sha/dma/sha.c @@ -226,7 +226,7 @@ int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, return 0; } -#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) +#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE) if (esp_ptr_external_ram(input)) { Cache_WriteBack_Addr((uint32_t)input, ilen); } diff --git a/components/mbedtls/test/test_aes.c b/components/mbedtls/test/test_aes.c index fa62cec9c3..5f63444c02 100644 --- a/components/mbedtls/test/test_aes.c +++ b/components/mbedtls/test/test_aes.c @@ -781,24 +781,22 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]") -#ifdef CONFIG_SPIRAM_USE_MALLOC - -const uint8_t expected_cipher_psram_end[] = { - 0x7e, 0xdf, 0x13, 0xf3, 0x56, 0xef, 0x67, 0x01, - 0xfc, 0x08, 0x49, 0x62, 0xfa, 0xfe, 0x0c, 0x8b, - 0x99, 0x39, 0x09, 0x51, 0x2c, 0x9a, 0xd5, 0x48, - 0x4f, 0x76, 0xa2, 0x19, 0x2c, 0x08, 0x9d, 0x6a, +const uint8_t expected_cipher_ctr_end[] = { + 0x93, 0xca, 0xe0, 0x44, 0x96, 0x6d, 0xcb, 0xb2, + 0xcf, 0x8a, 0x8d, 0x73, 0x8c, 0x6b, 0xfa, 0x4d, + 0xd6, 0xc4, 0x18, 0x49, 0xdd, 0xc6, 0xbf, 0xc2, + 0xb9, 0xf0, 0x09, 0x69, 0x45, 0x42, 0xc6, 0x05, }; -void aes_psram_ctr_test(uint32_t input_buf_caps, uint32_t output_buf_caps) +void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps) { mbedtls_aes_context ctx; uint8_t nonce[16]; uint8_t key[16]; uint8_t stream_block[16]; - size_t SZ = 6000; - size_t ALIGNMENT_SIZE_BYTES = 16; + size_t SZ = 32*200; + size_t ALIGNMENT_SIZE_BYTES = 64; memset(nonce, 0x2F, 16); memset(key, 0x1E, 16); @@ -823,7 +821,7 @@ void aes_psram_ctr_test(uint32_t input_buf_caps, uint32_t output_buf_caps) offset = 0; memset(nonce, 0x2F, 16); mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, chipertext + i); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_psram_end, chipertext + i + SZ - 32, 32); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, chipertext + i + SZ - 32, 32); // Decrypt offset = 0; @@ -841,14 +839,23 @@ void aes_psram_ctr_test(uint32_t input_buf_caps, uint32_t output_buf_caps) free(decryptedtext); } +TEST_CASE("mbedtls AES internal mem alignment tests", "[aes]") +{ + uint32_t internal_dma_caps = MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL; + aes_ctr_alignment_test(internal_dma_caps, internal_dma_caps); +} + + +#ifdef CONFIG_SPIRAM_USE_MALLOC + void aes_psram_one_buf_ctr_test(void) { mbedtls_aes_context ctx; uint8_t nonce[16]; uint8_t key[16]; uint8_t stream_block[16]; - size_t SZ = 6000; - size_t ALIGNMENT_SIZE_BYTES = 16; + size_t SZ = 32*200; + size_t ALIGNMENT_SIZE_BYTES = 32; memset(nonce, 0x2F, 16); memset(key, 0x1E, 16); @@ -870,7 +877,7 @@ void aes_psram_one_buf_ctr_test(void) memset(buf, 0x26, SZ + ALIGNMENT_SIZE_BYTES); memset(nonce, 0x2F, 16); mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, buf + i, buf + i); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_psram_end, buf + i + SZ - 32, 32); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, buf + i + SZ - 32, 32); // Decrypt offset = 0; @@ -1452,9 +1459,9 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps) /* Tests how crypto DMA handles data in external memory */ TEST_CASE("mbedtls AES PSRAM tests", "[aes]") { - aes_psram_ctr_test(MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); - aes_psram_ctr_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); - aes_psram_ctr_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); + aes_ctr_alignment_test(MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); + aes_ctr_alignment_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); + aes_ctr_alignment_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); aes_psram_one_buf_ctr_test(); } diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index ed8aa86ed6..804fbf71aa 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -54,6 +54,7 @@ #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define SOC_CACHE_SUPPORT_WRAP 1 +#define SOC_PSRAM_DMA_CAPABLE 1 /*-------------------------- ADC CAPS ----------------------------------------*/ #define SOC_ADC_PERIPH_NUM (2) diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 38c53510ee..42f834b22c 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -19,6 +19,7 @@ #define SOC_DIG_SIGN_SUPPORTED 1 #define SOC_HMAC_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define SOC_PSRAM_DMA_CAPABLE 1 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 /*-------------------------- ADC CAPS ----------------------------------------*/