Merge branch 'bugfix/fix_dac_driver_ut' into 'master'

Driver(dac): fix DAC-DMA driver and unit test

Closes IDF-1407

See merge request espressif/esp-idf!8814

components/soc/src/esp32s2/CMakeLists.txt

@@ -1,4 +1,5 @@
 set(srcs "adc_hal.c"
+        "dac_hal.c"
         "brownout_hal.c"
         "cp_dma_hal.c"
         "rtc_clk.c"

components/soc/src/esp32s2/adc_hal.c

@@ -16,7 +16,7 @@
 
 #include "hal/adc_hal.h"
 #include "hal/adc_types.h"
-#include "esp_log.h"
+
 /*---------------------------------------------------------------
                     Digital controller setting
 ---------------------------------------------------------------*/
@@ -96,6 +96,9 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
  * Enable clock and select clock source for ADC digital controller.
  * Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
  *
+ * @note ADC and DAC digital controller share the same frequency divider.
+ *       Please set a reasonable frequency division factor to meet the sampling frequency of the ADC and the output frequency of the DAC.
+ *
  * @param clk Refer to ``adc_digi_clk_t``.
  */
 void adc_hal_digi_clk_config(const adc_digi_clk_t *clk)

components/soc/src/esp32s2/dac_hal.c

@@ -0,0 +1,55 @@
+// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// The HAL layer for ADC (esp32s2 specific part)
+
+#include "hal/dac_hal.h"
+#include "hal/adc_hal.h"
+#include "hal/dac_types.h"
+
+/*---------------------------------------------------------------
+                    Digital controller setting
+---------------------------------------------------------------*/
+
+void dac_hal_digi_init(void)
+{
+    dac_ll_digi_clk_inv(true);
+}
+
+void dac_hal_digi_deinit(void)
+{
+    dac_ll_digi_trigger_output(false);
+    dac_ll_digi_enable_dma(false);
+    dac_ll_digi_fifo_reset();
+    dac_ll_digi_reset();
+}
+
+void dac_hal_digi_controller_config(const dac_digi_config_t *cfg)
+{
+    dac_ll_digi_set_convert_mode(cfg->mode);
+    dac_ll_digi_set_trigger_interval(cfg->interval);
+    adc_hal_digi_clk_config(&cfg->dig_clk);
+}
+
+void dac_hal_digi_start(void)
+{
+    dac_ll_digi_enable_dma(true);
+    dac_ll_digi_trigger_output(true);
+}
+
+void dac_hal_digi_stop(void)
+{
+    dac_ll_digi_trigger_output(false);
+    dac_ll_digi_enable_dma(false);
+}

components/soc/src/esp32s2/include/hal/adc_hal.h

@@ -66,6 +66,9 @@ void adc_hal_digi_disable(void);
  * Enable clock and select clock source for ADC digital controller.
  * Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
  *
+ * @note ADC and DAC digital controller share the same frequency divider.
+ *       Please set a reasonable frequency division factor to meet the sampling frequency of the ADC and the output frequency of the DAC.
+ *
  * @param clk Refer to ``adc_digi_clk_t``.
  */
 void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);

components/soc/src/esp32s2/include/hal/dac_hal.h

@@ -0,0 +1,76 @@
+// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The HAL layer for DAC (esp32s2 specific part)
+
+#pragma once
+
+#include "hal/dac_ll.h"
+#include "hal/dac_types.h"
+
+#include_next "hal/dac_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*---------------------------------------------------------------
+                    Digital controller setting
+---------------------------------------------------------------*/
+/**
+ * Digital controller initialization.
+ */
+void dac_hal_digi_init(void);
+
+/**
+ * Digital controller deinitialization.
+ */
+void dac_hal_digi_deinit(void);
+
+/**
+ * Setting the DAC digital controller.
+ *
+ * @param cfg Pointer to digital controller paramter.
+ */
+void dac_hal_digi_controller_config(const dac_digi_config_t *cfg);
+
+/**
+ * DAC digital controller start output voltage.
+ */
+void dac_hal_digi_start(void);
+
+/**
+ * DAC digital controller stop output voltage.
+ */
+void dac_hal_digi_stop(void);
+
+/**
+ * Reset DAC digital controller FIFO.
+ */
+#define dac_hal_digi_fifo_reset() dac_ll_digi_fifo_reset()
+
+/**
+ * Reset DAC digital controller.
+ */
+#define dac_hal_digi_reset() dac_ll_digi_reset()
+
+#ifdef __cplusplus
+}
+#endif

components/soc/src/esp32s2/include/hal/dac_ll.h

@@ -23,15 +23,16 @@
 #include <stdlib.h>
 #include "soc/dac_periph.h"
 #include "hal/dac_types.h"
+#include "soc/apb_saradc_struct.h"
+#include "soc/apb_saradc_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /*---------------------------------------------------------------
-                    RTC controller setting
+                    DAC common setting
 ---------------------------------------------------------------*/
-
 /**
  * Power on dac module and start output voltage.
  *
@@ -59,6 +60,9 @@ static inline void dac_ll_power_down(dac_channel_t channel)
     }
 }
 
+/*---------------------------------------------------------------
+                    RTC controller setting
+---------------------------------------------------------------*/
 /**
  * Output voltage with value (8 bit).
  *
@@ -204,23 +208,79 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
 /************************************/
 /*           DAC DMA API's          */
 /************************************/
+
 /**
- * Enable DAC output data from I2S DMA.
- * I2S_CLK connect to DAC_CLK, I2S_DATA_OUT connect to DAC_DATA.
+ * Enable/disable invert the DAC digital controller clock signal.
+ * 
+ * @param enable true or false.
  */
-static inline void dac_ll_dma_enable(void)
+static inline void dac_ll_digi_clk_inv(bool enable)
 {
-    SENS.sar_dac_ctrl1.dac_dig_force = 1;
-    SENS.sar_dac_ctrl1.dac_clk_inv = 1;
+    SENS.sar_dac_ctrl1.dac_clk_inv = enable;
 }
 
 /**
- * Disable DAC output data from I2S DMA.
+ * Enable/disable DAC-DMA mode for dac digital controller.
  */
-static inline void dac_ll_dma_disable(void)
+static inline void dac_ll_digi_enable_dma(bool enable)
 {
-    SENS.sar_dac_ctrl1.dac_dig_force = 0;
-    SENS.sar_dac_ctrl1.dac_clk_inv = 0;
+    SENS.sar_dac_ctrl1.dac_dig_force = enable;
+    APB_SARADC.apb_dac_ctrl.apb_dac_trans = enable;
+}
+
+/**
+ * Sets the number of interval clock cycles for the digital controller to trigger the DAC output.
+ * Expression: `dac_output_freq` = `controller_clk` / interval.
+ *
+ * @note The clocks of the DAC digital controller use the ADC digital controller clock divider.
+ *
+ * @param cycle The number of clock cycles for the trigger output interval. The unit is the divided clock.
+ */
+static inline void dac_ll_digi_set_trigger_interval(uint32_t cycle)
+{
+    APB_SARADC.apb_dac_ctrl.dac_timer_target = cycle;
+}
+
+/**
+ * Enable/disable DAC digital controller to trigger the DAC output.
+ *
+ * @param enable true or false.
+ */
+static inline void dac_ll_digi_trigger_output(bool enable)
+{
+    APB_SARADC.apb_dac_ctrl.dac_timer_en = enable;
+}
+
+/**
+ * Set DAC conversion mode for digital controller.
+ *
+ * @param mode Conversion mode select. See ``dac_digi_convert_mode_t``.
+ */
+static inline void dac_ll_digi_set_convert_mode(dac_digi_convert_mode_t mode)
+{
+    if (mode == DAC_CONV_NORMAL) {
+        APB_SARADC.apb_dac_ctrl.apb_dac_alter_mode = 0;
+    } else {
+        APB_SARADC.apb_dac_ctrl.apb_dac_alter_mode = 1;
+    }
+}
+
+/**
+ * Reset FIFO of DAC digital controller.
+ */
+static inline void dac_ll_digi_fifo_reset(void)
+{
+    APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 1;
+    APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 0;
+}
+
+/**
+ * Reset DAC digital controller.
+ */
+static inline void dac_ll_digi_reset(void)
+{
+    APB_SARADC.apb_dac_ctrl.apb_dac_rst = 1;
+    APB_SARADC.apb_dac_ctrl.apb_dac_rst = 0;
 }
 
 #ifdef __cplusplus