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feat(esp32c5): support esp32c5 g0 components

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laokaiyao
2023-12-05 15:38:55 +08:00
parent 8eee6529dd
commit 2b44d62e43
47 changed files with 5498 additions and 302 deletions
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components/hal/esp32c5/include/.gitkeep
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328
components/hal/esp32c5/include/hal/cache_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include <stdbool.h>
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// #include "soc/extmem_reg.h"
// #include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4)
#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4)
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
/**
* @brief Check if Cache auto preload is enabled or not.
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// bool enabled = false;
// if (REG_GET_BIT(EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG, EXTMEM_L1_CACHE_AUTOLOAD_ENA)) {
// enabled = true;
// }
// return enabled;
return (bool)0;
}
/**
* @brief Disable Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// (void) type;
// Cache_Disable_ICache();
}
/**
* @brief Enable Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
* @param data_autoload_en data autoload enabled or not
* @param inst_autoload_en inst autoload enabled or not
*/
__attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
* @brief Suspend Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Suspend_ICache();
}
/**
* @brief Resume Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
* @param data_autoload_en data autoload enabled or not
* @param inst_autoload_en inst autoload enabled or not
*/
__attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
* @brief Invalidate cache supported addr
*
* Invalidate a cache item
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
* @param vaddr start address of the region to be invalidated
* @param size size of the region to be invalidated
*/
__attribute__((always_inline))
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Invalidate_Addr(vaddr, size);
}
/**
* @brief Freeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
}
/**
* @brief Unfreeze Cache
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*/
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// Cache_Freeze_ICache_Disable();
}
/**
* @brief Get Cache line size, in bytes
*
* @param cache_level level of the cache
* @param type see `cache_type_t`
* @param cache_id id of the cache in this type and level
*
* @return Cache line size, in bytes
*/
__attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// uint32_t size = 0;
// size = Cache_Get_ICache_Line_Size();
// return size;
return (uint32_t)0;
}
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// cache_bus_mask_t mask = (cache_bus_mask_t)0;
// // uint32_t vaddr_end = vaddr_start + len - 1;
// if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
// //c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
// mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
// } else {
// HAL_ASSERT(0); //Out of region
// }
// // return mask;
return (cache_bus_mask_t)0;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
// // uint32_t ibus_mask = 0;
// ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
// REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
// // uint32_t dbus_mask = 0;
// dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
// REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be disabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
// // uint32_t ibus_mask = 0;
// ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
// REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
// // uint32_t dbus_mask = 0;
// dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
// REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
}
/**
* @brief Get Cache level and the ID of the vaddr
*
* @param vaddr_start virtual address start
* @param len vaddr length
* @param out_level cache level
* @param out_id cache id
*
* @return true for valid
*/
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// bool valid = false;
// uint32_t vaddr_end = vaddr_start + len - 1;
// // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
// valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
// // if (valid) {
// *out_level = 1;
// *out_id = 0;
// }
// // return valid;
return (bool)0;
}
/*------------------------------------------------------------------------------
* Interrupt
*----------------------------------------------------------------------------*/
/**
* @brief Enable Cache access error interrupt
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param mask Interrupt mask
*/
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
}
/**
* @brief Clear Cache access error interrupt status
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param mask Interrupt mask
*/
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
}
/**
* @brief Get Cache access error interrupt status
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param mask Interrupt mask
*
* @return Status mask
*/
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
// return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
return (uint32_t)0;
}
#ifdef __cplusplus
return (uint32_t)0;
}
#endif

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components/hal/esp32c5/include/hal/efuse_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "esp32p4/rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.rd_repeat_data1.wdt_delay_sel;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.rd_mac_sys_0.mac_0;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.rd_mac_sys_1.mac_1;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.rd_repeat_data2.secure_boot_en;
return (bool)0;
}
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// // return EFUSE.rd_mac_sys_5;
// return 0;
return (uint32_t)0;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return 0;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return 0;
return (bool)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return 0;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return 0;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return 0;
return (bool)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return 0;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// EFUSE.conf.cfg_ecdsa_blk = efuse_blk;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.cmd.read_cmd;
return (bool)0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// return EFUSE.cmd.pgm_cmd;
return (bool)0;
}
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// EFUSE.cmd.read_cmd = 1;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
// EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// EFUSE.wr_tim_conf2.pwr_off_num = value;
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
{
// TODO: [ESP32C5] IDF-8674 (inherit from C6)
// EFUSE.wr_tim_conf0_rs_bypass.update = 1;
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus
}
#endif

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components/hal/esp32c5/include/hal/lpwdt_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/wdt_types.h"
#include "soc/rtc_cntl_periph.h"
#include "soc/efuse_reg.h"
#include "esp_attr.h"
#include "esp_assert.h"
#include "esp32c5/rom/ets_sys.h"
/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
#define LP_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
#define LP_WDT_RESET_LENGTH_100_NS 0
#define LP_WDT_RESET_LENGTH_200_NS 1
#define LP_WDT_RESET_LENGTH_300_NS 2
#define LP_WDT_RESET_LENGTH_400_NS 3
#define LP_WDT_RESET_LENGTH_500_NS 4
#define LP_WDT_RESET_LENGTH_800_NS 5
#define LP_WDT_RESET_LENGTH_1600_NS 6
#define LP_WDT_RESET_LENGTH_3200_NS 7
#define LP_WDT_STG_SEL_OFF 0
#define LP_WDT_STG_SEL_INT 1
#define LP_WDT_STG_SEL_RESET_CPU 2
#define LP_WDT_STG_SEL_RESET_SYSTEM 3
#define LP_WDT_STG_SEL_RESET_RTC 4
//Type check wdt_stage_action_t
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
//Type check wdt_reset_sig_length_t
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
/**
* @brief Enable the RWDT
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_en = 1;
}
/**
* @brief Disable the RWDT
*
* @param hw Start address of the peripheral registers.
* @note This function does not disable the flashboot mode. Therefore, given that
* the MWDT is disabled using this function, a timeout can still occur
* if the flashboot mode is simultaneously enabled.
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_en = 0;
}
/**
* @brief Check if the RWDT is enabled
*
* @param hw Start address of the peripheral registers.
* @return True if RTC WDT is enabled
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// return (hw->config0.wdt_en) ? true : false;
return (bool)0;
}
/**
* @brief Configure a particular stage of the RWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to configure
* @param timeout Number of timer ticks for the stage to timeout (see note).
* @param behavior What action to take when the stage times out
*
* @note The value of of RWDT stage 0 timeout register is special, in
* that an implicit multiplier is applied to that value to produce
* and effective timeout tick value. The multiplier is dependent
* on an EFuse value. Therefore, when configuring stage 0, the valid
* values for the timeout argument are:
* - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
* - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
* - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
* - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
*/
FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// switch (stage) {
// case WDT_STAGE0:
// hw->config0.wdt_stg0 = behavior;
// //Account of implicty multiplier applied to stage 0 timeout tick config value
// hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
// break;
// case WDT_STAGE1:
// hw->config0.wdt_stg1 = behavior;
// hw->config2.val = timeout_ticks;
// break;
// case WDT_STAGE2:
// hw->config0.wdt_stg2 = behavior;
// hw->config3.val = timeout_ticks;
// break;
// case WDT_STAGE3:
// hw->config0.wdt_stg3 = behavior;
// hw->config4.val = timeout_ticks;
// break;
// default:
// abort();
// }
}
/**
* @brief Disable a particular stage of the RWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to disable
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// switch (stage) {
// case WDT_STAGE0:
// hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE1:
// hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE2:
// hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE3:
// hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
// break;
// default:
// abort();
// }
}
/**
* @brief Set the length of the CPU reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of CPU reset signal
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_cpu_reset_length = length;
}
/**
* @brief Set the length of the system reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of system reset signal
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_sys_reset_length = length;
}
/**
* @brief Enable/Disable the RWDT flashboot mode.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
*
* @note Flashboot mode is independent and can trigger a WDT timeout event if the
* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
* on flashboot, and should be disabled by software when flashbooting completes.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable CPU0 to be reset, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable CPU1 to be reset, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable the RWDT pause during sleep functionality
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
}
/**
* @brief Enable/Disable chip reset on RWDT timeout.
*
* A chip reset also resets the analog portion of the chip. It will appear as a
* POWERON reset rather than an RTC reset.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
}
/**
* @brief Set width of chip reset signal
*
* @param hw Start address of the peripheral registers.
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
}
/**
* @brief Feed the RWDT
*
* Resets the current timer count and current stage.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->feed.rtc_wdt_feed = 1;
}
/**
* @brief Enable write protection of the RWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->wprotect.val = 0;
}
/**
* @brief Disable write protection of the RWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->wprotect.val = LP_WDT_WKEY_VALUE;
}
/**
* @brief Enable the RWDT interrupt.
*
* @param hw Start address of the peripheral registers.
* @param enable True to enable RWDT interrupt, false to disable.
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
}
/**
* @brief Check if the RWDT interrupt has been triggered
*
* @param hw Start address of the peripheral registers.
* @return True if the RWDT interrupt was triggered
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// return (hw->int_st.lp_wdt_int_st) ? true : false;
return (bool)0;
}
/**
* @brief Clear the RWDT interrupt status.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635 (inherit from C6)
// hw->int_clr.lp_wdt_int_clr = 1;
}
#ifdef __cplusplus
}
#endif

433
components/hal/esp32c5/include/hal/mmu_ll.h Normal file
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@@ -0,0 +1,433 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/spi_mem_reg.h"
// #include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#include "hal/efuse_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Convert MMU virtual address to linear address
*
* @param vaddr virtual address
*
* @return linear address
*/
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
return (uint32_t)0;
}
/**
* Convert MMU linear address to virtual address
*
* @param laddr linear address
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
* @param target virtual address aimed physical memory target, not used
*
* @return virtual address
*/
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)target;
// (void)vaddr_type;
// //On ESP32C5, I/D share the same vaddr range
// return SOC_MMU_IBUS_VADDR_BASE | laddr;
return (uint32_t)0;
}
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// unsigned cnt = efuse_ll_get_flash_crypt_cnt();
// // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
// cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
// return (cnt == 1);
return (bool)0;
}
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
// return (page_size_code == 0) ? MMU_PAGE_64KB :
// (page_size_code == 1) ? MMU_PAGE_32KB :
// (page_size_code == 2) ? MMU_PAGE_16KB :
// MMU_PAGE_8KB;
return (mmu_page_size_t)0;
}
/**
* Set MMU page size
*
* @param size MMU page size
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 :
// (size == MMU_PAGE_32KB) ? 1 :
// (size == MMU_PAGE_16KB) ? 2 :
// (size == MMU_PAGE_8KB) ? 3 : 0;
// REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// (void)type;
// uint32_t vaddr_end = vaddr_start + len - 1;
// return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
return (bool)0;
}
/**
* Check if the paddr region is valid
*
* @param mmu_id MMU ID
* @param paddr_start start of the physical address
* @param len length, in bytes
*
* @return
* True for valid
*/
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
// (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
// ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
return (bool)0;
}
/**
* To get the MMU table entry id to be mapped
*
* @param mmu_id MMU ID
* @param vaddr virtual address to be mapped
*
* @return
* MMU table entry id
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
return (uint32_t)0;
}
/**
* Format the paddr to be mappable
*
* @param mmu_id MMU ID
* @param paddr physical address to be mapped
* @param target paddr memory target, not used
*
* @return
* mmu_val - paddr in MMU table supported format
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// (void)target;
// mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// return paddr >> shift_code;
return (uint32_t)0;
}
/**
* Write to the MMU table to map the virtual memory and the physical memory
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be set into an MMU entry, for physical address
* @param target MMU target physical memory.
*/
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// (void)target;
// uint32_t mmu_raw_value;
// if (mmu_ll_cache_encryption_enabled()) {
// mmu_val |= SOC_MMU_SENSITIVE;
// }
// // mmu_raw_value = mmu_val | SOC_MMU_VALID;
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
}
/**
* Read the raw value from MMU table
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be read from MMU table
*/
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// uint32_t mmu_raw_value;
// uint32_t ret;
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
// if (mmu_ll_cache_encryption_enabled()) {
// mmu_raw_value &= ~SOC_MMU_SENSITIVE;
// }
// if (!(mmu_raw_value & SOC_MMU_VALID)) {
// return 0;
// }
// ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
// return ret;
return (uint32_t)0;
}
/**
* Set MMU table entry as invalid
*
* @param mmu_id MMU ID
* @param entry_id MMU entry
*/
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
}
/**
* Unmap all the items in the MMU table
*
* @param mmu_id MMU ID
*/
__attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
// mmu_ll_set_entry_invalid(mmu_id, i);
// }
}
/**
* Check MMU table entry value is valid
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
*
* @return Ture for MMU entry is valid; False for invalid
*/
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
// // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
return (bool)0;
}
/**
* Get the MMU table entry target
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
*
* @return Target, see `mmu_target_t`
*/
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// return MMU_TARGET_FLASH0;
return (mmu_target_t)0;
}
/**
* Convert MMU entry ID to paddr base
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
*
* @return paddr base
*/
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
// // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
// return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
return (uint32_t)0;
}
/**
* Find the MMU table entry ID based on table map value
* @note This function can only find the first match entry ID. However it is possible that a physical address
* is mapped to multiple virtual addresses
*
* @param mmu_id MMU ID
* @param mmu_val map value to be read from MMU table standing for paddr
* @param target physical memory target, see `mmu_target_t`
*
* @return MMU entry ID, -1 for invalid
*/
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
// if (mmu_ll_check_entry_valid(mmu_id, i)) {
// if (mmu_ll_get_entry_target(mmu_id, i) == target) {
// REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
// if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
// return i;
// }
// }
// }
// }
// // return -1;
return (int)0;
}
/**
* Convert MMU entry ID to vaddr base
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
*/
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
// (void)mmu_id;
// mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
// uint32_t shift_code = 0;
// // switch (page_size) {
// case MMU_PAGE_64KB:
// shift_code = 16;
// break;
// case MMU_PAGE_32KB:
// shift_code = 15;
// break;
// case MMU_PAGE_16KB:
// shift_code = 14;
// break;
// case MMU_PAGE_8KB:
// shift_code = 13;
// break;
// default:
// HAL_ASSERT(shift_code);
// }
// uint32_t laddr = entry_id << shift_code;
// // /**
// * For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
// * Here we just pass MMU_TARGET_FLASH0 to get vaddr
// */
// return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
return (uint32_t)0;
}
#ifdef __cplusplus
return (uint32_t)0;
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Timer Group register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "soc/timer_periph.h"
#include "soc/timer_group_struct.h"
#include "soc/pcr_struct.h"
#include "hal/wdt_types.h"
#include "hal/assert.h"
#include "esp_attr.h"
#include "esp_assert.h"
#include "hal/misc.h"
/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
/* Possible values for TIMG_WDT_STGx */
#define TIMG_WDT_STG_SEL_OFF 0
#define TIMG_WDT_STG_SEL_INT 1
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
//Type check wdt_stage_action_t
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
//Type check wdt_reset_sig_length_t
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
/**
* @brief Enable the MWDT
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtconfig0.wdt_en = 1;
}
/**
* @brief Disable the MWDT
*
* @param hw Start address of the peripheral registers.
* @note This function does not disable the flashboot mode. Therefore, given that
* the MWDT is disabled using this function, a timeout can still occur
* if the flashboot mode is simultaneously enabled.
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtconfig0.wdt_en = 0;
}
/**
* Check if the MWDT is enabled
*
* @param hw Start address of the peripheral registers.
* @return True if the MWDT is enabled, false otherwise
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// return (hw->wdtconfig0.wdt_en) ? true : false;
return (bool)0;
}
/**
* @brief Configure a particular stage of the MWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to configure
* @param timeout Number of timer ticks for the stage to timeout
* @param behavior What action to take when the stage times out
*/
FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// switch (stage) {
// case WDT_STAGE0:
// hw->wdtconfig0.wdt_stg0 = behavior;
// hw->wdtconfig2.wdt_stg0_hold = timeout;
// break;
// case WDT_STAGE1:
// hw->wdtconfig0.wdt_stg1 = behavior;
// hw->wdtconfig3.wdt_stg1_hold = timeout;
// break;
// case WDT_STAGE2:
// hw->wdtconfig0.wdt_stg2 = behavior;
// hw->wdtconfig4.wdt_stg2_hold = timeout;
// break;
// case WDT_STAGE3:
// hw->wdtconfig0.wdt_stg3 = behavior;
// hw->wdtconfig5.wdt_stg3_hold = timeout;
// break;
// default:
// HAL_ASSERT(false && "unsupported WDT stage");
// break;
// }
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
* @brief Disable a particular stage of the MWDT
*
* @param hw Start address of the peripheral registers.
* @param stage Which stage to disable
*/
FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// switch (stage) {
// case WDT_STAGE0:
// hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE1:
// hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE2:
// hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE3:
// hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
// break;
// default:
// HAL_ASSERT(false && "unsupported WDT stage");
// break;
// }
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
* @brief Set the length of the CPU reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of CPU reset signal
*/
FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtconfig0.wdt_cpu_reset_length = length;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
* @brief Set the length of the system reset action
*
* @param hw Start address of the peripheral registers.
* @param length Length of system reset signal
*/
FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtconfig0.wdt_sys_reset_length = length;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
* @brief Enable/Disable the MWDT flashboot mode.
*
* @param hw Beginning address of the peripheral registers.
* @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode.
*
* @note Flashboot mode is independent and can trigger a WDT timeout event if the
* WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled
* on flashboot, and should be disabled by software when flashbooting completes.
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
* @brief Set the clock prescaler of the MWDT
*
* @param hw Start address of the peripheral registers.
* @param prescaler Prescaler value between 1 to 65535
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// // We take care of the "read-modify-write" procedure by ourselves.
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
* @brief Feed the MWDT
*
* Resets the current timer count and current stage.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtfeed.wdt_feed = 1;
}
/**
* @brief Enable write protection of the MWDT registers
*
* Locking the MWDT will prevent any of the MWDT's registers from being modified
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtwprotect.wdt_wkey = 0;
}
/**
* @brief Disable write protection of the MWDT registers
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
* @brief Clear the MWDT interrupt status.
*
* @param hw Start address of the peripheral registers.
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->int_clr_timers.wdt_int_clr = 1;
}
/**
* @brief Set the interrupt enable bit for the MWDT interrupt.
*
* @param hw Beginning address of the peripheral registers.
* @param enable Whether to enable the MWDT interrupt
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
}
/**
* @brief Set the clock source for the MWDT.
*
* @param hw Beginning address of the peripheral registers.
* @param clk_src Clock source
*/
FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// uint8_t clk_id = 0;
// switch (clk_src) {
// case MWDT_CLK_SRC_XTAL:
// clk_id = 0;
// break;
// case MWDT_CLK_SRC_PLL_F80M:
// clk_id = 1;
// break;
// case MWDT_CLK_SRC_RC_FAST:
// clk_id = 2;
// break;
// default:
// HAL_ASSERT(false);
// break;
// }
// // if (hw == &TIMERG0) {
// PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id;
// } else {
// PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id;
// }
}
/**
* @brief Enable MWDT module clock
*
* @param hw Beginning address of the peripheral registers.
* @param en true to enable, false to disable
*/
__attribute__((always_inline))
static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
{
// TODO: [ESP32C5] IDF-8650 (inherit from C6)
// if (hw == &TIMERG0) {
// PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
// } else {
// PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
// }
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for RTC(LP) watchdog register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/lpwdt_ll.h"
typedef lp_wdt_dev_t rwdt_dev_t;
#define RWDT_DEV_GET() &LP_WDT
#define rwdt_ll_enable(hw) \
lpwdt_ll_enable(hw)
#define rwdt_ll_disable(hw) \
lpwdt_ll_disable(hw)
#define rwdt_ll_check_if_enabled(hw) \
lpwdt_ll_check_if_enabled(hw)
#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \
lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior)
#define rwdt_ll_disable_stage(hw, stage) \
lpwdt_ll_disable_stage(hw, stage)
#define rwdt_ll_set_cpu_reset_length(hw, length) \
lpwdt_ll_set_cpu_reset_length(hw, length)
#define rwdt_ll_set_sys_reset_length(hw, length) \
lpwdt_ll_set_sys_reset_length(hw, length)
#define rwdt_ll_set_flashboot_en(hw, enable) \
lpwdt_ll_set_flashboot_en(hw, enable)
#define rwdt_ll_set_procpu_reset_en(hw, enable) \
lpwdt_ll_set_procpu_reset_en(hw, enable)
#define rwdt_ll_set_appcpu_reset_en(hw, enable) \
lpwdt_ll_set_appcpu_reset_en(hw, enable)
#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \
lpwdt_ll_set_pause_in_sleep_en(hw, enable)
#define rwdt_ll_set_chip_reset_en(hw, enable) \
lpwdt_ll_set_chip_reset_en(hw, enable)
#define rwdt_ll_set_chip_reset_width(hw, width) \
lpwdt_ll_set_chip_reset_width(hw, width)
#define rwdt_ll_feed(hw) \
lpwdt_ll_feed(hw)
#define rwdt_ll_write_protect_enable(hw) \
lpwdt_ll_write_protect_enable(hw)
#define rwdt_ll_write_protect_disable(hw) \
lpwdt_ll_write_protect_disable(hw)
#define rwdt_ll_set_intr_enable(hw, enable) \
lpwdt_ll_set_intr_enable(hw, enable)
#define rwdt_ll_check_intr_status(hw) \
lpwdt_ll_check_intr_status(hw)
#define rwdt_ll_clear_intr_status(hw) \
lpwdt_ll_clear_intr_status(hw)
#ifdef __cplusplus
}
#endif

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