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feat(esp32c5): support esp32c5 g0 components

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laokaiyao
2023-12-05 15:38:55 +08:00
parent 8eee6529dd
commit 2b44d62e43
47 changed files with 5498 additions and 302 deletions
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components/riscv/include/riscv/rv_utils.h
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@@ -134,6 +134,9 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
#if CONFIG_IDF_TARGET_ESP32P4
// As per CLIC specs, mintstatus CSR should be at 0xFB1, however esp32p4 implements it at 0x346
#define MINTSTATUS 0x346
#elif CONFIG_IDF_TARGET_ESP32C5
// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from P4) Check the correctness
#define MINTSTATUS 0x346
#else
#error "rv_utils_get_mintstatus() is not implemented. Check for correct mintstatus register address."
#endif /* CONFIG_IDF_TARGET_ESP32P4 */