From 2b52f7f696e61b46c3e9b5448b2fe73bc66daded Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Mon, 2 Aug 2021 17:16:30 +0800
Subject: [PATCH] mspi: fix no buffer reset before each psram read issue

In psram timing tuning driver, we rely on psram read and write functions
defined in `spi_timing_config.c`. If we don't do buffer reset (clear to
0), the function may untouch the buffer, which will keep last time value
(since we reuse the buffer). Therefore, if the first read is expected,
but next few reads didn't modify the buffer content, we will still see
the expected data.

These functions relies on `esp_rom_opiflash_exec_cmd`.
---
 .../spi_flash/esp32s3/spi_timing_config.c     | 51 ++++++++++++++-----
 1 file changed, 37 insertions(+), 14 deletions(-)

diff --git a/components/spi_flash/esp32s3/spi_timing_config.c b/components/spi_flash/esp32s3/spi_timing_config.c
index ef496e68cb..a96c294045 100644
--- a/components/spi_flash/esp32s3/spi_timing_config.c
+++ b/components/spi_flash/esp32s3/spi_timing_config.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <sys/param.h>
 #include "sdkconfig.h"
 #include "string.h"
 #include "esp_attr.h"
@@ -156,16 +157,13 @@ void IRAM_ATTR spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf,
 #endif
 }
 
-void IRAM_ATTR spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
+static void IRAM_ATTR s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
 {
-#if CONFIG_ESPTOOLPY_OCT_FLASH
-    uint32_t cmd = OPI_PSRAM_SYNC_WRITE;
-    int dummy = OCT_PSRAM_WR_DUMMY_NUM;
-
+#if CONFIG_SPIRAM_MODE_OCT
     esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
-                            cmd, 16,
+                            OPI_PSRAM_SYNC_WRITE, 16,
                             addr, 32,
-                            dummy,
+                            OCT_PSRAM_WR_DUMMY_NUM,
                             buf, 8 * len,
                             NULL, 0,
                             BIT(1),
@@ -175,16 +173,16 @@ void IRAM_ATTR spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf,
 #endif
 }
 
-void IRAM_ATTR spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, uint32_t addr, uint32_t len)
+static void IRAM_ATTR s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
 {
-#if CONFIG_ESPTOOLPY_OCT_FLASH
-    uint32_t cmd = OPI_PSRAM_SYNC_READ;
-    int dummy = OCT_PSRAM_RD_DUMMY_NUM;
-
+#if CONFIG_SPIRAM_MODE_OCT
+    for (int i = 0; i < 16; i++) {
+        REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0);
+    }
     esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
-                            cmd, 16,
+                            OPI_PSRAM_SYNC_READ, 16,
                             addr, 32,
-                            dummy,
+                            OCT_PSRAM_RD_DUMMY_NUM,
                             NULL, 0,
                             buf, 8 * len,
                             BIT(1),
@@ -194,4 +192,29 @@ void IRAM_ATTR spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t *buf, u
 #endif
 }
 
+static void IRAM_ATTR s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read)
+{
+    while (len) {
+        uint32_t length = MIN(len, 32);
+        if (is_read) {
+            s_psram_read_data(1, buf, addr, length);
+        } else {
+            s_psram_write_data(1, buf, addr, length);
+        }
+        addr += length;
+        buf += length;
+        len -= length;
+    }
+}
+
+void IRAM_ATTR spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
+{
+    s_psram_execution(spi_num, buf, addr, len, false);
+}
+
+void IRAM_ATTR spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
+{
+    s_psram_execution(spi_num, buf, addr, len, true);
+}
+
 #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING