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clk_tree: Add basic clock support for esp32h2

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- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration

Remove FPGA build for esp32h2
This commit is contained in:
Song Ruo Jing
2023-02-09 15:39:38 +08:00
parent 89190fab02
commit 2c2a62e323
53 changed files with 3504 additions and 3611 deletions
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6
components/soc/esp32c6/include/soc/clk_tree_defs.h
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@@ -115,9 +115,9 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 240MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */

6
components/soc/esp32c6/include/soc/pcr_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1699,8 +1699,8 @@ typedef union {
typedef union {
struct {
/** clk_32k_sel : R/W; bitpos: [1:0]; default: 0;
* This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and
* timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
* This field indicates which one 32KHz clock will be used by timergroup.
* 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
*/
uint32_t clk_32k_sel:2;
uint32_t reserved_2:30;

76
components/soc/esp32c6/include/soc/rtc.h
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@@ -40,8 +40,6 @@ extern "C" {
* The functions are loosely split into the following groups:
* - rtc_clk: clock switching, calibration
* - rtc_time: reading RTC counter, conversion between counter values and time
* - rtc_sleep: entry into sleep modes
* - rtc_init: initialization
*/
#define MHZ (1000000)
@@ -198,32 +196,6 @@ typedef struct {
.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
}
typedef struct {
uint16_t wifi_powerup_cycles : 7;
uint16_t wifi_wait_cycles : 9;
uint16_t bt_powerup_cycles : 7;
uint16_t bt_wait_cycles : 9;
uint16_t cpu_top_powerup_cycles : 7;
uint16_t cpu_top_wait_cycles : 9;
uint16_t dg_wrap_powerup_cycles : 7;
uint16_t dg_wrap_wait_cycles : 9;
uint16_t dg_peri_powerup_cycles : 7;
uint16_t dg_peri_wait_cycles : 9;
} rtc_init_config_t;
#define RTC_INIT_CONFIG_DEFAULT() { \
.wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
.bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.bt_wait_cycles = OTHER_BLOCKS_WAIT, \
.cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
.dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
.dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
}
/**
* Initialize clocks and set CPU frequency
*
@@ -314,9 +286,10 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
*
* - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000
* - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000
* - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
* - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000
* - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768
* - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768
*
* rtc_clk_cal function can be used to get more precise value by comparing
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
@@ -515,49 +488,6 @@ bool rtc_dig_8m_enabled(void);
uint32_t rtc_clk_freq_cal(uint32_t cal_val);
/**
* RTC power and clock control initialization settings
*/
typedef struct {
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
uint32_t cpu_waiti_clk_gate : 1;
uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise.
} rtc_config_t;
/**
* Default initializer of rtc_config_t.
*
* This initializer sets all fields to "reasonable" values (e.g. suggested for
* production use).
*/
#define RTC_CONFIG_DEFAULT() {\
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
.clkctl_init = 1, \
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1, \
.cali_ocode = 0\
}
/**
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
void rtc_init(rtc_config_t cfg);
// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
// **WARNING**: The following are only for backwards compatibility.
// Please use the declarations in soc/clk_tree_defs.h instead.

1
components/soc/esp32c6/include/soc/soc.h
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@@ -139,6 +139,7 @@
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 )
#define MODEM_APB_CLK_FREQ ( 80*1000000 )