From bd292025209cd6ba889c532962447de7e05a8199 Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Wed, 14 Aug 2019 16:07:24 +0800 Subject: [PATCH 1/3] 1. Fix backtrace is incomplete 2. Optimization code style --- .../bootloader_support/src/esp_image_format.c | 2 +- components/heap/heap_caps.c | 6 +++++- components/soc/esp32/include/soc/soc.h | 4 ++-- components/soc/esp32s2beta/include/soc/soc.h | 4 ++-- .../soc/esp32s2beta/soc_memory_layout.c | 21 ++++++++----------- components/soc/src/memory_layout_utils.c | 13 ++++++------ components/xtensa/include/esp_debug_helpers.h | 2 +- 7 files changed, 27 insertions(+), 25 deletions(-) diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index a4375a6540..2eca06942d 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -350,7 +350,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme /* Before loading segment, check it doesn't clobber bootloader RAM. */ if (do_load) { const intptr_t load_end = load_addr + data_len; - if (load_end <= (intptr_t) SOC_DIRAM_DRAM_HIGH) { + if (load_end < (intptr_t) SOC_DRAM_HIGH) { /* Writing to DRAM */ intptr_t sp = (intptr_t)get_sp(); if (load_end > sp - STACK_LOAD_HEADROOM) { diff --git a/components/heap/heap_caps.c b/components/heap/heap_caps.c index 9c7d91a2ee..4323a2389e 100644 --- a/components/heap/heap_caps.c +++ b/components/heap/heap_caps.c @@ -39,12 +39,16 @@ possible. This should optimize the amount of RAM accessible to the code without IRAM_ATTR static void *dram_alloc_to_iram_addr(void *addr, size_t len) { uintptr_t dstart = (uintptr_t)addr; //First word - uintptr_t dend = dstart + len - 4; //Last word + uintptr_t dend = dstart + len; //Last word + 4 assert(esp_ptr_in_diram_dram((void *)dstart)); assert(esp_ptr_in_diram_dram((void *)dend)); assert((dstart & 3) == 0); assert((dend & 3) == 0); +#if CONFIG_IDF_TARGET_ESP32 uint32_t istart = SOC_DIRAM_IRAM_LOW + (SOC_DIRAM_DRAM_HIGH - dend); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + uint32_t istart = SOC_DIRAM_IRAM_LOW + (dstart - SOC_DIRAM_DRAM_LOW); +#endif uint32_t *iptr = (uint32_t *)istart; *iptr = dstart; return iptr + 1; diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index c751072ca2..603408795b 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -258,9 +258,9 @@ //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x400A0000 -#define SOC_DIRAM_IRAM_HIGH 0x400BFFFC +#define SOC_DIRAM_IRAM_HIGH 0x400C0000 #define SOC_DIRAM_DRAM_LOW 0x3FFE0000 -#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC +#define SOC_DIRAM_DRAM_HIGH 0x40000000 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FFAE000 diff --git a/components/soc/esp32s2beta/include/soc/soc.h b/components/soc/esp32s2beta/include/soc/soc.h index 86cd83e3d2..80e68aacc3 100644 --- a/components/soc/esp32s2beta/include/soc/soc.h +++ b/components/soc/esp32s2beta/include/soc/soc.h @@ -201,9 +201,9 @@ //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40020000 -#define SOC_DIRAM_IRAM_HIGH 0x4006FFFC +#define SOC_DIRAM_IRAM_HIGH 0x40070000 #define SOC_DIRAM_DRAM_LOW 0x3FFB0000 -#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC +#define SOC_DIRAM_DRAM_HIGH 0x40000000 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FFB0000 diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c index 390794f453..9c9bc7e801 100644 --- a/components/soc/esp32s2beta/soc_memory_layout.c +++ b/components/soc/esp32s2beta/soc_memory_layout.c @@ -75,21 +75,21 @@ const soc_memory_region_t soc_memory_regions[] = { #endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB #if CONFIG_ESP32S2_DATA_CACHE_0KB - { 0x3FFB2000, 0x2000, 0, 0x400B2000}, //Block 1, can be use as I/D cache memory - { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB2000, 0x2000, 0, 0x40022000}, //Block 1, can be use as I/D cache memory + { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #elif CONFIG_ESP32S2_DATA_CACHE_8KB - { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #else - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #endif #else #if CONFIG_ESP32S2_DATA_CACHE_0KB - { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #elif CONFIG_ESP32S2_DATA_CACHE_8KB - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #endif #endif { 0x3FFB8000, 0x4000, 0, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory @@ -121,9 +121,6 @@ extern int _data_start_xtos; These are removed from the soc_memory_regions array when heaps are created. */ -// DRAM counterpart of the of the region reserved for IRAM in the linker script -SOC_RESERVE_MEMORY_REGION(0x3ffb8000, 0x3FFD0000, dram_mapped_to_iram); - //ROM data region SOC_RESERVE_MEMORY_REGION(0x3fff8000, (intptr_t)&_data_start_xtos, rom_data_region); diff --git a/components/soc/src/memory_layout_utils.c b/components/soc/src/memory_layout_utils.c index 29f752b9da..cc3b91046f 100644 --- a/components/soc/src/memory_layout_utils.c +++ b/components/soc/src/memory_layout_utils.c @@ -127,13 +127,14 @@ size_t soc_get_available_memory_regions(soc_memory_region_t *regions) bool move_to_next = true; for (size_t i = 0; i < num_reserved; i++) { - if (reserved[i].end <= in_start) { - /* reserved region ends before 'in' starts */ - continue; + if (reserved[i].start >= SOC_DRAM_HIGH && in_end < SOC_DRAM_HIGH && in.iram_address != 0) { + reserved[i].start = reserved[i].start - (in.iram_address - in.start); + reserved[i].end = reserved[i].end - (in.iram_address - in.start); } - else if (reserved[i].start >= in_end) { - /* reserved region starts after 'in' ends */ - break; + + if (reserved[i].end <= in_start || reserved[i].start >= in_end) { + /* reserved region ends before 'in' starts or reserved region starts after 'in' ends */ + continue; } else if (reserved[i].start <= in_start && reserved[i].end >= in_end) { /* reserved covers all of 'in' */ diff --git a/components/xtensa/include/esp_debug_helpers.h b/components/xtensa/include/esp_debug_helpers.h index ad2681de29..d088ddeef1 100644 --- a/components/xtensa/include/esp_debug_helpers.h +++ b/components/xtensa/include/esp_debug_helpers.h @@ -22,6 +22,7 @@ extern "C" { #include #include "esp_err.h" +#include "soc/soc.h" #define ESP_WATCHPOINT_LOAD 0x40000000 #define ESP_WATCHPOINT_STORE 0x80000000 @@ -126,7 +127,6 @@ bool esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame); */ esp_err_t esp_backtrace_print(int depth); - #endif #ifdef __cplusplus } From c057c141eb84031f60d0b31169e6068a8d8225ad Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Thu, 5 Sep 2019 19:00:14 +0800 Subject: [PATCH 2/3] Fix bug for reserved memory regions 1. Release 16KB memory of reserved regions to heap 2. Modify the dram_seg address of bootloader to 0x3FFF8000, size is 16K --- .../bootloader/subproject/main/ld/esp32s2beta/bootloader.ld | 4 ++-- components/soc/esp32s2beta/soc_memory_layout.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld index c2861a4ff7..4f0655a250 100644 --- a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld @@ -16,8 +16,8 @@ MEMORY /* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */ iram_loader_seg (RWX) : org = 0x40022000, len = 0x2000 /* 8KB, APP CPU cache */ iram_seg (RWX) : org = 0x40024000, len = 0x4000 /* 16KB, IRAM */ - /* 12k at the end of DRAM, after ROM bootloader stack */ - dram_seg (RW) : org = 0x3FFF5000, len = 0x3000 + /* 16k at the end of DRAM, after ROM bootloader stack */ + dram_seg (RW) : org = 0x3FFF8000, len = 0x4000 } /* Default entry point: */ diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c index 9c9bc7e801..38df52df0d 100644 --- a/components/soc/esp32s2beta/soc_memory_layout.c +++ b/components/soc/esp32s2beta/soc_memory_layout.c @@ -122,7 +122,7 @@ extern int _data_start_xtos; These are removed from the soc_memory_regions array when heaps are created. */ //ROM data region -SOC_RESERVE_MEMORY_REGION(0x3fff8000, (intptr_t)&_data_start_xtos, rom_data_region); +SOC_RESERVE_MEMORY_REGION(0x3fffc000, (intptr_t)&_data_start_xtos, rom_data_region); // TODO: soc_memory_layout: handle trace memory regions - IDF-750 From 4ef4b29c744b3c02ffb0cad52631d23dbba60c1e Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Fri, 6 Sep 2019 11:15:53 +0800 Subject: [PATCH 3/3] Reorganize the memory to maximize contiguous DRAM 1. Fix bug for variable sdkconfig_header in CMakeLists.txt 2. Modify the load address of bootloader 3. Modify the load address of application program --- .../main/ld/esp32s2beta/bootloader.ld | 7 ++- components/esp32s2beta/CMakeLists.txt | 1 + components/esp32s2beta/ld/esp32s2beta.ld | 44 +++++++++++++------ 3 files changed, 35 insertions(+), 17 deletions(-) diff --git a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld index 4f0655a250..b211cad613 100644 --- a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld @@ -13,10 +13,9 @@ MEMORY { /* I/O */ dport0_seg (RW) : org = 0x3FF00000, len = 0x10 - /* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */ - iram_loader_seg (RWX) : org = 0x40022000, len = 0x2000 /* 8KB, APP CPU cache */ - iram_seg (RWX) : org = 0x40024000, len = 0x4000 /* 16KB, IRAM */ - /* 16k at the end of DRAM, after ROM bootloader stack */ + iram_loader_seg (RWX) : org = 0x40062000, len = 0x2000 /* 8KB, IRAM */ + iram_seg (RWX) : org = 0x40064000, len = 0x4000 /* 16KB, IRAM */ + /* 16k at the end of DRAM, before ROM data & stack */ dram_seg (RW) : org = 0x3FFF8000, len = 0x4000 } diff --git a/components/esp32s2beta/CMakeLists.txt b/components/esp32s2beta/CMakeLists.txt index 3855be6c99..12ef46b38b 100644 --- a/components/esp32s2beta/CMakeLists.txt +++ b/components/esp32s2beta/CMakeLists.txt @@ -1,4 +1,5 @@ idf_build_get_property(target IDF_TARGET) +idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER) if(NOT "${target}" STREQUAL "esp32s2beta") return() endif() diff --git a/components/esp32s2beta/ld/esp32s2beta.ld b/components/esp32s2beta/ld/esp32s2beta.ld index 2ddb072bc7..e69b47e19f 100644 --- a/components/esp32s2beta/ld/esp32s2beta.ld +++ b/components/esp32s2beta/ld/esp32s2beta.ld @@ -1,4 +1,4 @@ -/* ESP32 Linker Script Memory Layout +/* ESP32S2Beta Linker Script Memory Layout This file describes the memory layout (memory blocks) as virtual memory addresses. @@ -16,19 +16,42 @@ */ #include "sdkconfig.h" -/* If BT is not built at all */ -#ifndef CONFIG_BT_RESERVE_DRAM -#define CONFIG_BT_RESERVE_DRAM 0 + +#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB +#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000 +#else +#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000 #endif +#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB +#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0 +#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB +#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000 +#else +#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000 +#endif + +#define RAM_IRAM_START 0x40020000 +#define RAM_DRAM_START 0x3FFB0000 +#define DATA_RAM_END 0x3FFF2000 /* start address of bootloader */ + +#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE) +#define IRAM_SIZE 0x18000 + +#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + + CONFIG_ESP32S2_DATA_CACHE_SIZE \ + + IRAM_SIZE) +#define DRAM_SIZE DATA_RAM_END - DRAM_ORG + MEMORY { /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but are connected to the data port of the CPU and eg allow bytewise access. */ - /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_0_seg (RX) : org = 0x40028000, len = 0x18000 + /* IRAM for CPU.*/ + iram0_0_seg (RX) : org = IRAM_ORG, len = IRAM_SIZE /* Even though the segment name is iram, it is actually mapped to flash */ @@ -41,17 +64,12 @@ MEMORY */ - /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. + /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. - - Note: Length of this section *should* be 0x50000, and this extra DRAM is available - in heap at runtime. However due to static ROM memory usage at this 176KB mark, the - additional static memory temporarily cannot be used. */ - dram0_0_seg (RW) : org = 0x3FFD0000 + CONFIG_BT_RESERVE_DRAM, - len = 0x28000 - CONFIG_BT_RESERVE_DRAM + dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE /* Flash mapped constant data */ drom0_0_seg (R) : org = 0x3F000018, len = 0x3f0000-0x18